1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/cpu.h> 146 #include <machine/platform.h> 147 #include <machine/frame.h> 148 #include <machine/md_var.h> 149 #include <machine/psl.h> 150 #include <machine/bat.h> 151 #include <machine/pte.h> 152 #include <machine/sr.h> 153 #include <machine/trap.h> 154 #include <machine/mmuvar.h> 155 156 #include "mmu_if.h" 157 158 #define MOEA_DEBUG 159 160 #define TODO panic("%s: not implemented", __func__); 161 162 static __inline u_int32_t 163 cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167 } 168 169 static __inline uint64_t 170 va_to_vsid(pmap_t pm, vm_offset_t va) 171 { 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173 } 174 175 #define PTESYNC() __asm __volatile("ptesync"); 176 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 177 #define SYNC() __asm __volatile("sync"); 178 #define EIEIO() __asm __volatile("eieio"); 179 180 /* 181 * The tlbie instruction must be executed in 64-bit mode 182 * so we have to twiddle MSR[SF] around every invocation. 183 * Just to add to the fun, exceptions must be off as well 184 * so that we can't trap in 64-bit mode. What a pain. 185 */ 186 struct mtx tlbie_mutex; 187 188 static __inline void 189 TLBIE(pmap_t pmap, vm_offset_t va) { 190 uint64_t vpn; 191 register_t vpn_hi, vpn_lo; 192 register_t msr; 193 register_t scratch; 194 195 vpn = (uint64_t)(va & ADDR_PIDX); 196 if (pmap != NULL) 197 vpn |= (va_to_vsid(pmap,va) << 28); 198 vpn &= ~(0xffffULL << 48); 199 200 vpn_hi = (uint32_t)(vpn >> 32); 201 vpn_lo = (uint32_t)vpn; 202 203 mtx_lock_spin(&tlbie_mutex); 204 __asm __volatile("\ 205 mfmsr %0; \ 206 mr %1, %0; \ 207 insrdi %1,%5,1,0; \ 208 mtmsrd %1; \ 209 ptesync; \ 210 \ 211 sld %1,%2,%4; \ 212 or %1,%1,%3; \ 213 tlbie %1; \ 214 \ 215 mtmsrd %0; \ 216 eieio; \ 217 tlbsync; \ 218 ptesync;" 219 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1) 220 : "memory"); 221 mtx_unlock_spin(&tlbie_mutex); 222 } 223 224 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 225 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 226 227 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 228 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 229 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 230 231 #define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ 232 #define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ 233 #define PVO_WIRED 0x010UL /* PVO entry is wired */ 234 #define PVO_MANAGED 0x020UL /* PVO entry is managed */ 235 #define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during 236 bootstrap */ 237 #define PVO_FAKE 0x100UL /* fictitious phys page */ 238 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 239 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 240 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 241 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 242 #define PVO_PTEGIDX_CLR(pvo) \ 243 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 244 #define PVO_PTEGIDX_SET(pvo, i) \ 245 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 246 247 #define MOEA_PVO_CHECK(pvo) 248 249 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 250 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 251 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 252 253 struct ofw_map { 254 vm_offset_t om_va; 255 vm_size_t om_len; 256 vm_offset_t om_pa_hi; 257 vm_offset_t om_pa_lo; 258 u_int om_mode; 259 }; 260 261 /* 262 * Map of physical memory regions. 263 */ 264 static struct mem_region *regions; 265 static struct mem_region *pregions; 266 extern u_int phys_avail_count; 267 extern int regions_sz, pregions_sz; 268 extern int ofw_real_mode; 269 270 extern struct pmap ofw_pmap; 271 272 extern void bs_remap_earlyboot(void); 273 274 275 /* 276 * Lock for the pteg and pvo tables. 277 */ 278 struct mtx moea64_table_mutex; 279 280 /* 281 * PTEG data. 282 */ 283 static struct lpteg *moea64_pteg_table; 284 u_int moea64_pteg_count; 285 u_int moea64_pteg_mask; 286 287 /* 288 * PVO data. 289 */ 290 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 291 /* lists of unmanaged pages */ 292 struct pvo_head moea64_pvo_kunmanaged = 293 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 294 struct pvo_head moea64_pvo_unmanaged = 295 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 296 297 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 298 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 299 300 vm_offset_t pvo_allocator_start; 301 vm_offset_t pvo_allocator_end; 302 303 #define BPVO_POOL_SIZE 327680 304 static struct pvo_entry *moea64_bpvo_pool; 305 static int moea64_bpvo_pool_index = 0; 306 307 #define VSID_NBPW (sizeof(u_int32_t) * 8) 308 static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 309 310 static boolean_t moea64_initialized = FALSE; 311 312 /* 313 * Statistics. 314 */ 315 u_int moea64_pte_valid = 0; 316 u_int moea64_pte_overflow = 0; 317 u_int moea64_pvo_entries = 0; 318 u_int moea64_pvo_enter_calls = 0; 319 u_int moea64_pvo_remove_calls = 0; 320 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 321 &moea64_pte_valid, 0, ""); 322 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 323 &moea64_pte_overflow, 0, ""); 324 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 325 &moea64_pvo_entries, 0, ""); 326 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 327 &moea64_pvo_enter_calls, 0, ""); 328 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 329 &moea64_pvo_remove_calls, 0, ""); 330 331 vm_offset_t moea64_scratchpage_va[2]; 332 struct pvo_entry *moea64_scratchpage_pvo[2]; 333 struct lpte *moea64_scratchpage_pte[2]; 334 struct mtx moea64_scratchpage_mtx; 335 336 /* 337 * Allocate physical memory for use in moea64_bootstrap. 338 */ 339 static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 340 341 /* 342 * PTE calls. 343 */ 344 static int moea64_pte_insert(u_int, struct lpte *); 345 346 /* 347 * PVO calls. 348 */ 349 static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 350 vm_offset_t, vm_offset_t, uint64_t, int); 351 static void moea64_pvo_remove(struct pvo_entry *, int); 352 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 353 static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 354 355 /* 356 * Utility routines. 357 */ 358 static void moea64_bridge_bootstrap(mmu_t mmup, 359 vm_offset_t kernelstart, vm_offset_t kernelend); 360 static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 361 static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 362 vm_prot_t, boolean_t); 363 static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 364 static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *); 365 static void moea64_kremove(mmu_t, vm_offset_t); 366 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 367 vm_offset_t pa, vm_size_t sz); 368 static void tlbia(void); 369 370 /* 371 * Kernel MMU interface 372 */ 373 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 374 void moea64_clear_modify(mmu_t, vm_page_t); 375 void moea64_clear_reference(mmu_t, vm_page_t); 376 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 377 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 378 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 379 vm_prot_t); 380 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 381 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 382 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 383 void moea64_init(mmu_t); 384 boolean_t moea64_is_modified(mmu_t, vm_page_t); 385 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 386 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 387 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 388 int moea64_page_wired_mappings(mmu_t, vm_page_t); 389 void moea64_pinit(mmu_t, pmap_t); 390 void moea64_pinit0(mmu_t, pmap_t); 391 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 392 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 393 void moea64_qremove(mmu_t, vm_offset_t, int); 394 void moea64_release(mmu_t, pmap_t); 395 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 396 void moea64_remove_all(mmu_t, vm_page_t); 397 void moea64_remove_write(mmu_t, vm_page_t); 398 void moea64_zero_page(mmu_t, vm_page_t); 399 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 400 void moea64_zero_page_idle(mmu_t, vm_page_t); 401 void moea64_activate(mmu_t, struct thread *); 402 void moea64_deactivate(mmu_t, struct thread *); 403 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 404 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 405 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 406 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 407 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 408 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 409 410 static mmu_method_t moea64_bridge_methods[] = { 411 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 412 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 413 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 414 MMUMETHOD(mmu_copy_page, moea64_copy_page), 415 MMUMETHOD(mmu_enter, moea64_enter), 416 MMUMETHOD(mmu_enter_object, moea64_enter_object), 417 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 418 MMUMETHOD(mmu_extract, moea64_extract), 419 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 420 MMUMETHOD(mmu_init, moea64_init), 421 MMUMETHOD(mmu_is_modified, moea64_is_modified), 422 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 423 MMUMETHOD(mmu_map, moea64_map), 424 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 425 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 426 MMUMETHOD(mmu_pinit, moea64_pinit), 427 MMUMETHOD(mmu_pinit0, moea64_pinit0), 428 MMUMETHOD(mmu_protect, moea64_protect), 429 MMUMETHOD(mmu_qenter, moea64_qenter), 430 MMUMETHOD(mmu_qremove, moea64_qremove), 431 MMUMETHOD(mmu_release, moea64_release), 432 MMUMETHOD(mmu_remove, moea64_remove), 433 MMUMETHOD(mmu_remove_all, moea64_remove_all), 434 MMUMETHOD(mmu_remove_write, moea64_remove_write), 435 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 436 MMUMETHOD(mmu_zero_page, moea64_zero_page), 437 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 438 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 439 MMUMETHOD(mmu_activate, moea64_activate), 440 MMUMETHOD(mmu_deactivate, moea64_deactivate), 441 442 /* Internal interfaces */ 443 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 444 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 445 MMUMETHOD(mmu_mapdev, moea64_mapdev), 446 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 447 MMUMETHOD(mmu_kextract, moea64_kextract), 448 MMUMETHOD(mmu_kenter, moea64_kenter), 449 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 450 451 { 0, 0 } 452 }; 453 454 static mmu_def_t oea64_bridge_mmu = { 455 MMU_TYPE_G5, 456 moea64_bridge_methods, 457 0 458 }; 459 MMU_DEF(oea64_bridge_mmu); 460 461 static __inline u_int 462 va_to_pteg(uint64_t vsid, vm_offset_t addr) 463 { 464 u_int hash; 465 466 hash = vsid ^ (((uint64_t)addr & ADDR_PIDX) >> 467 ADDR_PIDX_SHFT); 468 return (hash & moea64_pteg_mask); 469 } 470 471 static __inline struct pvo_head * 472 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 473 { 474 struct vm_page *pg; 475 476 pg = PHYS_TO_VM_PAGE(pa); 477 478 if (pg_p != NULL) 479 *pg_p = pg; 480 481 if (pg == NULL) 482 return (&moea64_pvo_unmanaged); 483 484 return (&pg->md.mdpg_pvoh); 485 } 486 487 static __inline struct pvo_head * 488 vm_page_to_pvoh(vm_page_t m) 489 { 490 491 return (&m->md.mdpg_pvoh); 492 } 493 494 static __inline void 495 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 496 { 497 498 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 499 m->md.mdpg_attrs &= ~ptebit; 500 } 501 502 static __inline u_int64_t 503 moea64_attr_fetch(vm_page_t m) 504 { 505 506 return (m->md.mdpg_attrs); 507 } 508 509 static __inline void 510 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 511 { 512 513 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 514 m->md.mdpg_attrs |= ptebit; 515 } 516 517 static __inline void 518 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 519 uint64_t pte_lo) 520 { 521 ASSERT_TABLE_LOCK(); 522 523 /* 524 * Construct a PTE. Default to IMB initially. Valid bit only gets 525 * set when the real pte is set in memory. 526 * 527 * Note: Don't set the valid bit for correct operation of tlb update. 528 */ 529 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 530 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 531 532 pt->pte_lo = pte_lo; 533 } 534 535 static __inline void 536 moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 537 { 538 539 ASSERT_TABLE_LOCK(); 540 541 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 542 } 543 544 static __inline void 545 moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 546 { 547 ASSERT_TABLE_LOCK(); 548 549 /* 550 * As shown in Section 7.6.3.2.3 551 */ 552 pt->pte_lo &= ~ptebit; 553 TLBIE(pmap,va); 554 } 555 556 static __inline void 557 moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 558 { 559 560 ASSERT_TABLE_LOCK(); 561 pvo_pt->pte_hi |= LPTE_VALID; 562 563 /* 564 * Update the PTE as defined in section 7.6.3.1. 565 * Note that the REF/CHG bits are from pvo_pt and thus should have 566 * been saved so this routine can restore them (if desired). 567 */ 568 pt->pte_lo = pvo_pt->pte_lo; 569 EIEIO(); 570 pt->pte_hi = pvo_pt->pte_hi; 571 PTESYNC(); 572 moea64_pte_valid++; 573 } 574 575 static __inline void 576 moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 577 { 578 ASSERT_TABLE_LOCK(); 579 pvo_pt->pte_hi &= ~LPTE_VALID; 580 581 /* 582 * Force the reg & chg bits back into the PTEs. 583 */ 584 SYNC(); 585 586 /* 587 * Invalidate the pte. 588 */ 589 pt->pte_hi &= ~LPTE_VALID; 590 TLBIE(pmap,va); 591 592 /* 593 * Save the reg & chg bits. 594 */ 595 moea64_pte_synch(pt, pvo_pt); 596 moea64_pte_valid--; 597 } 598 599 static __inline void 600 moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 601 { 602 603 /* 604 * Invalidate the PTE 605 */ 606 moea64_pte_unset(pt, pvo_pt, pmap, va); 607 moea64_pte_set(pt, pvo_pt); 608 if (pmap == kernel_pmap) 609 isync(); 610 } 611 612 static __inline uint64_t 613 moea64_calc_wimg(vm_offset_t pa) 614 { 615 uint64_t pte_lo; 616 int i; 617 618 /* 619 * Assume the page is cache inhibited and access is guarded unless 620 * it's in our available memory array. 621 */ 622 pte_lo = LPTE_I | LPTE_G; 623 for (i = 0; i < pregions_sz; i++) { 624 if ((pa >= pregions[i].mr_start) && 625 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 626 pte_lo &= ~(LPTE_I | LPTE_G); 627 pte_lo |= LPTE_M; 628 break; 629 } 630 } 631 632 return pte_lo; 633 } 634 635 /* 636 * Quick sort callout for comparing memory regions. 637 */ 638 static int mr_cmp(const void *a, const void *b); 639 static int om_cmp(const void *a, const void *b); 640 641 static int 642 mr_cmp(const void *a, const void *b) 643 { 644 const struct mem_region *regiona; 645 const struct mem_region *regionb; 646 647 regiona = a; 648 regionb = b; 649 if (regiona->mr_start < regionb->mr_start) 650 return (-1); 651 else if (regiona->mr_start > regionb->mr_start) 652 return (1); 653 else 654 return (0); 655 } 656 657 static int 658 om_cmp(const void *a, const void *b) 659 { 660 const struct ofw_map *mapa; 661 const struct ofw_map *mapb; 662 663 mapa = a; 664 mapb = b; 665 if (mapa->om_pa_hi < mapb->om_pa_hi) 666 return (-1); 667 else if (mapa->om_pa_hi > mapb->om_pa_hi) 668 return (1); 669 else if (mapa->om_pa_lo < mapb->om_pa_lo) 670 return (-1); 671 else if (mapa->om_pa_lo > mapb->om_pa_lo) 672 return (1); 673 else 674 return (0); 675 } 676 677 static void 678 moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 679 { 680 int i = 0; 681 682 /* 683 * Initialize segment registers and MMU 684 */ 685 686 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 687 for (i = 0; i < 16; i++) { 688 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 689 } 690 __asm __volatile ("ptesync; mtsdr1 %0; isync" 691 :: "r"((u_int)moea64_pteg_table 692 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 693 tlbia(); 694 } 695 696 static void 697 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 698 { 699 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 700 register_t msr; 701 vm_offset_t off; 702 int i, ofw_mappings; 703 704 bzero(translations, sz); 705 if (OF_getprop(mmu, "translations", translations, sz) == -1) 706 panic("moea64_bootstrap: can't get ofw translations"); 707 708 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 709 sz /= sizeof(*translations); 710 qsort(translations, sz, sizeof (*translations), om_cmp); 711 712 for (i = 0, ofw_mappings = 0; i < sz; i++) { 713 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 714 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 715 translations[i].om_len); 716 717 if (translations[i].om_pa_lo % PAGE_SIZE) 718 panic("OFW translation not page-aligned!"); 719 720 if (translations[i].om_pa_hi) 721 panic("OFW translations above 32-bit boundary!"); 722 723 /* Now enter the pages for this mapping */ 724 725 /* 726 * Lock the ofw pmap. pmap_kenter(), which we use for the 727 * pages the kernel also needs, does its own locking. 728 */ 729 PMAP_LOCK(&ofw_pmap); 730 DISABLE_TRANS(msr); 731 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 732 struct vm_page m; 733 734 /* Map low memory mappings into the kernel pmap, too. 735 * These are typically mappings made by the loader, 736 * so we need them if we want to keep executing. */ 737 738 if (translations[i].om_va + off < SEGMENT_LENGTH) 739 moea64_kenter(mmup, translations[i].om_va + off, 740 translations[i].om_va + off); 741 742 m.phys_addr = translations[i].om_pa_lo + off; 743 moea64_enter_locked(&ofw_pmap, 744 translations[i].om_va + off, &m, VM_PROT_ALL, 1); 745 746 ofw_mappings++; 747 } 748 ENABLE_TRANS(msr); 749 PMAP_UNLOCK(&ofw_pmap); 750 } 751 } 752 753 static void 754 moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 755 { 756 ihandle_t mmui; 757 phandle_t chosen; 758 phandle_t mmu; 759 size_t sz; 760 int i, j; 761 vm_size_t size, physsz, hwphyssz; 762 vm_offset_t pa, va, off; 763 register_t msr; 764 void *dpcpu; 765 766 /* We don't have a direct map since there is no BAT */ 767 hw_direct_map = 0; 768 769 /* Make sure battable is zero, since we have no BAT */ 770 for (i = 0; i < 16; i++) { 771 battable[i].batu = 0; 772 battable[i].batl = 0; 773 } 774 775 /* Get physical memory regions from firmware */ 776 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 777 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 778 779 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 780 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 781 panic("moea64_bootstrap: phys_avail too small"); 782 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 783 phys_avail_count = 0; 784 physsz = 0; 785 hwphyssz = 0; 786 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 787 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 788 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 789 regions[i].mr_start + regions[i].mr_size, 790 regions[i].mr_size); 791 if (hwphyssz != 0 && 792 (physsz + regions[i].mr_size) >= hwphyssz) { 793 if (physsz < hwphyssz) { 794 phys_avail[j] = regions[i].mr_start; 795 phys_avail[j + 1] = regions[i].mr_start + 796 hwphyssz - physsz; 797 physsz = hwphyssz; 798 phys_avail_count++; 799 } 800 break; 801 } 802 phys_avail[j] = regions[i].mr_start; 803 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 804 phys_avail_count++; 805 physsz += regions[i].mr_size; 806 } 807 physmem = btoc(physsz); 808 809 /* 810 * Allocate PTEG table. 811 */ 812 #ifdef PTEGCOUNT 813 moea64_pteg_count = PTEGCOUNT; 814 #else 815 moea64_pteg_count = 0x1000; 816 817 while (moea64_pteg_count < physmem) 818 moea64_pteg_count <<= 1; 819 #endif /* PTEGCOUNT */ 820 821 size = moea64_pteg_count * sizeof(struct lpteg); 822 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 823 moea64_pteg_count, size); 824 825 /* 826 * We now need to allocate memory. This memory, to be allocated, 827 * has to reside in a page table. The page table we are about to 828 * allocate. We don't have BAT. So drop to data real mode for a minute 829 * as a measure of last resort. We do this a couple times. 830 */ 831 832 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 833 DISABLE_TRANS(msr); 834 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 835 ENABLE_TRANS(msr); 836 837 moea64_pteg_mask = moea64_pteg_count - 1; 838 839 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 840 841 /* 842 * Allocate pv/overflow lists. 843 */ 844 size = sizeof(struct pvo_head) * moea64_pteg_count; 845 846 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 847 PAGE_SIZE); 848 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 849 850 DISABLE_TRANS(msr); 851 for (i = 0; i < moea64_pteg_count; i++) 852 LIST_INIT(&moea64_pvo_table[i]); 853 ENABLE_TRANS(msr); 854 855 /* 856 * Initialize the lock that synchronizes access to the pteg and pvo 857 * tables. 858 */ 859 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 860 MTX_RECURSE); 861 862 /* 863 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU. 864 */ 865 mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN); 866 867 /* 868 * Initialise the unmanaged pvo pool. 869 */ 870 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 871 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 872 moea64_bpvo_pool_index = 0; 873 874 /* 875 * Make sure kernel vsid is allocated as well as VSID 0. 876 */ 877 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 878 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 879 moea64_vsid_bitmap[0] |= 1; 880 881 /* 882 * Initialize the kernel pmap (which is statically allocated). 883 */ 884 for (i = 0; i < 16; i++) 885 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 886 887 kernel_pmap->pmap_phys = kernel_pmap; 888 kernel_pmap->pm_active = ~0; 889 890 PMAP_LOCK_INIT(kernel_pmap); 891 892 /* 893 * Now map in all the other buffers we allocated earlier 894 */ 895 896 DISABLE_TRANS(msr); 897 size = moea64_pteg_count * sizeof(struct lpteg); 898 off = (vm_offset_t)(moea64_pteg_table); 899 for (pa = off; pa < off + size; pa += PAGE_SIZE) 900 moea64_kenter(mmup, pa, pa); 901 size = sizeof(struct pvo_head) * moea64_pteg_count; 902 off = (vm_offset_t)(moea64_pvo_table); 903 for (pa = off; pa < off + size; pa += PAGE_SIZE) 904 moea64_kenter(mmup, pa, pa); 905 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 906 off = (vm_offset_t)(moea64_bpvo_pool); 907 for (pa = off; pa < off + size; pa += PAGE_SIZE) 908 moea64_kenter(mmup, pa, pa); 909 910 /* 911 * Map certain important things, like ourselves. 912 * 913 * NOTE: We do not map the exception vector space. That code is 914 * used only in real mode, and leaving it unmapped allows us to 915 * catch NULL pointer deferences, instead of making NULL a valid 916 * address. 917 */ 918 919 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 920 moea64_kenter(mmup, pa, pa); 921 ENABLE_TRANS(msr); 922 923 if (!ofw_real_mode) { 924 /* 925 * Set up the Open Firmware pmap and add its mappings. 926 */ 927 928 moea64_pinit(mmup, &ofw_pmap); 929 ofw_pmap.pm_sr[KERNEL_SR] = kernel_pmap->pm_sr[KERNEL_SR]; 930 ofw_pmap.pm_sr[KERNEL2_SR] = kernel_pmap->pm_sr[KERNEL2_SR]; 931 932 if ((chosen = OF_finddevice("/chosen")) == -1) 933 panic("moea64_bootstrap: can't find /chosen"); 934 OF_getprop(chosen, "mmu", &mmui, 4); 935 if ((mmu = OF_instance_to_package(mmui)) == -1) 936 panic("moea64_bootstrap: can't get mmu package"); 937 if ((sz = OF_getproplen(mmu, "translations")) == -1) 938 panic("moea64_bootstrap: can't get ofw translation count"); 939 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 940 panic("moea64_bootstrap: too many ofw translations"); 941 942 moea64_add_ofw_mappings(mmup, mmu, sz); 943 } 944 945 #ifdef SMP 946 TLBSYNC(); 947 #endif 948 949 /* 950 * Calculate the last available physical address. 951 */ 952 for (i = 0; phys_avail[i + 2] != 0; i += 2) 953 ; 954 Maxmem = powerpc_btop(phys_avail[i + 1]); 955 956 /* 957 * Initialize MMU and remap early physical mappings 958 */ 959 moea64_bridge_cpu_bootstrap(mmup,0); 960 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 961 pmap_bootstrapped++; 962 bs_remap_earlyboot(); 963 964 /* 965 * Set the start and end of kva. 966 */ 967 virtual_avail = VM_MIN_KERNEL_ADDRESS; 968 virtual_end = VM_MAX_KERNEL_ADDRESS; 969 970 /* 971 * Allocate some stupid buffer regions. 972 */ 973 974 pvo_allocator_start = virtual_avail; 975 virtual_avail += SEGMENT_LENGTH/4; 976 pvo_allocator_end = virtual_avail; 977 978 /* 979 * Allocate some things for page zeroing 980 */ 981 982 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 983 for (i = 0; i < 2; i++) { 984 moea64_scratchpage_va[i] = virtual_avail; 985 virtual_avail += PAGE_SIZE; 986 987 moea64_kenter(mmup,moea64_scratchpage_va[i],kernelstart); 988 989 LOCK_TABLE(); 990 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(kernel_pmap, 991 moea64_scratchpage_va[i],&j); 992 moea64_scratchpage_pte[i] = moea64_pvo_to_pte( 993 moea64_scratchpage_pvo[i],j); 994 UNLOCK_TABLE(); 995 } 996 997 /* 998 * Allocate a kernel stack with a guard page for thread0 and map it 999 * into the kernel page map. 1000 */ 1001 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1002 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1003 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1004 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1005 thread0.td_kstack = va; 1006 thread0.td_kstack_pages = KSTACK_PAGES; 1007 for (i = 0; i < KSTACK_PAGES; i++) { 1008 moea64_kenter(mmup, va, pa); 1009 pa += PAGE_SIZE; 1010 va += PAGE_SIZE; 1011 } 1012 1013 /* 1014 * Allocate virtual address space for the message buffer. 1015 */ 1016 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1017 msgbufp = (struct msgbuf *)virtual_avail; 1018 va = virtual_avail; 1019 virtual_avail += round_page(MSGBUF_SIZE); 1020 while (va < virtual_avail) { 1021 moea64_kenter(mmup, va, pa); 1022 pa += PAGE_SIZE; 1023 va += PAGE_SIZE; 1024 } 1025 1026 /* 1027 * Allocate virtual address space for the dynamic percpu area. 1028 */ 1029 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1030 dpcpu = (void *)virtual_avail; 1031 va = virtual_avail; 1032 virtual_avail += DPCPU_SIZE; 1033 while (va < virtual_avail) { 1034 moea64_kenter(mmup, va, pa); 1035 pa += PAGE_SIZE; 1036 va += PAGE_SIZE; 1037 } 1038 dpcpu_init(dpcpu, 0); 1039 } 1040 1041 /* 1042 * Activate a user pmap. The pmap must be activated before it's address 1043 * space can be accessed in any way. 1044 */ 1045 void 1046 moea64_activate(mmu_t mmu, struct thread *td) 1047 { 1048 pmap_t pm, pmr; 1049 1050 /* 1051 * Load all the data we need up front to encourage the compiler to 1052 * not issue any loads while we have interrupts disabled below. 1053 */ 1054 pm = &td->td_proc->p_vmspace->vm_pmap; 1055 pmr = pm->pmap_phys; 1056 1057 pm->pm_active |= PCPU_GET(cpumask); 1058 PCPU_SET(curpmap, pmr); 1059 } 1060 1061 void 1062 moea64_deactivate(mmu_t mmu, struct thread *td) 1063 { 1064 pmap_t pm; 1065 1066 pm = &td->td_proc->p_vmspace->vm_pmap; 1067 pm->pm_active &= ~(PCPU_GET(cpumask)); 1068 PCPU_SET(curpmap, NULL); 1069 } 1070 1071 void 1072 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1073 { 1074 struct pvo_entry *pvo; 1075 1076 PMAP_LOCK(pm); 1077 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1078 1079 if (pvo != NULL) { 1080 if (wired) { 1081 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1082 pm->pm_stats.wired_count++; 1083 pvo->pvo_vaddr |= PVO_WIRED; 1084 } else { 1085 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1086 pm->pm_stats.wired_count--; 1087 pvo->pvo_vaddr &= ~PVO_WIRED; 1088 } 1089 } 1090 PMAP_UNLOCK(pm); 1091 } 1092 1093 /* 1094 * Zero a page of physical memory by temporarily mapping it into the tlb. 1095 */ 1096 void 1097 moea64_zero_page(mmu_t mmu, vm_page_t m) 1098 { 1099 moea64_zero_page_area(mmu,m,0,PAGE_SIZE); 1100 } 1101 1102 /* 1103 * This goes through and sets the physical address of our 1104 * special scratch PTE to the PA we want to zero or copy. Because 1105 * of locking issues (this can get called in pvo_enter() by 1106 * the UMA allocator), we can't use most other utility functions here 1107 */ 1108 1109 static __inline 1110 void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1111 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1112 (~LPTE_WIMG & ~LPTE_RPGN); 1113 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1114 moea64_calc_wimg(pa) | (uint64_t)pa; 1115 1116 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1117 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1118 1119 moea64_scratchpage_pte[which]->pte_lo = 1120 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo; 1121 EIEIO(); 1122 1123 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1124 PTESYNC(); isync(); 1125 } 1126 1127 void 1128 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1129 { 1130 vm_offset_t dst; 1131 vm_offset_t src; 1132 1133 dst = VM_PAGE_TO_PHYS(mdst); 1134 src = VM_PAGE_TO_PHYS(msrc); 1135 1136 mtx_lock(&moea64_scratchpage_mtx); 1137 1138 moea64_set_scratchpage_pa(0,src); 1139 moea64_set_scratchpage_pa(1,dst); 1140 1141 kcopy((void *)moea64_scratchpage_va[0], 1142 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1143 1144 mtx_unlock(&moea64_scratchpage_mtx); 1145 } 1146 1147 void 1148 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1149 { 1150 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1151 1152 if (!moea64_initialized) 1153 panic("moea64_zero_page: can't zero pa %#x", pa); 1154 if (size + off > PAGE_SIZE) 1155 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1156 1157 mtx_lock(&moea64_scratchpage_mtx); 1158 1159 moea64_set_scratchpage_pa(0,pa); 1160 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1161 mtx_unlock(&moea64_scratchpage_mtx); 1162 } 1163 1164 void 1165 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1166 { 1167 1168 moea64_zero_page(mmu, m); 1169 } 1170 1171 /* 1172 * Map the given physical page at the specified virtual address in the 1173 * target pmap with the protection requested. If specified the page 1174 * will be wired down. 1175 */ 1176 void 1177 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1178 vm_prot_t prot, boolean_t wired) 1179 { 1180 1181 vm_page_lock_queues(); 1182 PMAP_LOCK(pmap); 1183 moea64_enter_locked(pmap, va, m, prot, wired); 1184 vm_page_unlock_queues(); 1185 PMAP_UNLOCK(pmap); 1186 } 1187 1188 /* 1189 * Map the given physical page at the specified virtual address in the 1190 * target pmap with the protection requested. If specified the page 1191 * will be wired down. 1192 * 1193 * The page queues and pmap must be locked. 1194 */ 1195 1196 static void 1197 moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1198 boolean_t wired) 1199 { 1200 struct pvo_head *pvo_head; 1201 uma_zone_t zone; 1202 vm_page_t pg; 1203 uint64_t pte_lo; 1204 u_int pvo_flags; 1205 int error; 1206 1207 if (!moea64_initialized) { 1208 pvo_head = &moea64_pvo_kunmanaged; 1209 pg = NULL; 1210 zone = moea64_upvo_zone; 1211 pvo_flags = 0; 1212 } else { 1213 pvo_head = vm_page_to_pvoh(m); 1214 pg = m; 1215 zone = moea64_mpvo_zone; 1216 pvo_flags = PVO_MANAGED; 1217 } 1218 1219 if (pmap_bootstrapped) 1220 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1221 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1222 1223 /* XXX change the pvo head for fake pages */ 1224 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1225 pvo_flags &= ~PVO_MANAGED; 1226 pvo_head = &moea64_pvo_kunmanaged; 1227 zone = moea64_upvo_zone; 1228 } 1229 1230 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1231 1232 if (prot & VM_PROT_WRITE) { 1233 pte_lo |= LPTE_BW; 1234 if (pmap_bootstrapped) 1235 vm_page_flag_set(m, PG_WRITEABLE); 1236 } else 1237 pte_lo |= LPTE_BR; 1238 1239 if (prot & VM_PROT_EXECUTE) 1240 pvo_flags |= VM_PROT_EXECUTE; 1241 1242 if (wired) 1243 pvo_flags |= PVO_WIRED; 1244 1245 if ((m->flags & PG_FICTITIOUS) != 0) 1246 pvo_flags |= PVO_FAKE; 1247 1248 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1249 pte_lo, pvo_flags); 1250 1251 /* 1252 * Flush the page from the instruction cache if this page is 1253 * mapped executable and cacheable. 1254 */ 1255 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1256 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1257 } 1258 } 1259 1260 static void 1261 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1262 { 1263 1264 /* 1265 * This is much trickier than on older systems because 1266 * we can't sync the icache on physical addresses directly 1267 * without a direct map. Instead we check a couple of cases 1268 * where the memory is already mapped in and, failing that, 1269 * use the same trick we use for page zeroing to create 1270 * a temporary mapping for this physical address. 1271 */ 1272 1273 if (!pmap_bootstrapped) { 1274 /* 1275 * If PMAP is not bootstrapped, we are likely to be 1276 * in real mode. 1277 */ 1278 __syncicache((void *)pa, sz); 1279 } else if (pmap == kernel_pmap) { 1280 __syncicache((void *)va, sz); 1281 } else { 1282 /* Use the scratch page to set up a temp mapping */ 1283 1284 mtx_lock(&moea64_scratchpage_mtx); 1285 1286 moea64_set_scratchpage_pa(1,pa & ~ADDR_POFF); 1287 __syncicache((void *)(moea64_scratchpage_va[1] + 1288 (va & ADDR_POFF)), sz); 1289 1290 mtx_unlock(&moea64_scratchpage_mtx); 1291 } 1292 } 1293 1294 /* 1295 * Maps a sequence of resident pages belonging to the same object. 1296 * The sequence begins with the given page m_start. This page is 1297 * mapped at the given virtual address start. Each subsequent page is 1298 * mapped at a virtual address that is offset from start by the same 1299 * amount as the page is offset from m_start within the object. The 1300 * last page in the sequence is the page with the largest offset from 1301 * m_start that can be mapped at a virtual address less than the given 1302 * virtual address end. Not every virtual page between start and end 1303 * is mapped; only those for which a resident page exists with the 1304 * corresponding offset from m_start are mapped. 1305 */ 1306 void 1307 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1308 vm_page_t m_start, vm_prot_t prot) 1309 { 1310 vm_page_t m; 1311 vm_pindex_t diff, psize; 1312 1313 psize = atop(end - start); 1314 m = m_start; 1315 PMAP_LOCK(pm); 1316 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1317 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1318 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1319 m = TAILQ_NEXT(m, listq); 1320 } 1321 PMAP_UNLOCK(pm); 1322 } 1323 1324 void 1325 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1326 vm_prot_t prot) 1327 { 1328 PMAP_LOCK(pm); 1329 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1330 FALSE); 1331 PMAP_UNLOCK(pm); 1332 1333 } 1334 1335 vm_paddr_t 1336 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1337 { 1338 struct pvo_entry *pvo; 1339 vm_paddr_t pa; 1340 1341 PMAP_LOCK(pm); 1342 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1343 if (pvo == NULL) 1344 pa = 0; 1345 else 1346 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1347 PMAP_UNLOCK(pm); 1348 return (pa); 1349 } 1350 1351 /* 1352 * Atomically extract and hold the physical page with the given 1353 * pmap and virtual address pair if that mapping permits the given 1354 * protection. 1355 */ 1356 vm_page_t 1357 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1358 { 1359 struct pvo_entry *pvo; 1360 vm_page_t m; 1361 1362 m = NULL; 1363 vm_page_lock_queues(); 1364 PMAP_LOCK(pmap); 1365 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1366 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1367 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1368 (prot & VM_PROT_WRITE) == 0)) { 1369 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1370 vm_page_hold(m); 1371 } 1372 vm_page_unlock_queues(); 1373 PMAP_UNLOCK(pmap); 1374 return (m); 1375 } 1376 1377 static void * 1378 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1379 { 1380 /* 1381 * This entire routine is a horrible hack to avoid bothering kmem 1382 * for new KVA addresses. Because this can get called from inside 1383 * kmem allocation routines, calling kmem for a new address here 1384 * can lead to multiply locking non-recursive mutexes. 1385 */ 1386 static vm_pindex_t color; 1387 vm_offset_t va; 1388 1389 vm_page_t m; 1390 int pflags, needed_lock; 1391 1392 *flags = UMA_SLAB_PRIV; 1393 needed_lock = !PMAP_LOCKED(kernel_pmap); 1394 1395 if (needed_lock) 1396 PMAP_LOCK(kernel_pmap); 1397 1398 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1399 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1400 else 1401 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1402 if (wait & M_ZERO) 1403 pflags |= VM_ALLOC_ZERO; 1404 1405 for (;;) { 1406 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1407 if (m == NULL) { 1408 if (wait & M_NOWAIT) 1409 return (NULL); 1410 VM_WAIT; 1411 } else 1412 break; 1413 } 1414 1415 va = pvo_allocator_start; 1416 pvo_allocator_start += PAGE_SIZE; 1417 1418 if (pvo_allocator_start >= pvo_allocator_end) 1419 panic("Ran out of PVO allocator buffer space!"); 1420 1421 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1422 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1423 PVO_WIRED | PVO_BOOTSTRAP); 1424 1425 if (needed_lock) 1426 PMAP_UNLOCK(kernel_pmap); 1427 1428 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1429 bzero((void *)va, PAGE_SIZE); 1430 1431 return (void *)va; 1432 } 1433 1434 void 1435 moea64_init(mmu_t mmu) 1436 { 1437 1438 CTR0(KTR_PMAP, "moea64_init"); 1439 1440 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1441 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1442 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1443 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1444 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1445 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1446 1447 if (!hw_direct_map) { 1448 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1449 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1450 } 1451 1452 moea64_initialized = TRUE; 1453 } 1454 1455 boolean_t 1456 moea64_is_modified(mmu_t mmu, vm_page_t m) 1457 { 1458 1459 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1460 return (FALSE); 1461 1462 return (moea64_query_bit(m, LPTE_CHG)); 1463 } 1464 1465 void 1466 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1467 { 1468 1469 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1470 return; 1471 moea64_clear_bit(m, LPTE_REF, NULL); 1472 } 1473 1474 void 1475 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1476 { 1477 1478 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1479 return; 1480 moea64_clear_bit(m, LPTE_CHG, NULL); 1481 } 1482 1483 /* 1484 * Clear the write and modified bits in each of the given page's mappings. 1485 */ 1486 void 1487 moea64_remove_write(mmu_t mmu, vm_page_t m) 1488 { 1489 struct pvo_entry *pvo; 1490 struct lpte *pt; 1491 pmap_t pmap; 1492 uint64_t lo; 1493 1494 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1495 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1496 (m->flags & PG_WRITEABLE) == 0) 1497 return; 1498 lo = moea64_attr_fetch(m); 1499 SYNC(); 1500 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1501 pmap = pvo->pvo_pmap; 1502 PMAP_LOCK(pmap); 1503 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1504 LOCK_TABLE(); 1505 pt = moea64_pvo_to_pte(pvo, -1); 1506 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1507 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1508 if (pt != NULL) { 1509 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1510 lo |= pvo->pvo_pte.lpte.pte_lo; 1511 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1512 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1513 pvo->pvo_pmap, PVO_VADDR(pvo)); 1514 } 1515 UNLOCK_TABLE(); 1516 } 1517 PMAP_UNLOCK(pmap); 1518 } 1519 if ((lo & LPTE_CHG) != 0) { 1520 moea64_attr_clear(m, LPTE_CHG); 1521 vm_page_dirty(m); 1522 } 1523 vm_page_flag_clear(m, PG_WRITEABLE); 1524 } 1525 1526 /* 1527 * moea64_ts_referenced: 1528 * 1529 * Return a count of reference bits for a page, clearing those bits. 1530 * It is not necessary for every reference bit to be cleared, but it 1531 * is necessary that 0 only be returned when there are truly no 1532 * reference bits set. 1533 * 1534 * XXX: The exact number of bits to check and clear is a matter that 1535 * should be tested and standardized at some point in the future for 1536 * optimal aging of shared pages. 1537 */ 1538 boolean_t 1539 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1540 { 1541 int count; 1542 1543 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1544 return (0); 1545 1546 count = moea64_clear_bit(m, LPTE_REF, NULL); 1547 1548 return (count); 1549 } 1550 1551 /* 1552 * Map a wired page into kernel virtual address space. 1553 */ 1554 void 1555 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1556 { 1557 uint64_t pte_lo; 1558 int error; 1559 1560 if (!pmap_bootstrapped) { 1561 if (va >= VM_MIN_KERNEL_ADDRESS && va < VM_MAX_KERNEL_ADDRESS) 1562 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1563 } 1564 1565 pte_lo = moea64_calc_wimg(pa); 1566 1567 PMAP_LOCK(kernel_pmap); 1568 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1569 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1570 PVO_WIRED | VM_PROT_EXECUTE); 1571 1572 if (error != 0 && error != ENOENT) 1573 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1574 pa, error); 1575 1576 /* 1577 * Flush the memory from the instruction cache. 1578 */ 1579 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1580 __syncicache((void *)va, PAGE_SIZE); 1581 } 1582 PMAP_UNLOCK(kernel_pmap); 1583 } 1584 1585 /* 1586 * Extract the physical page address associated with the given kernel virtual 1587 * address. 1588 */ 1589 vm_offset_t 1590 moea64_kextract(mmu_t mmu, vm_offset_t va) 1591 { 1592 struct pvo_entry *pvo; 1593 vm_paddr_t pa; 1594 1595 PMAP_LOCK(kernel_pmap); 1596 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1597 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1598 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1599 PMAP_UNLOCK(kernel_pmap); 1600 return (pa); 1601 } 1602 1603 /* 1604 * Remove a wired page from kernel virtual address space. 1605 */ 1606 void 1607 moea64_kremove(mmu_t mmu, vm_offset_t va) 1608 { 1609 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1610 } 1611 1612 /* 1613 * Map a range of physical addresses into kernel virtual address space. 1614 * 1615 * The value passed in *virt is a suggested virtual address for the mapping. 1616 * Architectures which can support a direct-mapped physical to virtual region 1617 * can return the appropriate address within that region, leaving '*virt' 1618 * unchanged. We cannot and therefore do not; *virt is updated with the 1619 * first usable address after the mapped region. 1620 */ 1621 vm_offset_t 1622 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1623 vm_offset_t pa_end, int prot) 1624 { 1625 vm_offset_t sva, va; 1626 1627 sva = *virt; 1628 va = sva; 1629 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1630 moea64_kenter(mmu, va, pa_start); 1631 *virt = va; 1632 1633 return (sva); 1634 } 1635 1636 /* 1637 * Returns true if the pmap's pv is one of the first 1638 * 16 pvs linked to from this page. This count may 1639 * be changed upwards or downwards in the future; it 1640 * is only necessary that true be returned for a small 1641 * subset of pmaps for proper page aging. 1642 */ 1643 boolean_t 1644 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1645 { 1646 int loops; 1647 struct pvo_entry *pvo; 1648 1649 if (!moea64_initialized || (m->flags & PG_FICTITIOUS)) 1650 return FALSE; 1651 1652 loops = 0; 1653 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1654 if (pvo->pvo_pmap == pmap) 1655 return (TRUE); 1656 if (++loops >= 16) 1657 break; 1658 } 1659 1660 return (FALSE); 1661 } 1662 1663 /* 1664 * Return the number of managed mappings to the given physical page 1665 * that are wired. 1666 */ 1667 int 1668 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1669 { 1670 struct pvo_entry *pvo; 1671 int count; 1672 1673 count = 0; 1674 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0) 1675 return (count); 1676 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1677 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1678 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1679 count++; 1680 return (count); 1681 } 1682 1683 static u_int moea64_vsidcontext; 1684 1685 void 1686 moea64_pinit(mmu_t mmu, pmap_t pmap) 1687 { 1688 int i, mask; 1689 u_int entropy; 1690 1691 PMAP_LOCK_INIT(pmap); 1692 1693 entropy = 0; 1694 __asm __volatile("mftb %0" : "=r"(entropy)); 1695 1696 if (pmap_bootstrapped) 1697 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1698 else 1699 pmap->pmap_phys = pmap; 1700 1701 /* 1702 * Allocate some segment registers for this pmap. 1703 */ 1704 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1705 u_int hash, n; 1706 1707 /* 1708 * Create a new value by mutiplying by a prime and adding in 1709 * entropy from the timebase register. This is to make the 1710 * VSID more random so that the PT hash function collides 1711 * less often. (Note that the prime casues gcc to do shifts 1712 * instead of a multiply.) 1713 */ 1714 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1715 hash = moea64_vsidcontext & (NPMAPS - 1); 1716 if (hash == 0) /* 0 is special, avoid it */ 1717 continue; 1718 n = hash >> 5; 1719 mask = 1 << (hash & (VSID_NBPW - 1)); 1720 hash = (moea64_vsidcontext & 0xfffff); 1721 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1722 /* anything free in this bucket? */ 1723 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1724 entropy = (moea64_vsidcontext >> 20); 1725 continue; 1726 } 1727 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1728 mask = 1 << i; 1729 hash &= 0xfffff & ~(VSID_NBPW - 1); 1730 hash |= i; 1731 } 1732 moea64_vsid_bitmap[n] |= mask; 1733 for (i = 0; i < 16; i++) { 1734 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1735 } 1736 return; 1737 } 1738 1739 panic("moea64_pinit: out of segments"); 1740 } 1741 1742 /* 1743 * Initialize the pmap associated with process 0. 1744 */ 1745 void 1746 moea64_pinit0(mmu_t mmu, pmap_t pm) 1747 { 1748 moea64_pinit(mmu, pm); 1749 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1750 } 1751 1752 /* 1753 * Set the physical protection on the specified range of this map as requested. 1754 */ 1755 void 1756 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1757 vm_prot_t prot) 1758 { 1759 struct pvo_entry *pvo; 1760 struct lpte *pt; 1761 int pteidx; 1762 1763 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1764 eva, prot); 1765 1766 1767 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1768 ("moea64_protect: non current pmap")); 1769 1770 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1771 moea64_remove(mmu, pm, sva, eva); 1772 return; 1773 } 1774 1775 vm_page_lock_queues(); 1776 PMAP_LOCK(pm); 1777 for (; sva < eva; sva += PAGE_SIZE) { 1778 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1779 if (pvo == NULL) 1780 continue; 1781 1782 /* 1783 * Grab the PTE pointer before we diddle with the cached PTE 1784 * copy. 1785 */ 1786 LOCK_TABLE(); 1787 pt = moea64_pvo_to_pte(pvo, pteidx); 1788 1789 /* 1790 * Change the protection of the page. 1791 */ 1792 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1793 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1794 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1795 if ((prot & VM_PROT_EXECUTE) == 0) 1796 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1797 1798 /* 1799 * If the PVO is in the page table, update that pte as well. 1800 */ 1801 if (pt != NULL) { 1802 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1803 pvo->pvo_pmap, PVO_VADDR(pvo)); 1804 if ((pvo->pvo_pte.lpte.pte_lo & 1805 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1806 moea64_syncicache(pm, sva, 1807 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1808 PAGE_SIZE); 1809 } 1810 } 1811 UNLOCK_TABLE(); 1812 } 1813 vm_page_unlock_queues(); 1814 PMAP_UNLOCK(pm); 1815 } 1816 1817 /* 1818 * Map a list of wired pages into kernel virtual address space. This is 1819 * intended for temporary mappings which do not need page modification or 1820 * references recorded. Existing mappings in the region are overwritten. 1821 */ 1822 void 1823 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1824 { 1825 while (count-- > 0) { 1826 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1827 va += PAGE_SIZE; 1828 m++; 1829 } 1830 } 1831 1832 /* 1833 * Remove page mappings from kernel virtual address space. Intended for 1834 * temporary mappings entered by moea64_qenter. 1835 */ 1836 void 1837 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1838 { 1839 while (count-- > 0) { 1840 moea64_kremove(mmu, va); 1841 va += PAGE_SIZE; 1842 } 1843 } 1844 1845 void 1846 moea64_release(mmu_t mmu, pmap_t pmap) 1847 { 1848 int idx, mask; 1849 1850 /* 1851 * Free segment register's VSID 1852 */ 1853 if (pmap->pm_sr[0] == 0) 1854 panic("moea64_release"); 1855 1856 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1857 mask = 1 << (idx % VSID_NBPW); 1858 idx /= VSID_NBPW; 1859 moea64_vsid_bitmap[idx] &= ~mask; 1860 PMAP_LOCK_DESTROY(pmap); 1861 } 1862 1863 /* 1864 * Remove the given range of addresses from the specified map. 1865 */ 1866 void 1867 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1868 { 1869 struct pvo_entry *pvo; 1870 int pteidx; 1871 1872 vm_page_lock_queues(); 1873 PMAP_LOCK(pm); 1874 for (; sva < eva; sva += PAGE_SIZE) { 1875 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1876 if (pvo != NULL) { 1877 moea64_pvo_remove(pvo, pteidx); 1878 } 1879 } 1880 vm_page_unlock_queues(); 1881 PMAP_UNLOCK(pm); 1882 } 1883 1884 /* 1885 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1886 * will reflect changes in pte's back to the vm_page. 1887 */ 1888 void 1889 moea64_remove_all(mmu_t mmu, vm_page_t m) 1890 { 1891 struct pvo_head *pvo_head; 1892 struct pvo_entry *pvo, *next_pvo; 1893 pmap_t pmap; 1894 1895 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1896 1897 pvo_head = vm_page_to_pvoh(m); 1898 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1899 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1900 1901 MOEA_PVO_CHECK(pvo); /* sanity check */ 1902 pmap = pvo->pvo_pmap; 1903 PMAP_LOCK(pmap); 1904 moea64_pvo_remove(pvo, -1); 1905 PMAP_UNLOCK(pmap); 1906 } 1907 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 1908 moea64_attr_clear(m, LPTE_CHG); 1909 vm_page_dirty(m); 1910 } 1911 vm_page_flag_clear(m, PG_WRITEABLE); 1912 } 1913 1914 /* 1915 * Allocate a physical page of memory directly from the phys_avail map. 1916 * Can only be called from moea64_bootstrap before avail start and end are 1917 * calculated. 1918 */ 1919 static vm_offset_t 1920 moea64_bootstrap_alloc(vm_size_t size, u_int align) 1921 { 1922 vm_offset_t s, e; 1923 int i, j; 1924 1925 size = round_page(size); 1926 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1927 if (align != 0) 1928 s = (phys_avail[i] + align - 1) & ~(align - 1); 1929 else 1930 s = phys_avail[i]; 1931 e = s + size; 1932 1933 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1934 continue; 1935 1936 if (s == phys_avail[i]) { 1937 phys_avail[i] += size; 1938 } else if (e == phys_avail[i + 1]) { 1939 phys_avail[i + 1] -= size; 1940 } else { 1941 for (j = phys_avail_count * 2; j > i; j -= 2) { 1942 phys_avail[j] = phys_avail[j - 2]; 1943 phys_avail[j + 1] = phys_avail[j - 1]; 1944 } 1945 1946 phys_avail[i + 3] = phys_avail[i + 1]; 1947 phys_avail[i + 1] = s; 1948 phys_avail[i + 2] = e; 1949 phys_avail_count++; 1950 } 1951 1952 return (s); 1953 } 1954 panic("moea64_bootstrap_alloc: could not allocate memory"); 1955 } 1956 1957 static void 1958 tlbia(void) 1959 { 1960 vm_offset_t i; 1961 register_t msr, scratch; 1962 1963 for (i = 0; i < 0xFF000; i += 0x00001000) { 1964 __asm __volatile("\ 1965 mfmsr %0; \ 1966 mr %1, %0; \ 1967 insrdi %1,%3,1,0; \ 1968 mtmsrd %1; \ 1969 ptesync; \ 1970 \ 1971 tlbiel %2; \ 1972 \ 1973 mtmsrd %0; \ 1974 eieio; \ 1975 tlbsync; \ 1976 ptesync;" 1977 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1)); 1978 } 1979 } 1980 1981 static int 1982 moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1983 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags) 1984 { 1985 struct pvo_entry *pvo; 1986 uint64_t vsid; 1987 int first; 1988 u_int ptegidx; 1989 int i; 1990 int bootstrap; 1991 1992 /* 1993 * One nasty thing that can happen here is that the UMA calls to 1994 * allocate new PVOs need to map more memory, which calls pvo_enter(), 1995 * which calls UMA... 1996 * 1997 * We break the loop by detecting recursion and allocating out of 1998 * the bootstrap pool. 1999 */ 2000 2001 moea64_pvo_enter_calls++; 2002 first = 0; 2003 bootstrap = (flags & PVO_BOOTSTRAP); 2004 2005 if (!moea64_initialized) 2006 bootstrap = 1; 2007 2008 /* 2009 * Compute the PTE Group index. 2010 */ 2011 va &= ~ADDR_POFF; 2012 vsid = va_to_vsid(pm, va); 2013 ptegidx = va_to_pteg(vsid, va); 2014 2015 /* 2016 * Remove any existing mapping for this page. Reuse the pvo entry if 2017 * there is a mapping. 2018 */ 2019 LOCK_TABLE(); 2020 2021 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2022 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2023 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2024 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2025 (pte_lo & LPTE_PP)) { 2026 UNLOCK_TABLE(); 2027 return (0); 2028 } 2029 moea64_pvo_remove(pvo, -1); 2030 break; 2031 } 2032 } 2033 2034 /* 2035 * If we aren't overwriting a mapping, try to allocate. 2036 */ 2037 if (bootstrap) { 2038 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2039 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2040 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2041 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2042 } 2043 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2044 moea64_bpvo_pool_index++; 2045 bootstrap = 1; 2046 } else { 2047 /* 2048 * Note: drop the table around the UMA allocation in 2049 * case the UMA allocator needs to manipulate the page 2050 * table. The mapping we are working with is already 2051 * protected by the PMAP lock. 2052 */ 2053 UNLOCK_TABLE(); 2054 pvo = uma_zalloc(zone, M_NOWAIT); 2055 LOCK_TABLE(); 2056 } 2057 2058 if (pvo == NULL) { 2059 UNLOCK_TABLE(); 2060 return (ENOMEM); 2061 } 2062 2063 moea64_pvo_entries++; 2064 pvo->pvo_vaddr = va; 2065 pvo->pvo_pmap = pm; 2066 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2067 pvo->pvo_vaddr &= ~ADDR_POFF; 2068 2069 if (!(flags & VM_PROT_EXECUTE)) 2070 pte_lo |= LPTE_NOEXEC; 2071 if (flags & PVO_WIRED) 2072 pvo->pvo_vaddr |= PVO_WIRED; 2073 if (pvo_head != &moea64_pvo_kunmanaged) 2074 pvo->pvo_vaddr |= PVO_MANAGED; 2075 if (bootstrap) 2076 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2077 if (flags & PVO_FAKE) 2078 pvo->pvo_vaddr |= PVO_FAKE; 2079 2080 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2081 (uint64_t)(pa) | pte_lo); 2082 2083 /* 2084 * Remember if the list was empty and therefore will be the first 2085 * item. 2086 */ 2087 if (LIST_FIRST(pvo_head) == NULL) 2088 first = 1; 2089 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2090 2091 if (pvo->pvo_vaddr & PVO_WIRED) 2092 pm->pm_stats.wired_count++; 2093 pm->pm_stats.resident_count++; 2094 2095 /* 2096 * We hope this succeeds but it isn't required. 2097 */ 2098 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2099 if (i >= 0) { 2100 PVO_PTEGIDX_SET(pvo, i); 2101 } else { 2102 panic("moea64_pvo_enter: overflow"); 2103 moea64_pte_overflow++; 2104 } 2105 2106 if (pm == kernel_pmap) 2107 isync(); 2108 2109 UNLOCK_TABLE(); 2110 2111 return (first ? ENOENT : 0); 2112 } 2113 2114 static void 2115 moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2116 { 2117 struct lpte *pt; 2118 2119 /* 2120 * If there is an active pte entry, we need to deactivate it (and 2121 * save the ref & cfg bits). 2122 */ 2123 LOCK_TABLE(); 2124 pt = moea64_pvo_to_pte(pvo, pteidx); 2125 if (pt != NULL) { 2126 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2127 PVO_VADDR(pvo)); 2128 PVO_PTEGIDX_CLR(pvo); 2129 } else { 2130 moea64_pte_overflow--; 2131 } 2132 UNLOCK_TABLE(); 2133 2134 /* 2135 * Update our statistics. 2136 */ 2137 pvo->pvo_pmap->pm_stats.resident_count--; 2138 if (pvo->pvo_vaddr & PVO_WIRED) 2139 pvo->pvo_pmap->pm_stats.wired_count--; 2140 2141 /* 2142 * Save the REF/CHG bits into their cache if the page is managed. 2143 */ 2144 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2145 struct vm_page *pg; 2146 2147 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2148 if (pg != NULL) { 2149 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2150 (LPTE_REF | LPTE_CHG)); 2151 } 2152 } 2153 2154 /* 2155 * Remove this PVO from the PV list. 2156 */ 2157 LIST_REMOVE(pvo, pvo_vlink); 2158 2159 /* 2160 * Remove this from the overflow list and return it to the pool 2161 * if we aren't going to reuse it. 2162 */ 2163 LIST_REMOVE(pvo, pvo_olink); 2164 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2165 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2166 moea64_upvo_zone, pvo); 2167 moea64_pvo_entries--; 2168 moea64_pvo_remove_calls++; 2169 } 2170 2171 static __inline int 2172 moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2173 { 2174 int pteidx; 2175 2176 /* 2177 * We can find the actual pte entry without searching by grabbing 2178 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2179 * noticing the HID bit. 2180 */ 2181 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2182 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2183 pteidx ^= moea64_pteg_mask * 8; 2184 2185 return (pteidx); 2186 } 2187 2188 static struct pvo_entry * 2189 moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2190 { 2191 struct pvo_entry *pvo; 2192 int ptegidx; 2193 uint64_t vsid; 2194 2195 va &= ~ADDR_POFF; 2196 vsid = va_to_vsid(pm, va); 2197 ptegidx = va_to_pteg(vsid, va); 2198 2199 LOCK_TABLE(); 2200 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2201 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2202 if (pteidx_p) 2203 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2204 break; 2205 } 2206 } 2207 UNLOCK_TABLE(); 2208 2209 return (pvo); 2210 } 2211 2212 static struct lpte * 2213 moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2214 { 2215 struct lpte *pt; 2216 2217 /* 2218 * If we haven't been supplied the ptegidx, calculate it. 2219 */ 2220 if (pteidx == -1) { 2221 int ptegidx; 2222 uint64_t vsid; 2223 2224 vsid = va_to_vsid(pvo->pvo_pmap, PVO_VADDR(pvo)); 2225 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo)); 2226 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2227 } 2228 2229 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2230 2231 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2232 !PVO_PTEGIDX_ISSET(pvo)) { 2233 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2234 "valid pte index", pvo); 2235 } 2236 2237 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2238 PVO_PTEGIDX_ISSET(pvo)) { 2239 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2240 "pvo but no valid pte", pvo); 2241 } 2242 2243 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2244 LPTE_VALID) { 2245 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2246 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2247 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2248 } 2249 2250 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2251 ~(LPTE_CHG|LPTE_REF)) != 0) { 2252 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2253 "pte %p in moea64_pteg_table difference is %#x", 2254 pvo, pt, 2255 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2256 } 2257 2258 ASSERT_TABLE_LOCK(); 2259 return (pt); 2260 } 2261 2262 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2263 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2264 "moea64_pteg_table but valid in pvo", pvo, pt); 2265 } 2266 2267 return (NULL); 2268 } 2269 2270 static int 2271 moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2272 { 2273 struct lpte *pt; 2274 int i; 2275 2276 ASSERT_TABLE_LOCK(); 2277 2278 /* 2279 * First try primary hash. 2280 */ 2281 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2282 if ((pt->pte_hi & LPTE_VALID) == 0) { 2283 pvo_pt->pte_hi &= ~LPTE_HID; 2284 moea64_pte_set(pt, pvo_pt); 2285 return (i); 2286 } 2287 } 2288 2289 /* 2290 * Now try secondary hash. 2291 */ 2292 ptegidx ^= moea64_pteg_mask; 2293 2294 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2295 if ((pt->pte_hi & LPTE_VALID) == 0) { 2296 pvo_pt->pte_hi |= LPTE_HID; 2297 moea64_pte_set(pt, pvo_pt); 2298 return (i); 2299 } 2300 } 2301 2302 panic("moea64_pte_insert: overflow"); 2303 return (-1); 2304 } 2305 2306 static boolean_t 2307 moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2308 { 2309 struct pvo_entry *pvo; 2310 struct lpte *pt; 2311 2312 if (moea64_attr_fetch(m) & ptebit) 2313 return (TRUE); 2314 2315 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2316 MOEA_PVO_CHECK(pvo); /* sanity check */ 2317 2318 /* 2319 * See if we saved the bit off. If so, cache it and return 2320 * success. 2321 */ 2322 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2323 moea64_attr_save(m, ptebit); 2324 MOEA_PVO_CHECK(pvo); /* sanity check */ 2325 return (TRUE); 2326 } 2327 } 2328 2329 /* 2330 * No luck, now go through the hard part of looking at the PTEs 2331 * themselves. Sync so that any pending REF/CHG bits are flushed to 2332 * the PTEs. 2333 */ 2334 SYNC(); 2335 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2336 MOEA_PVO_CHECK(pvo); /* sanity check */ 2337 2338 /* 2339 * See if this pvo has a valid PTE. if so, fetch the 2340 * REF/CHG bits from the valid PTE. If the appropriate 2341 * ptebit is set, cache it and return success. 2342 */ 2343 LOCK_TABLE(); 2344 pt = moea64_pvo_to_pte(pvo, -1); 2345 if (pt != NULL) { 2346 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2347 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2348 UNLOCK_TABLE(); 2349 2350 moea64_attr_save(m, ptebit); 2351 MOEA_PVO_CHECK(pvo); /* sanity check */ 2352 return (TRUE); 2353 } 2354 } 2355 UNLOCK_TABLE(); 2356 } 2357 2358 return (FALSE); 2359 } 2360 2361 static u_int 2362 moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit) 2363 { 2364 u_int count; 2365 struct pvo_entry *pvo; 2366 struct lpte *pt; 2367 uint64_t rv; 2368 2369 /* 2370 * Clear the cached value. 2371 */ 2372 rv = moea64_attr_fetch(m); 2373 moea64_attr_clear(m, ptebit); 2374 2375 /* 2376 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2377 * we can reset the right ones). note that since the pvo entries and 2378 * list heads are accessed via BAT0 and are never placed in the page 2379 * table, we don't have to worry about further accesses setting the 2380 * REF/CHG bits. 2381 */ 2382 SYNC(); 2383 2384 /* 2385 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2386 * valid pte clear the ptebit from the valid pte. 2387 */ 2388 count = 0; 2389 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2390 MOEA_PVO_CHECK(pvo); /* sanity check */ 2391 2392 LOCK_TABLE(); 2393 pt = moea64_pvo_to_pte(pvo, -1); 2394 if (pt != NULL) { 2395 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2396 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2397 count++; 2398 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2399 } 2400 } 2401 UNLOCK_TABLE(); 2402 rv |= pvo->pvo_pte.lpte.pte_lo; 2403 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2404 MOEA_PVO_CHECK(pvo); /* sanity check */ 2405 } 2406 2407 if (origbit != NULL) { 2408 *origbit = rv; 2409 } 2410 2411 return (count); 2412 } 2413 2414 boolean_t 2415 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2416 { 2417 return (EFAULT); 2418 } 2419 2420 /* 2421 * Map a set of physical memory pages into the kernel virtual 2422 * address space. Return a pointer to where it is mapped. This 2423 * routine is intended to be used for mapping device memory, 2424 * NOT real memory. 2425 */ 2426 void * 2427 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2428 { 2429 vm_offset_t va, tmpva, ppa, offset; 2430 2431 ppa = trunc_page(pa); 2432 offset = pa & PAGE_MASK; 2433 size = roundup(offset + size, PAGE_SIZE); 2434 2435 va = kmem_alloc_nofault(kernel_map, size); 2436 2437 if (!va) 2438 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2439 2440 for (tmpva = va; size > 0;) { 2441 moea64_kenter(mmu, tmpva, ppa); 2442 size -= PAGE_SIZE; 2443 tmpva += PAGE_SIZE; 2444 ppa += PAGE_SIZE; 2445 } 2446 2447 return ((void *)(va + offset)); 2448 } 2449 2450 void 2451 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2452 { 2453 vm_offset_t base, offset; 2454 2455 base = trunc_page(va); 2456 offset = va & PAGE_MASK; 2457 size = roundup(offset + size, PAGE_SIZE); 2458 2459 kmem_free(kernel_map, base, size); 2460 } 2461 2462 static void 2463 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2464 { 2465 struct pvo_entry *pvo; 2466 vm_offset_t lim; 2467 vm_paddr_t pa; 2468 vm_size_t len; 2469 2470 PMAP_LOCK(pm); 2471 while (sz > 0) { 2472 lim = round_page(va); 2473 len = MIN(lim - va, sz); 2474 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2475 if (pvo != NULL) { 2476 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2477 (va & ADDR_POFF); 2478 moea64_syncicache(pm, va, pa, len); 2479 } 2480 va += len; 2481 sz -= len; 2482 } 2483 PMAP_UNLOCK(pm); 2484 } 2485