1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_phys.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_PER_DOM (PA_LOCK_COUNT * 3) 123 #define PV_LOCK_COUNT (PV_LOCK_PER_DOM * MAXMEMDOM) 124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 125 126 /* 127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 129 * index at (N << 45). 130 */ 131 #ifdef __powerpc64__ 132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 134 #else 135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 136 #endif 137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 144 145 struct ofw_map { 146 cell_t om_va; 147 cell_t om_len; 148 uint64_t om_pa; 149 cell_t om_mode; 150 }; 151 152 extern unsigned char _etext[]; 153 extern unsigned char _end[]; 154 155 extern void *slbtrap, *slbtrapend; 156 157 /* 158 * Map of physical memory regions. 159 */ 160 static struct mem_region *regions; 161 static struct mem_region *pregions; 162 static struct numa_mem_region *numa_pregions; 163 static u_int phys_avail_count; 164 static int regions_sz, pregions_sz, numapregions_sz; 165 166 extern void bs_remap_earlyboot(void); 167 168 /* 169 * Lock for the SLB tables. 170 */ 171 struct mtx moea64_slb_mutex; 172 173 /* 174 * PTEG data. 175 */ 176 u_long moea64_pteg_count; 177 u_long moea64_pteg_mask; 178 179 /* 180 * PVO data. 181 */ 182 183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 184 185 static struct pvo_entry *moea64_bpvo_pool; 186 static int moea64_bpvo_pool_index = 0; 187 static int moea64_bpvo_pool_size = 327680; 188 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 190 &moea64_bpvo_pool_index, 0, ""); 191 192 #define VSID_NBPW (sizeof(u_int32_t) * 8) 193 #ifdef __powerpc64__ 194 #define NVSIDS (NPMAPS * 16) 195 #define VSID_HASHMASK 0xffffffffUL 196 #else 197 #define NVSIDS NPMAPS 198 #define VSID_HASHMASK 0xfffffUL 199 #endif 200 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 201 202 static boolean_t moea64_initialized = FALSE; 203 204 #ifdef MOEA64_STATS 205 /* 206 * Statistics. 207 */ 208 u_int moea64_pte_valid = 0; 209 u_int moea64_pte_overflow = 0; 210 u_int moea64_pvo_entries = 0; 211 u_int moea64_pvo_enter_calls = 0; 212 u_int moea64_pvo_remove_calls = 0; 213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 214 &moea64_pte_valid, 0, ""); 215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 216 &moea64_pte_overflow, 0, ""); 217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 218 &moea64_pvo_entries, 0, ""); 219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 220 &moea64_pvo_enter_calls, 0, ""); 221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 222 &moea64_pvo_remove_calls, 0, ""); 223 #endif 224 225 vm_offset_t moea64_scratchpage_va[2]; 226 struct pvo_entry *moea64_scratchpage_pvo[2]; 227 struct mtx moea64_scratchpage_mtx; 228 229 uint64_t moea64_large_page_mask = 0; 230 uint64_t moea64_large_page_size = 0; 231 int moea64_large_page_shift = 0; 232 233 /* 234 * PVO calls. 235 */ 236 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 237 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 238 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 240 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 241 struct pvo_entry *pvo, vm_page_t m); 242 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 243 244 /* 245 * Utility routines. 246 */ 247 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 248 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 249 static void moea64_kremove(mmu_t, vm_offset_t); 250 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 251 vm_paddr_t pa, vm_size_t sz); 252 static void moea64_pmap_init_qpages(void); 253 254 /* 255 * Kernel MMU interface 256 */ 257 void moea64_clear_modify(mmu_t, vm_page_t); 258 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 259 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 260 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 261 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 262 u_int flags, int8_t psind); 263 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 264 vm_prot_t); 265 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 266 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 267 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 268 void moea64_init(mmu_t); 269 boolean_t moea64_is_modified(mmu_t, vm_page_t); 270 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 271 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 272 int moea64_ts_referenced(mmu_t, vm_page_t); 273 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 274 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 275 void moea64_page_init(mmu_t, vm_page_t); 276 int moea64_page_wired_mappings(mmu_t, vm_page_t); 277 void moea64_pinit(mmu_t, pmap_t); 278 void moea64_pinit0(mmu_t, pmap_t); 279 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 280 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 281 void moea64_qremove(mmu_t, vm_offset_t, int); 282 void moea64_release(mmu_t, pmap_t); 283 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 284 void moea64_remove_pages(mmu_t, pmap_t); 285 void moea64_remove_all(mmu_t, vm_page_t); 286 void moea64_remove_write(mmu_t, vm_page_t); 287 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 288 void moea64_zero_page(mmu_t, vm_page_t); 289 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 290 void moea64_activate(mmu_t, struct thread *); 291 void moea64_deactivate(mmu_t, struct thread *); 292 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 293 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 294 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 295 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 296 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 297 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 298 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 299 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 300 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 301 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 302 void **va); 303 void moea64_scan_init(mmu_t mmu); 304 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 305 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 306 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 308 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 309 int *is_user, vm_offset_t *decoded_addr); 310 static size_t moea64_scan_pmap(mmu_t mmu); 311 static void *moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs); 312 313 314 static mmu_method_t moea64_methods[] = { 315 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 316 MMUMETHOD(mmu_copy_page, moea64_copy_page), 317 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 318 MMUMETHOD(mmu_enter, moea64_enter), 319 MMUMETHOD(mmu_enter_object, moea64_enter_object), 320 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 321 MMUMETHOD(mmu_extract, moea64_extract), 322 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 323 MMUMETHOD(mmu_init, moea64_init), 324 MMUMETHOD(mmu_is_modified, moea64_is_modified), 325 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 326 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 327 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 328 MMUMETHOD(mmu_map, moea64_map), 329 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 330 MMUMETHOD(mmu_page_init, moea64_page_init), 331 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 332 MMUMETHOD(mmu_pinit, moea64_pinit), 333 MMUMETHOD(mmu_pinit0, moea64_pinit0), 334 MMUMETHOD(mmu_protect, moea64_protect), 335 MMUMETHOD(mmu_qenter, moea64_qenter), 336 MMUMETHOD(mmu_qremove, moea64_qremove), 337 MMUMETHOD(mmu_release, moea64_release), 338 MMUMETHOD(mmu_remove, moea64_remove), 339 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 340 MMUMETHOD(mmu_remove_all, moea64_remove_all), 341 MMUMETHOD(mmu_remove_write, moea64_remove_write), 342 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 343 MMUMETHOD(mmu_unwire, moea64_unwire), 344 MMUMETHOD(mmu_zero_page, moea64_zero_page), 345 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 346 MMUMETHOD(mmu_activate, moea64_activate), 347 MMUMETHOD(mmu_deactivate, moea64_deactivate), 348 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 349 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 350 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 351 352 /* Internal interfaces */ 353 MMUMETHOD(mmu_mapdev, moea64_mapdev), 354 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 355 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 356 MMUMETHOD(mmu_kextract, moea64_kextract), 357 MMUMETHOD(mmu_kenter, moea64_kenter), 358 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 359 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 360 MMUMETHOD(mmu_scan_init, moea64_scan_init), 361 MMUMETHOD(mmu_scan_pmap, moea64_scan_pmap), 362 MMUMETHOD(mmu_dump_pmap_init, moea64_dump_pmap_init), 363 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 364 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 365 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 366 367 { 0, 0 } 368 }; 369 370 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 371 372 static struct pvo_head * 373 vm_page_to_pvoh(vm_page_t m) 374 { 375 376 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 377 return (&m->md.mdpg_pvoh); 378 } 379 380 static struct pvo_entry * 381 alloc_pvo_entry(int bootstrap) 382 { 383 struct pvo_entry *pvo; 384 385 if (!moea64_initialized || bootstrap) { 386 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 387 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 388 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 389 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 390 } 391 pvo = &moea64_bpvo_pool[ 392 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 393 bzero(pvo, sizeof(*pvo)); 394 pvo->pvo_vaddr = PVO_BOOTSTRAP; 395 } else 396 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 397 398 return (pvo); 399 } 400 401 402 static void 403 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 404 { 405 uint64_t vsid; 406 uint64_t hash; 407 int shift; 408 409 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 410 411 pvo->pvo_pmap = pmap; 412 va &= ~ADDR_POFF; 413 pvo->pvo_vaddr |= va; 414 vsid = va_to_vsid(pmap, va); 415 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 416 | (vsid << 16); 417 418 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 419 ADDR_PIDX_SHFT; 420 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 421 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 422 } 423 424 static void 425 free_pvo_entry(struct pvo_entry *pvo) 426 { 427 428 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 429 uma_zfree(moea64_pvo_zone, pvo); 430 } 431 432 void 433 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 434 { 435 436 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 437 LPTE_AVPN_MASK; 438 lpte->pte_hi |= LPTE_VALID; 439 440 if (pvo->pvo_vaddr & PVO_LARGE) 441 lpte->pte_hi |= LPTE_BIG; 442 if (pvo->pvo_vaddr & PVO_WIRED) 443 lpte->pte_hi |= LPTE_WIRED; 444 if (pvo->pvo_vaddr & PVO_HID) 445 lpte->pte_hi |= LPTE_HID; 446 447 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 448 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 449 lpte->pte_lo |= LPTE_BW; 450 else 451 lpte->pte_lo |= LPTE_BR; 452 453 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 454 lpte->pte_lo |= LPTE_NOEXEC; 455 } 456 457 static __inline uint64_t 458 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 459 { 460 uint64_t pte_lo; 461 int i; 462 463 if (ma != VM_MEMATTR_DEFAULT) { 464 switch (ma) { 465 case VM_MEMATTR_UNCACHEABLE: 466 return (LPTE_I | LPTE_G); 467 case VM_MEMATTR_CACHEABLE: 468 return (LPTE_M); 469 case VM_MEMATTR_WRITE_COMBINING: 470 case VM_MEMATTR_WRITE_BACK: 471 case VM_MEMATTR_PREFETCHABLE: 472 return (LPTE_I); 473 case VM_MEMATTR_WRITE_THROUGH: 474 return (LPTE_W | LPTE_M); 475 } 476 } 477 478 /* 479 * Assume the page is cache inhibited and access is guarded unless 480 * it's in our available memory array. 481 */ 482 pte_lo = LPTE_I | LPTE_G; 483 for (i = 0; i < pregions_sz; i++) { 484 if ((pa >= pregions[i].mr_start) && 485 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 486 pte_lo &= ~(LPTE_I | LPTE_G); 487 pte_lo |= LPTE_M; 488 break; 489 } 490 } 491 492 return pte_lo; 493 } 494 495 /* 496 * Quick sort callout for comparing memory regions. 497 */ 498 static int om_cmp(const void *a, const void *b); 499 500 static int 501 om_cmp(const void *a, const void *b) 502 { 503 const struct ofw_map *mapa; 504 const struct ofw_map *mapb; 505 506 mapa = a; 507 mapb = b; 508 if (mapa->om_pa < mapb->om_pa) 509 return (-1); 510 else if (mapa->om_pa > mapb->om_pa) 511 return (1); 512 else 513 return (0); 514 } 515 516 static void 517 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 518 { 519 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 520 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 521 struct pvo_entry *pvo; 522 register_t msr; 523 vm_offset_t off; 524 vm_paddr_t pa_base; 525 int i, j; 526 527 bzero(translations, sz); 528 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 529 sizeof(acells)); 530 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 531 panic("moea64_bootstrap: can't get ofw translations"); 532 533 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 534 sz /= sizeof(cell_t); 535 for (i = 0, j = 0; i < sz; j++) { 536 translations[j].om_va = trans_cells[i++]; 537 translations[j].om_len = trans_cells[i++]; 538 translations[j].om_pa = trans_cells[i++]; 539 if (acells == 2) { 540 translations[j].om_pa <<= 32; 541 translations[j].om_pa |= trans_cells[i++]; 542 } 543 translations[j].om_mode = trans_cells[i++]; 544 } 545 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 546 i, sz)); 547 548 sz = j; 549 qsort(translations, sz, sizeof (*translations), om_cmp); 550 551 for (i = 0; i < sz; i++) { 552 pa_base = translations[i].om_pa; 553 #ifndef __powerpc64__ 554 if ((translations[i].om_pa >> 32) != 0) 555 panic("OFW translations above 32-bit boundary!"); 556 #endif 557 558 if (pa_base % PAGE_SIZE) 559 panic("OFW translation not page-aligned (phys)!"); 560 if (translations[i].om_va % PAGE_SIZE) 561 panic("OFW translation not page-aligned (virt)!"); 562 563 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 564 pa_base, translations[i].om_va, translations[i].om_len); 565 566 /* Now enter the pages for this mapping */ 567 568 DISABLE_TRANS(msr); 569 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 570 /* If this address is direct-mapped, skip remapping */ 571 if (hw_direct_map && 572 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 573 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 574 == LPTE_M) 575 continue; 576 577 PMAP_LOCK(kernel_pmap); 578 pvo = moea64_pvo_find_va(kernel_pmap, 579 translations[i].om_va + off); 580 PMAP_UNLOCK(kernel_pmap); 581 if (pvo != NULL) 582 continue; 583 584 moea64_kenter(mmup, translations[i].om_va + off, 585 pa_base + off); 586 } 587 ENABLE_TRANS(msr); 588 } 589 } 590 591 #ifdef __powerpc64__ 592 static void 593 moea64_probe_large_page(void) 594 { 595 uint16_t pvr = mfpvr() >> 16; 596 597 switch (pvr) { 598 case IBM970: 599 case IBM970FX: 600 case IBM970MP: 601 powerpc_sync(); isync(); 602 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 603 powerpc_sync(); isync(); 604 605 /* FALLTHROUGH */ 606 default: 607 if (moea64_large_page_size == 0) { 608 moea64_large_page_size = 0x1000000; /* 16 MB */ 609 moea64_large_page_shift = 24; 610 } 611 } 612 613 moea64_large_page_mask = moea64_large_page_size - 1; 614 } 615 616 static void 617 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 618 { 619 struct slb *cache; 620 struct slb entry; 621 uint64_t esid, slbe; 622 uint64_t i; 623 624 cache = PCPU_GET(aim.slb); 625 esid = va >> ADDR_SR_SHFT; 626 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 627 628 for (i = 0; i < 64; i++) { 629 if (cache[i].slbe == (slbe | i)) 630 return; 631 } 632 633 entry.slbe = slbe; 634 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 635 if (large) 636 entry.slbv |= SLBV_L; 637 638 slb_insert_kernel(entry.slbe, entry.slbv); 639 } 640 #endif 641 642 static void 643 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 644 vm_offset_t kernelend) 645 { 646 struct pvo_entry *pvo; 647 register_t msr; 648 vm_paddr_t pa, pkernelstart, pkernelend; 649 vm_offset_t size, off; 650 uint64_t pte_lo; 651 int i; 652 653 if (moea64_large_page_size == 0) 654 hw_direct_map = 0; 655 656 DISABLE_TRANS(msr); 657 if (hw_direct_map) { 658 PMAP_LOCK(kernel_pmap); 659 for (i = 0; i < pregions_sz; i++) { 660 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 661 pregions[i].mr_size; pa += moea64_large_page_size) { 662 pte_lo = LPTE_M; 663 664 pvo = alloc_pvo_entry(1 /* bootstrap */); 665 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 666 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 667 668 /* 669 * Set memory access as guarded if prefetch within 670 * the page could exit the available physmem area. 671 */ 672 if (pa & moea64_large_page_mask) { 673 pa &= moea64_large_page_mask; 674 pte_lo |= LPTE_G; 675 } 676 if (pa + moea64_large_page_size > 677 pregions[i].mr_start + pregions[i].mr_size) 678 pte_lo |= LPTE_G; 679 680 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 681 VM_PROT_EXECUTE; 682 pvo->pvo_pte.pa = pa | pte_lo; 683 moea64_pvo_enter(mmup, pvo, NULL, NULL); 684 } 685 } 686 PMAP_UNLOCK(kernel_pmap); 687 } 688 689 /* 690 * Make sure the kernel and BPVO pool stay mapped on systems either 691 * without a direct map or on which the kernel is not already executing 692 * out of the direct-mapped region. 693 */ 694 if (kernelstart < DMAP_BASE_ADDRESS) { 695 /* 696 * For pre-dmap execution, we need to use identity mapping 697 * because we will be operating with the mmu on but in the 698 * wrong address configuration until we __restartkernel(). 699 */ 700 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 701 pa += PAGE_SIZE) 702 moea64_kenter(mmup, pa, pa); 703 } else if (!hw_direct_map) { 704 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 705 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 706 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 707 pa += PAGE_SIZE) 708 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 709 } 710 711 if (!hw_direct_map) { 712 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 713 off = (vm_offset_t)(moea64_bpvo_pool); 714 for (pa = off; pa < off + size; pa += PAGE_SIZE) 715 moea64_kenter(mmup, pa, pa); 716 717 /* Map exception vectors */ 718 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 719 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 720 } 721 ENABLE_TRANS(msr); 722 723 /* 724 * Allow user to override unmapped_buf_allowed for testing. 725 * XXXKIB Only direct map implementation was tested. 726 */ 727 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 728 &unmapped_buf_allowed)) 729 unmapped_buf_allowed = hw_direct_map; 730 } 731 732 /* Quick sort callout for comparing physical addresses. */ 733 static int 734 pa_cmp(const void *a, const void *b) 735 { 736 const vm_paddr_t *pa = a, *pb = b; 737 738 if (*pa < *pb) 739 return (-1); 740 else if (*pa > *pb) 741 return (1); 742 else 743 return (0); 744 } 745 746 void 747 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 748 { 749 int i, j; 750 vm_size_t physsz, hwphyssz; 751 vm_paddr_t kernelphysstart, kernelphysend; 752 int rm_pavail; 753 754 #ifndef __powerpc64__ 755 /* We don't have a direct map since there is no BAT */ 756 hw_direct_map = 0; 757 758 /* Make sure battable is zero, since we have no BAT */ 759 for (i = 0; i < 16; i++) { 760 battable[i].batu = 0; 761 battable[i].batl = 0; 762 } 763 #else 764 moea64_probe_large_page(); 765 766 /* Use a direct map if we have large page support */ 767 if (moea64_large_page_size > 0) 768 hw_direct_map = 1; 769 else 770 hw_direct_map = 0; 771 772 /* Install trap handlers for SLBs */ 773 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 774 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 775 __syncicache((void *)EXC_DSE, 0x80); 776 __syncicache((void *)EXC_ISE, 0x80); 777 #endif 778 779 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 780 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 781 782 /* Get physical memory regions from firmware */ 783 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 784 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 785 786 if (PHYS_AVAIL_ENTRIES < regions_sz) 787 panic("moea64_bootstrap: phys_avail too small"); 788 789 phys_avail_count = 0; 790 physsz = 0; 791 hwphyssz = 0; 792 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 793 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 794 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 795 regions[i].mr_start, regions[i].mr_start + 796 regions[i].mr_size, regions[i].mr_size); 797 if (hwphyssz != 0 && 798 (physsz + regions[i].mr_size) >= hwphyssz) { 799 if (physsz < hwphyssz) { 800 phys_avail[j] = regions[i].mr_start; 801 phys_avail[j + 1] = regions[i].mr_start + 802 hwphyssz - physsz; 803 physsz = hwphyssz; 804 phys_avail_count++; 805 dump_avail[j] = phys_avail[j]; 806 dump_avail[j + 1] = phys_avail[j + 1]; 807 } 808 break; 809 } 810 phys_avail[j] = regions[i].mr_start; 811 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 812 phys_avail_count++; 813 physsz += regions[i].mr_size; 814 dump_avail[j] = phys_avail[j]; 815 dump_avail[j + 1] = phys_avail[j + 1]; 816 } 817 818 /* Check for overlap with the kernel and exception vectors */ 819 rm_pavail = 0; 820 for (j = 0; j < 2*phys_avail_count; j+=2) { 821 if (phys_avail[j] < EXC_LAST) 822 phys_avail[j] += EXC_LAST; 823 824 if (phys_avail[j] >= kernelphysstart && 825 phys_avail[j+1] <= kernelphysend) { 826 phys_avail[j] = phys_avail[j+1] = ~0; 827 rm_pavail++; 828 continue; 829 } 830 831 if (kernelphysstart >= phys_avail[j] && 832 kernelphysstart < phys_avail[j+1]) { 833 if (kernelphysend < phys_avail[j+1]) { 834 phys_avail[2*phys_avail_count] = 835 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 836 phys_avail[2*phys_avail_count + 1] = 837 phys_avail[j+1]; 838 phys_avail_count++; 839 } 840 841 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 842 } 843 844 if (kernelphysend >= phys_avail[j] && 845 kernelphysend < phys_avail[j+1]) { 846 if (kernelphysstart > phys_avail[j]) { 847 phys_avail[2*phys_avail_count] = phys_avail[j]; 848 phys_avail[2*phys_avail_count + 1] = 849 kernelphysstart & ~PAGE_MASK; 850 phys_avail_count++; 851 } 852 853 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 854 PAGE_SIZE; 855 } 856 } 857 858 /* Remove physical available regions marked for removal (~0) */ 859 if (rm_pavail) { 860 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 861 pa_cmp); 862 phys_avail_count -= rm_pavail; 863 for (i = 2*phys_avail_count; 864 i < 2*(phys_avail_count + rm_pavail); i+=2) 865 phys_avail[i] = phys_avail[i+1] = 0; 866 } 867 868 physmem = btoc(physsz); 869 870 #ifdef PTEGCOUNT 871 moea64_pteg_count = PTEGCOUNT; 872 #else 873 moea64_pteg_count = 0x1000; 874 875 while (moea64_pteg_count < physmem) 876 moea64_pteg_count <<= 1; 877 878 moea64_pteg_count >>= 1; 879 #endif /* PTEGCOUNT */ 880 } 881 882 void 883 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 884 { 885 int i; 886 887 /* 888 * Set PTEG mask 889 */ 890 moea64_pteg_mask = moea64_pteg_count - 1; 891 892 /* 893 * Initialize SLB table lock and page locks 894 */ 895 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 896 for (i = 0; i < PV_LOCK_COUNT; i++) 897 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 898 899 /* 900 * Initialise the bootstrap pvo pool. 901 */ 902 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 903 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 904 moea64_bpvo_pool_index = 0; 905 906 /* Place at address usable through the direct map */ 907 if (hw_direct_map) 908 moea64_bpvo_pool = (struct pvo_entry *) 909 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 910 911 /* 912 * Make sure kernel vsid is allocated as well as VSID 0. 913 */ 914 #ifndef __powerpc64__ 915 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 916 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 917 moea64_vsid_bitmap[0] |= 1; 918 #endif 919 920 /* 921 * Initialize the kernel pmap (which is statically allocated). 922 */ 923 #ifdef __powerpc64__ 924 for (i = 0; i < 64; i++) { 925 pcpup->pc_aim.slb[i].slbv = 0; 926 pcpup->pc_aim.slb[i].slbe = 0; 927 } 928 #else 929 for (i = 0; i < 16; i++) 930 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 931 #endif 932 933 kernel_pmap->pmap_phys = kernel_pmap; 934 CPU_FILL(&kernel_pmap->pm_active); 935 RB_INIT(&kernel_pmap->pmap_pvo); 936 937 PMAP_LOCK_INIT(kernel_pmap); 938 939 /* 940 * Now map in all the other buffers we allocated earlier 941 */ 942 943 moea64_setup_direct_map(mmup, kernelstart, kernelend); 944 } 945 946 void 947 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 948 { 949 ihandle_t mmui; 950 phandle_t chosen; 951 phandle_t mmu; 952 ssize_t sz; 953 int i; 954 vm_offset_t pa, va; 955 void *dpcpu; 956 957 /* 958 * Set up the Open Firmware pmap and add its mappings if not in real 959 * mode. 960 */ 961 962 chosen = OF_finddevice("/chosen"); 963 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 964 mmu = OF_instance_to_package(mmui); 965 if (mmu == -1 || 966 (sz = OF_getproplen(mmu, "translations")) == -1) 967 sz = 0; 968 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 969 panic("moea64_bootstrap: too many ofw translations"); 970 971 if (sz > 0) 972 moea64_add_ofw_mappings(mmup, mmu, sz); 973 } 974 975 /* 976 * Calculate the last available physical address. 977 */ 978 Maxmem = 0; 979 for (i = 0; phys_avail[i + 2] != 0; i += 2) 980 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 981 982 /* 983 * Initialize MMU. 984 */ 985 MMU_CPU_BOOTSTRAP(mmup,0); 986 mtmsr(mfmsr() | PSL_DR | PSL_IR); 987 pmap_bootstrapped++; 988 989 /* 990 * Set the start and end of kva. 991 */ 992 virtual_avail = VM_MIN_KERNEL_ADDRESS; 993 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 994 995 /* 996 * Map the entire KVA range into the SLB. We must not fault there. 997 */ 998 #ifdef __powerpc64__ 999 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1000 moea64_bootstrap_slb_prefault(va, 0); 1001 #endif 1002 1003 /* 1004 * Remap any early IO mappings (console framebuffer, etc.) 1005 */ 1006 bs_remap_earlyboot(); 1007 1008 /* 1009 * Figure out how far we can extend virtual_end into segment 16 1010 * without running into existing mappings. Segment 16 is guaranteed 1011 * to contain neither RAM nor devices (at least on Apple hardware), 1012 * but will generally contain some OFW mappings we should not 1013 * step on. 1014 */ 1015 1016 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1017 PMAP_LOCK(kernel_pmap); 1018 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1019 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1020 virtual_end += PAGE_SIZE; 1021 PMAP_UNLOCK(kernel_pmap); 1022 #endif 1023 1024 /* 1025 * Allocate a kernel stack with a guard page for thread0 and map it 1026 * into the kernel page map. 1027 */ 1028 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1029 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1030 virtual_avail = va + kstack_pages * PAGE_SIZE; 1031 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1032 thread0.td_kstack = va; 1033 thread0.td_kstack_pages = kstack_pages; 1034 for (i = 0; i < kstack_pages; i++) { 1035 moea64_kenter(mmup, va, pa); 1036 pa += PAGE_SIZE; 1037 va += PAGE_SIZE; 1038 } 1039 1040 /* 1041 * Allocate virtual address space for the message buffer. 1042 */ 1043 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1044 msgbufp = (struct msgbuf *)virtual_avail; 1045 va = virtual_avail; 1046 virtual_avail += round_page(msgbufsize); 1047 while (va < virtual_avail) { 1048 moea64_kenter(mmup, va, pa); 1049 pa += PAGE_SIZE; 1050 va += PAGE_SIZE; 1051 } 1052 1053 /* 1054 * Allocate virtual address space for the dynamic percpu area. 1055 */ 1056 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1057 dpcpu = (void *)virtual_avail; 1058 va = virtual_avail; 1059 virtual_avail += DPCPU_SIZE; 1060 while (va < virtual_avail) { 1061 moea64_kenter(mmup, va, pa); 1062 pa += PAGE_SIZE; 1063 va += PAGE_SIZE; 1064 } 1065 dpcpu_init(dpcpu, curcpu); 1066 1067 crashdumpmap = (caddr_t)virtual_avail; 1068 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1069 1070 /* 1071 * Allocate some things for page zeroing. We put this directly 1072 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1073 * of the PVO book-keeping or other parts of the VM system 1074 * from even knowing that this hack exists. 1075 */ 1076 1077 if (!hw_direct_map) { 1078 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1079 MTX_DEF); 1080 for (i = 0; i < 2; i++) { 1081 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1082 virtual_end -= PAGE_SIZE; 1083 1084 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1085 1086 PMAP_LOCK(kernel_pmap); 1087 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1088 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1089 PMAP_UNLOCK(kernel_pmap); 1090 } 1091 } 1092 1093 numa_mem_regions(&numa_pregions, &numapregions_sz); 1094 } 1095 1096 static void 1097 moea64_pmap_init_qpages(void) 1098 { 1099 struct pcpu *pc; 1100 int i; 1101 1102 if (hw_direct_map) 1103 return; 1104 1105 CPU_FOREACH(i) { 1106 pc = pcpu_find(i); 1107 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1108 if (pc->pc_qmap_addr == 0) 1109 panic("pmap_init_qpages: unable to allocate KVA"); 1110 PMAP_LOCK(kernel_pmap); 1111 pc->pc_aim.qmap_pvo = 1112 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1113 PMAP_UNLOCK(kernel_pmap); 1114 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1115 } 1116 } 1117 1118 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1119 1120 /* 1121 * Activate a user pmap. This mostly involves setting some non-CPU 1122 * state. 1123 */ 1124 void 1125 moea64_activate(mmu_t mmu, struct thread *td) 1126 { 1127 pmap_t pm; 1128 1129 pm = &td->td_proc->p_vmspace->vm_pmap; 1130 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1131 1132 #ifdef __powerpc64__ 1133 PCPU_SET(aim.userslb, pm->pm_slb); 1134 __asm __volatile("slbmte %0, %1; isync" :: 1135 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1136 #else 1137 PCPU_SET(curpmap, pm->pmap_phys); 1138 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1139 #endif 1140 } 1141 1142 void 1143 moea64_deactivate(mmu_t mmu, struct thread *td) 1144 { 1145 pmap_t pm; 1146 1147 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1148 1149 pm = &td->td_proc->p_vmspace->vm_pmap; 1150 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1151 #ifdef __powerpc64__ 1152 PCPU_SET(aim.userslb, NULL); 1153 #else 1154 PCPU_SET(curpmap, NULL); 1155 #endif 1156 } 1157 1158 void 1159 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1160 { 1161 struct pvo_entry key, *pvo; 1162 vm_page_t m; 1163 int64_t refchg; 1164 1165 key.pvo_vaddr = sva; 1166 PMAP_LOCK(pm); 1167 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1168 pvo != NULL && PVO_VADDR(pvo) < eva; 1169 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1170 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1171 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1172 pvo); 1173 pvo->pvo_vaddr &= ~PVO_WIRED; 1174 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1175 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1176 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1177 if (refchg < 0) 1178 refchg = LPTE_CHG; 1179 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1180 1181 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1182 if (refchg & LPTE_CHG) 1183 vm_page_dirty(m); 1184 if (refchg & LPTE_REF) 1185 vm_page_aflag_set(m, PGA_REFERENCED); 1186 } 1187 pm->pm_stats.wired_count--; 1188 } 1189 PMAP_UNLOCK(pm); 1190 } 1191 1192 /* 1193 * This goes through and sets the physical address of our 1194 * special scratch PTE to the PA we want to zero or copy. Because 1195 * of locking issues (this can get called in pvo_enter() by 1196 * the UMA allocator), we can't use most other utility functions here 1197 */ 1198 1199 static __inline 1200 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1201 { 1202 struct pvo_entry *pvo; 1203 1204 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1205 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1206 1207 pvo = moea64_scratchpage_pvo[which]; 1208 PMAP_LOCK(pvo->pvo_pmap); 1209 pvo->pvo_pte.pa = 1210 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1211 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1212 PMAP_UNLOCK(pvo->pvo_pmap); 1213 isync(); 1214 } 1215 1216 void 1217 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1218 { 1219 vm_offset_t dst; 1220 vm_offset_t src; 1221 1222 dst = VM_PAGE_TO_PHYS(mdst); 1223 src = VM_PAGE_TO_PHYS(msrc); 1224 1225 if (hw_direct_map) { 1226 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1227 PAGE_SIZE); 1228 } else { 1229 mtx_lock(&moea64_scratchpage_mtx); 1230 1231 moea64_set_scratchpage_pa(mmu, 0, src); 1232 moea64_set_scratchpage_pa(mmu, 1, dst); 1233 1234 bcopy((void *)moea64_scratchpage_va[0], 1235 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1236 1237 mtx_unlock(&moea64_scratchpage_mtx); 1238 } 1239 } 1240 1241 static inline void 1242 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1243 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1244 { 1245 void *a_cp, *b_cp; 1246 vm_offset_t a_pg_offset, b_pg_offset; 1247 int cnt; 1248 1249 while (xfersize > 0) { 1250 a_pg_offset = a_offset & PAGE_MASK; 1251 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1252 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1253 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1254 a_pg_offset; 1255 b_pg_offset = b_offset & PAGE_MASK; 1256 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1257 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1258 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1259 b_pg_offset; 1260 bcopy(a_cp, b_cp, cnt); 1261 a_offset += cnt; 1262 b_offset += cnt; 1263 xfersize -= cnt; 1264 } 1265 } 1266 1267 static inline void 1268 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1269 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1270 { 1271 void *a_cp, *b_cp; 1272 vm_offset_t a_pg_offset, b_pg_offset; 1273 int cnt; 1274 1275 mtx_lock(&moea64_scratchpage_mtx); 1276 while (xfersize > 0) { 1277 a_pg_offset = a_offset & PAGE_MASK; 1278 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1279 moea64_set_scratchpage_pa(mmu, 0, 1280 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1281 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1282 b_pg_offset = b_offset & PAGE_MASK; 1283 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1284 moea64_set_scratchpage_pa(mmu, 1, 1285 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1286 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1287 bcopy(a_cp, b_cp, cnt); 1288 a_offset += cnt; 1289 b_offset += cnt; 1290 xfersize -= cnt; 1291 } 1292 mtx_unlock(&moea64_scratchpage_mtx); 1293 } 1294 1295 void 1296 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1297 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1298 { 1299 1300 if (hw_direct_map) { 1301 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1302 xfersize); 1303 } else { 1304 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1305 xfersize); 1306 } 1307 } 1308 1309 void 1310 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1311 { 1312 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1313 1314 if (size + off > PAGE_SIZE) 1315 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1316 1317 if (hw_direct_map) { 1318 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1319 } else { 1320 mtx_lock(&moea64_scratchpage_mtx); 1321 moea64_set_scratchpage_pa(mmu, 0, pa); 1322 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1323 mtx_unlock(&moea64_scratchpage_mtx); 1324 } 1325 } 1326 1327 /* 1328 * Zero a page of physical memory by temporarily mapping it 1329 */ 1330 void 1331 moea64_zero_page(mmu_t mmu, vm_page_t m) 1332 { 1333 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1334 vm_offset_t va, off; 1335 1336 if (!hw_direct_map) { 1337 mtx_lock(&moea64_scratchpage_mtx); 1338 1339 moea64_set_scratchpage_pa(mmu, 0, pa); 1340 va = moea64_scratchpage_va[0]; 1341 } else { 1342 va = PHYS_TO_DMAP(pa); 1343 } 1344 1345 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1346 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1347 1348 if (!hw_direct_map) 1349 mtx_unlock(&moea64_scratchpage_mtx); 1350 } 1351 1352 vm_offset_t 1353 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1354 { 1355 struct pvo_entry *pvo; 1356 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1357 1358 if (hw_direct_map) 1359 return (PHYS_TO_DMAP(pa)); 1360 1361 /* 1362 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1363 * a critical section and access the PCPU data like on i386. 1364 * Instead, pin the thread and grab the PCPU lock to prevent 1365 * a preempting thread from using the same PCPU data. 1366 */ 1367 sched_pin(); 1368 1369 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1370 pvo = PCPU_GET(aim.qmap_pvo); 1371 1372 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1373 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1374 (uint64_t)pa; 1375 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1376 isync(); 1377 1378 return (PCPU_GET(qmap_addr)); 1379 } 1380 1381 void 1382 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1383 { 1384 if (hw_direct_map) 1385 return; 1386 1387 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1388 KASSERT(PCPU_GET(qmap_addr) == addr, 1389 ("moea64_quick_remove_page: invalid address")); 1390 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1391 sched_unpin(); 1392 } 1393 1394 /* 1395 * Map the given physical page at the specified virtual address in the 1396 * target pmap with the protection requested. If specified the page 1397 * will be wired down. 1398 */ 1399 1400 int 1401 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1402 vm_prot_t prot, u_int flags, int8_t psind) 1403 { 1404 struct pvo_entry *pvo, *oldpvo; 1405 struct pvo_head *pvo_head; 1406 uint64_t pte_lo; 1407 int error; 1408 1409 if ((m->oflags & VPO_UNMANAGED) == 0) { 1410 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1411 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1412 else 1413 VM_OBJECT_ASSERT_LOCKED(m->object); 1414 } 1415 1416 pvo = alloc_pvo_entry(0); 1417 if (pvo == NULL) 1418 return (KERN_RESOURCE_SHORTAGE); 1419 pvo->pvo_pmap = NULL; /* to be filled in later */ 1420 pvo->pvo_pte.prot = prot; 1421 1422 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1423 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1424 1425 if ((flags & PMAP_ENTER_WIRED) != 0) 1426 pvo->pvo_vaddr |= PVO_WIRED; 1427 1428 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1429 pvo_head = NULL; 1430 } else { 1431 pvo_head = &m->md.mdpg_pvoh; 1432 pvo->pvo_vaddr |= PVO_MANAGED; 1433 } 1434 1435 PV_PAGE_LOCK(m); 1436 PMAP_LOCK(pmap); 1437 if (pvo->pvo_pmap == NULL) 1438 init_pvo_entry(pvo, pmap, va); 1439 if (prot & VM_PROT_WRITE) 1440 if (pmap_bootstrapped && 1441 (m->oflags & VPO_UNMANAGED) == 0) 1442 vm_page_aflag_set(m, PGA_WRITEABLE); 1443 1444 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1445 if (error == EEXIST) { 1446 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1447 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1448 oldpvo->pvo_pte.prot == prot) { 1449 /* Identical mapping already exists */ 1450 error = 0; 1451 1452 /* If not in page table, reinsert it */ 1453 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1454 STAT_MOEA64(moea64_pte_overflow--); 1455 MOEA64_PTE_INSERT(mmu, oldpvo); 1456 } 1457 1458 /* Then just clean up and go home */ 1459 PV_PAGE_UNLOCK(m); 1460 PMAP_UNLOCK(pmap); 1461 free_pvo_entry(pvo); 1462 goto out; 1463 } else { 1464 /* Otherwise, need to kill it first */ 1465 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1466 "mapping does not match new mapping")); 1467 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1468 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1469 } 1470 } 1471 PMAP_UNLOCK(pmap); 1472 PV_PAGE_UNLOCK(m); 1473 1474 /* Free any dead pages */ 1475 if (error == EEXIST) { 1476 moea64_pvo_remove_from_page(mmu, oldpvo); 1477 free_pvo_entry(oldpvo); 1478 } 1479 1480 out: 1481 /* 1482 * Flush the page from the instruction cache if this page is 1483 * mapped executable and cacheable. 1484 */ 1485 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1486 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1487 vm_page_aflag_set(m, PGA_EXECUTABLE); 1488 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1489 } 1490 return (KERN_SUCCESS); 1491 } 1492 1493 static void 1494 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1495 vm_size_t sz) 1496 { 1497 1498 /* 1499 * This is much trickier than on older systems because 1500 * we can't sync the icache on physical addresses directly 1501 * without a direct map. Instead we check a couple of cases 1502 * where the memory is already mapped in and, failing that, 1503 * use the same trick we use for page zeroing to create 1504 * a temporary mapping for this physical address. 1505 */ 1506 1507 if (!pmap_bootstrapped) { 1508 /* 1509 * If PMAP is not bootstrapped, we are likely to be 1510 * in real mode. 1511 */ 1512 __syncicache((void *)(uintptr_t)pa, sz); 1513 } else if (pmap == kernel_pmap) { 1514 __syncicache((void *)va, sz); 1515 } else if (hw_direct_map) { 1516 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1517 } else { 1518 /* Use the scratch page to set up a temp mapping */ 1519 1520 mtx_lock(&moea64_scratchpage_mtx); 1521 1522 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1523 __syncicache((void *)(moea64_scratchpage_va[1] + 1524 (va & ADDR_POFF)), sz); 1525 1526 mtx_unlock(&moea64_scratchpage_mtx); 1527 } 1528 } 1529 1530 /* 1531 * Maps a sequence of resident pages belonging to the same object. 1532 * The sequence begins with the given page m_start. This page is 1533 * mapped at the given virtual address start. Each subsequent page is 1534 * mapped at a virtual address that is offset from start by the same 1535 * amount as the page is offset from m_start within the object. The 1536 * last page in the sequence is the page with the largest offset from 1537 * m_start that can be mapped at a virtual address less than the given 1538 * virtual address end. Not every virtual page between start and end 1539 * is mapped; only those for which a resident page exists with the 1540 * corresponding offset from m_start are mapped. 1541 */ 1542 void 1543 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1544 vm_page_t m_start, vm_prot_t prot) 1545 { 1546 vm_page_t m; 1547 vm_pindex_t diff, psize; 1548 1549 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1550 1551 psize = atop(end - start); 1552 m = m_start; 1553 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1554 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1555 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1556 PMAP_ENTER_QUICK_LOCKED, 0); 1557 m = TAILQ_NEXT(m, listq); 1558 } 1559 } 1560 1561 void 1562 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1563 vm_prot_t prot) 1564 { 1565 1566 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1567 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1568 } 1569 1570 vm_paddr_t 1571 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1572 { 1573 struct pvo_entry *pvo; 1574 vm_paddr_t pa; 1575 1576 PMAP_LOCK(pm); 1577 pvo = moea64_pvo_find_va(pm, va); 1578 if (pvo == NULL) 1579 pa = 0; 1580 else 1581 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1582 PMAP_UNLOCK(pm); 1583 1584 return (pa); 1585 } 1586 1587 /* 1588 * Atomically extract and hold the physical page with the given 1589 * pmap and virtual address pair if that mapping permits the given 1590 * protection. 1591 */ 1592 vm_page_t 1593 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1594 { 1595 struct pvo_entry *pvo; 1596 vm_page_t m; 1597 1598 m = NULL; 1599 PMAP_LOCK(pmap); 1600 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1601 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1602 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1603 if (!vm_page_wire_mapped(m)) 1604 m = NULL; 1605 } 1606 PMAP_UNLOCK(pmap); 1607 return (m); 1608 } 1609 1610 static mmu_t installed_mmu; 1611 1612 static void * 1613 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1614 uint8_t *flags, int wait) 1615 { 1616 struct pvo_entry *pvo; 1617 vm_offset_t va; 1618 vm_page_t m; 1619 int needed_lock; 1620 1621 /* 1622 * This entire routine is a horrible hack to avoid bothering kmem 1623 * for new KVA addresses. Because this can get called from inside 1624 * kmem allocation routines, calling kmem for a new address here 1625 * can lead to multiply locking non-recursive mutexes. 1626 */ 1627 1628 *flags = UMA_SLAB_PRIV; 1629 needed_lock = !PMAP_LOCKED(kernel_pmap); 1630 1631 m = vm_page_alloc_domain(NULL, 0, domain, 1632 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1633 if (m == NULL) 1634 return (NULL); 1635 1636 va = VM_PAGE_TO_PHYS(m); 1637 1638 pvo = alloc_pvo_entry(1 /* bootstrap */); 1639 1640 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1641 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1642 1643 if (needed_lock) 1644 PMAP_LOCK(kernel_pmap); 1645 1646 init_pvo_entry(pvo, kernel_pmap, va); 1647 pvo->pvo_vaddr |= PVO_WIRED; 1648 1649 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1650 1651 if (needed_lock) 1652 PMAP_UNLOCK(kernel_pmap); 1653 1654 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1655 bzero((void *)va, PAGE_SIZE); 1656 1657 return (void *)va; 1658 } 1659 1660 extern int elf32_nxstack; 1661 1662 void 1663 moea64_init(mmu_t mmu) 1664 { 1665 1666 CTR0(KTR_PMAP, "moea64_init"); 1667 1668 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1669 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1670 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1671 1672 if (!hw_direct_map) { 1673 installed_mmu = mmu; 1674 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1675 } 1676 1677 #ifdef COMPAT_FREEBSD32 1678 elf32_nxstack = 1; 1679 #endif 1680 1681 moea64_initialized = TRUE; 1682 } 1683 1684 boolean_t 1685 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1686 { 1687 1688 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1689 ("moea64_is_referenced: page %p is not managed", m)); 1690 1691 return (moea64_query_bit(mmu, m, LPTE_REF)); 1692 } 1693 1694 boolean_t 1695 moea64_is_modified(mmu_t mmu, vm_page_t m) 1696 { 1697 1698 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1699 ("moea64_is_modified: page %p is not managed", m)); 1700 1701 /* 1702 * If the page is not busied then this check is racy. 1703 */ 1704 if (!pmap_page_is_write_mapped(m)) 1705 return (FALSE); 1706 1707 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1708 } 1709 1710 boolean_t 1711 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1712 { 1713 struct pvo_entry *pvo; 1714 boolean_t rv = TRUE; 1715 1716 PMAP_LOCK(pmap); 1717 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1718 if (pvo != NULL) 1719 rv = FALSE; 1720 PMAP_UNLOCK(pmap); 1721 return (rv); 1722 } 1723 1724 void 1725 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1726 { 1727 1728 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1729 ("moea64_clear_modify: page %p is not managed", m)); 1730 vm_page_assert_busied(m); 1731 1732 if (!pmap_page_is_write_mapped(m)) 1733 return; 1734 moea64_clear_bit(mmu, m, LPTE_CHG); 1735 } 1736 1737 /* 1738 * Clear the write and modified bits in each of the given page's mappings. 1739 */ 1740 void 1741 moea64_remove_write(mmu_t mmu, vm_page_t m) 1742 { 1743 struct pvo_entry *pvo; 1744 int64_t refchg, ret; 1745 pmap_t pmap; 1746 1747 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1748 ("moea64_remove_write: page %p is not managed", m)); 1749 vm_page_assert_busied(m); 1750 1751 if (!pmap_page_is_write_mapped(m)) 1752 return 1753 1754 powerpc_sync(); 1755 PV_PAGE_LOCK(m); 1756 refchg = 0; 1757 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1758 pmap = pvo->pvo_pmap; 1759 PMAP_LOCK(pmap); 1760 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1761 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1762 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1763 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1764 MOEA64_PTE_PROT_UPDATE); 1765 if (ret < 0) 1766 ret = LPTE_CHG; 1767 refchg |= ret; 1768 if (pvo->pvo_pmap == kernel_pmap) 1769 isync(); 1770 } 1771 PMAP_UNLOCK(pmap); 1772 } 1773 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1774 vm_page_dirty(m); 1775 vm_page_aflag_clear(m, PGA_WRITEABLE); 1776 PV_PAGE_UNLOCK(m); 1777 } 1778 1779 /* 1780 * moea64_ts_referenced: 1781 * 1782 * Return a count of reference bits for a page, clearing those bits. 1783 * It is not necessary for every reference bit to be cleared, but it 1784 * is necessary that 0 only be returned when there are truly no 1785 * reference bits set. 1786 * 1787 * XXX: The exact number of bits to check and clear is a matter that 1788 * should be tested and standardized at some point in the future for 1789 * optimal aging of shared pages. 1790 */ 1791 int 1792 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1793 { 1794 1795 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1796 ("moea64_ts_referenced: page %p is not managed", m)); 1797 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1798 } 1799 1800 /* 1801 * Modify the WIMG settings of all mappings for a page. 1802 */ 1803 void 1804 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1805 { 1806 struct pvo_entry *pvo; 1807 int64_t refchg; 1808 pmap_t pmap; 1809 uint64_t lo; 1810 1811 if ((m->oflags & VPO_UNMANAGED) != 0) { 1812 m->md.mdpg_cache_attrs = ma; 1813 return; 1814 } 1815 1816 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1817 1818 PV_PAGE_LOCK(m); 1819 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1820 pmap = pvo->pvo_pmap; 1821 PMAP_LOCK(pmap); 1822 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1823 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1824 pvo->pvo_pte.pa |= lo; 1825 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1826 MOEA64_PTE_INVALIDATE); 1827 if (refchg < 0) 1828 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1829 LPTE_CHG : 0; 1830 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1831 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1832 refchg |= 1833 atomic_readandclear_32(&m->md.mdpg_attrs); 1834 if (refchg & LPTE_CHG) 1835 vm_page_dirty(m); 1836 if (refchg & LPTE_REF) 1837 vm_page_aflag_set(m, PGA_REFERENCED); 1838 } 1839 if (pvo->pvo_pmap == kernel_pmap) 1840 isync(); 1841 } 1842 PMAP_UNLOCK(pmap); 1843 } 1844 m->md.mdpg_cache_attrs = ma; 1845 PV_PAGE_UNLOCK(m); 1846 } 1847 1848 /* 1849 * Map a wired page into kernel virtual address space. 1850 */ 1851 void 1852 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1853 { 1854 int error; 1855 struct pvo_entry *pvo, *oldpvo; 1856 1857 do { 1858 pvo = alloc_pvo_entry(0); 1859 if (pvo == NULL) 1860 vm_wait(NULL); 1861 } while (pvo == NULL); 1862 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1863 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1864 pvo->pvo_vaddr |= PVO_WIRED; 1865 1866 PMAP_LOCK(kernel_pmap); 1867 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1868 if (oldpvo != NULL) 1869 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1870 init_pvo_entry(pvo, kernel_pmap, va); 1871 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1872 PMAP_UNLOCK(kernel_pmap); 1873 1874 /* Free any dead pages */ 1875 if (oldpvo != NULL) { 1876 moea64_pvo_remove_from_page(mmu, oldpvo); 1877 free_pvo_entry(oldpvo); 1878 } 1879 1880 if (error != 0 && error != ENOENT) 1881 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1882 (uintmax_t)pa, error); 1883 } 1884 1885 void 1886 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1887 { 1888 1889 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1890 } 1891 1892 /* 1893 * Extract the physical page address associated with the given kernel virtual 1894 * address. 1895 */ 1896 vm_paddr_t 1897 moea64_kextract(mmu_t mmu, vm_offset_t va) 1898 { 1899 struct pvo_entry *pvo; 1900 vm_paddr_t pa; 1901 1902 /* 1903 * Shortcut the direct-mapped case when applicable. We never put 1904 * anything but 1:1 (or 62-bit aliased) mappings below 1905 * VM_MIN_KERNEL_ADDRESS. 1906 */ 1907 if (va < VM_MIN_KERNEL_ADDRESS) 1908 return (va & ~DMAP_BASE_ADDRESS); 1909 1910 PMAP_LOCK(kernel_pmap); 1911 pvo = moea64_pvo_find_va(kernel_pmap, va); 1912 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1913 va)); 1914 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1915 PMAP_UNLOCK(kernel_pmap); 1916 return (pa); 1917 } 1918 1919 /* 1920 * Remove a wired page from kernel virtual address space. 1921 */ 1922 void 1923 moea64_kremove(mmu_t mmu, vm_offset_t va) 1924 { 1925 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1926 } 1927 1928 /* 1929 * Provide a kernel pointer corresponding to a given userland pointer. 1930 * The returned pointer is valid until the next time this function is 1931 * called in this thread. This is used internally in copyin/copyout. 1932 */ 1933 static int 1934 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1935 void **kaddr, size_t ulen, size_t *klen) 1936 { 1937 size_t l; 1938 #ifdef __powerpc64__ 1939 struct slb *slb; 1940 #endif 1941 register_t slbv; 1942 1943 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1944 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1945 if (l > ulen) 1946 l = ulen; 1947 if (klen) 1948 *klen = l; 1949 else if (l != ulen) 1950 return (EFAULT); 1951 1952 #ifdef __powerpc64__ 1953 /* Try lockless look-up first */ 1954 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1955 1956 if (slb == NULL) { 1957 /* If it isn't there, we need to pre-fault the VSID */ 1958 PMAP_LOCK(pm); 1959 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1960 PMAP_UNLOCK(pm); 1961 } else { 1962 slbv = slb->slbv; 1963 } 1964 1965 /* Mark segment no-execute */ 1966 slbv |= SLBV_N; 1967 #else 1968 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1969 1970 /* Mark segment no-execute */ 1971 slbv |= SR_N; 1972 #endif 1973 1974 /* If we have already set this VSID, we can just return */ 1975 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1976 return (0); 1977 1978 __asm __volatile("isync"); 1979 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1980 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1981 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1982 #ifdef __powerpc64__ 1983 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1984 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1985 #else 1986 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1987 #endif 1988 1989 return (0); 1990 } 1991 1992 /* 1993 * Figure out where a given kernel pointer (usually in a fault) points 1994 * to from the VM's perspective, potentially remapping into userland's 1995 * address space. 1996 */ 1997 static int 1998 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1999 vm_offset_t *decoded_addr) 2000 { 2001 vm_offset_t user_sr; 2002 2003 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2004 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2005 addr &= ADDR_PIDX | ADDR_POFF; 2006 addr |= user_sr << ADDR_SR_SHFT; 2007 *decoded_addr = addr; 2008 *is_user = 1; 2009 } else { 2010 *decoded_addr = addr; 2011 *is_user = 0; 2012 } 2013 2014 return (0); 2015 } 2016 2017 /* 2018 * Map a range of physical addresses into kernel virtual address space. 2019 * 2020 * The value passed in *virt is a suggested virtual address for the mapping. 2021 * Architectures which can support a direct-mapped physical to virtual region 2022 * can return the appropriate address within that region, leaving '*virt' 2023 * unchanged. Other architectures should map the pages starting at '*virt' and 2024 * update '*virt' with the first usable address after the mapped region. 2025 */ 2026 vm_offset_t 2027 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2028 vm_paddr_t pa_end, int prot) 2029 { 2030 vm_offset_t sva, va; 2031 2032 if (hw_direct_map) { 2033 /* 2034 * Check if every page in the region is covered by the direct 2035 * map. The direct map covers all of physical memory. Use 2036 * moea64_calc_wimg() as a shortcut to see if the page is in 2037 * physical memory as a way to see if the direct map covers it. 2038 */ 2039 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2040 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2041 break; 2042 if (va == pa_end) 2043 return (PHYS_TO_DMAP(pa_start)); 2044 } 2045 sva = *virt; 2046 va = sva; 2047 /* XXX respect prot argument */ 2048 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2049 moea64_kenter(mmu, va, pa_start); 2050 *virt = va; 2051 2052 return (sva); 2053 } 2054 2055 /* 2056 * Returns true if the pmap's pv is one of the first 2057 * 16 pvs linked to from this page. This count may 2058 * be changed upwards or downwards in the future; it 2059 * is only necessary that true be returned for a small 2060 * subset of pmaps for proper page aging. 2061 */ 2062 boolean_t 2063 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2064 { 2065 int loops; 2066 struct pvo_entry *pvo; 2067 boolean_t rv; 2068 2069 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2070 ("moea64_page_exists_quick: page %p is not managed", m)); 2071 loops = 0; 2072 rv = FALSE; 2073 PV_PAGE_LOCK(m); 2074 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2075 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2076 rv = TRUE; 2077 break; 2078 } 2079 if (++loops >= 16) 2080 break; 2081 } 2082 PV_PAGE_UNLOCK(m); 2083 return (rv); 2084 } 2085 2086 void 2087 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2088 { 2089 2090 m->md.mdpg_attrs = 0; 2091 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2092 LIST_INIT(&m->md.mdpg_pvoh); 2093 } 2094 2095 /* 2096 * Return the number of managed mappings to the given physical page 2097 * that are wired. 2098 */ 2099 int 2100 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2101 { 2102 struct pvo_entry *pvo; 2103 int count; 2104 2105 count = 0; 2106 if ((m->oflags & VPO_UNMANAGED) != 0) 2107 return (count); 2108 PV_PAGE_LOCK(m); 2109 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2110 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2111 count++; 2112 PV_PAGE_UNLOCK(m); 2113 return (count); 2114 } 2115 2116 static uintptr_t moea64_vsidcontext; 2117 2118 uintptr_t 2119 moea64_get_unique_vsid(void) { 2120 u_int entropy; 2121 register_t hash; 2122 uint32_t mask; 2123 int i; 2124 2125 entropy = 0; 2126 __asm __volatile("mftb %0" : "=r"(entropy)); 2127 2128 mtx_lock(&moea64_slb_mutex); 2129 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2130 u_int n; 2131 2132 /* 2133 * Create a new value by mutiplying by a prime and adding in 2134 * entropy from the timebase register. This is to make the 2135 * VSID more random so that the PT hash function collides 2136 * less often. (Note that the prime casues gcc to do shifts 2137 * instead of a multiply.) 2138 */ 2139 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2140 hash = moea64_vsidcontext & (NVSIDS - 1); 2141 if (hash == 0) /* 0 is special, avoid it */ 2142 continue; 2143 n = hash >> 5; 2144 mask = 1 << (hash & (VSID_NBPW - 1)); 2145 hash = (moea64_vsidcontext & VSID_HASHMASK); 2146 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2147 /* anything free in this bucket? */ 2148 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2149 entropy = (moea64_vsidcontext >> 20); 2150 continue; 2151 } 2152 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2153 mask = 1 << i; 2154 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2155 hash |= i; 2156 } 2157 if (hash == VSID_VRMA) /* also special, avoid this too */ 2158 continue; 2159 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2160 ("Allocating in-use VSID %#zx\n", hash)); 2161 moea64_vsid_bitmap[n] |= mask; 2162 mtx_unlock(&moea64_slb_mutex); 2163 return (hash); 2164 } 2165 2166 mtx_unlock(&moea64_slb_mutex); 2167 panic("%s: out of segments",__func__); 2168 } 2169 2170 #ifdef __powerpc64__ 2171 void 2172 moea64_pinit(mmu_t mmu, pmap_t pmap) 2173 { 2174 2175 RB_INIT(&pmap->pmap_pvo); 2176 2177 pmap->pm_slb_tree_root = slb_alloc_tree(); 2178 pmap->pm_slb = slb_alloc_user_cache(); 2179 pmap->pm_slb_len = 0; 2180 } 2181 #else 2182 void 2183 moea64_pinit(mmu_t mmu, pmap_t pmap) 2184 { 2185 int i; 2186 uint32_t hash; 2187 2188 RB_INIT(&pmap->pmap_pvo); 2189 2190 if (pmap_bootstrapped) 2191 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2192 (vm_offset_t)pmap); 2193 else 2194 pmap->pmap_phys = pmap; 2195 2196 /* 2197 * Allocate some segment registers for this pmap. 2198 */ 2199 hash = moea64_get_unique_vsid(); 2200 2201 for (i = 0; i < 16; i++) 2202 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2203 2204 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2205 } 2206 #endif 2207 2208 /* 2209 * Initialize the pmap associated with process 0. 2210 */ 2211 void 2212 moea64_pinit0(mmu_t mmu, pmap_t pm) 2213 { 2214 2215 PMAP_LOCK_INIT(pm); 2216 moea64_pinit(mmu, pm); 2217 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2218 } 2219 2220 /* 2221 * Set the physical protection on the specified range of this map as requested. 2222 */ 2223 static void 2224 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2225 { 2226 struct vm_page *pg; 2227 vm_prot_t oldprot; 2228 int32_t refchg; 2229 2230 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2231 2232 /* 2233 * Change the protection of the page. 2234 */ 2235 oldprot = pvo->pvo_pte.prot; 2236 pvo->pvo_pte.prot = prot; 2237 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2238 2239 /* 2240 * If the PVO is in the page table, update mapping 2241 */ 2242 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2243 if (refchg < 0) 2244 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2245 2246 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2247 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2248 if ((pg->oflags & VPO_UNMANAGED) == 0) 2249 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2250 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2251 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2252 } 2253 2254 /* 2255 * Update vm about the REF/CHG bits if the page is managed and we have 2256 * removed write access. 2257 */ 2258 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2259 (oldprot & VM_PROT_WRITE)) { 2260 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2261 if (refchg & LPTE_CHG) 2262 vm_page_dirty(pg); 2263 if (refchg & LPTE_REF) 2264 vm_page_aflag_set(pg, PGA_REFERENCED); 2265 } 2266 } 2267 2268 void 2269 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2270 vm_prot_t prot) 2271 { 2272 struct pvo_entry *pvo, *tpvo, key; 2273 2274 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2275 sva, eva, prot); 2276 2277 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2278 ("moea64_protect: non current pmap")); 2279 2280 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2281 moea64_remove(mmu, pm, sva, eva); 2282 return; 2283 } 2284 2285 PMAP_LOCK(pm); 2286 key.pvo_vaddr = sva; 2287 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2288 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2289 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2290 moea64_pvo_protect(mmu, pm, pvo, prot); 2291 } 2292 PMAP_UNLOCK(pm); 2293 } 2294 2295 /* 2296 * Map a list of wired pages into kernel virtual address space. This is 2297 * intended for temporary mappings which do not need page modification or 2298 * references recorded. Existing mappings in the region are overwritten. 2299 */ 2300 void 2301 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2302 { 2303 while (count-- > 0) { 2304 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2305 va += PAGE_SIZE; 2306 m++; 2307 } 2308 } 2309 2310 /* 2311 * Remove page mappings from kernel virtual address space. Intended for 2312 * temporary mappings entered by moea64_qenter. 2313 */ 2314 void 2315 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2316 { 2317 while (count-- > 0) { 2318 moea64_kremove(mmu, va); 2319 va += PAGE_SIZE; 2320 } 2321 } 2322 2323 void 2324 moea64_release_vsid(uint64_t vsid) 2325 { 2326 int idx, mask; 2327 2328 mtx_lock(&moea64_slb_mutex); 2329 idx = vsid & (NVSIDS-1); 2330 mask = 1 << (idx % VSID_NBPW); 2331 idx /= VSID_NBPW; 2332 KASSERT(moea64_vsid_bitmap[idx] & mask, 2333 ("Freeing unallocated VSID %#jx", vsid)); 2334 moea64_vsid_bitmap[idx] &= ~mask; 2335 mtx_unlock(&moea64_slb_mutex); 2336 } 2337 2338 2339 void 2340 moea64_release(mmu_t mmu, pmap_t pmap) 2341 { 2342 2343 /* 2344 * Free segment registers' VSIDs 2345 */ 2346 #ifdef __powerpc64__ 2347 slb_free_tree(pmap); 2348 slb_free_user_cache(pmap->pm_slb); 2349 #else 2350 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2351 2352 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2353 #endif 2354 } 2355 2356 /* 2357 * Remove all pages mapped by the specified pmap 2358 */ 2359 void 2360 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2361 { 2362 struct pvo_entry *pvo, *tpvo; 2363 struct pvo_dlist tofree; 2364 2365 SLIST_INIT(&tofree); 2366 2367 PMAP_LOCK(pm); 2368 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2369 if (pvo->pvo_vaddr & PVO_WIRED) 2370 continue; 2371 2372 /* 2373 * For locking reasons, remove this from the page table and 2374 * pmap, but save delinking from the vm_page for a second 2375 * pass 2376 */ 2377 moea64_pvo_remove_from_pmap(mmu, pvo); 2378 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2379 } 2380 PMAP_UNLOCK(pm); 2381 2382 while (!SLIST_EMPTY(&tofree)) { 2383 pvo = SLIST_FIRST(&tofree); 2384 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2385 moea64_pvo_remove_from_page(mmu, pvo); 2386 free_pvo_entry(pvo); 2387 } 2388 } 2389 2390 /* 2391 * Remove the given range of addresses from the specified map. 2392 */ 2393 void 2394 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2395 { 2396 struct pvo_entry *pvo, *tpvo, key; 2397 struct pvo_dlist tofree; 2398 2399 /* 2400 * Perform an unsynchronized read. This is, however, safe. 2401 */ 2402 if (pm->pm_stats.resident_count == 0) 2403 return; 2404 2405 key.pvo_vaddr = sva; 2406 2407 SLIST_INIT(&tofree); 2408 2409 PMAP_LOCK(pm); 2410 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2411 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2412 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2413 2414 /* 2415 * For locking reasons, remove this from the page table and 2416 * pmap, but save delinking from the vm_page for a second 2417 * pass 2418 */ 2419 moea64_pvo_remove_from_pmap(mmu, pvo); 2420 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2421 } 2422 PMAP_UNLOCK(pm); 2423 2424 while (!SLIST_EMPTY(&tofree)) { 2425 pvo = SLIST_FIRST(&tofree); 2426 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2427 moea64_pvo_remove_from_page(mmu, pvo); 2428 free_pvo_entry(pvo); 2429 } 2430 } 2431 2432 /* 2433 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2434 * will reflect changes in pte's back to the vm_page. 2435 */ 2436 void 2437 moea64_remove_all(mmu_t mmu, vm_page_t m) 2438 { 2439 struct pvo_entry *pvo, *next_pvo; 2440 struct pvo_head freequeue; 2441 int wasdead; 2442 pmap_t pmap; 2443 2444 LIST_INIT(&freequeue); 2445 2446 PV_PAGE_LOCK(m); 2447 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2448 pmap = pvo->pvo_pmap; 2449 PMAP_LOCK(pmap); 2450 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2451 if (!wasdead) 2452 moea64_pvo_remove_from_pmap(mmu, pvo); 2453 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2454 if (!wasdead) 2455 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2456 PMAP_UNLOCK(pmap); 2457 2458 } 2459 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2460 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2461 PV_PAGE_UNLOCK(m); 2462 2463 /* Clean up UMA allocations */ 2464 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2465 free_pvo_entry(pvo); 2466 } 2467 2468 /* 2469 * Allocate a physical page of memory directly from the phys_avail map. 2470 * Can only be called from moea64_bootstrap before avail start and end are 2471 * calculated. 2472 */ 2473 vm_offset_t 2474 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2475 { 2476 vm_offset_t s, e; 2477 int i, j; 2478 2479 size = round_page(size); 2480 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2481 if (align != 0) 2482 s = roundup2(phys_avail[i], align); 2483 else 2484 s = phys_avail[i]; 2485 e = s + size; 2486 2487 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2488 continue; 2489 2490 if (s + size > platform_real_maxaddr()) 2491 continue; 2492 2493 if (s == phys_avail[i]) { 2494 phys_avail[i] += size; 2495 } else if (e == phys_avail[i + 1]) { 2496 phys_avail[i + 1] -= size; 2497 } else { 2498 for (j = phys_avail_count * 2; j > i; j -= 2) { 2499 phys_avail[j] = phys_avail[j - 2]; 2500 phys_avail[j + 1] = phys_avail[j - 1]; 2501 } 2502 2503 phys_avail[i + 3] = phys_avail[i + 1]; 2504 phys_avail[i + 1] = s; 2505 phys_avail[i + 2] = e; 2506 phys_avail_count++; 2507 } 2508 2509 return (s); 2510 } 2511 panic("moea64_bootstrap_alloc: could not allocate memory"); 2512 } 2513 2514 static int 2515 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2516 struct pvo_entry **oldpvop) 2517 { 2518 int first, err; 2519 struct pvo_entry *old_pvo; 2520 2521 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2522 2523 STAT_MOEA64(moea64_pvo_enter_calls++); 2524 2525 /* 2526 * Add to pmap list 2527 */ 2528 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2529 2530 if (old_pvo != NULL) { 2531 if (oldpvop != NULL) 2532 *oldpvop = old_pvo; 2533 return (EEXIST); 2534 } 2535 2536 /* 2537 * Remember if the list was empty and therefore will be the first 2538 * item. 2539 */ 2540 if (pvo_head != NULL) { 2541 if (LIST_FIRST(pvo_head) == NULL) 2542 first = 1; 2543 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2544 } 2545 2546 if (pvo->pvo_vaddr & PVO_WIRED) 2547 pvo->pvo_pmap->pm_stats.wired_count++; 2548 pvo->pvo_pmap->pm_stats.resident_count++; 2549 2550 /* 2551 * Insert it into the hardware page table 2552 */ 2553 err = MOEA64_PTE_INSERT(mmu, pvo); 2554 if (err != 0) { 2555 panic("moea64_pvo_enter: overflow"); 2556 } 2557 2558 STAT_MOEA64(moea64_pvo_entries++); 2559 2560 if (pvo->pvo_pmap == kernel_pmap) 2561 isync(); 2562 2563 #ifdef __powerpc64__ 2564 /* 2565 * Make sure all our bootstrap mappings are in the SLB as soon 2566 * as virtual memory is switched on. 2567 */ 2568 if (!pmap_bootstrapped) 2569 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2570 pvo->pvo_vaddr & PVO_LARGE); 2571 #endif 2572 2573 return (first ? ENOENT : 0); 2574 } 2575 2576 static void 2577 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2578 { 2579 struct vm_page *pg; 2580 int32_t refchg; 2581 2582 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2583 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2584 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2585 2586 /* 2587 * If there is an active pte entry, we need to deactivate it 2588 */ 2589 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2590 if (refchg < 0) { 2591 /* 2592 * If it was evicted from the page table, be pessimistic and 2593 * dirty the page. 2594 */ 2595 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2596 refchg = LPTE_CHG; 2597 else 2598 refchg = 0; 2599 } 2600 2601 /* 2602 * Update our statistics. 2603 */ 2604 pvo->pvo_pmap->pm_stats.resident_count--; 2605 if (pvo->pvo_vaddr & PVO_WIRED) 2606 pvo->pvo_pmap->pm_stats.wired_count--; 2607 2608 /* 2609 * Remove this PVO from the pmap list. 2610 */ 2611 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2612 2613 /* 2614 * Mark this for the next sweep 2615 */ 2616 pvo->pvo_vaddr |= PVO_DEAD; 2617 2618 /* Send RC bits to VM */ 2619 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2620 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2621 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2622 if (pg != NULL) { 2623 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2624 if (refchg & LPTE_CHG) 2625 vm_page_dirty(pg); 2626 if (refchg & LPTE_REF) 2627 vm_page_aflag_set(pg, PGA_REFERENCED); 2628 } 2629 } 2630 } 2631 2632 static inline void 2633 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2634 vm_page_t m) 2635 { 2636 2637 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2638 2639 /* Use NULL pmaps as a sentinel for races in page deletion */ 2640 if (pvo->pvo_pmap == NULL) 2641 return; 2642 pvo->pvo_pmap = NULL; 2643 2644 /* 2645 * Update vm about page writeability/executability if managed 2646 */ 2647 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2648 if (pvo->pvo_vaddr & PVO_MANAGED) { 2649 if (m != NULL) { 2650 LIST_REMOVE(pvo, pvo_vlink); 2651 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2652 vm_page_aflag_clear(m, 2653 PGA_WRITEABLE | PGA_EXECUTABLE); 2654 } 2655 } 2656 2657 STAT_MOEA64(moea64_pvo_entries--); 2658 STAT_MOEA64(moea64_pvo_remove_calls++); 2659 } 2660 2661 static void 2662 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2663 { 2664 vm_page_t pg = NULL; 2665 2666 if (pvo->pvo_vaddr & PVO_MANAGED) 2667 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2668 2669 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2670 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2671 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2672 } 2673 2674 static struct pvo_entry * 2675 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2676 { 2677 struct pvo_entry key; 2678 2679 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2680 2681 key.pvo_vaddr = va & ~ADDR_POFF; 2682 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2683 } 2684 2685 static boolean_t 2686 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2687 { 2688 struct pvo_entry *pvo; 2689 int64_t ret; 2690 boolean_t rv; 2691 2692 /* 2693 * See if this bit is stored in the page already. 2694 */ 2695 if (m->md.mdpg_attrs & ptebit) 2696 return (TRUE); 2697 2698 /* 2699 * Examine each PTE. Sync so that any pending REF/CHG bits are 2700 * flushed to the PTEs. 2701 */ 2702 rv = FALSE; 2703 powerpc_sync(); 2704 PV_PAGE_LOCK(m); 2705 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2706 ret = 0; 2707 2708 /* 2709 * See if this pvo has a valid PTE. if so, fetch the 2710 * REF/CHG bits from the valid PTE. If the appropriate 2711 * ptebit is set, return success. 2712 */ 2713 PMAP_LOCK(pvo->pvo_pmap); 2714 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2715 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2716 PMAP_UNLOCK(pvo->pvo_pmap); 2717 2718 if (ret > 0) { 2719 atomic_set_32(&m->md.mdpg_attrs, 2720 ret & (LPTE_CHG | LPTE_REF)); 2721 if (ret & ptebit) { 2722 rv = TRUE; 2723 break; 2724 } 2725 } 2726 } 2727 PV_PAGE_UNLOCK(m); 2728 2729 return (rv); 2730 } 2731 2732 static u_int 2733 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2734 { 2735 u_int count; 2736 struct pvo_entry *pvo; 2737 int64_t ret; 2738 2739 /* 2740 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2741 * we can reset the right ones). 2742 */ 2743 powerpc_sync(); 2744 2745 /* 2746 * For each pvo entry, clear the pte's ptebit. 2747 */ 2748 count = 0; 2749 PV_PAGE_LOCK(m); 2750 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2751 ret = 0; 2752 2753 PMAP_LOCK(pvo->pvo_pmap); 2754 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2755 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2756 PMAP_UNLOCK(pvo->pvo_pmap); 2757 2758 if (ret > 0 && (ret & ptebit)) 2759 count++; 2760 } 2761 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2762 PV_PAGE_UNLOCK(m); 2763 2764 return (count); 2765 } 2766 2767 boolean_t 2768 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2769 { 2770 struct pvo_entry *pvo, key; 2771 vm_offset_t ppa; 2772 int error = 0; 2773 2774 if (hw_direct_map && mem_valid(pa, size) == 0) 2775 return (0); 2776 2777 PMAP_LOCK(kernel_pmap); 2778 ppa = pa & ~ADDR_POFF; 2779 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2780 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2781 ppa < pa + size; ppa += PAGE_SIZE, 2782 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2783 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2784 error = EFAULT; 2785 break; 2786 } 2787 } 2788 PMAP_UNLOCK(kernel_pmap); 2789 2790 return (error); 2791 } 2792 2793 /* 2794 * Map a set of physical memory pages into the kernel virtual 2795 * address space. Return a pointer to where it is mapped. This 2796 * routine is intended to be used for mapping device memory, 2797 * NOT real memory. 2798 */ 2799 void * 2800 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2801 { 2802 vm_offset_t va, tmpva, ppa, offset; 2803 2804 ppa = trunc_page(pa); 2805 offset = pa & PAGE_MASK; 2806 size = roundup2(offset + size, PAGE_SIZE); 2807 2808 va = kva_alloc(size); 2809 2810 if (!va) 2811 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2812 2813 for (tmpva = va; size > 0;) { 2814 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2815 size -= PAGE_SIZE; 2816 tmpva += PAGE_SIZE; 2817 ppa += PAGE_SIZE; 2818 } 2819 2820 return ((void *)(va + offset)); 2821 } 2822 2823 void * 2824 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2825 { 2826 2827 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2828 } 2829 2830 void 2831 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2832 { 2833 vm_offset_t base, offset; 2834 2835 base = trunc_page(va); 2836 offset = va & PAGE_MASK; 2837 size = roundup2(offset + size, PAGE_SIZE); 2838 2839 kva_free(base, size); 2840 } 2841 2842 void 2843 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2844 { 2845 struct pvo_entry *pvo; 2846 vm_offset_t lim; 2847 vm_paddr_t pa; 2848 vm_size_t len; 2849 2850 if (__predict_false(pm == NULL)) 2851 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2852 2853 PMAP_LOCK(pm); 2854 while (sz > 0) { 2855 lim = round_page(va+1); 2856 len = MIN(lim - va, sz); 2857 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2858 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2859 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2860 moea64_syncicache(mmu, pm, va, pa, len); 2861 } 2862 va += len; 2863 sz -= len; 2864 } 2865 PMAP_UNLOCK(pm); 2866 } 2867 2868 void 2869 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2870 { 2871 2872 *va = (void *)(uintptr_t)pa; 2873 } 2874 2875 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2876 2877 void 2878 moea64_scan_init(mmu_t mmu) 2879 { 2880 struct pvo_entry *pvo; 2881 vm_offset_t va; 2882 int i; 2883 2884 if (!do_minidump) { 2885 /* Initialize phys. segments for dumpsys(). */ 2886 memset(&dump_map, 0, sizeof(dump_map)); 2887 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2888 for (i = 0; i < pregions_sz; i++) { 2889 dump_map[i].pa_start = pregions[i].mr_start; 2890 dump_map[i].pa_size = pregions[i].mr_size; 2891 } 2892 return; 2893 } 2894 2895 /* Virtual segments for minidumps: */ 2896 memset(&dump_map, 0, sizeof(dump_map)); 2897 2898 /* 1st: kernel .data and .bss. */ 2899 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2900 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2901 dump_map[0].pa_start; 2902 2903 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2904 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2905 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2906 2907 /* 3rd: kernel VM. */ 2908 va = dump_map[1].pa_start + dump_map[1].pa_size; 2909 /* Find start of next chunk (from va). */ 2910 while (va < virtual_end) { 2911 /* Don't dump the buffer cache. */ 2912 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2913 va = kmi.buffer_eva; 2914 continue; 2915 } 2916 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2917 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2918 break; 2919 va += PAGE_SIZE; 2920 } 2921 if (va < virtual_end) { 2922 dump_map[2].pa_start = va; 2923 va += PAGE_SIZE; 2924 /* Find last page in chunk. */ 2925 while (va < virtual_end) { 2926 /* Don't run into the buffer cache. */ 2927 if (va == kmi.buffer_sva) 2928 break; 2929 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2930 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2931 break; 2932 va += PAGE_SIZE; 2933 } 2934 dump_map[2].pa_size = va - dump_map[2].pa_start; 2935 } 2936 } 2937 2938 #ifdef __powerpc64__ 2939 2940 static size_t 2941 moea64_scan_pmap(mmu_t mmu) 2942 { 2943 struct pvo_entry *pvo; 2944 vm_paddr_t pa, pa_end; 2945 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 2946 uint64_t lpsize; 2947 2948 lpsize = moea64_large_page_size; 2949 kstart = trunc_page((vm_offset_t)_etext); 2950 kend = round_page((vm_offset_t)_end); 2951 kstart_lp = kstart & ~moea64_large_page_mask; 2952 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 2953 2954 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 2955 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 2956 kstart, kend, kstart_lp, kend_lp); 2957 2958 PMAP_LOCK(kernel_pmap); 2959 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 2960 va = pvo->pvo_vaddr; 2961 2962 if (va & PVO_DEAD) 2963 continue; 2964 2965 /* Skip DMAP (except kernel area) */ 2966 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 2967 if (va & PVO_LARGE) { 2968 pgva = va & ~moea64_large_page_mask; 2969 if (pgva < kstart_lp || pgva >= kend_lp) 2970 continue; 2971 } else { 2972 pgva = trunc_page(va); 2973 if (pgva < kstart || pgva >= kend) 2974 continue; 2975 } 2976 } 2977 2978 pa = pvo->pvo_pte.pa & LPTE_RPGN; 2979 2980 if (va & PVO_LARGE) { 2981 pa_end = pa + lpsize; 2982 for (; pa < pa_end; pa += PAGE_SIZE) { 2983 if (is_dumpable(pa)) 2984 dump_add_page(pa); 2985 } 2986 } else { 2987 if (is_dumpable(pa)) 2988 dump_add_page(pa); 2989 } 2990 } 2991 PMAP_UNLOCK(kernel_pmap); 2992 2993 return (sizeof(struct lpte) * moea64_pteg_count * 8); 2994 } 2995 2996 static struct dump_context dump_ctx; 2997 2998 static void * 2999 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3000 { 3001 dump_ctx.ptex = 0; 3002 dump_ctx.ptex_end = moea64_pteg_count * 8; 3003 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3004 return (&dump_ctx); 3005 } 3006 3007 #else 3008 3009 static size_t 3010 moea64_scan_pmap(mmu_t mmu) 3011 { 3012 return (0); 3013 } 3014 3015 static void * 3016 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs) 3017 { 3018 return (NULL); 3019 } 3020 3021 #endif 3022