1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_compat.h" 118 #include "opt_kstack_pages.h" 119 120 #include <sys/param.h> 121 #include <sys/kernel.h> 122 #include <sys/queue.h> 123 #include <sys/cpuset.h> 124 #include <sys/ktr.h> 125 #include <sys/lock.h> 126 #include <sys/msgbuf.h> 127 #include <sys/mutex.h> 128 #include <sys/proc.h> 129 #include <sys/rwlock.h> 130 #include <sys/sched.h> 131 #include <sys/sysctl.h> 132 #include <sys/systm.h> 133 #include <sys/vmmeter.h> 134 135 #include <sys/kdb.h> 136 137 #include <dev/ofw/openfirm.h> 138 139 #include <vm/vm.h> 140 #include <vm/vm_param.h> 141 #include <vm/vm_kern.h> 142 #include <vm/vm_page.h> 143 #include <vm/vm_map.h> 144 #include <vm/vm_object.h> 145 #include <vm/vm_extern.h> 146 #include <vm/vm_pageout.h> 147 #include <vm/vm_pager.h> 148 #include <vm/uma.h> 149 150 #include <machine/_inttypes.h> 151 #include <machine/cpu.h> 152 #include <machine/platform.h> 153 #include <machine/frame.h> 154 #include <machine/md_var.h> 155 #include <machine/psl.h> 156 #include <machine/bat.h> 157 #include <machine/hid.h> 158 #include <machine/pte.h> 159 #include <machine/sr.h> 160 #include <machine/trap.h> 161 #include <machine/mmuvar.h> 162 163 #include "mmu_oea64.h" 164 #include "mmu_if.h" 165 #include "moea64_if.h" 166 167 void moea64_release_vsid(uint64_t vsid); 168 uintptr_t moea64_get_unique_vsid(void); 169 170 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 171 #define ENABLE_TRANS(msr) mtmsr(msr) 172 173 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 174 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 175 #define VSID_HASH_MASK 0x0000007fffffffffULL 176 177 /* 178 * Locking semantics: 179 * -- Read lock: if no modifications are being made to either the PVO lists 180 * or page table or if any modifications being made result in internal 181 * changes (e.g. wiring, protection) such that the existence of the PVOs 182 * is unchanged and they remain associated with the same pmap (in which 183 * case the changes should be protected by the pmap lock) 184 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 185 */ 186 187 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 188 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 189 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 190 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 191 192 struct ofw_map { 193 cell_t om_va; 194 cell_t om_len; 195 cell_t om_pa_hi; 196 cell_t om_pa_lo; 197 cell_t om_mode; 198 }; 199 200 /* 201 * Map of physical memory regions. 202 */ 203 static struct mem_region *regions; 204 static struct mem_region *pregions; 205 static u_int phys_avail_count; 206 static int regions_sz, pregions_sz; 207 208 extern void bs_remap_earlyboot(void); 209 210 /* 211 * Lock for the pteg and pvo tables. 212 */ 213 struct rwlock moea64_table_lock; 214 struct mtx moea64_slb_mutex; 215 216 /* 217 * PTEG data. 218 */ 219 u_int moea64_pteg_count; 220 u_int moea64_pteg_mask; 221 222 /* 223 * PVO data. 224 */ 225 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 226 struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */ 227 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 228 229 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 230 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 231 232 #define BPVO_POOL_SIZE 327680 233 static struct pvo_entry *moea64_bpvo_pool; 234 static int moea64_bpvo_pool_index = 0; 235 236 #define VSID_NBPW (sizeof(u_int32_t) * 8) 237 #ifdef __powerpc64__ 238 #define NVSIDS (NPMAPS * 16) 239 #define VSID_HASHMASK 0xffffffffUL 240 #else 241 #define NVSIDS NPMAPS 242 #define VSID_HASHMASK 0xfffffUL 243 #endif 244 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 245 246 static boolean_t moea64_initialized = FALSE; 247 248 /* 249 * Statistics. 250 */ 251 u_int moea64_pte_valid = 0; 252 u_int moea64_pte_overflow = 0; 253 u_int moea64_pvo_entries = 0; 254 u_int moea64_pvo_enter_calls = 0; 255 u_int moea64_pvo_remove_calls = 0; 256 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 257 &moea64_pte_valid, 0, ""); 258 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 259 &moea64_pte_overflow, 0, ""); 260 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 261 &moea64_pvo_entries, 0, ""); 262 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 263 &moea64_pvo_enter_calls, 0, ""); 264 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 265 &moea64_pvo_remove_calls, 0, ""); 266 267 vm_offset_t moea64_scratchpage_va[2]; 268 struct pvo_entry *moea64_scratchpage_pvo[2]; 269 uintptr_t moea64_scratchpage_pte[2]; 270 struct mtx moea64_scratchpage_mtx; 271 272 uint64_t moea64_large_page_mask = 0; 273 int moea64_large_page_size = 0; 274 int moea64_large_page_shift = 0; 275 276 /* 277 * PVO calls. 278 */ 279 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 280 vm_offset_t, vm_offset_t, uint64_t, int); 281 static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 282 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 283 284 /* 285 * Utility routines. 286 */ 287 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 288 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 289 static void moea64_kremove(mmu_t, vm_offset_t); 290 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 291 vm_offset_t pa, vm_size_t sz); 292 293 /* 294 * Kernel MMU interface 295 */ 296 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 297 void moea64_clear_modify(mmu_t, vm_page_t); 298 void moea64_clear_reference(mmu_t, vm_page_t); 299 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 300 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 301 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 302 vm_prot_t); 303 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 304 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 305 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 306 void moea64_init(mmu_t); 307 boolean_t moea64_is_modified(mmu_t, vm_page_t); 308 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 309 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 310 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 311 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 312 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 313 int moea64_page_wired_mappings(mmu_t, vm_page_t); 314 void moea64_pinit(mmu_t, pmap_t); 315 void moea64_pinit0(mmu_t, pmap_t); 316 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 317 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 318 void moea64_qremove(mmu_t, vm_offset_t, int); 319 void moea64_release(mmu_t, pmap_t); 320 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 321 void moea64_remove_pages(mmu_t, pmap_t); 322 void moea64_remove_all(mmu_t, vm_page_t); 323 void moea64_remove_write(mmu_t, vm_page_t); 324 void moea64_zero_page(mmu_t, vm_page_t); 325 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 326 void moea64_zero_page_idle(mmu_t, vm_page_t); 327 void moea64_activate(mmu_t, struct thread *); 328 void moea64_deactivate(mmu_t, struct thread *); 329 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 330 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 331 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 332 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 333 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 334 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 335 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 336 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 337 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 338 339 static mmu_method_t moea64_methods[] = { 340 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 341 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 342 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 343 MMUMETHOD(mmu_copy_page, moea64_copy_page), 344 MMUMETHOD(mmu_enter, moea64_enter), 345 MMUMETHOD(mmu_enter_object, moea64_enter_object), 346 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 347 MMUMETHOD(mmu_extract, moea64_extract), 348 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 349 MMUMETHOD(mmu_init, moea64_init), 350 MMUMETHOD(mmu_is_modified, moea64_is_modified), 351 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 352 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 353 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 354 MMUMETHOD(mmu_map, moea64_map), 355 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 356 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 357 MMUMETHOD(mmu_pinit, moea64_pinit), 358 MMUMETHOD(mmu_pinit0, moea64_pinit0), 359 MMUMETHOD(mmu_protect, moea64_protect), 360 MMUMETHOD(mmu_qenter, moea64_qenter), 361 MMUMETHOD(mmu_qremove, moea64_qremove), 362 MMUMETHOD(mmu_release, moea64_release), 363 MMUMETHOD(mmu_remove, moea64_remove), 364 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 365 MMUMETHOD(mmu_remove_all, moea64_remove_all), 366 MMUMETHOD(mmu_remove_write, moea64_remove_write), 367 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 368 MMUMETHOD(mmu_zero_page, moea64_zero_page), 369 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 370 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 371 MMUMETHOD(mmu_activate, moea64_activate), 372 MMUMETHOD(mmu_deactivate, moea64_deactivate), 373 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 374 375 /* Internal interfaces */ 376 MMUMETHOD(mmu_mapdev, moea64_mapdev), 377 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 378 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 379 MMUMETHOD(mmu_kextract, moea64_kextract), 380 MMUMETHOD(mmu_kenter, moea64_kenter), 381 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 382 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 383 384 { 0, 0 } 385 }; 386 387 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 388 389 static __inline u_int 390 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 391 { 392 uint64_t hash; 393 int shift; 394 395 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 396 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 397 shift); 398 return (hash & moea64_pteg_mask); 399 } 400 401 static __inline struct pvo_head * 402 vm_page_to_pvoh(vm_page_t m) 403 { 404 405 return (&m->md.mdpg_pvoh); 406 } 407 408 static __inline void 409 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 410 uint64_t pte_lo, int flags) 411 { 412 413 /* 414 * Construct a PTE. Default to IMB initially. Valid bit only gets 415 * set when the real pte is set in memory. 416 * 417 * Note: Don't set the valid bit for correct operation of tlb update. 418 */ 419 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 420 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 421 422 if (flags & PVO_LARGE) 423 pt->pte_hi |= LPTE_BIG; 424 425 pt->pte_lo = pte_lo; 426 } 427 428 static __inline uint64_t 429 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 430 { 431 uint64_t pte_lo; 432 int i; 433 434 if (ma != VM_MEMATTR_DEFAULT) { 435 switch (ma) { 436 case VM_MEMATTR_UNCACHEABLE: 437 return (LPTE_I | LPTE_G); 438 case VM_MEMATTR_WRITE_COMBINING: 439 case VM_MEMATTR_WRITE_BACK: 440 case VM_MEMATTR_PREFETCHABLE: 441 return (LPTE_I); 442 case VM_MEMATTR_WRITE_THROUGH: 443 return (LPTE_W | LPTE_M); 444 } 445 } 446 447 /* 448 * Assume the page is cache inhibited and access is guarded unless 449 * it's in our available memory array. 450 */ 451 pte_lo = LPTE_I | LPTE_G; 452 for (i = 0; i < pregions_sz; i++) { 453 if ((pa >= pregions[i].mr_start) && 454 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 455 pte_lo &= ~(LPTE_I | LPTE_G); 456 pte_lo |= LPTE_M; 457 break; 458 } 459 } 460 461 return pte_lo; 462 } 463 464 /* 465 * Quick sort callout for comparing memory regions. 466 */ 467 static int om_cmp(const void *a, const void *b); 468 469 static int 470 om_cmp(const void *a, const void *b) 471 { 472 const struct ofw_map *mapa; 473 const struct ofw_map *mapb; 474 475 mapa = a; 476 mapb = b; 477 if (mapa->om_pa_hi < mapb->om_pa_hi) 478 return (-1); 479 else if (mapa->om_pa_hi > mapb->om_pa_hi) 480 return (1); 481 else if (mapa->om_pa_lo < mapb->om_pa_lo) 482 return (-1); 483 else if (mapa->om_pa_lo > mapb->om_pa_lo) 484 return (1); 485 else 486 return (0); 487 } 488 489 static void 490 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 491 { 492 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 493 register_t msr; 494 vm_offset_t off; 495 vm_paddr_t pa_base; 496 int i; 497 498 bzero(translations, sz); 499 if (OF_getprop(mmu, "translations", translations, sz) == -1) 500 panic("moea64_bootstrap: can't get ofw translations"); 501 502 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 503 sz /= sizeof(*translations); 504 qsort(translations, sz, sizeof (*translations), om_cmp); 505 506 for (i = 0; i < sz; i++) { 507 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 508 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 509 translations[i].om_len); 510 511 if (translations[i].om_pa_lo % PAGE_SIZE) 512 panic("OFW translation not page-aligned!"); 513 514 pa_base = translations[i].om_pa_lo; 515 516 #ifdef __powerpc64__ 517 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 518 #else 519 if (translations[i].om_pa_hi) 520 panic("OFW translations above 32-bit boundary!"); 521 #endif 522 523 /* Now enter the pages for this mapping */ 524 525 DISABLE_TRANS(msr); 526 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 527 if (moea64_pvo_find_va(kernel_pmap, 528 translations[i].om_va + off) != NULL) 529 continue; 530 531 moea64_kenter(mmup, translations[i].om_va + off, 532 pa_base + off); 533 } 534 ENABLE_TRANS(msr); 535 } 536 } 537 538 #ifdef __powerpc64__ 539 static void 540 moea64_probe_large_page(void) 541 { 542 uint16_t pvr = mfpvr() >> 16; 543 544 switch (pvr) { 545 case IBM970: 546 case IBM970FX: 547 case IBM970MP: 548 powerpc_sync(); isync(); 549 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 550 powerpc_sync(); isync(); 551 552 /* FALLTHROUGH */ 553 case IBMCELLBE: 554 moea64_large_page_size = 0x1000000; /* 16 MB */ 555 moea64_large_page_shift = 24; 556 break; 557 default: 558 moea64_large_page_size = 0; 559 } 560 561 moea64_large_page_mask = moea64_large_page_size - 1; 562 } 563 564 static void 565 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 566 { 567 struct slb *cache; 568 struct slb entry; 569 uint64_t esid, slbe; 570 uint64_t i; 571 572 cache = PCPU_GET(slb); 573 esid = va >> ADDR_SR_SHFT; 574 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 575 576 for (i = 0; i < 64; i++) { 577 if (cache[i].slbe == (slbe | i)) 578 return; 579 } 580 581 entry.slbe = slbe; 582 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 583 if (large) 584 entry.slbv |= SLBV_L; 585 586 slb_insert_kernel(entry.slbe, entry.slbv); 587 } 588 #endif 589 590 static void 591 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 592 vm_offset_t kernelend) 593 { 594 register_t msr; 595 vm_paddr_t pa; 596 vm_offset_t size, off; 597 uint64_t pte_lo; 598 int i; 599 600 if (moea64_large_page_size == 0) 601 hw_direct_map = 0; 602 603 DISABLE_TRANS(msr); 604 if (hw_direct_map) { 605 LOCK_TABLE_WR(); 606 PMAP_LOCK(kernel_pmap); 607 for (i = 0; i < pregions_sz; i++) { 608 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 609 pregions[i].mr_size; pa += moea64_large_page_size) { 610 pte_lo = LPTE_M; 611 612 /* 613 * Set memory access as guarded if prefetch within 614 * the page could exit the available physmem area. 615 */ 616 if (pa & moea64_large_page_mask) { 617 pa &= moea64_large_page_mask; 618 pte_lo |= LPTE_G; 619 } 620 if (pa + moea64_large_page_size > 621 pregions[i].mr_start + pregions[i].mr_size) 622 pte_lo |= LPTE_G; 623 624 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 625 &moea64_pvo_kunmanaged, pa, pa, 626 pte_lo, PVO_WIRED | PVO_LARGE); 627 } 628 } 629 PMAP_UNLOCK(kernel_pmap); 630 UNLOCK_TABLE_WR(); 631 } else { 632 size = sizeof(struct pvo_head) * moea64_pteg_count; 633 off = (vm_offset_t)(moea64_pvo_table); 634 for (pa = off; pa < off + size; pa += PAGE_SIZE) 635 moea64_kenter(mmup, pa, pa); 636 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 637 off = (vm_offset_t)(moea64_bpvo_pool); 638 for (pa = off; pa < off + size; pa += PAGE_SIZE) 639 moea64_kenter(mmup, pa, pa); 640 641 /* 642 * Map certain important things, like ourselves. 643 * 644 * NOTE: We do not map the exception vector space. That code is 645 * used only in real mode, and leaving it unmapped allows us to 646 * catch NULL pointer deferences, instead of making NULL a valid 647 * address. 648 */ 649 650 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 651 pa += PAGE_SIZE) 652 moea64_kenter(mmup, pa, pa); 653 } 654 ENABLE_TRANS(msr); 655 } 656 657 void 658 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 659 { 660 int i, j; 661 vm_size_t physsz, hwphyssz; 662 663 #ifndef __powerpc64__ 664 /* We don't have a direct map since there is no BAT */ 665 hw_direct_map = 0; 666 667 /* Make sure battable is zero, since we have no BAT */ 668 for (i = 0; i < 16; i++) { 669 battable[i].batu = 0; 670 battable[i].batl = 0; 671 } 672 #else 673 moea64_probe_large_page(); 674 675 /* Use a direct map if we have large page support */ 676 if (moea64_large_page_size > 0) 677 hw_direct_map = 1; 678 else 679 hw_direct_map = 0; 680 #endif 681 682 /* Get physical memory regions from firmware */ 683 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 684 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 685 686 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 687 panic("moea64_bootstrap: phys_avail too small"); 688 689 phys_avail_count = 0; 690 physsz = 0; 691 hwphyssz = 0; 692 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 693 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 694 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 695 regions[i].mr_start + regions[i].mr_size, 696 regions[i].mr_size); 697 if (hwphyssz != 0 && 698 (physsz + regions[i].mr_size) >= hwphyssz) { 699 if (physsz < hwphyssz) { 700 phys_avail[j] = regions[i].mr_start; 701 phys_avail[j + 1] = regions[i].mr_start + 702 hwphyssz - physsz; 703 physsz = hwphyssz; 704 phys_avail_count++; 705 } 706 break; 707 } 708 phys_avail[j] = regions[i].mr_start; 709 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 710 phys_avail_count++; 711 physsz += regions[i].mr_size; 712 } 713 714 /* Check for overlap with the kernel and exception vectors */ 715 for (j = 0; j < 2*phys_avail_count; j+=2) { 716 if (phys_avail[j] < EXC_LAST) 717 phys_avail[j] += EXC_LAST; 718 719 if (kernelstart >= phys_avail[j] && 720 kernelstart < phys_avail[j+1]) { 721 if (kernelend < phys_avail[j+1]) { 722 phys_avail[2*phys_avail_count] = 723 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 724 phys_avail[2*phys_avail_count + 1] = 725 phys_avail[j+1]; 726 phys_avail_count++; 727 } 728 729 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 730 } 731 732 if (kernelend >= phys_avail[j] && 733 kernelend < phys_avail[j+1]) { 734 if (kernelstart > phys_avail[j]) { 735 phys_avail[2*phys_avail_count] = phys_avail[j]; 736 phys_avail[2*phys_avail_count + 1] = 737 kernelstart & ~PAGE_MASK; 738 phys_avail_count++; 739 } 740 741 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 742 } 743 } 744 745 physmem = btoc(physsz); 746 747 #ifdef PTEGCOUNT 748 moea64_pteg_count = PTEGCOUNT; 749 #else 750 moea64_pteg_count = 0x1000; 751 752 while (moea64_pteg_count < physmem) 753 moea64_pteg_count <<= 1; 754 755 moea64_pteg_count >>= 1; 756 #endif /* PTEGCOUNT */ 757 } 758 759 void 760 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 761 { 762 vm_size_t size; 763 register_t msr; 764 int i; 765 766 /* 767 * Set PTEG mask 768 */ 769 moea64_pteg_mask = moea64_pteg_count - 1; 770 771 /* 772 * Allocate pv/overflow lists. 773 */ 774 size = sizeof(struct pvo_head) * moea64_pteg_count; 775 776 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 777 PAGE_SIZE); 778 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 779 780 DISABLE_TRANS(msr); 781 for (i = 0; i < moea64_pteg_count; i++) 782 LIST_INIT(&moea64_pvo_table[i]); 783 ENABLE_TRANS(msr); 784 785 /* 786 * Initialize the lock that synchronizes access to the pteg and pvo 787 * tables. 788 */ 789 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 790 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 791 792 /* 793 * Initialise the unmanaged pvo pool. 794 */ 795 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 796 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 797 moea64_bpvo_pool_index = 0; 798 799 /* 800 * Make sure kernel vsid is allocated as well as VSID 0. 801 */ 802 #ifndef __powerpc64__ 803 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 804 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 805 moea64_vsid_bitmap[0] |= 1; 806 #endif 807 808 /* 809 * Initialize the kernel pmap (which is statically allocated). 810 */ 811 #ifdef __powerpc64__ 812 for (i = 0; i < 64; i++) { 813 pcpup->pc_slb[i].slbv = 0; 814 pcpup->pc_slb[i].slbe = 0; 815 } 816 #else 817 for (i = 0; i < 16; i++) 818 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 819 #endif 820 821 kernel_pmap->pmap_phys = kernel_pmap; 822 CPU_FILL(&kernel_pmap->pm_active); 823 LIST_INIT(&kernel_pmap->pmap_pvo); 824 825 PMAP_LOCK_INIT(kernel_pmap); 826 827 /* 828 * Now map in all the other buffers we allocated earlier 829 */ 830 831 moea64_setup_direct_map(mmup, kernelstart, kernelend); 832 } 833 834 void 835 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 836 { 837 ihandle_t mmui; 838 phandle_t chosen; 839 phandle_t mmu; 840 size_t sz; 841 int i; 842 vm_offset_t pa, va; 843 void *dpcpu; 844 845 /* 846 * Set up the Open Firmware pmap and add its mappings if not in real 847 * mode. 848 */ 849 850 chosen = OF_finddevice("/chosen"); 851 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 852 mmu = OF_instance_to_package(mmui); 853 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 854 sz = 0; 855 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 856 panic("moea64_bootstrap: too many ofw translations"); 857 858 if (sz > 0) 859 moea64_add_ofw_mappings(mmup, mmu, sz); 860 } 861 862 /* 863 * Calculate the last available physical address. 864 */ 865 for (i = 0; phys_avail[i + 2] != 0; i += 2) 866 ; 867 Maxmem = powerpc_btop(phys_avail[i + 1]); 868 869 /* 870 * Initialize MMU and remap early physical mappings 871 */ 872 MMU_CPU_BOOTSTRAP(mmup,0); 873 mtmsr(mfmsr() | PSL_DR | PSL_IR); 874 pmap_bootstrapped++; 875 bs_remap_earlyboot(); 876 877 /* 878 * Set the start and end of kva. 879 */ 880 virtual_avail = VM_MIN_KERNEL_ADDRESS; 881 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 882 883 /* 884 * Map the entire KVA range into the SLB. We must not fault there. 885 */ 886 #ifdef __powerpc64__ 887 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 888 moea64_bootstrap_slb_prefault(va, 0); 889 #endif 890 891 /* 892 * Figure out how far we can extend virtual_end into segment 16 893 * without running into existing mappings. Segment 16 is guaranteed 894 * to contain neither RAM nor devices (at least on Apple hardware), 895 * but will generally contain some OFW mappings we should not 896 * step on. 897 */ 898 899 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 900 PMAP_LOCK(kernel_pmap); 901 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 902 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 903 virtual_end += PAGE_SIZE; 904 PMAP_UNLOCK(kernel_pmap); 905 #endif 906 907 /* 908 * Allocate a kernel stack with a guard page for thread0 and map it 909 * into the kernel page map. 910 */ 911 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 912 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 913 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 914 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 915 thread0.td_kstack = va; 916 thread0.td_kstack_pages = KSTACK_PAGES; 917 for (i = 0; i < KSTACK_PAGES; i++) { 918 moea64_kenter(mmup, va, pa); 919 pa += PAGE_SIZE; 920 va += PAGE_SIZE; 921 } 922 923 /* 924 * Allocate virtual address space for the message buffer. 925 */ 926 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 927 msgbufp = (struct msgbuf *)virtual_avail; 928 va = virtual_avail; 929 virtual_avail += round_page(msgbufsize); 930 while (va < virtual_avail) { 931 moea64_kenter(mmup, va, pa); 932 pa += PAGE_SIZE; 933 va += PAGE_SIZE; 934 } 935 936 /* 937 * Allocate virtual address space for the dynamic percpu area. 938 */ 939 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 940 dpcpu = (void *)virtual_avail; 941 va = virtual_avail; 942 virtual_avail += DPCPU_SIZE; 943 while (va < virtual_avail) { 944 moea64_kenter(mmup, va, pa); 945 pa += PAGE_SIZE; 946 va += PAGE_SIZE; 947 } 948 dpcpu_init(dpcpu, 0); 949 950 /* 951 * Allocate some things for page zeroing. We put this directly 952 * in the page table, marked with LPTE_LOCKED, to avoid any 953 * of the PVO book-keeping or other parts of the VM system 954 * from even knowing that this hack exists. 955 */ 956 957 if (!hw_direct_map) { 958 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 959 MTX_DEF); 960 for (i = 0; i < 2; i++) { 961 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 962 virtual_end -= PAGE_SIZE; 963 964 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 965 966 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 967 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 968 LOCK_TABLE_RD(); 969 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 970 mmup, moea64_scratchpage_pvo[i]); 971 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 972 |= LPTE_LOCKED; 973 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 974 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 975 moea64_scratchpage_pvo[i]->pvo_vpn); 976 UNLOCK_TABLE_RD(); 977 } 978 } 979 } 980 981 /* 982 * Activate a user pmap. The pmap must be activated before its address 983 * space can be accessed in any way. 984 */ 985 void 986 moea64_activate(mmu_t mmu, struct thread *td) 987 { 988 pmap_t pm; 989 990 pm = &td->td_proc->p_vmspace->vm_pmap; 991 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 992 993 #ifdef __powerpc64__ 994 PCPU_SET(userslb, pm->pm_slb); 995 #else 996 PCPU_SET(curpmap, pm->pmap_phys); 997 #endif 998 } 999 1000 void 1001 moea64_deactivate(mmu_t mmu, struct thread *td) 1002 { 1003 pmap_t pm; 1004 1005 pm = &td->td_proc->p_vmspace->vm_pmap; 1006 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1007 #ifdef __powerpc64__ 1008 PCPU_SET(userslb, NULL); 1009 #else 1010 PCPU_SET(curpmap, NULL); 1011 #endif 1012 } 1013 1014 void 1015 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1016 { 1017 struct pvo_entry *pvo; 1018 uintptr_t pt; 1019 uint64_t vsid; 1020 int i, ptegidx; 1021 1022 LOCK_TABLE_WR(); 1023 PMAP_LOCK(pm); 1024 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1025 1026 if (pvo != NULL) { 1027 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1028 1029 if (wired) { 1030 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1031 pm->pm_stats.wired_count++; 1032 pvo->pvo_vaddr |= PVO_WIRED; 1033 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1034 } else { 1035 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1036 pm->pm_stats.wired_count--; 1037 pvo->pvo_vaddr &= ~PVO_WIRED; 1038 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1039 } 1040 1041 if (pt != -1) { 1042 /* Update wiring flag in page table. */ 1043 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1044 pvo->pvo_vpn); 1045 } else if (wired) { 1046 /* 1047 * If we are wiring the page, and it wasn't in the 1048 * page table before, add it. 1049 */ 1050 vsid = PVO_VSID(pvo); 1051 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1052 pvo->pvo_vaddr & PVO_LARGE); 1053 1054 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1055 1056 if (i >= 0) { 1057 PVO_PTEGIDX_CLR(pvo); 1058 PVO_PTEGIDX_SET(pvo, i); 1059 } 1060 } 1061 1062 } 1063 UNLOCK_TABLE_WR(); 1064 PMAP_UNLOCK(pm); 1065 } 1066 1067 /* 1068 * This goes through and sets the physical address of our 1069 * special scratch PTE to the PA we want to zero or copy. Because 1070 * of locking issues (this can get called in pvo_enter() by 1071 * the UMA allocator), we can't use most other utility functions here 1072 */ 1073 1074 static __inline 1075 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1076 1077 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1078 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1079 1080 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1081 ~(LPTE_WIMG | LPTE_RPGN); 1082 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1083 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1084 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1085 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1086 moea64_scratchpage_pvo[which]->pvo_vpn); 1087 isync(); 1088 } 1089 1090 void 1091 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1092 { 1093 vm_offset_t dst; 1094 vm_offset_t src; 1095 1096 dst = VM_PAGE_TO_PHYS(mdst); 1097 src = VM_PAGE_TO_PHYS(msrc); 1098 1099 if (hw_direct_map) { 1100 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1101 } else { 1102 mtx_lock(&moea64_scratchpage_mtx); 1103 1104 moea64_set_scratchpage_pa(mmu, 0, src); 1105 moea64_set_scratchpage_pa(mmu, 1, dst); 1106 1107 bcopy((void *)moea64_scratchpage_va[0], 1108 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1109 1110 mtx_unlock(&moea64_scratchpage_mtx); 1111 } 1112 } 1113 1114 void 1115 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1116 { 1117 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1118 1119 if (size + off > PAGE_SIZE) 1120 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1121 1122 if (hw_direct_map) { 1123 bzero((caddr_t)pa + off, size); 1124 } else { 1125 mtx_lock(&moea64_scratchpage_mtx); 1126 moea64_set_scratchpage_pa(mmu, 0, pa); 1127 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1128 mtx_unlock(&moea64_scratchpage_mtx); 1129 } 1130 } 1131 1132 /* 1133 * Zero a page of physical memory by temporarily mapping it 1134 */ 1135 void 1136 moea64_zero_page(mmu_t mmu, vm_page_t m) 1137 { 1138 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1139 vm_offset_t va, off; 1140 1141 if (!hw_direct_map) { 1142 mtx_lock(&moea64_scratchpage_mtx); 1143 1144 moea64_set_scratchpage_pa(mmu, 0, pa); 1145 va = moea64_scratchpage_va[0]; 1146 } else { 1147 va = pa; 1148 } 1149 1150 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1151 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1152 1153 if (!hw_direct_map) 1154 mtx_unlock(&moea64_scratchpage_mtx); 1155 } 1156 1157 void 1158 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1159 { 1160 1161 moea64_zero_page(mmu, m); 1162 } 1163 1164 /* 1165 * Map the given physical page at the specified virtual address in the 1166 * target pmap with the protection requested. If specified the page 1167 * will be wired down. 1168 */ 1169 1170 void 1171 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1172 vm_prot_t prot, boolean_t wired) 1173 { 1174 struct pvo_head *pvo_head; 1175 uma_zone_t zone; 1176 vm_page_t pg; 1177 uint64_t pte_lo; 1178 u_int pvo_flags; 1179 int error; 1180 1181 if (!moea64_initialized) { 1182 pvo_head = &moea64_pvo_kunmanaged; 1183 pg = NULL; 1184 zone = moea64_upvo_zone; 1185 pvo_flags = 0; 1186 } else { 1187 pvo_head = vm_page_to_pvoh(m); 1188 pg = m; 1189 zone = moea64_mpvo_zone; 1190 pvo_flags = PVO_MANAGED; 1191 } 1192 1193 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1194 VM_OBJECT_LOCKED(m->object), 1195 ("moea64_enter: page %p is not busy", m)); 1196 1197 /* XXX change the pvo head for fake pages */ 1198 if ((m->oflags & VPO_UNMANAGED) != 0) { 1199 pvo_flags &= ~PVO_MANAGED; 1200 pvo_head = &moea64_pvo_kunmanaged; 1201 zone = moea64_upvo_zone; 1202 } 1203 1204 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1205 1206 if (prot & VM_PROT_WRITE) { 1207 pte_lo |= LPTE_BW; 1208 if (pmap_bootstrapped && 1209 (m->oflags & VPO_UNMANAGED) == 0) 1210 vm_page_aflag_set(m, PGA_WRITEABLE); 1211 } else 1212 pte_lo |= LPTE_BR; 1213 1214 if ((prot & VM_PROT_EXECUTE) == 0) 1215 pte_lo |= LPTE_NOEXEC; 1216 1217 if (wired) 1218 pvo_flags |= PVO_WIRED; 1219 1220 LOCK_TABLE_WR(); 1221 PMAP_LOCK(pmap); 1222 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1223 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1224 PMAP_UNLOCK(pmap); 1225 UNLOCK_TABLE_WR(); 1226 1227 /* 1228 * Flush the page from the instruction cache if this page is 1229 * mapped executable and cacheable. 1230 */ 1231 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1232 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1233 vm_page_aflag_set(m, PGA_EXECUTABLE); 1234 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1235 } 1236 } 1237 1238 static void 1239 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1240 vm_size_t sz) 1241 { 1242 1243 /* 1244 * This is much trickier than on older systems because 1245 * we can't sync the icache on physical addresses directly 1246 * without a direct map. Instead we check a couple of cases 1247 * where the memory is already mapped in and, failing that, 1248 * use the same trick we use for page zeroing to create 1249 * a temporary mapping for this physical address. 1250 */ 1251 1252 if (!pmap_bootstrapped) { 1253 /* 1254 * If PMAP is not bootstrapped, we are likely to be 1255 * in real mode. 1256 */ 1257 __syncicache((void *)pa, sz); 1258 } else if (pmap == kernel_pmap) { 1259 __syncicache((void *)va, sz); 1260 } else if (hw_direct_map) { 1261 __syncicache((void *)pa, sz); 1262 } else { 1263 /* Use the scratch page to set up a temp mapping */ 1264 1265 mtx_lock(&moea64_scratchpage_mtx); 1266 1267 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1268 __syncicache((void *)(moea64_scratchpage_va[1] + 1269 (va & ADDR_POFF)), sz); 1270 1271 mtx_unlock(&moea64_scratchpage_mtx); 1272 } 1273 } 1274 1275 /* 1276 * Maps a sequence of resident pages belonging to the same object. 1277 * The sequence begins with the given page m_start. This page is 1278 * mapped at the given virtual address start. Each subsequent page is 1279 * mapped at a virtual address that is offset from start by the same 1280 * amount as the page is offset from m_start within the object. The 1281 * last page in the sequence is the page with the largest offset from 1282 * m_start that can be mapped at a virtual address less than the given 1283 * virtual address end. Not every virtual page between start and end 1284 * is mapped; only those for which a resident page exists with the 1285 * corresponding offset from m_start are mapped. 1286 */ 1287 void 1288 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1289 vm_page_t m_start, vm_prot_t prot) 1290 { 1291 vm_page_t m; 1292 vm_pindex_t diff, psize; 1293 1294 psize = atop(end - start); 1295 m = m_start; 1296 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1297 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1298 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1299 m = TAILQ_NEXT(m, listq); 1300 } 1301 } 1302 1303 void 1304 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1305 vm_prot_t prot) 1306 { 1307 1308 moea64_enter(mmu, pm, va, m, 1309 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1310 } 1311 1312 vm_paddr_t 1313 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1314 { 1315 struct pvo_entry *pvo; 1316 vm_paddr_t pa; 1317 1318 LOCK_TABLE_RD(); 1319 PMAP_LOCK(pm); 1320 pvo = moea64_pvo_find_va(pm, va); 1321 if (pvo == NULL) 1322 pa = 0; 1323 else 1324 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1325 (va - PVO_VADDR(pvo)); 1326 UNLOCK_TABLE_RD(); 1327 PMAP_UNLOCK(pm); 1328 return (pa); 1329 } 1330 1331 /* 1332 * Atomically extract and hold the physical page with the given 1333 * pmap and virtual address pair if that mapping permits the given 1334 * protection. 1335 */ 1336 1337 extern int pa_tryrelock_restart; 1338 1339 static int 1340 vm_page_pa_tryrelock_moea64(pmap_t pmap, vm_paddr_t pa, vm_paddr_t *locked) 1341 { 1342 /* 1343 * This is a duplicate of vm_page_pa_tryrelock(), but with proper 1344 * handling of the table lock 1345 */ 1346 vm_paddr_t lockpa; 1347 1348 lockpa = *locked; 1349 *locked = pa; 1350 if (lockpa) { 1351 PA_LOCK_ASSERT(lockpa, MA_OWNED); 1352 if (PA_LOCKPTR(pa) == PA_LOCKPTR(lockpa)) 1353 return (0); 1354 PA_UNLOCK(lockpa); 1355 } 1356 if (PA_TRYLOCK(pa)) 1357 return (0); 1358 UNLOCK_TABLE_RD(); 1359 PMAP_UNLOCK(pmap); 1360 atomic_add_int(&pa_tryrelock_restart, 1); 1361 PA_LOCK(pa); 1362 LOCK_TABLE_RD(); 1363 PMAP_LOCK(pmap); 1364 return (EAGAIN); 1365 } 1366 1367 vm_page_t 1368 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1369 { 1370 struct pvo_entry *pvo; 1371 vm_page_t m; 1372 vm_paddr_t pa; 1373 1374 m = NULL; 1375 pa = 0; 1376 LOCK_TABLE_RD(); 1377 PMAP_LOCK(pmap); 1378 retry: 1379 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1380 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1381 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1382 (prot & VM_PROT_WRITE) == 0)) { 1383 if (vm_page_pa_tryrelock_moea64(pmap, 1384 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1385 goto retry; 1386 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1387 vm_page_hold(m); 1388 } 1389 PA_UNLOCK_COND(pa); 1390 UNLOCK_TABLE_RD(); 1391 PMAP_UNLOCK(pmap); 1392 return (m); 1393 } 1394 1395 static mmu_t installed_mmu; 1396 1397 static void * 1398 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1399 { 1400 /* 1401 * This entire routine is a horrible hack to avoid bothering kmem 1402 * for new KVA addresses. Because this can get called from inside 1403 * kmem allocation routines, calling kmem for a new address here 1404 * can lead to multiply locking non-recursive mutexes. 1405 */ 1406 vm_offset_t va; 1407 1408 vm_page_t m; 1409 int pflags, needed_lock; 1410 1411 *flags = UMA_SLAB_PRIV; 1412 needed_lock = !PMAP_LOCKED(kernel_pmap); 1413 1414 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1415 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1416 else 1417 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1418 if (wait & M_ZERO) 1419 pflags |= VM_ALLOC_ZERO; 1420 1421 for (;;) { 1422 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1423 if (m == NULL) { 1424 if (wait & M_NOWAIT) 1425 return (NULL); 1426 VM_WAIT; 1427 } else 1428 break; 1429 } 1430 1431 va = VM_PAGE_TO_PHYS(m); 1432 1433 LOCK_TABLE_WR(); 1434 if (needed_lock) 1435 PMAP_LOCK(kernel_pmap); 1436 1437 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1438 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1439 PVO_WIRED | PVO_BOOTSTRAP); 1440 1441 if (needed_lock) 1442 PMAP_UNLOCK(kernel_pmap); 1443 UNLOCK_TABLE_WR(); 1444 1445 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1446 bzero((void *)va, PAGE_SIZE); 1447 1448 return (void *)va; 1449 } 1450 1451 extern int elf32_nxstack; 1452 1453 void 1454 moea64_init(mmu_t mmu) 1455 { 1456 1457 CTR0(KTR_PMAP, "moea64_init"); 1458 1459 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1460 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1461 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1462 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1463 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1464 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1465 1466 if (!hw_direct_map) { 1467 installed_mmu = mmu; 1468 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1469 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1470 } 1471 1472 #ifdef COMPAT_FREEBSD32 1473 elf32_nxstack = 1; 1474 #endif 1475 1476 moea64_initialized = TRUE; 1477 } 1478 1479 boolean_t 1480 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1481 { 1482 1483 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1484 ("moea64_is_referenced: page %p is not managed", m)); 1485 return (moea64_query_bit(mmu, m, PTE_REF)); 1486 } 1487 1488 boolean_t 1489 moea64_is_modified(mmu_t mmu, vm_page_t m) 1490 { 1491 1492 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1493 ("moea64_is_modified: page %p is not managed", m)); 1494 1495 /* 1496 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1497 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1498 * is clear, no PTEs can have LPTE_CHG set. 1499 */ 1500 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1501 if ((m->oflags & VPO_BUSY) == 0 && 1502 (m->aflags & PGA_WRITEABLE) == 0) 1503 return (FALSE); 1504 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1505 } 1506 1507 boolean_t 1508 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1509 { 1510 struct pvo_entry *pvo; 1511 boolean_t rv; 1512 1513 LOCK_TABLE_RD(); 1514 PMAP_LOCK(pmap); 1515 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1516 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1517 PMAP_UNLOCK(pmap); 1518 UNLOCK_TABLE_RD(); 1519 return (rv); 1520 } 1521 1522 void 1523 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1524 { 1525 1526 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1527 ("moea64_clear_reference: page %p is not managed", m)); 1528 moea64_clear_bit(mmu, m, LPTE_REF); 1529 } 1530 1531 void 1532 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1533 { 1534 1535 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1536 ("moea64_clear_modify: page %p is not managed", m)); 1537 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1538 KASSERT((m->oflags & VPO_BUSY) == 0, 1539 ("moea64_clear_modify: page %p is busy", m)); 1540 1541 /* 1542 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1543 * set. If the object containing the page is locked and the page is 1544 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1545 */ 1546 if ((m->aflags & PGA_WRITEABLE) == 0) 1547 return; 1548 moea64_clear_bit(mmu, m, LPTE_CHG); 1549 } 1550 1551 /* 1552 * Clear the write and modified bits in each of the given page's mappings. 1553 */ 1554 void 1555 moea64_remove_write(mmu_t mmu, vm_page_t m) 1556 { 1557 struct pvo_entry *pvo; 1558 uintptr_t pt; 1559 pmap_t pmap; 1560 uint64_t lo = 0; 1561 1562 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1563 ("moea64_remove_write: page %p is not managed", m)); 1564 1565 /* 1566 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1567 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1568 * is clear, no page table entries need updating. 1569 */ 1570 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1571 if ((m->oflags & VPO_BUSY) == 0 && 1572 (m->aflags & PGA_WRITEABLE) == 0) 1573 return; 1574 powerpc_sync(); 1575 LOCK_TABLE_RD(); 1576 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1577 pmap = pvo->pvo_pmap; 1578 PMAP_LOCK(pmap); 1579 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1580 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1581 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1582 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1583 if (pt != -1) { 1584 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1585 lo |= pvo->pvo_pte.lpte.pte_lo; 1586 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1587 MOEA64_PTE_CHANGE(mmu, pt, 1588 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1589 if (pvo->pvo_pmap == kernel_pmap) 1590 isync(); 1591 } 1592 } 1593 if ((lo & LPTE_CHG) != 0) 1594 vm_page_dirty(m); 1595 PMAP_UNLOCK(pmap); 1596 } 1597 UNLOCK_TABLE_RD(); 1598 vm_page_aflag_clear(m, PGA_WRITEABLE); 1599 } 1600 1601 /* 1602 * moea64_ts_referenced: 1603 * 1604 * Return a count of reference bits for a page, clearing those bits. 1605 * It is not necessary for every reference bit to be cleared, but it 1606 * is necessary that 0 only be returned when there are truly no 1607 * reference bits set. 1608 * 1609 * XXX: The exact number of bits to check and clear is a matter that 1610 * should be tested and standardized at some point in the future for 1611 * optimal aging of shared pages. 1612 */ 1613 boolean_t 1614 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1615 { 1616 1617 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1618 ("moea64_ts_referenced: page %p is not managed", m)); 1619 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1620 } 1621 1622 /* 1623 * Modify the WIMG settings of all mappings for a page. 1624 */ 1625 void 1626 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1627 { 1628 struct pvo_entry *pvo; 1629 struct pvo_head *pvo_head; 1630 uintptr_t pt; 1631 pmap_t pmap; 1632 uint64_t lo; 1633 1634 if ((m->oflags & VPO_UNMANAGED) != 0) { 1635 m->md.mdpg_cache_attrs = ma; 1636 return; 1637 } 1638 1639 pvo_head = vm_page_to_pvoh(m); 1640 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1641 LOCK_TABLE_RD(); 1642 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1643 pmap = pvo->pvo_pmap; 1644 PMAP_LOCK(pmap); 1645 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1646 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1647 pvo->pvo_pte.lpte.pte_lo |= lo; 1648 if (pt != -1) { 1649 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1650 pvo->pvo_vpn); 1651 if (pvo->pvo_pmap == kernel_pmap) 1652 isync(); 1653 } 1654 PMAP_UNLOCK(pmap); 1655 } 1656 UNLOCK_TABLE_RD(); 1657 m->md.mdpg_cache_attrs = ma; 1658 } 1659 1660 /* 1661 * Map a wired page into kernel virtual address space. 1662 */ 1663 void 1664 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1665 { 1666 uint64_t pte_lo; 1667 int error; 1668 1669 pte_lo = moea64_calc_wimg(pa, ma); 1670 1671 LOCK_TABLE_WR(); 1672 PMAP_LOCK(kernel_pmap); 1673 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1674 &moea64_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1675 PMAP_UNLOCK(kernel_pmap); 1676 UNLOCK_TABLE_WR(); 1677 1678 if (error != 0 && error != ENOENT) 1679 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1680 pa, error); 1681 } 1682 1683 void 1684 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1685 { 1686 1687 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1688 } 1689 1690 /* 1691 * Extract the physical page address associated with the given kernel virtual 1692 * address. 1693 */ 1694 vm_offset_t 1695 moea64_kextract(mmu_t mmu, vm_offset_t va) 1696 { 1697 struct pvo_entry *pvo; 1698 vm_paddr_t pa; 1699 1700 /* 1701 * Shortcut the direct-mapped case when applicable. We never put 1702 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1703 */ 1704 if (va < VM_MIN_KERNEL_ADDRESS) 1705 return (va); 1706 1707 LOCK_TABLE_RD(); 1708 PMAP_LOCK(kernel_pmap); 1709 pvo = moea64_pvo_find_va(kernel_pmap, va); 1710 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1711 va)); 1712 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1713 UNLOCK_TABLE_RD(); 1714 PMAP_UNLOCK(kernel_pmap); 1715 return (pa); 1716 } 1717 1718 /* 1719 * Remove a wired page from kernel virtual address space. 1720 */ 1721 void 1722 moea64_kremove(mmu_t mmu, vm_offset_t va) 1723 { 1724 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1725 } 1726 1727 /* 1728 * Map a range of physical addresses into kernel virtual address space. 1729 * 1730 * The value passed in *virt is a suggested virtual address for the mapping. 1731 * Architectures which can support a direct-mapped physical to virtual region 1732 * can return the appropriate address within that region, leaving '*virt' 1733 * unchanged. We cannot and therefore do not; *virt is updated with the 1734 * first usable address after the mapped region. 1735 */ 1736 vm_offset_t 1737 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1738 vm_offset_t pa_end, int prot) 1739 { 1740 vm_offset_t sva, va; 1741 1742 sva = *virt; 1743 va = sva; 1744 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1745 moea64_kenter(mmu, va, pa_start); 1746 *virt = va; 1747 1748 return (sva); 1749 } 1750 1751 /* 1752 * Returns true if the pmap's pv is one of the first 1753 * 16 pvs linked to from this page. This count may 1754 * be changed upwards or downwards in the future; it 1755 * is only necessary that true be returned for a small 1756 * subset of pmaps for proper page aging. 1757 */ 1758 boolean_t 1759 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1760 { 1761 int loops; 1762 struct pvo_entry *pvo; 1763 boolean_t rv; 1764 1765 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1766 ("moea64_page_exists_quick: page %p is not managed", m)); 1767 loops = 0; 1768 rv = FALSE; 1769 LOCK_TABLE_RD(); 1770 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1771 if (pvo->pvo_pmap == pmap) { 1772 rv = TRUE; 1773 break; 1774 } 1775 if (++loops >= 16) 1776 break; 1777 } 1778 UNLOCK_TABLE_RD(); 1779 return (rv); 1780 } 1781 1782 /* 1783 * Return the number of managed mappings to the given physical page 1784 * that are wired. 1785 */ 1786 int 1787 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1788 { 1789 struct pvo_entry *pvo; 1790 int count; 1791 1792 count = 0; 1793 if ((m->oflags & VPO_UNMANAGED) != 0) 1794 return (count); 1795 LOCK_TABLE_RD(); 1796 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1797 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1798 count++; 1799 UNLOCK_TABLE_RD(); 1800 return (count); 1801 } 1802 1803 static uintptr_t moea64_vsidcontext; 1804 1805 uintptr_t 1806 moea64_get_unique_vsid(void) { 1807 u_int entropy; 1808 register_t hash; 1809 uint32_t mask; 1810 int i; 1811 1812 entropy = 0; 1813 __asm __volatile("mftb %0" : "=r"(entropy)); 1814 1815 mtx_lock(&moea64_slb_mutex); 1816 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1817 u_int n; 1818 1819 /* 1820 * Create a new value by mutiplying by a prime and adding in 1821 * entropy from the timebase register. This is to make the 1822 * VSID more random so that the PT hash function collides 1823 * less often. (Note that the prime casues gcc to do shifts 1824 * instead of a multiply.) 1825 */ 1826 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1827 hash = moea64_vsidcontext & (NVSIDS - 1); 1828 if (hash == 0) /* 0 is special, avoid it */ 1829 continue; 1830 n = hash >> 5; 1831 mask = 1 << (hash & (VSID_NBPW - 1)); 1832 hash = (moea64_vsidcontext & VSID_HASHMASK); 1833 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1834 /* anything free in this bucket? */ 1835 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1836 entropy = (moea64_vsidcontext >> 20); 1837 continue; 1838 } 1839 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1840 mask = 1 << i; 1841 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1842 hash |= i; 1843 } 1844 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1845 ("Allocating in-use VSID %#zx\n", hash)); 1846 moea64_vsid_bitmap[n] |= mask; 1847 mtx_unlock(&moea64_slb_mutex); 1848 return (hash); 1849 } 1850 1851 mtx_unlock(&moea64_slb_mutex); 1852 panic("%s: out of segments",__func__); 1853 } 1854 1855 #ifdef __powerpc64__ 1856 void 1857 moea64_pinit(mmu_t mmu, pmap_t pmap) 1858 { 1859 PMAP_LOCK_INIT(pmap); 1860 LIST_INIT(&pmap->pmap_pvo); 1861 1862 pmap->pm_slb_tree_root = slb_alloc_tree(); 1863 pmap->pm_slb = slb_alloc_user_cache(); 1864 pmap->pm_slb_len = 0; 1865 } 1866 #else 1867 void 1868 moea64_pinit(mmu_t mmu, pmap_t pmap) 1869 { 1870 int i; 1871 uint32_t hash; 1872 1873 PMAP_LOCK_INIT(pmap); 1874 LIST_INIT(&pmap->pmap_pvo); 1875 1876 if (pmap_bootstrapped) 1877 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1878 (vm_offset_t)pmap); 1879 else 1880 pmap->pmap_phys = pmap; 1881 1882 /* 1883 * Allocate some segment registers for this pmap. 1884 */ 1885 hash = moea64_get_unique_vsid(); 1886 1887 for (i = 0; i < 16; i++) 1888 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1889 1890 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1891 } 1892 #endif 1893 1894 /* 1895 * Initialize the pmap associated with process 0. 1896 */ 1897 void 1898 moea64_pinit0(mmu_t mmu, pmap_t pm) 1899 { 1900 moea64_pinit(mmu, pm); 1901 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1902 } 1903 1904 /* 1905 * Set the physical protection on the specified range of this map as requested. 1906 */ 1907 static void 1908 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1909 { 1910 uintptr_t pt; 1911 struct vm_page *pg; 1912 uint64_t oldlo; 1913 1914 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1915 1916 /* 1917 * Grab the PTE pointer before we diddle with the cached PTE 1918 * copy. 1919 */ 1920 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1921 1922 /* 1923 * Change the protection of the page. 1924 */ 1925 oldlo = pvo->pvo_pte.lpte.pte_lo; 1926 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1927 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1928 if ((prot & VM_PROT_EXECUTE) == 0) 1929 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1930 if (prot & VM_PROT_WRITE) 1931 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1932 else 1933 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1934 1935 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1936 1937 /* 1938 * If the PVO is in the page table, update that pte as well. 1939 */ 1940 if (pt != -1) 1941 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1942 pvo->pvo_vpn); 1943 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1944 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1945 if ((pg->oflags & VPO_UNMANAGED) == 0) 1946 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1947 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1948 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1949 } 1950 1951 /* 1952 * Update vm about the REF/CHG bits if the page is managed and we have 1953 * removed write access. 1954 */ 1955 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1956 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) { 1957 if (pg != NULL) { 1958 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1959 vm_page_dirty(pg); 1960 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1961 vm_page_aflag_set(pg, PGA_REFERENCED); 1962 } 1963 } 1964 } 1965 1966 void 1967 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1968 vm_prot_t prot) 1969 { 1970 struct pvo_entry *pvo, *tpvo; 1971 1972 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1973 sva, eva, prot); 1974 1975 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1976 ("moea64_protect: non current pmap")); 1977 1978 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1979 moea64_remove(mmu, pm, sva, eva); 1980 return; 1981 } 1982 1983 LOCK_TABLE_RD(); 1984 PMAP_LOCK(pm); 1985 if ((eva - sva)/PAGE_SIZE < pm->pm_stats.resident_count) { 1986 while (sva < eva) { 1987 #ifdef __powerpc64__ 1988 if (pm != kernel_pmap && 1989 user_va_to_slb_entry(pm, sva) == NULL) { 1990 sva = roundup2(sva + 1, SEGMENT_LENGTH); 1991 continue; 1992 } 1993 #endif 1994 pvo = moea64_pvo_find_va(pm, sva); 1995 if (pvo != NULL) 1996 moea64_pvo_protect(mmu, pm, pvo, prot); 1997 sva += PAGE_SIZE; 1998 } 1999 } else { 2000 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 2001 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 2002 continue; 2003 moea64_pvo_protect(mmu, pm, pvo, prot); 2004 } 2005 } 2006 UNLOCK_TABLE_RD(); 2007 PMAP_UNLOCK(pm); 2008 } 2009 2010 /* 2011 * Map a list of wired pages into kernel virtual address space. This is 2012 * intended for temporary mappings which do not need page modification or 2013 * references recorded. Existing mappings in the region are overwritten. 2014 */ 2015 void 2016 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2017 { 2018 while (count-- > 0) { 2019 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2020 va += PAGE_SIZE; 2021 m++; 2022 } 2023 } 2024 2025 /* 2026 * Remove page mappings from kernel virtual address space. Intended for 2027 * temporary mappings entered by moea64_qenter. 2028 */ 2029 void 2030 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2031 { 2032 while (count-- > 0) { 2033 moea64_kremove(mmu, va); 2034 va += PAGE_SIZE; 2035 } 2036 } 2037 2038 void 2039 moea64_release_vsid(uint64_t vsid) 2040 { 2041 int idx, mask; 2042 2043 mtx_lock(&moea64_slb_mutex); 2044 idx = vsid & (NVSIDS-1); 2045 mask = 1 << (idx % VSID_NBPW); 2046 idx /= VSID_NBPW; 2047 KASSERT(moea64_vsid_bitmap[idx] & mask, 2048 ("Freeing unallocated VSID %#jx", vsid)); 2049 moea64_vsid_bitmap[idx] &= ~mask; 2050 mtx_unlock(&moea64_slb_mutex); 2051 } 2052 2053 2054 void 2055 moea64_release(mmu_t mmu, pmap_t pmap) 2056 { 2057 2058 /* 2059 * Free segment registers' VSIDs 2060 */ 2061 #ifdef __powerpc64__ 2062 slb_free_tree(pmap); 2063 slb_free_user_cache(pmap->pm_slb); 2064 #else 2065 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2066 2067 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2068 #endif 2069 2070 PMAP_LOCK_DESTROY(pmap); 2071 } 2072 2073 /* 2074 * Remove all pages mapped by the specified pmap 2075 */ 2076 void 2077 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2078 { 2079 struct pvo_entry *pvo, *tpvo; 2080 2081 LOCK_TABLE_WR(); 2082 PMAP_LOCK(pm); 2083 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 2084 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2085 moea64_pvo_remove(mmu, pvo); 2086 } 2087 UNLOCK_TABLE_WR(); 2088 PMAP_UNLOCK(pm); 2089 } 2090 2091 /* 2092 * Remove the given range of addresses from the specified map. 2093 */ 2094 void 2095 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2096 { 2097 struct pvo_entry *pvo, *tpvo; 2098 2099 /* 2100 * Perform an unsynchronized read. This is, however, safe. 2101 */ 2102 if (pm->pm_stats.resident_count == 0) 2103 return; 2104 2105 LOCK_TABLE_WR(); 2106 PMAP_LOCK(pm); 2107 if ((eva - sva)/PAGE_SIZE < pm->pm_stats.resident_count) { 2108 while (sva < eva) { 2109 #ifdef __powerpc64__ 2110 if (pm != kernel_pmap && 2111 user_va_to_slb_entry(pm, sva) == NULL) { 2112 sva = roundup2(sva + 1, SEGMENT_LENGTH); 2113 continue; 2114 } 2115 #endif 2116 pvo = moea64_pvo_find_va(pm, sva); 2117 if (pvo != NULL) 2118 moea64_pvo_remove(mmu, pvo); 2119 sva += PAGE_SIZE; 2120 } 2121 } else { 2122 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 2123 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 2124 continue; 2125 moea64_pvo_remove(mmu, pvo); 2126 } 2127 } 2128 UNLOCK_TABLE_WR(); 2129 PMAP_UNLOCK(pm); 2130 } 2131 2132 /* 2133 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2134 * will reflect changes in pte's back to the vm_page. 2135 */ 2136 void 2137 moea64_remove_all(mmu_t mmu, vm_page_t m) 2138 { 2139 struct pvo_entry *pvo, *next_pvo; 2140 pmap_t pmap; 2141 2142 LOCK_TABLE_WR(); 2143 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2144 pmap = pvo->pvo_pmap; 2145 PMAP_LOCK(pmap); 2146 moea64_pvo_remove(mmu, pvo); 2147 PMAP_UNLOCK(pmap); 2148 } 2149 UNLOCK_TABLE_WR(); 2150 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2151 vm_page_dirty(m); 2152 vm_page_aflag_clear(m, PGA_WRITEABLE); 2153 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2154 } 2155 2156 /* 2157 * Allocate a physical page of memory directly from the phys_avail map. 2158 * Can only be called from moea64_bootstrap before avail start and end are 2159 * calculated. 2160 */ 2161 vm_offset_t 2162 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2163 { 2164 vm_offset_t s, e; 2165 int i, j; 2166 2167 size = round_page(size); 2168 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2169 if (align != 0) 2170 s = (phys_avail[i] + align - 1) & ~(align - 1); 2171 else 2172 s = phys_avail[i]; 2173 e = s + size; 2174 2175 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2176 continue; 2177 2178 if (s + size > platform_real_maxaddr()) 2179 continue; 2180 2181 if (s == phys_avail[i]) { 2182 phys_avail[i] += size; 2183 } else if (e == phys_avail[i + 1]) { 2184 phys_avail[i + 1] -= size; 2185 } else { 2186 for (j = phys_avail_count * 2; j > i; j -= 2) { 2187 phys_avail[j] = phys_avail[j - 2]; 2188 phys_avail[j + 1] = phys_avail[j - 1]; 2189 } 2190 2191 phys_avail[i + 3] = phys_avail[i + 1]; 2192 phys_avail[i + 1] = s; 2193 phys_avail[i + 2] = e; 2194 phys_avail_count++; 2195 } 2196 2197 return (s); 2198 } 2199 panic("moea64_bootstrap_alloc: could not allocate memory"); 2200 } 2201 2202 static int 2203 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2204 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2205 uint64_t pte_lo, int flags) 2206 { 2207 struct pvo_entry *pvo; 2208 uint64_t vsid; 2209 int first; 2210 u_int ptegidx; 2211 int i; 2212 int bootstrap; 2213 2214 /* 2215 * One nasty thing that can happen here is that the UMA calls to 2216 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2217 * which calls UMA... 2218 * 2219 * We break the loop by detecting recursion and allocating out of 2220 * the bootstrap pool. 2221 */ 2222 2223 first = 0; 2224 bootstrap = (flags & PVO_BOOTSTRAP); 2225 2226 if (!moea64_initialized) 2227 bootstrap = 1; 2228 2229 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2230 rw_assert(&moea64_table_lock, RA_WLOCKED); 2231 2232 /* 2233 * Compute the PTE Group index. 2234 */ 2235 va &= ~ADDR_POFF; 2236 vsid = va_to_vsid(pm, va); 2237 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2238 2239 /* 2240 * Remove any existing mapping for this page. Reuse the pvo entry if 2241 * there is a mapping. 2242 */ 2243 moea64_pvo_enter_calls++; 2244 2245 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2246 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2247 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2248 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2249 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2250 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2251 /* Re-insert if spilled */ 2252 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2253 &pvo->pvo_pte.lpte); 2254 if (i >= 0) 2255 PVO_PTEGIDX_SET(pvo, i); 2256 moea64_pte_overflow--; 2257 } 2258 return (0); 2259 } 2260 moea64_pvo_remove(mmu, pvo); 2261 break; 2262 } 2263 } 2264 2265 /* 2266 * If we aren't overwriting a mapping, try to allocate. 2267 */ 2268 if (bootstrap) { 2269 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2270 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2271 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2272 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2273 } 2274 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2275 moea64_bpvo_pool_index++; 2276 bootstrap = 1; 2277 } else { 2278 /* 2279 * Note: drop the table lock around the UMA allocation in 2280 * case the UMA allocator needs to manipulate the page 2281 * table. The mapping we are working with is already 2282 * protected by the PMAP lock. 2283 */ 2284 pvo = uma_zalloc(zone, M_NOWAIT); 2285 } 2286 2287 if (pvo == NULL) 2288 return (ENOMEM); 2289 2290 moea64_pvo_entries++; 2291 pvo->pvo_vaddr = va; 2292 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2293 | (vsid << 16); 2294 pvo->pvo_pmap = pm; 2295 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2296 pvo->pvo_vaddr &= ~ADDR_POFF; 2297 2298 if (flags & PVO_WIRED) 2299 pvo->pvo_vaddr |= PVO_WIRED; 2300 if (pvo_head != &moea64_pvo_kunmanaged) 2301 pvo->pvo_vaddr |= PVO_MANAGED; 2302 if (bootstrap) 2303 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2304 if (flags & PVO_LARGE) 2305 pvo->pvo_vaddr |= PVO_LARGE; 2306 2307 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2308 (uint64_t)(pa) | pte_lo, flags); 2309 2310 /* 2311 * Add to pmap list 2312 */ 2313 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink); 2314 2315 /* 2316 * Remember if the list was empty and therefore will be the first 2317 * item. 2318 */ 2319 if (LIST_FIRST(pvo_head) == NULL) 2320 first = 1; 2321 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2322 2323 if (pvo->pvo_vaddr & PVO_WIRED) { 2324 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2325 pm->pm_stats.wired_count++; 2326 } 2327 pm->pm_stats.resident_count++; 2328 2329 /* 2330 * We hope this succeeds but it isn't required. 2331 */ 2332 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2333 if (i >= 0) { 2334 PVO_PTEGIDX_SET(pvo, i); 2335 } else { 2336 panic("moea64_pvo_enter: overflow"); 2337 moea64_pte_overflow++; 2338 } 2339 2340 if (pm == kernel_pmap) 2341 isync(); 2342 2343 #ifdef __powerpc64__ 2344 /* 2345 * Make sure all our bootstrap mappings are in the SLB as soon 2346 * as virtual memory is switched on. 2347 */ 2348 if (!pmap_bootstrapped) 2349 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2350 #endif 2351 2352 return (first ? ENOENT : 0); 2353 } 2354 2355 static void 2356 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2357 { 2358 struct vm_page *pg; 2359 uintptr_t pt; 2360 2361 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2362 rw_assert(&moea64_table_lock, RA_WLOCKED); 2363 2364 /* 2365 * If there is an active pte entry, we need to deactivate it (and 2366 * save the ref & cfg bits). 2367 */ 2368 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2369 if (pt != -1) { 2370 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2371 PVO_PTEGIDX_CLR(pvo); 2372 } else { 2373 moea64_pte_overflow--; 2374 } 2375 2376 /* 2377 * Update our statistics. 2378 */ 2379 pvo->pvo_pmap->pm_stats.resident_count--; 2380 if (pvo->pvo_vaddr & PVO_WIRED) 2381 pvo->pvo_pmap->pm_stats.wired_count--; 2382 2383 /* 2384 * Remove this PVO from the PV and pmap lists. 2385 */ 2386 LIST_REMOVE(pvo, pvo_vlink); 2387 LIST_REMOVE(pvo, pvo_plink); 2388 2389 /* 2390 * Remove this from the overflow list and return it to the pool 2391 * if we aren't going to reuse it. 2392 */ 2393 LIST_REMOVE(pvo, pvo_olink); 2394 2395 /* 2396 * Update vm about the REF/CHG bits if the page is managed. 2397 */ 2398 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2399 2400 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2401 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2402 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2403 vm_page_dirty(pg); 2404 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2405 vm_page_aflag_set(pg, PGA_REFERENCED); 2406 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2407 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2408 } 2409 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2410 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2411 } 2412 2413 moea64_pvo_entries--; 2414 moea64_pvo_remove_calls++; 2415 2416 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2417 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2418 moea64_upvo_zone, pvo); 2419 } 2420 2421 static struct pvo_entry * 2422 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2423 { 2424 struct pvo_entry *pvo; 2425 int ptegidx; 2426 uint64_t vsid; 2427 #ifdef __powerpc64__ 2428 uint64_t slbv; 2429 2430 if (pm == kernel_pmap) { 2431 slbv = kernel_va_to_slbv(va); 2432 } else { 2433 struct slb *slb; 2434 slb = user_va_to_slb_entry(pm, va); 2435 /* The page is not mapped if the segment isn't */ 2436 if (slb == NULL) 2437 return NULL; 2438 slbv = slb->slbv; 2439 } 2440 2441 vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2442 if (slbv & SLBV_L) 2443 va &= ~moea64_large_page_mask; 2444 else 2445 va &= ~ADDR_POFF; 2446 ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L); 2447 #else 2448 va &= ~ADDR_POFF; 2449 vsid = va_to_vsid(pm, va); 2450 ptegidx = va_to_pteg(vsid, va, 0); 2451 #endif 2452 2453 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2454 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2455 break; 2456 } 2457 2458 return (pvo); 2459 } 2460 2461 static boolean_t 2462 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2463 { 2464 struct pvo_entry *pvo; 2465 uintptr_t pt; 2466 2467 LOCK_TABLE_RD(); 2468 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2469 /* 2470 * See if we saved the bit off. If so, return success. 2471 */ 2472 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2473 UNLOCK_TABLE_RD(); 2474 return (TRUE); 2475 } 2476 } 2477 2478 /* 2479 * No luck, now go through the hard part of looking at the PTEs 2480 * themselves. Sync so that any pending REF/CHG bits are flushed to 2481 * the PTEs. 2482 */ 2483 powerpc_sync(); 2484 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2485 2486 /* 2487 * See if this pvo has a valid PTE. if so, fetch the 2488 * REF/CHG bits from the valid PTE. If the appropriate 2489 * ptebit is set, return success. 2490 */ 2491 PMAP_LOCK(pvo->pvo_pmap); 2492 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2493 if (pt != -1) { 2494 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2495 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2496 PMAP_UNLOCK(pvo->pvo_pmap); 2497 UNLOCK_TABLE_RD(); 2498 return (TRUE); 2499 } 2500 } 2501 PMAP_UNLOCK(pvo->pvo_pmap); 2502 } 2503 2504 UNLOCK_TABLE_RD(); 2505 return (FALSE); 2506 } 2507 2508 static u_int 2509 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2510 { 2511 u_int count; 2512 struct pvo_entry *pvo; 2513 uintptr_t pt; 2514 2515 /* 2516 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2517 * we can reset the right ones). note that since the pvo entries and 2518 * list heads are accessed via BAT0 and are never placed in the page 2519 * table, we don't have to worry about further accesses setting the 2520 * REF/CHG bits. 2521 */ 2522 powerpc_sync(); 2523 2524 /* 2525 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2526 * valid pte clear the ptebit from the valid pte. 2527 */ 2528 count = 0; 2529 LOCK_TABLE_RD(); 2530 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2531 PMAP_LOCK(pvo->pvo_pmap); 2532 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2533 if (pt != -1) { 2534 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2535 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2536 count++; 2537 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2538 pvo->pvo_vpn, ptebit); 2539 } 2540 } 2541 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2542 PMAP_UNLOCK(pvo->pvo_pmap); 2543 } 2544 2545 UNLOCK_TABLE_RD(); 2546 return (count); 2547 } 2548 2549 boolean_t 2550 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2551 { 2552 struct pvo_entry *pvo; 2553 vm_offset_t ppa; 2554 int error = 0; 2555 2556 LOCK_TABLE_RD(); 2557 PMAP_LOCK(kernel_pmap); 2558 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2559 pvo = moea64_pvo_find_va(kernel_pmap, ppa); 2560 if (pvo == NULL || 2561 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2562 error = EFAULT; 2563 break; 2564 } 2565 } 2566 UNLOCK_TABLE_RD(); 2567 PMAP_UNLOCK(kernel_pmap); 2568 2569 return (error); 2570 } 2571 2572 /* 2573 * Map a set of physical memory pages into the kernel virtual 2574 * address space. Return a pointer to where it is mapped. This 2575 * routine is intended to be used for mapping device memory, 2576 * NOT real memory. 2577 */ 2578 void * 2579 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2580 { 2581 vm_offset_t va, tmpva, ppa, offset; 2582 2583 ppa = trunc_page(pa); 2584 offset = pa & PAGE_MASK; 2585 size = roundup2(offset + size, PAGE_SIZE); 2586 2587 va = kmem_alloc_nofault(kernel_map, size); 2588 2589 if (!va) 2590 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2591 2592 for (tmpva = va; size > 0;) { 2593 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2594 size -= PAGE_SIZE; 2595 tmpva += PAGE_SIZE; 2596 ppa += PAGE_SIZE; 2597 } 2598 2599 return ((void *)(va + offset)); 2600 } 2601 2602 void * 2603 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2604 { 2605 2606 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2607 } 2608 2609 void 2610 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2611 { 2612 vm_offset_t base, offset; 2613 2614 base = trunc_page(va); 2615 offset = va & PAGE_MASK; 2616 size = roundup2(offset + size, PAGE_SIZE); 2617 2618 kmem_free(kernel_map, base, size); 2619 } 2620 2621 void 2622 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2623 { 2624 struct pvo_entry *pvo; 2625 vm_offset_t lim; 2626 vm_paddr_t pa; 2627 vm_size_t len; 2628 2629 LOCK_TABLE_RD(); 2630 PMAP_LOCK(pm); 2631 while (sz > 0) { 2632 lim = round_page(va); 2633 len = MIN(lim - va, sz); 2634 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2635 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2636 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2637 (va & ADDR_POFF); 2638 moea64_syncicache(mmu, pm, va, pa, len); 2639 } 2640 va += len; 2641 sz -= len; 2642 } 2643 UNLOCK_TABLE_RD(); 2644 PMAP_UNLOCK(pm); 2645 } 2646