1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_compat.h" 106 #include "opt_kstack_pages.h" 107 108 #include <sys/param.h> 109 #include <sys/kernel.h> 110 #include <sys/conf.h> 111 #include <sys/queue.h> 112 #include <sys/cpuset.h> 113 #include <sys/kerneldump.h> 114 #include <sys/ktr.h> 115 #include <sys/lock.h> 116 #include <sys/msgbuf.h> 117 #include <sys/malloc.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <sys/kdb.h> 127 128 #include <dev/ofw/openfirm.h> 129 130 #include <vm/vm.h> 131 #include <vm/vm_param.h> 132 #include <vm/vm_kern.h> 133 #include <vm/vm_page.h> 134 #include <vm/vm_map.h> 135 #include <vm/vm_object.h> 136 #include <vm/vm_extern.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/_inttypes.h> 141 #include <machine/cpu.h> 142 #include <machine/platform.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/bat.h> 147 #include <machine/hid.h> 148 #include <machine/pte.h> 149 #include <machine/sr.h> 150 #include <machine/trap.h> 151 #include <machine/mmuvar.h> 152 153 #include "mmu_oea64.h" 154 #include "mmu_if.h" 155 #include "moea64_if.h" 156 157 void moea64_release_vsid(uint64_t vsid); 158 uintptr_t moea64_get_unique_vsid(void); 159 160 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 161 #define ENABLE_TRANS(msr) mtmsr(msr) 162 163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 165 #define VSID_HASH_MASK 0x0000007fffffffffULL 166 167 /* 168 * Locking semantics: 169 * -- Read lock: if no modifications are being made to either the PVO lists 170 * or page table or if any modifications being made result in internal 171 * changes (e.g. wiring, protection) such that the existence of the PVOs 172 * is unchanged and they remain associated with the same pmap (in which 173 * case the changes should be protected by the pmap lock) 174 * -- Write lock: required if PTEs/PVOs are being inserted or removed. 175 */ 176 177 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock) 178 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock) 179 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock) 180 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock) 181 182 struct ofw_map { 183 cell_t om_va; 184 cell_t om_len; 185 uint64_t om_pa; 186 cell_t om_mode; 187 }; 188 189 extern unsigned char _etext[]; 190 extern unsigned char _end[]; 191 192 extern int ofw_real_mode; 193 194 /* 195 * Map of physical memory regions. 196 */ 197 static struct mem_region *regions; 198 static struct mem_region *pregions; 199 static u_int phys_avail_count; 200 static int regions_sz, pregions_sz; 201 202 extern void bs_remap_earlyboot(void); 203 204 /* 205 * Lock for the pteg and pvo tables. 206 */ 207 struct rwlock moea64_table_lock; 208 struct mtx moea64_slb_mutex; 209 210 /* 211 * PTEG data. 212 */ 213 u_int moea64_pteg_count; 214 u_int moea64_pteg_mask; 215 216 /* 217 * PVO data. 218 */ 219 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 220 221 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 222 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 223 224 #define BPVO_POOL_SIZE 327680 225 static struct pvo_entry *moea64_bpvo_pool; 226 static int moea64_bpvo_pool_index = 0; 227 228 #define VSID_NBPW (sizeof(u_int32_t) * 8) 229 #ifdef __powerpc64__ 230 #define NVSIDS (NPMAPS * 16) 231 #define VSID_HASHMASK 0xffffffffUL 232 #else 233 #define NVSIDS NPMAPS 234 #define VSID_HASHMASK 0xfffffUL 235 #endif 236 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 237 238 static boolean_t moea64_initialized = FALSE; 239 240 /* 241 * Statistics. 242 */ 243 u_int moea64_pte_valid = 0; 244 u_int moea64_pte_overflow = 0; 245 u_int moea64_pvo_entries = 0; 246 u_int moea64_pvo_enter_calls = 0; 247 u_int moea64_pvo_remove_calls = 0; 248 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 249 &moea64_pte_valid, 0, ""); 250 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 251 &moea64_pte_overflow, 0, ""); 252 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 253 &moea64_pvo_entries, 0, ""); 254 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 255 &moea64_pvo_enter_calls, 0, ""); 256 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 257 &moea64_pvo_remove_calls, 0, ""); 258 259 vm_offset_t moea64_scratchpage_va[2]; 260 struct pvo_entry *moea64_scratchpage_pvo[2]; 261 uintptr_t moea64_scratchpage_pte[2]; 262 struct mtx moea64_scratchpage_mtx; 263 264 uint64_t moea64_large_page_mask = 0; 265 uint64_t moea64_large_page_size = 0; 266 int moea64_large_page_shift = 0; 267 268 /* 269 * PVO calls. 270 */ 271 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 272 vm_offset_t, vm_offset_t, uint64_t, int, int8_t); 273 static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 274 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 275 276 /* 277 * Utility routines. 278 */ 279 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 280 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 281 static void moea64_kremove(mmu_t, vm_offset_t); 282 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 283 vm_offset_t pa, vm_size_t sz); 284 285 /* 286 * Kernel MMU interface 287 */ 288 void moea64_clear_modify(mmu_t, vm_page_t); 289 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 290 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 291 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 292 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 293 u_int flags, int8_t psind); 294 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 295 vm_prot_t); 296 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 297 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 298 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 299 void moea64_init(mmu_t); 300 boolean_t moea64_is_modified(mmu_t, vm_page_t); 301 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 302 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 303 int moea64_ts_referenced(mmu_t, vm_page_t); 304 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 305 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 306 int moea64_page_wired_mappings(mmu_t, vm_page_t); 307 void moea64_pinit(mmu_t, pmap_t); 308 void moea64_pinit0(mmu_t, pmap_t); 309 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 310 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 311 void moea64_qremove(mmu_t, vm_offset_t, int); 312 void moea64_release(mmu_t, pmap_t); 313 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 314 void moea64_remove_pages(mmu_t, pmap_t); 315 void moea64_remove_all(mmu_t, vm_page_t); 316 void moea64_remove_write(mmu_t, vm_page_t); 317 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 318 void moea64_zero_page(mmu_t, vm_page_t); 319 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 320 void moea64_zero_page_idle(mmu_t, vm_page_t); 321 void moea64_activate(mmu_t, struct thread *); 322 void moea64_deactivate(mmu_t, struct thread *); 323 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 324 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 325 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 326 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 327 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 328 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 329 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 330 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 331 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 332 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 333 void **va); 334 void moea64_scan_init(mmu_t mmu); 335 336 static mmu_method_t moea64_methods[] = { 337 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 338 MMUMETHOD(mmu_copy_page, moea64_copy_page), 339 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 340 MMUMETHOD(mmu_enter, moea64_enter), 341 MMUMETHOD(mmu_enter_object, moea64_enter_object), 342 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 343 MMUMETHOD(mmu_extract, moea64_extract), 344 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 345 MMUMETHOD(mmu_init, moea64_init), 346 MMUMETHOD(mmu_is_modified, moea64_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 350 MMUMETHOD(mmu_map, moea64_map), 351 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 352 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 353 MMUMETHOD(mmu_pinit, moea64_pinit), 354 MMUMETHOD(mmu_pinit0, moea64_pinit0), 355 MMUMETHOD(mmu_protect, moea64_protect), 356 MMUMETHOD(mmu_qenter, moea64_qenter), 357 MMUMETHOD(mmu_qremove, moea64_qremove), 358 MMUMETHOD(mmu_release, moea64_release), 359 MMUMETHOD(mmu_remove, moea64_remove), 360 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 361 MMUMETHOD(mmu_remove_all, moea64_remove_all), 362 MMUMETHOD(mmu_remove_write, moea64_remove_write), 363 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 364 MMUMETHOD(mmu_unwire, moea64_unwire), 365 MMUMETHOD(mmu_zero_page, moea64_zero_page), 366 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 367 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 368 MMUMETHOD(mmu_activate, moea64_activate), 369 MMUMETHOD(mmu_deactivate, moea64_deactivate), 370 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_mapdev, moea64_mapdev), 374 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 375 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 376 MMUMETHOD(mmu_kextract, moea64_kextract), 377 MMUMETHOD(mmu_kenter, moea64_kenter), 378 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 379 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 380 MMUMETHOD(mmu_scan_init, moea64_scan_init), 381 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 382 383 { 0, 0 } 384 }; 385 386 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 387 388 static __inline u_int 389 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 390 { 391 uint64_t hash; 392 int shift; 393 394 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 395 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 396 shift); 397 return (hash & moea64_pteg_mask); 398 } 399 400 static __inline struct pvo_head * 401 vm_page_to_pvoh(vm_page_t m) 402 { 403 404 return (&m->md.mdpg_pvoh); 405 } 406 407 static __inline void 408 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 409 uint64_t pte_lo, int flags) 410 { 411 412 /* 413 * Construct a PTE. Default to IMB initially. Valid bit only gets 414 * set when the real pte is set in memory. 415 * 416 * Note: Don't set the valid bit for correct operation of tlb update. 417 */ 418 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 419 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 420 421 if (flags & PVO_LARGE) 422 pt->pte_hi |= LPTE_BIG; 423 424 pt->pte_lo = pte_lo; 425 } 426 427 static __inline uint64_t 428 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 429 { 430 uint64_t pte_lo; 431 int i; 432 433 if (ma != VM_MEMATTR_DEFAULT) { 434 switch (ma) { 435 case VM_MEMATTR_UNCACHEABLE: 436 return (LPTE_I | LPTE_G); 437 case VM_MEMATTR_WRITE_COMBINING: 438 case VM_MEMATTR_WRITE_BACK: 439 case VM_MEMATTR_PREFETCHABLE: 440 return (LPTE_I); 441 case VM_MEMATTR_WRITE_THROUGH: 442 return (LPTE_W | LPTE_M); 443 } 444 } 445 446 /* 447 * Assume the page is cache inhibited and access is guarded unless 448 * it's in our available memory array. 449 */ 450 pte_lo = LPTE_I | LPTE_G; 451 for (i = 0; i < pregions_sz; i++) { 452 if ((pa >= pregions[i].mr_start) && 453 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 454 pte_lo &= ~(LPTE_I | LPTE_G); 455 pte_lo |= LPTE_M; 456 break; 457 } 458 } 459 460 return pte_lo; 461 } 462 463 /* 464 * Quick sort callout for comparing memory regions. 465 */ 466 static int om_cmp(const void *a, const void *b); 467 468 static int 469 om_cmp(const void *a, const void *b) 470 { 471 const struct ofw_map *mapa; 472 const struct ofw_map *mapb; 473 474 mapa = a; 475 mapb = b; 476 if (mapa->om_pa < mapb->om_pa) 477 return (-1); 478 else if (mapa->om_pa > mapb->om_pa) 479 return (1); 480 else 481 return (0); 482 } 483 484 static void 485 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 486 { 487 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 488 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 489 register_t msr; 490 vm_offset_t off; 491 vm_paddr_t pa_base; 492 int i, j; 493 494 bzero(translations, sz); 495 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 496 sizeof(acells)); 497 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 498 panic("moea64_bootstrap: can't get ofw translations"); 499 500 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 501 sz /= sizeof(cell_t); 502 for (i = 0, j = 0; i < sz; j++) { 503 translations[j].om_va = trans_cells[i++]; 504 translations[j].om_len = trans_cells[i++]; 505 translations[j].om_pa = trans_cells[i++]; 506 if (acells == 2) { 507 translations[j].om_pa <<= 32; 508 translations[j].om_pa |= trans_cells[i++]; 509 } 510 translations[j].om_mode = trans_cells[i++]; 511 } 512 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 513 i, sz)); 514 515 sz = j; 516 qsort(translations, sz, sizeof (*translations), om_cmp); 517 518 for (i = 0; i < sz; i++) { 519 pa_base = translations[i].om_pa; 520 #ifndef __powerpc64__ 521 if ((translations[i].om_pa >> 32) != 0) 522 panic("OFW translations above 32-bit boundary!"); 523 #endif 524 525 if (pa_base % PAGE_SIZE) 526 panic("OFW translation not page-aligned (phys)!"); 527 if (translations[i].om_va % PAGE_SIZE) 528 panic("OFW translation not page-aligned (virt)!"); 529 530 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 531 pa_base, translations[i].om_va, translations[i].om_len); 532 533 /* Now enter the pages for this mapping */ 534 535 DISABLE_TRANS(msr); 536 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 537 if (moea64_pvo_find_va(kernel_pmap, 538 translations[i].om_va + off) != NULL) 539 continue; 540 541 moea64_kenter(mmup, translations[i].om_va + off, 542 pa_base + off); 543 } 544 ENABLE_TRANS(msr); 545 } 546 } 547 548 #ifdef __powerpc64__ 549 static void 550 moea64_probe_large_page(void) 551 { 552 uint16_t pvr = mfpvr() >> 16; 553 554 switch (pvr) { 555 case IBM970: 556 case IBM970FX: 557 case IBM970MP: 558 powerpc_sync(); isync(); 559 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 560 powerpc_sync(); isync(); 561 562 /* FALLTHROUGH */ 563 default: 564 moea64_large_page_size = 0x1000000; /* 16 MB */ 565 moea64_large_page_shift = 24; 566 } 567 568 moea64_large_page_mask = moea64_large_page_size - 1; 569 } 570 571 static void 572 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 573 { 574 struct slb *cache; 575 struct slb entry; 576 uint64_t esid, slbe; 577 uint64_t i; 578 579 cache = PCPU_GET(slb); 580 esid = va >> ADDR_SR_SHFT; 581 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 582 583 for (i = 0; i < 64; i++) { 584 if (cache[i].slbe == (slbe | i)) 585 return; 586 } 587 588 entry.slbe = slbe; 589 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 590 if (large) 591 entry.slbv |= SLBV_L; 592 593 slb_insert_kernel(entry.slbe, entry.slbv); 594 } 595 #endif 596 597 static void 598 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 599 vm_offset_t kernelend) 600 { 601 register_t msr; 602 vm_paddr_t pa; 603 vm_offset_t size, off; 604 uint64_t pte_lo; 605 int i; 606 607 if (moea64_large_page_size == 0) 608 hw_direct_map = 0; 609 610 DISABLE_TRANS(msr); 611 if (hw_direct_map) { 612 LOCK_TABLE_WR(); 613 PMAP_LOCK(kernel_pmap); 614 for (i = 0; i < pregions_sz; i++) { 615 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 616 pregions[i].mr_size; pa += moea64_large_page_size) { 617 pte_lo = LPTE_M; 618 619 /* 620 * Set memory access as guarded if prefetch within 621 * the page could exit the available physmem area. 622 */ 623 if (pa & moea64_large_page_mask) { 624 pa &= moea64_large_page_mask; 625 pte_lo |= LPTE_G; 626 } 627 if (pa + moea64_large_page_size > 628 pregions[i].mr_start + pregions[i].mr_size) 629 pte_lo |= LPTE_G; 630 631 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 632 NULL, pa, pa, pte_lo, 633 PVO_WIRED | PVO_LARGE, 0); 634 } 635 } 636 PMAP_UNLOCK(kernel_pmap); 637 UNLOCK_TABLE_WR(); 638 } else { 639 size = sizeof(struct pvo_head) * moea64_pteg_count; 640 off = (vm_offset_t)(moea64_pvo_table); 641 for (pa = off; pa < off + size; pa += PAGE_SIZE) 642 moea64_kenter(mmup, pa, pa); 643 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 644 off = (vm_offset_t)(moea64_bpvo_pool); 645 for (pa = off; pa < off + size; pa += PAGE_SIZE) 646 moea64_kenter(mmup, pa, pa); 647 648 /* 649 * Map certain important things, like ourselves. 650 * 651 * NOTE: We do not map the exception vector space. That code is 652 * used only in real mode, and leaving it unmapped allows us to 653 * catch NULL pointer deferences, instead of making NULL a valid 654 * address. 655 */ 656 657 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 658 pa += PAGE_SIZE) 659 moea64_kenter(mmup, pa, pa); 660 } 661 ENABLE_TRANS(msr); 662 663 /* 664 * Allow user to override unmapped_buf_allowed for testing. 665 * XXXKIB Only direct map implementation was tested. 666 */ 667 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 668 &unmapped_buf_allowed)) 669 unmapped_buf_allowed = hw_direct_map; 670 } 671 672 void 673 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 674 { 675 int i, j; 676 vm_size_t physsz, hwphyssz; 677 678 #ifndef __powerpc64__ 679 /* We don't have a direct map since there is no BAT */ 680 hw_direct_map = 0; 681 682 /* Make sure battable is zero, since we have no BAT */ 683 for (i = 0; i < 16; i++) { 684 battable[i].batu = 0; 685 battable[i].batl = 0; 686 } 687 #else 688 moea64_probe_large_page(); 689 690 /* Use a direct map if we have large page support */ 691 if (moea64_large_page_size > 0) 692 hw_direct_map = 1; 693 else 694 hw_direct_map = 0; 695 #endif 696 697 /* Get physical memory regions from firmware */ 698 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 699 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 700 701 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 702 panic("moea64_bootstrap: phys_avail too small"); 703 704 phys_avail_count = 0; 705 physsz = 0; 706 hwphyssz = 0; 707 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 708 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 709 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 710 regions[i].mr_start, regions[i].mr_start + 711 regions[i].mr_size, regions[i].mr_size); 712 if (hwphyssz != 0 && 713 (physsz + regions[i].mr_size) >= hwphyssz) { 714 if (physsz < hwphyssz) { 715 phys_avail[j] = regions[i].mr_start; 716 phys_avail[j + 1] = regions[i].mr_start + 717 hwphyssz - physsz; 718 physsz = hwphyssz; 719 phys_avail_count++; 720 } 721 break; 722 } 723 phys_avail[j] = regions[i].mr_start; 724 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 725 phys_avail_count++; 726 physsz += regions[i].mr_size; 727 } 728 729 /* Check for overlap with the kernel and exception vectors */ 730 for (j = 0; j < 2*phys_avail_count; j+=2) { 731 if (phys_avail[j] < EXC_LAST) 732 phys_avail[j] += EXC_LAST; 733 734 if (kernelstart >= phys_avail[j] && 735 kernelstart < phys_avail[j+1]) { 736 if (kernelend < phys_avail[j+1]) { 737 phys_avail[2*phys_avail_count] = 738 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 739 phys_avail[2*phys_avail_count + 1] = 740 phys_avail[j+1]; 741 phys_avail_count++; 742 } 743 744 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 745 } 746 747 if (kernelend >= phys_avail[j] && 748 kernelend < phys_avail[j+1]) { 749 if (kernelstart > phys_avail[j]) { 750 phys_avail[2*phys_avail_count] = phys_avail[j]; 751 phys_avail[2*phys_avail_count + 1] = 752 kernelstart & ~PAGE_MASK; 753 phys_avail_count++; 754 } 755 756 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 757 } 758 } 759 760 physmem = btoc(physsz); 761 762 #ifdef PTEGCOUNT 763 moea64_pteg_count = PTEGCOUNT; 764 #else 765 moea64_pteg_count = 0x1000; 766 767 while (moea64_pteg_count < physmem) 768 moea64_pteg_count <<= 1; 769 770 moea64_pteg_count >>= 1; 771 #endif /* PTEGCOUNT */ 772 } 773 774 void 775 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 776 { 777 vm_size_t size; 778 register_t msr; 779 int i; 780 781 /* 782 * Set PTEG mask 783 */ 784 moea64_pteg_mask = moea64_pteg_count - 1; 785 786 /* 787 * Allocate pv/overflow lists. 788 */ 789 size = sizeof(struct pvo_head) * moea64_pteg_count; 790 791 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 792 PAGE_SIZE); 793 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 794 795 DISABLE_TRANS(msr); 796 for (i = 0; i < moea64_pteg_count; i++) 797 LIST_INIT(&moea64_pvo_table[i]); 798 ENABLE_TRANS(msr); 799 800 /* 801 * Initialize the lock that synchronizes access to the pteg and pvo 802 * tables. 803 */ 804 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE); 805 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 806 807 /* 808 * Initialise the unmanaged pvo pool. 809 */ 810 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 811 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 812 moea64_bpvo_pool_index = 0; 813 814 /* 815 * Make sure kernel vsid is allocated as well as VSID 0. 816 */ 817 #ifndef __powerpc64__ 818 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 819 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 820 moea64_vsid_bitmap[0] |= 1; 821 #endif 822 823 /* 824 * Initialize the kernel pmap (which is statically allocated). 825 */ 826 #ifdef __powerpc64__ 827 for (i = 0; i < 64; i++) { 828 pcpup->pc_slb[i].slbv = 0; 829 pcpup->pc_slb[i].slbe = 0; 830 } 831 #else 832 for (i = 0; i < 16; i++) 833 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 834 #endif 835 836 kernel_pmap->pmap_phys = kernel_pmap; 837 CPU_FILL(&kernel_pmap->pm_active); 838 RB_INIT(&kernel_pmap->pmap_pvo); 839 840 PMAP_LOCK_INIT(kernel_pmap); 841 842 /* 843 * Now map in all the other buffers we allocated earlier 844 */ 845 846 moea64_setup_direct_map(mmup, kernelstart, kernelend); 847 } 848 849 void 850 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 851 { 852 ihandle_t mmui; 853 phandle_t chosen; 854 phandle_t mmu; 855 ssize_t sz; 856 int i; 857 vm_offset_t pa, va; 858 void *dpcpu; 859 860 /* 861 * Set up the Open Firmware pmap and add its mappings if not in real 862 * mode. 863 */ 864 865 chosen = OF_finddevice("/chosen"); 866 if (!ofw_real_mode && chosen != -1 && 867 OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 868 mmu = OF_instance_to_package(mmui); 869 if (mmu == -1 || 870 (sz = OF_getproplen(mmu, "translations")) == -1) 871 sz = 0; 872 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 873 panic("moea64_bootstrap: too many ofw translations"); 874 875 if (sz > 0) 876 moea64_add_ofw_mappings(mmup, mmu, sz); 877 } 878 879 /* 880 * Calculate the last available physical address. 881 */ 882 for (i = 0; phys_avail[i + 2] != 0; i += 2) 883 ; 884 Maxmem = powerpc_btop(phys_avail[i + 1]); 885 886 /* 887 * Initialize MMU and remap early physical mappings 888 */ 889 MMU_CPU_BOOTSTRAP(mmup,0); 890 mtmsr(mfmsr() | PSL_DR | PSL_IR); 891 pmap_bootstrapped++; 892 bs_remap_earlyboot(); 893 894 /* 895 * Set the start and end of kva. 896 */ 897 virtual_avail = VM_MIN_KERNEL_ADDRESS; 898 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 899 900 /* 901 * Map the entire KVA range into the SLB. We must not fault there. 902 */ 903 #ifdef __powerpc64__ 904 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 905 moea64_bootstrap_slb_prefault(va, 0); 906 #endif 907 908 /* 909 * Figure out how far we can extend virtual_end into segment 16 910 * without running into existing mappings. Segment 16 is guaranteed 911 * to contain neither RAM nor devices (at least on Apple hardware), 912 * but will generally contain some OFW mappings we should not 913 * step on. 914 */ 915 916 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 917 PMAP_LOCK(kernel_pmap); 918 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 919 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 920 virtual_end += PAGE_SIZE; 921 PMAP_UNLOCK(kernel_pmap); 922 #endif 923 924 /* 925 * Allocate a kernel stack with a guard page for thread0 and map it 926 * into the kernel page map. 927 */ 928 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 929 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 930 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 931 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 932 thread0.td_kstack = va; 933 thread0.td_kstack_pages = KSTACK_PAGES; 934 for (i = 0; i < KSTACK_PAGES; i++) { 935 moea64_kenter(mmup, va, pa); 936 pa += PAGE_SIZE; 937 va += PAGE_SIZE; 938 } 939 940 /* 941 * Allocate virtual address space for the message buffer. 942 */ 943 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 944 msgbufp = (struct msgbuf *)virtual_avail; 945 va = virtual_avail; 946 virtual_avail += round_page(msgbufsize); 947 while (va < virtual_avail) { 948 moea64_kenter(mmup, va, pa); 949 pa += PAGE_SIZE; 950 va += PAGE_SIZE; 951 } 952 953 /* 954 * Allocate virtual address space for the dynamic percpu area. 955 */ 956 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 957 dpcpu = (void *)virtual_avail; 958 va = virtual_avail; 959 virtual_avail += DPCPU_SIZE; 960 while (va < virtual_avail) { 961 moea64_kenter(mmup, va, pa); 962 pa += PAGE_SIZE; 963 va += PAGE_SIZE; 964 } 965 dpcpu_init(dpcpu, 0); 966 967 /* 968 * Allocate some things for page zeroing. We put this directly 969 * in the page table, marked with LPTE_LOCKED, to avoid any 970 * of the PVO book-keeping or other parts of the VM system 971 * from even knowing that this hack exists. 972 */ 973 974 if (!hw_direct_map) { 975 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 976 MTX_DEF); 977 for (i = 0; i < 2; i++) { 978 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 979 virtual_end -= PAGE_SIZE; 980 981 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 982 983 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 984 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 985 LOCK_TABLE_RD(); 986 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 987 mmup, moea64_scratchpage_pvo[i]); 988 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 989 |= LPTE_LOCKED; 990 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 991 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 992 moea64_scratchpage_pvo[i]->pvo_vpn); 993 UNLOCK_TABLE_RD(); 994 } 995 } 996 } 997 998 /* 999 * Activate a user pmap. The pmap must be activated before its address 1000 * space can be accessed in any way. 1001 */ 1002 void 1003 moea64_activate(mmu_t mmu, struct thread *td) 1004 { 1005 pmap_t pm; 1006 1007 pm = &td->td_proc->p_vmspace->vm_pmap; 1008 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1009 1010 #ifdef __powerpc64__ 1011 PCPU_SET(userslb, pm->pm_slb); 1012 #else 1013 PCPU_SET(curpmap, pm->pmap_phys); 1014 #endif 1015 } 1016 1017 void 1018 moea64_deactivate(mmu_t mmu, struct thread *td) 1019 { 1020 pmap_t pm; 1021 1022 pm = &td->td_proc->p_vmspace->vm_pmap; 1023 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1024 #ifdef __powerpc64__ 1025 PCPU_SET(userslb, NULL); 1026 #else 1027 PCPU_SET(curpmap, NULL); 1028 #endif 1029 } 1030 1031 void 1032 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1033 { 1034 struct pvo_entry key, *pvo; 1035 uintptr_t pt; 1036 1037 LOCK_TABLE_RD(); 1038 PMAP_LOCK(pm); 1039 key.pvo_vaddr = sva; 1040 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1041 pvo != NULL && PVO_VADDR(pvo) < eva; 1042 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1043 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1044 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1045 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1046 pvo); 1047 pvo->pvo_vaddr &= ~PVO_WIRED; 1048 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_WIRED) == 0) 1049 panic("moea64_unwire: pte %p is missing LPTE_WIRED", 1050 &pvo->pvo_pte.lpte); 1051 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1052 if (pt != -1) { 1053 /* 1054 * The PTE's wired attribute is not a hardware 1055 * feature, so there is no need to invalidate any TLB 1056 * entries. 1057 */ 1058 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1059 pvo->pvo_vpn); 1060 } 1061 pm->pm_stats.wired_count--; 1062 } 1063 UNLOCK_TABLE_RD(); 1064 PMAP_UNLOCK(pm); 1065 } 1066 1067 /* 1068 * This goes through and sets the physical address of our 1069 * special scratch PTE to the PA we want to zero or copy. Because 1070 * of locking issues (this can get called in pvo_enter() by 1071 * the UMA allocator), we can't use most other utility functions here 1072 */ 1073 1074 static __inline 1075 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1076 1077 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1078 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1079 1080 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1081 ~(LPTE_WIMG | LPTE_RPGN); 1082 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1083 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1084 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1085 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1086 moea64_scratchpage_pvo[which]->pvo_vpn); 1087 isync(); 1088 } 1089 1090 void 1091 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1092 { 1093 vm_offset_t dst; 1094 vm_offset_t src; 1095 1096 dst = VM_PAGE_TO_PHYS(mdst); 1097 src = VM_PAGE_TO_PHYS(msrc); 1098 1099 if (hw_direct_map) { 1100 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1101 } else { 1102 mtx_lock(&moea64_scratchpage_mtx); 1103 1104 moea64_set_scratchpage_pa(mmu, 0, src); 1105 moea64_set_scratchpage_pa(mmu, 1, dst); 1106 1107 bcopy((void *)moea64_scratchpage_va[0], 1108 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1109 1110 mtx_unlock(&moea64_scratchpage_mtx); 1111 } 1112 } 1113 1114 static inline void 1115 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1116 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1117 { 1118 void *a_cp, *b_cp; 1119 vm_offset_t a_pg_offset, b_pg_offset; 1120 int cnt; 1121 1122 while (xfersize > 0) { 1123 a_pg_offset = a_offset & PAGE_MASK; 1124 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1125 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1126 a_pg_offset; 1127 b_pg_offset = b_offset & PAGE_MASK; 1128 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1129 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1130 b_pg_offset; 1131 bcopy(a_cp, b_cp, cnt); 1132 a_offset += cnt; 1133 b_offset += cnt; 1134 xfersize -= cnt; 1135 } 1136 } 1137 1138 static inline void 1139 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1140 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1141 { 1142 void *a_cp, *b_cp; 1143 vm_offset_t a_pg_offset, b_pg_offset; 1144 int cnt; 1145 1146 mtx_lock(&moea64_scratchpage_mtx); 1147 while (xfersize > 0) { 1148 a_pg_offset = a_offset & PAGE_MASK; 1149 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1150 moea64_set_scratchpage_pa(mmu, 0, 1151 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1152 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1153 b_pg_offset = b_offset & PAGE_MASK; 1154 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1155 moea64_set_scratchpage_pa(mmu, 1, 1156 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1157 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1158 bcopy(a_cp, b_cp, cnt); 1159 a_offset += cnt; 1160 b_offset += cnt; 1161 xfersize -= cnt; 1162 } 1163 mtx_unlock(&moea64_scratchpage_mtx); 1164 } 1165 1166 void 1167 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1168 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1169 { 1170 1171 if (hw_direct_map) { 1172 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1173 xfersize); 1174 } else { 1175 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1176 xfersize); 1177 } 1178 } 1179 1180 void 1181 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1182 { 1183 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1184 1185 if (size + off > PAGE_SIZE) 1186 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1187 1188 if (hw_direct_map) { 1189 bzero((caddr_t)pa + off, size); 1190 } else { 1191 mtx_lock(&moea64_scratchpage_mtx); 1192 moea64_set_scratchpage_pa(mmu, 0, pa); 1193 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1194 mtx_unlock(&moea64_scratchpage_mtx); 1195 } 1196 } 1197 1198 /* 1199 * Zero a page of physical memory by temporarily mapping it 1200 */ 1201 void 1202 moea64_zero_page(mmu_t mmu, vm_page_t m) 1203 { 1204 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1205 vm_offset_t va, off; 1206 1207 if (!hw_direct_map) { 1208 mtx_lock(&moea64_scratchpage_mtx); 1209 1210 moea64_set_scratchpage_pa(mmu, 0, pa); 1211 va = moea64_scratchpage_va[0]; 1212 } else { 1213 va = pa; 1214 } 1215 1216 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1217 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1218 1219 if (!hw_direct_map) 1220 mtx_unlock(&moea64_scratchpage_mtx); 1221 } 1222 1223 void 1224 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1225 { 1226 1227 moea64_zero_page(mmu, m); 1228 } 1229 1230 /* 1231 * Map the given physical page at the specified virtual address in the 1232 * target pmap with the protection requested. If specified the page 1233 * will be wired down. 1234 */ 1235 1236 int 1237 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1238 vm_prot_t prot, u_int flags, int8_t psind) 1239 { 1240 struct pvo_head *pvo_head; 1241 uma_zone_t zone; 1242 uint64_t pte_lo; 1243 u_int pvo_flags; 1244 int error; 1245 1246 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1247 VM_OBJECT_ASSERT_LOCKED(m->object); 1248 1249 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1250 pvo_head = NULL; 1251 zone = moea64_upvo_zone; 1252 pvo_flags = 0; 1253 } else { 1254 pvo_head = vm_page_to_pvoh(m); 1255 zone = moea64_mpvo_zone; 1256 pvo_flags = PVO_MANAGED; 1257 } 1258 1259 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1260 1261 if (prot & VM_PROT_WRITE) { 1262 pte_lo |= LPTE_BW; 1263 if (pmap_bootstrapped && 1264 (m->oflags & VPO_UNMANAGED) == 0) 1265 vm_page_aflag_set(m, PGA_WRITEABLE); 1266 } else 1267 pte_lo |= LPTE_BR; 1268 1269 if ((prot & VM_PROT_EXECUTE) == 0) 1270 pte_lo |= LPTE_NOEXEC; 1271 1272 if ((flags & PMAP_ENTER_WIRED) != 0) 1273 pvo_flags |= PVO_WIRED; 1274 1275 for (;;) { 1276 LOCK_TABLE_WR(); 1277 PMAP_LOCK(pmap); 1278 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1279 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags, psind); 1280 PMAP_UNLOCK(pmap); 1281 UNLOCK_TABLE_WR(); 1282 if (error != ENOMEM) 1283 break; 1284 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1285 return (KERN_RESOURCE_SHORTAGE); 1286 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1287 VM_WAIT; 1288 } 1289 1290 /* 1291 * Flush the page from the instruction cache if this page is 1292 * mapped executable and cacheable. 1293 */ 1294 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1295 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1296 vm_page_aflag_set(m, PGA_EXECUTABLE); 1297 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1298 } 1299 return (KERN_SUCCESS); 1300 } 1301 1302 static void 1303 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1304 vm_size_t sz) 1305 { 1306 1307 /* 1308 * This is much trickier than on older systems because 1309 * we can't sync the icache on physical addresses directly 1310 * without a direct map. Instead we check a couple of cases 1311 * where the memory is already mapped in and, failing that, 1312 * use the same trick we use for page zeroing to create 1313 * a temporary mapping for this physical address. 1314 */ 1315 1316 if (!pmap_bootstrapped) { 1317 /* 1318 * If PMAP is not bootstrapped, we are likely to be 1319 * in real mode. 1320 */ 1321 __syncicache((void *)pa, sz); 1322 } else if (pmap == kernel_pmap) { 1323 __syncicache((void *)va, sz); 1324 } else if (hw_direct_map) { 1325 __syncicache((void *)pa, sz); 1326 } else { 1327 /* Use the scratch page to set up a temp mapping */ 1328 1329 mtx_lock(&moea64_scratchpage_mtx); 1330 1331 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1332 __syncicache((void *)(moea64_scratchpage_va[1] + 1333 (va & ADDR_POFF)), sz); 1334 1335 mtx_unlock(&moea64_scratchpage_mtx); 1336 } 1337 } 1338 1339 /* 1340 * Maps a sequence of resident pages belonging to the same object. 1341 * The sequence begins with the given page m_start. This page is 1342 * mapped at the given virtual address start. Each subsequent page is 1343 * mapped at a virtual address that is offset from start by the same 1344 * amount as the page is offset from m_start within the object. The 1345 * last page in the sequence is the page with the largest offset from 1346 * m_start that can be mapped at a virtual address less than the given 1347 * virtual address end. Not every virtual page between start and end 1348 * is mapped; only those for which a resident page exists with the 1349 * corresponding offset from m_start are mapped. 1350 */ 1351 void 1352 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1353 vm_page_t m_start, vm_prot_t prot) 1354 { 1355 vm_page_t m; 1356 vm_pindex_t diff, psize; 1357 1358 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1359 1360 psize = atop(end - start); 1361 m = m_start; 1362 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1363 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1364 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1365 m = TAILQ_NEXT(m, listq); 1366 } 1367 } 1368 1369 void 1370 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1371 vm_prot_t prot) 1372 { 1373 1374 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1375 PMAP_ENTER_NOSLEEP, 0); 1376 } 1377 1378 vm_paddr_t 1379 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1380 { 1381 struct pvo_entry *pvo; 1382 vm_paddr_t pa; 1383 1384 PMAP_LOCK(pm); 1385 pvo = moea64_pvo_find_va(pm, va); 1386 if (pvo == NULL) 1387 pa = 0; 1388 else 1389 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1390 (va - PVO_VADDR(pvo)); 1391 PMAP_UNLOCK(pm); 1392 return (pa); 1393 } 1394 1395 /* 1396 * Atomically extract and hold the physical page with the given 1397 * pmap and virtual address pair if that mapping permits the given 1398 * protection. 1399 */ 1400 vm_page_t 1401 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1402 { 1403 struct pvo_entry *pvo; 1404 vm_page_t m; 1405 vm_paddr_t pa; 1406 1407 m = NULL; 1408 pa = 0; 1409 PMAP_LOCK(pmap); 1410 retry: 1411 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1412 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1413 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1414 (prot & VM_PROT_WRITE) == 0)) { 1415 if (vm_page_pa_tryrelock(pmap, 1416 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1417 goto retry; 1418 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1419 vm_page_hold(m); 1420 } 1421 PA_UNLOCK_COND(pa); 1422 PMAP_UNLOCK(pmap); 1423 return (m); 1424 } 1425 1426 static mmu_t installed_mmu; 1427 1428 static void * 1429 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1430 { 1431 /* 1432 * This entire routine is a horrible hack to avoid bothering kmem 1433 * for new KVA addresses. Because this can get called from inside 1434 * kmem allocation routines, calling kmem for a new address here 1435 * can lead to multiply locking non-recursive mutexes. 1436 */ 1437 vm_offset_t va; 1438 1439 vm_page_t m; 1440 int pflags, needed_lock; 1441 1442 *flags = UMA_SLAB_PRIV; 1443 needed_lock = !PMAP_LOCKED(kernel_pmap); 1444 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1445 1446 for (;;) { 1447 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1448 if (m == NULL) { 1449 if (wait & M_NOWAIT) 1450 return (NULL); 1451 VM_WAIT; 1452 } else 1453 break; 1454 } 1455 1456 va = VM_PAGE_TO_PHYS(m); 1457 1458 LOCK_TABLE_WR(); 1459 if (needed_lock) 1460 PMAP_LOCK(kernel_pmap); 1461 1462 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1463 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP, 1464 0); 1465 1466 if (needed_lock) 1467 PMAP_UNLOCK(kernel_pmap); 1468 UNLOCK_TABLE_WR(); 1469 1470 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1471 bzero((void *)va, PAGE_SIZE); 1472 1473 return (void *)va; 1474 } 1475 1476 extern int elf32_nxstack; 1477 1478 void 1479 moea64_init(mmu_t mmu) 1480 { 1481 1482 CTR0(KTR_PMAP, "moea64_init"); 1483 1484 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1485 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1486 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1487 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1488 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1489 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1490 1491 if (!hw_direct_map) { 1492 installed_mmu = mmu; 1493 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1494 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1495 } 1496 1497 #ifdef COMPAT_FREEBSD32 1498 elf32_nxstack = 1; 1499 #endif 1500 1501 moea64_initialized = TRUE; 1502 } 1503 1504 boolean_t 1505 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1506 { 1507 1508 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1509 ("moea64_is_referenced: page %p is not managed", m)); 1510 return (moea64_query_bit(mmu, m, PTE_REF)); 1511 } 1512 1513 boolean_t 1514 moea64_is_modified(mmu_t mmu, vm_page_t m) 1515 { 1516 1517 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1518 ("moea64_is_modified: page %p is not managed", m)); 1519 1520 /* 1521 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1522 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1523 * is clear, no PTEs can have LPTE_CHG set. 1524 */ 1525 VM_OBJECT_ASSERT_LOCKED(m->object); 1526 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1527 return (FALSE); 1528 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1529 } 1530 1531 boolean_t 1532 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1533 { 1534 struct pvo_entry *pvo; 1535 boolean_t rv; 1536 1537 PMAP_LOCK(pmap); 1538 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1539 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1540 PMAP_UNLOCK(pmap); 1541 return (rv); 1542 } 1543 1544 void 1545 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1546 { 1547 1548 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1549 ("moea64_clear_modify: page %p is not managed", m)); 1550 VM_OBJECT_ASSERT_WLOCKED(m->object); 1551 KASSERT(!vm_page_xbusied(m), 1552 ("moea64_clear_modify: page %p is exclusive busied", m)); 1553 1554 /* 1555 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1556 * set. If the object containing the page is locked and the page is 1557 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1558 */ 1559 if ((m->aflags & PGA_WRITEABLE) == 0) 1560 return; 1561 moea64_clear_bit(mmu, m, LPTE_CHG); 1562 } 1563 1564 /* 1565 * Clear the write and modified bits in each of the given page's mappings. 1566 */ 1567 void 1568 moea64_remove_write(mmu_t mmu, vm_page_t m) 1569 { 1570 struct pvo_entry *pvo; 1571 uintptr_t pt; 1572 pmap_t pmap; 1573 uint64_t lo = 0; 1574 1575 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1576 ("moea64_remove_write: page %p is not managed", m)); 1577 1578 /* 1579 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1580 * set by another thread while the object is locked. Thus, 1581 * if PGA_WRITEABLE is clear, no page table entries need updating. 1582 */ 1583 VM_OBJECT_ASSERT_WLOCKED(m->object); 1584 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1585 return; 1586 powerpc_sync(); 1587 LOCK_TABLE_RD(); 1588 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1589 pmap = pvo->pvo_pmap; 1590 PMAP_LOCK(pmap); 1591 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1592 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1593 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1594 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1595 if (pt != -1) { 1596 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1597 lo |= pvo->pvo_pte.lpte.pte_lo; 1598 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1599 MOEA64_PTE_CHANGE(mmu, pt, 1600 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1601 if (pvo->pvo_pmap == kernel_pmap) 1602 isync(); 1603 } 1604 } 1605 if ((lo & LPTE_CHG) != 0) 1606 vm_page_dirty(m); 1607 PMAP_UNLOCK(pmap); 1608 } 1609 UNLOCK_TABLE_RD(); 1610 vm_page_aflag_clear(m, PGA_WRITEABLE); 1611 } 1612 1613 /* 1614 * moea64_ts_referenced: 1615 * 1616 * Return a count of reference bits for a page, clearing those bits. 1617 * It is not necessary for every reference bit to be cleared, but it 1618 * is necessary that 0 only be returned when there are truly no 1619 * reference bits set. 1620 * 1621 * XXX: The exact number of bits to check and clear is a matter that 1622 * should be tested and standardized at some point in the future for 1623 * optimal aging of shared pages. 1624 */ 1625 int 1626 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1627 { 1628 1629 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1630 ("moea64_ts_referenced: page %p is not managed", m)); 1631 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1632 } 1633 1634 /* 1635 * Modify the WIMG settings of all mappings for a page. 1636 */ 1637 void 1638 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1639 { 1640 struct pvo_entry *pvo; 1641 struct pvo_head *pvo_head; 1642 uintptr_t pt; 1643 pmap_t pmap; 1644 uint64_t lo; 1645 1646 if ((m->oflags & VPO_UNMANAGED) != 0) { 1647 m->md.mdpg_cache_attrs = ma; 1648 return; 1649 } 1650 1651 pvo_head = vm_page_to_pvoh(m); 1652 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1653 LOCK_TABLE_RD(); 1654 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1655 pmap = pvo->pvo_pmap; 1656 PMAP_LOCK(pmap); 1657 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1658 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1659 pvo->pvo_pte.lpte.pte_lo |= lo; 1660 if (pt != -1) { 1661 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1662 pvo->pvo_vpn); 1663 if (pvo->pvo_pmap == kernel_pmap) 1664 isync(); 1665 } 1666 PMAP_UNLOCK(pmap); 1667 } 1668 UNLOCK_TABLE_RD(); 1669 m->md.mdpg_cache_attrs = ma; 1670 } 1671 1672 /* 1673 * Map a wired page into kernel virtual address space. 1674 */ 1675 void 1676 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1677 { 1678 uint64_t pte_lo; 1679 int error; 1680 1681 pte_lo = moea64_calc_wimg(pa, ma); 1682 1683 LOCK_TABLE_WR(); 1684 PMAP_LOCK(kernel_pmap); 1685 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1686 NULL, va, pa, pte_lo, PVO_WIRED, 0); 1687 PMAP_UNLOCK(kernel_pmap); 1688 UNLOCK_TABLE_WR(); 1689 1690 if (error != 0 && error != ENOENT) 1691 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1692 pa, error); 1693 } 1694 1695 void 1696 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1697 { 1698 1699 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1700 } 1701 1702 /* 1703 * Extract the physical page address associated with the given kernel virtual 1704 * address. 1705 */ 1706 vm_paddr_t 1707 moea64_kextract(mmu_t mmu, vm_offset_t va) 1708 { 1709 struct pvo_entry *pvo; 1710 vm_paddr_t pa; 1711 1712 /* 1713 * Shortcut the direct-mapped case when applicable. We never put 1714 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1715 */ 1716 if (va < VM_MIN_KERNEL_ADDRESS) 1717 return (va); 1718 1719 PMAP_LOCK(kernel_pmap); 1720 pvo = moea64_pvo_find_va(kernel_pmap, va); 1721 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1722 va)); 1723 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1724 PMAP_UNLOCK(kernel_pmap); 1725 return (pa); 1726 } 1727 1728 /* 1729 * Remove a wired page from kernel virtual address space. 1730 */ 1731 void 1732 moea64_kremove(mmu_t mmu, vm_offset_t va) 1733 { 1734 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1735 } 1736 1737 /* 1738 * Map a range of physical addresses into kernel virtual address space. 1739 * 1740 * The value passed in *virt is a suggested virtual address for the mapping. 1741 * Architectures which can support a direct-mapped physical to virtual region 1742 * can return the appropriate address within that region, leaving '*virt' 1743 * unchanged. We cannot and therefore do not; *virt is updated with the 1744 * first usable address after the mapped region. 1745 */ 1746 vm_offset_t 1747 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1748 vm_paddr_t pa_end, int prot) 1749 { 1750 vm_offset_t sva, va; 1751 1752 sva = *virt; 1753 va = sva; 1754 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1755 moea64_kenter(mmu, va, pa_start); 1756 *virt = va; 1757 1758 return (sva); 1759 } 1760 1761 /* 1762 * Returns true if the pmap's pv is one of the first 1763 * 16 pvs linked to from this page. This count may 1764 * be changed upwards or downwards in the future; it 1765 * is only necessary that true be returned for a small 1766 * subset of pmaps for proper page aging. 1767 */ 1768 boolean_t 1769 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1770 { 1771 int loops; 1772 struct pvo_entry *pvo; 1773 boolean_t rv; 1774 1775 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1776 ("moea64_page_exists_quick: page %p is not managed", m)); 1777 loops = 0; 1778 rv = FALSE; 1779 LOCK_TABLE_RD(); 1780 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1781 if (pvo->pvo_pmap == pmap) { 1782 rv = TRUE; 1783 break; 1784 } 1785 if (++loops >= 16) 1786 break; 1787 } 1788 UNLOCK_TABLE_RD(); 1789 return (rv); 1790 } 1791 1792 /* 1793 * Return the number of managed mappings to the given physical page 1794 * that are wired. 1795 */ 1796 int 1797 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1798 { 1799 struct pvo_entry *pvo; 1800 int count; 1801 1802 count = 0; 1803 if ((m->oflags & VPO_UNMANAGED) != 0) 1804 return (count); 1805 LOCK_TABLE_RD(); 1806 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1807 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1808 count++; 1809 UNLOCK_TABLE_RD(); 1810 return (count); 1811 } 1812 1813 static uintptr_t moea64_vsidcontext; 1814 1815 uintptr_t 1816 moea64_get_unique_vsid(void) { 1817 u_int entropy; 1818 register_t hash; 1819 uint32_t mask; 1820 int i; 1821 1822 entropy = 0; 1823 __asm __volatile("mftb %0" : "=r"(entropy)); 1824 1825 mtx_lock(&moea64_slb_mutex); 1826 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1827 u_int n; 1828 1829 /* 1830 * Create a new value by mutiplying by a prime and adding in 1831 * entropy from the timebase register. This is to make the 1832 * VSID more random so that the PT hash function collides 1833 * less often. (Note that the prime casues gcc to do shifts 1834 * instead of a multiply.) 1835 */ 1836 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1837 hash = moea64_vsidcontext & (NVSIDS - 1); 1838 if (hash == 0) /* 0 is special, avoid it */ 1839 continue; 1840 n = hash >> 5; 1841 mask = 1 << (hash & (VSID_NBPW - 1)); 1842 hash = (moea64_vsidcontext & VSID_HASHMASK); 1843 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1844 /* anything free in this bucket? */ 1845 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1846 entropy = (moea64_vsidcontext >> 20); 1847 continue; 1848 } 1849 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1850 mask = 1 << i; 1851 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1852 hash |= i; 1853 } 1854 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1855 ("Allocating in-use VSID %#zx\n", hash)); 1856 moea64_vsid_bitmap[n] |= mask; 1857 mtx_unlock(&moea64_slb_mutex); 1858 return (hash); 1859 } 1860 1861 mtx_unlock(&moea64_slb_mutex); 1862 panic("%s: out of segments",__func__); 1863 } 1864 1865 #ifdef __powerpc64__ 1866 void 1867 moea64_pinit(mmu_t mmu, pmap_t pmap) 1868 { 1869 1870 RB_INIT(&pmap->pmap_pvo); 1871 1872 pmap->pm_slb_tree_root = slb_alloc_tree(); 1873 pmap->pm_slb = slb_alloc_user_cache(); 1874 pmap->pm_slb_len = 0; 1875 } 1876 #else 1877 void 1878 moea64_pinit(mmu_t mmu, pmap_t pmap) 1879 { 1880 int i; 1881 uint32_t hash; 1882 1883 RB_INIT(&pmap->pmap_pvo); 1884 1885 if (pmap_bootstrapped) 1886 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1887 (vm_offset_t)pmap); 1888 else 1889 pmap->pmap_phys = pmap; 1890 1891 /* 1892 * Allocate some segment registers for this pmap. 1893 */ 1894 hash = moea64_get_unique_vsid(); 1895 1896 for (i = 0; i < 16; i++) 1897 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1898 1899 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1900 } 1901 #endif 1902 1903 /* 1904 * Initialize the pmap associated with process 0. 1905 */ 1906 void 1907 moea64_pinit0(mmu_t mmu, pmap_t pm) 1908 { 1909 1910 PMAP_LOCK_INIT(pm); 1911 moea64_pinit(mmu, pm); 1912 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1913 } 1914 1915 /* 1916 * Set the physical protection on the specified range of this map as requested. 1917 */ 1918 static void 1919 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1920 { 1921 uintptr_t pt; 1922 struct vm_page *pg; 1923 uint64_t oldlo; 1924 1925 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1926 1927 /* 1928 * Grab the PTE pointer before we diddle with the cached PTE 1929 * copy. 1930 */ 1931 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1932 1933 /* 1934 * Change the protection of the page. 1935 */ 1936 oldlo = pvo->pvo_pte.lpte.pte_lo; 1937 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1938 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1939 if ((prot & VM_PROT_EXECUTE) == 0) 1940 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1941 if (prot & VM_PROT_WRITE) 1942 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW; 1943 else 1944 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1945 1946 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1947 1948 /* 1949 * If the PVO is in the page table, update that pte as well. 1950 */ 1951 if (pt != -1) 1952 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1953 pvo->pvo_vpn); 1954 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1955 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1956 if ((pg->oflags & VPO_UNMANAGED) == 0) 1957 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1958 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1959 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE); 1960 } 1961 1962 /* 1963 * Update vm about the REF/CHG bits if the page is managed and we have 1964 * removed write access. 1965 */ 1966 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && 1967 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) { 1968 if (pg != NULL) { 1969 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 1970 vm_page_dirty(pg); 1971 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 1972 vm_page_aflag_set(pg, PGA_REFERENCED); 1973 } 1974 } 1975 } 1976 1977 void 1978 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1979 vm_prot_t prot) 1980 { 1981 struct pvo_entry *pvo, *tpvo, key; 1982 1983 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 1984 sva, eva, prot); 1985 1986 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1987 ("moea64_protect: non current pmap")); 1988 1989 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1990 moea64_remove(mmu, pm, sva, eva); 1991 return; 1992 } 1993 1994 LOCK_TABLE_RD(); 1995 PMAP_LOCK(pm); 1996 key.pvo_vaddr = sva; 1997 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1998 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1999 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2000 moea64_pvo_protect(mmu, pm, pvo, prot); 2001 } 2002 UNLOCK_TABLE_RD(); 2003 PMAP_UNLOCK(pm); 2004 } 2005 2006 /* 2007 * Map a list of wired pages into kernel virtual address space. This is 2008 * intended for temporary mappings which do not need page modification or 2009 * references recorded. Existing mappings in the region are overwritten. 2010 */ 2011 void 2012 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2013 { 2014 while (count-- > 0) { 2015 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2016 va += PAGE_SIZE; 2017 m++; 2018 } 2019 } 2020 2021 /* 2022 * Remove page mappings from kernel virtual address space. Intended for 2023 * temporary mappings entered by moea64_qenter. 2024 */ 2025 void 2026 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2027 { 2028 while (count-- > 0) { 2029 moea64_kremove(mmu, va); 2030 va += PAGE_SIZE; 2031 } 2032 } 2033 2034 void 2035 moea64_release_vsid(uint64_t vsid) 2036 { 2037 int idx, mask; 2038 2039 mtx_lock(&moea64_slb_mutex); 2040 idx = vsid & (NVSIDS-1); 2041 mask = 1 << (idx % VSID_NBPW); 2042 idx /= VSID_NBPW; 2043 KASSERT(moea64_vsid_bitmap[idx] & mask, 2044 ("Freeing unallocated VSID %#jx", vsid)); 2045 moea64_vsid_bitmap[idx] &= ~mask; 2046 mtx_unlock(&moea64_slb_mutex); 2047 } 2048 2049 2050 void 2051 moea64_release(mmu_t mmu, pmap_t pmap) 2052 { 2053 2054 /* 2055 * Free segment registers' VSIDs 2056 */ 2057 #ifdef __powerpc64__ 2058 slb_free_tree(pmap); 2059 slb_free_user_cache(pmap->pm_slb); 2060 #else 2061 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2062 2063 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2064 #endif 2065 } 2066 2067 /* 2068 * Remove all pages mapped by the specified pmap 2069 */ 2070 void 2071 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2072 { 2073 struct pvo_entry *pvo, *tpvo; 2074 2075 LOCK_TABLE_WR(); 2076 PMAP_LOCK(pm); 2077 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2078 if (!(pvo->pvo_vaddr & PVO_WIRED)) 2079 moea64_pvo_remove(mmu, pvo); 2080 } 2081 UNLOCK_TABLE_WR(); 2082 PMAP_UNLOCK(pm); 2083 } 2084 2085 /* 2086 * Remove the given range of addresses from the specified map. 2087 */ 2088 void 2089 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2090 { 2091 struct pvo_entry *pvo, *tpvo, key; 2092 2093 /* 2094 * Perform an unsynchronized read. This is, however, safe. 2095 */ 2096 if (pm->pm_stats.resident_count == 0) 2097 return; 2098 2099 LOCK_TABLE_WR(); 2100 PMAP_LOCK(pm); 2101 key.pvo_vaddr = sva; 2102 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2103 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2104 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2105 moea64_pvo_remove(mmu, pvo); 2106 } 2107 UNLOCK_TABLE_WR(); 2108 PMAP_UNLOCK(pm); 2109 } 2110 2111 /* 2112 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2113 * will reflect changes in pte's back to the vm_page. 2114 */ 2115 void 2116 moea64_remove_all(mmu_t mmu, vm_page_t m) 2117 { 2118 struct pvo_entry *pvo, *next_pvo; 2119 pmap_t pmap; 2120 2121 LOCK_TABLE_WR(); 2122 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2123 pmap = pvo->pvo_pmap; 2124 PMAP_LOCK(pmap); 2125 moea64_pvo_remove(mmu, pvo); 2126 PMAP_UNLOCK(pmap); 2127 } 2128 UNLOCK_TABLE_WR(); 2129 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m)) 2130 vm_page_dirty(m); 2131 vm_page_aflag_clear(m, PGA_WRITEABLE); 2132 vm_page_aflag_clear(m, PGA_EXECUTABLE); 2133 } 2134 2135 /* 2136 * Allocate a physical page of memory directly from the phys_avail map. 2137 * Can only be called from moea64_bootstrap before avail start and end are 2138 * calculated. 2139 */ 2140 vm_offset_t 2141 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2142 { 2143 vm_offset_t s, e; 2144 int i, j; 2145 2146 size = round_page(size); 2147 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2148 if (align != 0) 2149 s = (phys_avail[i] + align - 1) & ~(align - 1); 2150 else 2151 s = phys_avail[i]; 2152 e = s + size; 2153 2154 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2155 continue; 2156 2157 if (s + size > platform_real_maxaddr()) 2158 continue; 2159 2160 if (s == phys_avail[i]) { 2161 phys_avail[i] += size; 2162 } else if (e == phys_avail[i + 1]) { 2163 phys_avail[i + 1] -= size; 2164 } else { 2165 for (j = phys_avail_count * 2; j > i; j -= 2) { 2166 phys_avail[j] = phys_avail[j - 2]; 2167 phys_avail[j + 1] = phys_avail[j - 1]; 2168 } 2169 2170 phys_avail[i + 3] = phys_avail[i + 1]; 2171 phys_avail[i + 1] = s; 2172 phys_avail[i + 2] = e; 2173 phys_avail_count++; 2174 } 2175 2176 return (s); 2177 } 2178 panic("moea64_bootstrap_alloc: could not allocate memory"); 2179 } 2180 2181 static int 2182 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2183 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2184 uint64_t pte_lo, int flags, int8_t psind __unused) 2185 { 2186 struct pvo_entry *pvo; 2187 uintptr_t pt; 2188 uint64_t vsid; 2189 int first; 2190 u_int ptegidx; 2191 int i; 2192 int bootstrap; 2193 2194 /* 2195 * One nasty thing that can happen here is that the UMA calls to 2196 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2197 * which calls UMA... 2198 * 2199 * We break the loop by detecting recursion and allocating out of 2200 * the bootstrap pool. 2201 */ 2202 2203 first = 0; 2204 bootstrap = (flags & PVO_BOOTSTRAP); 2205 2206 if (!moea64_initialized) 2207 bootstrap = 1; 2208 2209 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2210 rw_assert(&moea64_table_lock, RA_WLOCKED); 2211 2212 /* 2213 * Compute the PTE Group index. 2214 */ 2215 va &= ~ADDR_POFF; 2216 vsid = va_to_vsid(pm, va); 2217 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2218 2219 /* 2220 * Remove any existing mapping for this page. Reuse the pvo entry if 2221 * there is a mapping. 2222 */ 2223 moea64_pvo_enter_calls++; 2224 2225 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2226 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2227 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2228 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2229 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2230 /* 2231 * The physical page and protection are not 2232 * changing. Instead, this may be a request 2233 * to change the mapping's wired attribute. 2234 */ 2235 pt = -1; 2236 if ((flags & PVO_WIRED) != 0 && 2237 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2238 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2239 pvo->pvo_vaddr |= PVO_WIRED; 2240 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2241 pm->pm_stats.wired_count++; 2242 } else if ((flags & PVO_WIRED) == 0 && 2243 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2244 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2245 pvo->pvo_vaddr &= ~PVO_WIRED; 2246 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 2247 pm->pm_stats.wired_count--; 2248 } 2249 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2250 KASSERT(pt == -1, 2251 ("moea64_pvo_enter: valid pt")); 2252 /* Re-insert if spilled */ 2253 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2254 &pvo->pvo_pte.lpte); 2255 if (i >= 0) 2256 PVO_PTEGIDX_SET(pvo, i); 2257 moea64_pte_overflow--; 2258 } else if (pt != -1) { 2259 /* 2260 * The PTE's wired attribute is not a 2261 * hardware feature, so there is no 2262 * need to invalidate any TLB entries. 2263 */ 2264 MOEA64_PTE_CHANGE(mmu, pt, 2265 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2266 } 2267 return (0); 2268 } 2269 moea64_pvo_remove(mmu, pvo); 2270 break; 2271 } 2272 } 2273 2274 /* 2275 * If we aren't overwriting a mapping, try to allocate. 2276 */ 2277 if (bootstrap) { 2278 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2279 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2280 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2281 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2282 } 2283 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2284 moea64_bpvo_pool_index++; 2285 bootstrap = 1; 2286 } else { 2287 pvo = uma_zalloc(zone, M_NOWAIT); 2288 } 2289 2290 if (pvo == NULL) 2291 return (ENOMEM); 2292 2293 moea64_pvo_entries++; 2294 pvo->pvo_vaddr = va; 2295 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2296 | (vsid << 16); 2297 pvo->pvo_pmap = pm; 2298 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2299 pvo->pvo_vaddr &= ~ADDR_POFF; 2300 2301 if (flags & PVO_WIRED) 2302 pvo->pvo_vaddr |= PVO_WIRED; 2303 if (pvo_head != NULL) 2304 pvo->pvo_vaddr |= PVO_MANAGED; 2305 if (bootstrap) 2306 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2307 if (flags & PVO_LARGE) 2308 pvo->pvo_vaddr |= PVO_LARGE; 2309 2310 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2311 (uint64_t)(pa) | pte_lo, flags); 2312 2313 /* 2314 * Add to pmap list 2315 */ 2316 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2317 2318 /* 2319 * Remember if the list was empty and therefore will be the first 2320 * item. 2321 */ 2322 if (pvo_head != NULL) { 2323 if (LIST_FIRST(pvo_head) == NULL) 2324 first = 1; 2325 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2326 } 2327 2328 if (pvo->pvo_vaddr & PVO_WIRED) { 2329 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2330 pm->pm_stats.wired_count++; 2331 } 2332 pm->pm_stats.resident_count++; 2333 2334 /* 2335 * We hope this succeeds but it isn't required. 2336 */ 2337 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2338 if (i >= 0) { 2339 PVO_PTEGIDX_SET(pvo, i); 2340 } else { 2341 panic("moea64_pvo_enter: overflow"); 2342 moea64_pte_overflow++; 2343 } 2344 2345 if (pm == kernel_pmap) 2346 isync(); 2347 2348 #ifdef __powerpc64__ 2349 /* 2350 * Make sure all our bootstrap mappings are in the SLB as soon 2351 * as virtual memory is switched on. 2352 */ 2353 if (!pmap_bootstrapped) 2354 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2355 #endif 2356 2357 return (first ? ENOENT : 0); 2358 } 2359 2360 static void 2361 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2362 { 2363 struct vm_page *pg; 2364 uintptr_t pt; 2365 2366 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2367 rw_assert(&moea64_table_lock, RA_WLOCKED); 2368 2369 /* 2370 * If there is an active pte entry, we need to deactivate it (and 2371 * save the ref & cfg bits). 2372 */ 2373 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2374 if (pt != -1) { 2375 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2376 PVO_PTEGIDX_CLR(pvo); 2377 } else { 2378 moea64_pte_overflow--; 2379 } 2380 2381 /* 2382 * Update our statistics. 2383 */ 2384 pvo->pvo_pmap->pm_stats.resident_count--; 2385 if (pvo->pvo_vaddr & PVO_WIRED) 2386 pvo->pvo_pmap->pm_stats.wired_count--; 2387 2388 /* 2389 * Remove this PVO from the pmap list. 2390 */ 2391 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2392 2393 /* 2394 * Remove this from the overflow list and return it to the pool 2395 * if we aren't going to reuse it. 2396 */ 2397 LIST_REMOVE(pvo, pvo_olink); 2398 2399 /* 2400 * Update vm about the REF/CHG bits if the page is managed. 2401 */ 2402 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2403 2404 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) { 2405 LIST_REMOVE(pvo, pvo_vlink); 2406 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 2407 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG) 2408 vm_page_dirty(pg); 2409 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF) 2410 vm_page_aflag_set(pg, PGA_REFERENCED); 2411 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2412 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2413 } 2414 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2415 vm_page_aflag_clear(pg, PGA_EXECUTABLE); 2416 } 2417 2418 moea64_pvo_entries--; 2419 moea64_pvo_remove_calls++; 2420 2421 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2422 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2423 moea64_upvo_zone, pvo); 2424 } 2425 2426 static struct pvo_entry * 2427 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2428 { 2429 struct pvo_entry key; 2430 2431 key.pvo_vaddr = va & ~ADDR_POFF; 2432 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2433 } 2434 2435 static boolean_t 2436 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2437 { 2438 struct pvo_entry *pvo; 2439 uintptr_t pt; 2440 2441 LOCK_TABLE_RD(); 2442 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2443 /* 2444 * See if we saved the bit off. If so, return success. 2445 */ 2446 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2447 UNLOCK_TABLE_RD(); 2448 return (TRUE); 2449 } 2450 } 2451 2452 /* 2453 * No luck, now go through the hard part of looking at the PTEs 2454 * themselves. Sync so that any pending REF/CHG bits are flushed to 2455 * the PTEs. 2456 */ 2457 powerpc_sync(); 2458 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2459 2460 /* 2461 * See if this pvo has a valid PTE. if so, fetch the 2462 * REF/CHG bits from the valid PTE. If the appropriate 2463 * ptebit is set, return success. 2464 */ 2465 PMAP_LOCK(pvo->pvo_pmap); 2466 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2467 if (pt != -1) { 2468 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2469 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2470 PMAP_UNLOCK(pvo->pvo_pmap); 2471 UNLOCK_TABLE_RD(); 2472 return (TRUE); 2473 } 2474 } 2475 PMAP_UNLOCK(pvo->pvo_pmap); 2476 } 2477 2478 UNLOCK_TABLE_RD(); 2479 return (FALSE); 2480 } 2481 2482 static u_int 2483 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2484 { 2485 u_int count; 2486 struct pvo_entry *pvo; 2487 uintptr_t pt; 2488 2489 /* 2490 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2491 * we can reset the right ones). note that since the pvo entries and 2492 * list heads are accessed via BAT0 and are never placed in the page 2493 * table, we don't have to worry about further accesses setting the 2494 * REF/CHG bits. 2495 */ 2496 powerpc_sync(); 2497 2498 /* 2499 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2500 * valid pte clear the ptebit from the valid pte. 2501 */ 2502 count = 0; 2503 LOCK_TABLE_RD(); 2504 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2505 PMAP_LOCK(pvo->pvo_pmap); 2506 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2507 if (pt != -1) { 2508 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2509 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2510 count++; 2511 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2512 pvo->pvo_vpn, ptebit); 2513 } 2514 } 2515 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2516 PMAP_UNLOCK(pvo->pvo_pmap); 2517 } 2518 2519 UNLOCK_TABLE_RD(); 2520 return (count); 2521 } 2522 2523 boolean_t 2524 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2525 { 2526 struct pvo_entry *pvo, key; 2527 vm_offset_t ppa; 2528 int error = 0; 2529 2530 PMAP_LOCK(kernel_pmap); 2531 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2532 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2533 ppa < pa + size; ppa += PAGE_SIZE, 2534 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2535 if (pvo == NULL || 2536 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2537 error = EFAULT; 2538 break; 2539 } 2540 } 2541 PMAP_UNLOCK(kernel_pmap); 2542 2543 return (error); 2544 } 2545 2546 /* 2547 * Map a set of physical memory pages into the kernel virtual 2548 * address space. Return a pointer to where it is mapped. This 2549 * routine is intended to be used for mapping device memory, 2550 * NOT real memory. 2551 */ 2552 void * 2553 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2554 { 2555 vm_offset_t va, tmpva, ppa, offset; 2556 2557 ppa = trunc_page(pa); 2558 offset = pa & PAGE_MASK; 2559 size = roundup2(offset + size, PAGE_SIZE); 2560 2561 va = kva_alloc(size); 2562 2563 if (!va) 2564 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2565 2566 for (tmpva = va; size > 0;) { 2567 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2568 size -= PAGE_SIZE; 2569 tmpva += PAGE_SIZE; 2570 ppa += PAGE_SIZE; 2571 } 2572 2573 return ((void *)(va + offset)); 2574 } 2575 2576 void * 2577 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2578 { 2579 2580 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2581 } 2582 2583 void 2584 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2585 { 2586 vm_offset_t base, offset; 2587 2588 base = trunc_page(va); 2589 offset = va & PAGE_MASK; 2590 size = roundup2(offset + size, PAGE_SIZE); 2591 2592 kva_free(base, size); 2593 } 2594 2595 void 2596 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2597 { 2598 struct pvo_entry *pvo; 2599 vm_offset_t lim; 2600 vm_paddr_t pa; 2601 vm_size_t len; 2602 2603 PMAP_LOCK(pm); 2604 while (sz > 0) { 2605 lim = round_page(va); 2606 len = MIN(lim - va, sz); 2607 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2608 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) { 2609 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 2610 (va & ADDR_POFF); 2611 moea64_syncicache(mmu, pm, va, pa, len); 2612 } 2613 va += len; 2614 sz -= len; 2615 } 2616 PMAP_UNLOCK(pm); 2617 } 2618 2619 void 2620 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2621 { 2622 2623 *va = (void *)pa; 2624 } 2625 2626 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2627 2628 void 2629 moea64_scan_init(mmu_t mmu) 2630 { 2631 struct pvo_entry *pvo; 2632 vm_offset_t va; 2633 int i; 2634 2635 if (!do_minidump) { 2636 /* Initialize phys. segments for dumpsys(). */ 2637 memset(&dump_map, 0, sizeof(dump_map)); 2638 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2639 for (i = 0; i < pregions_sz; i++) { 2640 dump_map[i].pa_start = pregions[i].mr_start; 2641 dump_map[i].pa_size = pregions[i].mr_size; 2642 } 2643 return; 2644 } 2645 2646 /* Virtual segments for minidumps: */ 2647 memset(&dump_map, 0, sizeof(dump_map)); 2648 2649 /* 1st: kernel .data and .bss. */ 2650 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2651 dump_map[0].pa_size = round_page((uintptr_t)_end) - dump_map[0].pa_start; 2652 2653 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2654 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2655 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2656 2657 /* 3rd: kernel VM. */ 2658 va = dump_map[1].pa_start + dump_map[1].pa_size; 2659 /* Find start of next chunk (from va). */ 2660 while (va < virtual_end) { 2661 /* Don't dump the buffer cache. */ 2662 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2663 va = kmi.buffer_eva; 2664 continue; 2665 } 2666 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2667 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2668 break; 2669 va += PAGE_SIZE; 2670 } 2671 if (va < virtual_end) { 2672 dump_map[2].pa_start = va; 2673 va += PAGE_SIZE; 2674 /* Find last page in chunk. */ 2675 while (va < virtual_end) { 2676 /* Don't run into the buffer cache. */ 2677 if (va == kmi.buffer_sva) 2678 break; 2679 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2680 if (pvo == NULL || 2681 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) 2682 break; 2683 va += PAGE_SIZE; 2684 } 2685 dump_map[2].pa_size = va - dump_map[2].pa_start; 2686 } 2687 } 2688