1 /*- 2 * Copyright (c) 2008-2015 Nathan Whitehorn 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Manages physical address maps. 32 * 33 * Since the information managed by this module is also stored by the 34 * logical address mapping module, this module may throw away valid virtual 35 * to physical mappings at almost any time. However, invalidations of 36 * mappings must be done as requested. 37 * 38 * In order to cope with hardware architectures which make virtual to 39 * physical map invalidates expensive, this module may delay invalidate 40 * reduced protection operations until such time as they are actually 41 * necessary. This module is given full information as to which processors 42 * are currently using which maps, and to when physical maps must be made 43 * correct. 44 */ 45 46 #include "opt_compat.h" 47 #include "opt_kstack_pages.h" 48 49 #include <sys/param.h> 50 #include <sys/kernel.h> 51 #include <sys/conf.h> 52 #include <sys/queue.h> 53 #include <sys/cpuset.h> 54 #include <sys/kerneldump.h> 55 #include <sys/ktr.h> 56 #include <sys/lock.h> 57 #include <sys/msgbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/mutex.h> 60 #include <sys/proc.h> 61 #include <sys/rwlock.h> 62 #include <sys/sched.h> 63 #include <sys/sysctl.h> 64 #include <sys/systm.h> 65 #include <sys/vmmeter.h> 66 #include <sys/smp.h> 67 68 #include <sys/kdb.h> 69 70 #include <dev/ofw/openfirm.h> 71 72 #include <vm/vm.h> 73 #include <vm/vm_param.h> 74 #include <vm/vm_kern.h> 75 #include <vm/vm_page.h> 76 #include <vm/vm_map.h> 77 #include <vm/vm_object.h> 78 #include <vm/vm_extern.h> 79 #include <vm/vm_pageout.h> 80 #include <vm/uma.h> 81 82 #include <machine/_inttypes.h> 83 #include <machine/cpu.h> 84 #include <machine/platform.h> 85 #include <machine/frame.h> 86 #include <machine/md_var.h> 87 #include <machine/psl.h> 88 #include <machine/bat.h> 89 #include <machine/hid.h> 90 #include <machine/pte.h> 91 #include <machine/sr.h> 92 #include <machine/trap.h> 93 #include <machine/mmuvar.h> 94 95 #include "mmu_oea64.h" 96 #include "mmu_if.h" 97 #include "moea64_if.h" 98 99 void moea64_release_vsid(uint64_t vsid); 100 uintptr_t moea64_get_unique_vsid(void); 101 102 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 103 #define ENABLE_TRANS(msr) mtmsr(msr) 104 105 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 106 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 107 #define VSID_HASH_MASK 0x0000007fffffffffULL 108 109 /* 110 * Locking semantics: 111 * 112 * There are two locks of interest: the page locks and the pmap locks, which 113 * protect their individual PVO lists and are locked in that order. The contents 114 * of all PVO entries are protected by the locks of their respective pmaps. 115 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 116 * into any list. 117 * 118 */ 119 120 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 121 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 122 123 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 124 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 125 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 126 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 127 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 128 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 129 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 130 131 struct ofw_map { 132 cell_t om_va; 133 cell_t om_len; 134 uint64_t om_pa; 135 cell_t om_mode; 136 }; 137 138 extern unsigned char _etext[]; 139 extern unsigned char _end[]; 140 141 /* 142 * Map of physical memory regions. 143 */ 144 static struct mem_region *regions; 145 static struct mem_region *pregions; 146 static u_int phys_avail_count; 147 static int regions_sz, pregions_sz; 148 149 extern void bs_remap_earlyboot(void); 150 151 /* 152 * Lock for the SLB tables. 153 */ 154 struct mtx moea64_slb_mutex; 155 156 /* 157 * PTEG data. 158 */ 159 u_int moea64_pteg_count; 160 u_int moea64_pteg_mask; 161 162 /* 163 * PVO data. 164 */ 165 166 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 167 168 static struct pvo_entry *moea64_bpvo_pool; 169 static int moea64_bpvo_pool_index = 0; 170 static int moea64_bpvo_pool_size = 327680; 171 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 172 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 173 &moea64_bpvo_pool_index, 0, ""); 174 175 #define VSID_NBPW (sizeof(u_int32_t) * 8) 176 #ifdef __powerpc64__ 177 #define NVSIDS (NPMAPS * 16) 178 #define VSID_HASHMASK 0xffffffffUL 179 #else 180 #define NVSIDS NPMAPS 181 #define VSID_HASHMASK 0xfffffUL 182 #endif 183 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 184 185 static boolean_t moea64_initialized = FALSE; 186 187 /* 188 * Statistics. 189 */ 190 u_int moea64_pte_valid = 0; 191 u_int moea64_pte_overflow = 0; 192 u_int moea64_pvo_entries = 0; 193 u_int moea64_pvo_enter_calls = 0; 194 u_int moea64_pvo_remove_calls = 0; 195 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 196 &moea64_pte_valid, 0, ""); 197 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 198 &moea64_pte_overflow, 0, ""); 199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 200 &moea64_pvo_entries, 0, ""); 201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 202 &moea64_pvo_enter_calls, 0, ""); 203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 204 &moea64_pvo_remove_calls, 0, ""); 205 206 vm_offset_t moea64_scratchpage_va[2]; 207 struct pvo_entry *moea64_scratchpage_pvo[2]; 208 struct mtx moea64_scratchpage_mtx; 209 210 uint64_t moea64_large_page_mask = 0; 211 uint64_t moea64_large_page_size = 0; 212 int moea64_large_page_shift = 0; 213 214 /* 215 * PVO calls. 216 */ 217 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 218 struct pvo_head *pvo_head); 219 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 220 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 221 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 222 223 /* 224 * Utility routines. 225 */ 226 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 227 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 228 static void moea64_kremove(mmu_t, vm_offset_t); 229 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 230 vm_paddr_t pa, vm_size_t sz); 231 static void moea64_pmap_init_qpages(void); 232 233 /* 234 * Kernel MMU interface 235 */ 236 void moea64_clear_modify(mmu_t, vm_page_t); 237 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 238 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 239 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 240 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 241 u_int flags, int8_t psind); 242 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 243 vm_prot_t); 244 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 245 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 246 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 247 void moea64_init(mmu_t); 248 boolean_t moea64_is_modified(mmu_t, vm_page_t); 249 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 250 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 251 int moea64_ts_referenced(mmu_t, vm_page_t); 252 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 253 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 254 int moea64_page_wired_mappings(mmu_t, vm_page_t); 255 void moea64_pinit(mmu_t, pmap_t); 256 void moea64_pinit0(mmu_t, pmap_t); 257 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 258 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 259 void moea64_qremove(mmu_t, vm_offset_t, int); 260 void moea64_release(mmu_t, pmap_t); 261 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 262 void moea64_remove_pages(mmu_t, pmap_t); 263 void moea64_remove_all(mmu_t, vm_page_t); 264 void moea64_remove_write(mmu_t, vm_page_t); 265 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 266 void moea64_zero_page(mmu_t, vm_page_t); 267 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 268 void moea64_zero_page_idle(mmu_t, vm_page_t); 269 void moea64_activate(mmu_t, struct thread *); 270 void moea64_deactivate(mmu_t, struct thread *); 271 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 272 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 273 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 274 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 275 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 276 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 277 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 278 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 279 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 280 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 281 void **va); 282 void moea64_scan_init(mmu_t mmu); 283 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 284 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 285 286 static mmu_method_t moea64_methods[] = { 287 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 288 MMUMETHOD(mmu_copy_page, moea64_copy_page), 289 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 290 MMUMETHOD(mmu_enter, moea64_enter), 291 MMUMETHOD(mmu_enter_object, moea64_enter_object), 292 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 293 MMUMETHOD(mmu_extract, moea64_extract), 294 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 295 MMUMETHOD(mmu_init, moea64_init), 296 MMUMETHOD(mmu_is_modified, moea64_is_modified), 297 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 298 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 299 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 300 MMUMETHOD(mmu_map, moea64_map), 301 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 302 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 303 MMUMETHOD(mmu_pinit, moea64_pinit), 304 MMUMETHOD(mmu_pinit0, moea64_pinit0), 305 MMUMETHOD(mmu_protect, moea64_protect), 306 MMUMETHOD(mmu_qenter, moea64_qenter), 307 MMUMETHOD(mmu_qremove, moea64_qremove), 308 MMUMETHOD(mmu_release, moea64_release), 309 MMUMETHOD(mmu_remove, moea64_remove), 310 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 311 MMUMETHOD(mmu_remove_all, moea64_remove_all), 312 MMUMETHOD(mmu_remove_write, moea64_remove_write), 313 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 314 MMUMETHOD(mmu_unwire, moea64_unwire), 315 MMUMETHOD(mmu_zero_page, moea64_zero_page), 316 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 317 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 318 MMUMETHOD(mmu_activate, moea64_activate), 319 MMUMETHOD(mmu_deactivate, moea64_deactivate), 320 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 321 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 322 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 323 324 /* Internal interfaces */ 325 MMUMETHOD(mmu_mapdev, moea64_mapdev), 326 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 327 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 328 MMUMETHOD(mmu_kextract, moea64_kextract), 329 MMUMETHOD(mmu_kenter, moea64_kenter), 330 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 331 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 332 MMUMETHOD(mmu_scan_init, moea64_scan_init), 333 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 334 335 { 0, 0 } 336 }; 337 338 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 339 340 static struct pvo_head * 341 vm_page_to_pvoh(vm_page_t m) 342 { 343 344 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 345 return (&m->md.mdpg_pvoh); 346 } 347 348 static struct pvo_entry * 349 alloc_pvo_entry(int bootstrap) 350 { 351 struct pvo_entry *pvo; 352 353 if (!moea64_initialized || bootstrap) { 354 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 355 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 356 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 357 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 358 } 359 pvo = &moea64_bpvo_pool[ 360 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 361 bzero(pvo, sizeof(*pvo)); 362 pvo->pvo_vaddr = PVO_BOOTSTRAP; 363 } else { 364 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 365 bzero(pvo, sizeof(*pvo)); 366 } 367 368 return (pvo); 369 } 370 371 372 static void 373 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 374 { 375 uint64_t vsid; 376 uint64_t hash; 377 int shift; 378 379 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 380 381 pvo->pvo_pmap = pmap; 382 va &= ~ADDR_POFF; 383 pvo->pvo_vaddr |= va; 384 vsid = va_to_vsid(pmap, va); 385 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 386 | (vsid << 16); 387 388 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 389 ADDR_PIDX_SHFT; 390 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 391 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 392 } 393 394 static void 395 free_pvo_entry(struct pvo_entry *pvo) 396 { 397 398 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 399 uma_zfree(moea64_pvo_zone, pvo); 400 } 401 402 void 403 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 404 { 405 406 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 407 LPTE_AVPN_MASK; 408 lpte->pte_hi |= LPTE_VALID; 409 410 if (pvo->pvo_vaddr & PVO_LARGE) 411 lpte->pte_hi |= LPTE_BIG; 412 if (pvo->pvo_vaddr & PVO_WIRED) 413 lpte->pte_hi |= LPTE_WIRED; 414 if (pvo->pvo_vaddr & PVO_HID) 415 lpte->pte_hi |= LPTE_HID; 416 417 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 418 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 419 lpte->pte_lo |= LPTE_BW; 420 else 421 lpte->pte_lo |= LPTE_BR; 422 423 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 424 lpte->pte_lo |= LPTE_NOEXEC; 425 } 426 427 static __inline uint64_t 428 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 429 { 430 uint64_t pte_lo; 431 int i; 432 433 if (ma != VM_MEMATTR_DEFAULT) { 434 switch (ma) { 435 case VM_MEMATTR_UNCACHEABLE: 436 return (LPTE_I | LPTE_G); 437 case VM_MEMATTR_WRITE_COMBINING: 438 case VM_MEMATTR_WRITE_BACK: 439 case VM_MEMATTR_PREFETCHABLE: 440 return (LPTE_I); 441 case VM_MEMATTR_WRITE_THROUGH: 442 return (LPTE_W | LPTE_M); 443 } 444 } 445 446 /* 447 * Assume the page is cache inhibited and access is guarded unless 448 * it's in our available memory array. 449 */ 450 pte_lo = LPTE_I | LPTE_G; 451 for (i = 0; i < pregions_sz; i++) { 452 if ((pa >= pregions[i].mr_start) && 453 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 454 pte_lo &= ~(LPTE_I | LPTE_G); 455 pte_lo |= LPTE_M; 456 break; 457 } 458 } 459 460 return pte_lo; 461 } 462 463 /* 464 * Quick sort callout for comparing memory regions. 465 */ 466 static int om_cmp(const void *a, const void *b); 467 468 static int 469 om_cmp(const void *a, const void *b) 470 { 471 const struct ofw_map *mapa; 472 const struct ofw_map *mapb; 473 474 mapa = a; 475 mapb = b; 476 if (mapa->om_pa < mapb->om_pa) 477 return (-1); 478 else if (mapa->om_pa > mapb->om_pa) 479 return (1); 480 else 481 return (0); 482 } 483 484 static void 485 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 486 { 487 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 488 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 489 struct pvo_entry *pvo; 490 register_t msr; 491 vm_offset_t off; 492 vm_paddr_t pa_base; 493 int i, j; 494 495 bzero(translations, sz); 496 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 497 sizeof(acells)); 498 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 499 panic("moea64_bootstrap: can't get ofw translations"); 500 501 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 502 sz /= sizeof(cell_t); 503 for (i = 0, j = 0; i < sz; j++) { 504 translations[j].om_va = trans_cells[i++]; 505 translations[j].om_len = trans_cells[i++]; 506 translations[j].om_pa = trans_cells[i++]; 507 if (acells == 2) { 508 translations[j].om_pa <<= 32; 509 translations[j].om_pa |= trans_cells[i++]; 510 } 511 translations[j].om_mode = trans_cells[i++]; 512 } 513 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 514 i, sz)); 515 516 sz = j; 517 qsort(translations, sz, sizeof (*translations), om_cmp); 518 519 for (i = 0; i < sz; i++) { 520 pa_base = translations[i].om_pa; 521 #ifndef __powerpc64__ 522 if ((translations[i].om_pa >> 32) != 0) 523 panic("OFW translations above 32-bit boundary!"); 524 #endif 525 526 if (pa_base % PAGE_SIZE) 527 panic("OFW translation not page-aligned (phys)!"); 528 if (translations[i].om_va % PAGE_SIZE) 529 panic("OFW translation not page-aligned (virt)!"); 530 531 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 532 pa_base, translations[i].om_va, translations[i].om_len); 533 534 /* Now enter the pages for this mapping */ 535 536 DISABLE_TRANS(msr); 537 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 538 /* If this address is direct-mapped, skip remapping */ 539 if (hw_direct_map && translations[i].om_va == pa_base && 540 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 541 continue; 542 543 PMAP_LOCK(kernel_pmap); 544 pvo = moea64_pvo_find_va(kernel_pmap, 545 translations[i].om_va + off); 546 PMAP_UNLOCK(kernel_pmap); 547 if (pvo != NULL) 548 continue; 549 550 moea64_kenter(mmup, translations[i].om_va + off, 551 pa_base + off); 552 } 553 ENABLE_TRANS(msr); 554 } 555 } 556 557 #ifdef __powerpc64__ 558 static void 559 moea64_probe_large_page(void) 560 { 561 uint16_t pvr = mfpvr() >> 16; 562 563 switch (pvr) { 564 case IBM970: 565 case IBM970FX: 566 case IBM970MP: 567 powerpc_sync(); isync(); 568 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 569 powerpc_sync(); isync(); 570 571 /* FALLTHROUGH */ 572 default: 573 moea64_large_page_size = 0x1000000; /* 16 MB */ 574 moea64_large_page_shift = 24; 575 } 576 577 moea64_large_page_mask = moea64_large_page_size - 1; 578 } 579 580 static void 581 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 582 { 583 struct slb *cache; 584 struct slb entry; 585 uint64_t esid, slbe; 586 uint64_t i; 587 588 cache = PCPU_GET(slb); 589 esid = va >> ADDR_SR_SHFT; 590 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 591 592 for (i = 0; i < 64; i++) { 593 if (cache[i].slbe == (slbe | i)) 594 return; 595 } 596 597 entry.slbe = slbe; 598 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 599 if (large) 600 entry.slbv |= SLBV_L; 601 602 slb_insert_kernel(entry.slbe, entry.slbv); 603 } 604 #endif 605 606 static void 607 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 608 vm_offset_t kernelend) 609 { 610 struct pvo_entry *pvo; 611 register_t msr; 612 vm_paddr_t pa; 613 vm_offset_t size, off; 614 uint64_t pte_lo; 615 int i; 616 617 if (moea64_large_page_size == 0) 618 hw_direct_map = 0; 619 620 DISABLE_TRANS(msr); 621 if (hw_direct_map) { 622 PMAP_LOCK(kernel_pmap); 623 for (i = 0; i < pregions_sz; i++) { 624 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 625 pregions[i].mr_size; pa += moea64_large_page_size) { 626 pte_lo = LPTE_M; 627 628 pvo = alloc_pvo_entry(1 /* bootstrap */); 629 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 630 init_pvo_entry(pvo, kernel_pmap, pa); 631 632 /* 633 * Set memory access as guarded if prefetch within 634 * the page could exit the available physmem area. 635 */ 636 if (pa & moea64_large_page_mask) { 637 pa &= moea64_large_page_mask; 638 pte_lo |= LPTE_G; 639 } 640 if (pa + moea64_large_page_size > 641 pregions[i].mr_start + pregions[i].mr_size) 642 pte_lo |= LPTE_G; 643 644 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 645 VM_PROT_EXECUTE; 646 pvo->pvo_pte.pa = pa | pte_lo; 647 moea64_pvo_enter(mmup, pvo, NULL); 648 } 649 } 650 PMAP_UNLOCK(kernel_pmap); 651 } else { 652 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 653 off = (vm_offset_t)(moea64_bpvo_pool); 654 for (pa = off; pa < off + size; pa += PAGE_SIZE) 655 moea64_kenter(mmup, pa, pa); 656 657 /* 658 * Map certain important things, like ourselves. 659 * 660 * NOTE: We do not map the exception vector space. That code is 661 * used only in real mode, and leaving it unmapped allows us to 662 * catch NULL pointer deferences, instead of making NULL a valid 663 * address. 664 */ 665 666 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 667 pa += PAGE_SIZE) 668 moea64_kenter(mmup, pa, pa); 669 } 670 ENABLE_TRANS(msr); 671 672 /* 673 * Allow user to override unmapped_buf_allowed for testing. 674 * XXXKIB Only direct map implementation was tested. 675 */ 676 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 677 &unmapped_buf_allowed)) 678 unmapped_buf_allowed = hw_direct_map; 679 } 680 681 void 682 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 683 { 684 int i, j; 685 vm_size_t physsz, hwphyssz; 686 687 #ifndef __powerpc64__ 688 /* We don't have a direct map since there is no BAT */ 689 hw_direct_map = 0; 690 691 /* Make sure battable is zero, since we have no BAT */ 692 for (i = 0; i < 16; i++) { 693 battable[i].batu = 0; 694 battable[i].batl = 0; 695 } 696 #else 697 moea64_probe_large_page(); 698 699 /* Use a direct map if we have large page support */ 700 if (moea64_large_page_size > 0) 701 hw_direct_map = 1; 702 else 703 hw_direct_map = 0; 704 #endif 705 706 /* Get physical memory regions from firmware */ 707 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 708 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 709 710 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 711 panic("moea64_bootstrap: phys_avail too small"); 712 713 phys_avail_count = 0; 714 physsz = 0; 715 hwphyssz = 0; 716 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 717 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 718 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 719 regions[i].mr_start, regions[i].mr_start + 720 regions[i].mr_size, regions[i].mr_size); 721 if (hwphyssz != 0 && 722 (physsz + regions[i].mr_size) >= hwphyssz) { 723 if (physsz < hwphyssz) { 724 phys_avail[j] = regions[i].mr_start; 725 phys_avail[j + 1] = regions[i].mr_start + 726 hwphyssz - physsz; 727 physsz = hwphyssz; 728 phys_avail_count++; 729 } 730 break; 731 } 732 phys_avail[j] = regions[i].mr_start; 733 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 734 phys_avail_count++; 735 physsz += regions[i].mr_size; 736 } 737 738 /* Check for overlap with the kernel and exception vectors */ 739 for (j = 0; j < 2*phys_avail_count; j+=2) { 740 if (phys_avail[j] < EXC_LAST) 741 phys_avail[j] += EXC_LAST; 742 743 if (kernelstart >= phys_avail[j] && 744 kernelstart < phys_avail[j+1]) { 745 if (kernelend < phys_avail[j+1]) { 746 phys_avail[2*phys_avail_count] = 747 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 748 phys_avail[2*phys_avail_count + 1] = 749 phys_avail[j+1]; 750 phys_avail_count++; 751 } 752 753 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 754 } 755 756 if (kernelend >= phys_avail[j] && 757 kernelend < phys_avail[j+1]) { 758 if (kernelstart > phys_avail[j]) { 759 phys_avail[2*phys_avail_count] = phys_avail[j]; 760 phys_avail[2*phys_avail_count + 1] = 761 kernelstart & ~PAGE_MASK; 762 phys_avail_count++; 763 } 764 765 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 766 } 767 } 768 769 physmem = btoc(physsz); 770 771 #ifdef PTEGCOUNT 772 moea64_pteg_count = PTEGCOUNT; 773 #else 774 moea64_pteg_count = 0x1000; 775 776 while (moea64_pteg_count < physmem) 777 moea64_pteg_count <<= 1; 778 779 moea64_pteg_count >>= 1; 780 #endif /* PTEGCOUNT */ 781 } 782 783 void 784 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 785 { 786 int i; 787 788 /* 789 * Set PTEG mask 790 */ 791 moea64_pteg_mask = moea64_pteg_count - 1; 792 793 /* 794 * Initialize SLB table lock and page locks 795 */ 796 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 797 for (i = 0; i < PV_LOCK_COUNT; i++) 798 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 799 800 /* 801 * Initialise the bootstrap pvo pool. 802 */ 803 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 804 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 805 moea64_bpvo_pool_index = 0; 806 807 /* 808 * Make sure kernel vsid is allocated as well as VSID 0. 809 */ 810 #ifndef __powerpc64__ 811 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 812 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 813 moea64_vsid_bitmap[0] |= 1; 814 #endif 815 816 /* 817 * Initialize the kernel pmap (which is statically allocated). 818 */ 819 #ifdef __powerpc64__ 820 for (i = 0; i < 64; i++) { 821 pcpup->pc_slb[i].slbv = 0; 822 pcpup->pc_slb[i].slbe = 0; 823 } 824 #else 825 for (i = 0; i < 16; i++) 826 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 827 #endif 828 829 kernel_pmap->pmap_phys = kernel_pmap; 830 CPU_FILL(&kernel_pmap->pm_active); 831 RB_INIT(&kernel_pmap->pmap_pvo); 832 833 PMAP_LOCK_INIT(kernel_pmap); 834 835 /* 836 * Now map in all the other buffers we allocated earlier 837 */ 838 839 moea64_setup_direct_map(mmup, kernelstart, kernelend); 840 } 841 842 void 843 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 844 { 845 ihandle_t mmui; 846 phandle_t chosen; 847 phandle_t mmu; 848 ssize_t sz; 849 int i; 850 vm_offset_t pa, va; 851 void *dpcpu; 852 853 /* 854 * Set up the Open Firmware pmap and add its mappings if not in real 855 * mode. 856 */ 857 858 chosen = OF_finddevice("/chosen"); 859 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 860 mmu = OF_instance_to_package(mmui); 861 if (mmu == -1 || 862 (sz = OF_getproplen(mmu, "translations")) == -1) 863 sz = 0; 864 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 865 panic("moea64_bootstrap: too many ofw translations"); 866 867 if (sz > 0) 868 moea64_add_ofw_mappings(mmup, mmu, sz); 869 } 870 871 /* 872 * Calculate the last available physical address. 873 */ 874 for (i = 0; phys_avail[i + 2] != 0; i += 2) 875 ; 876 Maxmem = powerpc_btop(phys_avail[i + 1]); 877 878 /* 879 * Initialize MMU and remap early physical mappings 880 */ 881 MMU_CPU_BOOTSTRAP(mmup,0); 882 mtmsr(mfmsr() | PSL_DR | PSL_IR); 883 pmap_bootstrapped++; 884 bs_remap_earlyboot(); 885 886 /* 887 * Set the start and end of kva. 888 */ 889 virtual_avail = VM_MIN_KERNEL_ADDRESS; 890 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 891 892 /* 893 * Map the entire KVA range into the SLB. We must not fault there. 894 */ 895 #ifdef __powerpc64__ 896 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 897 moea64_bootstrap_slb_prefault(va, 0); 898 #endif 899 900 /* 901 * Figure out how far we can extend virtual_end into segment 16 902 * without running into existing mappings. Segment 16 is guaranteed 903 * to contain neither RAM nor devices (at least on Apple hardware), 904 * but will generally contain some OFW mappings we should not 905 * step on. 906 */ 907 908 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 909 PMAP_LOCK(kernel_pmap); 910 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 911 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 912 virtual_end += PAGE_SIZE; 913 PMAP_UNLOCK(kernel_pmap); 914 #endif 915 916 /* 917 * Allocate a kernel stack with a guard page for thread0 and map it 918 * into the kernel page map. 919 */ 920 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 921 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 922 virtual_avail = va + kstack_pages * PAGE_SIZE; 923 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 924 thread0.td_kstack = va; 925 thread0.td_kstack_pages = kstack_pages; 926 for (i = 0; i < kstack_pages; i++) { 927 moea64_kenter(mmup, va, pa); 928 pa += PAGE_SIZE; 929 va += PAGE_SIZE; 930 } 931 932 /* 933 * Allocate virtual address space for the message buffer. 934 */ 935 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 936 msgbufp = (struct msgbuf *)virtual_avail; 937 va = virtual_avail; 938 virtual_avail += round_page(msgbufsize); 939 while (va < virtual_avail) { 940 moea64_kenter(mmup, va, pa); 941 pa += PAGE_SIZE; 942 va += PAGE_SIZE; 943 } 944 945 /* 946 * Allocate virtual address space for the dynamic percpu area. 947 */ 948 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 949 dpcpu = (void *)virtual_avail; 950 va = virtual_avail; 951 virtual_avail += DPCPU_SIZE; 952 while (va < virtual_avail) { 953 moea64_kenter(mmup, va, pa); 954 pa += PAGE_SIZE; 955 va += PAGE_SIZE; 956 } 957 dpcpu_init(dpcpu, 0); 958 959 /* 960 * Allocate some things for page zeroing. We put this directly 961 * in the page table and use MOEA64_PTE_REPLACE to avoid any 962 * of the PVO book-keeping or other parts of the VM system 963 * from even knowing that this hack exists. 964 */ 965 966 if (!hw_direct_map) { 967 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 968 MTX_DEF); 969 for (i = 0; i < 2; i++) { 970 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 971 virtual_end -= PAGE_SIZE; 972 973 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 974 975 PMAP_LOCK(kernel_pmap); 976 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 977 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 978 PMAP_UNLOCK(kernel_pmap); 979 } 980 } 981 } 982 983 static void 984 moea64_pmap_init_qpages(void) 985 { 986 struct pcpu *pc; 987 int i; 988 989 if (hw_direct_map) 990 return; 991 992 CPU_FOREACH(i) { 993 pc = pcpu_find(i); 994 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 995 if (pc->pc_qmap_addr == 0) 996 panic("pmap_init_qpages: unable to allocate KVA"); 997 PMAP_LOCK(kernel_pmap); 998 pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 999 PMAP_UNLOCK(kernel_pmap); 1000 mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF); 1001 } 1002 } 1003 1004 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1005 1006 /* 1007 * Activate a user pmap. This mostly involves setting some non-CPU 1008 * state. 1009 */ 1010 void 1011 moea64_activate(mmu_t mmu, struct thread *td) 1012 { 1013 pmap_t pm; 1014 1015 pm = &td->td_proc->p_vmspace->vm_pmap; 1016 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1017 1018 #ifdef __powerpc64__ 1019 PCPU_SET(userslb, pm->pm_slb); 1020 __asm __volatile("slbmte %0, %1; isync" :: 1021 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1022 #else 1023 PCPU_SET(curpmap, pm->pmap_phys); 1024 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1025 #endif 1026 } 1027 1028 void 1029 moea64_deactivate(mmu_t mmu, struct thread *td) 1030 { 1031 pmap_t pm; 1032 1033 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1034 1035 pm = &td->td_proc->p_vmspace->vm_pmap; 1036 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1037 #ifdef __powerpc64__ 1038 PCPU_SET(userslb, NULL); 1039 #else 1040 PCPU_SET(curpmap, NULL); 1041 #endif 1042 } 1043 1044 void 1045 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1046 { 1047 struct pvo_entry key, *pvo; 1048 vm_page_t m; 1049 int64_t refchg; 1050 1051 key.pvo_vaddr = sva; 1052 PMAP_LOCK(pm); 1053 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1054 pvo != NULL && PVO_VADDR(pvo) < eva; 1055 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1056 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1057 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1058 pvo); 1059 pvo->pvo_vaddr &= ~PVO_WIRED; 1060 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1061 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1062 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1063 if (refchg < 0) 1064 refchg = LPTE_CHG; 1065 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1066 1067 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1068 if (refchg & LPTE_CHG) 1069 vm_page_dirty(m); 1070 if (refchg & LPTE_REF) 1071 vm_page_aflag_set(m, PGA_REFERENCED); 1072 } 1073 pm->pm_stats.wired_count--; 1074 } 1075 PMAP_UNLOCK(pm); 1076 } 1077 1078 /* 1079 * This goes through and sets the physical address of our 1080 * special scratch PTE to the PA we want to zero or copy. Because 1081 * of locking issues (this can get called in pvo_enter() by 1082 * the UMA allocator), we can't use most other utility functions here 1083 */ 1084 1085 static __inline 1086 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1087 1088 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1089 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1090 1091 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1092 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1093 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1094 MOEA64_PTE_INVALIDATE); 1095 isync(); 1096 } 1097 1098 void 1099 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1100 { 1101 vm_offset_t dst; 1102 vm_offset_t src; 1103 1104 dst = VM_PAGE_TO_PHYS(mdst); 1105 src = VM_PAGE_TO_PHYS(msrc); 1106 1107 if (hw_direct_map) { 1108 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1109 } else { 1110 mtx_lock(&moea64_scratchpage_mtx); 1111 1112 moea64_set_scratchpage_pa(mmu, 0, src); 1113 moea64_set_scratchpage_pa(mmu, 1, dst); 1114 1115 bcopy((void *)moea64_scratchpage_va[0], 1116 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1117 1118 mtx_unlock(&moea64_scratchpage_mtx); 1119 } 1120 } 1121 1122 static inline void 1123 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1124 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1125 { 1126 void *a_cp, *b_cp; 1127 vm_offset_t a_pg_offset, b_pg_offset; 1128 int cnt; 1129 1130 while (xfersize > 0) { 1131 a_pg_offset = a_offset & PAGE_MASK; 1132 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1133 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1134 a_pg_offset; 1135 b_pg_offset = b_offset & PAGE_MASK; 1136 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1137 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1138 b_pg_offset; 1139 bcopy(a_cp, b_cp, cnt); 1140 a_offset += cnt; 1141 b_offset += cnt; 1142 xfersize -= cnt; 1143 } 1144 } 1145 1146 static inline void 1147 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1148 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1149 { 1150 void *a_cp, *b_cp; 1151 vm_offset_t a_pg_offset, b_pg_offset; 1152 int cnt; 1153 1154 mtx_lock(&moea64_scratchpage_mtx); 1155 while (xfersize > 0) { 1156 a_pg_offset = a_offset & PAGE_MASK; 1157 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1158 moea64_set_scratchpage_pa(mmu, 0, 1159 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1160 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1161 b_pg_offset = b_offset & PAGE_MASK; 1162 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1163 moea64_set_scratchpage_pa(mmu, 1, 1164 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1165 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1166 bcopy(a_cp, b_cp, cnt); 1167 a_offset += cnt; 1168 b_offset += cnt; 1169 xfersize -= cnt; 1170 } 1171 mtx_unlock(&moea64_scratchpage_mtx); 1172 } 1173 1174 void 1175 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1176 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1177 { 1178 1179 if (hw_direct_map) { 1180 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1181 xfersize); 1182 } else { 1183 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1184 xfersize); 1185 } 1186 } 1187 1188 void 1189 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1190 { 1191 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1192 1193 if (size + off > PAGE_SIZE) 1194 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1195 1196 if (hw_direct_map) { 1197 bzero((caddr_t)pa + off, size); 1198 } else { 1199 mtx_lock(&moea64_scratchpage_mtx); 1200 moea64_set_scratchpage_pa(mmu, 0, pa); 1201 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1202 mtx_unlock(&moea64_scratchpage_mtx); 1203 } 1204 } 1205 1206 /* 1207 * Zero a page of physical memory by temporarily mapping it 1208 */ 1209 void 1210 moea64_zero_page(mmu_t mmu, vm_page_t m) 1211 { 1212 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1213 vm_offset_t va, off; 1214 1215 if (!hw_direct_map) { 1216 mtx_lock(&moea64_scratchpage_mtx); 1217 1218 moea64_set_scratchpage_pa(mmu, 0, pa); 1219 va = moea64_scratchpage_va[0]; 1220 } else { 1221 va = pa; 1222 } 1223 1224 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1225 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1226 1227 if (!hw_direct_map) 1228 mtx_unlock(&moea64_scratchpage_mtx); 1229 } 1230 1231 void 1232 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1233 { 1234 1235 moea64_zero_page(mmu, m); 1236 } 1237 1238 vm_offset_t 1239 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1240 { 1241 struct pvo_entry *pvo; 1242 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1243 1244 if (hw_direct_map) 1245 return (pa); 1246 1247 /* 1248 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1249 * a critical section and access the PCPU data like on i386. 1250 * Instead, pin the thread and grab the PCPU lock to prevent 1251 * a preempting thread from using the same PCPU data. 1252 */ 1253 sched_pin(); 1254 1255 mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED); 1256 pvo = PCPU_GET(qmap_pvo); 1257 1258 mtx_lock(PCPU_PTR(qmap_lock)); 1259 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1260 (uint64_t)pa; 1261 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1262 isync(); 1263 1264 return (PCPU_GET(qmap_addr)); 1265 } 1266 1267 void 1268 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1269 { 1270 if (hw_direct_map) 1271 return; 1272 1273 mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED); 1274 KASSERT(PCPU_GET(qmap_addr) == addr, 1275 ("moea64_quick_remove_page: invalid address")); 1276 mtx_unlock(PCPU_PTR(qmap_lock)); 1277 sched_unpin(); 1278 } 1279 1280 /* 1281 * Map the given physical page at the specified virtual address in the 1282 * target pmap with the protection requested. If specified the page 1283 * will be wired down. 1284 */ 1285 1286 int 1287 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1288 vm_prot_t prot, u_int flags, int8_t psind) 1289 { 1290 struct pvo_entry *pvo, *oldpvo; 1291 struct pvo_head *pvo_head; 1292 uint64_t pte_lo; 1293 int error; 1294 1295 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1296 VM_OBJECT_ASSERT_LOCKED(m->object); 1297 1298 pvo = alloc_pvo_entry(0); 1299 pvo->pvo_pmap = NULL; /* to be filled in later */ 1300 pvo->pvo_pte.prot = prot; 1301 1302 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1303 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1304 1305 if ((flags & PMAP_ENTER_WIRED) != 0) 1306 pvo->pvo_vaddr |= PVO_WIRED; 1307 1308 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1309 pvo_head = NULL; 1310 } else { 1311 pvo_head = &m->md.mdpg_pvoh; 1312 pvo->pvo_vaddr |= PVO_MANAGED; 1313 } 1314 1315 for (;;) { 1316 PV_PAGE_LOCK(m); 1317 PMAP_LOCK(pmap); 1318 if (pvo->pvo_pmap == NULL) 1319 init_pvo_entry(pvo, pmap, va); 1320 if (prot & VM_PROT_WRITE) 1321 if (pmap_bootstrapped && 1322 (m->oflags & VPO_UNMANAGED) == 0) 1323 vm_page_aflag_set(m, PGA_WRITEABLE); 1324 1325 oldpvo = moea64_pvo_find_va(pmap, va); 1326 if (oldpvo != NULL) { 1327 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1328 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1329 oldpvo->pvo_pte.prot == prot) { 1330 /* Identical mapping already exists */ 1331 error = 0; 1332 1333 /* If not in page table, reinsert it */ 1334 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1335 moea64_pte_overflow--; 1336 MOEA64_PTE_INSERT(mmu, oldpvo); 1337 } 1338 1339 /* Then just clean up and go home */ 1340 PV_PAGE_UNLOCK(m); 1341 PMAP_UNLOCK(pmap); 1342 free_pvo_entry(pvo); 1343 break; 1344 } 1345 1346 /* Otherwise, need to kill it first */ 1347 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1348 "mapping does not match new mapping")); 1349 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1350 } 1351 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1352 PV_PAGE_UNLOCK(m); 1353 PMAP_UNLOCK(pmap); 1354 1355 /* Free any dead pages */ 1356 if (oldpvo != NULL) { 1357 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1358 moea64_pvo_remove_from_page(mmu, oldpvo); 1359 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1360 free_pvo_entry(oldpvo); 1361 } 1362 1363 if (error != ENOMEM) 1364 break; 1365 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1366 return (KERN_RESOURCE_SHORTAGE); 1367 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1368 VM_WAIT; 1369 } 1370 1371 /* 1372 * Flush the page from the instruction cache if this page is 1373 * mapped executable and cacheable. 1374 */ 1375 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1376 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1377 vm_page_aflag_set(m, PGA_EXECUTABLE); 1378 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1379 } 1380 return (KERN_SUCCESS); 1381 } 1382 1383 static void 1384 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1385 vm_size_t sz) 1386 { 1387 1388 /* 1389 * This is much trickier than on older systems because 1390 * we can't sync the icache on physical addresses directly 1391 * without a direct map. Instead we check a couple of cases 1392 * where the memory is already mapped in and, failing that, 1393 * use the same trick we use for page zeroing to create 1394 * a temporary mapping for this physical address. 1395 */ 1396 1397 if (!pmap_bootstrapped) { 1398 /* 1399 * If PMAP is not bootstrapped, we are likely to be 1400 * in real mode. 1401 */ 1402 __syncicache((void *)pa, sz); 1403 } else if (pmap == kernel_pmap) { 1404 __syncicache((void *)va, sz); 1405 } else if (hw_direct_map) { 1406 __syncicache((void *)pa, sz); 1407 } else { 1408 /* Use the scratch page to set up a temp mapping */ 1409 1410 mtx_lock(&moea64_scratchpage_mtx); 1411 1412 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1413 __syncicache((void *)(moea64_scratchpage_va[1] + 1414 (va & ADDR_POFF)), sz); 1415 1416 mtx_unlock(&moea64_scratchpage_mtx); 1417 } 1418 } 1419 1420 /* 1421 * Maps a sequence of resident pages belonging to the same object. 1422 * The sequence begins with the given page m_start. This page is 1423 * mapped at the given virtual address start. Each subsequent page is 1424 * mapped at a virtual address that is offset from start by the same 1425 * amount as the page is offset from m_start within the object. The 1426 * last page in the sequence is the page with the largest offset from 1427 * m_start that can be mapped at a virtual address less than the given 1428 * virtual address end. Not every virtual page between start and end 1429 * is mapped; only those for which a resident page exists with the 1430 * corresponding offset from m_start are mapped. 1431 */ 1432 void 1433 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1434 vm_page_t m_start, vm_prot_t prot) 1435 { 1436 vm_page_t m; 1437 vm_pindex_t diff, psize; 1438 1439 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1440 1441 psize = atop(end - start); 1442 m = m_start; 1443 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1444 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1445 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1446 m = TAILQ_NEXT(m, listq); 1447 } 1448 } 1449 1450 void 1451 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1452 vm_prot_t prot) 1453 { 1454 1455 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1456 PMAP_ENTER_NOSLEEP, 0); 1457 } 1458 1459 vm_paddr_t 1460 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1461 { 1462 struct pvo_entry *pvo; 1463 vm_paddr_t pa; 1464 1465 PMAP_LOCK(pm); 1466 pvo = moea64_pvo_find_va(pm, va); 1467 if (pvo == NULL) 1468 pa = 0; 1469 else 1470 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1471 PMAP_UNLOCK(pm); 1472 1473 return (pa); 1474 } 1475 1476 /* 1477 * Atomically extract and hold the physical page with the given 1478 * pmap and virtual address pair if that mapping permits the given 1479 * protection. 1480 */ 1481 vm_page_t 1482 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1483 { 1484 struct pvo_entry *pvo; 1485 vm_page_t m; 1486 vm_paddr_t pa; 1487 1488 m = NULL; 1489 pa = 0; 1490 PMAP_LOCK(pmap); 1491 retry: 1492 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1493 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1494 if (vm_page_pa_tryrelock(pmap, 1495 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1496 goto retry; 1497 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1498 vm_page_hold(m); 1499 } 1500 PA_UNLOCK_COND(pa); 1501 PMAP_UNLOCK(pmap); 1502 return (m); 1503 } 1504 1505 static mmu_t installed_mmu; 1506 1507 static void * 1508 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 1509 int wait) 1510 { 1511 struct pvo_entry *pvo; 1512 vm_offset_t va; 1513 vm_page_t m; 1514 int pflags, needed_lock; 1515 1516 /* 1517 * This entire routine is a horrible hack to avoid bothering kmem 1518 * for new KVA addresses. Because this can get called from inside 1519 * kmem allocation routines, calling kmem for a new address here 1520 * can lead to multiply locking non-recursive mutexes. 1521 */ 1522 1523 *flags = UMA_SLAB_PRIV; 1524 needed_lock = !PMAP_LOCKED(kernel_pmap); 1525 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1526 1527 for (;;) { 1528 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1529 if (m == NULL) { 1530 if (wait & M_NOWAIT) 1531 return (NULL); 1532 VM_WAIT; 1533 } else 1534 break; 1535 } 1536 1537 va = VM_PAGE_TO_PHYS(m); 1538 1539 pvo = alloc_pvo_entry(1 /* bootstrap */); 1540 1541 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1542 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1543 1544 if (needed_lock) 1545 PMAP_LOCK(kernel_pmap); 1546 1547 init_pvo_entry(pvo, kernel_pmap, va); 1548 pvo->pvo_vaddr |= PVO_WIRED; 1549 1550 moea64_pvo_enter(installed_mmu, pvo, NULL); 1551 1552 if (needed_lock) 1553 PMAP_UNLOCK(kernel_pmap); 1554 1555 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1556 bzero((void *)va, PAGE_SIZE); 1557 1558 return (void *)va; 1559 } 1560 1561 extern int elf32_nxstack; 1562 1563 void 1564 moea64_init(mmu_t mmu) 1565 { 1566 1567 CTR0(KTR_PMAP, "moea64_init"); 1568 1569 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1570 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1571 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1572 1573 if (!hw_direct_map) { 1574 installed_mmu = mmu; 1575 uma_zone_set_allocf(moea64_pvo_zone,moea64_uma_page_alloc); 1576 } 1577 1578 #ifdef COMPAT_FREEBSD32 1579 elf32_nxstack = 1; 1580 #endif 1581 1582 moea64_initialized = TRUE; 1583 } 1584 1585 boolean_t 1586 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1587 { 1588 1589 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1590 ("moea64_is_referenced: page %p is not managed", m)); 1591 1592 return (moea64_query_bit(mmu, m, LPTE_REF)); 1593 } 1594 1595 boolean_t 1596 moea64_is_modified(mmu_t mmu, vm_page_t m) 1597 { 1598 1599 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1600 ("moea64_is_modified: page %p is not managed", m)); 1601 1602 /* 1603 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1604 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1605 * is clear, no PTEs can have LPTE_CHG set. 1606 */ 1607 VM_OBJECT_ASSERT_LOCKED(m->object); 1608 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1609 return (FALSE); 1610 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1611 } 1612 1613 boolean_t 1614 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1615 { 1616 struct pvo_entry *pvo; 1617 boolean_t rv = TRUE; 1618 1619 PMAP_LOCK(pmap); 1620 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1621 if (pvo != NULL) 1622 rv = FALSE; 1623 PMAP_UNLOCK(pmap); 1624 return (rv); 1625 } 1626 1627 void 1628 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1629 { 1630 1631 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1632 ("moea64_clear_modify: page %p is not managed", m)); 1633 VM_OBJECT_ASSERT_WLOCKED(m->object); 1634 KASSERT(!vm_page_xbusied(m), 1635 ("moea64_clear_modify: page %p is exclusive busied", m)); 1636 1637 /* 1638 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1639 * set. If the object containing the page is locked and the page is 1640 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1641 */ 1642 if ((m->aflags & PGA_WRITEABLE) == 0) 1643 return; 1644 moea64_clear_bit(mmu, m, LPTE_CHG); 1645 } 1646 1647 /* 1648 * Clear the write and modified bits in each of the given page's mappings. 1649 */ 1650 void 1651 moea64_remove_write(mmu_t mmu, vm_page_t m) 1652 { 1653 struct pvo_entry *pvo; 1654 int64_t refchg, ret; 1655 pmap_t pmap; 1656 1657 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1658 ("moea64_remove_write: page %p is not managed", m)); 1659 1660 /* 1661 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1662 * set by another thread while the object is locked. Thus, 1663 * if PGA_WRITEABLE is clear, no page table entries need updating. 1664 */ 1665 VM_OBJECT_ASSERT_WLOCKED(m->object); 1666 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1667 return; 1668 powerpc_sync(); 1669 PV_PAGE_LOCK(m); 1670 refchg = 0; 1671 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1672 pmap = pvo->pvo_pmap; 1673 PMAP_LOCK(pmap); 1674 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1675 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1676 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1677 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1678 MOEA64_PTE_PROT_UPDATE); 1679 if (ret < 0) 1680 ret = LPTE_CHG; 1681 refchg |= ret; 1682 if (pvo->pvo_pmap == kernel_pmap) 1683 isync(); 1684 } 1685 PMAP_UNLOCK(pmap); 1686 } 1687 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1688 vm_page_dirty(m); 1689 vm_page_aflag_clear(m, PGA_WRITEABLE); 1690 PV_PAGE_UNLOCK(m); 1691 } 1692 1693 /* 1694 * moea64_ts_referenced: 1695 * 1696 * Return a count of reference bits for a page, clearing those bits. 1697 * It is not necessary for every reference bit to be cleared, but it 1698 * is necessary that 0 only be returned when there are truly no 1699 * reference bits set. 1700 * 1701 * XXX: The exact number of bits to check and clear is a matter that 1702 * should be tested and standardized at some point in the future for 1703 * optimal aging of shared pages. 1704 */ 1705 int 1706 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1707 { 1708 1709 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1710 ("moea64_ts_referenced: page %p is not managed", m)); 1711 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1712 } 1713 1714 /* 1715 * Modify the WIMG settings of all mappings for a page. 1716 */ 1717 void 1718 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1719 { 1720 struct pvo_entry *pvo; 1721 int64_t refchg; 1722 pmap_t pmap; 1723 uint64_t lo; 1724 1725 if ((m->oflags & VPO_UNMANAGED) != 0) { 1726 m->md.mdpg_cache_attrs = ma; 1727 return; 1728 } 1729 1730 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1731 1732 PV_PAGE_LOCK(m); 1733 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1734 pmap = pvo->pvo_pmap; 1735 PMAP_LOCK(pmap); 1736 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1737 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1738 pvo->pvo_pte.pa |= lo; 1739 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1740 MOEA64_PTE_INVALIDATE); 1741 if (refchg < 0) 1742 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1743 LPTE_CHG : 0; 1744 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1745 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1746 refchg |= 1747 atomic_readandclear_32(&m->md.mdpg_attrs); 1748 if (refchg & LPTE_CHG) 1749 vm_page_dirty(m); 1750 if (refchg & LPTE_REF) 1751 vm_page_aflag_set(m, PGA_REFERENCED); 1752 } 1753 if (pvo->pvo_pmap == kernel_pmap) 1754 isync(); 1755 } 1756 PMAP_UNLOCK(pmap); 1757 } 1758 m->md.mdpg_cache_attrs = ma; 1759 PV_PAGE_UNLOCK(m); 1760 } 1761 1762 /* 1763 * Map a wired page into kernel virtual address space. 1764 */ 1765 void 1766 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1767 { 1768 int error; 1769 struct pvo_entry *pvo, *oldpvo; 1770 1771 pvo = alloc_pvo_entry(0); 1772 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1773 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1774 pvo->pvo_vaddr |= PVO_WIRED; 1775 1776 PMAP_LOCK(kernel_pmap); 1777 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1778 if (oldpvo != NULL) 1779 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1780 init_pvo_entry(pvo, kernel_pmap, va); 1781 error = moea64_pvo_enter(mmu, pvo, NULL); 1782 PMAP_UNLOCK(kernel_pmap); 1783 1784 /* Free any dead pages */ 1785 if (oldpvo != NULL) { 1786 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1787 moea64_pvo_remove_from_page(mmu, oldpvo); 1788 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1789 free_pvo_entry(oldpvo); 1790 } 1791 1792 if (error != 0 && error != ENOENT) 1793 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1794 pa, error); 1795 } 1796 1797 void 1798 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1799 { 1800 1801 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1802 } 1803 1804 /* 1805 * Extract the physical page address associated with the given kernel virtual 1806 * address. 1807 */ 1808 vm_paddr_t 1809 moea64_kextract(mmu_t mmu, vm_offset_t va) 1810 { 1811 struct pvo_entry *pvo; 1812 vm_paddr_t pa; 1813 1814 /* 1815 * Shortcut the direct-mapped case when applicable. We never put 1816 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1817 */ 1818 if (va < VM_MIN_KERNEL_ADDRESS) 1819 return (va); 1820 1821 PMAP_LOCK(kernel_pmap); 1822 pvo = moea64_pvo_find_va(kernel_pmap, va); 1823 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1824 va)); 1825 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1826 PMAP_UNLOCK(kernel_pmap); 1827 return (pa); 1828 } 1829 1830 /* 1831 * Remove a wired page from kernel virtual address space. 1832 */ 1833 void 1834 moea64_kremove(mmu_t mmu, vm_offset_t va) 1835 { 1836 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1837 } 1838 1839 /* 1840 * Map a range of physical addresses into kernel virtual address space. 1841 * 1842 * The value passed in *virt is a suggested virtual address for the mapping. 1843 * Architectures which can support a direct-mapped physical to virtual region 1844 * can return the appropriate address within that region, leaving '*virt' 1845 * unchanged. Other architectures should map the pages starting at '*virt' and 1846 * update '*virt' with the first usable address after the mapped region. 1847 */ 1848 vm_offset_t 1849 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1850 vm_paddr_t pa_end, int prot) 1851 { 1852 vm_offset_t sva, va; 1853 1854 if (hw_direct_map) { 1855 /* 1856 * Check if every page in the region is covered by the direct 1857 * map. The direct map covers all of physical memory. Use 1858 * moea64_calc_wimg() as a shortcut to see if the page is in 1859 * physical memory as a way to see if the direct map covers it. 1860 */ 1861 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1862 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1863 break; 1864 if (va == pa_end) 1865 return (pa_start); 1866 } 1867 sva = *virt; 1868 va = sva; 1869 /* XXX respect prot argument */ 1870 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1871 moea64_kenter(mmu, va, pa_start); 1872 *virt = va; 1873 1874 return (sva); 1875 } 1876 1877 /* 1878 * Returns true if the pmap's pv is one of the first 1879 * 16 pvs linked to from this page. This count may 1880 * be changed upwards or downwards in the future; it 1881 * is only necessary that true be returned for a small 1882 * subset of pmaps for proper page aging. 1883 */ 1884 boolean_t 1885 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1886 { 1887 int loops; 1888 struct pvo_entry *pvo; 1889 boolean_t rv; 1890 1891 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1892 ("moea64_page_exists_quick: page %p is not managed", m)); 1893 loops = 0; 1894 rv = FALSE; 1895 PV_PAGE_LOCK(m); 1896 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1897 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 1898 rv = TRUE; 1899 break; 1900 } 1901 if (++loops >= 16) 1902 break; 1903 } 1904 PV_PAGE_UNLOCK(m); 1905 return (rv); 1906 } 1907 1908 /* 1909 * Return the number of managed mappings to the given physical page 1910 * that are wired. 1911 */ 1912 int 1913 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1914 { 1915 struct pvo_entry *pvo; 1916 int count; 1917 1918 count = 0; 1919 if ((m->oflags & VPO_UNMANAGED) != 0) 1920 return (count); 1921 PV_PAGE_LOCK(m); 1922 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1923 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 1924 count++; 1925 PV_PAGE_UNLOCK(m); 1926 return (count); 1927 } 1928 1929 static uintptr_t moea64_vsidcontext; 1930 1931 uintptr_t 1932 moea64_get_unique_vsid(void) { 1933 u_int entropy; 1934 register_t hash; 1935 uint32_t mask; 1936 int i; 1937 1938 entropy = 0; 1939 __asm __volatile("mftb %0" : "=r"(entropy)); 1940 1941 mtx_lock(&moea64_slb_mutex); 1942 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1943 u_int n; 1944 1945 /* 1946 * Create a new value by mutiplying by a prime and adding in 1947 * entropy from the timebase register. This is to make the 1948 * VSID more random so that the PT hash function collides 1949 * less often. (Note that the prime casues gcc to do shifts 1950 * instead of a multiply.) 1951 */ 1952 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1953 hash = moea64_vsidcontext & (NVSIDS - 1); 1954 if (hash == 0) /* 0 is special, avoid it */ 1955 continue; 1956 n = hash >> 5; 1957 mask = 1 << (hash & (VSID_NBPW - 1)); 1958 hash = (moea64_vsidcontext & VSID_HASHMASK); 1959 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1960 /* anything free in this bucket? */ 1961 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1962 entropy = (moea64_vsidcontext >> 20); 1963 continue; 1964 } 1965 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1966 mask = 1 << i; 1967 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1968 hash |= i; 1969 } 1970 if (hash == VSID_VRMA) /* also special, avoid this too */ 1971 continue; 1972 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1973 ("Allocating in-use VSID %#zx\n", hash)); 1974 moea64_vsid_bitmap[n] |= mask; 1975 mtx_unlock(&moea64_slb_mutex); 1976 return (hash); 1977 } 1978 1979 mtx_unlock(&moea64_slb_mutex); 1980 panic("%s: out of segments",__func__); 1981 } 1982 1983 #ifdef __powerpc64__ 1984 void 1985 moea64_pinit(mmu_t mmu, pmap_t pmap) 1986 { 1987 1988 RB_INIT(&pmap->pmap_pvo); 1989 1990 pmap->pm_slb_tree_root = slb_alloc_tree(); 1991 pmap->pm_slb = slb_alloc_user_cache(); 1992 pmap->pm_slb_len = 0; 1993 } 1994 #else 1995 void 1996 moea64_pinit(mmu_t mmu, pmap_t pmap) 1997 { 1998 int i; 1999 uint32_t hash; 2000 2001 RB_INIT(&pmap->pmap_pvo); 2002 2003 if (pmap_bootstrapped) 2004 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2005 (vm_offset_t)pmap); 2006 else 2007 pmap->pmap_phys = pmap; 2008 2009 /* 2010 * Allocate some segment registers for this pmap. 2011 */ 2012 hash = moea64_get_unique_vsid(); 2013 2014 for (i = 0; i < 16; i++) 2015 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2016 2017 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2018 } 2019 #endif 2020 2021 /* 2022 * Initialize the pmap associated with process 0. 2023 */ 2024 void 2025 moea64_pinit0(mmu_t mmu, pmap_t pm) 2026 { 2027 2028 PMAP_LOCK_INIT(pm); 2029 moea64_pinit(mmu, pm); 2030 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2031 } 2032 2033 /* 2034 * Set the physical protection on the specified range of this map as requested. 2035 */ 2036 static void 2037 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2038 { 2039 struct vm_page *pg; 2040 vm_prot_t oldprot; 2041 int32_t refchg; 2042 2043 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2044 2045 /* 2046 * Change the protection of the page. 2047 */ 2048 oldprot = pvo->pvo_pte.prot; 2049 pvo->pvo_pte.prot = prot; 2050 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2051 2052 /* 2053 * If the PVO is in the page table, update mapping 2054 */ 2055 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2056 if (refchg < 0) 2057 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2058 2059 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2060 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2061 if ((pg->oflags & VPO_UNMANAGED) == 0) 2062 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2063 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2064 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2065 } 2066 2067 /* 2068 * Update vm about the REF/CHG bits if the page is managed and we have 2069 * removed write access. 2070 */ 2071 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2072 (oldprot & VM_PROT_WRITE)) { 2073 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2074 if (refchg & LPTE_CHG) 2075 vm_page_dirty(pg); 2076 if (refchg & LPTE_REF) 2077 vm_page_aflag_set(pg, PGA_REFERENCED); 2078 } 2079 } 2080 2081 void 2082 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2083 vm_prot_t prot) 2084 { 2085 struct pvo_entry *pvo, *tpvo, key; 2086 2087 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2088 sva, eva, prot); 2089 2090 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2091 ("moea64_protect: non current pmap")); 2092 2093 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2094 moea64_remove(mmu, pm, sva, eva); 2095 return; 2096 } 2097 2098 PMAP_LOCK(pm); 2099 key.pvo_vaddr = sva; 2100 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2101 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2102 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2103 moea64_pvo_protect(mmu, pm, pvo, prot); 2104 } 2105 PMAP_UNLOCK(pm); 2106 } 2107 2108 /* 2109 * Map a list of wired pages into kernel virtual address space. This is 2110 * intended for temporary mappings which do not need page modification or 2111 * references recorded. Existing mappings in the region are overwritten. 2112 */ 2113 void 2114 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2115 { 2116 while (count-- > 0) { 2117 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2118 va += PAGE_SIZE; 2119 m++; 2120 } 2121 } 2122 2123 /* 2124 * Remove page mappings from kernel virtual address space. Intended for 2125 * temporary mappings entered by moea64_qenter. 2126 */ 2127 void 2128 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2129 { 2130 while (count-- > 0) { 2131 moea64_kremove(mmu, va); 2132 va += PAGE_SIZE; 2133 } 2134 } 2135 2136 void 2137 moea64_release_vsid(uint64_t vsid) 2138 { 2139 int idx, mask; 2140 2141 mtx_lock(&moea64_slb_mutex); 2142 idx = vsid & (NVSIDS-1); 2143 mask = 1 << (idx % VSID_NBPW); 2144 idx /= VSID_NBPW; 2145 KASSERT(moea64_vsid_bitmap[idx] & mask, 2146 ("Freeing unallocated VSID %#jx", vsid)); 2147 moea64_vsid_bitmap[idx] &= ~mask; 2148 mtx_unlock(&moea64_slb_mutex); 2149 } 2150 2151 2152 void 2153 moea64_release(mmu_t mmu, pmap_t pmap) 2154 { 2155 2156 /* 2157 * Free segment registers' VSIDs 2158 */ 2159 #ifdef __powerpc64__ 2160 slb_free_tree(pmap); 2161 slb_free_user_cache(pmap->pm_slb); 2162 #else 2163 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2164 2165 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2166 #endif 2167 } 2168 2169 /* 2170 * Remove all pages mapped by the specified pmap 2171 */ 2172 void 2173 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2174 { 2175 struct pvo_entry *pvo, *tpvo; 2176 struct pvo_tree tofree; 2177 2178 RB_INIT(&tofree); 2179 2180 PMAP_LOCK(pm); 2181 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2182 if (pvo->pvo_vaddr & PVO_WIRED) 2183 continue; 2184 2185 /* 2186 * For locking reasons, remove this from the page table and 2187 * pmap, but save delinking from the vm_page for a second 2188 * pass 2189 */ 2190 moea64_pvo_remove_from_pmap(mmu, pvo); 2191 RB_INSERT(pvo_tree, &tofree, pvo); 2192 } 2193 PMAP_UNLOCK(pm); 2194 2195 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2196 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2197 moea64_pvo_remove_from_page(mmu, pvo); 2198 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2199 RB_REMOVE(pvo_tree, &tofree, pvo); 2200 free_pvo_entry(pvo); 2201 } 2202 } 2203 2204 /* 2205 * Remove the given range of addresses from the specified map. 2206 */ 2207 void 2208 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2209 { 2210 struct pvo_entry *pvo, *tpvo, key; 2211 struct pvo_tree tofree; 2212 2213 /* 2214 * Perform an unsynchronized read. This is, however, safe. 2215 */ 2216 if (pm->pm_stats.resident_count == 0) 2217 return; 2218 2219 key.pvo_vaddr = sva; 2220 2221 RB_INIT(&tofree); 2222 2223 PMAP_LOCK(pm); 2224 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2225 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2226 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2227 2228 /* 2229 * For locking reasons, remove this from the page table and 2230 * pmap, but save delinking from the vm_page for a second 2231 * pass 2232 */ 2233 moea64_pvo_remove_from_pmap(mmu, pvo); 2234 RB_INSERT(pvo_tree, &tofree, pvo); 2235 } 2236 PMAP_UNLOCK(pm); 2237 2238 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2239 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2240 moea64_pvo_remove_from_page(mmu, pvo); 2241 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2242 RB_REMOVE(pvo_tree, &tofree, pvo); 2243 free_pvo_entry(pvo); 2244 } 2245 } 2246 2247 /* 2248 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2249 * will reflect changes in pte's back to the vm_page. 2250 */ 2251 void 2252 moea64_remove_all(mmu_t mmu, vm_page_t m) 2253 { 2254 struct pvo_entry *pvo, *next_pvo; 2255 struct pvo_head freequeue; 2256 int wasdead; 2257 pmap_t pmap; 2258 2259 LIST_INIT(&freequeue); 2260 2261 PV_PAGE_LOCK(m); 2262 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2263 pmap = pvo->pvo_pmap; 2264 PMAP_LOCK(pmap); 2265 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2266 if (!wasdead) 2267 moea64_pvo_remove_from_pmap(mmu, pvo); 2268 moea64_pvo_remove_from_page(mmu, pvo); 2269 if (!wasdead) 2270 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2271 PMAP_UNLOCK(pmap); 2272 2273 } 2274 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2275 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2276 PV_PAGE_UNLOCK(m); 2277 2278 /* Clean up UMA allocations */ 2279 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2280 free_pvo_entry(pvo); 2281 } 2282 2283 /* 2284 * Allocate a physical page of memory directly from the phys_avail map. 2285 * Can only be called from moea64_bootstrap before avail start and end are 2286 * calculated. 2287 */ 2288 vm_offset_t 2289 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2290 { 2291 vm_offset_t s, e; 2292 int i, j; 2293 2294 size = round_page(size); 2295 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2296 if (align != 0) 2297 s = (phys_avail[i] + align - 1) & ~(align - 1); 2298 else 2299 s = phys_avail[i]; 2300 e = s + size; 2301 2302 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2303 continue; 2304 2305 if (s + size > platform_real_maxaddr()) 2306 continue; 2307 2308 if (s == phys_avail[i]) { 2309 phys_avail[i] += size; 2310 } else if (e == phys_avail[i + 1]) { 2311 phys_avail[i + 1] -= size; 2312 } else { 2313 for (j = phys_avail_count * 2; j > i; j -= 2) { 2314 phys_avail[j] = phys_avail[j - 2]; 2315 phys_avail[j + 1] = phys_avail[j - 1]; 2316 } 2317 2318 phys_avail[i + 3] = phys_avail[i + 1]; 2319 phys_avail[i + 1] = s; 2320 phys_avail[i + 2] = e; 2321 phys_avail_count++; 2322 } 2323 2324 return (s); 2325 } 2326 panic("moea64_bootstrap_alloc: could not allocate memory"); 2327 } 2328 2329 static int 2330 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2331 { 2332 int first, err; 2333 2334 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2335 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2336 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2337 2338 moea64_pvo_enter_calls++; 2339 2340 /* 2341 * Add to pmap list 2342 */ 2343 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2344 2345 /* 2346 * Remember if the list was empty and therefore will be the first 2347 * item. 2348 */ 2349 if (pvo_head != NULL) { 2350 if (LIST_FIRST(pvo_head) == NULL) 2351 first = 1; 2352 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2353 } 2354 2355 if (pvo->pvo_vaddr & PVO_WIRED) 2356 pvo->pvo_pmap->pm_stats.wired_count++; 2357 pvo->pvo_pmap->pm_stats.resident_count++; 2358 2359 /* 2360 * Insert it into the hardware page table 2361 */ 2362 err = MOEA64_PTE_INSERT(mmu, pvo); 2363 if (err != 0) { 2364 panic("moea64_pvo_enter: overflow"); 2365 } 2366 2367 moea64_pvo_entries++; 2368 2369 if (pvo->pvo_pmap == kernel_pmap) 2370 isync(); 2371 2372 #ifdef __powerpc64__ 2373 /* 2374 * Make sure all our bootstrap mappings are in the SLB as soon 2375 * as virtual memory is switched on. 2376 */ 2377 if (!pmap_bootstrapped) 2378 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2379 pvo->pvo_vaddr & PVO_LARGE); 2380 #endif 2381 2382 return (first ? ENOENT : 0); 2383 } 2384 2385 static void 2386 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2387 { 2388 struct vm_page *pg; 2389 int32_t refchg; 2390 2391 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2392 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2393 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2394 2395 /* 2396 * If there is an active pte entry, we need to deactivate it 2397 */ 2398 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2399 if (refchg < 0) { 2400 /* 2401 * If it was evicted from the page table, be pessimistic and 2402 * dirty the page. 2403 */ 2404 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2405 refchg = LPTE_CHG; 2406 else 2407 refchg = 0; 2408 } 2409 2410 /* 2411 * Update our statistics. 2412 */ 2413 pvo->pvo_pmap->pm_stats.resident_count--; 2414 if (pvo->pvo_vaddr & PVO_WIRED) 2415 pvo->pvo_pmap->pm_stats.wired_count--; 2416 2417 /* 2418 * Remove this PVO from the pmap list. 2419 */ 2420 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2421 2422 /* 2423 * Mark this for the next sweep 2424 */ 2425 pvo->pvo_vaddr |= PVO_DEAD; 2426 2427 /* Send RC bits to VM */ 2428 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2429 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2430 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2431 if (pg != NULL) { 2432 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2433 if (refchg & LPTE_CHG) 2434 vm_page_dirty(pg); 2435 if (refchg & LPTE_REF) 2436 vm_page_aflag_set(pg, PGA_REFERENCED); 2437 } 2438 } 2439 } 2440 2441 static void 2442 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2443 { 2444 struct vm_page *pg; 2445 2446 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2447 2448 /* Use NULL pmaps as a sentinel for races in page deletion */ 2449 if (pvo->pvo_pmap == NULL) 2450 return; 2451 pvo->pvo_pmap = NULL; 2452 2453 /* 2454 * Update vm about page writeability/executability if managed 2455 */ 2456 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2457 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2458 2459 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) { 2460 LIST_REMOVE(pvo, pvo_vlink); 2461 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2462 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE); 2463 } 2464 2465 moea64_pvo_entries--; 2466 moea64_pvo_remove_calls++; 2467 } 2468 2469 static struct pvo_entry * 2470 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2471 { 2472 struct pvo_entry key; 2473 2474 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2475 2476 key.pvo_vaddr = va & ~ADDR_POFF; 2477 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2478 } 2479 2480 static boolean_t 2481 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2482 { 2483 struct pvo_entry *pvo; 2484 int64_t ret; 2485 boolean_t rv; 2486 2487 /* 2488 * See if this bit is stored in the page already. 2489 */ 2490 if (m->md.mdpg_attrs & ptebit) 2491 return (TRUE); 2492 2493 /* 2494 * Examine each PTE. Sync so that any pending REF/CHG bits are 2495 * flushed to the PTEs. 2496 */ 2497 rv = FALSE; 2498 powerpc_sync(); 2499 PV_PAGE_LOCK(m); 2500 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2501 ret = 0; 2502 2503 /* 2504 * See if this pvo has a valid PTE. if so, fetch the 2505 * REF/CHG bits from the valid PTE. If the appropriate 2506 * ptebit is set, return success. 2507 */ 2508 PMAP_LOCK(pvo->pvo_pmap); 2509 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2510 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2511 PMAP_UNLOCK(pvo->pvo_pmap); 2512 2513 if (ret > 0) { 2514 atomic_set_32(&m->md.mdpg_attrs, 2515 ret & (LPTE_CHG | LPTE_REF)); 2516 if (ret & ptebit) { 2517 rv = TRUE; 2518 break; 2519 } 2520 } 2521 } 2522 PV_PAGE_UNLOCK(m); 2523 2524 return (rv); 2525 } 2526 2527 static u_int 2528 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2529 { 2530 u_int count; 2531 struct pvo_entry *pvo; 2532 int64_t ret; 2533 2534 /* 2535 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2536 * we can reset the right ones). 2537 */ 2538 powerpc_sync(); 2539 2540 /* 2541 * For each pvo entry, clear the pte's ptebit. 2542 */ 2543 count = 0; 2544 PV_PAGE_LOCK(m); 2545 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2546 ret = 0; 2547 2548 PMAP_LOCK(pvo->pvo_pmap); 2549 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2550 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2551 PMAP_UNLOCK(pvo->pvo_pmap); 2552 2553 if (ret > 0 && (ret & ptebit)) 2554 count++; 2555 } 2556 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2557 PV_PAGE_UNLOCK(m); 2558 2559 return (count); 2560 } 2561 2562 boolean_t 2563 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2564 { 2565 struct pvo_entry *pvo, key; 2566 vm_offset_t ppa; 2567 int error = 0; 2568 2569 PMAP_LOCK(kernel_pmap); 2570 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2571 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2572 ppa < pa + size; ppa += PAGE_SIZE, 2573 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2574 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2575 error = EFAULT; 2576 break; 2577 } 2578 } 2579 PMAP_UNLOCK(kernel_pmap); 2580 2581 return (error); 2582 } 2583 2584 /* 2585 * Map a set of physical memory pages into the kernel virtual 2586 * address space. Return a pointer to where it is mapped. This 2587 * routine is intended to be used for mapping device memory, 2588 * NOT real memory. 2589 */ 2590 void * 2591 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2592 { 2593 vm_offset_t va, tmpva, ppa, offset; 2594 2595 ppa = trunc_page(pa); 2596 offset = pa & PAGE_MASK; 2597 size = roundup2(offset + size, PAGE_SIZE); 2598 2599 va = kva_alloc(size); 2600 2601 if (!va) 2602 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2603 2604 for (tmpva = va; size > 0;) { 2605 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2606 size -= PAGE_SIZE; 2607 tmpva += PAGE_SIZE; 2608 ppa += PAGE_SIZE; 2609 } 2610 2611 return ((void *)(va + offset)); 2612 } 2613 2614 void * 2615 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2616 { 2617 2618 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2619 } 2620 2621 void 2622 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2623 { 2624 vm_offset_t base, offset; 2625 2626 base = trunc_page(va); 2627 offset = va & PAGE_MASK; 2628 size = roundup2(offset + size, PAGE_SIZE); 2629 2630 kva_free(base, size); 2631 } 2632 2633 void 2634 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2635 { 2636 struct pvo_entry *pvo; 2637 vm_offset_t lim; 2638 vm_paddr_t pa; 2639 vm_size_t len; 2640 2641 PMAP_LOCK(pm); 2642 while (sz > 0) { 2643 lim = round_page(va); 2644 len = MIN(lim - va, sz); 2645 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2646 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2647 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2648 moea64_syncicache(mmu, pm, va, pa, len); 2649 } 2650 va += len; 2651 sz -= len; 2652 } 2653 PMAP_UNLOCK(pm); 2654 } 2655 2656 void 2657 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2658 { 2659 2660 *va = (void *)pa; 2661 } 2662 2663 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2664 2665 void 2666 moea64_scan_init(mmu_t mmu) 2667 { 2668 struct pvo_entry *pvo; 2669 vm_offset_t va; 2670 int i; 2671 2672 if (!do_minidump) { 2673 /* Initialize phys. segments for dumpsys(). */ 2674 memset(&dump_map, 0, sizeof(dump_map)); 2675 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2676 for (i = 0; i < pregions_sz; i++) { 2677 dump_map[i].pa_start = pregions[i].mr_start; 2678 dump_map[i].pa_size = pregions[i].mr_size; 2679 } 2680 return; 2681 } 2682 2683 /* Virtual segments for minidumps: */ 2684 memset(&dump_map, 0, sizeof(dump_map)); 2685 2686 /* 1st: kernel .data and .bss. */ 2687 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2688 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2689 dump_map[0].pa_start; 2690 2691 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2692 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2693 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2694 2695 /* 3rd: kernel VM. */ 2696 va = dump_map[1].pa_start + dump_map[1].pa_size; 2697 /* Find start of next chunk (from va). */ 2698 while (va < virtual_end) { 2699 /* Don't dump the buffer cache. */ 2700 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2701 va = kmi.buffer_eva; 2702 continue; 2703 } 2704 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2705 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2706 break; 2707 va += PAGE_SIZE; 2708 } 2709 if (va < virtual_end) { 2710 dump_map[2].pa_start = va; 2711 va += PAGE_SIZE; 2712 /* Find last page in chunk. */ 2713 while (va < virtual_end) { 2714 /* Don't run into the buffer cache. */ 2715 if (va == kmi.buffer_sva) 2716 break; 2717 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2718 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2719 break; 2720 va += PAGE_SIZE; 2721 } 2722 dump_map[2].pa_size = va - dump_map[2].pa_start; 2723 } 2724 } 2725 2726