1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/cpu.h> 146 #include <machine/platform.h> 147 #include <machine/frame.h> 148 #include <machine/md_var.h> 149 #include <machine/psl.h> 150 #include <machine/bat.h> 151 #include <machine/pte.h> 152 #include <machine/sr.h> 153 #include <machine/trap.h> 154 #include <machine/mmuvar.h> 155 156 #include "mmu_if.h" 157 158 #define MOEA_DEBUG 159 160 #define TODO panic("%s: not implemented", __func__); 161 162 static __inline u_int32_t 163 cntlzw(volatile u_int32_t a) { 164 u_int32_t b; 165 __asm ("cntlzw %0, %1" : "=r"(b) : "r"(a)); 166 return b; 167 } 168 169 static __inline uint64_t 170 va_to_vsid(pmap_t pm, vm_offset_t va) 171 { 172 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 173 } 174 175 #define TLBSYNC() __asm __volatile("tlbsync; ptesync"); 176 #define SYNC() __asm __volatile("sync"); 177 #define EIEIO() __asm __volatile("eieio"); 178 179 /* 180 * The tlbie instruction must be executed in 64-bit mode 181 * so we have to twiddle MSR[SF] around every invocation. 182 * Just to add to the fun, exceptions must be off as well 183 * so that we can't trap in 64-bit mode. What a pain. 184 */ 185 186 static __inline void 187 TLBIE(pmap_t pmap, vm_offset_t va) { 188 register_t msr; 189 register_t scratch; 190 191 uint64_t vpn; 192 register_t vpn_hi, vpn_lo; 193 194 #if 1 195 /* 196 * CPU documentation says that tlbie takes the VPN, not the 197 * VA. I think the code below does this correctly. We will see. 198 */ 199 200 vpn = (uint64_t)(va & ADDR_PIDX); 201 if (pmap != NULL) 202 vpn |= (va_to_vsid(pmap,va) << 28); 203 #else 204 vpn = va; 205 #endif 206 207 vpn_hi = (uint32_t)(vpn >> 32); 208 vpn_lo = (uint32_t)vpn; 209 210 __asm __volatile("\ 211 mfmsr %0; \ 212 clrldi %1,%0,49; \ 213 insrdi %1,1,1,0; \ 214 mtmsrd %1; \ 215 ptesync; \ 216 \ 217 sld %1,%2,%4; \ 218 or %1,%1,%3; \ 219 tlbie %1; \ 220 \ 221 mtmsrd %0; \ 222 eieio; \ 223 tlbsync; \ 224 ptesync;" 225 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32)); 226 } 227 228 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 229 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 230 231 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 232 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 233 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 234 235 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 236 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 237 #define PVO_WIRED 0x010 /* PVO entry is wired */ 238 #define PVO_MANAGED 0x020 /* PVO entry is managed */ 239 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 240 bootstrap */ 241 #define PVO_FAKE 0x100 /* fictitious phys page */ 242 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 243 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 244 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 245 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 246 #define PVO_PTEGIDX_CLR(pvo) \ 247 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 248 #define PVO_PTEGIDX_SET(pvo, i) \ 249 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 250 251 #define MOEA_PVO_CHECK(pvo) 252 253 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 254 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 255 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 256 257 struct ofw_map { 258 vm_offset_t om_va; 259 vm_size_t om_len; 260 vm_offset_t om_pa_hi; 261 vm_offset_t om_pa_lo; 262 u_int om_mode; 263 }; 264 265 /* 266 * Map of physical memory regions. 267 */ 268 static struct mem_region *regions; 269 static struct mem_region *pregions; 270 extern u_int phys_avail_count; 271 extern int regions_sz, pregions_sz; 272 extern int ofw_real_mode; 273 static struct ofw_map translations[64]; 274 275 extern struct pmap ofw_pmap; 276 277 extern void bs_remap_earlyboot(void); 278 279 280 /* 281 * Lock for the pteg and pvo tables. 282 */ 283 struct mtx moea64_table_mutex; 284 285 /* 286 * PTEG data. 287 */ 288 static struct lpteg *moea64_pteg_table; 289 u_int moea64_pteg_count; 290 u_int moea64_pteg_mask; 291 292 /* 293 * PVO data. 294 */ 295 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 296 /* lists of unmanaged pages */ 297 struct pvo_head moea64_pvo_kunmanaged = 298 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 299 struct pvo_head moea64_pvo_unmanaged = 300 LIST_HEAD_INITIALIZER(moea64_pvo_unmanaged); 301 302 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 303 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 304 305 vm_offset_t pvo_allocator_start; 306 vm_offset_t pvo_allocator_end; 307 308 #define BPVO_POOL_SIZE 327680 309 static struct pvo_entry *moea64_bpvo_pool; 310 static int moea64_bpvo_pool_index = 0; 311 312 #define VSID_NBPW (sizeof(u_int32_t) * 8) 313 static u_int moea64_vsid_bitmap[NPMAPS / VSID_NBPW]; 314 315 static boolean_t moea64_initialized = FALSE; 316 317 /* 318 * Statistics. 319 */ 320 u_int moea64_pte_valid = 0; 321 u_int moea64_pte_overflow = 0; 322 u_int moea64_pvo_entries = 0; 323 u_int moea64_pvo_enter_calls = 0; 324 u_int moea64_pvo_remove_calls = 0; 325 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 326 &moea64_pte_valid, 0, ""); 327 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 328 &moea64_pte_overflow, 0, ""); 329 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 330 &moea64_pvo_entries, 0, ""); 331 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 332 &moea64_pvo_enter_calls, 0, ""); 333 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 334 &moea64_pvo_remove_calls, 0, ""); 335 336 vm_offset_t moea64_scratchpage_va[2]; 337 struct pvo_entry *moea64_scratchpage_pvo[2]; 338 struct lpte *moea64_scratchpage_pte[2]; 339 struct mtx moea64_scratchpage_mtx; 340 341 /* 342 * Allocate physical memory for use in moea64_bootstrap. 343 */ 344 static vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int); 345 346 /* 347 * PTE calls. 348 */ 349 static int moea64_pte_insert(u_int, struct lpte *); 350 351 /* 352 * PVO calls. 353 */ 354 static int moea64_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 355 vm_offset_t, vm_offset_t, uint64_t, int, int); 356 static void moea64_pvo_remove(struct pvo_entry *, int); 357 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t, int *); 358 static struct lpte *moea64_pvo_to_pte(const struct pvo_entry *, int); 359 360 /* 361 * Utility routines. 362 */ 363 static void moea64_bridge_bootstrap(mmu_t mmup, 364 vm_offset_t kernelstart, vm_offset_t kernelend); 365 static void moea64_bridge_cpu_bootstrap(mmu_t, int ap); 366 static void moea64_enter_locked(pmap_t, vm_offset_t, vm_page_t, 367 vm_prot_t, boolean_t); 368 static boolean_t moea64_query_bit(vm_page_t, u_int64_t); 369 static u_int moea64_clear_bit(vm_page_t, u_int64_t, u_int64_t *); 370 static void moea64_kremove(mmu_t, vm_offset_t); 371 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 372 vm_offset_t pa, vm_size_t sz); 373 static void tlbia(void); 374 375 /* 376 * Kernel MMU interface 377 */ 378 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 379 void moea64_clear_modify(mmu_t, vm_page_t); 380 void moea64_clear_reference(mmu_t, vm_page_t); 381 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 382 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 383 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 384 vm_prot_t); 385 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 386 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 387 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 388 void moea64_init(mmu_t); 389 boolean_t moea64_is_modified(mmu_t, vm_page_t); 390 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 391 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 392 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 393 int moea64_page_wired_mappings(mmu_t, vm_page_t); 394 void moea64_pinit(mmu_t, pmap_t); 395 void moea64_pinit0(mmu_t, pmap_t); 396 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 397 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 398 void moea64_qremove(mmu_t, vm_offset_t, int); 399 void moea64_release(mmu_t, pmap_t); 400 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 401 void moea64_remove_all(mmu_t, vm_page_t); 402 void moea64_remove_write(mmu_t, vm_page_t); 403 void moea64_zero_page(mmu_t, vm_page_t); 404 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 405 void moea64_zero_page_idle(mmu_t, vm_page_t); 406 void moea64_activate(mmu_t, struct thread *); 407 void moea64_deactivate(mmu_t, struct thread *); 408 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 409 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 410 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 411 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 412 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 413 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 414 415 static mmu_method_t moea64_bridge_methods[] = { 416 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 417 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 418 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 419 MMUMETHOD(mmu_copy_page, moea64_copy_page), 420 MMUMETHOD(mmu_enter, moea64_enter), 421 MMUMETHOD(mmu_enter_object, moea64_enter_object), 422 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 423 MMUMETHOD(mmu_extract, moea64_extract), 424 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 425 MMUMETHOD(mmu_init, moea64_init), 426 MMUMETHOD(mmu_is_modified, moea64_is_modified), 427 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 428 MMUMETHOD(mmu_map, moea64_map), 429 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 430 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 431 MMUMETHOD(mmu_pinit, moea64_pinit), 432 MMUMETHOD(mmu_pinit0, moea64_pinit0), 433 MMUMETHOD(mmu_protect, moea64_protect), 434 MMUMETHOD(mmu_qenter, moea64_qenter), 435 MMUMETHOD(mmu_qremove, moea64_qremove), 436 MMUMETHOD(mmu_release, moea64_release), 437 MMUMETHOD(mmu_remove, moea64_remove), 438 MMUMETHOD(mmu_remove_all, moea64_remove_all), 439 MMUMETHOD(mmu_remove_write, moea64_remove_write), 440 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 441 MMUMETHOD(mmu_zero_page, moea64_zero_page), 442 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 443 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 444 MMUMETHOD(mmu_activate, moea64_activate), 445 MMUMETHOD(mmu_deactivate, moea64_deactivate), 446 447 /* Internal interfaces */ 448 MMUMETHOD(mmu_bootstrap, moea64_bridge_bootstrap), 449 MMUMETHOD(mmu_cpu_bootstrap, moea64_bridge_cpu_bootstrap), 450 MMUMETHOD(mmu_mapdev, moea64_mapdev), 451 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 452 MMUMETHOD(mmu_kextract, moea64_kextract), 453 MMUMETHOD(mmu_kenter, moea64_kenter), 454 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 455 456 { 0, 0 } 457 }; 458 459 static mmu_def_t oea64_bridge_mmu = { 460 MMU_TYPE_G5, 461 moea64_bridge_methods, 462 0 463 }; 464 MMU_DEF(oea64_bridge_mmu); 465 466 static __inline u_int 467 va_to_pteg(uint64_t vsid, vm_offset_t addr) 468 { 469 u_int hash; 470 471 hash = vsid ^ (((uint64_t)addr & ADDR_PIDX) >> 472 ADDR_PIDX_SHFT); 473 return (hash & moea64_pteg_mask); 474 } 475 476 static __inline struct pvo_head * 477 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 478 { 479 struct vm_page *pg; 480 481 pg = PHYS_TO_VM_PAGE(pa); 482 483 if (pg_p != NULL) 484 *pg_p = pg; 485 486 if (pg == NULL) 487 return (&moea64_pvo_unmanaged); 488 489 return (&pg->md.mdpg_pvoh); 490 } 491 492 static __inline struct pvo_head * 493 vm_page_to_pvoh(vm_page_t m) 494 { 495 496 return (&m->md.mdpg_pvoh); 497 } 498 499 static __inline void 500 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 501 { 502 503 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 504 m->md.mdpg_attrs &= ~ptebit; 505 } 506 507 static __inline u_int64_t 508 moea64_attr_fetch(vm_page_t m) 509 { 510 511 return (m->md.mdpg_attrs); 512 } 513 514 static __inline void 515 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 516 { 517 518 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 519 m->md.mdpg_attrs |= ptebit; 520 } 521 522 static __inline int 523 moea64_pte_compare(const struct lpte *pt, const struct lpte *pvo_pt) 524 { 525 if (pt->pte_hi == pvo_pt->pte_hi) 526 return (1); 527 528 return (0); 529 } 530 531 static __inline int 532 moea64_pte_match(struct lpte *pt, uint64_t vsid, vm_offset_t va, int which) 533 { 534 return (pt->pte_hi & ~LPTE_VALID) == 535 ((vsid << LPTE_VSID_SHIFT) | 536 ((uint64_t)(va >> ADDR_API_SHFT64) & LPTE_API) | which); 537 } 538 539 static __inline void 540 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 541 uint64_t pte_lo) 542 { 543 ASSERT_TABLE_LOCK(); 544 545 /* 546 * Construct a PTE. Default to IMB initially. Valid bit only gets 547 * set when the real pte is set in memory. 548 * 549 * Note: Don't set the valid bit for correct operation of tlb update. 550 */ 551 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 552 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 553 554 pt->pte_lo = pte_lo; 555 } 556 557 static __inline void 558 moea64_pte_synch(struct lpte *pt, struct lpte *pvo_pt) 559 { 560 561 ASSERT_TABLE_LOCK(); 562 563 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG); 564 } 565 566 static __inline void 567 moea64_pte_clear(struct lpte *pt, pmap_t pmap, vm_offset_t va, u_int64_t ptebit) 568 { 569 ASSERT_TABLE_LOCK(); 570 571 /* 572 * As shown in Section 7.6.3.2.3 573 */ 574 pt->pte_lo &= ~ptebit; 575 TLBIE(pmap,va); 576 } 577 578 static __inline void 579 moea64_pte_set(struct lpte *pt, struct lpte *pvo_pt) 580 { 581 582 ASSERT_TABLE_LOCK(); 583 pvo_pt->pte_hi |= LPTE_VALID; 584 585 /* 586 * Update the PTE as defined in section 7.6.3.1. 587 * Note that the REF/CHG bits are from pvo_pt and thus should have 588 * been saved so this routine can restore them (if desired). 589 */ 590 pt->pte_lo = pvo_pt->pte_lo; 591 EIEIO(); 592 pt->pte_hi = pvo_pt->pte_hi; 593 SYNC(); 594 moea64_pte_valid++; 595 } 596 597 static __inline void 598 moea64_pte_unset(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 599 { 600 ASSERT_TABLE_LOCK(); 601 pvo_pt->pte_hi &= ~LPTE_VALID; 602 603 /* 604 * Force the reg & chg bits back into the PTEs. 605 */ 606 SYNC(); 607 608 /* 609 * Invalidate the pte. 610 */ 611 pt->pte_hi &= ~LPTE_VALID; 612 613 TLBIE(pmap,va); 614 615 /* 616 * Save the reg & chg bits. 617 */ 618 moea64_pte_synch(pt, pvo_pt); 619 moea64_pte_valid--; 620 } 621 622 static __inline void 623 moea64_pte_change(struct lpte *pt, struct lpte *pvo_pt, pmap_t pmap, vm_offset_t va) 624 { 625 626 /* 627 * Invalidate the PTE 628 */ 629 moea64_pte_unset(pt, pvo_pt, pmap, va); 630 moea64_pte_set(pt, pvo_pt); 631 } 632 633 static __inline uint64_t 634 moea64_calc_wimg(vm_offset_t pa) 635 { 636 uint64_t pte_lo; 637 int i; 638 639 /* 640 * Assume the page is cache inhibited and access is guarded unless 641 * it's in our available memory array. 642 */ 643 pte_lo = LPTE_I | LPTE_G; 644 for (i = 0; i < pregions_sz; i++) { 645 if ((pa >= pregions[i].mr_start) && 646 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 647 pte_lo &= ~(LPTE_I | LPTE_G); 648 pte_lo |= LPTE_M; 649 break; 650 } 651 } 652 653 return pte_lo; 654 } 655 656 /* 657 * Quick sort callout for comparing memory regions. 658 */ 659 static int mr_cmp(const void *a, const void *b); 660 static int om_cmp(const void *a, const void *b); 661 662 static int 663 mr_cmp(const void *a, const void *b) 664 { 665 const struct mem_region *regiona; 666 const struct mem_region *regionb; 667 668 regiona = a; 669 regionb = b; 670 if (regiona->mr_start < regionb->mr_start) 671 return (-1); 672 else if (regiona->mr_start > regionb->mr_start) 673 return (1); 674 else 675 return (0); 676 } 677 678 static int 679 om_cmp(const void *a, const void *b) 680 { 681 const struct ofw_map *mapa; 682 const struct ofw_map *mapb; 683 684 mapa = a; 685 mapb = b; 686 if (mapa->om_pa_hi < mapb->om_pa_hi) 687 return (-1); 688 else if (mapa->om_pa_hi > mapb->om_pa_hi) 689 return (1); 690 else if (mapa->om_pa_lo < mapb->om_pa_lo) 691 return (-1); 692 else if (mapa->om_pa_lo > mapb->om_pa_lo) 693 return (1); 694 else 695 return (0); 696 } 697 698 static void 699 moea64_bridge_cpu_bootstrap(mmu_t mmup, int ap) 700 { 701 int i = 0; 702 703 /* 704 * Initialize segment registers and MMU 705 */ 706 707 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync(); 708 for (i = 0; i < 16; i++) { 709 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 710 } 711 __asm __volatile ("sync; mtsdr1 %0; isync" 712 :: "r"((u_int)moea64_pteg_table 713 | (32 - cntlzw(moea64_pteg_mask >> 11)))); 714 tlbia(); 715 } 716 717 static void 718 moea64_bridge_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 719 { 720 ihandle_t mmui; 721 phandle_t chosen; 722 phandle_t mmu; 723 int sz; 724 int i, j; 725 int ofw_mappings; 726 vm_size_t size, physsz, hwphyssz; 727 vm_offset_t pa, va, off; 728 uint32_t msr; 729 void *dpcpu; 730 731 /* We don't have a direct map since there is no BAT */ 732 hw_direct_map = 0; 733 734 /* Make sure battable is zero, since we have no BAT */ 735 for (i = 0; i < 16; i++) { 736 battable[i].batu = 0; 737 battable[i].batl = 0; 738 } 739 740 /* Get physical memory regions from firmware */ 741 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 742 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 743 744 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 745 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 746 panic("moea64_bootstrap: phys_avail too small"); 747 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 748 phys_avail_count = 0; 749 physsz = 0; 750 hwphyssz = 0; 751 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 752 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 753 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 754 regions[i].mr_start + regions[i].mr_size, 755 regions[i].mr_size); 756 if (hwphyssz != 0 && 757 (physsz + regions[i].mr_size) >= hwphyssz) { 758 if (physsz < hwphyssz) { 759 phys_avail[j] = regions[i].mr_start; 760 phys_avail[j + 1] = regions[i].mr_start + 761 hwphyssz - physsz; 762 physsz = hwphyssz; 763 phys_avail_count++; 764 } 765 break; 766 } 767 phys_avail[j] = regions[i].mr_start; 768 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 769 phys_avail_count++; 770 physsz += regions[i].mr_size; 771 } 772 physmem = btoc(physsz); 773 774 /* 775 * Allocate PTEG table. 776 */ 777 #ifdef PTEGCOUNT 778 moea64_pteg_count = PTEGCOUNT; 779 #else 780 moea64_pteg_count = 0x1000; 781 782 while (moea64_pteg_count < physmem) 783 moea64_pteg_count <<= 1; 784 #endif /* PTEGCOUNT */ 785 786 size = moea64_pteg_count * sizeof(struct lpteg); 787 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes", 788 moea64_pteg_count, size); 789 790 /* 791 * We now need to allocate memory. This memory, to be allocated, 792 * has to reside in a page table. The page table we are about to 793 * allocate. We don't have BAT. So drop to data real mode for a minute 794 * as a measure of last resort. We do this a couple times. 795 */ 796 797 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size); 798 DISABLE_TRANS(msr); 799 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg)); 800 ENABLE_TRANS(msr); 801 802 moea64_pteg_mask = moea64_pteg_count - 1; 803 804 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table); 805 806 /* 807 * Allocate pv/overflow lists. 808 */ 809 size = sizeof(struct pvo_head) * moea64_pteg_count; 810 811 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 812 PAGE_SIZE); 813 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 814 815 DISABLE_TRANS(msr); 816 for (i = 0; i < moea64_pteg_count; i++) 817 LIST_INIT(&moea64_pvo_table[i]); 818 ENABLE_TRANS(msr); 819 820 /* 821 * Initialize the lock that synchronizes access to the pteg and pvo 822 * tables. 823 */ 824 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 825 MTX_RECURSE); 826 827 /* 828 * Initialise the unmanaged pvo pool. 829 */ 830 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 831 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 832 moea64_bpvo_pool_index = 0; 833 834 /* 835 * Make sure kernel vsid is allocated as well as VSID 0. 836 */ 837 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 838 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 839 moea64_vsid_bitmap[0] |= 1; 840 841 /* 842 * Initialize the kernel pmap (which is statically allocated). 843 */ 844 for (i = 0; i < 16; i++) 845 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 846 847 kernel_pmap->pmap_phys = kernel_pmap; 848 kernel_pmap->pm_active = ~0; 849 850 PMAP_LOCK_INIT(kernel_pmap); 851 852 /* 853 * Now map in all the other buffers we allocated earlier 854 */ 855 856 DISABLE_TRANS(msr); 857 size = moea64_pteg_count * sizeof(struct lpteg); 858 off = (vm_offset_t)(moea64_pteg_table); 859 for (pa = off; pa < off + size; pa += PAGE_SIZE) 860 moea64_kenter(mmup, pa, pa); 861 size = sizeof(struct pvo_head) * moea64_pteg_count; 862 off = (vm_offset_t)(moea64_pvo_table); 863 for (pa = off; pa < off + size; pa += PAGE_SIZE) 864 moea64_kenter(mmup, pa, pa); 865 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 866 off = (vm_offset_t)(moea64_bpvo_pool); 867 for (pa = off; pa < off + size; pa += PAGE_SIZE) 868 moea64_kenter(mmup, pa, pa); 869 ENABLE_TRANS(msr); 870 871 /* 872 * Map certain important things, like ourselves and the exception 873 * vectors 874 */ 875 876 DISABLE_TRANS(msr); 877 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; pa += PAGE_SIZE) 878 moea64_kenter(mmup, pa, pa); 879 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 880 moea64_kenter(mmup, pa, pa); 881 ENABLE_TRANS(msr); 882 883 if (!ofw_real_mode) { 884 /* 885 * Set up the Open Firmware pmap and add its mappings. 886 */ 887 888 moea64_pinit(mmup, &ofw_pmap); 889 ofw_pmap.pm_sr[KERNEL_SR] = kernel_pmap->pm_sr[KERNEL_SR]; 890 ofw_pmap.pm_sr[KERNEL2_SR] = kernel_pmap->pm_sr[KERNEL2_SR]; 891 892 if ((chosen = OF_finddevice("/chosen")) == -1) 893 panic("moea64_bootstrap: can't find /chosen"); 894 OF_getprop(chosen, "mmu", &mmui, 4); 895 if ((mmu = OF_instance_to_package(mmui)) == -1) 896 panic("moea64_bootstrap: can't get mmu package"); 897 if ((sz = OF_getproplen(mmu, "translations")) == -1) 898 panic("moea64_bootstrap: can't get ofw translation count"); 899 900 bzero(translations, sz); 901 if (OF_getprop(mmu, "translations", translations, sz) == -1) 902 panic("moea64_bootstrap: can't get ofw translations"); 903 904 CTR0(KTR_PMAP, "moea64_bootstrap: translations"); 905 sz /= sizeof(*translations); 906 qsort(translations, sz, sizeof (*translations), om_cmp); 907 908 for (i = 0, ofw_mappings = 0; i < sz; i++) { 909 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 910 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 911 translations[i].om_len); 912 913 if (translations[i].om_pa_lo % PAGE_SIZE) 914 panic("OFW translation not page-aligned!"); 915 916 if (translations[i].om_pa_hi) 917 panic("OFW translations above 32-bit boundary!"); 918 919 /* Now enter the pages for this mapping */ 920 921 /* 922 * Lock the ofw pmap. pmap_kenter(), which we use for the 923 * pages the kernel also needs, does its own locking. 924 */ 925 PMAP_LOCK(&ofw_pmap); 926 DISABLE_TRANS(msr); 927 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 928 struct vm_page m; 929 930 /* Map low memory mappings into the kernel pmap, too. 931 * These are typically mappings made by the loader, 932 * so we need them if we want to keep executing. */ 933 934 if (translations[i].om_va + off < SEGMENT_LENGTH) 935 moea64_kenter(mmup, translations[i].om_va + off, 936 translations[i].om_va + off); 937 938 m.phys_addr = translations[i].om_pa_lo + off; 939 moea64_enter_locked(&ofw_pmap, 940 translations[i].om_va + off, &m, VM_PROT_ALL, 1); 941 942 ofw_mappings++; 943 } 944 ENABLE_TRANS(msr); 945 PMAP_UNLOCK(&ofw_pmap); 946 } 947 } 948 949 #ifdef SMP 950 TLBSYNC(); 951 #endif 952 953 /* 954 * Calculate the last available physical address. 955 */ 956 for (i = 0; phys_avail[i + 2] != 0; i += 2) 957 ; 958 Maxmem = powerpc_btop(phys_avail[i + 1]); 959 960 /* 961 * Initialize MMU and remap early physical mappings 962 */ 963 moea64_bridge_cpu_bootstrap(mmup,0); 964 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 965 pmap_bootstrapped++; 966 bs_remap_earlyboot(); 967 968 /* 969 * Set the start and end of kva. 970 */ 971 virtual_avail = VM_MIN_KERNEL_ADDRESS; 972 virtual_end = VM_MAX_KERNEL_ADDRESS; 973 974 /* 975 * Allocate some stupid buffer regions. 976 */ 977 978 pvo_allocator_start = virtual_avail; 979 virtual_avail += SEGMENT_LENGTH/4; 980 pvo_allocator_end = virtual_avail; 981 982 /* 983 * Allocate some things for page zeroing 984 */ 985 986 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, MTX_DEF); 987 for (i = 0; i < 2; i++) { 988 moea64_scratchpage_va[i] = virtual_avail; 989 virtual_avail += PAGE_SIZE; 990 991 moea64_kenter(mmup,moea64_scratchpage_va[i],kernelstart); 992 993 LOCK_TABLE(); 994 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(kernel_pmap, 995 moea64_scratchpage_va[i],&j); 996 moea64_scratchpage_pte[i] = moea64_pvo_to_pte( 997 moea64_scratchpage_pvo[i],j); 998 UNLOCK_TABLE(); 999 } 1000 1001 /* 1002 * Allocate a kernel stack with a guard page for thread0 and map it 1003 * into the kernel page map. 1004 */ 1005 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 1006 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1007 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 1008 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 1009 thread0.td_kstack = va; 1010 thread0.td_kstack_pages = KSTACK_PAGES; 1011 for (i = 0; i < KSTACK_PAGES; i++) { 1012 moea64_kenter(mmup, va, pa);; 1013 pa += PAGE_SIZE; 1014 va += PAGE_SIZE; 1015 } 1016 1017 /* 1018 * Allocate virtual address space for the message buffer. 1019 */ 1020 pa = msgbuf_phys = moea64_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 1021 msgbufp = (struct msgbuf *)virtual_avail; 1022 va = virtual_avail; 1023 virtual_avail += round_page(MSGBUF_SIZE); 1024 while (va < virtual_avail) { 1025 moea64_kenter(mmup, va, pa);; 1026 pa += PAGE_SIZE; 1027 va += PAGE_SIZE; 1028 } 1029 1030 /* 1031 * Allocate virtual address space for the dynamic percpu area. 1032 */ 1033 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1034 dpcpu = (void *)virtual_avail; 1035 va = virtual_avail; 1036 virtual_avail += DPCPU_SIZE; 1037 while (va < virtual_avail) { 1038 moea64_kenter(mmup, va, pa);; 1039 pa += PAGE_SIZE; 1040 va += PAGE_SIZE; 1041 } 1042 dpcpu_init(dpcpu, 0); 1043 } 1044 1045 /* 1046 * Activate a user pmap. The pmap must be activated before it's address 1047 * space can be accessed in any way. 1048 */ 1049 void 1050 moea64_activate(mmu_t mmu, struct thread *td) 1051 { 1052 pmap_t pm, pmr; 1053 1054 /* 1055 * Load all the data we need up front to encourage the compiler to 1056 * not issue any loads while we have interrupts disabled below. 1057 */ 1058 pm = &td->td_proc->p_vmspace->vm_pmap; 1059 pmr = pm->pmap_phys; 1060 1061 pm->pm_active |= PCPU_GET(cpumask); 1062 PCPU_SET(curpmap, pmr); 1063 } 1064 1065 void 1066 moea64_deactivate(mmu_t mmu, struct thread *td) 1067 { 1068 pmap_t pm; 1069 1070 pm = &td->td_proc->p_vmspace->vm_pmap; 1071 pm->pm_active &= ~(PCPU_GET(cpumask)); 1072 PCPU_SET(curpmap, NULL); 1073 } 1074 1075 void 1076 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1077 { 1078 struct pvo_entry *pvo; 1079 1080 PMAP_LOCK(pm); 1081 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1082 1083 if (pvo != NULL) { 1084 if (wired) { 1085 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1086 pm->pm_stats.wired_count++; 1087 pvo->pvo_vaddr |= PVO_WIRED; 1088 } else { 1089 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1090 pm->pm_stats.wired_count--; 1091 pvo->pvo_vaddr &= ~PVO_WIRED; 1092 } 1093 } 1094 PMAP_UNLOCK(pm); 1095 } 1096 1097 /* 1098 * Zero a page of physical memory by temporarily mapping it into the tlb. 1099 */ 1100 void 1101 moea64_zero_page(mmu_t mmu, vm_page_t m) 1102 { 1103 moea64_zero_page_area(mmu,m,0,PAGE_SIZE); 1104 } 1105 1106 /* 1107 * This goes through and sets the physical address of our 1108 * special scratch PTE to the PA we want to zero or copy. Because 1109 * of locking issues (this can get called in pvo_enter() by 1110 * the UMA allocator), we can't use most other utility functions here 1111 */ 1112 1113 static __inline 1114 void moea64_set_scratchpage_pa(int which, vm_offset_t pa) { 1115 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1116 (~LPTE_WIMG & ~LPTE_RPGN); 1117 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1118 moea64_calc_wimg(pa) | (uint64_t)pa; 1119 1120 moea64_scratchpage_pte[which]->pte_hi &= ~LPTE_VALID; 1121 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1122 1123 moea64_scratchpage_pte[which]->pte_lo = 1124 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo; 1125 EIEIO(); 1126 1127 moea64_scratchpage_pte[which]->pte_hi |= LPTE_VALID; 1128 TLBIE(kernel_pmap, moea64_scratchpage_va[which]); 1129 } 1130 1131 void 1132 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1133 { 1134 vm_offset_t dst; 1135 vm_offset_t src; 1136 1137 dst = VM_PAGE_TO_PHYS(mdst); 1138 src = VM_PAGE_TO_PHYS(msrc); 1139 1140 mtx_lock(&moea64_scratchpage_mtx); 1141 1142 moea64_set_scratchpage_pa(0,src); 1143 moea64_set_scratchpage_pa(1,dst); 1144 1145 kcopy((void *)moea64_scratchpage_va[0], 1146 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1147 1148 __syncicache((void *)moea64_scratchpage_va[1],PAGE_SIZE); 1149 1150 mtx_unlock(&moea64_scratchpage_mtx); 1151 } 1152 1153 void 1154 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1155 { 1156 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1157 1158 if (!moea64_initialized) 1159 panic("moea64_zero_page: can't zero pa %#x", pa); 1160 if (size + off > PAGE_SIZE) 1161 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1162 1163 mtx_lock(&moea64_scratchpage_mtx); 1164 1165 moea64_set_scratchpage_pa(0,pa); 1166 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1167 __syncicache((void *)moea64_scratchpage_va[0],PAGE_SIZE); 1168 1169 mtx_unlock(&moea64_scratchpage_mtx); 1170 } 1171 1172 void 1173 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1174 { 1175 1176 moea64_zero_page(mmu, m); 1177 } 1178 1179 /* 1180 * Map the given physical page at the specified virtual address in the 1181 * target pmap with the protection requested. If specified the page 1182 * will be wired down. 1183 */ 1184 void 1185 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1186 vm_prot_t prot, boolean_t wired) 1187 { 1188 1189 vm_page_lock_queues(); 1190 PMAP_LOCK(pmap); 1191 moea64_enter_locked(pmap, va, m, prot, wired); 1192 vm_page_unlock_queues(); 1193 PMAP_UNLOCK(pmap); 1194 } 1195 1196 /* 1197 * Map the given physical page at the specified virtual address in the 1198 * target pmap with the protection requested. If specified the page 1199 * will be wired down. 1200 * 1201 * The page queues and pmap must be locked. 1202 */ 1203 1204 static void 1205 moea64_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1206 boolean_t wired) 1207 { 1208 struct pvo_head *pvo_head; 1209 uma_zone_t zone; 1210 vm_page_t pg; 1211 uint64_t pte_lo; 1212 u_int pvo_flags; 1213 int error; 1214 1215 if (!moea64_initialized) { 1216 pvo_head = &moea64_pvo_kunmanaged; 1217 pg = NULL; 1218 zone = moea64_upvo_zone; 1219 pvo_flags = 0; 1220 } else { 1221 pvo_head = vm_page_to_pvoh(m); 1222 pg = m; 1223 zone = moea64_mpvo_zone; 1224 pvo_flags = PVO_MANAGED; 1225 } 1226 1227 if (pmap_bootstrapped) 1228 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1229 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1230 1231 /* XXX change the pvo head for fake pages */ 1232 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1233 pvo_flags &= ~PVO_MANAGED; 1234 pvo_head = &moea64_pvo_kunmanaged; 1235 zone = moea64_upvo_zone; 1236 } 1237 1238 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m)); 1239 1240 if (prot & VM_PROT_WRITE) { 1241 pte_lo |= LPTE_BW; 1242 if (pmap_bootstrapped) 1243 vm_page_flag_set(m, PG_WRITEABLE); 1244 } else 1245 pte_lo |= LPTE_BR; 1246 1247 if (prot & VM_PROT_EXECUTE) 1248 pvo_flags |= VM_PROT_EXECUTE; 1249 1250 if (wired) 1251 pvo_flags |= PVO_WIRED; 1252 1253 if ((m->flags & PG_FICTITIOUS) != 0) 1254 pvo_flags |= PVO_FAKE; 1255 1256 error = moea64_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1257 pte_lo, pvo_flags, 0); 1258 1259 if (pmap == kernel_pmap) 1260 TLBIE(pmap, va); 1261 1262 /* 1263 * Flush the page from the instruction cache if this page is 1264 * mapped executable and cacheable. 1265 */ 1266 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1267 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1268 } 1269 } 1270 1271 static void 1272 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_offset_t pa, vm_size_t sz) 1273 { 1274 /* 1275 * This is much trickier than on older systems because 1276 * we can't sync the icache on physical addresses directly 1277 * without a direct map. Instead we check a couple of cases 1278 * where the memory is already mapped in and, failing that, 1279 * use the same trick we use for page zeroing to create 1280 * a temporary mapping for this physical address. 1281 */ 1282 1283 if (!pmap_bootstrapped) { 1284 /* 1285 * If PMAP is not bootstrapped, we are likely to be 1286 * in real mode. 1287 */ 1288 __syncicache((void *)pa, sz); 1289 } else if (pmap == kernel_pmap) { 1290 __syncicache((void *)va, sz); 1291 } else { 1292 /* Use the scratch page to set up a temp mapping */ 1293 1294 mtx_lock(&moea64_scratchpage_mtx); 1295 1296 moea64_set_scratchpage_pa(1,pa); 1297 __syncicache((void *)moea64_scratchpage_va[1], sz); 1298 1299 mtx_unlock(&moea64_scratchpage_mtx); 1300 } 1301 } 1302 1303 /* 1304 * Maps a sequence of resident pages belonging to the same object. 1305 * The sequence begins with the given page m_start. This page is 1306 * mapped at the given virtual address start. Each subsequent page is 1307 * mapped at a virtual address that is offset from start by the same 1308 * amount as the page is offset from m_start within the object. The 1309 * last page in the sequence is the page with the largest offset from 1310 * m_start that can be mapped at a virtual address less than the given 1311 * virtual address end. Not every virtual page between start and end 1312 * is mapped; only those for which a resident page exists with the 1313 * corresponding offset from m_start are mapped. 1314 */ 1315 void 1316 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1317 vm_page_t m_start, vm_prot_t prot) 1318 { 1319 vm_page_t m; 1320 vm_pindex_t diff, psize; 1321 1322 psize = atop(end - start); 1323 m = m_start; 1324 PMAP_LOCK(pm); 1325 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1326 moea64_enter_locked(pm, start + ptoa(diff), m, prot & 1327 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1328 m = TAILQ_NEXT(m, listq); 1329 } 1330 PMAP_UNLOCK(pm); 1331 } 1332 1333 void 1334 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1335 vm_prot_t prot) 1336 { 1337 PMAP_LOCK(pm); 1338 moea64_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1339 FALSE); 1340 PMAP_UNLOCK(pm); 1341 1342 } 1343 1344 vm_paddr_t 1345 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1346 { 1347 struct pvo_entry *pvo; 1348 vm_paddr_t pa; 1349 1350 PMAP_LOCK(pm); 1351 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1352 if (pvo == NULL) 1353 pa = 0; 1354 else 1355 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1356 PMAP_UNLOCK(pm); 1357 return (pa); 1358 } 1359 1360 /* 1361 * Atomically extract and hold the physical page with the given 1362 * pmap and virtual address pair if that mapping permits the given 1363 * protection. 1364 */ 1365 vm_page_t 1366 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1367 { 1368 struct pvo_entry *pvo; 1369 vm_page_t m; 1370 1371 m = NULL; 1372 vm_page_lock_queues(); 1373 PMAP_LOCK(pmap); 1374 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1375 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1376 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1377 (prot & VM_PROT_WRITE) == 0)) { 1378 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1379 vm_page_hold(m); 1380 } 1381 vm_page_unlock_queues(); 1382 PMAP_UNLOCK(pmap); 1383 return (m); 1384 } 1385 1386 static void * 1387 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1388 { 1389 /* 1390 * This entire routine is a horrible hack to avoid bothering kmem 1391 * for new KVA addresses. Because this can get called from inside 1392 * kmem allocation routines, calling kmem for a new address here 1393 * can lead to multiply locking non-recursive mutexes. 1394 */ 1395 static vm_pindex_t color; 1396 vm_offset_t va; 1397 1398 vm_page_t m; 1399 int pflags, needed_lock; 1400 1401 *flags = UMA_SLAB_PRIV; 1402 needed_lock = !PMAP_LOCKED(kernel_pmap); 1403 1404 if (needed_lock) 1405 PMAP_LOCK(kernel_pmap); 1406 1407 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1408 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1409 else 1410 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1411 if (wait & M_ZERO) 1412 pflags |= VM_ALLOC_ZERO; 1413 1414 for (;;) { 1415 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1416 if (m == NULL) { 1417 if (wait & M_NOWAIT) 1418 return (NULL); 1419 VM_WAIT; 1420 } else 1421 break; 1422 } 1423 1424 va = pvo_allocator_start; 1425 pvo_allocator_start += PAGE_SIZE; 1426 1427 if (pvo_allocator_start >= pvo_allocator_end) 1428 panic("Ran out of PVO allocator buffer space!"); 1429 1430 /* Now call pvo_enter in recursive mode */ 1431 moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1432 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1433 PVO_WIRED | PVO_BOOTSTRAP, 1); 1434 1435 TLBIE(kernel_pmap, va); 1436 1437 if (needed_lock) 1438 PMAP_UNLOCK(kernel_pmap); 1439 1440 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1441 bzero((void *)va, PAGE_SIZE); 1442 1443 return (void *)va; 1444 } 1445 1446 void 1447 moea64_init(mmu_t mmu) 1448 { 1449 1450 CTR0(KTR_PMAP, "moea64_init"); 1451 1452 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1453 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1454 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1455 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1456 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1457 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1458 1459 if (!hw_direct_map) { 1460 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1461 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1462 } 1463 1464 moea64_initialized = TRUE; 1465 } 1466 1467 boolean_t 1468 moea64_is_modified(mmu_t mmu, vm_page_t m) 1469 { 1470 1471 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1472 return (FALSE); 1473 1474 return (moea64_query_bit(m, LPTE_CHG)); 1475 } 1476 1477 void 1478 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1479 { 1480 1481 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1482 return; 1483 moea64_clear_bit(m, LPTE_REF, NULL); 1484 } 1485 1486 void 1487 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1488 { 1489 1490 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1491 return; 1492 moea64_clear_bit(m, LPTE_CHG, NULL); 1493 } 1494 1495 /* 1496 * Clear the write and modified bits in each of the given page's mappings. 1497 */ 1498 void 1499 moea64_remove_write(mmu_t mmu, vm_page_t m) 1500 { 1501 struct pvo_entry *pvo; 1502 struct lpte *pt; 1503 pmap_t pmap; 1504 uint64_t lo; 1505 1506 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1507 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1508 (m->flags & PG_WRITEABLE) == 0) 1509 return; 1510 lo = moea64_attr_fetch(m); 1511 SYNC(); 1512 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1513 pmap = pvo->pvo_pmap; 1514 PMAP_LOCK(pmap); 1515 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1516 LOCK_TABLE(); 1517 pt = moea64_pvo_to_pte(pvo, -1); 1518 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1519 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1520 if (pt != NULL) { 1521 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 1522 lo |= pvo->pvo_pte.lpte.pte_lo; 1523 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1524 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1525 pvo->pvo_pmap, pvo->pvo_vaddr); 1526 } 1527 UNLOCK_TABLE(); 1528 } 1529 PMAP_UNLOCK(pmap); 1530 } 1531 if ((lo & LPTE_CHG) != 0) { 1532 moea64_attr_clear(m, LPTE_CHG); 1533 vm_page_dirty(m); 1534 } 1535 vm_page_flag_clear(m, PG_WRITEABLE); 1536 } 1537 1538 /* 1539 * moea64_ts_referenced: 1540 * 1541 * Return a count of reference bits for a page, clearing those bits. 1542 * It is not necessary for every reference bit to be cleared, but it 1543 * is necessary that 0 only be returned when there are truly no 1544 * reference bits set. 1545 * 1546 * XXX: The exact number of bits to check and clear is a matter that 1547 * should be tested and standardized at some point in the future for 1548 * optimal aging of shared pages. 1549 */ 1550 boolean_t 1551 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1552 { 1553 int count; 1554 1555 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1556 return (0); 1557 1558 count = moea64_clear_bit(m, LPTE_REF, NULL); 1559 1560 return (count); 1561 } 1562 1563 /* 1564 * Map a wired page into kernel virtual address space. 1565 */ 1566 void 1567 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1568 { 1569 uint64_t pte_lo; 1570 int error; 1571 1572 if (!pmap_bootstrapped) { 1573 if (va >= VM_MIN_KERNEL_ADDRESS && va < VM_MAX_KERNEL_ADDRESS) 1574 panic("Trying to enter an address in KVA -- %#x!\n",pa); 1575 } 1576 1577 pte_lo = moea64_calc_wimg(pa); 1578 1579 PMAP_LOCK(kernel_pmap); 1580 error = moea64_pvo_enter(kernel_pmap, moea64_upvo_zone, 1581 &moea64_pvo_kunmanaged, va, pa, pte_lo, 1582 PVO_WIRED | VM_PROT_EXECUTE, 0); 1583 1584 TLBIE(kernel_pmap, va); 1585 1586 if (error != 0 && error != ENOENT) 1587 panic("moea64_kenter: failed to enter va %#x pa %#x: %d", va, 1588 pa, error); 1589 1590 /* 1591 * Flush the memory from the instruction cache. 1592 */ 1593 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) { 1594 __syncicache((void *)va, PAGE_SIZE); 1595 } 1596 PMAP_UNLOCK(kernel_pmap); 1597 } 1598 1599 /* 1600 * Extract the physical page address associated with the given kernel virtual 1601 * address. 1602 */ 1603 vm_offset_t 1604 moea64_kextract(mmu_t mmu, vm_offset_t va) 1605 { 1606 struct pvo_entry *pvo; 1607 vm_paddr_t pa; 1608 1609 PMAP_LOCK(kernel_pmap); 1610 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1611 KASSERT(pvo != NULL, ("moea64_kextract: no addr found")); 1612 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va & ADDR_POFF); 1613 PMAP_UNLOCK(kernel_pmap); 1614 return (pa); 1615 } 1616 1617 /* 1618 * Remove a wired page from kernel virtual address space. 1619 */ 1620 void 1621 moea64_kremove(mmu_t mmu, vm_offset_t va) 1622 { 1623 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1624 } 1625 1626 /* 1627 * Map a range of physical addresses into kernel virtual address space. 1628 * 1629 * The value passed in *virt is a suggested virtual address for the mapping. 1630 * Architectures which can support a direct-mapped physical to virtual region 1631 * can return the appropriate address within that region, leaving '*virt' 1632 * unchanged. We cannot and therefore do not; *virt is updated with the 1633 * first usable address after the mapped region. 1634 */ 1635 vm_offset_t 1636 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1637 vm_offset_t pa_end, int prot) 1638 { 1639 vm_offset_t sva, va; 1640 1641 sva = *virt; 1642 va = sva; 1643 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1644 moea64_kenter(mmu, va, pa_start); 1645 *virt = va; 1646 1647 return (sva); 1648 } 1649 1650 /* 1651 * Returns true if the pmap's pv is one of the first 1652 * 16 pvs linked to from this page. This count may 1653 * be changed upwards or downwards in the future; it 1654 * is only necessary that true be returned for a small 1655 * subset of pmaps for proper page aging. 1656 */ 1657 boolean_t 1658 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1659 { 1660 int loops; 1661 struct pvo_entry *pvo; 1662 1663 if (!moea64_initialized || (m->flags & PG_FICTITIOUS)) 1664 return FALSE; 1665 1666 loops = 0; 1667 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1668 if (pvo->pvo_pmap == pmap) 1669 return (TRUE); 1670 if (++loops >= 16) 1671 break; 1672 } 1673 1674 return (FALSE); 1675 } 1676 1677 /* 1678 * Return the number of managed mappings to the given physical page 1679 * that are wired. 1680 */ 1681 int 1682 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1683 { 1684 struct pvo_entry *pvo; 1685 int count; 1686 1687 count = 0; 1688 if (!moea64_initialized || (m->flags & PG_FICTITIOUS) != 0) 1689 return (count); 1690 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1691 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1692 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1693 count++; 1694 return (count); 1695 } 1696 1697 static u_int moea64_vsidcontext; 1698 1699 void 1700 moea64_pinit(mmu_t mmu, pmap_t pmap) 1701 { 1702 int i, mask; 1703 u_int entropy; 1704 1705 PMAP_LOCK_INIT(pmap); 1706 1707 entropy = 0; 1708 __asm __volatile("mftb %0" : "=r"(entropy)); 1709 1710 if (pmap_bootstrapped) 1711 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, (vm_offset_t)pmap); 1712 else 1713 pmap->pmap_phys = pmap; 1714 1715 /* 1716 * Allocate some segment registers for this pmap. 1717 */ 1718 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1719 u_int hash, n; 1720 1721 /* 1722 * Create a new value by mutiplying by a prime and adding in 1723 * entropy from the timebase register. This is to make the 1724 * VSID more random so that the PT hash function collides 1725 * less often. (Note that the prime casues gcc to do shifts 1726 * instead of a multiply.) 1727 */ 1728 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1729 hash = moea64_vsidcontext & (NPMAPS - 1); 1730 if (hash == 0) /* 0 is special, avoid it */ 1731 continue; 1732 n = hash >> 5; 1733 mask = 1 << (hash & (VSID_NBPW - 1)); 1734 hash = (moea64_vsidcontext & 0xfffff); 1735 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1736 /* anything free in this bucket? */ 1737 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1738 entropy = (moea64_vsidcontext >> 20); 1739 continue; 1740 } 1741 i = ffs(~moea64_vsid_bitmap[i]) - 1; 1742 mask = 1 << i; 1743 hash &= 0xfffff & ~(VSID_NBPW - 1); 1744 hash |= i; 1745 } 1746 moea64_vsid_bitmap[n] |= mask; 1747 for (i = 0; i < 16; i++) { 1748 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1749 } 1750 return; 1751 } 1752 1753 panic("moea64_pinit: out of segments"); 1754 } 1755 1756 /* 1757 * Initialize the pmap associated with process 0. 1758 */ 1759 void 1760 moea64_pinit0(mmu_t mmu, pmap_t pm) 1761 { 1762 moea64_pinit(mmu, pm); 1763 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1764 } 1765 1766 /* 1767 * Set the physical protection on the specified range of this map as requested. 1768 */ 1769 void 1770 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1771 vm_prot_t prot) 1772 { 1773 struct pvo_entry *pvo; 1774 struct lpte *pt; 1775 int pteidx; 1776 1777 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1778 eva, prot); 1779 1780 1781 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1782 ("moea64_protect: non current pmap")); 1783 1784 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1785 moea64_remove(mmu, pm, sva, eva); 1786 return; 1787 } 1788 1789 vm_page_lock_queues(); 1790 PMAP_LOCK(pm); 1791 for (; sva < eva; sva += PAGE_SIZE) { 1792 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1793 if (pvo == NULL) 1794 continue; 1795 1796 /* 1797 * Grab the PTE pointer before we diddle with the cached PTE 1798 * copy. 1799 */ 1800 LOCK_TABLE(); 1801 pt = moea64_pvo_to_pte(pvo, pteidx); 1802 1803 /* 1804 * Change the protection of the page. 1805 */ 1806 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1807 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1808 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1809 if ((prot & VM_PROT_EXECUTE) == 0) 1810 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1811 1812 /* 1813 * If the PVO is in the page table, update that pte as well. 1814 */ 1815 if (pt != NULL) { 1816 moea64_pte_change(pt, &pvo->pvo_pte.lpte, 1817 pvo->pvo_pmap, pvo->pvo_vaddr); 1818 if ((pvo->pvo_pte.lpte.pte_lo & 1819 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1820 moea64_syncicache(pm, sva, 1821 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1822 PAGE_SIZE); 1823 } 1824 } 1825 UNLOCK_TABLE(); 1826 } 1827 vm_page_unlock_queues(); 1828 PMAP_UNLOCK(pm); 1829 } 1830 1831 /* 1832 * Map a list of wired pages into kernel virtual address space. This is 1833 * intended for temporary mappings which do not need page modification or 1834 * references recorded. Existing mappings in the region are overwritten. 1835 */ 1836 void 1837 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1838 { 1839 while (count-- > 0) { 1840 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1841 va += PAGE_SIZE; 1842 m++; 1843 } 1844 } 1845 1846 /* 1847 * Remove page mappings from kernel virtual address space. Intended for 1848 * temporary mappings entered by moea64_qenter. 1849 */ 1850 void 1851 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 1852 { 1853 while (count-- > 0) { 1854 moea64_kremove(mmu, va); 1855 va += PAGE_SIZE; 1856 } 1857 } 1858 1859 void 1860 moea64_release(mmu_t mmu, pmap_t pmap) 1861 { 1862 int idx, mask; 1863 1864 /* 1865 * Free segment register's VSID 1866 */ 1867 if (pmap->pm_sr[0] == 0) 1868 panic("moea64_release"); 1869 1870 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1871 mask = 1 << (idx % VSID_NBPW); 1872 idx /= VSID_NBPW; 1873 moea64_vsid_bitmap[idx] &= ~mask; 1874 PMAP_LOCK_DESTROY(pmap); 1875 } 1876 1877 /* 1878 * Remove the given range of addresses from the specified map. 1879 */ 1880 void 1881 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1882 { 1883 struct pvo_entry *pvo; 1884 int pteidx; 1885 1886 vm_page_lock_queues(); 1887 PMAP_LOCK(pm); 1888 for (; sva < eva; sva += PAGE_SIZE) { 1889 pvo = moea64_pvo_find_va(pm, sva, &pteidx); 1890 if (pvo != NULL) { 1891 moea64_pvo_remove(pvo, pteidx); 1892 } 1893 } 1894 vm_page_unlock_queues(); 1895 PMAP_UNLOCK(pm); 1896 } 1897 1898 /* 1899 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 1900 * will reflect changes in pte's back to the vm_page. 1901 */ 1902 void 1903 moea64_remove_all(mmu_t mmu, vm_page_t m) 1904 { 1905 struct pvo_head *pvo_head; 1906 struct pvo_entry *pvo, *next_pvo; 1907 pmap_t pmap; 1908 1909 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1910 1911 pvo_head = vm_page_to_pvoh(m); 1912 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1913 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1914 1915 MOEA_PVO_CHECK(pvo); /* sanity check */ 1916 pmap = pvo->pvo_pmap; 1917 PMAP_LOCK(pmap); 1918 moea64_pvo_remove(pvo, -1); 1919 PMAP_UNLOCK(pmap); 1920 } 1921 vm_page_flag_clear(m, PG_WRITEABLE); 1922 } 1923 1924 /* 1925 * Allocate a physical page of memory directly from the phys_avail map. 1926 * Can only be called from moea64_bootstrap before avail start and end are 1927 * calculated. 1928 */ 1929 static vm_offset_t 1930 moea64_bootstrap_alloc(vm_size_t size, u_int align) 1931 { 1932 vm_offset_t s, e; 1933 int i, j; 1934 1935 size = round_page(size); 1936 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1937 if (align != 0) 1938 s = (phys_avail[i] + align - 1) & ~(align - 1); 1939 else 1940 s = phys_avail[i]; 1941 e = s + size; 1942 1943 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1944 continue; 1945 1946 if (s == phys_avail[i]) { 1947 phys_avail[i] += size; 1948 } else if (e == phys_avail[i + 1]) { 1949 phys_avail[i + 1] -= size; 1950 } else { 1951 for (j = phys_avail_count * 2; j > i; j -= 2) { 1952 phys_avail[j] = phys_avail[j - 2]; 1953 phys_avail[j + 1] = phys_avail[j - 1]; 1954 } 1955 1956 phys_avail[i + 3] = phys_avail[i + 1]; 1957 phys_avail[i + 1] = s; 1958 phys_avail[i + 2] = e; 1959 phys_avail_count++; 1960 } 1961 1962 return (s); 1963 } 1964 panic("moea64_bootstrap_alloc: could not allocate memory"); 1965 } 1966 1967 static void 1968 tlbia(void) 1969 { 1970 vm_offset_t i; 1971 1972 for (i = 0; i < 0xFF000; i += 0x00001000) 1973 TLBIE(NULL,i); 1974 } 1975 1976 static int 1977 moea64_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1978 vm_offset_t va, vm_offset_t pa, uint64_t pte_lo, int flags, int recurse) 1979 { 1980 struct pvo_entry *pvo; 1981 uint64_t vsid; 1982 int first; 1983 u_int ptegidx; 1984 int i; 1985 int bootstrap; 1986 1987 /* 1988 * One nasty thing that can happen here is that the UMA calls to 1989 * allocate new PVOs need to map more memory, which calls pvo_enter(), 1990 * which calls UMA... 1991 * 1992 * We break the loop by detecting recursion and allocating out of 1993 * the bootstrap pool. 1994 */ 1995 1996 moea64_pvo_enter_calls++; 1997 first = 0; 1998 bootstrap = (flags & PVO_BOOTSTRAP); 1999 2000 if (!moea64_initialized) 2001 bootstrap = 1; 2002 2003 /* 2004 * Compute the PTE Group index. 2005 */ 2006 va &= ~ADDR_POFF; 2007 vsid = va_to_vsid(pm, va); 2008 ptegidx = va_to_pteg(vsid, va); 2009 2010 /* 2011 * Remove any existing mapping for this page. Reuse the pvo entry if 2012 * there is a mapping. 2013 */ 2014 if (!recurse) 2015 LOCK_TABLE(); 2016 2017 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2018 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2019 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2020 (pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == 2021 (pte_lo & LPTE_PP)) { 2022 if (!recurse) 2023 UNLOCK_TABLE(); 2024 return (0); 2025 } 2026 moea64_pvo_remove(pvo, -1); 2027 break; 2028 } 2029 } 2030 2031 /* 2032 * If we aren't overwriting a mapping, try to allocate. 2033 */ 2034 if (bootstrap) { 2035 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2036 panic("moea64_enter: bpvo pool exhausted, %d, %d, %d", 2037 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2038 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2039 } 2040 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2041 moea64_bpvo_pool_index++; 2042 bootstrap = 1; 2043 } else { 2044 pvo = uma_zalloc(zone, M_NOWAIT); 2045 } 2046 2047 if (pvo == NULL) { 2048 if (!recurse) 2049 UNLOCK_TABLE(); 2050 return (ENOMEM); 2051 } 2052 2053 moea64_pvo_entries++; 2054 pvo->pvo_vaddr = va; 2055 pvo->pvo_pmap = pm; 2056 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2057 pvo->pvo_vaddr &= ~ADDR_POFF; 2058 2059 if (!(flags & VM_PROT_EXECUTE)) 2060 pte_lo |= LPTE_NOEXEC; 2061 if (flags & PVO_WIRED) 2062 pvo->pvo_vaddr |= PVO_WIRED; 2063 if (pvo_head != &moea64_pvo_kunmanaged) 2064 pvo->pvo_vaddr |= PVO_MANAGED; 2065 if (bootstrap) 2066 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2067 if (flags & PVO_FAKE) 2068 pvo->pvo_vaddr |= PVO_FAKE; 2069 2070 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2071 (uint64_t)(pa) | pte_lo); 2072 2073 /* 2074 * Remember if the list was empty and therefore will be the first 2075 * item. 2076 */ 2077 if (LIST_FIRST(pvo_head) == NULL) 2078 first = 1; 2079 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2080 2081 if (pvo->pvo_pte.lpte.pte_lo & PVO_WIRED) 2082 pm->pm_stats.wired_count++; 2083 pm->pm_stats.resident_count++; 2084 2085 /* 2086 * We hope this succeeds but it isn't required. 2087 */ 2088 i = moea64_pte_insert(ptegidx, &pvo->pvo_pte.lpte); 2089 if (i >= 0) { 2090 PVO_PTEGIDX_SET(pvo, i); 2091 } else { 2092 panic("moea64_pvo_enter: overflow"); 2093 moea64_pte_overflow++; 2094 } 2095 2096 if (!recurse) 2097 UNLOCK_TABLE(); 2098 2099 return (first ? ENOENT : 0); 2100 } 2101 2102 static void 2103 moea64_pvo_remove(struct pvo_entry *pvo, int pteidx) 2104 { 2105 struct lpte *pt; 2106 2107 /* 2108 * If there is an active pte entry, we need to deactivate it (and 2109 * save the ref & cfg bits). 2110 */ 2111 LOCK_TABLE(); 2112 pt = moea64_pvo_to_pte(pvo, pteidx); 2113 if (pt != NULL) { 2114 moea64_pte_unset(pt, &pvo->pvo_pte.lpte, pvo->pvo_pmap, 2115 pvo->pvo_vaddr); 2116 PVO_PTEGIDX_CLR(pvo); 2117 } else { 2118 moea64_pte_overflow--; 2119 } 2120 UNLOCK_TABLE(); 2121 2122 /* 2123 * Update our statistics. 2124 */ 2125 pvo->pvo_pmap->pm_stats.resident_count--; 2126 if (pvo->pvo_pte.lpte.pte_lo & PVO_WIRED) 2127 pvo->pvo_pmap->pm_stats.wired_count--; 2128 2129 /* 2130 * Save the REF/CHG bits into their cache if the page is managed. 2131 */ 2132 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2133 struct vm_page *pg; 2134 2135 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2136 if (pg != NULL) { 2137 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2138 (LPTE_REF | LPTE_CHG)); 2139 } 2140 } 2141 2142 /* 2143 * Remove this PVO from the PV list. 2144 */ 2145 LIST_REMOVE(pvo, pvo_vlink); 2146 2147 /* 2148 * Remove this from the overflow list and return it to the pool 2149 * if we aren't going to reuse it. 2150 */ 2151 LIST_REMOVE(pvo, pvo_olink); 2152 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2153 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea64_mpvo_zone : 2154 moea64_upvo_zone, pvo); 2155 moea64_pvo_entries--; 2156 moea64_pvo_remove_calls++; 2157 } 2158 2159 static __inline int 2160 moea64_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2161 { 2162 int pteidx; 2163 2164 /* 2165 * We can find the actual pte entry without searching by grabbing 2166 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2167 * noticing the HID bit. 2168 */ 2169 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2170 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID) 2171 pteidx ^= moea64_pteg_mask * 8; 2172 2173 return (pteidx); 2174 } 2175 2176 static struct pvo_entry * 2177 moea64_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2178 { 2179 struct pvo_entry *pvo; 2180 int ptegidx; 2181 uint64_t vsid; 2182 2183 va &= ~ADDR_POFF; 2184 vsid = va_to_vsid(pm, va); 2185 ptegidx = va_to_pteg(vsid, va); 2186 2187 LOCK_TABLE(); 2188 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2189 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2190 if (pteidx_p) 2191 *pteidx_p = moea64_pvo_pte_index(pvo, ptegidx); 2192 break; 2193 } 2194 } 2195 UNLOCK_TABLE(); 2196 2197 return (pvo); 2198 } 2199 2200 static struct lpte * 2201 moea64_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2202 { 2203 struct lpte *pt; 2204 2205 /* 2206 * If we haven't been supplied the ptegidx, calculate it. 2207 */ 2208 if (pteidx == -1) { 2209 int ptegidx; 2210 uint64_t vsid; 2211 2212 vsid = va_to_vsid(pvo->pvo_pmap, pvo->pvo_vaddr); 2213 ptegidx = va_to_pteg(vsid, pvo->pvo_vaddr); 2214 pteidx = moea64_pvo_pte_index(pvo, ptegidx); 2215 } 2216 2217 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2218 2219 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 2220 !PVO_PTEGIDX_ISSET(pvo)) { 2221 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no " 2222 "valid pte index", pvo); 2223 } 2224 2225 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 && 2226 PVO_PTEGIDX_ISSET(pvo)) { 2227 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo " 2228 "pvo but no valid pte", pvo); 2229 } 2230 2231 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) == 2232 LPTE_VALID) { 2233 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) { 2234 panic("moea64_pvo_to_pte: pvo %p has valid pte in " 2235 "moea64_pteg_table %p but invalid in pvo", pvo, pt); 2236 } 2237 2238 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) & 2239 ~(LPTE_CHG|LPTE_REF)) != 0) { 2240 panic("moea64_pvo_to_pte: pvo %p pte does not match " 2241 "pte %p in moea64_pteg_table difference is %#x", 2242 pvo, pt, 2243 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo)); 2244 } 2245 2246 ASSERT_TABLE_LOCK(); 2247 return (pt); 2248 } 2249 2250 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) { 2251 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in " 2252 "moea64_pteg_table but valid in pvo", pvo, pt); 2253 } 2254 2255 return (NULL); 2256 } 2257 2258 static int 2259 moea64_pte_insert(u_int ptegidx, struct lpte *pvo_pt) 2260 { 2261 struct lpte *pt; 2262 int i; 2263 2264 ASSERT_TABLE_LOCK(); 2265 2266 /* 2267 * First try primary hash. 2268 */ 2269 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2270 if ((pt->pte_hi & LPTE_VALID) == 0) { 2271 pvo_pt->pte_hi &= ~LPTE_HID; 2272 moea64_pte_set(pt, pvo_pt); 2273 return (i); 2274 } 2275 } 2276 2277 /* 2278 * Now try secondary hash. 2279 */ 2280 ptegidx ^= moea64_pteg_mask; 2281 2282 for (pt = moea64_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2283 if ((pt->pte_hi & LPTE_VALID) == 0) { 2284 pvo_pt->pte_hi |= LPTE_HID; 2285 moea64_pte_set(pt, pvo_pt); 2286 return (i); 2287 } 2288 } 2289 2290 panic("moea64_pte_insert: overflow"); 2291 return (-1); 2292 } 2293 2294 static boolean_t 2295 moea64_query_bit(vm_page_t m, u_int64_t ptebit) 2296 { 2297 struct pvo_entry *pvo; 2298 struct lpte *pt; 2299 2300 #if 0 2301 if (moea64_attr_fetch(m) & ptebit) 2302 return (TRUE); 2303 #endif 2304 2305 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2306 MOEA_PVO_CHECK(pvo); /* sanity check */ 2307 2308 /* 2309 * See if we saved the bit off. If so, cache it and return 2310 * success. 2311 */ 2312 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2313 moea64_attr_save(m, ptebit); 2314 MOEA_PVO_CHECK(pvo); /* sanity check */ 2315 return (TRUE); 2316 } 2317 } 2318 2319 /* 2320 * No luck, now go through the hard part of looking at the PTEs 2321 * themselves. Sync so that any pending REF/CHG bits are flushed to 2322 * the PTEs. 2323 */ 2324 SYNC(); 2325 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2326 MOEA_PVO_CHECK(pvo); /* sanity check */ 2327 2328 /* 2329 * See if this pvo has a valid PTE. if so, fetch the 2330 * REF/CHG bits from the valid PTE. If the appropriate 2331 * ptebit is set, cache it and return success. 2332 */ 2333 LOCK_TABLE(); 2334 pt = moea64_pvo_to_pte(pvo, -1); 2335 if (pt != NULL) { 2336 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2337 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2338 UNLOCK_TABLE(); 2339 2340 moea64_attr_save(m, ptebit); 2341 MOEA_PVO_CHECK(pvo); /* sanity check */ 2342 return (TRUE); 2343 } 2344 } 2345 UNLOCK_TABLE(); 2346 } 2347 2348 return (FALSE); 2349 } 2350 2351 static u_int 2352 moea64_clear_bit(vm_page_t m, u_int64_t ptebit, u_int64_t *origbit) 2353 { 2354 u_int count; 2355 struct pvo_entry *pvo; 2356 struct lpte *pt; 2357 uint64_t rv; 2358 2359 /* 2360 * Clear the cached value. 2361 */ 2362 rv = moea64_attr_fetch(m); 2363 moea64_attr_clear(m, ptebit); 2364 2365 /* 2366 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2367 * we can reset the right ones). note that since the pvo entries and 2368 * list heads are accessed via BAT0 and are never placed in the page 2369 * table, we don't have to worry about further accesses setting the 2370 * REF/CHG bits. 2371 */ 2372 SYNC(); 2373 2374 /* 2375 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2376 * valid pte clear the ptebit from the valid pte. 2377 */ 2378 count = 0; 2379 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2380 MOEA_PVO_CHECK(pvo); /* sanity check */ 2381 2382 LOCK_TABLE(); 2383 pt = moea64_pvo_to_pte(pvo, -1); 2384 if (pt != NULL) { 2385 moea64_pte_synch(pt, &pvo->pvo_pte.lpte); 2386 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2387 count++; 2388 moea64_pte_clear(pt, pvo->pvo_pmap, PVO_VADDR(pvo), ptebit); 2389 } 2390 } 2391 UNLOCK_TABLE(); 2392 rv |= pvo->pvo_pte.lpte.pte_lo; 2393 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2394 MOEA_PVO_CHECK(pvo); /* sanity check */ 2395 } 2396 2397 if (origbit != NULL) { 2398 *origbit = rv; 2399 } 2400 2401 return (count); 2402 } 2403 2404 boolean_t 2405 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2406 { 2407 return (EFAULT); 2408 } 2409 2410 /* 2411 * Map a set of physical memory pages into the kernel virtual 2412 * address space. Return a pointer to where it is mapped. This 2413 * routine is intended to be used for mapping device memory, 2414 * NOT real memory. 2415 */ 2416 void * 2417 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2418 { 2419 vm_offset_t va, tmpva, ppa, offset; 2420 2421 ppa = trunc_page(pa); 2422 offset = pa & PAGE_MASK; 2423 size = roundup(offset + size, PAGE_SIZE); 2424 2425 va = kmem_alloc_nofault(kernel_map, size); 2426 2427 if (!va) 2428 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2429 2430 for (tmpva = va; size > 0;) { 2431 moea64_kenter(mmu, tmpva, ppa); 2432 size -= PAGE_SIZE; 2433 tmpva += PAGE_SIZE; 2434 ppa += PAGE_SIZE; 2435 } 2436 2437 return ((void *)(va + offset)); 2438 } 2439 2440 void 2441 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2442 { 2443 vm_offset_t base, offset; 2444 2445 base = trunc_page(va); 2446 offset = va & PAGE_MASK; 2447 size = roundup(offset + size, PAGE_SIZE); 2448 2449 kmem_free(kernel_map, base, size); 2450 } 2451 2452 static void 2453 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2454 { 2455 struct pvo_entry *pvo; 2456 vm_offset_t lim; 2457 vm_paddr_t pa; 2458 vm_size_t len; 2459 2460 PMAP_LOCK(pm); 2461 while (sz > 0) { 2462 lim = round_page(va); 2463 len = MIN(lim - va, sz); 2464 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2465 if (pvo != NULL) { 2466 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2467 (va & ADDR_POFF); 2468 moea64_syncicache(pm, va, pa, len); 2469 } 2470 va += len; 2471 sz -= len; 2472 } 2473 PMAP_UNLOCK(pm); 2474 } 2475