1 /*- 2 * Copyright (c) 2008-2015 Nathan Whitehorn 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Manages physical address maps. 32 * 33 * Since the information managed by this module is also stored by the 34 * logical address mapping module, this module may throw away valid virtual 35 * to physical mappings at almost any time. However, invalidations of 36 * mappings must be done as requested. 37 * 38 * In order to cope with hardware architectures which make virtual to 39 * physical map invalidates expensive, this module may delay invalidate 40 * reduced protection operations until such time as they are actually 41 * necessary. This module is given full information as to which processors 42 * are currently using which maps, and to when physical maps must be made 43 * correct. 44 */ 45 46 #include "opt_compat.h" 47 #include "opt_kstack_pages.h" 48 49 #include <sys/param.h> 50 #include <sys/kernel.h> 51 #include <sys/conf.h> 52 #include <sys/queue.h> 53 #include <sys/cpuset.h> 54 #include <sys/kerneldump.h> 55 #include <sys/ktr.h> 56 #include <sys/lock.h> 57 #include <sys/msgbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/mutex.h> 60 #include <sys/proc.h> 61 #include <sys/rwlock.h> 62 #include <sys/sched.h> 63 #include <sys/sysctl.h> 64 #include <sys/systm.h> 65 #include <sys/vmmeter.h> 66 #include <sys/smp.h> 67 68 #include <sys/kdb.h> 69 70 #include <dev/ofw/openfirm.h> 71 72 #include <vm/vm.h> 73 #include <vm/vm_param.h> 74 #include <vm/vm_kern.h> 75 #include <vm/vm_page.h> 76 #include <vm/vm_map.h> 77 #include <vm/vm_object.h> 78 #include <vm/vm_extern.h> 79 #include <vm/vm_pageout.h> 80 #include <vm/uma.h> 81 82 #include <machine/_inttypes.h> 83 #include <machine/cpu.h> 84 #include <machine/platform.h> 85 #include <machine/frame.h> 86 #include <machine/md_var.h> 87 #include <machine/psl.h> 88 #include <machine/bat.h> 89 #include <machine/hid.h> 90 #include <machine/pte.h> 91 #include <machine/sr.h> 92 #include <machine/trap.h> 93 #include <machine/mmuvar.h> 94 95 #include "mmu_oea64.h" 96 #include "mmu_if.h" 97 #include "moea64_if.h" 98 99 void moea64_release_vsid(uint64_t vsid); 100 uintptr_t moea64_get_unique_vsid(void); 101 102 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 103 #define ENABLE_TRANS(msr) mtmsr(msr) 104 105 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 106 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 107 #define VSID_HASH_MASK 0x0000007fffffffffULL 108 109 /* 110 * Locking semantics: 111 * 112 * There are two locks of interest: the page locks and the pmap locks, which 113 * protect their individual PVO lists and are locked in that order. The contents 114 * of all PVO entries are protected by the locks of their respective pmaps. 115 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 116 * into any list. 117 * 118 */ 119 120 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 121 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 122 123 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 124 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 125 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 126 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 127 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 128 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 129 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 130 131 struct ofw_map { 132 cell_t om_va; 133 cell_t om_len; 134 uint64_t om_pa; 135 cell_t om_mode; 136 }; 137 138 extern unsigned char _etext[]; 139 extern unsigned char _end[]; 140 141 /* 142 * Map of physical memory regions. 143 */ 144 static struct mem_region *regions; 145 static struct mem_region *pregions; 146 static u_int phys_avail_count; 147 static int regions_sz, pregions_sz; 148 149 extern void bs_remap_earlyboot(void); 150 151 /* 152 * Lock for the SLB tables. 153 */ 154 struct mtx moea64_slb_mutex; 155 156 /* 157 * PTEG data. 158 */ 159 u_int moea64_pteg_count; 160 u_int moea64_pteg_mask; 161 162 /* 163 * PVO data. 164 */ 165 166 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 167 168 static struct pvo_entry *moea64_bpvo_pool; 169 static int moea64_bpvo_pool_index = 0; 170 static int moea64_bpvo_pool_size = 327680; 171 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 172 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 173 &moea64_bpvo_pool_index, 0, ""); 174 175 #define VSID_NBPW (sizeof(u_int32_t) * 8) 176 #ifdef __powerpc64__ 177 #define NVSIDS (NPMAPS * 16) 178 #define VSID_HASHMASK 0xffffffffUL 179 #else 180 #define NVSIDS NPMAPS 181 #define VSID_HASHMASK 0xfffffUL 182 #endif 183 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 184 185 static boolean_t moea64_initialized = FALSE; 186 187 /* 188 * Statistics. 189 */ 190 u_int moea64_pte_valid = 0; 191 u_int moea64_pte_overflow = 0; 192 u_int moea64_pvo_entries = 0; 193 u_int moea64_pvo_enter_calls = 0; 194 u_int moea64_pvo_remove_calls = 0; 195 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 196 &moea64_pte_valid, 0, ""); 197 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 198 &moea64_pte_overflow, 0, ""); 199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 200 &moea64_pvo_entries, 0, ""); 201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 202 &moea64_pvo_enter_calls, 0, ""); 203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 204 &moea64_pvo_remove_calls, 0, ""); 205 206 vm_offset_t moea64_scratchpage_va[2]; 207 struct pvo_entry *moea64_scratchpage_pvo[2]; 208 struct mtx moea64_scratchpage_mtx; 209 210 uint64_t moea64_large_page_mask = 0; 211 uint64_t moea64_large_page_size = 0; 212 int moea64_large_page_shift = 0; 213 214 /* 215 * PVO calls. 216 */ 217 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 218 struct pvo_head *pvo_head); 219 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 220 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 221 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 222 223 /* 224 * Utility routines. 225 */ 226 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 227 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 228 static void moea64_kremove(mmu_t, vm_offset_t); 229 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 230 vm_paddr_t pa, vm_size_t sz); 231 static void moea64_pmap_init_qpages(void); 232 233 /* 234 * Kernel MMU interface 235 */ 236 void moea64_clear_modify(mmu_t, vm_page_t); 237 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 238 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 239 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 240 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 241 u_int flags, int8_t psind); 242 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 243 vm_prot_t); 244 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 245 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 246 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 247 void moea64_init(mmu_t); 248 boolean_t moea64_is_modified(mmu_t, vm_page_t); 249 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 250 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 251 int moea64_ts_referenced(mmu_t, vm_page_t); 252 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 253 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 254 int moea64_page_wired_mappings(mmu_t, vm_page_t); 255 void moea64_pinit(mmu_t, pmap_t); 256 void moea64_pinit0(mmu_t, pmap_t); 257 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 258 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 259 void moea64_qremove(mmu_t, vm_offset_t, int); 260 void moea64_release(mmu_t, pmap_t); 261 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 262 void moea64_remove_pages(mmu_t, pmap_t); 263 void moea64_remove_all(mmu_t, vm_page_t); 264 void moea64_remove_write(mmu_t, vm_page_t); 265 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 266 void moea64_zero_page(mmu_t, vm_page_t); 267 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 268 void moea64_zero_page_idle(mmu_t, vm_page_t); 269 void moea64_activate(mmu_t, struct thread *); 270 void moea64_deactivate(mmu_t, struct thread *); 271 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 272 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 273 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 274 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 275 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 276 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 277 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 278 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 279 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 280 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 281 void **va); 282 void moea64_scan_init(mmu_t mmu); 283 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 284 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 285 286 static mmu_method_t moea64_methods[] = { 287 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 288 MMUMETHOD(mmu_copy_page, moea64_copy_page), 289 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 290 MMUMETHOD(mmu_enter, moea64_enter), 291 MMUMETHOD(mmu_enter_object, moea64_enter_object), 292 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 293 MMUMETHOD(mmu_extract, moea64_extract), 294 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 295 MMUMETHOD(mmu_init, moea64_init), 296 MMUMETHOD(mmu_is_modified, moea64_is_modified), 297 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 298 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 299 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 300 MMUMETHOD(mmu_map, moea64_map), 301 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 302 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 303 MMUMETHOD(mmu_pinit, moea64_pinit), 304 MMUMETHOD(mmu_pinit0, moea64_pinit0), 305 MMUMETHOD(mmu_protect, moea64_protect), 306 MMUMETHOD(mmu_qenter, moea64_qenter), 307 MMUMETHOD(mmu_qremove, moea64_qremove), 308 MMUMETHOD(mmu_release, moea64_release), 309 MMUMETHOD(mmu_remove, moea64_remove), 310 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 311 MMUMETHOD(mmu_remove_all, moea64_remove_all), 312 MMUMETHOD(mmu_remove_write, moea64_remove_write), 313 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 314 MMUMETHOD(mmu_unwire, moea64_unwire), 315 MMUMETHOD(mmu_zero_page, moea64_zero_page), 316 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 317 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 318 MMUMETHOD(mmu_activate, moea64_activate), 319 MMUMETHOD(mmu_deactivate, moea64_deactivate), 320 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 321 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 322 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 323 324 /* Internal interfaces */ 325 MMUMETHOD(mmu_mapdev, moea64_mapdev), 326 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 327 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 328 MMUMETHOD(mmu_kextract, moea64_kextract), 329 MMUMETHOD(mmu_kenter, moea64_kenter), 330 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 331 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 332 MMUMETHOD(mmu_scan_init, moea64_scan_init), 333 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 334 335 { 0, 0 } 336 }; 337 338 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 339 340 static struct pvo_head * 341 vm_page_to_pvoh(vm_page_t m) 342 { 343 344 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 345 return (&m->md.mdpg_pvoh); 346 } 347 348 static struct pvo_entry * 349 alloc_pvo_entry(int bootstrap) 350 { 351 struct pvo_entry *pvo; 352 353 if (!moea64_initialized || bootstrap) { 354 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 355 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 356 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 357 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 358 } 359 pvo = &moea64_bpvo_pool[ 360 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 361 bzero(pvo, sizeof(*pvo)); 362 pvo->pvo_vaddr = PVO_BOOTSTRAP; 363 } else { 364 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 365 bzero(pvo, sizeof(*pvo)); 366 } 367 368 return (pvo); 369 } 370 371 372 static void 373 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 374 { 375 uint64_t vsid; 376 uint64_t hash; 377 int shift; 378 379 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 380 381 pvo->pvo_pmap = pmap; 382 va &= ~ADDR_POFF; 383 pvo->pvo_vaddr |= va; 384 vsid = va_to_vsid(pmap, va); 385 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 386 | (vsid << 16); 387 388 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 389 ADDR_PIDX_SHFT; 390 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 391 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 392 } 393 394 static void 395 free_pvo_entry(struct pvo_entry *pvo) 396 { 397 398 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 399 uma_zfree(moea64_pvo_zone, pvo); 400 } 401 402 void 403 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 404 { 405 406 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 407 LPTE_AVPN_MASK; 408 lpte->pte_hi |= LPTE_VALID; 409 410 if (pvo->pvo_vaddr & PVO_LARGE) 411 lpte->pte_hi |= LPTE_BIG; 412 if (pvo->pvo_vaddr & PVO_WIRED) 413 lpte->pte_hi |= LPTE_WIRED; 414 if (pvo->pvo_vaddr & PVO_HID) 415 lpte->pte_hi |= LPTE_HID; 416 417 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 418 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 419 lpte->pte_lo |= LPTE_BW; 420 else 421 lpte->pte_lo |= LPTE_BR; 422 423 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 424 lpte->pte_lo |= LPTE_NOEXEC; 425 } 426 427 static __inline uint64_t 428 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 429 { 430 uint64_t pte_lo; 431 int i; 432 433 if (ma != VM_MEMATTR_DEFAULT) { 434 switch (ma) { 435 case VM_MEMATTR_UNCACHEABLE: 436 return (LPTE_I | LPTE_G); 437 case VM_MEMATTR_CACHEABLE: 438 return (LPTE_M); 439 case VM_MEMATTR_WRITE_COMBINING: 440 case VM_MEMATTR_WRITE_BACK: 441 case VM_MEMATTR_PREFETCHABLE: 442 return (LPTE_I); 443 case VM_MEMATTR_WRITE_THROUGH: 444 return (LPTE_W | LPTE_M); 445 } 446 } 447 448 /* 449 * Assume the page is cache inhibited and access is guarded unless 450 * it's in our available memory array. 451 */ 452 pte_lo = LPTE_I | LPTE_G; 453 for (i = 0; i < pregions_sz; i++) { 454 if ((pa >= pregions[i].mr_start) && 455 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 456 pte_lo &= ~(LPTE_I | LPTE_G); 457 pte_lo |= LPTE_M; 458 break; 459 } 460 } 461 462 return pte_lo; 463 } 464 465 /* 466 * Quick sort callout for comparing memory regions. 467 */ 468 static int om_cmp(const void *a, const void *b); 469 470 static int 471 om_cmp(const void *a, const void *b) 472 { 473 const struct ofw_map *mapa; 474 const struct ofw_map *mapb; 475 476 mapa = a; 477 mapb = b; 478 if (mapa->om_pa < mapb->om_pa) 479 return (-1); 480 else if (mapa->om_pa > mapb->om_pa) 481 return (1); 482 else 483 return (0); 484 } 485 486 static void 487 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 488 { 489 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 490 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 491 struct pvo_entry *pvo; 492 register_t msr; 493 vm_offset_t off; 494 vm_paddr_t pa_base; 495 int i, j; 496 497 bzero(translations, sz); 498 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 499 sizeof(acells)); 500 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 501 panic("moea64_bootstrap: can't get ofw translations"); 502 503 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 504 sz /= sizeof(cell_t); 505 for (i = 0, j = 0; i < sz; j++) { 506 translations[j].om_va = trans_cells[i++]; 507 translations[j].om_len = trans_cells[i++]; 508 translations[j].om_pa = trans_cells[i++]; 509 if (acells == 2) { 510 translations[j].om_pa <<= 32; 511 translations[j].om_pa |= trans_cells[i++]; 512 } 513 translations[j].om_mode = trans_cells[i++]; 514 } 515 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 516 i, sz)); 517 518 sz = j; 519 qsort(translations, sz, sizeof (*translations), om_cmp); 520 521 for (i = 0; i < sz; i++) { 522 pa_base = translations[i].om_pa; 523 #ifndef __powerpc64__ 524 if ((translations[i].om_pa >> 32) != 0) 525 panic("OFW translations above 32-bit boundary!"); 526 #endif 527 528 if (pa_base % PAGE_SIZE) 529 panic("OFW translation not page-aligned (phys)!"); 530 if (translations[i].om_va % PAGE_SIZE) 531 panic("OFW translation not page-aligned (virt)!"); 532 533 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 534 pa_base, translations[i].om_va, translations[i].om_len); 535 536 /* Now enter the pages for this mapping */ 537 538 DISABLE_TRANS(msr); 539 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 540 /* If this address is direct-mapped, skip remapping */ 541 if (hw_direct_map && translations[i].om_va == pa_base && 542 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 543 continue; 544 545 PMAP_LOCK(kernel_pmap); 546 pvo = moea64_pvo_find_va(kernel_pmap, 547 translations[i].om_va + off); 548 PMAP_UNLOCK(kernel_pmap); 549 if (pvo != NULL) 550 continue; 551 552 moea64_kenter(mmup, translations[i].om_va + off, 553 pa_base + off); 554 } 555 ENABLE_TRANS(msr); 556 } 557 } 558 559 #ifdef __powerpc64__ 560 static void 561 moea64_probe_large_page(void) 562 { 563 uint16_t pvr = mfpvr() >> 16; 564 565 switch (pvr) { 566 case IBM970: 567 case IBM970FX: 568 case IBM970MP: 569 powerpc_sync(); isync(); 570 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 571 powerpc_sync(); isync(); 572 573 /* FALLTHROUGH */ 574 default: 575 moea64_large_page_size = 0x1000000; /* 16 MB */ 576 moea64_large_page_shift = 24; 577 } 578 579 moea64_large_page_mask = moea64_large_page_size - 1; 580 } 581 582 static void 583 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 584 { 585 struct slb *cache; 586 struct slb entry; 587 uint64_t esid, slbe; 588 uint64_t i; 589 590 cache = PCPU_GET(slb); 591 esid = va >> ADDR_SR_SHFT; 592 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 593 594 for (i = 0; i < 64; i++) { 595 if (cache[i].slbe == (slbe | i)) 596 return; 597 } 598 599 entry.slbe = slbe; 600 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 601 if (large) 602 entry.slbv |= SLBV_L; 603 604 slb_insert_kernel(entry.slbe, entry.slbv); 605 } 606 #endif 607 608 static void 609 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 610 vm_offset_t kernelend) 611 { 612 struct pvo_entry *pvo; 613 register_t msr; 614 vm_paddr_t pa; 615 vm_offset_t size, off; 616 uint64_t pte_lo; 617 int i; 618 619 if (moea64_large_page_size == 0) 620 hw_direct_map = 0; 621 622 DISABLE_TRANS(msr); 623 if (hw_direct_map) { 624 PMAP_LOCK(kernel_pmap); 625 for (i = 0; i < pregions_sz; i++) { 626 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 627 pregions[i].mr_size; pa += moea64_large_page_size) { 628 pte_lo = LPTE_M; 629 630 pvo = alloc_pvo_entry(1 /* bootstrap */); 631 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 632 init_pvo_entry(pvo, kernel_pmap, pa); 633 634 /* 635 * Set memory access as guarded if prefetch within 636 * the page could exit the available physmem area. 637 */ 638 if (pa & moea64_large_page_mask) { 639 pa &= moea64_large_page_mask; 640 pte_lo |= LPTE_G; 641 } 642 if (pa + moea64_large_page_size > 643 pregions[i].mr_start + pregions[i].mr_size) 644 pte_lo |= LPTE_G; 645 646 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 647 VM_PROT_EXECUTE; 648 pvo->pvo_pte.pa = pa | pte_lo; 649 moea64_pvo_enter(mmup, pvo, NULL); 650 } 651 } 652 PMAP_UNLOCK(kernel_pmap); 653 } else { 654 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 655 off = (vm_offset_t)(moea64_bpvo_pool); 656 for (pa = off; pa < off + size; pa += PAGE_SIZE) 657 moea64_kenter(mmup, pa, pa); 658 659 /* 660 * Map certain important things, like ourselves. 661 * 662 * NOTE: We do not map the exception vector space. That code is 663 * used only in real mode, and leaving it unmapped allows us to 664 * catch NULL pointer deferences, instead of making NULL a valid 665 * address. 666 */ 667 668 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 669 pa += PAGE_SIZE) 670 moea64_kenter(mmup, pa, pa); 671 } 672 ENABLE_TRANS(msr); 673 674 /* 675 * Allow user to override unmapped_buf_allowed for testing. 676 * XXXKIB Only direct map implementation was tested. 677 */ 678 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 679 &unmapped_buf_allowed)) 680 unmapped_buf_allowed = hw_direct_map; 681 } 682 683 void 684 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 685 { 686 int i, j; 687 vm_size_t physsz, hwphyssz; 688 689 #ifndef __powerpc64__ 690 /* We don't have a direct map since there is no BAT */ 691 hw_direct_map = 0; 692 693 /* Make sure battable is zero, since we have no BAT */ 694 for (i = 0; i < 16; i++) { 695 battable[i].batu = 0; 696 battable[i].batl = 0; 697 } 698 #else 699 moea64_probe_large_page(); 700 701 /* Use a direct map if we have large page support */ 702 if (moea64_large_page_size > 0) 703 hw_direct_map = 1; 704 else 705 hw_direct_map = 0; 706 #endif 707 708 /* Get physical memory regions from firmware */ 709 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 710 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 711 712 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 713 panic("moea64_bootstrap: phys_avail too small"); 714 715 phys_avail_count = 0; 716 physsz = 0; 717 hwphyssz = 0; 718 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 719 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 720 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 721 regions[i].mr_start, regions[i].mr_start + 722 regions[i].mr_size, regions[i].mr_size); 723 if (hwphyssz != 0 && 724 (physsz + regions[i].mr_size) >= hwphyssz) { 725 if (physsz < hwphyssz) { 726 phys_avail[j] = regions[i].mr_start; 727 phys_avail[j + 1] = regions[i].mr_start + 728 hwphyssz - physsz; 729 physsz = hwphyssz; 730 phys_avail_count++; 731 } 732 break; 733 } 734 phys_avail[j] = regions[i].mr_start; 735 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 736 phys_avail_count++; 737 physsz += regions[i].mr_size; 738 } 739 740 /* Check for overlap with the kernel and exception vectors */ 741 for (j = 0; j < 2*phys_avail_count; j+=2) { 742 if (phys_avail[j] < EXC_LAST) 743 phys_avail[j] += EXC_LAST; 744 745 if (kernelstart >= phys_avail[j] && 746 kernelstart < phys_avail[j+1]) { 747 if (kernelend < phys_avail[j+1]) { 748 phys_avail[2*phys_avail_count] = 749 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 750 phys_avail[2*phys_avail_count + 1] = 751 phys_avail[j+1]; 752 phys_avail_count++; 753 } 754 755 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 756 } 757 758 if (kernelend >= phys_avail[j] && 759 kernelend < phys_avail[j+1]) { 760 if (kernelstart > phys_avail[j]) { 761 phys_avail[2*phys_avail_count] = phys_avail[j]; 762 phys_avail[2*phys_avail_count + 1] = 763 kernelstart & ~PAGE_MASK; 764 phys_avail_count++; 765 } 766 767 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 768 } 769 } 770 771 physmem = btoc(physsz); 772 773 #ifdef PTEGCOUNT 774 moea64_pteg_count = PTEGCOUNT; 775 #else 776 moea64_pteg_count = 0x1000; 777 778 while (moea64_pteg_count < physmem) 779 moea64_pteg_count <<= 1; 780 781 moea64_pteg_count >>= 1; 782 #endif /* PTEGCOUNT */ 783 } 784 785 void 786 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 787 { 788 int i; 789 790 /* 791 * Set PTEG mask 792 */ 793 moea64_pteg_mask = moea64_pteg_count - 1; 794 795 /* 796 * Initialize SLB table lock and page locks 797 */ 798 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 799 for (i = 0; i < PV_LOCK_COUNT; i++) 800 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 801 802 /* 803 * Initialise the bootstrap pvo pool. 804 */ 805 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 806 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 807 moea64_bpvo_pool_index = 0; 808 809 /* 810 * Make sure kernel vsid is allocated as well as VSID 0. 811 */ 812 #ifndef __powerpc64__ 813 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 814 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 815 moea64_vsid_bitmap[0] |= 1; 816 #endif 817 818 /* 819 * Initialize the kernel pmap (which is statically allocated). 820 */ 821 #ifdef __powerpc64__ 822 for (i = 0; i < 64; i++) { 823 pcpup->pc_slb[i].slbv = 0; 824 pcpup->pc_slb[i].slbe = 0; 825 } 826 #else 827 for (i = 0; i < 16; i++) 828 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 829 #endif 830 831 kernel_pmap->pmap_phys = kernel_pmap; 832 CPU_FILL(&kernel_pmap->pm_active); 833 RB_INIT(&kernel_pmap->pmap_pvo); 834 835 PMAP_LOCK_INIT(kernel_pmap); 836 837 /* 838 * Now map in all the other buffers we allocated earlier 839 */ 840 841 moea64_setup_direct_map(mmup, kernelstart, kernelend); 842 } 843 844 void 845 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 846 { 847 ihandle_t mmui; 848 phandle_t chosen; 849 phandle_t mmu; 850 ssize_t sz; 851 int i; 852 vm_offset_t pa, va; 853 void *dpcpu; 854 855 /* 856 * Set up the Open Firmware pmap and add its mappings if not in real 857 * mode. 858 */ 859 860 chosen = OF_finddevice("/chosen"); 861 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 862 mmu = OF_instance_to_package(mmui); 863 if (mmu == -1 || 864 (sz = OF_getproplen(mmu, "translations")) == -1) 865 sz = 0; 866 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 867 panic("moea64_bootstrap: too many ofw translations"); 868 869 if (sz > 0) 870 moea64_add_ofw_mappings(mmup, mmu, sz); 871 } 872 873 /* 874 * Calculate the last available physical address. 875 */ 876 for (i = 0; phys_avail[i + 2] != 0; i += 2) 877 ; 878 Maxmem = powerpc_btop(phys_avail[i + 1]); 879 880 /* 881 * Initialize MMU and remap early physical mappings 882 */ 883 MMU_CPU_BOOTSTRAP(mmup,0); 884 mtmsr(mfmsr() | PSL_DR | PSL_IR); 885 pmap_bootstrapped++; 886 bs_remap_earlyboot(); 887 888 /* 889 * Set the start and end of kva. 890 */ 891 virtual_avail = VM_MIN_KERNEL_ADDRESS; 892 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 893 894 /* 895 * Map the entire KVA range into the SLB. We must not fault there. 896 */ 897 #ifdef __powerpc64__ 898 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 899 moea64_bootstrap_slb_prefault(va, 0); 900 #endif 901 902 /* 903 * Figure out how far we can extend virtual_end into segment 16 904 * without running into existing mappings. Segment 16 is guaranteed 905 * to contain neither RAM nor devices (at least on Apple hardware), 906 * but will generally contain some OFW mappings we should not 907 * step on. 908 */ 909 910 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 911 PMAP_LOCK(kernel_pmap); 912 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 913 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 914 virtual_end += PAGE_SIZE; 915 PMAP_UNLOCK(kernel_pmap); 916 #endif 917 918 /* 919 * Allocate a kernel stack with a guard page for thread0 and map it 920 * into the kernel page map. 921 */ 922 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 923 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 924 virtual_avail = va + kstack_pages * PAGE_SIZE; 925 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 926 thread0.td_kstack = va; 927 thread0.td_kstack_pages = kstack_pages; 928 for (i = 0; i < kstack_pages; i++) { 929 moea64_kenter(mmup, va, pa); 930 pa += PAGE_SIZE; 931 va += PAGE_SIZE; 932 } 933 934 /* 935 * Allocate virtual address space for the message buffer. 936 */ 937 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 938 msgbufp = (struct msgbuf *)virtual_avail; 939 va = virtual_avail; 940 virtual_avail += round_page(msgbufsize); 941 while (va < virtual_avail) { 942 moea64_kenter(mmup, va, pa); 943 pa += PAGE_SIZE; 944 va += PAGE_SIZE; 945 } 946 947 /* 948 * Allocate virtual address space for the dynamic percpu area. 949 */ 950 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 951 dpcpu = (void *)virtual_avail; 952 va = virtual_avail; 953 virtual_avail += DPCPU_SIZE; 954 while (va < virtual_avail) { 955 moea64_kenter(mmup, va, pa); 956 pa += PAGE_SIZE; 957 va += PAGE_SIZE; 958 } 959 dpcpu_init(dpcpu, 0); 960 961 /* 962 * Allocate some things for page zeroing. We put this directly 963 * in the page table and use MOEA64_PTE_REPLACE to avoid any 964 * of the PVO book-keeping or other parts of the VM system 965 * from even knowing that this hack exists. 966 */ 967 968 if (!hw_direct_map) { 969 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 970 MTX_DEF); 971 for (i = 0; i < 2; i++) { 972 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 973 virtual_end -= PAGE_SIZE; 974 975 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 976 977 PMAP_LOCK(kernel_pmap); 978 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 979 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 980 PMAP_UNLOCK(kernel_pmap); 981 } 982 } 983 } 984 985 static void 986 moea64_pmap_init_qpages(void) 987 { 988 struct pcpu *pc; 989 int i; 990 991 if (hw_direct_map) 992 return; 993 994 CPU_FOREACH(i) { 995 pc = pcpu_find(i); 996 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 997 if (pc->pc_qmap_addr == 0) 998 panic("pmap_init_qpages: unable to allocate KVA"); 999 PMAP_LOCK(kernel_pmap); 1000 pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1001 PMAP_UNLOCK(kernel_pmap); 1002 mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF); 1003 } 1004 } 1005 1006 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1007 1008 /* 1009 * Activate a user pmap. This mostly involves setting some non-CPU 1010 * state. 1011 */ 1012 void 1013 moea64_activate(mmu_t mmu, struct thread *td) 1014 { 1015 pmap_t pm; 1016 1017 pm = &td->td_proc->p_vmspace->vm_pmap; 1018 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1019 1020 #ifdef __powerpc64__ 1021 PCPU_SET(userslb, pm->pm_slb); 1022 __asm __volatile("slbmte %0, %1; isync" :: 1023 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1024 #else 1025 PCPU_SET(curpmap, pm->pmap_phys); 1026 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1027 #endif 1028 } 1029 1030 void 1031 moea64_deactivate(mmu_t mmu, struct thread *td) 1032 { 1033 pmap_t pm; 1034 1035 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1036 1037 pm = &td->td_proc->p_vmspace->vm_pmap; 1038 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1039 #ifdef __powerpc64__ 1040 PCPU_SET(userslb, NULL); 1041 #else 1042 PCPU_SET(curpmap, NULL); 1043 #endif 1044 } 1045 1046 void 1047 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1048 { 1049 struct pvo_entry key, *pvo; 1050 vm_page_t m; 1051 int64_t refchg; 1052 1053 key.pvo_vaddr = sva; 1054 PMAP_LOCK(pm); 1055 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1056 pvo != NULL && PVO_VADDR(pvo) < eva; 1057 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1058 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1059 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1060 pvo); 1061 pvo->pvo_vaddr &= ~PVO_WIRED; 1062 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1063 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1064 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1065 if (refchg < 0) 1066 refchg = LPTE_CHG; 1067 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1068 1069 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1070 if (refchg & LPTE_CHG) 1071 vm_page_dirty(m); 1072 if (refchg & LPTE_REF) 1073 vm_page_aflag_set(m, PGA_REFERENCED); 1074 } 1075 pm->pm_stats.wired_count--; 1076 } 1077 PMAP_UNLOCK(pm); 1078 } 1079 1080 /* 1081 * This goes through and sets the physical address of our 1082 * special scratch PTE to the PA we want to zero or copy. Because 1083 * of locking issues (this can get called in pvo_enter() by 1084 * the UMA allocator), we can't use most other utility functions here 1085 */ 1086 1087 static __inline 1088 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1089 1090 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1091 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1092 1093 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1094 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1095 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1096 MOEA64_PTE_INVALIDATE); 1097 isync(); 1098 } 1099 1100 void 1101 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1102 { 1103 vm_offset_t dst; 1104 vm_offset_t src; 1105 1106 dst = VM_PAGE_TO_PHYS(mdst); 1107 src = VM_PAGE_TO_PHYS(msrc); 1108 1109 if (hw_direct_map) { 1110 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1111 } else { 1112 mtx_lock(&moea64_scratchpage_mtx); 1113 1114 moea64_set_scratchpage_pa(mmu, 0, src); 1115 moea64_set_scratchpage_pa(mmu, 1, dst); 1116 1117 bcopy((void *)moea64_scratchpage_va[0], 1118 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1119 1120 mtx_unlock(&moea64_scratchpage_mtx); 1121 } 1122 } 1123 1124 static inline void 1125 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1126 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1127 { 1128 void *a_cp, *b_cp; 1129 vm_offset_t a_pg_offset, b_pg_offset; 1130 int cnt; 1131 1132 while (xfersize > 0) { 1133 a_pg_offset = a_offset & PAGE_MASK; 1134 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1135 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1136 a_pg_offset; 1137 b_pg_offset = b_offset & PAGE_MASK; 1138 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1139 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1140 b_pg_offset; 1141 bcopy(a_cp, b_cp, cnt); 1142 a_offset += cnt; 1143 b_offset += cnt; 1144 xfersize -= cnt; 1145 } 1146 } 1147 1148 static inline void 1149 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1150 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1151 { 1152 void *a_cp, *b_cp; 1153 vm_offset_t a_pg_offset, b_pg_offset; 1154 int cnt; 1155 1156 mtx_lock(&moea64_scratchpage_mtx); 1157 while (xfersize > 0) { 1158 a_pg_offset = a_offset & PAGE_MASK; 1159 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1160 moea64_set_scratchpage_pa(mmu, 0, 1161 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1162 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1163 b_pg_offset = b_offset & PAGE_MASK; 1164 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1165 moea64_set_scratchpage_pa(mmu, 1, 1166 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1167 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1168 bcopy(a_cp, b_cp, cnt); 1169 a_offset += cnt; 1170 b_offset += cnt; 1171 xfersize -= cnt; 1172 } 1173 mtx_unlock(&moea64_scratchpage_mtx); 1174 } 1175 1176 void 1177 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1178 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1179 { 1180 1181 if (hw_direct_map) { 1182 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1183 xfersize); 1184 } else { 1185 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1186 xfersize); 1187 } 1188 } 1189 1190 void 1191 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1192 { 1193 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1194 1195 if (size + off > PAGE_SIZE) 1196 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1197 1198 if (hw_direct_map) { 1199 bzero((caddr_t)pa + off, size); 1200 } else { 1201 mtx_lock(&moea64_scratchpage_mtx); 1202 moea64_set_scratchpage_pa(mmu, 0, pa); 1203 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1204 mtx_unlock(&moea64_scratchpage_mtx); 1205 } 1206 } 1207 1208 /* 1209 * Zero a page of physical memory by temporarily mapping it 1210 */ 1211 void 1212 moea64_zero_page(mmu_t mmu, vm_page_t m) 1213 { 1214 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1215 vm_offset_t va, off; 1216 1217 if (!hw_direct_map) { 1218 mtx_lock(&moea64_scratchpage_mtx); 1219 1220 moea64_set_scratchpage_pa(mmu, 0, pa); 1221 va = moea64_scratchpage_va[0]; 1222 } else { 1223 va = pa; 1224 } 1225 1226 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1227 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1228 1229 if (!hw_direct_map) 1230 mtx_unlock(&moea64_scratchpage_mtx); 1231 } 1232 1233 void 1234 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1235 { 1236 1237 moea64_zero_page(mmu, m); 1238 } 1239 1240 vm_offset_t 1241 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1242 { 1243 struct pvo_entry *pvo; 1244 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1245 1246 if (hw_direct_map) 1247 return (pa); 1248 1249 /* 1250 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1251 * a critical section and access the PCPU data like on i386. 1252 * Instead, pin the thread and grab the PCPU lock to prevent 1253 * a preempting thread from using the same PCPU data. 1254 */ 1255 sched_pin(); 1256 1257 mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED); 1258 pvo = PCPU_GET(qmap_pvo); 1259 1260 mtx_lock(PCPU_PTR(qmap_lock)); 1261 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1262 (uint64_t)pa; 1263 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1264 isync(); 1265 1266 return (PCPU_GET(qmap_addr)); 1267 } 1268 1269 void 1270 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1271 { 1272 if (hw_direct_map) 1273 return; 1274 1275 mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED); 1276 KASSERT(PCPU_GET(qmap_addr) == addr, 1277 ("moea64_quick_remove_page: invalid address")); 1278 mtx_unlock(PCPU_PTR(qmap_lock)); 1279 sched_unpin(); 1280 } 1281 1282 /* 1283 * Map the given physical page at the specified virtual address in the 1284 * target pmap with the protection requested. If specified the page 1285 * will be wired down. 1286 */ 1287 1288 int 1289 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1290 vm_prot_t prot, u_int flags, int8_t psind) 1291 { 1292 struct pvo_entry *pvo, *oldpvo; 1293 struct pvo_head *pvo_head; 1294 uint64_t pte_lo; 1295 int error; 1296 1297 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1298 VM_OBJECT_ASSERT_LOCKED(m->object); 1299 1300 pvo = alloc_pvo_entry(0); 1301 pvo->pvo_pmap = NULL; /* to be filled in later */ 1302 pvo->pvo_pte.prot = prot; 1303 1304 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1305 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1306 1307 if ((flags & PMAP_ENTER_WIRED) != 0) 1308 pvo->pvo_vaddr |= PVO_WIRED; 1309 1310 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1311 pvo_head = NULL; 1312 } else { 1313 pvo_head = &m->md.mdpg_pvoh; 1314 pvo->pvo_vaddr |= PVO_MANAGED; 1315 } 1316 1317 for (;;) { 1318 PV_PAGE_LOCK(m); 1319 PMAP_LOCK(pmap); 1320 if (pvo->pvo_pmap == NULL) 1321 init_pvo_entry(pvo, pmap, va); 1322 if (prot & VM_PROT_WRITE) 1323 if (pmap_bootstrapped && 1324 (m->oflags & VPO_UNMANAGED) == 0) 1325 vm_page_aflag_set(m, PGA_WRITEABLE); 1326 1327 oldpvo = moea64_pvo_find_va(pmap, va); 1328 if (oldpvo != NULL) { 1329 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1330 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1331 oldpvo->pvo_pte.prot == prot) { 1332 /* Identical mapping already exists */ 1333 error = 0; 1334 1335 /* If not in page table, reinsert it */ 1336 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1337 moea64_pte_overflow--; 1338 MOEA64_PTE_INSERT(mmu, oldpvo); 1339 } 1340 1341 /* Then just clean up and go home */ 1342 PV_PAGE_UNLOCK(m); 1343 PMAP_UNLOCK(pmap); 1344 free_pvo_entry(pvo); 1345 break; 1346 } 1347 1348 /* Otherwise, need to kill it first */ 1349 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1350 "mapping does not match new mapping")); 1351 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1352 } 1353 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1354 PV_PAGE_UNLOCK(m); 1355 PMAP_UNLOCK(pmap); 1356 1357 /* Free any dead pages */ 1358 if (oldpvo != NULL) { 1359 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1360 moea64_pvo_remove_from_page(mmu, oldpvo); 1361 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1362 free_pvo_entry(oldpvo); 1363 } 1364 1365 if (error != ENOMEM) 1366 break; 1367 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1368 return (KERN_RESOURCE_SHORTAGE); 1369 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1370 VM_WAIT; 1371 } 1372 1373 /* 1374 * Flush the page from the instruction cache if this page is 1375 * mapped executable and cacheable. 1376 */ 1377 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1378 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1379 vm_page_aflag_set(m, PGA_EXECUTABLE); 1380 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1381 } 1382 return (KERN_SUCCESS); 1383 } 1384 1385 static void 1386 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1387 vm_size_t sz) 1388 { 1389 1390 /* 1391 * This is much trickier than on older systems because 1392 * we can't sync the icache on physical addresses directly 1393 * without a direct map. Instead we check a couple of cases 1394 * where the memory is already mapped in and, failing that, 1395 * use the same trick we use for page zeroing to create 1396 * a temporary mapping for this physical address. 1397 */ 1398 1399 if (!pmap_bootstrapped) { 1400 /* 1401 * If PMAP is not bootstrapped, we are likely to be 1402 * in real mode. 1403 */ 1404 __syncicache((void *)pa, sz); 1405 } else if (pmap == kernel_pmap) { 1406 __syncicache((void *)va, sz); 1407 } else if (hw_direct_map) { 1408 __syncicache((void *)pa, sz); 1409 } else { 1410 /* Use the scratch page to set up a temp mapping */ 1411 1412 mtx_lock(&moea64_scratchpage_mtx); 1413 1414 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1415 __syncicache((void *)(moea64_scratchpage_va[1] + 1416 (va & ADDR_POFF)), sz); 1417 1418 mtx_unlock(&moea64_scratchpage_mtx); 1419 } 1420 } 1421 1422 /* 1423 * Maps a sequence of resident pages belonging to the same object. 1424 * The sequence begins with the given page m_start. This page is 1425 * mapped at the given virtual address start. Each subsequent page is 1426 * mapped at a virtual address that is offset from start by the same 1427 * amount as the page is offset from m_start within the object. The 1428 * last page in the sequence is the page with the largest offset from 1429 * m_start that can be mapped at a virtual address less than the given 1430 * virtual address end. Not every virtual page between start and end 1431 * is mapped; only those for which a resident page exists with the 1432 * corresponding offset from m_start are mapped. 1433 */ 1434 void 1435 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1436 vm_page_t m_start, vm_prot_t prot) 1437 { 1438 vm_page_t m; 1439 vm_pindex_t diff, psize; 1440 1441 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1442 1443 psize = atop(end - start); 1444 m = m_start; 1445 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1446 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1447 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1448 m = TAILQ_NEXT(m, listq); 1449 } 1450 } 1451 1452 void 1453 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1454 vm_prot_t prot) 1455 { 1456 1457 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1458 PMAP_ENTER_NOSLEEP, 0); 1459 } 1460 1461 vm_paddr_t 1462 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1463 { 1464 struct pvo_entry *pvo; 1465 vm_paddr_t pa; 1466 1467 PMAP_LOCK(pm); 1468 pvo = moea64_pvo_find_va(pm, va); 1469 if (pvo == NULL) 1470 pa = 0; 1471 else 1472 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1473 PMAP_UNLOCK(pm); 1474 1475 return (pa); 1476 } 1477 1478 /* 1479 * Atomically extract and hold the physical page with the given 1480 * pmap and virtual address pair if that mapping permits the given 1481 * protection. 1482 */ 1483 vm_page_t 1484 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1485 { 1486 struct pvo_entry *pvo; 1487 vm_page_t m; 1488 vm_paddr_t pa; 1489 1490 m = NULL; 1491 pa = 0; 1492 PMAP_LOCK(pmap); 1493 retry: 1494 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1495 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1496 if (vm_page_pa_tryrelock(pmap, 1497 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1498 goto retry; 1499 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1500 vm_page_hold(m); 1501 } 1502 PA_UNLOCK_COND(pa); 1503 PMAP_UNLOCK(pmap); 1504 return (m); 1505 } 1506 1507 static mmu_t installed_mmu; 1508 1509 static void * 1510 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 1511 int wait) 1512 { 1513 struct pvo_entry *pvo; 1514 vm_offset_t va; 1515 vm_page_t m; 1516 int pflags, needed_lock; 1517 1518 /* 1519 * This entire routine is a horrible hack to avoid bothering kmem 1520 * for new KVA addresses. Because this can get called from inside 1521 * kmem allocation routines, calling kmem for a new address here 1522 * can lead to multiply locking non-recursive mutexes. 1523 */ 1524 1525 *flags = UMA_SLAB_PRIV; 1526 needed_lock = !PMAP_LOCKED(kernel_pmap); 1527 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1528 1529 for (;;) { 1530 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1531 if (m == NULL) { 1532 if (wait & M_NOWAIT) 1533 return (NULL); 1534 VM_WAIT; 1535 } else 1536 break; 1537 } 1538 1539 va = VM_PAGE_TO_PHYS(m); 1540 1541 pvo = alloc_pvo_entry(1 /* bootstrap */); 1542 1543 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1544 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1545 1546 if (needed_lock) 1547 PMAP_LOCK(kernel_pmap); 1548 1549 init_pvo_entry(pvo, kernel_pmap, va); 1550 pvo->pvo_vaddr |= PVO_WIRED; 1551 1552 moea64_pvo_enter(installed_mmu, pvo, NULL); 1553 1554 if (needed_lock) 1555 PMAP_UNLOCK(kernel_pmap); 1556 1557 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1558 bzero((void *)va, PAGE_SIZE); 1559 1560 return (void *)va; 1561 } 1562 1563 extern int elf32_nxstack; 1564 1565 void 1566 moea64_init(mmu_t mmu) 1567 { 1568 1569 CTR0(KTR_PMAP, "moea64_init"); 1570 1571 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1572 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1573 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1574 1575 if (!hw_direct_map) { 1576 installed_mmu = mmu; 1577 uma_zone_set_allocf(moea64_pvo_zone,moea64_uma_page_alloc); 1578 } 1579 1580 #ifdef COMPAT_FREEBSD32 1581 elf32_nxstack = 1; 1582 #endif 1583 1584 moea64_initialized = TRUE; 1585 } 1586 1587 boolean_t 1588 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1589 { 1590 1591 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1592 ("moea64_is_referenced: page %p is not managed", m)); 1593 1594 return (moea64_query_bit(mmu, m, LPTE_REF)); 1595 } 1596 1597 boolean_t 1598 moea64_is_modified(mmu_t mmu, vm_page_t m) 1599 { 1600 1601 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1602 ("moea64_is_modified: page %p is not managed", m)); 1603 1604 /* 1605 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1606 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1607 * is clear, no PTEs can have LPTE_CHG set. 1608 */ 1609 VM_OBJECT_ASSERT_LOCKED(m->object); 1610 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1611 return (FALSE); 1612 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1613 } 1614 1615 boolean_t 1616 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1617 { 1618 struct pvo_entry *pvo; 1619 boolean_t rv = TRUE; 1620 1621 PMAP_LOCK(pmap); 1622 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1623 if (pvo != NULL) 1624 rv = FALSE; 1625 PMAP_UNLOCK(pmap); 1626 return (rv); 1627 } 1628 1629 void 1630 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1631 { 1632 1633 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1634 ("moea64_clear_modify: page %p is not managed", m)); 1635 VM_OBJECT_ASSERT_WLOCKED(m->object); 1636 KASSERT(!vm_page_xbusied(m), 1637 ("moea64_clear_modify: page %p is exclusive busied", m)); 1638 1639 /* 1640 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1641 * set. If the object containing the page is locked and the page is 1642 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1643 */ 1644 if ((m->aflags & PGA_WRITEABLE) == 0) 1645 return; 1646 moea64_clear_bit(mmu, m, LPTE_CHG); 1647 } 1648 1649 /* 1650 * Clear the write and modified bits in each of the given page's mappings. 1651 */ 1652 void 1653 moea64_remove_write(mmu_t mmu, vm_page_t m) 1654 { 1655 struct pvo_entry *pvo; 1656 int64_t refchg, ret; 1657 pmap_t pmap; 1658 1659 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1660 ("moea64_remove_write: page %p is not managed", m)); 1661 1662 /* 1663 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1664 * set by another thread while the object is locked. Thus, 1665 * if PGA_WRITEABLE is clear, no page table entries need updating. 1666 */ 1667 VM_OBJECT_ASSERT_WLOCKED(m->object); 1668 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1669 return; 1670 powerpc_sync(); 1671 PV_PAGE_LOCK(m); 1672 refchg = 0; 1673 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1674 pmap = pvo->pvo_pmap; 1675 PMAP_LOCK(pmap); 1676 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1677 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1678 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1679 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1680 MOEA64_PTE_PROT_UPDATE); 1681 if (ret < 0) 1682 ret = LPTE_CHG; 1683 refchg |= ret; 1684 if (pvo->pvo_pmap == kernel_pmap) 1685 isync(); 1686 } 1687 PMAP_UNLOCK(pmap); 1688 } 1689 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1690 vm_page_dirty(m); 1691 vm_page_aflag_clear(m, PGA_WRITEABLE); 1692 PV_PAGE_UNLOCK(m); 1693 } 1694 1695 /* 1696 * moea64_ts_referenced: 1697 * 1698 * Return a count of reference bits for a page, clearing those bits. 1699 * It is not necessary for every reference bit to be cleared, but it 1700 * is necessary that 0 only be returned when there are truly no 1701 * reference bits set. 1702 * 1703 * XXX: The exact number of bits to check and clear is a matter that 1704 * should be tested and standardized at some point in the future for 1705 * optimal aging of shared pages. 1706 */ 1707 int 1708 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1709 { 1710 1711 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1712 ("moea64_ts_referenced: page %p is not managed", m)); 1713 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1714 } 1715 1716 /* 1717 * Modify the WIMG settings of all mappings for a page. 1718 */ 1719 void 1720 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1721 { 1722 struct pvo_entry *pvo; 1723 int64_t refchg; 1724 pmap_t pmap; 1725 uint64_t lo; 1726 1727 if ((m->oflags & VPO_UNMANAGED) != 0) { 1728 m->md.mdpg_cache_attrs = ma; 1729 return; 1730 } 1731 1732 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1733 1734 PV_PAGE_LOCK(m); 1735 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1736 pmap = pvo->pvo_pmap; 1737 PMAP_LOCK(pmap); 1738 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1739 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1740 pvo->pvo_pte.pa |= lo; 1741 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1742 MOEA64_PTE_INVALIDATE); 1743 if (refchg < 0) 1744 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1745 LPTE_CHG : 0; 1746 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1747 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1748 refchg |= 1749 atomic_readandclear_32(&m->md.mdpg_attrs); 1750 if (refchg & LPTE_CHG) 1751 vm_page_dirty(m); 1752 if (refchg & LPTE_REF) 1753 vm_page_aflag_set(m, PGA_REFERENCED); 1754 } 1755 if (pvo->pvo_pmap == kernel_pmap) 1756 isync(); 1757 } 1758 PMAP_UNLOCK(pmap); 1759 } 1760 m->md.mdpg_cache_attrs = ma; 1761 PV_PAGE_UNLOCK(m); 1762 } 1763 1764 /* 1765 * Map a wired page into kernel virtual address space. 1766 */ 1767 void 1768 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1769 { 1770 int error; 1771 struct pvo_entry *pvo, *oldpvo; 1772 1773 pvo = alloc_pvo_entry(0); 1774 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1775 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1776 pvo->pvo_vaddr |= PVO_WIRED; 1777 1778 PMAP_LOCK(kernel_pmap); 1779 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1780 if (oldpvo != NULL) 1781 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1782 init_pvo_entry(pvo, kernel_pmap, va); 1783 error = moea64_pvo_enter(mmu, pvo, NULL); 1784 PMAP_UNLOCK(kernel_pmap); 1785 1786 /* Free any dead pages */ 1787 if (oldpvo != NULL) { 1788 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1789 moea64_pvo_remove_from_page(mmu, oldpvo); 1790 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1791 free_pvo_entry(oldpvo); 1792 } 1793 1794 if (error != 0 && error != ENOENT) 1795 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1796 pa, error); 1797 } 1798 1799 void 1800 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1801 { 1802 1803 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1804 } 1805 1806 /* 1807 * Extract the physical page address associated with the given kernel virtual 1808 * address. 1809 */ 1810 vm_paddr_t 1811 moea64_kextract(mmu_t mmu, vm_offset_t va) 1812 { 1813 struct pvo_entry *pvo; 1814 vm_paddr_t pa; 1815 1816 /* 1817 * Shortcut the direct-mapped case when applicable. We never put 1818 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1819 */ 1820 if (va < VM_MIN_KERNEL_ADDRESS) 1821 return (va); 1822 1823 PMAP_LOCK(kernel_pmap); 1824 pvo = moea64_pvo_find_va(kernel_pmap, va); 1825 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1826 va)); 1827 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1828 PMAP_UNLOCK(kernel_pmap); 1829 return (pa); 1830 } 1831 1832 /* 1833 * Remove a wired page from kernel virtual address space. 1834 */ 1835 void 1836 moea64_kremove(mmu_t mmu, vm_offset_t va) 1837 { 1838 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1839 } 1840 1841 /* 1842 * Map a range of physical addresses into kernel virtual address space. 1843 * 1844 * The value passed in *virt is a suggested virtual address for the mapping. 1845 * Architectures which can support a direct-mapped physical to virtual region 1846 * can return the appropriate address within that region, leaving '*virt' 1847 * unchanged. Other architectures should map the pages starting at '*virt' and 1848 * update '*virt' with the first usable address after the mapped region. 1849 */ 1850 vm_offset_t 1851 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1852 vm_paddr_t pa_end, int prot) 1853 { 1854 vm_offset_t sva, va; 1855 1856 if (hw_direct_map) { 1857 /* 1858 * Check if every page in the region is covered by the direct 1859 * map. The direct map covers all of physical memory. Use 1860 * moea64_calc_wimg() as a shortcut to see if the page is in 1861 * physical memory as a way to see if the direct map covers it. 1862 */ 1863 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1864 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1865 break; 1866 if (va == pa_end) 1867 return (pa_start); 1868 } 1869 sva = *virt; 1870 va = sva; 1871 /* XXX respect prot argument */ 1872 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1873 moea64_kenter(mmu, va, pa_start); 1874 *virt = va; 1875 1876 return (sva); 1877 } 1878 1879 /* 1880 * Returns true if the pmap's pv is one of the first 1881 * 16 pvs linked to from this page. This count may 1882 * be changed upwards or downwards in the future; it 1883 * is only necessary that true be returned for a small 1884 * subset of pmaps for proper page aging. 1885 */ 1886 boolean_t 1887 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1888 { 1889 int loops; 1890 struct pvo_entry *pvo; 1891 boolean_t rv; 1892 1893 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1894 ("moea64_page_exists_quick: page %p is not managed", m)); 1895 loops = 0; 1896 rv = FALSE; 1897 PV_PAGE_LOCK(m); 1898 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1899 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 1900 rv = TRUE; 1901 break; 1902 } 1903 if (++loops >= 16) 1904 break; 1905 } 1906 PV_PAGE_UNLOCK(m); 1907 return (rv); 1908 } 1909 1910 /* 1911 * Return the number of managed mappings to the given physical page 1912 * that are wired. 1913 */ 1914 int 1915 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1916 { 1917 struct pvo_entry *pvo; 1918 int count; 1919 1920 count = 0; 1921 if ((m->oflags & VPO_UNMANAGED) != 0) 1922 return (count); 1923 PV_PAGE_LOCK(m); 1924 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1925 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 1926 count++; 1927 PV_PAGE_UNLOCK(m); 1928 return (count); 1929 } 1930 1931 static uintptr_t moea64_vsidcontext; 1932 1933 uintptr_t 1934 moea64_get_unique_vsid(void) { 1935 u_int entropy; 1936 register_t hash; 1937 uint32_t mask; 1938 int i; 1939 1940 entropy = 0; 1941 __asm __volatile("mftb %0" : "=r"(entropy)); 1942 1943 mtx_lock(&moea64_slb_mutex); 1944 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1945 u_int n; 1946 1947 /* 1948 * Create a new value by mutiplying by a prime and adding in 1949 * entropy from the timebase register. This is to make the 1950 * VSID more random so that the PT hash function collides 1951 * less often. (Note that the prime casues gcc to do shifts 1952 * instead of a multiply.) 1953 */ 1954 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1955 hash = moea64_vsidcontext & (NVSIDS - 1); 1956 if (hash == 0) /* 0 is special, avoid it */ 1957 continue; 1958 n = hash >> 5; 1959 mask = 1 << (hash & (VSID_NBPW - 1)); 1960 hash = (moea64_vsidcontext & VSID_HASHMASK); 1961 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1962 /* anything free in this bucket? */ 1963 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1964 entropy = (moea64_vsidcontext >> 20); 1965 continue; 1966 } 1967 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1968 mask = 1 << i; 1969 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 1970 hash |= i; 1971 } 1972 if (hash == VSID_VRMA) /* also special, avoid this too */ 1973 continue; 1974 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1975 ("Allocating in-use VSID %#zx\n", hash)); 1976 moea64_vsid_bitmap[n] |= mask; 1977 mtx_unlock(&moea64_slb_mutex); 1978 return (hash); 1979 } 1980 1981 mtx_unlock(&moea64_slb_mutex); 1982 panic("%s: out of segments",__func__); 1983 } 1984 1985 #ifdef __powerpc64__ 1986 void 1987 moea64_pinit(mmu_t mmu, pmap_t pmap) 1988 { 1989 1990 RB_INIT(&pmap->pmap_pvo); 1991 1992 pmap->pm_slb_tree_root = slb_alloc_tree(); 1993 pmap->pm_slb = slb_alloc_user_cache(); 1994 pmap->pm_slb_len = 0; 1995 } 1996 #else 1997 void 1998 moea64_pinit(mmu_t mmu, pmap_t pmap) 1999 { 2000 int i; 2001 uint32_t hash; 2002 2003 RB_INIT(&pmap->pmap_pvo); 2004 2005 if (pmap_bootstrapped) 2006 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2007 (vm_offset_t)pmap); 2008 else 2009 pmap->pmap_phys = pmap; 2010 2011 /* 2012 * Allocate some segment registers for this pmap. 2013 */ 2014 hash = moea64_get_unique_vsid(); 2015 2016 for (i = 0; i < 16; i++) 2017 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2018 2019 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2020 } 2021 #endif 2022 2023 /* 2024 * Initialize the pmap associated with process 0. 2025 */ 2026 void 2027 moea64_pinit0(mmu_t mmu, pmap_t pm) 2028 { 2029 2030 PMAP_LOCK_INIT(pm); 2031 moea64_pinit(mmu, pm); 2032 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2033 } 2034 2035 /* 2036 * Set the physical protection on the specified range of this map as requested. 2037 */ 2038 static void 2039 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2040 { 2041 struct vm_page *pg; 2042 vm_prot_t oldprot; 2043 int32_t refchg; 2044 2045 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2046 2047 /* 2048 * Change the protection of the page. 2049 */ 2050 oldprot = pvo->pvo_pte.prot; 2051 pvo->pvo_pte.prot = prot; 2052 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2053 2054 /* 2055 * If the PVO is in the page table, update mapping 2056 */ 2057 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2058 if (refchg < 0) 2059 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2060 2061 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2062 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2063 if ((pg->oflags & VPO_UNMANAGED) == 0) 2064 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2065 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2066 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2067 } 2068 2069 /* 2070 * Update vm about the REF/CHG bits if the page is managed and we have 2071 * removed write access. 2072 */ 2073 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2074 (oldprot & VM_PROT_WRITE)) { 2075 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2076 if (refchg & LPTE_CHG) 2077 vm_page_dirty(pg); 2078 if (refchg & LPTE_REF) 2079 vm_page_aflag_set(pg, PGA_REFERENCED); 2080 } 2081 } 2082 2083 void 2084 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2085 vm_prot_t prot) 2086 { 2087 struct pvo_entry *pvo, *tpvo, key; 2088 2089 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2090 sva, eva, prot); 2091 2092 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2093 ("moea64_protect: non current pmap")); 2094 2095 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2096 moea64_remove(mmu, pm, sva, eva); 2097 return; 2098 } 2099 2100 PMAP_LOCK(pm); 2101 key.pvo_vaddr = sva; 2102 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2103 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2104 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2105 moea64_pvo_protect(mmu, pm, pvo, prot); 2106 } 2107 PMAP_UNLOCK(pm); 2108 } 2109 2110 /* 2111 * Map a list of wired pages into kernel virtual address space. This is 2112 * intended for temporary mappings which do not need page modification or 2113 * references recorded. Existing mappings in the region are overwritten. 2114 */ 2115 void 2116 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2117 { 2118 while (count-- > 0) { 2119 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2120 va += PAGE_SIZE; 2121 m++; 2122 } 2123 } 2124 2125 /* 2126 * Remove page mappings from kernel virtual address space. Intended for 2127 * temporary mappings entered by moea64_qenter. 2128 */ 2129 void 2130 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2131 { 2132 while (count-- > 0) { 2133 moea64_kremove(mmu, va); 2134 va += PAGE_SIZE; 2135 } 2136 } 2137 2138 void 2139 moea64_release_vsid(uint64_t vsid) 2140 { 2141 int idx, mask; 2142 2143 mtx_lock(&moea64_slb_mutex); 2144 idx = vsid & (NVSIDS-1); 2145 mask = 1 << (idx % VSID_NBPW); 2146 idx /= VSID_NBPW; 2147 KASSERT(moea64_vsid_bitmap[idx] & mask, 2148 ("Freeing unallocated VSID %#jx", vsid)); 2149 moea64_vsid_bitmap[idx] &= ~mask; 2150 mtx_unlock(&moea64_slb_mutex); 2151 } 2152 2153 2154 void 2155 moea64_release(mmu_t mmu, pmap_t pmap) 2156 { 2157 2158 /* 2159 * Free segment registers' VSIDs 2160 */ 2161 #ifdef __powerpc64__ 2162 slb_free_tree(pmap); 2163 slb_free_user_cache(pmap->pm_slb); 2164 #else 2165 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2166 2167 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2168 #endif 2169 } 2170 2171 /* 2172 * Remove all pages mapped by the specified pmap 2173 */ 2174 void 2175 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2176 { 2177 struct pvo_entry *pvo, *tpvo; 2178 struct pvo_tree tofree; 2179 2180 RB_INIT(&tofree); 2181 2182 PMAP_LOCK(pm); 2183 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2184 if (pvo->pvo_vaddr & PVO_WIRED) 2185 continue; 2186 2187 /* 2188 * For locking reasons, remove this from the page table and 2189 * pmap, but save delinking from the vm_page for a second 2190 * pass 2191 */ 2192 moea64_pvo_remove_from_pmap(mmu, pvo); 2193 RB_INSERT(pvo_tree, &tofree, pvo); 2194 } 2195 PMAP_UNLOCK(pm); 2196 2197 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2198 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2199 moea64_pvo_remove_from_page(mmu, pvo); 2200 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2201 RB_REMOVE(pvo_tree, &tofree, pvo); 2202 free_pvo_entry(pvo); 2203 } 2204 } 2205 2206 /* 2207 * Remove the given range of addresses from the specified map. 2208 */ 2209 void 2210 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2211 { 2212 struct pvo_entry *pvo, *tpvo, key; 2213 struct pvo_tree tofree; 2214 2215 /* 2216 * Perform an unsynchronized read. This is, however, safe. 2217 */ 2218 if (pm->pm_stats.resident_count == 0) 2219 return; 2220 2221 key.pvo_vaddr = sva; 2222 2223 RB_INIT(&tofree); 2224 2225 PMAP_LOCK(pm); 2226 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2227 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2228 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2229 2230 /* 2231 * For locking reasons, remove this from the page table and 2232 * pmap, but save delinking from the vm_page for a second 2233 * pass 2234 */ 2235 moea64_pvo_remove_from_pmap(mmu, pvo); 2236 RB_INSERT(pvo_tree, &tofree, pvo); 2237 } 2238 PMAP_UNLOCK(pm); 2239 2240 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2241 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2242 moea64_pvo_remove_from_page(mmu, pvo); 2243 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2244 RB_REMOVE(pvo_tree, &tofree, pvo); 2245 free_pvo_entry(pvo); 2246 } 2247 } 2248 2249 /* 2250 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2251 * will reflect changes in pte's back to the vm_page. 2252 */ 2253 void 2254 moea64_remove_all(mmu_t mmu, vm_page_t m) 2255 { 2256 struct pvo_entry *pvo, *next_pvo; 2257 struct pvo_head freequeue; 2258 int wasdead; 2259 pmap_t pmap; 2260 2261 LIST_INIT(&freequeue); 2262 2263 PV_PAGE_LOCK(m); 2264 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2265 pmap = pvo->pvo_pmap; 2266 PMAP_LOCK(pmap); 2267 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2268 if (!wasdead) 2269 moea64_pvo_remove_from_pmap(mmu, pvo); 2270 moea64_pvo_remove_from_page(mmu, pvo); 2271 if (!wasdead) 2272 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2273 PMAP_UNLOCK(pmap); 2274 2275 } 2276 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2277 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2278 PV_PAGE_UNLOCK(m); 2279 2280 /* Clean up UMA allocations */ 2281 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2282 free_pvo_entry(pvo); 2283 } 2284 2285 /* 2286 * Allocate a physical page of memory directly from the phys_avail map. 2287 * Can only be called from moea64_bootstrap before avail start and end are 2288 * calculated. 2289 */ 2290 vm_offset_t 2291 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2292 { 2293 vm_offset_t s, e; 2294 int i, j; 2295 2296 size = round_page(size); 2297 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2298 if (align != 0) 2299 s = roundup2(phys_avail[i], align); 2300 else 2301 s = phys_avail[i]; 2302 e = s + size; 2303 2304 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2305 continue; 2306 2307 if (s + size > platform_real_maxaddr()) 2308 continue; 2309 2310 if (s == phys_avail[i]) { 2311 phys_avail[i] += size; 2312 } else if (e == phys_avail[i + 1]) { 2313 phys_avail[i + 1] -= size; 2314 } else { 2315 for (j = phys_avail_count * 2; j > i; j -= 2) { 2316 phys_avail[j] = phys_avail[j - 2]; 2317 phys_avail[j + 1] = phys_avail[j - 1]; 2318 } 2319 2320 phys_avail[i + 3] = phys_avail[i + 1]; 2321 phys_avail[i + 1] = s; 2322 phys_avail[i + 2] = e; 2323 phys_avail_count++; 2324 } 2325 2326 return (s); 2327 } 2328 panic("moea64_bootstrap_alloc: could not allocate memory"); 2329 } 2330 2331 static int 2332 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2333 { 2334 int first, err; 2335 2336 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2337 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2338 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2339 2340 moea64_pvo_enter_calls++; 2341 2342 /* 2343 * Add to pmap list 2344 */ 2345 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2346 2347 /* 2348 * Remember if the list was empty and therefore will be the first 2349 * item. 2350 */ 2351 if (pvo_head != NULL) { 2352 if (LIST_FIRST(pvo_head) == NULL) 2353 first = 1; 2354 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2355 } 2356 2357 if (pvo->pvo_vaddr & PVO_WIRED) 2358 pvo->pvo_pmap->pm_stats.wired_count++; 2359 pvo->pvo_pmap->pm_stats.resident_count++; 2360 2361 /* 2362 * Insert it into the hardware page table 2363 */ 2364 err = MOEA64_PTE_INSERT(mmu, pvo); 2365 if (err != 0) { 2366 panic("moea64_pvo_enter: overflow"); 2367 } 2368 2369 moea64_pvo_entries++; 2370 2371 if (pvo->pvo_pmap == kernel_pmap) 2372 isync(); 2373 2374 #ifdef __powerpc64__ 2375 /* 2376 * Make sure all our bootstrap mappings are in the SLB as soon 2377 * as virtual memory is switched on. 2378 */ 2379 if (!pmap_bootstrapped) 2380 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2381 pvo->pvo_vaddr & PVO_LARGE); 2382 #endif 2383 2384 return (first ? ENOENT : 0); 2385 } 2386 2387 static void 2388 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2389 { 2390 struct vm_page *pg; 2391 int32_t refchg; 2392 2393 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2394 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2395 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2396 2397 /* 2398 * If there is an active pte entry, we need to deactivate it 2399 */ 2400 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2401 if (refchg < 0) { 2402 /* 2403 * If it was evicted from the page table, be pessimistic and 2404 * dirty the page. 2405 */ 2406 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2407 refchg = LPTE_CHG; 2408 else 2409 refchg = 0; 2410 } 2411 2412 /* 2413 * Update our statistics. 2414 */ 2415 pvo->pvo_pmap->pm_stats.resident_count--; 2416 if (pvo->pvo_vaddr & PVO_WIRED) 2417 pvo->pvo_pmap->pm_stats.wired_count--; 2418 2419 /* 2420 * Remove this PVO from the pmap list. 2421 */ 2422 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2423 2424 /* 2425 * Mark this for the next sweep 2426 */ 2427 pvo->pvo_vaddr |= PVO_DEAD; 2428 2429 /* Send RC bits to VM */ 2430 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2431 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2432 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2433 if (pg != NULL) { 2434 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2435 if (refchg & LPTE_CHG) 2436 vm_page_dirty(pg); 2437 if (refchg & LPTE_REF) 2438 vm_page_aflag_set(pg, PGA_REFERENCED); 2439 } 2440 } 2441 } 2442 2443 static void 2444 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2445 { 2446 struct vm_page *pg; 2447 2448 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2449 2450 /* Use NULL pmaps as a sentinel for races in page deletion */ 2451 if (pvo->pvo_pmap == NULL) 2452 return; 2453 pvo->pvo_pmap = NULL; 2454 2455 /* 2456 * Update vm about page writeability/executability if managed 2457 */ 2458 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2459 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2460 2461 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) { 2462 LIST_REMOVE(pvo, pvo_vlink); 2463 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2464 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE); 2465 } 2466 2467 moea64_pvo_entries--; 2468 moea64_pvo_remove_calls++; 2469 } 2470 2471 static struct pvo_entry * 2472 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2473 { 2474 struct pvo_entry key; 2475 2476 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2477 2478 key.pvo_vaddr = va & ~ADDR_POFF; 2479 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2480 } 2481 2482 static boolean_t 2483 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2484 { 2485 struct pvo_entry *pvo; 2486 int64_t ret; 2487 boolean_t rv; 2488 2489 /* 2490 * See if this bit is stored in the page already. 2491 */ 2492 if (m->md.mdpg_attrs & ptebit) 2493 return (TRUE); 2494 2495 /* 2496 * Examine each PTE. Sync so that any pending REF/CHG bits are 2497 * flushed to the PTEs. 2498 */ 2499 rv = FALSE; 2500 powerpc_sync(); 2501 PV_PAGE_LOCK(m); 2502 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2503 ret = 0; 2504 2505 /* 2506 * See if this pvo has a valid PTE. if so, fetch the 2507 * REF/CHG bits from the valid PTE. If the appropriate 2508 * ptebit is set, return success. 2509 */ 2510 PMAP_LOCK(pvo->pvo_pmap); 2511 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2512 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2513 PMAP_UNLOCK(pvo->pvo_pmap); 2514 2515 if (ret > 0) { 2516 atomic_set_32(&m->md.mdpg_attrs, 2517 ret & (LPTE_CHG | LPTE_REF)); 2518 if (ret & ptebit) { 2519 rv = TRUE; 2520 break; 2521 } 2522 } 2523 } 2524 PV_PAGE_UNLOCK(m); 2525 2526 return (rv); 2527 } 2528 2529 static u_int 2530 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2531 { 2532 u_int count; 2533 struct pvo_entry *pvo; 2534 int64_t ret; 2535 2536 /* 2537 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2538 * we can reset the right ones). 2539 */ 2540 powerpc_sync(); 2541 2542 /* 2543 * For each pvo entry, clear the pte's ptebit. 2544 */ 2545 count = 0; 2546 PV_PAGE_LOCK(m); 2547 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2548 ret = 0; 2549 2550 PMAP_LOCK(pvo->pvo_pmap); 2551 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2552 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2553 PMAP_UNLOCK(pvo->pvo_pmap); 2554 2555 if (ret > 0 && (ret & ptebit)) 2556 count++; 2557 } 2558 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2559 PV_PAGE_UNLOCK(m); 2560 2561 return (count); 2562 } 2563 2564 boolean_t 2565 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2566 { 2567 struct pvo_entry *pvo, key; 2568 vm_offset_t ppa; 2569 int error = 0; 2570 2571 PMAP_LOCK(kernel_pmap); 2572 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2573 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2574 ppa < pa + size; ppa += PAGE_SIZE, 2575 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2576 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2577 error = EFAULT; 2578 break; 2579 } 2580 } 2581 PMAP_UNLOCK(kernel_pmap); 2582 2583 return (error); 2584 } 2585 2586 /* 2587 * Map a set of physical memory pages into the kernel virtual 2588 * address space. Return a pointer to where it is mapped. This 2589 * routine is intended to be used for mapping device memory, 2590 * NOT real memory. 2591 */ 2592 void * 2593 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2594 { 2595 vm_offset_t va, tmpva, ppa, offset; 2596 2597 ppa = trunc_page(pa); 2598 offset = pa & PAGE_MASK; 2599 size = roundup2(offset + size, PAGE_SIZE); 2600 2601 va = kva_alloc(size); 2602 2603 if (!va) 2604 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2605 2606 for (tmpva = va; size > 0;) { 2607 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2608 size -= PAGE_SIZE; 2609 tmpva += PAGE_SIZE; 2610 ppa += PAGE_SIZE; 2611 } 2612 2613 return ((void *)(va + offset)); 2614 } 2615 2616 void * 2617 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2618 { 2619 2620 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2621 } 2622 2623 void 2624 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2625 { 2626 vm_offset_t base, offset; 2627 2628 base = trunc_page(va); 2629 offset = va & PAGE_MASK; 2630 size = roundup2(offset + size, PAGE_SIZE); 2631 2632 kva_free(base, size); 2633 } 2634 2635 void 2636 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2637 { 2638 struct pvo_entry *pvo; 2639 vm_offset_t lim; 2640 vm_paddr_t pa; 2641 vm_size_t len; 2642 2643 PMAP_LOCK(pm); 2644 while (sz > 0) { 2645 lim = round_page(va); 2646 len = MIN(lim - va, sz); 2647 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2648 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2649 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2650 moea64_syncicache(mmu, pm, va, pa, len); 2651 } 2652 va += len; 2653 sz -= len; 2654 } 2655 PMAP_UNLOCK(pm); 2656 } 2657 2658 void 2659 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2660 { 2661 2662 *va = (void *)pa; 2663 } 2664 2665 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2666 2667 void 2668 moea64_scan_init(mmu_t mmu) 2669 { 2670 struct pvo_entry *pvo; 2671 vm_offset_t va; 2672 int i; 2673 2674 if (!do_minidump) { 2675 /* Initialize phys. segments for dumpsys(). */ 2676 memset(&dump_map, 0, sizeof(dump_map)); 2677 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2678 for (i = 0; i < pregions_sz; i++) { 2679 dump_map[i].pa_start = pregions[i].mr_start; 2680 dump_map[i].pa_size = pregions[i].mr_size; 2681 } 2682 return; 2683 } 2684 2685 /* Virtual segments for minidumps: */ 2686 memset(&dump_map, 0, sizeof(dump_map)); 2687 2688 /* 1st: kernel .data and .bss. */ 2689 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2690 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2691 dump_map[0].pa_start; 2692 2693 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2694 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2695 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2696 2697 /* 3rd: kernel VM. */ 2698 va = dump_map[1].pa_start + dump_map[1].pa_size; 2699 /* Find start of next chunk (from va). */ 2700 while (va < virtual_end) { 2701 /* Don't dump the buffer cache. */ 2702 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2703 va = kmi.buffer_eva; 2704 continue; 2705 } 2706 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2707 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2708 break; 2709 va += PAGE_SIZE; 2710 } 2711 if (va < virtual_end) { 2712 dump_map[2].pa_start = va; 2713 va += PAGE_SIZE; 2714 /* Find last page in chunk. */ 2715 while (va < virtual_end) { 2716 /* Don't run into the buffer cache. */ 2717 if (va == kmi.buffer_sva) 2718 break; 2719 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2720 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2721 break; 2722 va += PAGE_SIZE; 2723 } 2724 dump_map[2].pa_size = va - dump_map[2].pa_start; 2725 } 2726 } 2727 2728