xref: /freebsd/sys/powerpc/aim/mmu_oea64.c (revision 13de33a5dc2304b13d595d75d48c51793958474f)
1 /*-
2  * Copyright (c) 2001 The NetBSD Foundation, Inc.
3  * All rights reserved.
4  *
5  * This code is derived from software contributed to The NetBSD Foundation
6  * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *        This product includes software developed by the NetBSD
19  *        Foundation, Inc. and its contributors.
20  * 4. Neither the name of The NetBSD Foundation nor the names of its
21  *    contributors may be used to endorse or promote products derived
22  *    from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  * POSSIBILITY OF SUCH DAMAGE.
35  */
36 /*-
37  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38  * Copyright (C) 1995, 1996 TooLs GmbH.
39  * All rights reserved.
40  *
41  * Redistribution and use in source and binary forms, with or without
42  * modification, are permitted provided that the following conditions
43  * are met:
44  * 1. Redistributions of source code must retain the above copyright
45  *    notice, this list of conditions and the following disclaimer.
46  * 2. Redistributions in binary form must reproduce the above copyright
47  *    notice, this list of conditions and the following disclaimer in the
48  *    documentation and/or other materials provided with the distribution.
49  * 3. All advertising materials mentioning features or use of this software
50  *    must display the following acknowledgement:
51  *	This product includes software developed by TooLs GmbH.
52  * 4. The name of TooLs GmbH may not be used to endorse or promote products
53  *    derived from this software without specific prior written permission.
54  *
55  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65  *
66  * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
67  */
68 /*-
69  * Copyright (C) 2001 Benno Rice.
70  * All rights reserved.
71  *
72  * Redistribution and use in source and binary forms, with or without
73  * modification, are permitted provided that the following conditions
74  * are met:
75  * 1. Redistributions of source code must retain the above copyright
76  *    notice, this list of conditions and the following disclaimer.
77  * 2. Redistributions in binary form must reproduce the above copyright
78  *    notice, this list of conditions and the following disclaimer in the
79  *    documentation and/or other materials provided with the distribution.
80  *
81  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
91  */
92 
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
95 
96 /*
97  * Manages physical address maps.
98  *
99  * Since the information managed by this module is also stored by the
100  * logical address mapping module, this module may throw away valid virtual
101  * to physical mappings at almost any time.  However, invalidations of
102  * mappings must be done as requested.
103  *
104  * In order to cope with hardware architectures which make virtual to
105  * physical map invalidates expensive, this module may delay invalidate
106  * reduced protection operations until such time as they are actually
107  * necessary.  This module is given full information as to which processors
108  * are currently using which maps, and to when physical maps must be made
109  * correct.
110  */
111 
112 #include "opt_compat.h"
113 #include "opt_kstack_pages.h"
114 
115 #include <sys/param.h>
116 #include <sys/kernel.h>
117 #include <sys/queue.h>
118 #include <sys/cpuset.h>
119 #include <sys/ktr.h>
120 #include <sys/lock.h>
121 #include <sys/msgbuf.h>
122 #include <sys/malloc.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rwlock.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/systm.h>
129 #include <sys/vmmeter.h>
130 
131 #include <sys/kdb.h>
132 
133 #include <dev/ofw/openfirm.h>
134 
135 #include <vm/vm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
143 #include <vm/uma.h>
144 
145 #include <machine/_inttypes.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/frame.h>
149 #include <machine/md_var.h>
150 #include <machine/psl.h>
151 #include <machine/bat.h>
152 #include <machine/hid.h>
153 #include <machine/pte.h>
154 #include <machine/sr.h>
155 #include <machine/trap.h>
156 #include <machine/mmuvar.h>
157 
158 #include "mmu_oea64.h"
159 #include "mmu_if.h"
160 #include "moea64_if.h"
161 
162 void moea64_release_vsid(uint64_t vsid);
163 uintptr_t moea64_get_unique_vsid(void);
164 
165 #define DISABLE_TRANS(msr)	msr = mfmsr(); mtmsr(msr & ~PSL_DR)
166 #define ENABLE_TRANS(msr)	mtmsr(msr)
167 
168 #define	VSID_MAKE(sr, hash)	((sr) | (((hash) & 0xfffff) << 4))
169 #define	VSID_TO_HASH(vsid)	(((vsid) >> 4) & 0xfffff)
170 #define	VSID_HASH_MASK		0x0000007fffffffffULL
171 
172 /*
173  * Locking semantics:
174  * -- Read lock: if no modifications are being made to either the PVO lists
175  *    or page table or if any modifications being made result in internal
176  *    changes (e.g. wiring, protection) such that the existence of the PVOs
177  *    is unchanged and they remain associated with the same pmap (in which
178  *    case the changes should be protected by the pmap lock)
179  * -- Write lock: required if PTEs/PVOs are being inserted or removed.
180  */
181 
182 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
183 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
184 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
185 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
186 
187 struct ofw_map {
188 	cell_t	om_va;
189 	cell_t	om_len;
190 	uint64_t om_pa;
191 	cell_t	om_mode;
192 };
193 
194 extern unsigned char _etext[];
195 extern unsigned char _end[];
196 
197 extern int dumpsys_minidump;
198 
199 /*
200  * Map of physical memory regions.
201  */
202 static struct	mem_region *regions;
203 static struct	mem_region *pregions;
204 static u_int	phys_avail_count;
205 static int	regions_sz, pregions_sz;
206 
207 extern void bs_remap_earlyboot(void);
208 
209 /*
210  * Lock for the pteg and pvo tables.
211  */
212 struct rwlock	moea64_table_lock;
213 struct mtx	moea64_slb_mutex;
214 
215 /*
216  * PTEG data.
217  */
218 u_int		moea64_pteg_count;
219 u_int		moea64_pteg_mask;
220 
221 /*
222  * PVO data.
223  */
224 struct	pvo_head *moea64_pvo_table;		/* pvo entries by pteg index */
225 
226 uma_zone_t	moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
227 uma_zone_t	moea64_mpvo_zone; /* zone for pvo entries for managed pages */
228 
229 #define	BPVO_POOL_SIZE	327680
230 static struct	pvo_entry *moea64_bpvo_pool;
231 static int	moea64_bpvo_pool_index = 0;
232 
233 #define	VSID_NBPW	(sizeof(u_int32_t) * 8)
234 #ifdef __powerpc64__
235 #define	NVSIDS		(NPMAPS * 16)
236 #define VSID_HASHMASK	0xffffffffUL
237 #else
238 #define NVSIDS		NPMAPS
239 #define VSID_HASHMASK	0xfffffUL
240 #endif
241 static u_int	moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
242 
243 static boolean_t moea64_initialized = FALSE;
244 
245 /*
246  * Statistics.
247  */
248 u_int	moea64_pte_valid = 0;
249 u_int	moea64_pte_overflow = 0;
250 u_int	moea64_pvo_entries = 0;
251 u_int	moea64_pvo_enter_calls = 0;
252 u_int	moea64_pvo_remove_calls = 0;
253 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
254     &moea64_pte_valid, 0, "");
255 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
256     &moea64_pte_overflow, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
258     &moea64_pvo_entries, 0, "");
259 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
260     &moea64_pvo_enter_calls, 0, "");
261 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
262     &moea64_pvo_remove_calls, 0, "");
263 
264 vm_offset_t	moea64_scratchpage_va[2];
265 struct pvo_entry *moea64_scratchpage_pvo[2];
266 uintptr_t	moea64_scratchpage_pte[2];
267 struct	mtx	moea64_scratchpage_mtx;
268 
269 uint64_t 	moea64_large_page_mask = 0;
270 uint64_t	moea64_large_page_size = 0;
271 int		moea64_large_page_shift = 0;
272 
273 /*
274  * PVO calls.
275  */
276 static int	moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
277 		    vm_offset_t, vm_offset_t, uint64_t, int);
278 static void	moea64_pvo_remove(mmu_t, struct pvo_entry *);
279 static struct	pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
280 
281 /*
282  * Utility routines.
283  */
284 static boolean_t	moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
285 static u_int		moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
286 static void		moea64_kremove(mmu_t, vm_offset_t);
287 static void		moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
288 			    vm_offset_t pa, vm_size_t sz);
289 
290 /*
291  * Kernel MMU interface
292  */
293 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
294 void moea64_clear_modify(mmu_t, vm_page_t);
295 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
296 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
297     vm_page_t *mb, vm_offset_t b_offset, int xfersize);
298 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
299 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
300     vm_prot_t);
301 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
302 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
303 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
304 void moea64_init(mmu_t);
305 boolean_t moea64_is_modified(mmu_t, vm_page_t);
306 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
307 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
308 int moea64_ts_referenced(mmu_t, vm_page_t);
309 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
310 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
311 int moea64_page_wired_mappings(mmu_t, vm_page_t);
312 void moea64_pinit(mmu_t, pmap_t);
313 void moea64_pinit0(mmu_t, pmap_t);
314 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
315 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
316 void moea64_qremove(mmu_t, vm_offset_t, int);
317 void moea64_release(mmu_t, pmap_t);
318 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
319 void moea64_remove_pages(mmu_t, pmap_t);
320 void moea64_remove_all(mmu_t, vm_page_t);
321 void moea64_remove_write(mmu_t, vm_page_t);
322 void moea64_zero_page(mmu_t, vm_page_t);
323 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
324 void moea64_zero_page_idle(mmu_t, vm_page_t);
325 void moea64_activate(mmu_t, struct thread *);
326 void moea64_deactivate(mmu_t, struct thread *);
327 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
328 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
329 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
330 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
331 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
332 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
333 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
334 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
335 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
336 vm_offset_t moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
337     vm_size_t *sz);
338 struct pmap_md * moea64_scan_md(mmu_t mmu, struct pmap_md *prev);
339 
340 static mmu_method_t moea64_methods[] = {
341 	MMUMETHOD(mmu_change_wiring,	moea64_change_wiring),
342 	MMUMETHOD(mmu_clear_modify,	moea64_clear_modify),
343 	MMUMETHOD(mmu_copy_page,	moea64_copy_page),
344 	MMUMETHOD(mmu_copy_pages,	moea64_copy_pages),
345 	MMUMETHOD(mmu_enter,		moea64_enter),
346 	MMUMETHOD(mmu_enter_object,	moea64_enter_object),
347 	MMUMETHOD(mmu_enter_quick,	moea64_enter_quick),
348 	MMUMETHOD(mmu_extract,		moea64_extract),
349 	MMUMETHOD(mmu_extract_and_hold,	moea64_extract_and_hold),
350 	MMUMETHOD(mmu_init,		moea64_init),
351 	MMUMETHOD(mmu_is_modified,	moea64_is_modified),
352 	MMUMETHOD(mmu_is_prefaultable,	moea64_is_prefaultable),
353 	MMUMETHOD(mmu_is_referenced,	moea64_is_referenced),
354 	MMUMETHOD(mmu_ts_referenced,	moea64_ts_referenced),
355 	MMUMETHOD(mmu_map,     		moea64_map),
356 	MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
357 	MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
358 	MMUMETHOD(mmu_pinit,		moea64_pinit),
359 	MMUMETHOD(mmu_pinit0,		moea64_pinit0),
360 	MMUMETHOD(mmu_protect,		moea64_protect),
361 	MMUMETHOD(mmu_qenter,		moea64_qenter),
362 	MMUMETHOD(mmu_qremove,		moea64_qremove),
363 	MMUMETHOD(mmu_release,		moea64_release),
364 	MMUMETHOD(mmu_remove,		moea64_remove),
365 	MMUMETHOD(mmu_remove_pages,	moea64_remove_pages),
366 	MMUMETHOD(mmu_remove_all,      	moea64_remove_all),
367 	MMUMETHOD(mmu_remove_write,	moea64_remove_write),
368 	MMUMETHOD(mmu_sync_icache,	moea64_sync_icache),
369 	MMUMETHOD(mmu_zero_page,       	moea64_zero_page),
370 	MMUMETHOD(mmu_zero_page_area,	moea64_zero_page_area),
371 	MMUMETHOD(mmu_zero_page_idle,	moea64_zero_page_idle),
372 	MMUMETHOD(mmu_activate,		moea64_activate),
373 	MMUMETHOD(mmu_deactivate,      	moea64_deactivate),
374 	MMUMETHOD(mmu_page_set_memattr,	moea64_page_set_memattr),
375 
376 	/* Internal interfaces */
377 	MMUMETHOD(mmu_mapdev,		moea64_mapdev),
378 	MMUMETHOD(mmu_mapdev_attr,	moea64_mapdev_attr),
379 	MMUMETHOD(mmu_unmapdev,		moea64_unmapdev),
380 	MMUMETHOD(mmu_kextract,		moea64_kextract),
381 	MMUMETHOD(mmu_kenter,		moea64_kenter),
382 	MMUMETHOD(mmu_kenter_attr,	moea64_kenter_attr),
383 	MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
384 	MMUMETHOD(mmu_scan_md,		moea64_scan_md),
385 	MMUMETHOD(mmu_dumpsys_map,	moea64_dumpsys_map),
386 
387 	{ 0, 0 }
388 };
389 
390 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
391 
392 static __inline u_int
393 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
394 {
395 	uint64_t hash;
396 	int shift;
397 
398 	shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
399 	hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
400 	    shift);
401 	return (hash & moea64_pteg_mask);
402 }
403 
404 static __inline struct pvo_head *
405 vm_page_to_pvoh(vm_page_t m)
406 {
407 
408 	return (&m->md.mdpg_pvoh);
409 }
410 
411 static __inline void
412 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
413     uint64_t pte_lo, int flags)
414 {
415 
416 	/*
417 	 * Construct a PTE.  Default to IMB initially.  Valid bit only gets
418 	 * set when the real pte is set in memory.
419 	 *
420 	 * Note: Don't set the valid bit for correct operation of tlb update.
421 	 */
422 	pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
423 	    (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
424 
425 	if (flags & PVO_LARGE)
426 		pt->pte_hi |= LPTE_BIG;
427 
428 	pt->pte_lo = pte_lo;
429 }
430 
431 static __inline uint64_t
432 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
433 {
434 	uint64_t pte_lo;
435 	int i;
436 
437 	if (ma != VM_MEMATTR_DEFAULT) {
438 		switch (ma) {
439 		case VM_MEMATTR_UNCACHEABLE:
440 			return (LPTE_I | LPTE_G);
441 		case VM_MEMATTR_WRITE_COMBINING:
442 		case VM_MEMATTR_WRITE_BACK:
443 		case VM_MEMATTR_PREFETCHABLE:
444 			return (LPTE_I);
445 		case VM_MEMATTR_WRITE_THROUGH:
446 			return (LPTE_W | LPTE_M);
447 		}
448 	}
449 
450 	/*
451 	 * Assume the page is cache inhibited and access is guarded unless
452 	 * it's in our available memory array.
453 	 */
454 	pte_lo = LPTE_I | LPTE_G;
455 	for (i = 0; i < pregions_sz; i++) {
456 		if ((pa >= pregions[i].mr_start) &&
457 		    (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
458 			pte_lo &= ~(LPTE_I | LPTE_G);
459 			pte_lo |= LPTE_M;
460 			break;
461 		}
462 	}
463 
464 	return pte_lo;
465 }
466 
467 /*
468  * Quick sort callout for comparing memory regions.
469  */
470 static int	om_cmp(const void *a, const void *b);
471 
472 static int
473 om_cmp(const void *a, const void *b)
474 {
475 	const struct	ofw_map *mapa;
476 	const struct	ofw_map *mapb;
477 
478 	mapa = a;
479 	mapb = b;
480 	if (mapa->om_pa < mapb->om_pa)
481 		return (-1);
482 	else if (mapa->om_pa > mapb->om_pa)
483 		return (1);
484 	else
485 		return (0);
486 }
487 
488 static void
489 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
490 {
491 	struct ofw_map	translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
492 	pcell_t		acells, trans_cells[sz/sizeof(cell_t)];
493 	register_t	msr;
494 	vm_offset_t	off;
495 	vm_paddr_t	pa_base;
496 	int		i, j;
497 
498 	bzero(translations, sz);
499 	OF_getprop(OF_finddevice("/"), "#address-cells", &acells,
500 	    sizeof(acells));
501 	if (OF_getprop(mmu, "translations", trans_cells, sz) == -1)
502 		panic("moea64_bootstrap: can't get ofw translations");
503 
504 	CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
505 	sz /= sizeof(cell_t);
506 	for (i = 0, j = 0; i < sz; j++) {
507 		translations[j].om_va = trans_cells[i++];
508 		translations[j].om_len = trans_cells[i++];
509 		translations[j].om_pa = trans_cells[i++];
510 		if (acells == 2) {
511 			translations[j].om_pa <<= 32;
512 			translations[j].om_pa |= trans_cells[i++];
513 		}
514 		translations[j].om_mode = trans_cells[i++];
515 	}
516 	KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
517 	    i, sz));
518 
519 	sz = j;
520 	qsort(translations, sz, sizeof (*translations), om_cmp);
521 
522 	for (i = 0; i < sz; i++) {
523 		pa_base = translations[i].om_pa;
524 	      #ifndef __powerpc64__
525 		if ((translations[i].om_pa >> 32) != 0)
526 			panic("OFW translations above 32-bit boundary!");
527 	      #endif
528 
529 		if (pa_base % PAGE_SIZE)
530 			panic("OFW translation not page-aligned (phys)!");
531 		if (translations[i].om_va % PAGE_SIZE)
532 			panic("OFW translation not page-aligned (virt)!");
533 
534 		CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
535 		    pa_base, translations[i].om_va, translations[i].om_len);
536 
537 		/* Now enter the pages for this mapping */
538 
539 		DISABLE_TRANS(msr);
540 		for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
541 			if (moea64_pvo_find_va(kernel_pmap,
542 			    translations[i].om_va + off) != NULL)
543 				continue;
544 
545 			moea64_kenter(mmup, translations[i].om_va + off,
546 			    pa_base + off);
547 		}
548 		ENABLE_TRANS(msr);
549 	}
550 }
551 
552 #ifdef __powerpc64__
553 static void
554 moea64_probe_large_page(void)
555 {
556 	uint16_t pvr = mfpvr() >> 16;
557 
558 	switch (pvr) {
559 	case IBM970:
560 	case IBM970FX:
561 	case IBM970MP:
562 		powerpc_sync(); isync();
563 		mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
564 		powerpc_sync(); isync();
565 
566 		/* FALLTHROUGH */
567 	default:
568 		moea64_large_page_size = 0x1000000; /* 16 MB */
569 		moea64_large_page_shift = 24;
570 	}
571 
572 	moea64_large_page_mask = moea64_large_page_size - 1;
573 }
574 
575 static void
576 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
577 {
578 	struct slb *cache;
579 	struct slb entry;
580 	uint64_t esid, slbe;
581 	uint64_t i;
582 
583 	cache = PCPU_GET(slb);
584 	esid = va >> ADDR_SR_SHFT;
585 	slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
586 
587 	for (i = 0; i < 64; i++) {
588 		if (cache[i].slbe == (slbe | i))
589 			return;
590 	}
591 
592 	entry.slbe = slbe;
593 	entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
594 	if (large)
595 		entry.slbv |= SLBV_L;
596 
597 	slb_insert_kernel(entry.slbe, entry.slbv);
598 }
599 #endif
600 
601 static void
602 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
603     vm_offset_t kernelend)
604 {
605 	register_t msr;
606 	vm_paddr_t pa;
607 	vm_offset_t size, off;
608 	uint64_t pte_lo;
609 	int i;
610 
611 	if (moea64_large_page_size == 0)
612 		hw_direct_map = 0;
613 
614 	DISABLE_TRANS(msr);
615 	if (hw_direct_map) {
616 		LOCK_TABLE_WR();
617 		PMAP_LOCK(kernel_pmap);
618 		for (i = 0; i < pregions_sz; i++) {
619 		  for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
620 		     pregions[i].mr_size; pa += moea64_large_page_size) {
621 			pte_lo = LPTE_M;
622 
623 			/*
624 			 * Set memory access as guarded if prefetch within
625 			 * the page could exit the available physmem area.
626 			 */
627 			if (pa & moea64_large_page_mask) {
628 				pa &= moea64_large_page_mask;
629 				pte_lo |= LPTE_G;
630 			}
631 			if (pa + moea64_large_page_size >
632 			    pregions[i].mr_start + pregions[i].mr_size)
633 				pte_lo |= LPTE_G;
634 
635 			moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
636 				    NULL, pa, pa, pte_lo,
637 				    PVO_WIRED | PVO_LARGE);
638 		  }
639 		}
640 		PMAP_UNLOCK(kernel_pmap);
641 		UNLOCK_TABLE_WR();
642 	} else {
643 		size = sizeof(struct pvo_head) * moea64_pteg_count;
644 		off = (vm_offset_t)(moea64_pvo_table);
645 		for (pa = off; pa < off + size; pa += PAGE_SIZE)
646 			moea64_kenter(mmup, pa, pa);
647 		size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
648 		off = (vm_offset_t)(moea64_bpvo_pool);
649 		for (pa = off; pa < off + size; pa += PAGE_SIZE)
650 		moea64_kenter(mmup, pa, pa);
651 
652 		/*
653 		 * Map certain important things, like ourselves.
654 		 *
655 		 * NOTE: We do not map the exception vector space. That code is
656 		 * used only in real mode, and leaving it unmapped allows us to
657 		 * catch NULL pointer deferences, instead of making NULL a valid
658 		 * address.
659 		 */
660 
661 		for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
662 		    pa += PAGE_SIZE)
663 			moea64_kenter(mmup, pa, pa);
664 	}
665 	ENABLE_TRANS(msr);
666 
667 	/*
668 	 * Allow user to override unmapped_buf_allowed for testing.
669 	 * XXXKIB Only direct map implementation was tested.
670 	 */
671 	if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
672 	    &unmapped_buf_allowed))
673 		unmapped_buf_allowed = hw_direct_map;
674 }
675 
676 void
677 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
678 {
679 	int		i, j;
680 	vm_size_t	physsz, hwphyssz;
681 
682 #ifndef __powerpc64__
683 	/* We don't have a direct map since there is no BAT */
684 	hw_direct_map = 0;
685 
686 	/* Make sure battable is zero, since we have no BAT */
687 	for (i = 0; i < 16; i++) {
688 		battable[i].batu = 0;
689 		battable[i].batl = 0;
690 	}
691 #else
692 	moea64_probe_large_page();
693 
694 	/* Use a direct map if we have large page support */
695 	if (moea64_large_page_size > 0)
696 		hw_direct_map = 1;
697 	else
698 		hw_direct_map = 0;
699 #endif
700 
701 	/* Get physical memory regions from firmware */
702 	mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
703 	CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
704 
705 	if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
706 		panic("moea64_bootstrap: phys_avail too small");
707 
708 	phys_avail_count = 0;
709 	physsz = 0;
710 	hwphyssz = 0;
711 	TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
712 	for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
713 		CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
714 		    regions[i].mr_start, regions[i].mr_start +
715 		    regions[i].mr_size, regions[i].mr_size);
716 		if (hwphyssz != 0 &&
717 		    (physsz + regions[i].mr_size) >= hwphyssz) {
718 			if (physsz < hwphyssz) {
719 				phys_avail[j] = regions[i].mr_start;
720 				phys_avail[j + 1] = regions[i].mr_start +
721 				    hwphyssz - physsz;
722 				physsz = hwphyssz;
723 				phys_avail_count++;
724 			}
725 			break;
726 		}
727 		phys_avail[j] = regions[i].mr_start;
728 		phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
729 		phys_avail_count++;
730 		physsz += regions[i].mr_size;
731 	}
732 
733 	/* Check for overlap with the kernel and exception vectors */
734 	for (j = 0; j < 2*phys_avail_count; j+=2) {
735 		if (phys_avail[j] < EXC_LAST)
736 			phys_avail[j] += EXC_LAST;
737 
738 		if (kernelstart >= phys_avail[j] &&
739 		    kernelstart < phys_avail[j+1]) {
740 			if (kernelend < phys_avail[j+1]) {
741 				phys_avail[2*phys_avail_count] =
742 				    (kernelend & ~PAGE_MASK) + PAGE_SIZE;
743 				phys_avail[2*phys_avail_count + 1] =
744 				    phys_avail[j+1];
745 				phys_avail_count++;
746 			}
747 
748 			phys_avail[j+1] = kernelstart & ~PAGE_MASK;
749 		}
750 
751 		if (kernelend >= phys_avail[j] &&
752 		    kernelend < phys_avail[j+1]) {
753 			if (kernelstart > phys_avail[j]) {
754 				phys_avail[2*phys_avail_count] = phys_avail[j];
755 				phys_avail[2*phys_avail_count + 1] =
756 				    kernelstart & ~PAGE_MASK;
757 				phys_avail_count++;
758 			}
759 
760 			phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
761 		}
762 	}
763 
764 	physmem = btoc(physsz);
765 
766 #ifdef PTEGCOUNT
767 	moea64_pteg_count = PTEGCOUNT;
768 #else
769 	moea64_pteg_count = 0x1000;
770 
771 	while (moea64_pteg_count < physmem)
772 		moea64_pteg_count <<= 1;
773 
774 	moea64_pteg_count >>= 1;
775 #endif /* PTEGCOUNT */
776 }
777 
778 void
779 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
780 {
781 	vm_size_t	size;
782 	register_t	msr;
783 	int		i;
784 
785 	/*
786 	 * Set PTEG mask
787 	 */
788 	moea64_pteg_mask = moea64_pteg_count - 1;
789 
790 	/*
791 	 * Allocate pv/overflow lists.
792 	 */
793 	size = sizeof(struct pvo_head) * moea64_pteg_count;
794 
795 	moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
796 	    PAGE_SIZE);
797 	CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
798 
799 	DISABLE_TRANS(msr);
800 	for (i = 0; i < moea64_pteg_count; i++)
801 		LIST_INIT(&moea64_pvo_table[i]);
802 	ENABLE_TRANS(msr);
803 
804 	/*
805 	 * Initialize the lock that synchronizes access to the pteg and pvo
806 	 * tables.
807 	 */
808 	rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
809 	mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
810 
811 	/*
812 	 * Initialise the unmanaged pvo pool.
813 	 */
814 	moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
815 		BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
816 	moea64_bpvo_pool_index = 0;
817 
818 	/*
819 	 * Make sure kernel vsid is allocated as well as VSID 0.
820 	 */
821 	#ifndef __powerpc64__
822 	moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
823 		|= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
824 	moea64_vsid_bitmap[0] |= 1;
825 	#endif
826 
827 	/*
828 	 * Initialize the kernel pmap (which is statically allocated).
829 	 */
830 	#ifdef __powerpc64__
831 	for (i = 0; i < 64; i++) {
832 		pcpup->pc_slb[i].slbv = 0;
833 		pcpup->pc_slb[i].slbe = 0;
834 	}
835 	#else
836 	for (i = 0; i < 16; i++)
837 		kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
838 	#endif
839 
840 	kernel_pmap->pmap_phys = kernel_pmap;
841 	CPU_FILL(&kernel_pmap->pm_active);
842 	RB_INIT(&kernel_pmap->pmap_pvo);
843 
844 	PMAP_LOCK_INIT(kernel_pmap);
845 
846 	/*
847 	 * Now map in all the other buffers we allocated earlier
848 	 */
849 
850 	moea64_setup_direct_map(mmup, kernelstart, kernelend);
851 }
852 
853 void
854 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
855 {
856 	ihandle_t	mmui;
857 	phandle_t	chosen;
858 	phandle_t	mmu;
859 	size_t		sz;
860 	int		i;
861 	vm_offset_t	pa, va;
862 	void		*dpcpu;
863 
864 	/*
865 	 * Set up the Open Firmware pmap and add its mappings if not in real
866 	 * mode.
867 	 */
868 
869 	chosen = OF_finddevice("/chosen");
870 	if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
871 	    mmu = OF_instance_to_package(mmui);
872 	    if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
873 		sz = 0;
874 	    if (sz > 6144 /* tmpstksz - 2 KB headroom */)
875 		panic("moea64_bootstrap: too many ofw translations");
876 
877 	    if (sz > 0)
878 		moea64_add_ofw_mappings(mmup, mmu, sz);
879 	}
880 
881 	/*
882 	 * Calculate the last available physical address.
883 	 */
884 	for (i = 0; phys_avail[i + 2] != 0; i += 2)
885 		;
886 	Maxmem = powerpc_btop(phys_avail[i + 1]);
887 
888 	/*
889 	 * Initialize MMU and remap early physical mappings
890 	 */
891 	MMU_CPU_BOOTSTRAP(mmup,0);
892 	mtmsr(mfmsr() | PSL_DR | PSL_IR);
893 	pmap_bootstrapped++;
894 	bs_remap_earlyboot();
895 
896 	/*
897 	 * Set the start and end of kva.
898 	 */
899 	virtual_avail = VM_MIN_KERNEL_ADDRESS;
900 	virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
901 
902 	/*
903 	 * Map the entire KVA range into the SLB. We must not fault there.
904 	 */
905 	#ifdef __powerpc64__
906 	for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
907 		moea64_bootstrap_slb_prefault(va, 0);
908 	#endif
909 
910 	/*
911 	 * Figure out how far we can extend virtual_end into segment 16
912 	 * without running into existing mappings. Segment 16 is guaranteed
913 	 * to contain neither RAM nor devices (at least on Apple hardware),
914 	 * but will generally contain some OFW mappings we should not
915 	 * step on.
916 	 */
917 
918 	#ifndef __powerpc64__	/* KVA is in high memory on PPC64 */
919 	PMAP_LOCK(kernel_pmap);
920 	while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
921 	    moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
922 		virtual_end += PAGE_SIZE;
923 	PMAP_UNLOCK(kernel_pmap);
924 	#endif
925 
926 	/*
927 	 * Allocate a kernel stack with a guard page for thread0 and map it
928 	 * into the kernel page map.
929 	 */
930 	pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
931 	va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
932 	virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
933 	CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
934 	thread0.td_kstack = va;
935 	thread0.td_kstack_pages = KSTACK_PAGES;
936 	for (i = 0; i < KSTACK_PAGES; i++) {
937 		moea64_kenter(mmup, va, pa);
938 		pa += PAGE_SIZE;
939 		va += PAGE_SIZE;
940 	}
941 
942 	/*
943 	 * Allocate virtual address space for the message buffer.
944 	 */
945 	pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
946 	msgbufp = (struct msgbuf *)virtual_avail;
947 	va = virtual_avail;
948 	virtual_avail += round_page(msgbufsize);
949 	while (va < virtual_avail) {
950 		moea64_kenter(mmup, va, pa);
951 		pa += PAGE_SIZE;
952 		va += PAGE_SIZE;
953 	}
954 
955 	/*
956 	 * Allocate virtual address space for the dynamic percpu area.
957 	 */
958 	pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
959 	dpcpu = (void *)virtual_avail;
960 	va = virtual_avail;
961 	virtual_avail += DPCPU_SIZE;
962 	while (va < virtual_avail) {
963 		moea64_kenter(mmup, va, pa);
964 		pa += PAGE_SIZE;
965 		va += PAGE_SIZE;
966 	}
967 	dpcpu_init(dpcpu, 0);
968 
969 	/*
970 	 * Allocate some things for page zeroing. We put this directly
971 	 * in the page table, marked with LPTE_LOCKED, to avoid any
972 	 * of the PVO book-keeping or other parts of the VM system
973 	 * from even knowing that this hack exists.
974 	 */
975 
976 	if (!hw_direct_map) {
977 		mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
978 		    MTX_DEF);
979 		for (i = 0; i < 2; i++) {
980 			moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
981 			virtual_end -= PAGE_SIZE;
982 
983 			moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
984 
985 			moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
986 			    kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
987 			LOCK_TABLE_RD();
988 			moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
989 			    mmup, moea64_scratchpage_pvo[i]);
990 			moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
991 			    |= LPTE_LOCKED;
992 			MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
993 			    &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
994 			    moea64_scratchpage_pvo[i]->pvo_vpn);
995 			UNLOCK_TABLE_RD();
996 		}
997 	}
998 }
999 
1000 /*
1001  * Activate a user pmap.  The pmap must be activated before its address
1002  * space can be accessed in any way.
1003  */
1004 void
1005 moea64_activate(mmu_t mmu, struct thread *td)
1006 {
1007 	pmap_t	pm;
1008 
1009 	pm = &td->td_proc->p_vmspace->vm_pmap;
1010 	CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1011 
1012 	#ifdef __powerpc64__
1013 	PCPU_SET(userslb, pm->pm_slb);
1014 	#else
1015 	PCPU_SET(curpmap, pm->pmap_phys);
1016 	#endif
1017 }
1018 
1019 void
1020 moea64_deactivate(mmu_t mmu, struct thread *td)
1021 {
1022 	pmap_t	pm;
1023 
1024 	pm = &td->td_proc->p_vmspace->vm_pmap;
1025 	CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1026 	#ifdef __powerpc64__
1027 	PCPU_SET(userslb, NULL);
1028 	#else
1029 	PCPU_SET(curpmap, NULL);
1030 	#endif
1031 }
1032 
1033 void
1034 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1035 {
1036 	struct	pvo_entry *pvo;
1037 	uintptr_t pt;
1038 	uint64_t vsid;
1039 	int	i, ptegidx;
1040 
1041 	LOCK_TABLE_WR();
1042 	PMAP_LOCK(pm);
1043 	pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1044 
1045 	if (pvo != NULL) {
1046 		pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1047 
1048 		if (wired) {
1049 			if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1050 				pm->pm_stats.wired_count++;
1051 			pvo->pvo_vaddr |= PVO_WIRED;
1052 			pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1053 		} else {
1054 			if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1055 				pm->pm_stats.wired_count--;
1056 			pvo->pvo_vaddr &= ~PVO_WIRED;
1057 			pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1058 		}
1059 
1060 		if (pt != -1) {
1061 			/* Update wiring flag in page table. */
1062 			MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1063 			    pvo->pvo_vpn);
1064 		} else if (wired) {
1065 			/*
1066 			 * If we are wiring the page, and it wasn't in the
1067 			 * page table before, add it.
1068 			 */
1069 			vsid = PVO_VSID(pvo);
1070 			ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1071 			    pvo->pvo_vaddr & PVO_LARGE);
1072 
1073 			i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1074 
1075 			if (i >= 0) {
1076 				PVO_PTEGIDX_CLR(pvo);
1077 				PVO_PTEGIDX_SET(pvo, i);
1078 			}
1079 		}
1080 
1081 	}
1082 	UNLOCK_TABLE_WR();
1083 	PMAP_UNLOCK(pm);
1084 }
1085 
1086 /*
1087  * This goes through and sets the physical address of our
1088  * special scratch PTE to the PA we want to zero or copy. Because
1089  * of locking issues (this can get called in pvo_enter() by
1090  * the UMA allocator), we can't use most other utility functions here
1091  */
1092 
1093 static __inline
1094 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1095 
1096 	KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1097 	mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1098 
1099 	moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1100 	    ~(LPTE_WIMG | LPTE_RPGN);
1101 	moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1102 	    moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1103 	MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1104 	    &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1105 	    moea64_scratchpage_pvo[which]->pvo_vpn);
1106 	isync();
1107 }
1108 
1109 void
1110 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1111 {
1112 	vm_offset_t	dst;
1113 	vm_offset_t	src;
1114 
1115 	dst = VM_PAGE_TO_PHYS(mdst);
1116 	src = VM_PAGE_TO_PHYS(msrc);
1117 
1118 	if (hw_direct_map) {
1119 		bcopy((void *)src, (void *)dst, PAGE_SIZE);
1120 	} else {
1121 		mtx_lock(&moea64_scratchpage_mtx);
1122 
1123 		moea64_set_scratchpage_pa(mmu, 0, src);
1124 		moea64_set_scratchpage_pa(mmu, 1, dst);
1125 
1126 		bcopy((void *)moea64_scratchpage_va[0],
1127 		    (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1128 
1129 		mtx_unlock(&moea64_scratchpage_mtx);
1130 	}
1131 }
1132 
1133 static inline void
1134 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1135     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1136 {
1137 	void *a_cp, *b_cp;
1138 	vm_offset_t a_pg_offset, b_pg_offset;
1139 	int cnt;
1140 
1141 	while (xfersize > 0) {
1142 		a_pg_offset = a_offset & PAGE_MASK;
1143 		cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1144 		a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1145 		    a_pg_offset;
1146 		b_pg_offset = b_offset & PAGE_MASK;
1147 		cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1148 		b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1149 		    b_pg_offset;
1150 		bcopy(a_cp, b_cp, cnt);
1151 		a_offset += cnt;
1152 		b_offset += cnt;
1153 		xfersize -= cnt;
1154 	}
1155 }
1156 
1157 static inline void
1158 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1159     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1160 {
1161 	void *a_cp, *b_cp;
1162 	vm_offset_t a_pg_offset, b_pg_offset;
1163 	int cnt;
1164 
1165 	mtx_lock(&moea64_scratchpage_mtx);
1166 	while (xfersize > 0) {
1167 		a_pg_offset = a_offset & PAGE_MASK;
1168 		cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1169 		moea64_set_scratchpage_pa(mmu, 0,
1170 		    VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1171 		a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1172 		b_pg_offset = b_offset & PAGE_MASK;
1173 		cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1174 		moea64_set_scratchpage_pa(mmu, 1,
1175 		    VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1176 		b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1177 		bcopy(a_cp, b_cp, cnt);
1178 		a_offset += cnt;
1179 		b_offset += cnt;
1180 		xfersize -= cnt;
1181 	}
1182 	mtx_unlock(&moea64_scratchpage_mtx);
1183 }
1184 
1185 void
1186 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1187     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1188 {
1189 
1190 	if (hw_direct_map) {
1191 		moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1192 		    xfersize);
1193 	} else {
1194 		moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1195 		    xfersize);
1196 	}
1197 }
1198 
1199 void
1200 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1201 {
1202 	vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1203 
1204 	if (size + off > PAGE_SIZE)
1205 		panic("moea64_zero_page: size + off > PAGE_SIZE");
1206 
1207 	if (hw_direct_map) {
1208 		bzero((caddr_t)pa + off, size);
1209 	} else {
1210 		mtx_lock(&moea64_scratchpage_mtx);
1211 		moea64_set_scratchpage_pa(mmu, 0, pa);
1212 		bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1213 		mtx_unlock(&moea64_scratchpage_mtx);
1214 	}
1215 }
1216 
1217 /*
1218  * Zero a page of physical memory by temporarily mapping it
1219  */
1220 void
1221 moea64_zero_page(mmu_t mmu, vm_page_t m)
1222 {
1223 	vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1224 	vm_offset_t va, off;
1225 
1226 	if (!hw_direct_map) {
1227 		mtx_lock(&moea64_scratchpage_mtx);
1228 
1229 		moea64_set_scratchpage_pa(mmu, 0, pa);
1230 		va = moea64_scratchpage_va[0];
1231 	} else {
1232 		va = pa;
1233 	}
1234 
1235 	for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1236 		__asm __volatile("dcbz 0,%0" :: "r"(va + off));
1237 
1238 	if (!hw_direct_map)
1239 		mtx_unlock(&moea64_scratchpage_mtx);
1240 }
1241 
1242 void
1243 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1244 {
1245 
1246 	moea64_zero_page(mmu, m);
1247 }
1248 
1249 /*
1250  * Map the given physical page at the specified virtual address in the
1251  * target pmap with the protection requested.  If specified the page
1252  * will be wired down.
1253  */
1254 
1255 void
1256 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1257     vm_prot_t prot, boolean_t wired)
1258 {
1259 	struct		pvo_head *pvo_head;
1260 	uma_zone_t	zone;
1261 	vm_page_t	pg;
1262 	uint64_t	pte_lo;
1263 	u_int		pvo_flags;
1264 	int		error;
1265 
1266 	if (!moea64_initialized) {
1267 		pvo_head = NULL;
1268 		pg = NULL;
1269 		zone = moea64_upvo_zone;
1270 		pvo_flags = 0;
1271 	} else {
1272 		pvo_head = vm_page_to_pvoh(m);
1273 		pg = m;
1274 		zone = moea64_mpvo_zone;
1275 		pvo_flags = PVO_MANAGED;
1276 	}
1277 
1278 	if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1279 		VM_OBJECT_ASSERT_LOCKED(m->object);
1280 
1281 	/* XXX change the pvo head for fake pages */
1282 	if ((m->oflags & VPO_UNMANAGED) != 0) {
1283 		pvo_flags &= ~PVO_MANAGED;
1284 		pvo_head = NULL;
1285 		zone = moea64_upvo_zone;
1286 	}
1287 
1288 	pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1289 
1290 	if (prot & VM_PROT_WRITE) {
1291 		pte_lo |= LPTE_BW;
1292 		if (pmap_bootstrapped &&
1293 		    (m->oflags & VPO_UNMANAGED) == 0)
1294 			vm_page_aflag_set(m, PGA_WRITEABLE);
1295 	} else
1296 		pte_lo |= LPTE_BR;
1297 
1298 	if ((prot & VM_PROT_EXECUTE) == 0)
1299 		pte_lo |= LPTE_NOEXEC;
1300 
1301 	if (wired)
1302 		pvo_flags |= PVO_WIRED;
1303 
1304 	LOCK_TABLE_WR();
1305 	PMAP_LOCK(pmap);
1306 	error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1307 	    VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1308 	PMAP_UNLOCK(pmap);
1309 	UNLOCK_TABLE_WR();
1310 
1311 	/*
1312 	 * Flush the page from the instruction cache if this page is
1313 	 * mapped executable and cacheable.
1314 	 */
1315 	if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1316 	    (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1317 		vm_page_aflag_set(m, PGA_EXECUTABLE);
1318 		moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1319 	}
1320 }
1321 
1322 static void
1323 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1324     vm_size_t sz)
1325 {
1326 
1327 	/*
1328 	 * This is much trickier than on older systems because
1329 	 * we can't sync the icache on physical addresses directly
1330 	 * without a direct map. Instead we check a couple of cases
1331 	 * where the memory is already mapped in and, failing that,
1332 	 * use the same trick we use for page zeroing to create
1333 	 * a temporary mapping for this physical address.
1334 	 */
1335 
1336 	if (!pmap_bootstrapped) {
1337 		/*
1338 		 * If PMAP is not bootstrapped, we are likely to be
1339 		 * in real mode.
1340 		 */
1341 		__syncicache((void *)pa, sz);
1342 	} else if (pmap == kernel_pmap) {
1343 		__syncicache((void *)va, sz);
1344 	} else if (hw_direct_map) {
1345 		__syncicache((void *)pa, sz);
1346 	} else {
1347 		/* Use the scratch page to set up a temp mapping */
1348 
1349 		mtx_lock(&moea64_scratchpage_mtx);
1350 
1351 		moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1352 		__syncicache((void *)(moea64_scratchpage_va[1] +
1353 		    (va & ADDR_POFF)), sz);
1354 
1355 		mtx_unlock(&moea64_scratchpage_mtx);
1356 	}
1357 }
1358 
1359 /*
1360  * Maps a sequence of resident pages belonging to the same object.
1361  * The sequence begins with the given page m_start.  This page is
1362  * mapped at the given virtual address start.  Each subsequent page is
1363  * mapped at a virtual address that is offset from start by the same
1364  * amount as the page is offset from m_start within the object.  The
1365  * last page in the sequence is the page with the largest offset from
1366  * m_start that can be mapped at a virtual address less than the given
1367  * virtual address end.  Not every virtual page between start and end
1368  * is mapped; only those for which a resident page exists with the
1369  * corresponding offset from m_start are mapped.
1370  */
1371 void
1372 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1373     vm_page_t m_start, vm_prot_t prot)
1374 {
1375 	vm_page_t m;
1376 	vm_pindex_t diff, psize;
1377 
1378 	VM_OBJECT_ASSERT_LOCKED(m_start->object);
1379 
1380 	psize = atop(end - start);
1381 	m = m_start;
1382 	while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1383 		moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1384 		    (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1385 		m = TAILQ_NEXT(m, listq);
1386 	}
1387 }
1388 
1389 void
1390 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1391     vm_prot_t prot)
1392 {
1393 
1394 	moea64_enter(mmu, pm, va, m,
1395 	    prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1396 }
1397 
1398 vm_paddr_t
1399 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1400 {
1401 	struct	pvo_entry *pvo;
1402 	vm_paddr_t pa;
1403 
1404 	PMAP_LOCK(pm);
1405 	pvo = moea64_pvo_find_va(pm, va);
1406 	if (pvo == NULL)
1407 		pa = 0;
1408 	else
1409 		pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1410 		    (va - PVO_VADDR(pvo));
1411 	PMAP_UNLOCK(pm);
1412 	return (pa);
1413 }
1414 
1415 /*
1416  * Atomically extract and hold the physical page with the given
1417  * pmap and virtual address pair if that mapping permits the given
1418  * protection.
1419  */
1420 vm_page_t
1421 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1422 {
1423 	struct	pvo_entry *pvo;
1424 	vm_page_t m;
1425         vm_paddr_t pa;
1426 
1427 	m = NULL;
1428 	pa = 0;
1429 	PMAP_LOCK(pmap);
1430 retry:
1431 	pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1432 	if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1433 	    ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1434 	     (prot & VM_PROT_WRITE) == 0)) {
1435 		if (vm_page_pa_tryrelock(pmap,
1436 			pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1437 			goto retry;
1438 		m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1439 		vm_page_hold(m);
1440 	}
1441 	PA_UNLOCK_COND(pa);
1442 	PMAP_UNLOCK(pmap);
1443 	return (m);
1444 }
1445 
1446 static mmu_t installed_mmu;
1447 
1448 static void *
1449 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1450 {
1451 	/*
1452 	 * This entire routine is a horrible hack to avoid bothering kmem
1453 	 * for new KVA addresses. Because this can get called from inside
1454 	 * kmem allocation routines, calling kmem for a new address here
1455 	 * can lead to multiply locking non-recursive mutexes.
1456 	 */
1457         vm_offset_t va;
1458 
1459         vm_page_t m;
1460         int pflags, needed_lock;
1461 
1462 	*flags = UMA_SLAB_PRIV;
1463 	needed_lock = !PMAP_LOCKED(kernel_pmap);
1464 	pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
1465 
1466         for (;;) {
1467                 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
1468                 if (m == NULL) {
1469                         if (wait & M_NOWAIT)
1470                                 return (NULL);
1471                         VM_WAIT;
1472                 } else
1473                         break;
1474         }
1475 
1476 	va = VM_PAGE_TO_PHYS(m);
1477 
1478 	LOCK_TABLE_WR();
1479 	if (needed_lock)
1480 		PMAP_LOCK(kernel_pmap);
1481 
1482 	moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1483 	    NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP);
1484 
1485 	if (needed_lock)
1486 		PMAP_UNLOCK(kernel_pmap);
1487 	UNLOCK_TABLE_WR();
1488 
1489 	if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1490                 bzero((void *)va, PAGE_SIZE);
1491 
1492 	return (void *)va;
1493 }
1494 
1495 extern int elf32_nxstack;
1496 
1497 void
1498 moea64_init(mmu_t mmu)
1499 {
1500 
1501 	CTR0(KTR_PMAP, "moea64_init");
1502 
1503 	moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1504 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1505 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1506 	moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1507 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1508 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1509 
1510 	if (!hw_direct_map) {
1511 		installed_mmu = mmu;
1512 		uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1513 		uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1514 	}
1515 
1516 #ifdef COMPAT_FREEBSD32
1517 	elf32_nxstack = 1;
1518 #endif
1519 
1520 	moea64_initialized = TRUE;
1521 }
1522 
1523 boolean_t
1524 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1525 {
1526 
1527 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1528 	    ("moea64_is_referenced: page %p is not managed", m));
1529 	return (moea64_query_bit(mmu, m, PTE_REF));
1530 }
1531 
1532 boolean_t
1533 moea64_is_modified(mmu_t mmu, vm_page_t m)
1534 {
1535 
1536 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1537 	    ("moea64_is_modified: page %p is not managed", m));
1538 
1539 	/*
1540 	 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1541 	 * concurrently set while the object is locked.  Thus, if PGA_WRITEABLE
1542 	 * is clear, no PTEs can have LPTE_CHG set.
1543 	 */
1544 	VM_OBJECT_ASSERT_LOCKED(m->object);
1545 	if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1546 		return (FALSE);
1547 	return (moea64_query_bit(mmu, m, LPTE_CHG));
1548 }
1549 
1550 boolean_t
1551 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1552 {
1553 	struct pvo_entry *pvo;
1554 	boolean_t rv;
1555 
1556 	PMAP_LOCK(pmap);
1557 	pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1558 	rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1559 	PMAP_UNLOCK(pmap);
1560 	return (rv);
1561 }
1562 
1563 void
1564 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1565 {
1566 
1567 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1568 	    ("moea64_clear_modify: page %p is not managed", m));
1569 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1570 	KASSERT(!vm_page_xbusied(m),
1571 	    ("moea64_clear_modify: page %p is exclusive busied", m));
1572 
1573 	/*
1574 	 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1575 	 * set.  If the object containing the page is locked and the page is
1576 	 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1577 	 */
1578 	if ((m->aflags & PGA_WRITEABLE) == 0)
1579 		return;
1580 	moea64_clear_bit(mmu, m, LPTE_CHG);
1581 }
1582 
1583 /*
1584  * Clear the write and modified bits in each of the given page's mappings.
1585  */
1586 void
1587 moea64_remove_write(mmu_t mmu, vm_page_t m)
1588 {
1589 	struct	pvo_entry *pvo;
1590 	uintptr_t pt;
1591 	pmap_t	pmap;
1592 	uint64_t lo = 0;
1593 
1594 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1595 	    ("moea64_remove_write: page %p is not managed", m));
1596 
1597 	/*
1598 	 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1599 	 * set by another thread while the object is locked.  Thus,
1600 	 * if PGA_WRITEABLE is clear, no page table entries need updating.
1601 	 */
1602 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1603 	if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1604 		return;
1605 	powerpc_sync();
1606 	LOCK_TABLE_RD();
1607 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1608 		pmap = pvo->pvo_pmap;
1609 		PMAP_LOCK(pmap);
1610 		if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1611 			pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1612 			pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1613 			pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1614 			if (pt != -1) {
1615 				MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1616 				lo |= pvo->pvo_pte.lpte.pte_lo;
1617 				pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1618 				MOEA64_PTE_CHANGE(mmu, pt,
1619 				    &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1620 				if (pvo->pvo_pmap == kernel_pmap)
1621 					isync();
1622 			}
1623 		}
1624 		if ((lo & LPTE_CHG) != 0)
1625 			vm_page_dirty(m);
1626 		PMAP_UNLOCK(pmap);
1627 	}
1628 	UNLOCK_TABLE_RD();
1629 	vm_page_aflag_clear(m, PGA_WRITEABLE);
1630 }
1631 
1632 /*
1633  *	moea64_ts_referenced:
1634  *
1635  *	Return a count of reference bits for a page, clearing those bits.
1636  *	It is not necessary for every reference bit to be cleared, but it
1637  *	is necessary that 0 only be returned when there are truly no
1638  *	reference bits set.
1639  *
1640  *	XXX: The exact number of bits to check and clear is a matter that
1641  *	should be tested and standardized at some point in the future for
1642  *	optimal aging of shared pages.
1643  */
1644 int
1645 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1646 {
1647 
1648 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1649 	    ("moea64_ts_referenced: page %p is not managed", m));
1650 	return (moea64_clear_bit(mmu, m, LPTE_REF));
1651 }
1652 
1653 /*
1654  * Modify the WIMG settings of all mappings for a page.
1655  */
1656 void
1657 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1658 {
1659 	struct	pvo_entry *pvo;
1660 	struct  pvo_head *pvo_head;
1661 	uintptr_t pt;
1662 	pmap_t	pmap;
1663 	uint64_t lo;
1664 
1665 	if ((m->oflags & VPO_UNMANAGED) != 0) {
1666 		m->md.mdpg_cache_attrs = ma;
1667 		return;
1668 	}
1669 
1670 	pvo_head = vm_page_to_pvoh(m);
1671 	lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1672 	LOCK_TABLE_RD();
1673 	LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1674 		pmap = pvo->pvo_pmap;
1675 		PMAP_LOCK(pmap);
1676 		pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1677 		pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1678 		pvo->pvo_pte.lpte.pte_lo |= lo;
1679 		if (pt != -1) {
1680 			MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1681 			    pvo->pvo_vpn);
1682 			if (pvo->pvo_pmap == kernel_pmap)
1683 				isync();
1684 		}
1685 		PMAP_UNLOCK(pmap);
1686 	}
1687 	UNLOCK_TABLE_RD();
1688 	m->md.mdpg_cache_attrs = ma;
1689 }
1690 
1691 /*
1692  * Map a wired page into kernel virtual address space.
1693  */
1694 void
1695 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1696 {
1697 	uint64_t	pte_lo;
1698 	int		error;
1699 
1700 	pte_lo = moea64_calc_wimg(pa, ma);
1701 
1702 	LOCK_TABLE_WR();
1703 	PMAP_LOCK(kernel_pmap);
1704 	error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1705 	    NULL, va, pa, pte_lo, PVO_WIRED);
1706 	PMAP_UNLOCK(kernel_pmap);
1707 	UNLOCK_TABLE_WR();
1708 
1709 	if (error != 0 && error != ENOENT)
1710 		panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1711 		    pa, error);
1712 }
1713 
1714 void
1715 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1716 {
1717 
1718 	moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1719 }
1720 
1721 /*
1722  * Extract the physical page address associated with the given kernel virtual
1723  * address.
1724  */
1725 vm_paddr_t
1726 moea64_kextract(mmu_t mmu, vm_offset_t va)
1727 {
1728 	struct		pvo_entry *pvo;
1729 	vm_paddr_t pa;
1730 
1731 	/*
1732 	 * Shortcut the direct-mapped case when applicable.  We never put
1733 	 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1734 	 */
1735 	if (va < VM_MIN_KERNEL_ADDRESS)
1736 		return (va);
1737 
1738 	PMAP_LOCK(kernel_pmap);
1739 	pvo = moea64_pvo_find_va(kernel_pmap, va);
1740 	KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1741 	    va));
1742 	pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1743 	PMAP_UNLOCK(kernel_pmap);
1744 	return (pa);
1745 }
1746 
1747 /*
1748  * Remove a wired page from kernel virtual address space.
1749  */
1750 void
1751 moea64_kremove(mmu_t mmu, vm_offset_t va)
1752 {
1753 	moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1754 }
1755 
1756 /*
1757  * Map a range of physical addresses into kernel virtual address space.
1758  *
1759  * The value passed in *virt is a suggested virtual address for the mapping.
1760  * Architectures which can support a direct-mapped physical to virtual region
1761  * can return the appropriate address within that region, leaving '*virt'
1762  * unchanged.  We cannot and therefore do not; *virt is updated with the
1763  * first usable address after the mapped region.
1764  */
1765 vm_offset_t
1766 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1767     vm_paddr_t pa_end, int prot)
1768 {
1769 	vm_offset_t	sva, va;
1770 
1771 	sva = *virt;
1772 	va = sva;
1773 	for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1774 		moea64_kenter(mmu, va, pa_start);
1775 	*virt = va;
1776 
1777 	return (sva);
1778 }
1779 
1780 /*
1781  * Returns true if the pmap's pv is one of the first
1782  * 16 pvs linked to from this page.  This count may
1783  * be changed upwards or downwards in the future; it
1784  * is only necessary that true be returned for a small
1785  * subset of pmaps for proper page aging.
1786  */
1787 boolean_t
1788 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1789 {
1790         int loops;
1791 	struct pvo_entry *pvo;
1792 	boolean_t rv;
1793 
1794 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1795 	    ("moea64_page_exists_quick: page %p is not managed", m));
1796 	loops = 0;
1797 	rv = FALSE;
1798 	LOCK_TABLE_RD();
1799 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1800 		if (pvo->pvo_pmap == pmap) {
1801 			rv = TRUE;
1802 			break;
1803 		}
1804 		if (++loops >= 16)
1805 			break;
1806 	}
1807 	UNLOCK_TABLE_RD();
1808 	return (rv);
1809 }
1810 
1811 /*
1812  * Return the number of managed mappings to the given physical page
1813  * that are wired.
1814  */
1815 int
1816 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1817 {
1818 	struct pvo_entry *pvo;
1819 	int count;
1820 
1821 	count = 0;
1822 	if ((m->oflags & VPO_UNMANAGED) != 0)
1823 		return (count);
1824 	LOCK_TABLE_RD();
1825 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1826 		if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1827 			count++;
1828 	UNLOCK_TABLE_RD();
1829 	return (count);
1830 }
1831 
1832 static uintptr_t	moea64_vsidcontext;
1833 
1834 uintptr_t
1835 moea64_get_unique_vsid(void) {
1836 	u_int entropy;
1837 	register_t hash;
1838 	uint32_t mask;
1839 	int i;
1840 
1841 	entropy = 0;
1842 	__asm __volatile("mftb %0" : "=r"(entropy));
1843 
1844 	mtx_lock(&moea64_slb_mutex);
1845 	for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1846 		u_int	n;
1847 
1848 		/*
1849 		 * Create a new value by mutiplying by a prime and adding in
1850 		 * entropy from the timebase register.  This is to make the
1851 		 * VSID more random so that the PT hash function collides
1852 		 * less often.  (Note that the prime casues gcc to do shifts
1853 		 * instead of a multiply.)
1854 		 */
1855 		moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1856 		hash = moea64_vsidcontext & (NVSIDS - 1);
1857 		if (hash == 0)		/* 0 is special, avoid it */
1858 			continue;
1859 		n = hash >> 5;
1860 		mask = 1 << (hash & (VSID_NBPW - 1));
1861 		hash = (moea64_vsidcontext & VSID_HASHMASK);
1862 		if (moea64_vsid_bitmap[n] & mask) {	/* collision? */
1863 			/* anything free in this bucket? */
1864 			if (moea64_vsid_bitmap[n] == 0xffffffff) {
1865 				entropy = (moea64_vsidcontext >> 20);
1866 				continue;
1867 			}
1868 			i = ffs(~moea64_vsid_bitmap[n]) - 1;
1869 			mask = 1 << i;
1870 			hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1871 			hash |= i;
1872 		}
1873 		KASSERT(!(moea64_vsid_bitmap[n] & mask),
1874 		    ("Allocating in-use VSID %#zx\n", hash));
1875 		moea64_vsid_bitmap[n] |= mask;
1876 		mtx_unlock(&moea64_slb_mutex);
1877 		return (hash);
1878 	}
1879 
1880 	mtx_unlock(&moea64_slb_mutex);
1881 	panic("%s: out of segments",__func__);
1882 }
1883 
1884 #ifdef __powerpc64__
1885 void
1886 moea64_pinit(mmu_t mmu, pmap_t pmap)
1887 {
1888 
1889 	RB_INIT(&pmap->pmap_pvo);
1890 
1891 	pmap->pm_slb_tree_root = slb_alloc_tree();
1892 	pmap->pm_slb = slb_alloc_user_cache();
1893 	pmap->pm_slb_len = 0;
1894 }
1895 #else
1896 void
1897 moea64_pinit(mmu_t mmu, pmap_t pmap)
1898 {
1899 	int	i;
1900 	uint32_t hash;
1901 
1902 	RB_INIT(&pmap->pmap_pvo);
1903 
1904 	if (pmap_bootstrapped)
1905 		pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1906 		    (vm_offset_t)pmap);
1907 	else
1908 		pmap->pmap_phys = pmap;
1909 
1910 	/*
1911 	 * Allocate some segment registers for this pmap.
1912 	 */
1913 	hash = moea64_get_unique_vsid();
1914 
1915 	for (i = 0; i < 16; i++)
1916 		pmap->pm_sr[i] = VSID_MAKE(i, hash);
1917 
1918 	KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1919 }
1920 #endif
1921 
1922 /*
1923  * Initialize the pmap associated with process 0.
1924  */
1925 void
1926 moea64_pinit0(mmu_t mmu, pmap_t pm)
1927 {
1928 
1929 	PMAP_LOCK_INIT(pm);
1930 	moea64_pinit(mmu, pm);
1931 	bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1932 }
1933 
1934 /*
1935  * Set the physical protection on the specified range of this map as requested.
1936  */
1937 static void
1938 moea64_pvo_protect(mmu_t mmu,  pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1939 {
1940 	uintptr_t pt;
1941 	struct	vm_page *pg;
1942 	uint64_t oldlo;
1943 
1944 	PMAP_LOCK_ASSERT(pm, MA_OWNED);
1945 
1946 	/*
1947 	 * Grab the PTE pointer before we diddle with the cached PTE
1948 	 * copy.
1949 	 */
1950 	pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1951 
1952 	/*
1953 	 * Change the protection of the page.
1954 	 */
1955 	oldlo = pvo->pvo_pte.lpte.pte_lo;
1956 	pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1957 	pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1958 	if ((prot & VM_PROT_EXECUTE) == 0)
1959 		pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1960 	if (prot & VM_PROT_WRITE)
1961 		pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
1962 	else
1963 		pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1964 
1965 	pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1966 
1967 	/*
1968 	 * If the PVO is in the page table, update that pte as well.
1969 	 */
1970 	if (pt != -1)
1971 		MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1972 		    pvo->pvo_vpn);
1973 	if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
1974 	    (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1975 		if ((pg->oflags & VPO_UNMANAGED) == 0)
1976 			vm_page_aflag_set(pg, PGA_EXECUTABLE);
1977 		moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
1978 		    pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
1979 	}
1980 
1981 	/*
1982 	 * Update vm about the REF/CHG bits if the page is managed and we have
1983 	 * removed write access.
1984 	 */
1985 	if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
1986 	    (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) {
1987 		if (pg != NULL) {
1988 			if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
1989 				vm_page_dirty(pg);
1990 			if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
1991 				vm_page_aflag_set(pg, PGA_REFERENCED);
1992 		}
1993 	}
1994 }
1995 
1996 void
1997 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1998     vm_prot_t prot)
1999 {
2000 	struct	pvo_entry *pvo, *tpvo, key;
2001 
2002 	CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2003 	    sva, eva, prot);
2004 
2005 	KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2006 	    ("moea64_protect: non current pmap"));
2007 
2008 	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2009 		moea64_remove(mmu, pm, sva, eva);
2010 		return;
2011 	}
2012 
2013 	LOCK_TABLE_RD();
2014 	PMAP_LOCK(pm);
2015 	key.pvo_vaddr = sva;
2016 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2017 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2018 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2019 		moea64_pvo_protect(mmu, pm, pvo, prot);
2020 	}
2021 	UNLOCK_TABLE_RD();
2022 	PMAP_UNLOCK(pm);
2023 }
2024 
2025 /*
2026  * Map a list of wired pages into kernel virtual address space.  This is
2027  * intended for temporary mappings which do not need page modification or
2028  * references recorded.  Existing mappings in the region are overwritten.
2029  */
2030 void
2031 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2032 {
2033 	while (count-- > 0) {
2034 		moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2035 		va += PAGE_SIZE;
2036 		m++;
2037 	}
2038 }
2039 
2040 /*
2041  * Remove page mappings from kernel virtual address space.  Intended for
2042  * temporary mappings entered by moea64_qenter.
2043  */
2044 void
2045 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2046 {
2047 	while (count-- > 0) {
2048 		moea64_kremove(mmu, va);
2049 		va += PAGE_SIZE;
2050 	}
2051 }
2052 
2053 void
2054 moea64_release_vsid(uint64_t vsid)
2055 {
2056 	int idx, mask;
2057 
2058 	mtx_lock(&moea64_slb_mutex);
2059 	idx = vsid & (NVSIDS-1);
2060 	mask = 1 << (idx % VSID_NBPW);
2061 	idx /= VSID_NBPW;
2062 	KASSERT(moea64_vsid_bitmap[idx] & mask,
2063 	    ("Freeing unallocated VSID %#jx", vsid));
2064 	moea64_vsid_bitmap[idx] &= ~mask;
2065 	mtx_unlock(&moea64_slb_mutex);
2066 }
2067 
2068 
2069 void
2070 moea64_release(mmu_t mmu, pmap_t pmap)
2071 {
2072 
2073 	/*
2074 	 * Free segment registers' VSIDs
2075 	 */
2076     #ifdef __powerpc64__
2077 	slb_free_tree(pmap);
2078 	slb_free_user_cache(pmap->pm_slb);
2079     #else
2080 	KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2081 
2082 	moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2083     #endif
2084 }
2085 
2086 /*
2087  * Remove all pages mapped by the specified pmap
2088  */
2089 void
2090 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2091 {
2092 	struct	pvo_entry *pvo, *tpvo;
2093 
2094 	LOCK_TABLE_WR();
2095 	PMAP_LOCK(pm);
2096 	RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2097 		if (!(pvo->pvo_vaddr & PVO_WIRED))
2098 			moea64_pvo_remove(mmu, pvo);
2099 	}
2100 	UNLOCK_TABLE_WR();
2101 	PMAP_UNLOCK(pm);
2102 }
2103 
2104 /*
2105  * Remove the given range of addresses from the specified map.
2106  */
2107 void
2108 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2109 {
2110 	struct	pvo_entry *pvo, *tpvo, key;
2111 
2112 	/*
2113 	 * Perform an unsynchronized read.  This is, however, safe.
2114 	 */
2115 	if (pm->pm_stats.resident_count == 0)
2116 		return;
2117 
2118 	LOCK_TABLE_WR();
2119 	PMAP_LOCK(pm);
2120 	key.pvo_vaddr = sva;
2121 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2122 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2123 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2124 		moea64_pvo_remove(mmu, pvo);
2125 	}
2126 	UNLOCK_TABLE_WR();
2127 	PMAP_UNLOCK(pm);
2128 }
2129 
2130 /*
2131  * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2132  * will reflect changes in pte's back to the vm_page.
2133  */
2134 void
2135 moea64_remove_all(mmu_t mmu, vm_page_t m)
2136 {
2137 	struct	pvo_entry *pvo, *next_pvo;
2138 	pmap_t	pmap;
2139 
2140 	LOCK_TABLE_WR();
2141 	LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2142 		pmap = pvo->pvo_pmap;
2143 		PMAP_LOCK(pmap);
2144 		moea64_pvo_remove(mmu, pvo);
2145 		PMAP_UNLOCK(pmap);
2146 	}
2147 	UNLOCK_TABLE_WR();
2148 	if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2149 		vm_page_dirty(m);
2150 	vm_page_aflag_clear(m, PGA_WRITEABLE);
2151 	vm_page_aflag_clear(m, PGA_EXECUTABLE);
2152 }
2153 
2154 /*
2155  * Allocate a physical page of memory directly from the phys_avail map.
2156  * Can only be called from moea64_bootstrap before avail start and end are
2157  * calculated.
2158  */
2159 vm_offset_t
2160 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2161 {
2162 	vm_offset_t	s, e;
2163 	int		i, j;
2164 
2165 	size = round_page(size);
2166 	for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2167 		if (align != 0)
2168 			s = (phys_avail[i] + align - 1) & ~(align - 1);
2169 		else
2170 			s = phys_avail[i];
2171 		e = s + size;
2172 
2173 		if (s < phys_avail[i] || e > phys_avail[i + 1])
2174 			continue;
2175 
2176 		if (s + size > platform_real_maxaddr())
2177 			continue;
2178 
2179 		if (s == phys_avail[i]) {
2180 			phys_avail[i] += size;
2181 		} else if (e == phys_avail[i + 1]) {
2182 			phys_avail[i + 1] -= size;
2183 		} else {
2184 			for (j = phys_avail_count * 2; j > i; j -= 2) {
2185 				phys_avail[j] = phys_avail[j - 2];
2186 				phys_avail[j + 1] = phys_avail[j - 1];
2187 			}
2188 
2189 			phys_avail[i + 3] = phys_avail[i + 1];
2190 			phys_avail[i + 1] = s;
2191 			phys_avail[i + 2] = e;
2192 			phys_avail_count++;
2193 		}
2194 
2195 		return (s);
2196 	}
2197 	panic("moea64_bootstrap_alloc: could not allocate memory");
2198 }
2199 
2200 static int
2201 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2202     struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2203     uint64_t pte_lo, int flags)
2204 {
2205 	struct	 pvo_entry *pvo;
2206 	uint64_t vsid;
2207 	int	 first;
2208 	u_int	 ptegidx;
2209 	int	 i;
2210 	int      bootstrap;
2211 
2212 	/*
2213 	 * One nasty thing that can happen here is that the UMA calls to
2214 	 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2215 	 * which calls UMA...
2216 	 *
2217 	 * We break the loop by detecting recursion and allocating out of
2218 	 * the bootstrap pool.
2219 	 */
2220 
2221 	first = 0;
2222 	bootstrap = (flags & PVO_BOOTSTRAP);
2223 
2224 	if (!moea64_initialized)
2225 		bootstrap = 1;
2226 
2227 	PMAP_LOCK_ASSERT(pm, MA_OWNED);
2228 	rw_assert(&moea64_table_lock, RA_WLOCKED);
2229 
2230 	/*
2231 	 * Compute the PTE Group index.
2232 	 */
2233 	va &= ~ADDR_POFF;
2234 	vsid = va_to_vsid(pm, va);
2235 	ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2236 
2237 	/*
2238 	 * Remove any existing mapping for this page.  Reuse the pvo entry if
2239 	 * there is a mapping.
2240 	 */
2241 	moea64_pvo_enter_calls++;
2242 
2243 	LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2244 		if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2245 			if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2246 			    (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2247 			    == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2248 			    	if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2249 					/* Re-insert if spilled */
2250 					i = MOEA64_PTE_INSERT(mmu, ptegidx,
2251 					    &pvo->pvo_pte.lpte);
2252 					if (i >= 0)
2253 						PVO_PTEGIDX_SET(pvo, i);
2254 					moea64_pte_overflow--;
2255 				}
2256 				return (0);
2257 			}
2258 			moea64_pvo_remove(mmu, pvo);
2259 			break;
2260 		}
2261 	}
2262 
2263 	/*
2264 	 * If we aren't overwriting a mapping, try to allocate.
2265 	 */
2266 	if (bootstrap) {
2267 		if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2268 			panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2269 			      moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2270 			      BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2271 		}
2272 		pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2273 		moea64_bpvo_pool_index++;
2274 		bootstrap = 1;
2275 	} else {
2276 		pvo = uma_zalloc(zone, M_NOWAIT);
2277 	}
2278 
2279 	if (pvo == NULL)
2280 		return (ENOMEM);
2281 
2282 	moea64_pvo_entries++;
2283 	pvo->pvo_vaddr = va;
2284 	pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2285 	    | (vsid << 16);
2286 	pvo->pvo_pmap = pm;
2287 	LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2288 	pvo->pvo_vaddr &= ~ADDR_POFF;
2289 
2290 	if (flags & PVO_WIRED)
2291 		pvo->pvo_vaddr |= PVO_WIRED;
2292 	if (pvo_head != NULL)
2293 		pvo->pvo_vaddr |= PVO_MANAGED;
2294 	if (bootstrap)
2295 		pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2296 	if (flags & PVO_LARGE)
2297 		pvo->pvo_vaddr |= PVO_LARGE;
2298 
2299 	moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2300 	    (uint64_t)(pa) | pte_lo, flags);
2301 
2302 	/*
2303 	 * Add to pmap list
2304 	 */
2305 	RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2306 
2307 	/*
2308 	 * Remember if the list was empty and therefore will be the first
2309 	 * item.
2310 	 */
2311 	if (pvo_head != NULL) {
2312 		if (LIST_FIRST(pvo_head) == NULL)
2313 			first = 1;
2314 		LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2315 	}
2316 
2317 	if (pvo->pvo_vaddr & PVO_WIRED) {
2318 		pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2319 		pm->pm_stats.wired_count++;
2320 	}
2321 	pm->pm_stats.resident_count++;
2322 
2323 	/*
2324 	 * We hope this succeeds but it isn't required.
2325 	 */
2326 	i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2327 	if (i >= 0) {
2328 		PVO_PTEGIDX_SET(pvo, i);
2329 	} else {
2330 		panic("moea64_pvo_enter: overflow");
2331 		moea64_pte_overflow++;
2332 	}
2333 
2334 	if (pm == kernel_pmap)
2335 		isync();
2336 
2337 #ifdef __powerpc64__
2338 	/*
2339 	 * Make sure all our bootstrap mappings are in the SLB as soon
2340 	 * as virtual memory is switched on.
2341 	 */
2342 	if (!pmap_bootstrapped)
2343 		moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2344 #endif
2345 
2346 	return (first ? ENOENT : 0);
2347 }
2348 
2349 static void
2350 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2351 {
2352 	struct	vm_page *pg;
2353 	uintptr_t pt;
2354 
2355 	PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2356 	rw_assert(&moea64_table_lock, RA_WLOCKED);
2357 
2358 	/*
2359 	 * If there is an active pte entry, we need to deactivate it (and
2360 	 * save the ref & cfg bits).
2361 	 */
2362 	pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2363 	if (pt != -1) {
2364 		MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2365 		PVO_PTEGIDX_CLR(pvo);
2366 	} else {
2367 		moea64_pte_overflow--;
2368 	}
2369 
2370 	/*
2371 	 * Update our statistics.
2372 	 */
2373 	pvo->pvo_pmap->pm_stats.resident_count--;
2374 	if (pvo->pvo_vaddr & PVO_WIRED)
2375 		pvo->pvo_pmap->pm_stats.wired_count--;
2376 
2377 	/*
2378 	 * Remove this PVO from the pmap list.
2379 	 */
2380 	RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2381 
2382 	/*
2383 	 * Remove this from the overflow list and return it to the pool
2384 	 * if we aren't going to reuse it.
2385 	 */
2386 	LIST_REMOVE(pvo, pvo_olink);
2387 
2388 	/*
2389 	 * Update vm about the REF/CHG bits if the page is managed.
2390 	 */
2391 	pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2392 
2393 	if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2394 		LIST_REMOVE(pvo, pvo_vlink);
2395 		if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2396 			if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2397 				vm_page_dirty(pg);
2398 			if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2399 				vm_page_aflag_set(pg, PGA_REFERENCED);
2400 			if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2401 				vm_page_aflag_clear(pg, PGA_WRITEABLE);
2402 		}
2403 		if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2404 			vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2405 	}
2406 
2407 	moea64_pvo_entries--;
2408 	moea64_pvo_remove_calls++;
2409 
2410 	if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2411 		uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2412 		    moea64_upvo_zone, pvo);
2413 }
2414 
2415 static struct pvo_entry *
2416 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2417 {
2418 	struct pvo_entry key;
2419 
2420 	key.pvo_vaddr = va & ~ADDR_POFF;
2421 	return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2422 }
2423 
2424 static boolean_t
2425 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2426 {
2427 	struct	pvo_entry *pvo;
2428 	uintptr_t pt;
2429 
2430 	LOCK_TABLE_RD();
2431 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2432 		/*
2433 		 * See if we saved the bit off.  If so, return success.
2434 		 */
2435 		if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2436 			UNLOCK_TABLE_RD();
2437 			return (TRUE);
2438 		}
2439 	}
2440 
2441 	/*
2442 	 * No luck, now go through the hard part of looking at the PTEs
2443 	 * themselves.  Sync so that any pending REF/CHG bits are flushed to
2444 	 * the PTEs.
2445 	 */
2446 	powerpc_sync();
2447 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2448 
2449 		/*
2450 		 * See if this pvo has a valid PTE.  if so, fetch the
2451 		 * REF/CHG bits from the valid PTE.  If the appropriate
2452 		 * ptebit is set, return success.
2453 		 */
2454 		PMAP_LOCK(pvo->pvo_pmap);
2455 		pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2456 		if (pt != -1) {
2457 			MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2458 			if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2459 				PMAP_UNLOCK(pvo->pvo_pmap);
2460 				UNLOCK_TABLE_RD();
2461 				return (TRUE);
2462 			}
2463 		}
2464 		PMAP_UNLOCK(pvo->pvo_pmap);
2465 	}
2466 
2467 	UNLOCK_TABLE_RD();
2468 	return (FALSE);
2469 }
2470 
2471 static u_int
2472 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2473 {
2474 	u_int	count;
2475 	struct	pvo_entry *pvo;
2476 	uintptr_t pt;
2477 
2478 	/*
2479 	 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2480 	 * we can reset the right ones).  note that since the pvo entries and
2481 	 * list heads are accessed via BAT0 and are never placed in the page
2482 	 * table, we don't have to worry about further accesses setting the
2483 	 * REF/CHG bits.
2484 	 */
2485 	powerpc_sync();
2486 
2487 	/*
2488 	 * For each pvo entry, clear the pvo's ptebit.  If this pvo has a
2489 	 * valid pte clear the ptebit from the valid pte.
2490 	 */
2491 	count = 0;
2492 	LOCK_TABLE_RD();
2493 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2494 		PMAP_LOCK(pvo->pvo_pmap);
2495 		pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2496 		if (pt != -1) {
2497 			MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2498 			if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2499 				count++;
2500 				MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2501 				    pvo->pvo_vpn, ptebit);
2502 			}
2503 		}
2504 		pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2505 		PMAP_UNLOCK(pvo->pvo_pmap);
2506 	}
2507 
2508 	UNLOCK_TABLE_RD();
2509 	return (count);
2510 }
2511 
2512 boolean_t
2513 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2514 {
2515 	struct pvo_entry *pvo, key;
2516 	vm_offset_t ppa;
2517 	int error = 0;
2518 
2519 	PMAP_LOCK(kernel_pmap);
2520 	key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2521 	for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2522 	    ppa < pa + size; ppa += PAGE_SIZE,
2523 	    pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2524 		if (pvo == NULL ||
2525 		    (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2526 			error = EFAULT;
2527 			break;
2528 		}
2529 	}
2530 	PMAP_UNLOCK(kernel_pmap);
2531 
2532 	return (error);
2533 }
2534 
2535 /*
2536  * Map a set of physical memory pages into the kernel virtual
2537  * address space. Return a pointer to where it is mapped. This
2538  * routine is intended to be used for mapping device memory,
2539  * NOT real memory.
2540  */
2541 void *
2542 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2543 {
2544 	vm_offset_t va, tmpva, ppa, offset;
2545 
2546 	ppa = trunc_page(pa);
2547 	offset = pa & PAGE_MASK;
2548 	size = roundup2(offset + size, PAGE_SIZE);
2549 
2550 	va = kva_alloc(size);
2551 
2552 	if (!va)
2553 		panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2554 
2555 	for (tmpva = va; size > 0;) {
2556 		moea64_kenter_attr(mmu, tmpva, ppa, ma);
2557 		size -= PAGE_SIZE;
2558 		tmpva += PAGE_SIZE;
2559 		ppa += PAGE_SIZE;
2560 	}
2561 
2562 	return ((void *)(va + offset));
2563 }
2564 
2565 void *
2566 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2567 {
2568 
2569 	return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2570 }
2571 
2572 void
2573 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2574 {
2575 	vm_offset_t base, offset;
2576 
2577 	base = trunc_page(va);
2578 	offset = va & PAGE_MASK;
2579 	size = roundup2(offset + size, PAGE_SIZE);
2580 
2581 	kva_free(base, size);
2582 }
2583 
2584 void
2585 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2586 {
2587 	struct pvo_entry *pvo;
2588 	vm_offset_t lim;
2589 	vm_paddr_t pa;
2590 	vm_size_t len;
2591 
2592 	PMAP_LOCK(pm);
2593 	while (sz > 0) {
2594 		lim = round_page(va);
2595 		len = MIN(lim - va, sz);
2596 		pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2597 		if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2598 			pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2599 			    (va & ADDR_POFF);
2600 			moea64_syncicache(mmu, pm, va, pa, len);
2601 		}
2602 		va += len;
2603 		sz -= len;
2604 	}
2605 	PMAP_UNLOCK(pm);
2606 }
2607 
2608 vm_offset_t
2609 moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2610     vm_size_t *sz)
2611 {
2612 	if (md->md_vaddr == ~0UL)
2613 	    return (md->md_paddr + ofs);
2614 	else
2615 	    return (md->md_vaddr + ofs);
2616 }
2617 
2618 struct pmap_md *
2619 moea64_scan_md(mmu_t mmu, struct pmap_md *prev)
2620 {
2621 	static struct pmap_md md;
2622 	struct pvo_entry *pvo;
2623 	vm_offset_t va;
2624 
2625 	if (dumpsys_minidump) {
2626 		md.md_paddr = ~0UL;	/* Minidumps use virtual addresses. */
2627 		if (prev == NULL) {
2628 			/* 1st: kernel .data and .bss. */
2629 			md.md_index = 1;
2630 			md.md_vaddr = trunc_page((uintptr_t)_etext);
2631 			md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2632 			return (&md);
2633 		}
2634 		switch (prev->md_index) {
2635 		case 1:
2636 			/* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2637 			md.md_index = 2;
2638 			md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2639 			md.md_size = round_page(msgbufp->msg_size);
2640 			break;
2641 		case 2:
2642 			/* 3rd: kernel VM. */
2643 			va = prev->md_vaddr + prev->md_size;
2644 			/* Find start of next chunk (from va). */
2645 			while (va < virtual_end) {
2646 				/* Don't dump the buffer cache. */
2647 				if (va >= kmi.buffer_sva &&
2648 				    va < kmi.buffer_eva) {
2649 					va = kmi.buffer_eva;
2650 					continue;
2651 				}
2652 				pvo = moea64_pvo_find_va(kernel_pmap,
2653 				    va & ~ADDR_POFF);
2654 				if (pvo != NULL &&
2655 				    (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID))
2656 					break;
2657 				va += PAGE_SIZE;
2658 			}
2659 			if (va < virtual_end) {
2660 				md.md_vaddr = va;
2661 				va += PAGE_SIZE;
2662 				/* Find last page in chunk. */
2663 				while (va < virtual_end) {
2664 					/* Don't run into the buffer cache. */
2665 					if (va == kmi.buffer_sva)
2666 						break;
2667 					pvo = moea64_pvo_find_va(kernel_pmap,
2668 					    va & ~ADDR_POFF);
2669 					if (pvo == NULL ||
2670 					    !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID))
2671 						break;
2672 					va += PAGE_SIZE;
2673 				}
2674 				md.md_size = va - md.md_vaddr;
2675 				break;
2676 			}
2677 			md.md_index = 3;
2678 			/* FALLTHROUGH */
2679 		default:
2680 			return (NULL);
2681 		}
2682 	} else { /* minidumps */
2683 		if (prev == NULL) {
2684 			/* first physical chunk. */
2685 			md.md_paddr = pregions[0].mr_start;
2686 			md.md_size = pregions[0].mr_size;
2687 			md.md_vaddr = ~0UL;
2688 			md.md_index = 1;
2689 		} else if (md.md_index < pregions_sz) {
2690 			md.md_paddr = pregions[md.md_index].mr_start;
2691 			md.md_size = pregions[md.md_index].mr_size;
2692 			md.md_vaddr = ~0UL;
2693 			md.md_index++;
2694 		} else {
2695 			/* There's no next physical chunk. */
2696 			return (NULL);
2697 		}
2698 	}
2699 
2700 	return (&md);
2701 }
2702