1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <sys/kdb.h> 131 132 #include <dev/ofw/openfirm.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/uma.h> 144 145 #include <machine/_inttypes.h> 146 #include <machine/cpu.h> 147 #include <machine/platform.h> 148 #include <machine/frame.h> 149 #include <machine/md_var.h> 150 #include <machine/psl.h> 151 #include <machine/bat.h> 152 #include <machine/hid.h> 153 #include <machine/pte.h> 154 #include <machine/sr.h> 155 #include <machine/trap.h> 156 #include <machine/mmuvar.h> 157 158 #include "mmu_oea64.h" 159 #include "mmu_if.h" 160 #include "moea64_if.h" 161 162 void moea64_release_vsid(uint64_t vsid); 163 uintptr_t moea64_get_unique_vsid(void); 164 165 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync() 166 #define ENABLE_TRANS(msr) mtmsr(msr); isync() 167 168 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 169 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 170 #define VSID_HASH_MASK 0x0000007fffffffffULL 171 172 #define MOEA_PVO_CHECK(pvo) 173 174 #define LOCK_TABLE() mtx_lock(&moea64_table_mutex) 175 #define UNLOCK_TABLE() mtx_unlock(&moea64_table_mutex); 176 #define ASSERT_TABLE_LOCK() mtx_assert(&moea64_table_mutex, MA_OWNED) 177 178 struct ofw_map { 179 cell_t om_va; 180 cell_t om_len; 181 cell_t om_pa_hi; 182 cell_t om_pa_lo; 183 cell_t om_mode; 184 }; 185 186 /* 187 * Map of physical memory regions. 188 */ 189 static struct mem_region *regions; 190 static struct mem_region *pregions; 191 static u_int phys_avail_count; 192 static int regions_sz, pregions_sz; 193 194 extern void bs_remap_earlyboot(void); 195 196 /* 197 * Lock for the pteg and pvo tables. 198 */ 199 struct mtx moea64_table_mutex; 200 struct mtx moea64_slb_mutex; 201 202 /* 203 * PTEG data. 204 */ 205 u_int moea64_pteg_count; 206 u_int moea64_pteg_mask; 207 208 /* 209 * PVO data. 210 */ 211 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */ 212 struct pvo_head moea64_pvo_kunmanaged = /* list of unmanaged pages */ 213 LIST_HEAD_INITIALIZER(moea64_pvo_kunmanaged); 214 215 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */ 216 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */ 217 218 #define BPVO_POOL_SIZE 327680 219 static struct pvo_entry *moea64_bpvo_pool; 220 static int moea64_bpvo_pool_index = 0; 221 222 #define VSID_NBPW (sizeof(u_int32_t) * 8) 223 #ifdef __powerpc64__ 224 #define NVSIDS (NPMAPS * 16) 225 #define VSID_HASHMASK 0xffffffffUL 226 #else 227 #define NVSIDS NPMAPS 228 #define VSID_HASHMASK 0xfffffUL 229 #endif 230 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 231 232 static boolean_t moea64_initialized = FALSE; 233 234 /* 235 * Statistics. 236 */ 237 u_int moea64_pte_valid = 0; 238 u_int moea64_pte_overflow = 0; 239 u_int moea64_pvo_entries = 0; 240 u_int moea64_pvo_enter_calls = 0; 241 u_int moea64_pvo_remove_calls = 0; 242 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 243 &moea64_pte_valid, 0, ""); 244 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 245 &moea64_pte_overflow, 0, ""); 246 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 247 &moea64_pvo_entries, 0, ""); 248 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 249 &moea64_pvo_enter_calls, 0, ""); 250 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 251 &moea64_pvo_remove_calls, 0, ""); 252 253 vm_offset_t moea64_scratchpage_va[2]; 254 struct pvo_entry *moea64_scratchpage_pvo[2]; 255 uintptr_t moea64_scratchpage_pte[2]; 256 struct mtx moea64_scratchpage_mtx; 257 258 uint64_t moea64_large_page_mask = 0; 259 int moea64_large_page_size = 0; 260 int moea64_large_page_shift = 0; 261 262 /* 263 * PVO calls. 264 */ 265 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *, 266 vm_offset_t, vm_offset_t, uint64_t, int); 267 static void moea64_pvo_remove(mmu_t, struct pvo_entry *); 268 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 269 270 /* 271 * Utility routines. 272 */ 273 static void moea64_enter_locked(mmu_t, pmap_t, vm_offset_t, 274 vm_page_t, vm_prot_t, boolean_t); 275 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t); 276 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t); 277 static void moea64_kremove(mmu_t, vm_offset_t); 278 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 279 vm_offset_t pa, vm_size_t sz); 280 281 /* 282 * Kernel MMU interface 283 */ 284 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 285 void moea64_clear_modify(mmu_t, vm_page_t); 286 void moea64_clear_reference(mmu_t, vm_page_t); 287 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 288 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 289 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 290 vm_prot_t); 291 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 292 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 293 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 294 void moea64_init(mmu_t); 295 boolean_t moea64_is_modified(mmu_t, vm_page_t); 296 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 297 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 298 boolean_t moea64_ts_referenced(mmu_t, vm_page_t); 299 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 300 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 301 int moea64_page_wired_mappings(mmu_t, vm_page_t); 302 void moea64_pinit(mmu_t, pmap_t); 303 void moea64_pinit0(mmu_t, pmap_t); 304 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 305 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 306 void moea64_qremove(mmu_t, vm_offset_t, int); 307 void moea64_release(mmu_t, pmap_t); 308 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 309 void moea64_remove_all(mmu_t, vm_page_t); 310 void moea64_remove_write(mmu_t, vm_page_t); 311 void moea64_zero_page(mmu_t, vm_page_t); 312 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 313 void moea64_zero_page_idle(mmu_t, vm_page_t); 314 void moea64_activate(mmu_t, struct thread *); 315 void moea64_deactivate(mmu_t, struct thread *); 316 void *moea64_mapdev(mmu_t, vm_offset_t, vm_size_t); 317 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 318 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 319 vm_offset_t moea64_kextract(mmu_t, vm_offset_t); 320 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 321 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 322 void moea64_kenter(mmu_t, vm_offset_t, vm_offset_t); 323 boolean_t moea64_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 324 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 325 326 static mmu_method_t moea64_methods[] = { 327 MMUMETHOD(mmu_change_wiring, moea64_change_wiring), 328 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 329 MMUMETHOD(mmu_clear_reference, moea64_clear_reference), 330 MMUMETHOD(mmu_copy_page, moea64_copy_page), 331 MMUMETHOD(mmu_enter, moea64_enter), 332 MMUMETHOD(mmu_enter_object, moea64_enter_object), 333 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 334 MMUMETHOD(mmu_extract, moea64_extract), 335 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 336 MMUMETHOD(mmu_init, moea64_init), 337 MMUMETHOD(mmu_is_modified, moea64_is_modified), 338 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 339 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 340 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 341 MMUMETHOD(mmu_map, moea64_map), 342 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 343 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 344 MMUMETHOD(mmu_pinit, moea64_pinit), 345 MMUMETHOD(mmu_pinit0, moea64_pinit0), 346 MMUMETHOD(mmu_protect, moea64_protect), 347 MMUMETHOD(mmu_qenter, moea64_qenter), 348 MMUMETHOD(mmu_qremove, moea64_qremove), 349 MMUMETHOD(mmu_release, moea64_release), 350 MMUMETHOD(mmu_remove, moea64_remove), 351 MMUMETHOD(mmu_remove_all, moea64_remove_all), 352 MMUMETHOD(mmu_remove_write, moea64_remove_write), 353 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 354 MMUMETHOD(mmu_zero_page, moea64_zero_page), 355 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 356 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 357 MMUMETHOD(mmu_activate, moea64_activate), 358 MMUMETHOD(mmu_deactivate, moea64_deactivate), 359 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 360 361 /* Internal interfaces */ 362 MMUMETHOD(mmu_mapdev, moea64_mapdev), 363 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 364 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 365 MMUMETHOD(mmu_kextract, moea64_kextract), 366 MMUMETHOD(mmu_kenter, moea64_kenter), 367 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 368 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 369 370 { 0, 0 } 371 }; 372 373 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 374 375 static __inline u_int 376 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large) 377 { 378 uint64_t hash; 379 int shift; 380 381 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT; 382 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >> 383 shift); 384 return (hash & moea64_pteg_mask); 385 } 386 387 static __inline struct pvo_head * 388 vm_page_to_pvoh(vm_page_t m) 389 { 390 391 return (&m->md.mdpg_pvoh); 392 } 393 394 static __inline void 395 moea64_attr_clear(vm_page_t m, u_int64_t ptebit) 396 { 397 398 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 399 m->md.mdpg_attrs &= ~ptebit; 400 } 401 402 static __inline u_int64_t 403 moea64_attr_fetch(vm_page_t m) 404 { 405 406 return (m->md.mdpg_attrs); 407 } 408 409 static __inline void 410 moea64_attr_save(vm_page_t m, u_int64_t ptebit) 411 { 412 413 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 414 m->md.mdpg_attrs |= ptebit; 415 } 416 417 static __inline void 418 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va, 419 uint64_t pte_lo, int flags) 420 { 421 422 ASSERT_TABLE_LOCK(); 423 424 /* 425 * Construct a PTE. Default to IMB initially. Valid bit only gets 426 * set when the real pte is set in memory. 427 * 428 * Note: Don't set the valid bit for correct operation of tlb update. 429 */ 430 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) | 431 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API); 432 433 if (flags & PVO_LARGE) 434 pt->pte_hi |= LPTE_BIG; 435 436 pt->pte_lo = pte_lo; 437 } 438 439 static __inline uint64_t 440 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 441 { 442 uint64_t pte_lo; 443 int i; 444 445 if (ma != VM_MEMATTR_DEFAULT) { 446 switch (ma) { 447 case VM_MEMATTR_UNCACHEABLE: 448 return (LPTE_I | LPTE_G); 449 case VM_MEMATTR_WRITE_COMBINING: 450 case VM_MEMATTR_WRITE_BACK: 451 case VM_MEMATTR_PREFETCHABLE: 452 return (LPTE_I); 453 case VM_MEMATTR_WRITE_THROUGH: 454 return (LPTE_W | LPTE_M); 455 } 456 } 457 458 /* 459 * Assume the page is cache inhibited and access is guarded unless 460 * it's in our available memory array. 461 */ 462 pte_lo = LPTE_I | LPTE_G; 463 for (i = 0; i < pregions_sz; i++) { 464 if ((pa >= pregions[i].mr_start) && 465 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 466 pte_lo &= ~(LPTE_I | LPTE_G); 467 pte_lo |= LPTE_M; 468 break; 469 } 470 } 471 472 return pte_lo; 473 } 474 475 /* 476 * Quick sort callout for comparing memory regions. 477 */ 478 static int mr_cmp(const void *a, const void *b); 479 static int om_cmp(const void *a, const void *b); 480 481 static int 482 mr_cmp(const void *a, const void *b) 483 { 484 const struct mem_region *regiona; 485 const struct mem_region *regionb; 486 487 regiona = a; 488 regionb = b; 489 if (regiona->mr_start < regionb->mr_start) 490 return (-1); 491 else if (regiona->mr_start > regionb->mr_start) 492 return (1); 493 else 494 return (0); 495 } 496 497 static int 498 om_cmp(const void *a, const void *b) 499 { 500 const struct ofw_map *mapa; 501 const struct ofw_map *mapb; 502 503 mapa = a; 504 mapb = b; 505 if (mapa->om_pa_hi < mapb->om_pa_hi) 506 return (-1); 507 else if (mapa->om_pa_hi > mapb->om_pa_hi) 508 return (1); 509 else if (mapa->om_pa_lo < mapb->om_pa_lo) 510 return (-1); 511 else if (mapa->om_pa_lo > mapb->om_pa_lo) 512 return (1); 513 else 514 return (0); 515 } 516 517 static void 518 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 519 { 520 struct ofw_map translations[sz/sizeof(struct ofw_map)]; 521 register_t msr; 522 vm_offset_t off; 523 vm_paddr_t pa_base; 524 int i; 525 526 bzero(translations, sz); 527 if (OF_getprop(mmu, "translations", translations, sz) == -1) 528 panic("moea64_bootstrap: can't get ofw translations"); 529 530 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 531 sz /= sizeof(*translations); 532 qsort(translations, sz, sizeof (*translations), om_cmp); 533 534 for (i = 0; i < sz; i++) { 535 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 536 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va, 537 translations[i].om_len); 538 539 if (translations[i].om_pa_lo % PAGE_SIZE) 540 panic("OFW translation not page-aligned!"); 541 542 pa_base = translations[i].om_pa_lo; 543 544 #ifdef __powerpc64__ 545 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32; 546 #else 547 if (translations[i].om_pa_hi) 548 panic("OFW translations above 32-bit boundary!"); 549 #endif 550 551 /* Now enter the pages for this mapping */ 552 553 DISABLE_TRANS(msr); 554 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 555 if (moea64_pvo_find_va(kernel_pmap, 556 translations[i].om_va + off) != NULL) 557 continue; 558 559 moea64_kenter(mmup, translations[i].om_va + off, 560 pa_base + off); 561 } 562 ENABLE_TRANS(msr); 563 } 564 } 565 566 #ifdef __powerpc64__ 567 static void 568 moea64_probe_large_page(void) 569 { 570 uint16_t pvr = mfpvr() >> 16; 571 572 switch (pvr) { 573 case IBM970: 574 case IBM970FX: 575 case IBM970MP: 576 powerpc_sync(); isync(); 577 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 578 powerpc_sync(); isync(); 579 580 /* FALLTHROUGH */ 581 case IBMCELLBE: 582 moea64_large_page_size = 0x1000000; /* 16 MB */ 583 moea64_large_page_shift = 24; 584 break; 585 default: 586 moea64_large_page_size = 0; 587 } 588 589 moea64_large_page_mask = moea64_large_page_size - 1; 590 } 591 592 static void 593 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 594 { 595 struct slb *cache; 596 struct slb entry; 597 uint64_t esid, slbe; 598 uint64_t i; 599 600 cache = PCPU_GET(slb); 601 esid = va >> ADDR_SR_SHFT; 602 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 603 604 for (i = 0; i < 64; i++) { 605 if (cache[i].slbe == (slbe | i)) 606 return; 607 } 608 609 entry.slbe = slbe; 610 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 611 if (large) 612 entry.slbv |= SLBV_L; 613 614 slb_insert_kernel(entry.slbe, entry.slbv); 615 } 616 #endif 617 618 static void 619 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 620 vm_offset_t kernelend) 621 { 622 register_t msr; 623 vm_paddr_t pa; 624 vm_offset_t size, off; 625 uint64_t pte_lo; 626 int i; 627 628 if (moea64_large_page_size == 0) 629 hw_direct_map = 0; 630 631 DISABLE_TRANS(msr); 632 if (hw_direct_map) { 633 PMAP_LOCK(kernel_pmap); 634 for (i = 0; i < pregions_sz; i++) { 635 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 636 pregions[i].mr_size; pa += moea64_large_page_size) { 637 pte_lo = LPTE_M; 638 639 /* 640 * Set memory access as guarded if prefetch within 641 * the page could exit the available physmem area. 642 */ 643 if (pa & moea64_large_page_mask) { 644 pa &= moea64_large_page_mask; 645 pte_lo |= LPTE_G; 646 } 647 if (pa + moea64_large_page_size > 648 pregions[i].mr_start + pregions[i].mr_size) 649 pte_lo |= LPTE_G; 650 651 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone, 652 &moea64_pvo_kunmanaged, pa, pa, 653 pte_lo, PVO_WIRED | PVO_LARGE); 654 } 655 } 656 PMAP_UNLOCK(kernel_pmap); 657 } else { 658 size = sizeof(struct pvo_head) * moea64_pteg_count; 659 off = (vm_offset_t)(moea64_pvo_table); 660 for (pa = off; pa < off + size; pa += PAGE_SIZE) 661 moea64_kenter(mmup, pa, pa); 662 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry); 663 off = (vm_offset_t)(moea64_bpvo_pool); 664 for (pa = off; pa < off + size; pa += PAGE_SIZE) 665 moea64_kenter(mmup, pa, pa); 666 667 /* 668 * Map certain important things, like ourselves. 669 * 670 * NOTE: We do not map the exception vector space. That code is 671 * used only in real mode, and leaving it unmapped allows us to 672 * catch NULL pointer deferences, instead of making NULL a valid 673 * address. 674 */ 675 676 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 677 pa += PAGE_SIZE) 678 moea64_kenter(mmup, pa, pa); 679 } 680 ENABLE_TRANS(msr); 681 } 682 683 void 684 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 685 { 686 int i, j; 687 vm_size_t physsz, hwphyssz; 688 689 #ifndef __powerpc64__ 690 /* We don't have a direct map since there is no BAT */ 691 hw_direct_map = 0; 692 693 /* Make sure battable is zero, since we have no BAT */ 694 for (i = 0; i < 16; i++) { 695 battable[i].batu = 0; 696 battable[i].batl = 0; 697 } 698 #else 699 moea64_probe_large_page(); 700 701 /* Use a direct map if we have large page support */ 702 if (moea64_large_page_size > 0) 703 hw_direct_map = 1; 704 else 705 hw_direct_map = 0; 706 #endif 707 708 /* Get physical memory regions from firmware */ 709 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 710 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 711 712 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 713 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 714 panic("moea64_bootstrap: phys_avail too small"); 715 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 716 phys_avail_count = 0; 717 physsz = 0; 718 hwphyssz = 0; 719 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 720 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 721 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 722 regions[i].mr_start + regions[i].mr_size, 723 regions[i].mr_size); 724 if (hwphyssz != 0 && 725 (physsz + regions[i].mr_size) >= hwphyssz) { 726 if (physsz < hwphyssz) { 727 phys_avail[j] = regions[i].mr_start; 728 phys_avail[j + 1] = regions[i].mr_start + 729 hwphyssz - physsz; 730 physsz = hwphyssz; 731 phys_avail_count++; 732 } 733 break; 734 } 735 phys_avail[j] = regions[i].mr_start; 736 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 737 phys_avail_count++; 738 physsz += regions[i].mr_size; 739 } 740 741 /* Check for overlap with the kernel and exception vectors */ 742 for (j = 0; j < 2*phys_avail_count; j+=2) { 743 if (phys_avail[j] < EXC_LAST) 744 phys_avail[j] += EXC_LAST; 745 746 if (kernelstart >= phys_avail[j] && 747 kernelstart < phys_avail[j+1]) { 748 if (kernelend < phys_avail[j+1]) { 749 phys_avail[2*phys_avail_count] = 750 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 751 phys_avail[2*phys_avail_count + 1] = 752 phys_avail[j+1]; 753 phys_avail_count++; 754 } 755 756 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 757 } 758 759 if (kernelend >= phys_avail[j] && 760 kernelend < phys_avail[j+1]) { 761 if (kernelstart > phys_avail[j]) { 762 phys_avail[2*phys_avail_count] = phys_avail[j]; 763 phys_avail[2*phys_avail_count + 1] = 764 kernelstart & ~PAGE_MASK; 765 phys_avail_count++; 766 } 767 768 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 769 } 770 } 771 772 physmem = btoc(physsz); 773 774 #ifdef PTEGCOUNT 775 moea64_pteg_count = PTEGCOUNT; 776 #else 777 moea64_pteg_count = 0x1000; 778 779 while (moea64_pteg_count < physmem) 780 moea64_pteg_count <<= 1; 781 782 moea64_pteg_count >>= 1; 783 #endif /* PTEGCOUNT */ 784 } 785 786 void 787 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 788 { 789 vm_size_t size; 790 register_t msr; 791 int i; 792 793 /* 794 * Set PTEG mask 795 */ 796 moea64_pteg_mask = moea64_pteg_count - 1; 797 798 /* 799 * Allocate pv/overflow lists. 800 */ 801 size = sizeof(struct pvo_head) * moea64_pteg_count; 802 803 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size, 804 PAGE_SIZE); 805 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table); 806 807 DISABLE_TRANS(msr); 808 for (i = 0; i < moea64_pteg_count; i++) 809 LIST_INIT(&moea64_pvo_table[i]); 810 ENABLE_TRANS(msr); 811 812 /* 813 * Initialize the lock that synchronizes access to the pteg and pvo 814 * tables. 815 */ 816 mtx_init(&moea64_table_mutex, "pmap table", NULL, MTX_DEF | 817 MTX_RECURSE); 818 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 819 820 /* 821 * Initialise the unmanaged pvo pool. 822 */ 823 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 824 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 825 moea64_bpvo_pool_index = 0; 826 827 /* 828 * Make sure kernel vsid is allocated as well as VSID 0. 829 */ 830 #ifndef __powerpc64__ 831 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 832 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 833 moea64_vsid_bitmap[0] |= 1; 834 #endif 835 836 /* 837 * Initialize the kernel pmap (which is statically allocated). 838 */ 839 #ifdef __powerpc64__ 840 for (i = 0; i < 64; i++) { 841 pcpup->pc_slb[i].slbv = 0; 842 pcpup->pc_slb[i].slbe = 0; 843 } 844 #else 845 for (i = 0; i < 16; i++) 846 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 847 #endif 848 849 kernel_pmap->pmap_phys = kernel_pmap; 850 kernel_pmap->pm_active = ~0; 851 852 PMAP_LOCK_INIT(kernel_pmap); 853 854 /* 855 * Now map in all the other buffers we allocated earlier 856 */ 857 858 moea64_setup_direct_map(mmup, kernelstart, kernelend); 859 } 860 861 void 862 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 863 { 864 ihandle_t mmui; 865 phandle_t chosen; 866 phandle_t mmu; 867 size_t sz; 868 int i; 869 vm_offset_t pa, va; 870 void *dpcpu; 871 872 /* 873 * Set up the Open Firmware pmap and add its mappings if not in real 874 * mode. 875 */ 876 877 chosen = OF_finddevice("/chosen"); 878 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 879 mmu = OF_instance_to_package(mmui); 880 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1) 881 sz = 0; 882 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 883 panic("moea64_bootstrap: too many ofw translations"); 884 885 if (sz > 0) 886 moea64_add_ofw_mappings(mmup, mmu, sz); 887 } 888 889 /* 890 * Calculate the last available physical address. 891 */ 892 for (i = 0; phys_avail[i + 2] != 0; i += 2) 893 ; 894 Maxmem = powerpc_btop(phys_avail[i + 1]); 895 896 /* 897 * Initialize MMU and remap early physical mappings 898 */ 899 MMU_CPU_BOOTSTRAP(mmup,0); 900 mtmsr(mfmsr() | PSL_DR | PSL_IR); isync(); 901 pmap_bootstrapped++; 902 bs_remap_earlyboot(); 903 904 /* 905 * Set the start and end of kva. 906 */ 907 virtual_avail = VM_MIN_KERNEL_ADDRESS; 908 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 909 910 /* 911 * Map the entire KVA range into the SLB. We must not fault there. 912 */ 913 #ifdef __powerpc64__ 914 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 915 moea64_bootstrap_slb_prefault(va, 0); 916 #endif 917 918 /* 919 * Figure out how far we can extend virtual_end into segment 16 920 * without running into existing mappings. Segment 16 is guaranteed 921 * to contain neither RAM nor devices (at least on Apple hardware), 922 * but will generally contain some OFW mappings we should not 923 * step on. 924 */ 925 926 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 927 PMAP_LOCK(kernel_pmap); 928 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 929 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 930 virtual_end += PAGE_SIZE; 931 PMAP_UNLOCK(kernel_pmap); 932 #endif 933 934 /* 935 * Allocate a kernel stack with a guard page for thread0 and map it 936 * into the kernel page map. 937 */ 938 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 939 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 940 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 941 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 942 thread0.td_kstack = va; 943 thread0.td_kstack_pages = KSTACK_PAGES; 944 for (i = 0; i < KSTACK_PAGES; i++) { 945 moea64_kenter(mmup, va, pa); 946 pa += PAGE_SIZE; 947 va += PAGE_SIZE; 948 } 949 950 /* 951 * Allocate virtual address space for the message buffer. 952 */ 953 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 954 msgbufp = (struct msgbuf *)virtual_avail; 955 va = virtual_avail; 956 virtual_avail += round_page(msgbufsize); 957 while (va < virtual_avail) { 958 moea64_kenter(mmup, va, pa); 959 pa += PAGE_SIZE; 960 va += PAGE_SIZE; 961 } 962 963 /* 964 * Allocate virtual address space for the dynamic percpu area. 965 */ 966 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 967 dpcpu = (void *)virtual_avail; 968 va = virtual_avail; 969 virtual_avail += DPCPU_SIZE; 970 while (va < virtual_avail) { 971 moea64_kenter(mmup, va, pa); 972 pa += PAGE_SIZE; 973 va += PAGE_SIZE; 974 } 975 dpcpu_init(dpcpu, 0); 976 977 /* 978 * Allocate some things for page zeroing. We put this directly 979 * in the page table, marked with LPTE_LOCKED, to avoid any 980 * of the PVO book-keeping or other parts of the VM system 981 * from even knowing that this hack exists. 982 */ 983 984 if (!hw_direct_map) { 985 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 986 MTX_DEF); 987 for (i = 0; i < 2; i++) { 988 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 989 virtual_end -= PAGE_SIZE; 990 991 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 992 993 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 994 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 995 LOCK_TABLE(); 996 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE( 997 mmup, moea64_scratchpage_pvo[i]); 998 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi 999 |= LPTE_LOCKED; 1000 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i], 1001 &moea64_scratchpage_pvo[i]->pvo_pte.lpte, 1002 moea64_scratchpage_pvo[i]->pvo_vpn); 1003 UNLOCK_TABLE(); 1004 } 1005 } 1006 } 1007 1008 /* 1009 * Activate a user pmap. The pmap must be activated before its address 1010 * space can be accessed in any way. 1011 */ 1012 void 1013 moea64_activate(mmu_t mmu, struct thread *td) 1014 { 1015 pmap_t pm; 1016 1017 pm = &td->td_proc->p_vmspace->vm_pmap; 1018 pm->pm_active |= PCPU_GET(cpumask); 1019 1020 #ifdef __powerpc64__ 1021 PCPU_SET(userslb, pm->pm_slb); 1022 #else 1023 PCPU_SET(curpmap, pm->pmap_phys); 1024 #endif 1025 } 1026 1027 void 1028 moea64_deactivate(mmu_t mmu, struct thread *td) 1029 { 1030 pmap_t pm; 1031 1032 pm = &td->td_proc->p_vmspace->vm_pmap; 1033 pm->pm_active &= ~(PCPU_GET(cpumask)); 1034 #ifdef __powerpc64__ 1035 PCPU_SET(userslb, NULL); 1036 #else 1037 PCPU_SET(curpmap, NULL); 1038 #endif 1039 } 1040 1041 void 1042 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1043 { 1044 struct pvo_entry *pvo; 1045 uintptr_t pt; 1046 uint64_t vsid; 1047 int i, ptegidx; 1048 1049 PMAP_LOCK(pm); 1050 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 1051 1052 if (pvo != NULL) { 1053 LOCK_TABLE(); 1054 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1055 1056 if (wired) { 1057 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1058 pm->pm_stats.wired_count++; 1059 pvo->pvo_vaddr |= PVO_WIRED; 1060 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 1061 } else { 1062 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1063 pm->pm_stats.wired_count--; 1064 pvo->pvo_vaddr &= ~PVO_WIRED; 1065 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED; 1066 } 1067 1068 if (pt != -1) { 1069 /* Update wiring flag in page table. */ 1070 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1071 pvo->pvo_vpn); 1072 } else if (wired) { 1073 /* 1074 * If we are wiring the page, and it wasn't in the 1075 * page table before, add it. 1076 */ 1077 vsid = PVO_VSID(pvo); 1078 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo), 1079 pvo->pvo_vaddr & PVO_LARGE); 1080 1081 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 1082 1083 if (i >= 0) { 1084 PVO_PTEGIDX_CLR(pvo); 1085 PVO_PTEGIDX_SET(pvo, i); 1086 } 1087 } 1088 1089 UNLOCK_TABLE(); 1090 } 1091 PMAP_UNLOCK(pm); 1092 } 1093 1094 /* 1095 * This goes through and sets the physical address of our 1096 * special scratch PTE to the PA we want to zero or copy. Because 1097 * of locking issues (this can get called in pvo_enter() by 1098 * the UMA allocator), we can't use most other utility functions here 1099 */ 1100 1101 static __inline 1102 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1103 1104 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1105 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1106 1107 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &= 1108 ~(LPTE_WIMG | LPTE_RPGN); 1109 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |= 1110 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1111 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which], 1112 &moea64_scratchpage_pvo[which]->pvo_pte.lpte, 1113 moea64_scratchpage_pvo[which]->pvo_vpn); 1114 isync(); 1115 } 1116 1117 void 1118 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1119 { 1120 vm_offset_t dst; 1121 vm_offset_t src; 1122 1123 dst = VM_PAGE_TO_PHYS(mdst); 1124 src = VM_PAGE_TO_PHYS(msrc); 1125 1126 if (hw_direct_map) { 1127 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1128 } else { 1129 mtx_lock(&moea64_scratchpage_mtx); 1130 1131 moea64_set_scratchpage_pa(mmu, 0, src); 1132 moea64_set_scratchpage_pa(mmu, 1, dst); 1133 1134 kcopy((void *)moea64_scratchpage_va[0], 1135 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1136 1137 mtx_unlock(&moea64_scratchpage_mtx); 1138 } 1139 } 1140 1141 void 1142 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1143 { 1144 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1145 1146 if (!moea64_initialized) 1147 panic("moea64_zero_page: can't zero pa %#" PRIxPTR, pa); 1148 if (size + off > PAGE_SIZE) 1149 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1150 1151 if (hw_direct_map) { 1152 bzero((caddr_t)pa + off, size); 1153 } else { 1154 mtx_lock(&moea64_scratchpage_mtx); 1155 moea64_set_scratchpage_pa(mmu, 0, pa); 1156 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1157 mtx_unlock(&moea64_scratchpage_mtx); 1158 } 1159 } 1160 1161 /* 1162 * Zero a page of physical memory by temporarily mapping it 1163 */ 1164 void 1165 moea64_zero_page(mmu_t mmu, vm_page_t m) 1166 { 1167 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1168 vm_offset_t va, off; 1169 1170 if (!moea64_initialized) 1171 panic("moea64_zero_page: can't zero pa %#zx", pa); 1172 1173 if (!hw_direct_map) { 1174 mtx_lock(&moea64_scratchpage_mtx); 1175 1176 moea64_set_scratchpage_pa(mmu, 0, pa); 1177 va = moea64_scratchpage_va[0]; 1178 } else { 1179 va = pa; 1180 } 1181 1182 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1183 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1184 1185 if (!hw_direct_map) 1186 mtx_unlock(&moea64_scratchpage_mtx); 1187 } 1188 1189 void 1190 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1191 { 1192 1193 moea64_zero_page(mmu, m); 1194 } 1195 1196 /* 1197 * Map the given physical page at the specified virtual address in the 1198 * target pmap with the protection requested. If specified the page 1199 * will be wired down. 1200 */ 1201 void 1202 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1203 vm_prot_t prot, boolean_t wired) 1204 { 1205 1206 vm_page_lock_queues(); 1207 PMAP_LOCK(pmap); 1208 moea64_enter_locked(mmu, pmap, va, m, prot, wired); 1209 vm_page_unlock_queues(); 1210 PMAP_UNLOCK(pmap); 1211 } 1212 1213 /* 1214 * Map the given physical page at the specified virtual address in the 1215 * target pmap with the protection requested. If specified the page 1216 * will be wired down. 1217 * 1218 * The page queues and pmap must be locked. 1219 */ 1220 1221 static void 1222 moea64_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1223 vm_prot_t prot, boolean_t wired) 1224 { 1225 struct pvo_head *pvo_head; 1226 uma_zone_t zone; 1227 vm_page_t pg; 1228 uint64_t pte_lo; 1229 u_int pvo_flags; 1230 int error; 1231 1232 if (!moea64_initialized) { 1233 pvo_head = &moea64_pvo_kunmanaged; 1234 pg = NULL; 1235 zone = moea64_upvo_zone; 1236 pvo_flags = 0; 1237 } else { 1238 pvo_head = vm_page_to_pvoh(m); 1239 pg = m; 1240 zone = moea64_mpvo_zone; 1241 pvo_flags = PVO_MANAGED; 1242 } 1243 1244 if (pmap_bootstrapped) 1245 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1246 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1247 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1248 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1249 ("moea64_enter_locked: page %p is not busy", m)); 1250 1251 /* XXX change the pvo head for fake pages */ 1252 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1253 pvo_flags &= ~PVO_MANAGED; 1254 pvo_head = &moea64_pvo_kunmanaged; 1255 zone = moea64_upvo_zone; 1256 } 1257 1258 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1259 1260 if (prot & VM_PROT_WRITE) { 1261 pte_lo |= LPTE_BW; 1262 if (pmap_bootstrapped && 1263 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1264 vm_page_flag_set(m, PG_WRITEABLE); 1265 } else 1266 pte_lo |= LPTE_BR; 1267 1268 if ((prot & VM_PROT_EXECUTE) == 0) 1269 pte_lo |= LPTE_NOEXEC; 1270 1271 if (wired) 1272 pvo_flags |= PVO_WIRED; 1273 1274 if ((m->flags & PG_FICTITIOUS) != 0) 1275 pvo_flags |= PVO_FAKE; 1276 1277 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va, 1278 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags); 1279 1280 /* 1281 * Flush the page from the instruction cache if this page is 1282 * mapped executable and cacheable. 1283 */ 1284 if ((pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) 1285 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1286 } 1287 1288 static void 1289 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1290 vm_size_t sz) 1291 { 1292 1293 /* 1294 * This is much trickier than on older systems because 1295 * we can't sync the icache on physical addresses directly 1296 * without a direct map. Instead we check a couple of cases 1297 * where the memory is already mapped in and, failing that, 1298 * use the same trick we use for page zeroing to create 1299 * a temporary mapping for this physical address. 1300 */ 1301 1302 if (!pmap_bootstrapped) { 1303 /* 1304 * If PMAP is not bootstrapped, we are likely to be 1305 * in real mode. 1306 */ 1307 __syncicache((void *)pa, sz); 1308 } else if (pmap == kernel_pmap) { 1309 __syncicache((void *)va, sz); 1310 } else if (hw_direct_map) { 1311 __syncicache((void *)pa, sz); 1312 } else { 1313 /* Use the scratch page to set up a temp mapping */ 1314 1315 mtx_lock(&moea64_scratchpage_mtx); 1316 1317 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1318 __syncicache((void *)(moea64_scratchpage_va[1] + 1319 (va & ADDR_POFF)), sz); 1320 1321 mtx_unlock(&moea64_scratchpage_mtx); 1322 } 1323 } 1324 1325 /* 1326 * Maps a sequence of resident pages belonging to the same object. 1327 * The sequence begins with the given page m_start. This page is 1328 * mapped at the given virtual address start. Each subsequent page is 1329 * mapped at a virtual address that is offset from start by the same 1330 * amount as the page is offset from m_start within the object. The 1331 * last page in the sequence is the page with the largest offset from 1332 * m_start that can be mapped at a virtual address less than the given 1333 * virtual address end. Not every virtual page between start and end 1334 * is mapped; only those for which a resident page exists with the 1335 * corresponding offset from m_start are mapped. 1336 */ 1337 void 1338 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1339 vm_page_t m_start, vm_prot_t prot) 1340 { 1341 vm_page_t m; 1342 vm_pindex_t diff, psize; 1343 1344 psize = atop(end - start); 1345 m = m_start; 1346 vm_page_lock_queues(); 1347 PMAP_LOCK(pm); 1348 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1349 moea64_enter_locked(mmu, pm, start + ptoa(diff), m, prot & 1350 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1351 m = TAILQ_NEXT(m, listq); 1352 } 1353 vm_page_unlock_queues(); 1354 PMAP_UNLOCK(pm); 1355 } 1356 1357 void 1358 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1359 vm_prot_t prot) 1360 { 1361 1362 vm_page_lock_queues(); 1363 PMAP_LOCK(pm); 1364 moea64_enter_locked(mmu, pm, va, m, 1365 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1366 vm_page_unlock_queues(); 1367 PMAP_UNLOCK(pm); 1368 } 1369 1370 vm_paddr_t 1371 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1372 { 1373 struct pvo_entry *pvo; 1374 vm_paddr_t pa; 1375 1376 PMAP_LOCK(pm); 1377 pvo = moea64_pvo_find_va(pm, va); 1378 if (pvo == NULL) 1379 pa = 0; 1380 else 1381 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | 1382 (va - PVO_VADDR(pvo)); 1383 PMAP_UNLOCK(pm); 1384 return (pa); 1385 } 1386 1387 /* 1388 * Atomically extract and hold the physical page with the given 1389 * pmap and virtual address pair if that mapping permits the given 1390 * protection. 1391 */ 1392 vm_page_t 1393 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1394 { 1395 struct pvo_entry *pvo; 1396 vm_page_t m; 1397 vm_paddr_t pa; 1398 1399 m = NULL; 1400 pa = 0; 1401 PMAP_LOCK(pmap); 1402 retry: 1403 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1404 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) && 1405 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW || 1406 (prot & VM_PROT_WRITE) == 0)) { 1407 if (vm_page_pa_tryrelock(pmap, 1408 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa)) 1409 goto retry; 1410 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 1411 vm_page_hold(m); 1412 } 1413 PA_UNLOCK_COND(pa); 1414 PMAP_UNLOCK(pmap); 1415 return (m); 1416 } 1417 1418 static mmu_t installed_mmu; 1419 1420 static void * 1421 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1422 { 1423 /* 1424 * This entire routine is a horrible hack to avoid bothering kmem 1425 * for new KVA addresses. Because this can get called from inside 1426 * kmem allocation routines, calling kmem for a new address here 1427 * can lead to multiply locking non-recursive mutexes. 1428 */ 1429 static vm_pindex_t color; 1430 vm_offset_t va; 1431 1432 vm_page_t m; 1433 int pflags, needed_lock; 1434 1435 *flags = UMA_SLAB_PRIV; 1436 needed_lock = !PMAP_LOCKED(kernel_pmap); 1437 1438 if (needed_lock) 1439 PMAP_LOCK(kernel_pmap); 1440 1441 if ((wait & (M_NOWAIT|M_USE_RESERVE)) == M_NOWAIT) 1442 pflags = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED; 1443 else 1444 pflags = VM_ALLOC_SYSTEM | VM_ALLOC_WIRED; 1445 if (wait & M_ZERO) 1446 pflags |= VM_ALLOC_ZERO; 1447 1448 for (;;) { 1449 m = vm_page_alloc(NULL, color++, pflags | VM_ALLOC_NOOBJ); 1450 if (m == NULL) { 1451 if (wait & M_NOWAIT) 1452 return (NULL); 1453 VM_WAIT; 1454 } else 1455 break; 1456 } 1457 1458 va = VM_PAGE_TO_PHYS(m); 1459 1460 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone, 1461 &moea64_pvo_kunmanaged, va, VM_PAGE_TO_PHYS(m), LPTE_M, 1462 PVO_WIRED | PVO_BOOTSTRAP); 1463 1464 if (needed_lock) 1465 PMAP_UNLOCK(kernel_pmap); 1466 1467 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1468 bzero((void *)va, PAGE_SIZE); 1469 1470 return (void *)va; 1471 } 1472 1473 void 1474 moea64_init(mmu_t mmu) 1475 { 1476 1477 CTR0(KTR_PMAP, "moea64_init"); 1478 1479 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1480 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1481 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1482 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1483 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1484 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1485 1486 if (!hw_direct_map) { 1487 installed_mmu = mmu; 1488 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc); 1489 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc); 1490 } 1491 1492 moea64_initialized = TRUE; 1493 } 1494 1495 boolean_t 1496 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1497 { 1498 1499 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1500 ("moea64_is_referenced: page %p is not managed", m)); 1501 return (moea64_query_bit(mmu, m, PTE_REF)); 1502 } 1503 1504 boolean_t 1505 moea64_is_modified(mmu_t mmu, vm_page_t m) 1506 { 1507 1508 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1509 ("moea64_is_modified: page %p is not managed", m)); 1510 1511 /* 1512 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1513 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1514 * is clear, no PTEs can have LPTE_CHG set. 1515 */ 1516 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1517 if ((m->oflags & VPO_BUSY) == 0 && 1518 (m->flags & PG_WRITEABLE) == 0) 1519 return (FALSE); 1520 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1521 } 1522 1523 boolean_t 1524 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1525 { 1526 struct pvo_entry *pvo; 1527 boolean_t rv; 1528 1529 PMAP_LOCK(pmap); 1530 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1531 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0; 1532 PMAP_UNLOCK(pmap); 1533 return (rv); 1534 } 1535 1536 void 1537 moea64_clear_reference(mmu_t mmu, vm_page_t m) 1538 { 1539 1540 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1541 ("moea64_clear_reference: page %p is not managed", m)); 1542 moea64_clear_bit(mmu, m, LPTE_REF); 1543 } 1544 1545 void 1546 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1547 { 1548 1549 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1550 ("moea64_clear_modify: page %p is not managed", m)); 1551 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1552 KASSERT((m->oflags & VPO_BUSY) == 0, 1553 ("moea64_clear_modify: page %p is busy", m)); 1554 1555 /* 1556 * If the page is not PG_WRITEABLE, then no PTEs can have LPTE_CHG 1557 * set. If the object containing the page is locked and the page is 1558 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1559 */ 1560 if ((m->flags & PG_WRITEABLE) == 0) 1561 return; 1562 moea64_clear_bit(mmu, m, LPTE_CHG); 1563 } 1564 1565 /* 1566 * Clear the write and modified bits in each of the given page's mappings. 1567 */ 1568 void 1569 moea64_remove_write(mmu_t mmu, vm_page_t m) 1570 { 1571 struct pvo_entry *pvo; 1572 uintptr_t pt; 1573 pmap_t pmap; 1574 uint64_t lo; 1575 1576 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1577 ("moea64_remove_write: page %p is not managed", m)); 1578 1579 /* 1580 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1581 * another thread while the object is locked. Thus, if PG_WRITEABLE 1582 * is clear, no page table entries need updating. 1583 */ 1584 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1585 if ((m->oflags & VPO_BUSY) == 0 && 1586 (m->flags & PG_WRITEABLE) == 0) 1587 return; 1588 vm_page_lock_queues(); 1589 lo = moea64_attr_fetch(m); 1590 powerpc_sync(); 1591 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1592 pmap = pvo->pvo_pmap; 1593 PMAP_LOCK(pmap); 1594 LOCK_TABLE(); 1595 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) { 1596 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1597 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1598 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1599 if (pt != -1) { 1600 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 1601 lo |= pvo->pvo_pte.lpte.pte_lo; 1602 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG; 1603 MOEA64_PTE_CHANGE(mmu, pt, 1604 &pvo->pvo_pte.lpte, pvo->pvo_vpn); 1605 if (pvo->pvo_pmap == kernel_pmap) 1606 isync(); 1607 } 1608 } 1609 UNLOCK_TABLE(); 1610 PMAP_UNLOCK(pmap); 1611 } 1612 if ((lo & LPTE_CHG) != 0) { 1613 moea64_attr_clear(m, LPTE_CHG); 1614 vm_page_dirty(m); 1615 } 1616 vm_page_flag_clear(m, PG_WRITEABLE); 1617 vm_page_unlock_queues(); 1618 } 1619 1620 /* 1621 * moea64_ts_referenced: 1622 * 1623 * Return a count of reference bits for a page, clearing those bits. 1624 * It is not necessary for every reference bit to be cleared, but it 1625 * is necessary that 0 only be returned when there are truly no 1626 * reference bits set. 1627 * 1628 * XXX: The exact number of bits to check and clear is a matter that 1629 * should be tested and standardized at some point in the future for 1630 * optimal aging of shared pages. 1631 */ 1632 boolean_t 1633 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1634 { 1635 1636 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1637 ("moea64_ts_referenced: page %p is not managed", m)); 1638 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1639 } 1640 1641 /* 1642 * Modify the WIMG settings of all mappings for a page. 1643 */ 1644 void 1645 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1646 { 1647 struct pvo_entry *pvo; 1648 struct pvo_head *pvo_head; 1649 uintptr_t pt; 1650 pmap_t pmap; 1651 uint64_t lo; 1652 1653 if (m->flags & PG_FICTITIOUS) { 1654 m->md.mdpg_cache_attrs = ma; 1655 return; 1656 } 1657 1658 vm_page_lock_queues(); 1659 pvo_head = vm_page_to_pvoh(m); 1660 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1661 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1662 pmap = pvo->pvo_pmap; 1663 PMAP_LOCK(pmap); 1664 LOCK_TABLE(); 1665 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1666 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG; 1667 pvo->pvo_pte.lpte.pte_lo |= lo; 1668 if (pt != -1) { 1669 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1670 pvo->pvo_vpn); 1671 if (pvo->pvo_pmap == kernel_pmap) 1672 isync(); 1673 } 1674 UNLOCK_TABLE(); 1675 PMAP_UNLOCK(pmap); 1676 } 1677 m->md.mdpg_cache_attrs = ma; 1678 vm_page_unlock_queues(); 1679 } 1680 1681 /* 1682 * Map a wired page into kernel virtual address space. 1683 */ 1684 void 1685 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1686 { 1687 uint64_t pte_lo; 1688 int error; 1689 1690 pte_lo = moea64_calc_wimg(pa, ma); 1691 1692 PMAP_LOCK(kernel_pmap); 1693 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone, 1694 &moea64_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1695 1696 if (error != 0 && error != ENOENT) 1697 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1698 pa, error); 1699 1700 /* 1701 * Flush the memory from the instruction cache. 1702 */ 1703 if ((pte_lo & (LPTE_I | LPTE_G)) == 0) 1704 __syncicache((void *)va, PAGE_SIZE); 1705 PMAP_UNLOCK(kernel_pmap); 1706 } 1707 1708 void 1709 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1710 { 1711 1712 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1713 } 1714 1715 /* 1716 * Extract the physical page address associated with the given kernel virtual 1717 * address. 1718 */ 1719 vm_offset_t 1720 moea64_kextract(mmu_t mmu, vm_offset_t va) 1721 { 1722 struct pvo_entry *pvo; 1723 vm_paddr_t pa; 1724 1725 /* 1726 * Shortcut the direct-mapped case when applicable. We never put 1727 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1728 */ 1729 if (va < VM_MIN_KERNEL_ADDRESS) 1730 return (va); 1731 1732 PMAP_LOCK(kernel_pmap); 1733 pvo = moea64_pvo_find_va(kernel_pmap, va); 1734 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1735 va)); 1736 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) + (va - PVO_VADDR(pvo)); 1737 PMAP_UNLOCK(kernel_pmap); 1738 return (pa); 1739 } 1740 1741 /* 1742 * Remove a wired page from kernel virtual address space. 1743 */ 1744 void 1745 moea64_kremove(mmu_t mmu, vm_offset_t va) 1746 { 1747 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1748 } 1749 1750 /* 1751 * Map a range of physical addresses into kernel virtual address space. 1752 * 1753 * The value passed in *virt is a suggested virtual address for the mapping. 1754 * Architectures which can support a direct-mapped physical to virtual region 1755 * can return the appropriate address within that region, leaving '*virt' 1756 * unchanged. We cannot and therefore do not; *virt is updated with the 1757 * first usable address after the mapped region. 1758 */ 1759 vm_offset_t 1760 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1761 vm_offset_t pa_end, int prot) 1762 { 1763 vm_offset_t sva, va; 1764 1765 sva = *virt; 1766 va = sva; 1767 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1768 moea64_kenter(mmu, va, pa_start); 1769 *virt = va; 1770 1771 return (sva); 1772 } 1773 1774 /* 1775 * Returns true if the pmap's pv is one of the first 1776 * 16 pvs linked to from this page. This count may 1777 * be changed upwards or downwards in the future; it 1778 * is only necessary that true be returned for a small 1779 * subset of pmaps for proper page aging. 1780 */ 1781 boolean_t 1782 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1783 { 1784 int loops; 1785 struct pvo_entry *pvo; 1786 boolean_t rv; 1787 1788 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1789 ("moea64_page_exists_quick: page %p is not managed", m)); 1790 loops = 0; 1791 rv = FALSE; 1792 vm_page_lock_queues(); 1793 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1794 if (pvo->pvo_pmap == pmap) { 1795 rv = TRUE; 1796 break; 1797 } 1798 if (++loops >= 16) 1799 break; 1800 } 1801 vm_page_unlock_queues(); 1802 return (rv); 1803 } 1804 1805 /* 1806 * Return the number of managed mappings to the given physical page 1807 * that are wired. 1808 */ 1809 int 1810 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1811 { 1812 struct pvo_entry *pvo; 1813 int count; 1814 1815 count = 0; 1816 if ((m->flags & PG_FICTITIOUS) != 0) 1817 return (count); 1818 vm_page_lock_queues(); 1819 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1820 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1821 count++; 1822 vm_page_unlock_queues(); 1823 return (count); 1824 } 1825 1826 static uintptr_t moea64_vsidcontext; 1827 1828 uintptr_t 1829 moea64_get_unique_vsid(void) { 1830 u_int entropy; 1831 register_t hash; 1832 uint32_t mask; 1833 int i; 1834 1835 entropy = 0; 1836 __asm __volatile("mftb %0" : "=r"(entropy)); 1837 1838 mtx_lock(&moea64_slb_mutex); 1839 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1840 u_int n; 1841 1842 /* 1843 * Create a new value by mutiplying by a prime and adding in 1844 * entropy from the timebase register. This is to make the 1845 * VSID more random so that the PT hash function collides 1846 * less often. (Note that the prime casues gcc to do shifts 1847 * instead of a multiply.) 1848 */ 1849 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1850 hash = moea64_vsidcontext & (NVSIDS - 1); 1851 if (hash == 0) /* 0 is special, avoid it */ 1852 continue; 1853 n = hash >> 5; 1854 mask = 1 << (hash & (VSID_NBPW - 1)); 1855 hash = (moea64_vsidcontext & VSID_HASHMASK); 1856 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1857 /* anything free in this bucket? */ 1858 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1859 entropy = (moea64_vsidcontext >> 20); 1860 continue; 1861 } 1862 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1863 mask = 1 << i; 1864 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1865 hash |= i; 1866 } 1867 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1868 ("Allocating in-use VSID %#zx\n", hash)); 1869 moea64_vsid_bitmap[n] |= mask; 1870 mtx_unlock(&moea64_slb_mutex); 1871 return (hash); 1872 } 1873 1874 mtx_unlock(&moea64_slb_mutex); 1875 panic("%s: out of segments",__func__); 1876 } 1877 1878 #ifdef __powerpc64__ 1879 void 1880 moea64_pinit(mmu_t mmu, pmap_t pmap) 1881 { 1882 PMAP_LOCK_INIT(pmap); 1883 1884 pmap->pm_slb_tree_root = slb_alloc_tree(); 1885 pmap->pm_slb = slb_alloc_user_cache(); 1886 pmap->pm_slb_len = 0; 1887 } 1888 #else 1889 void 1890 moea64_pinit(mmu_t mmu, pmap_t pmap) 1891 { 1892 int i; 1893 uint32_t hash; 1894 1895 PMAP_LOCK_INIT(pmap); 1896 1897 if (pmap_bootstrapped) 1898 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1899 (vm_offset_t)pmap); 1900 else 1901 pmap->pmap_phys = pmap; 1902 1903 /* 1904 * Allocate some segment registers for this pmap. 1905 */ 1906 hash = moea64_get_unique_vsid(); 1907 1908 for (i = 0; i < 16; i++) 1909 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1910 1911 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1912 } 1913 #endif 1914 1915 /* 1916 * Initialize the pmap associated with process 0. 1917 */ 1918 void 1919 moea64_pinit0(mmu_t mmu, pmap_t pm) 1920 { 1921 moea64_pinit(mmu, pm); 1922 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1923 } 1924 1925 /* 1926 * Set the physical protection on the specified range of this map as requested. 1927 */ 1928 void 1929 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1930 vm_prot_t prot) 1931 { 1932 struct pvo_entry *pvo; 1933 uintptr_t pt; 1934 1935 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1936 eva, prot); 1937 1938 1939 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1940 ("moea64_protect: non current pmap")); 1941 1942 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1943 moea64_remove(mmu, pm, sva, eva); 1944 return; 1945 } 1946 1947 vm_page_lock_queues(); 1948 PMAP_LOCK(pm); 1949 for (; sva < eva; sva += PAGE_SIZE) { 1950 pvo = moea64_pvo_find_va(pm, sva); 1951 if (pvo == NULL) 1952 continue; 1953 1954 /* 1955 * Grab the PTE pointer before we diddle with the cached PTE 1956 * copy. 1957 */ 1958 LOCK_TABLE(); 1959 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 1960 1961 /* 1962 * Change the protection of the page. 1963 */ 1964 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP; 1965 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR; 1966 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC; 1967 if ((prot & VM_PROT_EXECUTE) == 0) 1968 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC; 1969 1970 /* 1971 * If the PVO is in the page table, update that pte as well. 1972 */ 1973 if (pt != -1) { 1974 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte, 1975 pvo->pvo_vpn); 1976 if ((pvo->pvo_pte.lpte.pte_lo & 1977 (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1978 moea64_syncicache(mmu, pm, sva, 1979 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, 1980 PAGE_SIZE); 1981 } 1982 } 1983 UNLOCK_TABLE(); 1984 } 1985 vm_page_unlock_queues(); 1986 PMAP_UNLOCK(pm); 1987 } 1988 1989 /* 1990 * Map a list of wired pages into kernel virtual address space. This is 1991 * intended for temporary mappings which do not need page modification or 1992 * references recorded. Existing mappings in the region are overwritten. 1993 */ 1994 void 1995 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 1996 { 1997 while (count-- > 0) { 1998 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1999 va += PAGE_SIZE; 2000 m++; 2001 } 2002 } 2003 2004 /* 2005 * Remove page mappings from kernel virtual address space. Intended for 2006 * temporary mappings entered by moea64_qenter. 2007 */ 2008 void 2009 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2010 { 2011 while (count-- > 0) { 2012 moea64_kremove(mmu, va); 2013 va += PAGE_SIZE; 2014 } 2015 } 2016 2017 void 2018 moea64_release_vsid(uint64_t vsid) 2019 { 2020 int idx, mask; 2021 2022 mtx_lock(&moea64_slb_mutex); 2023 idx = vsid & (NVSIDS-1); 2024 mask = 1 << (idx % VSID_NBPW); 2025 idx /= VSID_NBPW; 2026 KASSERT(moea64_vsid_bitmap[idx] & mask, 2027 ("Freeing unallocated VSID %#jx", vsid)); 2028 moea64_vsid_bitmap[idx] &= ~mask; 2029 mtx_unlock(&moea64_slb_mutex); 2030 } 2031 2032 2033 void 2034 moea64_release(mmu_t mmu, pmap_t pmap) 2035 { 2036 2037 /* 2038 * Free segment registers' VSIDs 2039 */ 2040 #ifdef __powerpc64__ 2041 slb_free_tree(pmap); 2042 slb_free_user_cache(pmap->pm_slb); 2043 #else 2044 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2045 2046 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2047 #endif 2048 2049 PMAP_LOCK_DESTROY(pmap); 2050 } 2051 2052 /* 2053 * Remove the given range of addresses from the specified map. 2054 */ 2055 void 2056 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2057 { 2058 struct pvo_entry *pvo; 2059 2060 vm_page_lock_queues(); 2061 PMAP_LOCK(pm); 2062 for (; sva < eva; sva += PAGE_SIZE) { 2063 pvo = moea64_pvo_find_va(pm, sva); 2064 if (pvo != NULL) 2065 moea64_pvo_remove(mmu, pvo); 2066 } 2067 vm_page_unlock_queues(); 2068 PMAP_UNLOCK(pm); 2069 } 2070 2071 /* 2072 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2073 * will reflect changes in pte's back to the vm_page. 2074 */ 2075 void 2076 moea64_remove_all(mmu_t mmu, vm_page_t m) 2077 { 2078 struct pvo_head *pvo_head; 2079 struct pvo_entry *pvo, *next_pvo; 2080 pmap_t pmap; 2081 2082 vm_page_lock_queues(); 2083 pvo_head = vm_page_to_pvoh(m); 2084 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 2085 next_pvo = LIST_NEXT(pvo, pvo_vlink); 2086 2087 MOEA_PVO_CHECK(pvo); /* sanity check */ 2088 pmap = pvo->pvo_pmap; 2089 PMAP_LOCK(pmap); 2090 moea64_pvo_remove(mmu, pvo); 2091 PMAP_UNLOCK(pmap); 2092 } 2093 if ((m->flags & PG_WRITEABLE) && moea64_is_modified(mmu, m)) { 2094 moea64_attr_clear(m, LPTE_CHG); 2095 vm_page_dirty(m); 2096 } 2097 vm_page_flag_clear(m, PG_WRITEABLE); 2098 vm_page_unlock_queues(); 2099 } 2100 2101 /* 2102 * Allocate a physical page of memory directly from the phys_avail map. 2103 * Can only be called from moea64_bootstrap before avail start and end are 2104 * calculated. 2105 */ 2106 vm_offset_t 2107 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2108 { 2109 vm_offset_t s, e; 2110 int i, j; 2111 2112 size = round_page(size); 2113 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2114 if (align != 0) 2115 s = (phys_avail[i] + align - 1) & ~(align - 1); 2116 else 2117 s = phys_avail[i]; 2118 e = s + size; 2119 2120 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2121 continue; 2122 2123 if (s + size > platform_real_maxaddr()) 2124 continue; 2125 2126 if (s == phys_avail[i]) { 2127 phys_avail[i] += size; 2128 } else if (e == phys_avail[i + 1]) { 2129 phys_avail[i + 1] -= size; 2130 } else { 2131 for (j = phys_avail_count * 2; j > i; j -= 2) { 2132 phys_avail[j] = phys_avail[j - 2]; 2133 phys_avail[j + 1] = phys_avail[j - 1]; 2134 } 2135 2136 phys_avail[i + 3] = phys_avail[i + 1]; 2137 phys_avail[i + 1] = s; 2138 phys_avail[i + 2] = e; 2139 phys_avail_count++; 2140 } 2141 2142 return (s); 2143 } 2144 panic("moea64_bootstrap_alloc: could not allocate memory"); 2145 } 2146 2147 static int 2148 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone, 2149 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa, 2150 uint64_t pte_lo, int flags) 2151 { 2152 struct pvo_entry *pvo; 2153 uint64_t vsid; 2154 int first; 2155 u_int ptegidx; 2156 int i; 2157 int bootstrap; 2158 2159 /* 2160 * One nasty thing that can happen here is that the UMA calls to 2161 * allocate new PVOs need to map more memory, which calls pvo_enter(), 2162 * which calls UMA... 2163 * 2164 * We break the loop by detecting recursion and allocating out of 2165 * the bootstrap pool. 2166 */ 2167 2168 first = 0; 2169 bootstrap = (flags & PVO_BOOTSTRAP); 2170 2171 if (!moea64_initialized) 2172 bootstrap = 1; 2173 2174 /* 2175 * Compute the PTE Group index. 2176 */ 2177 va &= ~ADDR_POFF; 2178 vsid = va_to_vsid(pm, va); 2179 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE); 2180 2181 /* 2182 * Remove any existing mapping for this page. Reuse the pvo entry if 2183 * there is a mapping. 2184 */ 2185 LOCK_TABLE(); 2186 2187 moea64_pvo_enter_calls++; 2188 2189 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2190 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2191 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa && 2192 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP)) 2193 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) { 2194 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) { 2195 /* Re-insert if spilled */ 2196 i = MOEA64_PTE_INSERT(mmu, ptegidx, 2197 &pvo->pvo_pte.lpte); 2198 if (i >= 0) 2199 PVO_PTEGIDX_SET(pvo, i); 2200 moea64_pte_overflow--; 2201 } 2202 UNLOCK_TABLE(); 2203 return (0); 2204 } 2205 moea64_pvo_remove(mmu, pvo); 2206 break; 2207 } 2208 } 2209 2210 /* 2211 * If we aren't overwriting a mapping, try to allocate. 2212 */ 2213 if (bootstrap) { 2214 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) { 2215 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 2216 moea64_bpvo_pool_index, BPVO_POOL_SIZE, 2217 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2218 } 2219 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index]; 2220 moea64_bpvo_pool_index++; 2221 bootstrap = 1; 2222 } else { 2223 /* 2224 * Note: drop the table lock around the UMA allocation in 2225 * case the UMA allocator needs to manipulate the page 2226 * table. The mapping we are working with is already 2227 * protected by the PMAP lock. 2228 */ 2229 UNLOCK_TABLE(); 2230 pvo = uma_zalloc(zone, M_NOWAIT); 2231 LOCK_TABLE(); 2232 } 2233 2234 if (pvo == NULL) { 2235 UNLOCK_TABLE(); 2236 return (ENOMEM); 2237 } 2238 2239 moea64_pvo_entries++; 2240 pvo->pvo_vaddr = va; 2241 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 2242 | (vsid << 16); 2243 pvo->pvo_pmap = pm; 2244 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink); 2245 pvo->pvo_vaddr &= ~ADDR_POFF; 2246 2247 if (flags & PVO_WIRED) 2248 pvo->pvo_vaddr |= PVO_WIRED; 2249 if (pvo_head != &moea64_pvo_kunmanaged) 2250 pvo->pvo_vaddr |= PVO_MANAGED; 2251 if (bootstrap) 2252 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2253 if (flags & PVO_FAKE) 2254 pvo->pvo_vaddr |= PVO_FAKE; 2255 if (flags & PVO_LARGE) 2256 pvo->pvo_vaddr |= PVO_LARGE; 2257 2258 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va, 2259 (uint64_t)(pa) | pte_lo, flags); 2260 2261 /* 2262 * Remember if the list was empty and therefore will be the first 2263 * item. 2264 */ 2265 if (LIST_FIRST(pvo_head) == NULL) 2266 first = 1; 2267 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2268 2269 if (pvo->pvo_vaddr & PVO_WIRED) { 2270 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED; 2271 pm->pm_stats.wired_count++; 2272 } 2273 pm->pm_stats.resident_count++; 2274 2275 /* 2276 * We hope this succeeds but it isn't required. 2277 */ 2278 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte); 2279 if (i >= 0) { 2280 PVO_PTEGIDX_SET(pvo, i); 2281 } else { 2282 panic("moea64_pvo_enter: overflow"); 2283 moea64_pte_overflow++; 2284 } 2285 2286 if (pm == kernel_pmap) 2287 isync(); 2288 2289 UNLOCK_TABLE(); 2290 2291 #ifdef __powerpc64__ 2292 /* 2293 * Make sure all our bootstrap mappings are in the SLB as soon 2294 * as virtual memory is switched on. 2295 */ 2296 if (!pmap_bootstrapped) 2297 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE); 2298 #endif 2299 2300 return (first ? ENOENT : 0); 2301 } 2302 2303 static void 2304 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo) 2305 { 2306 uintptr_t pt; 2307 2308 /* 2309 * If there is an active pte entry, we need to deactivate it (and 2310 * save the ref & cfg bits). 2311 */ 2312 LOCK_TABLE(); 2313 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2314 if (pt != -1) { 2315 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn); 2316 PVO_PTEGIDX_CLR(pvo); 2317 } else { 2318 moea64_pte_overflow--; 2319 } 2320 2321 /* 2322 * Update our statistics. 2323 */ 2324 pvo->pvo_pmap->pm_stats.resident_count--; 2325 if (pvo->pvo_vaddr & PVO_WIRED) 2326 pvo->pvo_pmap->pm_stats.wired_count--; 2327 2328 /* 2329 * Save the REF/CHG bits into their cache if the page is managed. 2330 */ 2331 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2332 struct vm_page *pg; 2333 2334 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN); 2335 if (pg != NULL) { 2336 moea64_attr_save(pg, pvo->pvo_pte.lpte.pte_lo & 2337 (LPTE_REF | LPTE_CHG)); 2338 } 2339 } 2340 2341 /* 2342 * Remove this PVO from the PV list. 2343 */ 2344 LIST_REMOVE(pvo, pvo_vlink); 2345 2346 /* 2347 * Remove this from the overflow list and return it to the pool 2348 * if we aren't going to reuse it. 2349 */ 2350 LIST_REMOVE(pvo, pvo_olink); 2351 2352 moea64_pvo_entries--; 2353 moea64_pvo_remove_calls++; 2354 2355 UNLOCK_TABLE(); 2356 2357 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2358 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone : 2359 moea64_upvo_zone, pvo); 2360 } 2361 2362 static struct pvo_entry * 2363 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2364 { 2365 struct pvo_entry *pvo; 2366 int ptegidx; 2367 uint64_t vsid; 2368 #ifdef __powerpc64__ 2369 uint64_t slbv; 2370 2371 if (pm == kernel_pmap) { 2372 slbv = kernel_va_to_slbv(va); 2373 } else { 2374 struct slb *slb; 2375 slb = user_va_to_slb_entry(pm, va); 2376 /* The page is not mapped if the segment isn't */ 2377 if (slb == NULL) 2378 return NULL; 2379 slbv = slb->slbv; 2380 } 2381 2382 vsid = (slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT; 2383 if (slbv & SLBV_L) 2384 va &= ~moea64_large_page_mask; 2385 else 2386 va &= ~ADDR_POFF; 2387 ptegidx = va_to_pteg(vsid, va, slbv & SLBV_L); 2388 #else 2389 va &= ~ADDR_POFF; 2390 vsid = va_to_vsid(pm, va); 2391 ptegidx = va_to_pteg(vsid, va, 0); 2392 #endif 2393 2394 LOCK_TABLE(); 2395 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) { 2396 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) 2397 break; 2398 } 2399 UNLOCK_TABLE(); 2400 2401 return (pvo); 2402 } 2403 2404 static boolean_t 2405 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2406 { 2407 struct pvo_entry *pvo; 2408 uintptr_t pt; 2409 2410 if (moea64_attr_fetch(m) & ptebit) 2411 return (TRUE); 2412 2413 vm_page_lock_queues(); 2414 2415 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2416 MOEA_PVO_CHECK(pvo); /* sanity check */ 2417 2418 /* 2419 * See if we saved the bit off. If so, cache it and return 2420 * success. 2421 */ 2422 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2423 moea64_attr_save(m, ptebit); 2424 MOEA_PVO_CHECK(pvo); /* sanity check */ 2425 vm_page_unlock_queues(); 2426 return (TRUE); 2427 } 2428 } 2429 2430 /* 2431 * No luck, now go through the hard part of looking at the PTEs 2432 * themselves. Sync so that any pending REF/CHG bits are flushed to 2433 * the PTEs. 2434 */ 2435 powerpc_sync(); 2436 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2437 MOEA_PVO_CHECK(pvo); /* sanity check */ 2438 2439 /* 2440 * See if this pvo has a valid PTE. if so, fetch the 2441 * REF/CHG bits from the valid PTE. If the appropriate 2442 * ptebit is set, cache it and return success. 2443 */ 2444 LOCK_TABLE(); 2445 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2446 if (pt != -1) { 2447 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2448 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2449 UNLOCK_TABLE(); 2450 2451 moea64_attr_save(m, ptebit); 2452 MOEA_PVO_CHECK(pvo); /* sanity check */ 2453 vm_page_unlock_queues(); 2454 return (TRUE); 2455 } 2456 } 2457 UNLOCK_TABLE(); 2458 } 2459 2460 vm_page_unlock_queues(); 2461 return (FALSE); 2462 } 2463 2464 static u_int 2465 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2466 { 2467 u_int count; 2468 struct pvo_entry *pvo; 2469 uintptr_t pt; 2470 2471 vm_page_lock_queues(); 2472 2473 /* 2474 * Clear the cached value. 2475 */ 2476 moea64_attr_clear(m, ptebit); 2477 2478 /* 2479 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2480 * we can reset the right ones). note that since the pvo entries and 2481 * list heads are accessed via BAT0 and are never placed in the page 2482 * table, we don't have to worry about further accesses setting the 2483 * REF/CHG bits. 2484 */ 2485 powerpc_sync(); 2486 2487 /* 2488 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2489 * valid pte clear the ptebit from the valid pte. 2490 */ 2491 count = 0; 2492 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2493 MOEA_PVO_CHECK(pvo); /* sanity check */ 2494 2495 LOCK_TABLE(); 2496 pt = MOEA64_PVO_TO_PTE(mmu, pvo); 2497 if (pt != -1) { 2498 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte); 2499 if (pvo->pvo_pte.lpte.pte_lo & ptebit) { 2500 count++; 2501 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte, 2502 pvo->pvo_vpn, ptebit); 2503 } 2504 } 2505 pvo->pvo_pte.lpte.pte_lo &= ~ptebit; 2506 MOEA_PVO_CHECK(pvo); /* sanity check */ 2507 UNLOCK_TABLE(); 2508 } 2509 2510 vm_page_unlock_queues(); 2511 return (count); 2512 } 2513 2514 boolean_t 2515 moea64_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2516 { 2517 struct pvo_entry *pvo; 2518 vm_offset_t ppa; 2519 int error = 0; 2520 2521 PMAP_LOCK(kernel_pmap); 2522 for (ppa = pa & ~ADDR_POFF; ppa < pa + size; ppa += PAGE_SIZE) { 2523 pvo = moea64_pvo_find_va(kernel_pmap, ppa); 2524 if (pvo == NULL || 2525 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) { 2526 error = EFAULT; 2527 break; 2528 } 2529 } 2530 PMAP_UNLOCK(kernel_pmap); 2531 2532 return (error); 2533 } 2534 2535 /* 2536 * Map a set of physical memory pages into the kernel virtual 2537 * address space. Return a pointer to where it is mapped. This 2538 * routine is intended to be used for mapping device memory, 2539 * NOT real memory. 2540 */ 2541 void * 2542 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2543 { 2544 vm_offset_t va, tmpva, ppa, offset; 2545 2546 ppa = trunc_page(pa); 2547 offset = pa & PAGE_MASK; 2548 size = roundup(offset + size, PAGE_SIZE); 2549 2550 va = kmem_alloc_nofault(kernel_map, size); 2551 2552 if (!va) 2553 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2554 2555 for (tmpva = va; size > 0;) { 2556 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2557 size -= PAGE_SIZE; 2558 tmpva += PAGE_SIZE; 2559 ppa += PAGE_SIZE; 2560 } 2561 2562 return ((void *)(va + offset)); 2563 } 2564 2565 void * 2566 moea64_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2567 { 2568 2569 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2570 } 2571 2572 void 2573 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2574 { 2575 vm_offset_t base, offset; 2576 2577 base = trunc_page(va); 2578 offset = va & PAGE_MASK; 2579 size = roundup(offset + size, PAGE_SIZE); 2580 2581 kmem_free(kernel_map, base, size); 2582 } 2583 2584 void 2585 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2586 { 2587 struct pvo_entry *pvo; 2588 vm_offset_t lim; 2589 vm_paddr_t pa; 2590 vm_size_t len; 2591 2592 PMAP_LOCK(pm); 2593 while (sz > 0) { 2594 lim = round_page(va); 2595 len = MIN(lim - va, sz); 2596 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2597 if (pvo != NULL) { 2598 pa = (pvo->pvo_pte.pte.pte_lo & LPTE_RPGN) | 2599 (va & ADDR_POFF); 2600 moea64_syncicache(mmu, pm, va, pa, len); 2601 } 2602 va += len; 2603 sz -= len; 2604 } 2605 PMAP_UNLOCK(pm); 2606 } 2607