1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_map.h> 78 #include <vm/vm_object.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_pageout.h> 81 #include <vm/uma.h> 82 83 #include <machine/_inttypes.h> 84 #include <machine/cpu.h> 85 #include <machine/platform.h> 86 #include <machine/frame.h> 87 #include <machine/md_var.h> 88 #include <machine/psl.h> 89 #include <machine/bat.h> 90 #include <machine/hid.h> 91 #include <machine/pte.h> 92 #include <machine/sr.h> 93 #include <machine/trap.h> 94 #include <machine/mmuvar.h> 95 96 #include "mmu_oea64.h" 97 #include "mmu_if.h" 98 #include "moea64_if.h" 99 100 void moea64_release_vsid(uint64_t vsid); 101 uintptr_t moea64_get_unique_vsid(void); 102 103 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 104 #define ENABLE_TRANS(msr) mtmsr(msr) 105 106 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 107 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 108 #define VSID_HASH_MASK 0x0000007fffffffffULL 109 110 /* 111 * Locking semantics: 112 * 113 * There are two locks of interest: the page locks and the pmap locks, which 114 * protect their individual PVO lists and are locked in that order. The contents 115 * of all PVO entries are protected by the locks of their respective pmaps. 116 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 117 * into any list. 118 * 119 */ 120 121 #define PV_LOCK_PER_DOM PA_LOCK_COUNT*3 122 #define PV_LOCK_COUNT PV_LOCK_PER_DOM*MAXMEMDOM 123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 124 125 /* 126 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 127 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 128 * index at (N << 45). 129 */ 130 #ifdef __powerpc64__ 131 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 132 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 133 #else 134 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 135 #endif 136 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 137 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 138 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 139 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 140 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 141 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 142 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 143 144 struct ofw_map { 145 cell_t om_va; 146 cell_t om_len; 147 uint64_t om_pa; 148 cell_t om_mode; 149 }; 150 151 extern unsigned char _etext[]; 152 extern unsigned char _end[]; 153 154 extern void *slbtrap, *slbtrapend; 155 156 /* 157 * Map of physical memory regions. 158 */ 159 static struct mem_region *regions; 160 static struct mem_region *pregions; 161 static struct numa_mem_region *numa_pregions; 162 static u_int phys_avail_count; 163 static int regions_sz, pregions_sz, numapregions_sz; 164 165 extern void bs_remap_earlyboot(void); 166 167 /* 168 * Lock for the SLB tables. 169 */ 170 struct mtx moea64_slb_mutex; 171 172 /* 173 * PTEG data. 174 */ 175 u_long moea64_pteg_count; 176 u_long moea64_pteg_mask; 177 178 /* 179 * PVO data. 180 */ 181 182 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 183 184 static struct pvo_entry *moea64_bpvo_pool; 185 static int moea64_bpvo_pool_index = 0; 186 static int moea64_bpvo_pool_size = 327680; 187 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 188 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 189 &moea64_bpvo_pool_index, 0, ""); 190 191 #define VSID_NBPW (sizeof(u_int32_t) * 8) 192 #ifdef __powerpc64__ 193 #define NVSIDS (NPMAPS * 16) 194 #define VSID_HASHMASK 0xffffffffUL 195 #else 196 #define NVSIDS NPMAPS 197 #define VSID_HASHMASK 0xfffffUL 198 #endif 199 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 200 201 static boolean_t moea64_initialized = FALSE; 202 203 #ifdef MOEA64_STATS 204 /* 205 * Statistics. 206 */ 207 u_int moea64_pte_valid = 0; 208 u_int moea64_pte_overflow = 0; 209 u_int moea64_pvo_entries = 0; 210 u_int moea64_pvo_enter_calls = 0; 211 u_int moea64_pvo_remove_calls = 0; 212 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 213 &moea64_pte_valid, 0, ""); 214 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 215 &moea64_pte_overflow, 0, ""); 216 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 217 &moea64_pvo_entries, 0, ""); 218 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 219 &moea64_pvo_enter_calls, 0, ""); 220 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 221 &moea64_pvo_remove_calls, 0, ""); 222 #endif 223 224 vm_offset_t moea64_scratchpage_va[2]; 225 struct pvo_entry *moea64_scratchpage_pvo[2]; 226 struct mtx moea64_scratchpage_mtx; 227 228 uint64_t moea64_large_page_mask = 0; 229 uint64_t moea64_large_page_size = 0; 230 int moea64_large_page_shift = 0; 231 232 /* 233 * PVO calls. 234 */ 235 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 236 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 237 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 238 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 240 struct pvo_entry *pvo, vm_page_t m); 241 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 242 243 /* 244 * Utility routines. 245 */ 246 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 247 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 248 static void moea64_kremove(mmu_t, vm_offset_t); 249 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 250 vm_paddr_t pa, vm_size_t sz); 251 static void moea64_pmap_init_qpages(void); 252 253 /* 254 * Kernel MMU interface 255 */ 256 void moea64_clear_modify(mmu_t, vm_page_t); 257 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 258 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 259 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 260 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 261 u_int flags, int8_t psind); 262 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 263 vm_prot_t); 264 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 265 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 266 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 267 void moea64_init(mmu_t); 268 boolean_t moea64_is_modified(mmu_t, vm_page_t); 269 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 270 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 271 int moea64_ts_referenced(mmu_t, vm_page_t); 272 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 273 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 274 void moea64_page_init(mmu_t, vm_page_t); 275 int moea64_page_wired_mappings(mmu_t, vm_page_t); 276 void moea64_pinit(mmu_t, pmap_t); 277 void moea64_pinit0(mmu_t, pmap_t); 278 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 279 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 280 void moea64_qremove(mmu_t, vm_offset_t, int); 281 void moea64_release(mmu_t, pmap_t); 282 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 283 void moea64_remove_pages(mmu_t, pmap_t); 284 void moea64_remove_all(mmu_t, vm_page_t); 285 void moea64_remove_write(mmu_t, vm_page_t); 286 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 287 void moea64_zero_page(mmu_t, vm_page_t); 288 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 289 void moea64_activate(mmu_t, struct thread *); 290 void moea64_deactivate(mmu_t, struct thread *); 291 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 292 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 293 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 294 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 295 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 296 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 297 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 298 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 299 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 300 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 301 void **va); 302 void moea64_scan_init(mmu_t mmu); 303 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 304 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 305 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 306 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 307 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 308 int *is_user, vm_offset_t *decoded_addr); 309 310 311 static mmu_method_t moea64_methods[] = { 312 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 313 MMUMETHOD(mmu_copy_page, moea64_copy_page), 314 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 315 MMUMETHOD(mmu_enter, moea64_enter), 316 MMUMETHOD(mmu_enter_object, moea64_enter_object), 317 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 318 MMUMETHOD(mmu_extract, moea64_extract), 319 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 320 MMUMETHOD(mmu_init, moea64_init), 321 MMUMETHOD(mmu_is_modified, moea64_is_modified), 322 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 323 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 324 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 325 MMUMETHOD(mmu_map, moea64_map), 326 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 327 MMUMETHOD(mmu_page_init, moea64_page_init), 328 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 329 MMUMETHOD(mmu_pinit, moea64_pinit), 330 MMUMETHOD(mmu_pinit0, moea64_pinit0), 331 MMUMETHOD(mmu_protect, moea64_protect), 332 MMUMETHOD(mmu_qenter, moea64_qenter), 333 MMUMETHOD(mmu_qremove, moea64_qremove), 334 MMUMETHOD(mmu_release, moea64_release), 335 MMUMETHOD(mmu_remove, moea64_remove), 336 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 337 MMUMETHOD(mmu_remove_all, moea64_remove_all), 338 MMUMETHOD(mmu_remove_write, moea64_remove_write), 339 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 340 MMUMETHOD(mmu_unwire, moea64_unwire), 341 MMUMETHOD(mmu_zero_page, moea64_zero_page), 342 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 343 MMUMETHOD(mmu_activate, moea64_activate), 344 MMUMETHOD(mmu_deactivate, moea64_deactivate), 345 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 346 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 347 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 348 349 /* Internal interfaces */ 350 MMUMETHOD(mmu_mapdev, moea64_mapdev), 351 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 352 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 353 MMUMETHOD(mmu_kextract, moea64_kextract), 354 MMUMETHOD(mmu_kenter, moea64_kenter), 355 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 356 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 357 MMUMETHOD(mmu_scan_init, moea64_scan_init), 358 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 359 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 360 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 361 362 { 0, 0 } 363 }; 364 365 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 366 367 static struct pvo_head * 368 vm_page_to_pvoh(vm_page_t m) 369 { 370 371 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 372 return (&m->md.mdpg_pvoh); 373 } 374 375 static struct pvo_entry * 376 alloc_pvo_entry(int bootstrap, int flags) 377 { 378 struct pvo_entry *pvo; 379 380 KASSERT(bootstrap || (flags & M_WAITOK) || (flags & M_NOWAIT), 381 ("Either M_WAITOK or M_NOWAIT flag must be specified " 382 "when bootstrap is 0")); 383 KASSERT(!bootstrap || !(flags & M_WAITOK), 384 ("M_WAITOK can't be used with bootstrap")); 385 386 if (!moea64_initialized || bootstrap) { 387 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 388 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 389 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 390 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 391 } 392 pvo = &moea64_bpvo_pool[ 393 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 394 bzero(pvo, sizeof(*pvo)); 395 pvo->pvo_vaddr = PVO_BOOTSTRAP; 396 } else 397 pvo = uma_zalloc(moea64_pvo_zone, flags | M_ZERO); 398 399 return (pvo); 400 } 401 402 403 static void 404 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 405 { 406 uint64_t vsid; 407 uint64_t hash; 408 int shift; 409 410 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 411 412 pvo->pvo_pmap = pmap; 413 va &= ~ADDR_POFF; 414 pvo->pvo_vaddr |= va; 415 vsid = va_to_vsid(pmap, va); 416 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 417 | (vsid << 16); 418 419 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 420 ADDR_PIDX_SHFT; 421 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 422 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 423 } 424 425 static void 426 free_pvo_entry(struct pvo_entry *pvo) 427 { 428 429 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 430 uma_zfree(moea64_pvo_zone, pvo); 431 } 432 433 void 434 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 435 { 436 437 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 438 LPTE_AVPN_MASK; 439 lpte->pte_hi |= LPTE_VALID; 440 441 if (pvo->pvo_vaddr & PVO_LARGE) 442 lpte->pte_hi |= LPTE_BIG; 443 if (pvo->pvo_vaddr & PVO_WIRED) 444 lpte->pte_hi |= LPTE_WIRED; 445 if (pvo->pvo_vaddr & PVO_HID) 446 lpte->pte_hi |= LPTE_HID; 447 448 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 449 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 450 lpte->pte_lo |= LPTE_BW; 451 else 452 lpte->pte_lo |= LPTE_BR; 453 454 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 455 lpte->pte_lo |= LPTE_NOEXEC; 456 } 457 458 static __inline uint64_t 459 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 460 { 461 uint64_t pte_lo; 462 int i; 463 464 if (ma != VM_MEMATTR_DEFAULT) { 465 switch (ma) { 466 case VM_MEMATTR_UNCACHEABLE: 467 return (LPTE_I | LPTE_G); 468 case VM_MEMATTR_CACHEABLE: 469 return (LPTE_M); 470 case VM_MEMATTR_WRITE_COMBINING: 471 case VM_MEMATTR_WRITE_BACK: 472 case VM_MEMATTR_PREFETCHABLE: 473 return (LPTE_I); 474 case VM_MEMATTR_WRITE_THROUGH: 475 return (LPTE_W | LPTE_M); 476 } 477 } 478 479 /* 480 * Assume the page is cache inhibited and access is guarded unless 481 * it's in our available memory array. 482 */ 483 pte_lo = LPTE_I | LPTE_G; 484 for (i = 0; i < pregions_sz; i++) { 485 if ((pa >= pregions[i].mr_start) && 486 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 487 pte_lo &= ~(LPTE_I | LPTE_G); 488 pte_lo |= LPTE_M; 489 break; 490 } 491 } 492 493 return pte_lo; 494 } 495 496 /* 497 * Quick sort callout for comparing memory regions. 498 */ 499 static int om_cmp(const void *a, const void *b); 500 501 static int 502 om_cmp(const void *a, const void *b) 503 { 504 const struct ofw_map *mapa; 505 const struct ofw_map *mapb; 506 507 mapa = a; 508 mapb = b; 509 if (mapa->om_pa < mapb->om_pa) 510 return (-1); 511 else if (mapa->om_pa > mapb->om_pa) 512 return (1); 513 else 514 return (0); 515 } 516 517 static void 518 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 519 { 520 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 521 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 522 struct pvo_entry *pvo; 523 register_t msr; 524 vm_offset_t off; 525 vm_paddr_t pa_base; 526 int i, j; 527 528 bzero(translations, sz); 529 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 530 sizeof(acells)); 531 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 532 panic("moea64_bootstrap: can't get ofw translations"); 533 534 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 535 sz /= sizeof(cell_t); 536 for (i = 0, j = 0; i < sz; j++) { 537 translations[j].om_va = trans_cells[i++]; 538 translations[j].om_len = trans_cells[i++]; 539 translations[j].om_pa = trans_cells[i++]; 540 if (acells == 2) { 541 translations[j].om_pa <<= 32; 542 translations[j].om_pa |= trans_cells[i++]; 543 } 544 translations[j].om_mode = trans_cells[i++]; 545 } 546 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 547 i, sz)); 548 549 sz = j; 550 qsort(translations, sz, sizeof (*translations), om_cmp); 551 552 for (i = 0; i < sz; i++) { 553 pa_base = translations[i].om_pa; 554 #ifndef __powerpc64__ 555 if ((translations[i].om_pa >> 32) != 0) 556 panic("OFW translations above 32-bit boundary!"); 557 #endif 558 559 if (pa_base % PAGE_SIZE) 560 panic("OFW translation not page-aligned (phys)!"); 561 if (translations[i].om_va % PAGE_SIZE) 562 panic("OFW translation not page-aligned (virt)!"); 563 564 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 565 pa_base, translations[i].om_va, translations[i].om_len); 566 567 /* Now enter the pages for this mapping */ 568 569 DISABLE_TRANS(msr); 570 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 571 /* If this address is direct-mapped, skip remapping */ 572 if (hw_direct_map && 573 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 574 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 575 == LPTE_M) 576 continue; 577 578 PMAP_LOCK(kernel_pmap); 579 pvo = moea64_pvo_find_va(kernel_pmap, 580 translations[i].om_va + off); 581 PMAP_UNLOCK(kernel_pmap); 582 if (pvo != NULL) 583 continue; 584 585 moea64_kenter(mmup, translations[i].om_va + off, 586 pa_base + off); 587 } 588 ENABLE_TRANS(msr); 589 } 590 } 591 592 #ifdef __powerpc64__ 593 static void 594 moea64_probe_large_page(void) 595 { 596 uint16_t pvr = mfpvr() >> 16; 597 598 switch (pvr) { 599 case IBM970: 600 case IBM970FX: 601 case IBM970MP: 602 powerpc_sync(); isync(); 603 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 604 powerpc_sync(); isync(); 605 606 /* FALLTHROUGH */ 607 default: 608 if (moea64_large_page_size == 0) { 609 moea64_large_page_size = 0x1000000; /* 16 MB */ 610 moea64_large_page_shift = 24; 611 } 612 } 613 614 moea64_large_page_mask = moea64_large_page_size - 1; 615 } 616 617 static void 618 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 619 { 620 struct slb *cache; 621 struct slb entry; 622 uint64_t esid, slbe; 623 uint64_t i; 624 625 cache = PCPU_GET(aim.slb); 626 esid = va >> ADDR_SR_SHFT; 627 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 628 629 for (i = 0; i < 64; i++) { 630 if (cache[i].slbe == (slbe | i)) 631 return; 632 } 633 634 entry.slbe = slbe; 635 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 636 if (large) 637 entry.slbv |= SLBV_L; 638 639 slb_insert_kernel(entry.slbe, entry.slbv); 640 } 641 #endif 642 643 static void 644 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 645 vm_offset_t kernelend) 646 { 647 struct pvo_entry *pvo; 648 register_t msr; 649 vm_paddr_t pa, pkernelstart, pkernelend; 650 vm_offset_t size, off; 651 uint64_t pte_lo; 652 int i; 653 654 if (moea64_large_page_size == 0) 655 hw_direct_map = 0; 656 657 DISABLE_TRANS(msr); 658 if (hw_direct_map) { 659 PMAP_LOCK(kernel_pmap); 660 for (i = 0; i < pregions_sz; i++) { 661 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 662 pregions[i].mr_size; pa += moea64_large_page_size) { 663 pte_lo = LPTE_M; 664 665 pvo = alloc_pvo_entry(1 /* bootstrap */, 0); 666 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 667 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 668 669 /* 670 * Set memory access as guarded if prefetch within 671 * the page could exit the available physmem area. 672 */ 673 if (pa & moea64_large_page_mask) { 674 pa &= moea64_large_page_mask; 675 pte_lo |= LPTE_G; 676 } 677 if (pa + moea64_large_page_size > 678 pregions[i].mr_start + pregions[i].mr_size) 679 pte_lo |= LPTE_G; 680 681 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 682 VM_PROT_EXECUTE; 683 pvo->pvo_pte.pa = pa | pte_lo; 684 moea64_pvo_enter(mmup, pvo, NULL, NULL); 685 } 686 } 687 PMAP_UNLOCK(kernel_pmap); 688 } 689 690 /* 691 * Make sure the kernel and BPVO pool stay mapped on systems either 692 * without a direct map or on which the kernel is not already executing 693 * out of the direct-mapped region. 694 */ 695 if (kernelstart < DMAP_BASE_ADDRESS) { 696 /* 697 * For pre-dmap execution, we need to use identity mapping 698 * because we will be operating with the mmu on but in the 699 * wrong address configuration until we __restartkernel(). 700 */ 701 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 702 pa += PAGE_SIZE) 703 moea64_kenter(mmup, pa, pa); 704 } else if (!hw_direct_map) { 705 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 706 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 707 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 708 pa += PAGE_SIZE) 709 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 710 } 711 712 if (!hw_direct_map) { 713 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 714 off = (vm_offset_t)(moea64_bpvo_pool); 715 for (pa = off; pa < off + size; pa += PAGE_SIZE) 716 moea64_kenter(mmup, pa, pa); 717 718 /* Map exception vectors */ 719 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 720 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 721 } 722 ENABLE_TRANS(msr); 723 724 /* 725 * Allow user to override unmapped_buf_allowed for testing. 726 * XXXKIB Only direct map implementation was tested. 727 */ 728 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 729 &unmapped_buf_allowed)) 730 unmapped_buf_allowed = hw_direct_map; 731 } 732 733 /* Quick sort callout for comparing physical addresses. */ 734 static int 735 pa_cmp(const void *a, const void *b) 736 { 737 const vm_paddr_t *pa = a, *pb = b; 738 739 if (*pa < *pb) 740 return (-1); 741 else if (*pa > *pb) 742 return (1); 743 else 744 return (0); 745 } 746 747 void 748 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 749 { 750 int i, j; 751 vm_size_t physsz, hwphyssz; 752 vm_paddr_t kernelphysstart, kernelphysend; 753 int rm_pavail; 754 755 #ifndef __powerpc64__ 756 /* We don't have a direct map since there is no BAT */ 757 hw_direct_map = 0; 758 759 /* Make sure battable is zero, since we have no BAT */ 760 for (i = 0; i < 16; i++) { 761 battable[i].batu = 0; 762 battable[i].batl = 0; 763 } 764 #else 765 moea64_probe_large_page(); 766 767 /* Use a direct map if we have large page support */ 768 if (moea64_large_page_size > 0) 769 hw_direct_map = 1; 770 else 771 hw_direct_map = 0; 772 773 /* Install trap handlers for SLBs */ 774 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 775 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 776 __syncicache((void *)EXC_DSE, 0x80); 777 __syncicache((void *)EXC_ISE, 0x80); 778 #endif 779 780 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 781 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 782 783 /* Get physical memory regions from firmware */ 784 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 785 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 786 787 if (nitems(phys_avail) < regions_sz) 788 panic("moea64_bootstrap: phys_avail too small"); 789 790 phys_avail_count = 0; 791 physsz = 0; 792 hwphyssz = 0; 793 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 794 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 795 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 796 regions[i].mr_start, regions[i].mr_start + 797 regions[i].mr_size, regions[i].mr_size); 798 if (hwphyssz != 0 && 799 (physsz + regions[i].mr_size) >= hwphyssz) { 800 if (physsz < hwphyssz) { 801 phys_avail[j] = regions[i].mr_start; 802 phys_avail[j + 1] = regions[i].mr_start + 803 hwphyssz - physsz; 804 physsz = hwphyssz; 805 phys_avail_count++; 806 } 807 break; 808 } 809 phys_avail[j] = regions[i].mr_start; 810 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 811 phys_avail_count++; 812 physsz += regions[i].mr_size; 813 } 814 815 /* Check for overlap with the kernel and exception vectors */ 816 rm_pavail = 0; 817 for (j = 0; j < 2*phys_avail_count; j+=2) { 818 if (phys_avail[j] < EXC_LAST) 819 phys_avail[j] += EXC_LAST; 820 821 if (phys_avail[j] >= kernelphysstart && 822 phys_avail[j+1] <= kernelphysend) { 823 phys_avail[j] = phys_avail[j+1] = ~0; 824 rm_pavail++; 825 continue; 826 } 827 828 if (kernelphysstart >= phys_avail[j] && 829 kernelphysstart < phys_avail[j+1]) { 830 if (kernelphysend < phys_avail[j+1]) { 831 phys_avail[2*phys_avail_count] = 832 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 833 phys_avail[2*phys_avail_count + 1] = 834 phys_avail[j+1]; 835 phys_avail_count++; 836 } 837 838 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 839 } 840 841 if (kernelphysend >= phys_avail[j] && 842 kernelphysend < phys_avail[j+1]) { 843 if (kernelphysstart > phys_avail[j]) { 844 phys_avail[2*phys_avail_count] = phys_avail[j]; 845 phys_avail[2*phys_avail_count + 1] = 846 kernelphysstart & ~PAGE_MASK; 847 phys_avail_count++; 848 } 849 850 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 851 PAGE_SIZE; 852 } 853 } 854 855 /* Remove physical available regions marked for removal (~0) */ 856 if (rm_pavail) { 857 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 858 pa_cmp); 859 phys_avail_count -= rm_pavail; 860 for (i = 2*phys_avail_count; 861 i < 2*(phys_avail_count + rm_pavail); i+=2) 862 phys_avail[i] = phys_avail[i+1] = 0; 863 } 864 865 physmem = btoc(physsz); 866 867 #ifdef PTEGCOUNT 868 moea64_pteg_count = PTEGCOUNT; 869 #else 870 moea64_pteg_count = 0x1000; 871 872 while (moea64_pteg_count < physmem) 873 moea64_pteg_count <<= 1; 874 875 moea64_pteg_count >>= 1; 876 #endif /* PTEGCOUNT */ 877 } 878 879 void 880 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 881 { 882 int i; 883 884 /* 885 * Set PTEG mask 886 */ 887 moea64_pteg_mask = moea64_pteg_count - 1; 888 889 /* 890 * Initialize SLB table lock and page locks 891 */ 892 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 893 for (i = 0; i < PV_LOCK_COUNT; i++) 894 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 895 896 /* 897 * Initialise the bootstrap pvo pool. 898 */ 899 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 900 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 901 moea64_bpvo_pool_index = 0; 902 903 /* Place at address usable through the direct map */ 904 if (hw_direct_map) 905 moea64_bpvo_pool = (struct pvo_entry *) 906 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 907 908 /* 909 * Make sure kernel vsid is allocated as well as VSID 0. 910 */ 911 #ifndef __powerpc64__ 912 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 913 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 914 moea64_vsid_bitmap[0] |= 1; 915 #endif 916 917 /* 918 * Initialize the kernel pmap (which is statically allocated). 919 */ 920 #ifdef __powerpc64__ 921 for (i = 0; i < 64; i++) { 922 pcpup->pc_aim.slb[i].slbv = 0; 923 pcpup->pc_aim.slb[i].slbe = 0; 924 } 925 #else 926 for (i = 0; i < 16; i++) 927 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 928 #endif 929 930 kernel_pmap->pmap_phys = kernel_pmap; 931 CPU_FILL(&kernel_pmap->pm_active); 932 RB_INIT(&kernel_pmap->pmap_pvo); 933 934 PMAP_LOCK_INIT(kernel_pmap); 935 936 /* 937 * Now map in all the other buffers we allocated earlier 938 */ 939 940 moea64_setup_direct_map(mmup, kernelstart, kernelend); 941 } 942 943 void 944 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 945 { 946 ihandle_t mmui; 947 phandle_t chosen; 948 phandle_t mmu; 949 ssize_t sz; 950 int i; 951 vm_offset_t pa, va; 952 void *dpcpu; 953 954 /* 955 * Set up the Open Firmware pmap and add its mappings if not in real 956 * mode. 957 */ 958 959 chosen = OF_finddevice("/chosen"); 960 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 961 mmu = OF_instance_to_package(mmui); 962 if (mmu == -1 || 963 (sz = OF_getproplen(mmu, "translations")) == -1) 964 sz = 0; 965 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 966 panic("moea64_bootstrap: too many ofw translations"); 967 968 if (sz > 0) 969 moea64_add_ofw_mappings(mmup, mmu, sz); 970 } 971 972 /* 973 * Calculate the last available physical address. 974 */ 975 Maxmem = 0; 976 for (i = 0; phys_avail[i + 2] != 0; i += 2) 977 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 978 979 /* 980 * Initialize MMU. 981 */ 982 MMU_CPU_BOOTSTRAP(mmup,0); 983 mtmsr(mfmsr() | PSL_DR | PSL_IR); 984 pmap_bootstrapped++; 985 986 /* 987 * Set the start and end of kva. 988 */ 989 virtual_avail = VM_MIN_KERNEL_ADDRESS; 990 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 991 992 /* 993 * Map the entire KVA range into the SLB. We must not fault there. 994 */ 995 #ifdef __powerpc64__ 996 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 997 moea64_bootstrap_slb_prefault(va, 0); 998 #endif 999 1000 /* 1001 * Remap any early IO mappings (console framebuffer, etc.) 1002 */ 1003 bs_remap_earlyboot(); 1004 1005 /* 1006 * Figure out how far we can extend virtual_end into segment 16 1007 * without running into existing mappings. Segment 16 is guaranteed 1008 * to contain neither RAM nor devices (at least on Apple hardware), 1009 * but will generally contain some OFW mappings we should not 1010 * step on. 1011 */ 1012 1013 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1014 PMAP_LOCK(kernel_pmap); 1015 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1016 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1017 virtual_end += PAGE_SIZE; 1018 PMAP_UNLOCK(kernel_pmap); 1019 #endif 1020 1021 /* 1022 * Allocate a kernel stack with a guard page for thread0 and map it 1023 * into the kernel page map. 1024 */ 1025 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1026 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1027 virtual_avail = va + kstack_pages * PAGE_SIZE; 1028 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1029 thread0.td_kstack = va; 1030 thread0.td_kstack_pages = kstack_pages; 1031 for (i = 0; i < kstack_pages; i++) { 1032 moea64_kenter(mmup, va, pa); 1033 pa += PAGE_SIZE; 1034 va += PAGE_SIZE; 1035 } 1036 1037 /* 1038 * Allocate virtual address space for the message buffer. 1039 */ 1040 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1041 msgbufp = (struct msgbuf *)virtual_avail; 1042 va = virtual_avail; 1043 virtual_avail += round_page(msgbufsize); 1044 while (va < virtual_avail) { 1045 moea64_kenter(mmup, va, pa); 1046 pa += PAGE_SIZE; 1047 va += PAGE_SIZE; 1048 } 1049 1050 /* 1051 * Allocate virtual address space for the dynamic percpu area. 1052 */ 1053 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1054 dpcpu = (void *)virtual_avail; 1055 va = virtual_avail; 1056 virtual_avail += DPCPU_SIZE; 1057 while (va < virtual_avail) { 1058 moea64_kenter(mmup, va, pa); 1059 pa += PAGE_SIZE; 1060 va += PAGE_SIZE; 1061 } 1062 dpcpu_init(dpcpu, curcpu); 1063 1064 /* 1065 * Allocate some things for page zeroing. We put this directly 1066 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1067 * of the PVO book-keeping or other parts of the VM system 1068 * from even knowing that this hack exists. 1069 */ 1070 1071 if (!hw_direct_map) { 1072 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1073 MTX_DEF); 1074 for (i = 0; i < 2; i++) { 1075 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1076 virtual_end -= PAGE_SIZE; 1077 1078 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1079 1080 PMAP_LOCK(kernel_pmap); 1081 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1082 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1083 PMAP_UNLOCK(kernel_pmap); 1084 } 1085 } 1086 1087 numa_mem_regions(&numa_pregions, &numapregions_sz); 1088 } 1089 1090 static void 1091 moea64_pmap_init_qpages(void) 1092 { 1093 struct pcpu *pc; 1094 int i; 1095 1096 if (hw_direct_map) 1097 return; 1098 1099 CPU_FOREACH(i) { 1100 pc = pcpu_find(i); 1101 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1102 if (pc->pc_qmap_addr == 0) 1103 panic("pmap_init_qpages: unable to allocate KVA"); 1104 PMAP_LOCK(kernel_pmap); 1105 pc->pc_aim.qmap_pvo = 1106 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1107 PMAP_UNLOCK(kernel_pmap); 1108 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1109 } 1110 } 1111 1112 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1113 1114 /* 1115 * Activate a user pmap. This mostly involves setting some non-CPU 1116 * state. 1117 */ 1118 void 1119 moea64_activate(mmu_t mmu, struct thread *td) 1120 { 1121 pmap_t pm; 1122 1123 pm = &td->td_proc->p_vmspace->vm_pmap; 1124 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1125 1126 #ifdef __powerpc64__ 1127 PCPU_SET(aim.userslb, pm->pm_slb); 1128 __asm __volatile("slbmte %0, %1; isync" :: 1129 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1130 #else 1131 PCPU_SET(curpmap, pm->pmap_phys); 1132 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1133 #endif 1134 } 1135 1136 void 1137 moea64_deactivate(mmu_t mmu, struct thread *td) 1138 { 1139 pmap_t pm; 1140 1141 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1142 1143 pm = &td->td_proc->p_vmspace->vm_pmap; 1144 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1145 #ifdef __powerpc64__ 1146 PCPU_SET(aim.userslb, NULL); 1147 #else 1148 PCPU_SET(curpmap, NULL); 1149 #endif 1150 } 1151 1152 void 1153 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1154 { 1155 struct pvo_entry key, *pvo; 1156 vm_page_t m; 1157 int64_t refchg; 1158 1159 key.pvo_vaddr = sva; 1160 PMAP_LOCK(pm); 1161 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1162 pvo != NULL && PVO_VADDR(pvo) < eva; 1163 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1164 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1165 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1166 pvo); 1167 pvo->pvo_vaddr &= ~PVO_WIRED; 1168 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1169 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1170 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1171 if (refchg < 0) 1172 refchg = LPTE_CHG; 1173 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1174 1175 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1176 if (refchg & LPTE_CHG) 1177 vm_page_dirty(m); 1178 if (refchg & LPTE_REF) 1179 vm_page_aflag_set(m, PGA_REFERENCED); 1180 } 1181 pm->pm_stats.wired_count--; 1182 } 1183 PMAP_UNLOCK(pm); 1184 } 1185 1186 /* 1187 * This goes through and sets the physical address of our 1188 * special scratch PTE to the PA we want to zero or copy. Because 1189 * of locking issues (this can get called in pvo_enter() by 1190 * the UMA allocator), we can't use most other utility functions here 1191 */ 1192 1193 static __inline 1194 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1195 { 1196 struct pvo_entry *pvo; 1197 1198 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1199 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1200 1201 pvo = moea64_scratchpage_pvo[which]; 1202 PMAP_LOCK(pvo->pvo_pmap); 1203 pvo->pvo_pte.pa = 1204 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1205 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1206 PMAP_UNLOCK(pvo->pvo_pmap); 1207 isync(); 1208 } 1209 1210 void 1211 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1212 { 1213 vm_offset_t dst; 1214 vm_offset_t src; 1215 1216 dst = VM_PAGE_TO_PHYS(mdst); 1217 src = VM_PAGE_TO_PHYS(msrc); 1218 1219 if (hw_direct_map) { 1220 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1221 PAGE_SIZE); 1222 } else { 1223 mtx_lock(&moea64_scratchpage_mtx); 1224 1225 moea64_set_scratchpage_pa(mmu, 0, src); 1226 moea64_set_scratchpage_pa(mmu, 1, dst); 1227 1228 bcopy((void *)moea64_scratchpage_va[0], 1229 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1230 1231 mtx_unlock(&moea64_scratchpage_mtx); 1232 } 1233 } 1234 1235 static inline void 1236 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1237 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1238 { 1239 void *a_cp, *b_cp; 1240 vm_offset_t a_pg_offset, b_pg_offset; 1241 int cnt; 1242 1243 while (xfersize > 0) { 1244 a_pg_offset = a_offset & PAGE_MASK; 1245 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1246 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1247 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1248 a_pg_offset; 1249 b_pg_offset = b_offset & PAGE_MASK; 1250 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1251 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1252 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1253 b_pg_offset; 1254 bcopy(a_cp, b_cp, cnt); 1255 a_offset += cnt; 1256 b_offset += cnt; 1257 xfersize -= cnt; 1258 } 1259 } 1260 1261 static inline void 1262 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1263 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1264 { 1265 void *a_cp, *b_cp; 1266 vm_offset_t a_pg_offset, b_pg_offset; 1267 int cnt; 1268 1269 mtx_lock(&moea64_scratchpage_mtx); 1270 while (xfersize > 0) { 1271 a_pg_offset = a_offset & PAGE_MASK; 1272 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1273 moea64_set_scratchpage_pa(mmu, 0, 1274 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1275 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1276 b_pg_offset = b_offset & PAGE_MASK; 1277 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1278 moea64_set_scratchpage_pa(mmu, 1, 1279 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1280 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1281 bcopy(a_cp, b_cp, cnt); 1282 a_offset += cnt; 1283 b_offset += cnt; 1284 xfersize -= cnt; 1285 } 1286 mtx_unlock(&moea64_scratchpage_mtx); 1287 } 1288 1289 void 1290 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1291 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1292 { 1293 1294 if (hw_direct_map) { 1295 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1296 xfersize); 1297 } else { 1298 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1299 xfersize); 1300 } 1301 } 1302 1303 void 1304 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1305 { 1306 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1307 1308 if (size + off > PAGE_SIZE) 1309 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1310 1311 if (hw_direct_map) { 1312 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1313 } else { 1314 mtx_lock(&moea64_scratchpage_mtx); 1315 moea64_set_scratchpage_pa(mmu, 0, pa); 1316 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1317 mtx_unlock(&moea64_scratchpage_mtx); 1318 } 1319 } 1320 1321 /* 1322 * Zero a page of physical memory by temporarily mapping it 1323 */ 1324 void 1325 moea64_zero_page(mmu_t mmu, vm_page_t m) 1326 { 1327 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1328 vm_offset_t va, off; 1329 1330 if (!hw_direct_map) { 1331 mtx_lock(&moea64_scratchpage_mtx); 1332 1333 moea64_set_scratchpage_pa(mmu, 0, pa); 1334 va = moea64_scratchpage_va[0]; 1335 } else { 1336 va = PHYS_TO_DMAP(pa); 1337 } 1338 1339 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1340 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1341 1342 if (!hw_direct_map) 1343 mtx_unlock(&moea64_scratchpage_mtx); 1344 } 1345 1346 vm_offset_t 1347 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1348 { 1349 struct pvo_entry *pvo; 1350 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1351 1352 if (hw_direct_map) 1353 return (PHYS_TO_DMAP(pa)); 1354 1355 /* 1356 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1357 * a critical section and access the PCPU data like on i386. 1358 * Instead, pin the thread and grab the PCPU lock to prevent 1359 * a preempting thread from using the same PCPU data. 1360 */ 1361 sched_pin(); 1362 1363 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1364 pvo = PCPU_GET(aim.qmap_pvo); 1365 1366 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1367 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1368 (uint64_t)pa; 1369 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1370 isync(); 1371 1372 return (PCPU_GET(qmap_addr)); 1373 } 1374 1375 void 1376 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1377 { 1378 if (hw_direct_map) 1379 return; 1380 1381 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1382 KASSERT(PCPU_GET(qmap_addr) == addr, 1383 ("moea64_quick_remove_page: invalid address")); 1384 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1385 sched_unpin(); 1386 } 1387 1388 /* 1389 * Map the given physical page at the specified virtual address in the 1390 * target pmap with the protection requested. If specified the page 1391 * will be wired down. 1392 */ 1393 1394 int 1395 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1396 vm_prot_t prot, u_int flags, int8_t psind) 1397 { 1398 struct pvo_entry *pvo, *oldpvo; 1399 struct pvo_head *pvo_head; 1400 uint64_t pte_lo; 1401 int error; 1402 1403 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1404 VM_OBJECT_ASSERT_LOCKED(m->object); 1405 1406 pvo = alloc_pvo_entry(0, M_NOWAIT); 1407 if (pvo == NULL) 1408 return (KERN_RESOURCE_SHORTAGE); 1409 pvo->pvo_pmap = NULL; /* to be filled in later */ 1410 pvo->pvo_pte.prot = prot; 1411 1412 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1413 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1414 1415 if ((flags & PMAP_ENTER_WIRED) != 0) 1416 pvo->pvo_vaddr |= PVO_WIRED; 1417 1418 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1419 pvo_head = NULL; 1420 } else { 1421 pvo_head = &m->md.mdpg_pvoh; 1422 pvo->pvo_vaddr |= PVO_MANAGED; 1423 } 1424 1425 PV_PAGE_LOCK(m); 1426 PMAP_LOCK(pmap); 1427 if (pvo->pvo_pmap == NULL) 1428 init_pvo_entry(pvo, pmap, va); 1429 if (prot & VM_PROT_WRITE) 1430 if (pmap_bootstrapped && 1431 (m->oflags & VPO_UNMANAGED) == 0) 1432 vm_page_aflag_set(m, PGA_WRITEABLE); 1433 1434 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1435 if (error == EEXIST) { 1436 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1437 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1438 oldpvo->pvo_pte.prot == prot) { 1439 /* Identical mapping already exists */ 1440 error = 0; 1441 1442 /* If not in page table, reinsert it */ 1443 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1444 STAT_MOEA64(moea64_pte_overflow--); 1445 MOEA64_PTE_INSERT(mmu, oldpvo); 1446 } 1447 1448 /* Then just clean up and go home */ 1449 PV_PAGE_UNLOCK(m); 1450 PMAP_UNLOCK(pmap); 1451 free_pvo_entry(pvo); 1452 goto out; 1453 } else { 1454 /* Otherwise, need to kill it first */ 1455 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1456 "mapping does not match new mapping")); 1457 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1458 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1459 } 1460 } 1461 PV_PAGE_UNLOCK(m); 1462 PMAP_UNLOCK(pmap); 1463 1464 /* Free any dead pages */ 1465 if (error == EEXIST) { 1466 moea64_pvo_remove_from_page(mmu, oldpvo); 1467 free_pvo_entry(oldpvo); 1468 } 1469 1470 out: 1471 /* 1472 * Flush the page from the instruction cache if this page is 1473 * mapped executable and cacheable. 1474 */ 1475 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1476 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1477 vm_page_aflag_set(m, PGA_EXECUTABLE); 1478 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1479 } 1480 return (KERN_SUCCESS); 1481 } 1482 1483 static void 1484 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1485 vm_size_t sz) 1486 { 1487 1488 /* 1489 * This is much trickier than on older systems because 1490 * we can't sync the icache on physical addresses directly 1491 * without a direct map. Instead we check a couple of cases 1492 * where the memory is already mapped in and, failing that, 1493 * use the same trick we use for page zeroing to create 1494 * a temporary mapping for this physical address. 1495 */ 1496 1497 if (!pmap_bootstrapped) { 1498 /* 1499 * If PMAP is not bootstrapped, we are likely to be 1500 * in real mode. 1501 */ 1502 __syncicache((void *)(uintptr_t)pa, sz); 1503 } else if (pmap == kernel_pmap) { 1504 __syncicache((void *)va, sz); 1505 } else if (hw_direct_map) { 1506 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1507 } else { 1508 /* Use the scratch page to set up a temp mapping */ 1509 1510 mtx_lock(&moea64_scratchpage_mtx); 1511 1512 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1513 __syncicache((void *)(moea64_scratchpage_va[1] + 1514 (va & ADDR_POFF)), sz); 1515 1516 mtx_unlock(&moea64_scratchpage_mtx); 1517 } 1518 } 1519 1520 /* 1521 * Maps a sequence of resident pages belonging to the same object. 1522 * The sequence begins with the given page m_start. This page is 1523 * mapped at the given virtual address start. Each subsequent page is 1524 * mapped at a virtual address that is offset from start by the same 1525 * amount as the page is offset from m_start within the object. The 1526 * last page in the sequence is the page with the largest offset from 1527 * m_start that can be mapped at a virtual address less than the given 1528 * virtual address end. Not every virtual page between start and end 1529 * is mapped; only those for which a resident page exists with the 1530 * corresponding offset from m_start are mapped. 1531 */ 1532 void 1533 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1534 vm_page_t m_start, vm_prot_t prot) 1535 { 1536 vm_page_t m; 1537 vm_pindex_t diff, psize; 1538 1539 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1540 1541 psize = atop(end - start); 1542 m = m_start; 1543 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1544 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1545 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1546 m = TAILQ_NEXT(m, listq); 1547 } 1548 } 1549 1550 void 1551 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1552 vm_prot_t prot) 1553 { 1554 1555 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1556 PMAP_ENTER_NOSLEEP, 0); 1557 } 1558 1559 vm_paddr_t 1560 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1561 { 1562 struct pvo_entry *pvo; 1563 vm_paddr_t pa; 1564 1565 PMAP_LOCK(pm); 1566 pvo = moea64_pvo_find_va(pm, va); 1567 if (pvo == NULL) 1568 pa = 0; 1569 else 1570 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1571 PMAP_UNLOCK(pm); 1572 1573 return (pa); 1574 } 1575 1576 /* 1577 * Atomically extract and hold the physical page with the given 1578 * pmap and virtual address pair if that mapping permits the given 1579 * protection. 1580 */ 1581 vm_page_t 1582 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1583 { 1584 struct pvo_entry *pvo; 1585 vm_page_t m; 1586 vm_paddr_t pa; 1587 1588 m = NULL; 1589 pa = 0; 1590 PMAP_LOCK(pmap); 1591 retry: 1592 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1593 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1594 if (vm_page_pa_tryrelock(pmap, 1595 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1596 goto retry; 1597 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1598 vm_page_wire(m); 1599 } 1600 PA_UNLOCK_COND(pa); 1601 PMAP_UNLOCK(pmap); 1602 return (m); 1603 } 1604 1605 static mmu_t installed_mmu; 1606 1607 static void * 1608 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1609 uint8_t *flags, int wait) 1610 { 1611 struct pvo_entry *pvo; 1612 vm_offset_t va; 1613 vm_page_t m; 1614 int needed_lock; 1615 1616 /* 1617 * This entire routine is a horrible hack to avoid bothering kmem 1618 * for new KVA addresses. Because this can get called from inside 1619 * kmem allocation routines, calling kmem for a new address here 1620 * can lead to multiply locking non-recursive mutexes. 1621 */ 1622 1623 *flags = UMA_SLAB_PRIV; 1624 needed_lock = !PMAP_LOCKED(kernel_pmap); 1625 1626 m = vm_page_alloc_domain(NULL, 0, domain, 1627 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1628 if (m == NULL) 1629 return (NULL); 1630 1631 va = VM_PAGE_TO_PHYS(m); 1632 1633 pvo = alloc_pvo_entry(1 /* bootstrap */, 0); 1634 1635 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1636 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1637 1638 if (needed_lock) 1639 PMAP_LOCK(kernel_pmap); 1640 1641 init_pvo_entry(pvo, kernel_pmap, va); 1642 pvo->pvo_vaddr |= PVO_WIRED; 1643 1644 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1645 1646 if (needed_lock) 1647 PMAP_UNLOCK(kernel_pmap); 1648 1649 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1650 bzero((void *)va, PAGE_SIZE); 1651 1652 return (void *)va; 1653 } 1654 1655 extern int elf32_nxstack; 1656 1657 void 1658 moea64_init(mmu_t mmu) 1659 { 1660 1661 CTR0(KTR_PMAP, "moea64_init"); 1662 1663 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1664 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1665 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1666 1667 if (!hw_direct_map) { 1668 installed_mmu = mmu; 1669 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1670 } 1671 1672 #ifdef COMPAT_FREEBSD32 1673 elf32_nxstack = 1; 1674 #endif 1675 1676 moea64_initialized = TRUE; 1677 } 1678 1679 boolean_t 1680 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1681 { 1682 1683 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1684 ("moea64_is_referenced: page %p is not managed", m)); 1685 1686 return (moea64_query_bit(mmu, m, LPTE_REF)); 1687 } 1688 1689 boolean_t 1690 moea64_is_modified(mmu_t mmu, vm_page_t m) 1691 { 1692 1693 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1694 ("moea64_is_modified: page %p is not managed", m)); 1695 1696 /* 1697 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1698 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1699 * is clear, no PTEs can have LPTE_CHG set. 1700 */ 1701 VM_OBJECT_ASSERT_LOCKED(m->object); 1702 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1703 return (FALSE); 1704 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1705 } 1706 1707 boolean_t 1708 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1709 { 1710 struct pvo_entry *pvo; 1711 boolean_t rv = TRUE; 1712 1713 PMAP_LOCK(pmap); 1714 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1715 if (pvo != NULL) 1716 rv = FALSE; 1717 PMAP_UNLOCK(pmap); 1718 return (rv); 1719 } 1720 1721 void 1722 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1723 { 1724 1725 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1726 ("moea64_clear_modify: page %p is not managed", m)); 1727 VM_OBJECT_ASSERT_WLOCKED(m->object); 1728 KASSERT(!vm_page_xbusied(m), 1729 ("moea64_clear_modify: page %p is exclusive busied", m)); 1730 1731 /* 1732 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1733 * set. If the object containing the page is locked and the page is 1734 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1735 */ 1736 if ((m->aflags & PGA_WRITEABLE) == 0) 1737 return; 1738 moea64_clear_bit(mmu, m, LPTE_CHG); 1739 } 1740 1741 /* 1742 * Clear the write and modified bits in each of the given page's mappings. 1743 */ 1744 void 1745 moea64_remove_write(mmu_t mmu, vm_page_t m) 1746 { 1747 struct pvo_entry *pvo; 1748 int64_t refchg, ret; 1749 pmap_t pmap; 1750 1751 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1752 ("moea64_remove_write: page %p is not managed", m)); 1753 1754 /* 1755 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1756 * set by another thread while the object is locked. Thus, 1757 * if PGA_WRITEABLE is clear, no page table entries need updating. 1758 */ 1759 VM_OBJECT_ASSERT_WLOCKED(m->object); 1760 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1761 return; 1762 powerpc_sync(); 1763 PV_PAGE_LOCK(m); 1764 refchg = 0; 1765 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1766 pmap = pvo->pvo_pmap; 1767 PMAP_LOCK(pmap); 1768 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1769 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1770 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1771 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1772 MOEA64_PTE_PROT_UPDATE); 1773 if (ret < 0) 1774 ret = LPTE_CHG; 1775 refchg |= ret; 1776 if (pvo->pvo_pmap == kernel_pmap) 1777 isync(); 1778 } 1779 PMAP_UNLOCK(pmap); 1780 } 1781 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1782 vm_page_dirty(m); 1783 vm_page_aflag_clear(m, PGA_WRITEABLE); 1784 PV_PAGE_UNLOCK(m); 1785 } 1786 1787 /* 1788 * moea64_ts_referenced: 1789 * 1790 * Return a count of reference bits for a page, clearing those bits. 1791 * It is not necessary for every reference bit to be cleared, but it 1792 * is necessary that 0 only be returned when there are truly no 1793 * reference bits set. 1794 * 1795 * XXX: The exact number of bits to check and clear is a matter that 1796 * should be tested and standardized at some point in the future for 1797 * optimal aging of shared pages. 1798 */ 1799 int 1800 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1801 { 1802 1803 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1804 ("moea64_ts_referenced: page %p is not managed", m)); 1805 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1806 } 1807 1808 /* 1809 * Modify the WIMG settings of all mappings for a page. 1810 */ 1811 void 1812 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1813 { 1814 struct pvo_entry *pvo; 1815 int64_t refchg; 1816 pmap_t pmap; 1817 uint64_t lo; 1818 1819 if ((m->oflags & VPO_UNMANAGED) != 0) { 1820 m->md.mdpg_cache_attrs = ma; 1821 return; 1822 } 1823 1824 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1825 1826 PV_PAGE_LOCK(m); 1827 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1828 pmap = pvo->pvo_pmap; 1829 PMAP_LOCK(pmap); 1830 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1831 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1832 pvo->pvo_pte.pa |= lo; 1833 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1834 MOEA64_PTE_INVALIDATE); 1835 if (refchg < 0) 1836 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1837 LPTE_CHG : 0; 1838 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1839 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1840 refchg |= 1841 atomic_readandclear_32(&m->md.mdpg_attrs); 1842 if (refchg & LPTE_CHG) 1843 vm_page_dirty(m); 1844 if (refchg & LPTE_REF) 1845 vm_page_aflag_set(m, PGA_REFERENCED); 1846 } 1847 if (pvo->pvo_pmap == kernel_pmap) 1848 isync(); 1849 } 1850 PMAP_UNLOCK(pmap); 1851 } 1852 m->md.mdpg_cache_attrs = ma; 1853 PV_PAGE_UNLOCK(m); 1854 } 1855 1856 /* 1857 * Map a wired page into kernel virtual address space. 1858 */ 1859 void 1860 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1861 { 1862 int error; 1863 struct pvo_entry *pvo, *oldpvo; 1864 1865 pvo = alloc_pvo_entry(0, M_WAITOK); 1866 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1867 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1868 pvo->pvo_vaddr |= PVO_WIRED; 1869 1870 PMAP_LOCK(kernel_pmap); 1871 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1872 if (oldpvo != NULL) 1873 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1874 init_pvo_entry(pvo, kernel_pmap, va); 1875 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1876 PMAP_UNLOCK(kernel_pmap); 1877 1878 /* Free any dead pages */ 1879 if (oldpvo != NULL) { 1880 moea64_pvo_remove_from_page(mmu, oldpvo); 1881 free_pvo_entry(oldpvo); 1882 } 1883 1884 if (error != 0 && error != ENOENT) 1885 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1886 (uintmax_t)pa, error); 1887 } 1888 1889 void 1890 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1891 { 1892 1893 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1894 } 1895 1896 /* 1897 * Extract the physical page address associated with the given kernel virtual 1898 * address. 1899 */ 1900 vm_paddr_t 1901 moea64_kextract(mmu_t mmu, vm_offset_t va) 1902 { 1903 struct pvo_entry *pvo; 1904 vm_paddr_t pa; 1905 1906 /* 1907 * Shortcut the direct-mapped case when applicable. We never put 1908 * anything but 1:1 (or 62-bit aliased) mappings below 1909 * VM_MIN_KERNEL_ADDRESS. 1910 */ 1911 if (va < VM_MIN_KERNEL_ADDRESS) 1912 return (va & ~DMAP_BASE_ADDRESS); 1913 1914 PMAP_LOCK(kernel_pmap); 1915 pvo = moea64_pvo_find_va(kernel_pmap, va); 1916 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1917 va)); 1918 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1919 PMAP_UNLOCK(kernel_pmap); 1920 return (pa); 1921 } 1922 1923 /* 1924 * Remove a wired page from kernel virtual address space. 1925 */ 1926 void 1927 moea64_kremove(mmu_t mmu, vm_offset_t va) 1928 { 1929 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1930 } 1931 1932 /* 1933 * Provide a kernel pointer corresponding to a given userland pointer. 1934 * The returned pointer is valid until the next time this function is 1935 * called in this thread. This is used internally in copyin/copyout. 1936 */ 1937 static int 1938 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1939 void **kaddr, size_t ulen, size_t *klen) 1940 { 1941 size_t l; 1942 #ifdef __powerpc64__ 1943 struct slb *slb; 1944 #endif 1945 register_t slbv; 1946 1947 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1948 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1949 if (l > ulen) 1950 l = ulen; 1951 if (klen) 1952 *klen = l; 1953 else if (l != ulen) 1954 return (EFAULT); 1955 1956 #ifdef __powerpc64__ 1957 /* Try lockless look-up first */ 1958 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1959 1960 if (slb == NULL) { 1961 /* If it isn't there, we need to pre-fault the VSID */ 1962 PMAP_LOCK(pm); 1963 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1964 PMAP_UNLOCK(pm); 1965 } else { 1966 slbv = slb->slbv; 1967 } 1968 1969 /* Mark segment no-execute */ 1970 slbv |= SLBV_N; 1971 #else 1972 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1973 1974 /* Mark segment no-execute */ 1975 slbv |= SR_N; 1976 #endif 1977 1978 /* If we have already set this VSID, we can just return */ 1979 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1980 return (0); 1981 1982 __asm __volatile("isync"); 1983 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1984 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1985 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1986 #ifdef __powerpc64__ 1987 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1988 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1989 #else 1990 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1991 #endif 1992 1993 return (0); 1994 } 1995 1996 /* 1997 * Figure out where a given kernel pointer (usually in a fault) points 1998 * to from the VM's perspective, potentially remapping into userland's 1999 * address space. 2000 */ 2001 static int 2002 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 2003 vm_offset_t *decoded_addr) 2004 { 2005 vm_offset_t user_sr; 2006 2007 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2008 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2009 addr &= ADDR_PIDX | ADDR_POFF; 2010 addr |= user_sr << ADDR_SR_SHFT; 2011 *decoded_addr = addr; 2012 *is_user = 1; 2013 } else { 2014 *decoded_addr = addr; 2015 *is_user = 0; 2016 } 2017 2018 return (0); 2019 } 2020 2021 /* 2022 * Map a range of physical addresses into kernel virtual address space. 2023 * 2024 * The value passed in *virt is a suggested virtual address for the mapping. 2025 * Architectures which can support a direct-mapped physical to virtual region 2026 * can return the appropriate address within that region, leaving '*virt' 2027 * unchanged. Other architectures should map the pages starting at '*virt' and 2028 * update '*virt' with the first usable address after the mapped region. 2029 */ 2030 vm_offset_t 2031 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2032 vm_paddr_t pa_end, int prot) 2033 { 2034 vm_offset_t sva, va; 2035 2036 if (hw_direct_map) { 2037 /* 2038 * Check if every page in the region is covered by the direct 2039 * map. The direct map covers all of physical memory. Use 2040 * moea64_calc_wimg() as a shortcut to see if the page is in 2041 * physical memory as a way to see if the direct map covers it. 2042 */ 2043 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2044 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2045 break; 2046 if (va == pa_end) 2047 return (PHYS_TO_DMAP(pa_start)); 2048 } 2049 sva = *virt; 2050 va = sva; 2051 /* XXX respect prot argument */ 2052 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2053 moea64_kenter(mmu, va, pa_start); 2054 *virt = va; 2055 2056 return (sva); 2057 } 2058 2059 /* 2060 * Returns true if the pmap's pv is one of the first 2061 * 16 pvs linked to from this page. This count may 2062 * be changed upwards or downwards in the future; it 2063 * is only necessary that true be returned for a small 2064 * subset of pmaps for proper page aging. 2065 */ 2066 boolean_t 2067 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2068 { 2069 int loops; 2070 struct pvo_entry *pvo; 2071 boolean_t rv; 2072 2073 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2074 ("moea64_page_exists_quick: page %p is not managed", m)); 2075 loops = 0; 2076 rv = FALSE; 2077 PV_PAGE_LOCK(m); 2078 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2079 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2080 rv = TRUE; 2081 break; 2082 } 2083 if (++loops >= 16) 2084 break; 2085 } 2086 PV_PAGE_UNLOCK(m); 2087 return (rv); 2088 } 2089 2090 void 2091 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2092 { 2093 2094 m->md.mdpg_attrs = 0; 2095 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2096 LIST_INIT(&m->md.mdpg_pvoh); 2097 } 2098 2099 /* 2100 * Return the number of managed mappings to the given physical page 2101 * that are wired. 2102 */ 2103 int 2104 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2105 { 2106 struct pvo_entry *pvo; 2107 int count; 2108 2109 count = 0; 2110 if ((m->oflags & VPO_UNMANAGED) != 0) 2111 return (count); 2112 PV_PAGE_LOCK(m); 2113 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2114 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2115 count++; 2116 PV_PAGE_UNLOCK(m); 2117 return (count); 2118 } 2119 2120 static uintptr_t moea64_vsidcontext; 2121 2122 uintptr_t 2123 moea64_get_unique_vsid(void) { 2124 u_int entropy; 2125 register_t hash; 2126 uint32_t mask; 2127 int i; 2128 2129 entropy = 0; 2130 __asm __volatile("mftb %0" : "=r"(entropy)); 2131 2132 mtx_lock(&moea64_slb_mutex); 2133 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2134 u_int n; 2135 2136 /* 2137 * Create a new value by mutiplying by a prime and adding in 2138 * entropy from the timebase register. This is to make the 2139 * VSID more random so that the PT hash function collides 2140 * less often. (Note that the prime casues gcc to do shifts 2141 * instead of a multiply.) 2142 */ 2143 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2144 hash = moea64_vsidcontext & (NVSIDS - 1); 2145 if (hash == 0) /* 0 is special, avoid it */ 2146 continue; 2147 n = hash >> 5; 2148 mask = 1 << (hash & (VSID_NBPW - 1)); 2149 hash = (moea64_vsidcontext & VSID_HASHMASK); 2150 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2151 /* anything free in this bucket? */ 2152 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2153 entropy = (moea64_vsidcontext >> 20); 2154 continue; 2155 } 2156 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2157 mask = 1 << i; 2158 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2159 hash |= i; 2160 } 2161 if (hash == VSID_VRMA) /* also special, avoid this too */ 2162 continue; 2163 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2164 ("Allocating in-use VSID %#zx\n", hash)); 2165 moea64_vsid_bitmap[n] |= mask; 2166 mtx_unlock(&moea64_slb_mutex); 2167 return (hash); 2168 } 2169 2170 mtx_unlock(&moea64_slb_mutex); 2171 panic("%s: out of segments",__func__); 2172 } 2173 2174 #ifdef __powerpc64__ 2175 void 2176 moea64_pinit(mmu_t mmu, pmap_t pmap) 2177 { 2178 2179 RB_INIT(&pmap->pmap_pvo); 2180 2181 pmap->pm_slb_tree_root = slb_alloc_tree(); 2182 pmap->pm_slb = slb_alloc_user_cache(); 2183 pmap->pm_slb_len = 0; 2184 } 2185 #else 2186 void 2187 moea64_pinit(mmu_t mmu, pmap_t pmap) 2188 { 2189 int i; 2190 uint32_t hash; 2191 2192 RB_INIT(&pmap->pmap_pvo); 2193 2194 if (pmap_bootstrapped) 2195 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2196 (vm_offset_t)pmap); 2197 else 2198 pmap->pmap_phys = pmap; 2199 2200 /* 2201 * Allocate some segment registers for this pmap. 2202 */ 2203 hash = moea64_get_unique_vsid(); 2204 2205 for (i = 0; i < 16; i++) 2206 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2207 2208 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2209 } 2210 #endif 2211 2212 /* 2213 * Initialize the pmap associated with process 0. 2214 */ 2215 void 2216 moea64_pinit0(mmu_t mmu, pmap_t pm) 2217 { 2218 2219 PMAP_LOCK_INIT(pm); 2220 moea64_pinit(mmu, pm); 2221 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2222 } 2223 2224 /* 2225 * Set the physical protection on the specified range of this map as requested. 2226 */ 2227 static void 2228 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2229 { 2230 struct vm_page *pg; 2231 vm_prot_t oldprot; 2232 int32_t refchg; 2233 2234 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2235 2236 /* 2237 * Change the protection of the page. 2238 */ 2239 oldprot = pvo->pvo_pte.prot; 2240 pvo->pvo_pte.prot = prot; 2241 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2242 2243 /* 2244 * If the PVO is in the page table, update mapping 2245 */ 2246 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2247 if (refchg < 0) 2248 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2249 2250 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2251 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2252 if ((pg->oflags & VPO_UNMANAGED) == 0) 2253 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2254 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2255 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2256 } 2257 2258 /* 2259 * Update vm about the REF/CHG bits if the page is managed and we have 2260 * removed write access. 2261 */ 2262 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2263 (oldprot & VM_PROT_WRITE)) { 2264 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2265 if (refchg & LPTE_CHG) 2266 vm_page_dirty(pg); 2267 if (refchg & LPTE_REF) 2268 vm_page_aflag_set(pg, PGA_REFERENCED); 2269 } 2270 } 2271 2272 void 2273 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2274 vm_prot_t prot) 2275 { 2276 struct pvo_entry *pvo, *tpvo, key; 2277 2278 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2279 sva, eva, prot); 2280 2281 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2282 ("moea64_protect: non current pmap")); 2283 2284 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2285 moea64_remove(mmu, pm, sva, eva); 2286 return; 2287 } 2288 2289 PMAP_LOCK(pm); 2290 key.pvo_vaddr = sva; 2291 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2292 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2293 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2294 moea64_pvo_protect(mmu, pm, pvo, prot); 2295 } 2296 PMAP_UNLOCK(pm); 2297 } 2298 2299 /* 2300 * Map a list of wired pages into kernel virtual address space. This is 2301 * intended for temporary mappings which do not need page modification or 2302 * references recorded. Existing mappings in the region are overwritten. 2303 */ 2304 void 2305 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2306 { 2307 while (count-- > 0) { 2308 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2309 va += PAGE_SIZE; 2310 m++; 2311 } 2312 } 2313 2314 /* 2315 * Remove page mappings from kernel virtual address space. Intended for 2316 * temporary mappings entered by moea64_qenter. 2317 */ 2318 void 2319 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2320 { 2321 while (count-- > 0) { 2322 moea64_kremove(mmu, va); 2323 va += PAGE_SIZE; 2324 } 2325 } 2326 2327 void 2328 moea64_release_vsid(uint64_t vsid) 2329 { 2330 int idx, mask; 2331 2332 mtx_lock(&moea64_slb_mutex); 2333 idx = vsid & (NVSIDS-1); 2334 mask = 1 << (idx % VSID_NBPW); 2335 idx /= VSID_NBPW; 2336 KASSERT(moea64_vsid_bitmap[idx] & mask, 2337 ("Freeing unallocated VSID %#jx", vsid)); 2338 moea64_vsid_bitmap[idx] &= ~mask; 2339 mtx_unlock(&moea64_slb_mutex); 2340 } 2341 2342 2343 void 2344 moea64_release(mmu_t mmu, pmap_t pmap) 2345 { 2346 2347 /* 2348 * Free segment registers' VSIDs 2349 */ 2350 #ifdef __powerpc64__ 2351 slb_free_tree(pmap); 2352 slb_free_user_cache(pmap->pm_slb); 2353 #else 2354 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2355 2356 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2357 #endif 2358 } 2359 2360 /* 2361 * Remove all pages mapped by the specified pmap 2362 */ 2363 void 2364 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2365 { 2366 struct pvo_entry *pvo, *tpvo; 2367 struct pvo_dlist tofree; 2368 2369 SLIST_INIT(&tofree); 2370 2371 PMAP_LOCK(pm); 2372 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2373 if (pvo->pvo_vaddr & PVO_WIRED) 2374 continue; 2375 2376 /* 2377 * For locking reasons, remove this from the page table and 2378 * pmap, but save delinking from the vm_page for a second 2379 * pass 2380 */ 2381 moea64_pvo_remove_from_pmap(mmu, pvo); 2382 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2383 } 2384 PMAP_UNLOCK(pm); 2385 2386 while (!SLIST_EMPTY(&tofree)) { 2387 pvo = SLIST_FIRST(&tofree); 2388 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2389 moea64_pvo_remove_from_page(mmu, pvo); 2390 free_pvo_entry(pvo); 2391 } 2392 } 2393 2394 /* 2395 * Remove the given range of addresses from the specified map. 2396 */ 2397 void 2398 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2399 { 2400 struct pvo_entry *pvo, *tpvo, key; 2401 struct pvo_dlist tofree; 2402 2403 /* 2404 * Perform an unsynchronized read. This is, however, safe. 2405 */ 2406 if (pm->pm_stats.resident_count == 0) 2407 return; 2408 2409 key.pvo_vaddr = sva; 2410 2411 SLIST_INIT(&tofree); 2412 2413 PMAP_LOCK(pm); 2414 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2415 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2416 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2417 2418 /* 2419 * For locking reasons, remove this from the page table and 2420 * pmap, but save delinking from the vm_page for a second 2421 * pass 2422 */ 2423 moea64_pvo_remove_from_pmap(mmu, pvo); 2424 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2425 } 2426 PMAP_UNLOCK(pm); 2427 2428 while (!SLIST_EMPTY(&tofree)) { 2429 pvo = SLIST_FIRST(&tofree); 2430 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2431 moea64_pvo_remove_from_page(mmu, pvo); 2432 free_pvo_entry(pvo); 2433 } 2434 } 2435 2436 /* 2437 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2438 * will reflect changes in pte's back to the vm_page. 2439 */ 2440 void 2441 moea64_remove_all(mmu_t mmu, vm_page_t m) 2442 { 2443 struct pvo_entry *pvo, *next_pvo; 2444 struct pvo_head freequeue; 2445 int wasdead; 2446 pmap_t pmap; 2447 2448 LIST_INIT(&freequeue); 2449 2450 PV_PAGE_LOCK(m); 2451 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2452 pmap = pvo->pvo_pmap; 2453 PMAP_LOCK(pmap); 2454 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2455 if (!wasdead) 2456 moea64_pvo_remove_from_pmap(mmu, pvo); 2457 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2458 if (!wasdead) 2459 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2460 PMAP_UNLOCK(pmap); 2461 2462 } 2463 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2464 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2465 PV_PAGE_UNLOCK(m); 2466 2467 /* Clean up UMA allocations */ 2468 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2469 free_pvo_entry(pvo); 2470 } 2471 2472 /* 2473 * Allocate a physical page of memory directly from the phys_avail map. 2474 * Can only be called from moea64_bootstrap before avail start and end are 2475 * calculated. 2476 */ 2477 vm_offset_t 2478 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2479 { 2480 vm_offset_t s, e; 2481 int i, j; 2482 2483 size = round_page(size); 2484 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2485 if (align != 0) 2486 s = roundup2(phys_avail[i], align); 2487 else 2488 s = phys_avail[i]; 2489 e = s + size; 2490 2491 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2492 continue; 2493 2494 if (s + size > platform_real_maxaddr()) 2495 continue; 2496 2497 if (s == phys_avail[i]) { 2498 phys_avail[i] += size; 2499 } else if (e == phys_avail[i + 1]) { 2500 phys_avail[i + 1] -= size; 2501 } else { 2502 for (j = phys_avail_count * 2; j > i; j -= 2) { 2503 phys_avail[j] = phys_avail[j - 2]; 2504 phys_avail[j + 1] = phys_avail[j - 1]; 2505 } 2506 2507 phys_avail[i + 3] = phys_avail[i + 1]; 2508 phys_avail[i + 1] = s; 2509 phys_avail[i + 2] = e; 2510 phys_avail_count++; 2511 } 2512 2513 return (s); 2514 } 2515 panic("moea64_bootstrap_alloc: could not allocate memory"); 2516 } 2517 2518 static int 2519 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2520 struct pvo_entry **oldpvop) 2521 { 2522 int first, err; 2523 struct pvo_entry *old_pvo; 2524 2525 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2526 2527 STAT_MOEA64(moea64_pvo_enter_calls++); 2528 2529 /* 2530 * Add to pmap list 2531 */ 2532 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2533 2534 if (old_pvo != NULL) { 2535 if (oldpvop != NULL) 2536 *oldpvop = old_pvo; 2537 return (EEXIST); 2538 } 2539 2540 /* 2541 * Remember if the list was empty and therefore will be the first 2542 * item. 2543 */ 2544 if (pvo_head != NULL) { 2545 if (LIST_FIRST(pvo_head) == NULL) 2546 first = 1; 2547 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2548 } 2549 2550 if (pvo->pvo_vaddr & PVO_WIRED) 2551 pvo->pvo_pmap->pm_stats.wired_count++; 2552 pvo->pvo_pmap->pm_stats.resident_count++; 2553 2554 /* 2555 * Insert it into the hardware page table 2556 */ 2557 err = MOEA64_PTE_INSERT(mmu, pvo); 2558 if (err != 0) { 2559 panic("moea64_pvo_enter: overflow"); 2560 } 2561 2562 STAT_MOEA64(moea64_pvo_entries++); 2563 2564 if (pvo->pvo_pmap == kernel_pmap) 2565 isync(); 2566 2567 #ifdef __powerpc64__ 2568 /* 2569 * Make sure all our bootstrap mappings are in the SLB as soon 2570 * as virtual memory is switched on. 2571 */ 2572 if (!pmap_bootstrapped) 2573 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2574 pvo->pvo_vaddr & PVO_LARGE); 2575 #endif 2576 2577 return (first ? ENOENT : 0); 2578 } 2579 2580 static void 2581 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2582 { 2583 struct vm_page *pg; 2584 int32_t refchg; 2585 2586 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2587 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2588 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2589 2590 /* 2591 * If there is an active pte entry, we need to deactivate it 2592 */ 2593 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2594 if (refchg < 0) { 2595 /* 2596 * If it was evicted from the page table, be pessimistic and 2597 * dirty the page. 2598 */ 2599 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2600 refchg = LPTE_CHG; 2601 else 2602 refchg = 0; 2603 } 2604 2605 /* 2606 * Update our statistics. 2607 */ 2608 pvo->pvo_pmap->pm_stats.resident_count--; 2609 if (pvo->pvo_vaddr & PVO_WIRED) 2610 pvo->pvo_pmap->pm_stats.wired_count--; 2611 2612 /* 2613 * Remove this PVO from the pmap list. 2614 */ 2615 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2616 2617 /* 2618 * Mark this for the next sweep 2619 */ 2620 pvo->pvo_vaddr |= PVO_DEAD; 2621 2622 /* Send RC bits to VM */ 2623 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2624 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2625 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2626 if (pg != NULL) { 2627 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2628 if (refchg & LPTE_CHG) 2629 vm_page_dirty(pg); 2630 if (refchg & LPTE_REF) 2631 vm_page_aflag_set(pg, PGA_REFERENCED); 2632 } 2633 } 2634 } 2635 2636 static inline void 2637 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2638 vm_page_t m) 2639 { 2640 2641 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2642 2643 /* Use NULL pmaps as a sentinel for races in page deletion */ 2644 if (pvo->pvo_pmap == NULL) 2645 return; 2646 pvo->pvo_pmap = NULL; 2647 2648 /* 2649 * Update vm about page writeability/executability if managed 2650 */ 2651 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2652 if (pvo->pvo_vaddr & PVO_MANAGED) { 2653 if (m != NULL) { 2654 LIST_REMOVE(pvo, pvo_vlink); 2655 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2656 vm_page_aflag_clear(m, 2657 PGA_WRITEABLE | PGA_EXECUTABLE); 2658 } 2659 } 2660 2661 STAT_MOEA64(moea64_pvo_entries--); 2662 STAT_MOEA64(moea64_pvo_remove_calls++); 2663 } 2664 2665 static void 2666 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2667 { 2668 vm_page_t pg = NULL; 2669 2670 if (pvo->pvo_vaddr & PVO_MANAGED) 2671 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2672 2673 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2674 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2675 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2676 } 2677 2678 static struct pvo_entry * 2679 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2680 { 2681 struct pvo_entry key; 2682 2683 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2684 2685 key.pvo_vaddr = va & ~ADDR_POFF; 2686 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2687 } 2688 2689 static boolean_t 2690 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2691 { 2692 struct pvo_entry *pvo; 2693 int64_t ret; 2694 boolean_t rv; 2695 2696 /* 2697 * See if this bit is stored in the page already. 2698 */ 2699 if (m->md.mdpg_attrs & ptebit) 2700 return (TRUE); 2701 2702 /* 2703 * Examine each PTE. Sync so that any pending REF/CHG bits are 2704 * flushed to the PTEs. 2705 */ 2706 rv = FALSE; 2707 powerpc_sync(); 2708 PV_PAGE_LOCK(m); 2709 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2710 ret = 0; 2711 2712 /* 2713 * See if this pvo has a valid PTE. if so, fetch the 2714 * REF/CHG bits from the valid PTE. If the appropriate 2715 * ptebit is set, return success. 2716 */ 2717 PMAP_LOCK(pvo->pvo_pmap); 2718 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2719 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2720 PMAP_UNLOCK(pvo->pvo_pmap); 2721 2722 if (ret > 0) { 2723 atomic_set_32(&m->md.mdpg_attrs, 2724 ret & (LPTE_CHG | LPTE_REF)); 2725 if (ret & ptebit) { 2726 rv = TRUE; 2727 break; 2728 } 2729 } 2730 } 2731 PV_PAGE_UNLOCK(m); 2732 2733 return (rv); 2734 } 2735 2736 static u_int 2737 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2738 { 2739 u_int count; 2740 struct pvo_entry *pvo; 2741 int64_t ret; 2742 2743 /* 2744 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2745 * we can reset the right ones). 2746 */ 2747 powerpc_sync(); 2748 2749 /* 2750 * For each pvo entry, clear the pte's ptebit. 2751 */ 2752 count = 0; 2753 PV_PAGE_LOCK(m); 2754 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2755 ret = 0; 2756 2757 PMAP_LOCK(pvo->pvo_pmap); 2758 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2759 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2760 PMAP_UNLOCK(pvo->pvo_pmap); 2761 2762 if (ret > 0 && (ret & ptebit)) 2763 count++; 2764 } 2765 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2766 PV_PAGE_UNLOCK(m); 2767 2768 return (count); 2769 } 2770 2771 boolean_t 2772 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2773 { 2774 struct pvo_entry *pvo, key; 2775 vm_offset_t ppa; 2776 int error = 0; 2777 2778 if (hw_direct_map && mem_valid(pa, size) == 0) 2779 return (0); 2780 2781 PMAP_LOCK(kernel_pmap); 2782 ppa = pa & ~ADDR_POFF; 2783 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2784 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2785 ppa < pa + size; ppa += PAGE_SIZE, 2786 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2787 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2788 error = EFAULT; 2789 break; 2790 } 2791 } 2792 PMAP_UNLOCK(kernel_pmap); 2793 2794 return (error); 2795 } 2796 2797 /* 2798 * Map a set of physical memory pages into the kernel virtual 2799 * address space. Return a pointer to where it is mapped. This 2800 * routine is intended to be used for mapping device memory, 2801 * NOT real memory. 2802 */ 2803 void * 2804 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2805 { 2806 vm_offset_t va, tmpva, ppa, offset; 2807 2808 ppa = trunc_page(pa); 2809 offset = pa & PAGE_MASK; 2810 size = roundup2(offset + size, PAGE_SIZE); 2811 2812 va = kva_alloc(size); 2813 2814 if (!va) 2815 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2816 2817 for (tmpva = va; size > 0;) { 2818 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2819 size -= PAGE_SIZE; 2820 tmpva += PAGE_SIZE; 2821 ppa += PAGE_SIZE; 2822 } 2823 2824 return ((void *)(va + offset)); 2825 } 2826 2827 void * 2828 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2829 { 2830 2831 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2832 } 2833 2834 void 2835 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2836 { 2837 vm_offset_t base, offset; 2838 2839 base = trunc_page(va); 2840 offset = va & PAGE_MASK; 2841 size = roundup2(offset + size, PAGE_SIZE); 2842 2843 kva_free(base, size); 2844 } 2845 2846 void 2847 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2848 { 2849 struct pvo_entry *pvo; 2850 vm_offset_t lim; 2851 vm_paddr_t pa; 2852 vm_size_t len; 2853 2854 if (__predict_false(pm == NULL)) 2855 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2856 2857 PMAP_LOCK(pm); 2858 while (sz > 0) { 2859 lim = round_page(va+1); 2860 len = MIN(lim - va, sz); 2861 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2862 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2863 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2864 moea64_syncicache(mmu, pm, va, pa, len); 2865 } 2866 va += len; 2867 sz -= len; 2868 } 2869 PMAP_UNLOCK(pm); 2870 } 2871 2872 void 2873 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2874 { 2875 2876 *va = (void *)(uintptr_t)pa; 2877 } 2878 2879 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2880 2881 void 2882 moea64_scan_init(mmu_t mmu) 2883 { 2884 struct pvo_entry *pvo; 2885 vm_offset_t va; 2886 int i; 2887 2888 if (!do_minidump) { 2889 /* Initialize phys. segments for dumpsys(). */ 2890 memset(&dump_map, 0, sizeof(dump_map)); 2891 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2892 for (i = 0; i < pregions_sz; i++) { 2893 dump_map[i].pa_start = pregions[i].mr_start; 2894 dump_map[i].pa_size = pregions[i].mr_size; 2895 } 2896 return; 2897 } 2898 2899 /* Virtual segments for minidumps: */ 2900 memset(&dump_map, 0, sizeof(dump_map)); 2901 2902 /* 1st: kernel .data and .bss. */ 2903 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2904 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2905 dump_map[0].pa_start; 2906 2907 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2908 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2909 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2910 2911 /* 3rd: kernel VM. */ 2912 va = dump_map[1].pa_start + dump_map[1].pa_size; 2913 /* Find start of next chunk (from va). */ 2914 while (va < virtual_end) { 2915 /* Don't dump the buffer cache. */ 2916 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2917 va = kmi.buffer_eva; 2918 continue; 2919 } 2920 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2921 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2922 break; 2923 va += PAGE_SIZE; 2924 } 2925 if (va < virtual_end) { 2926 dump_map[2].pa_start = va; 2927 va += PAGE_SIZE; 2928 /* Find last page in chunk. */ 2929 while (va < virtual_end) { 2930 /* Don't run into the buffer cache. */ 2931 if (va == kmi.buffer_sva) 2932 break; 2933 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2934 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2935 break; 2936 va += PAGE_SIZE; 2937 } 2938 dump_map[2].pa_size = va - dump_map[2].pa_start; 2939 } 2940 } 2941 2942