1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 69 #include <sys/kdb.h> 70 71 #include <dev/ofw/openfirm.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_kern.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_phys.h> 78 #include <vm/vm_map.h> 79 #include <vm/vm_object.h> 80 #include <vm/vm_extern.h> 81 #include <vm/vm_pageout.h> 82 #include <vm/uma.h> 83 84 #include <machine/_inttypes.h> 85 #include <machine/cpu.h> 86 #include <machine/platform.h> 87 #include <machine/frame.h> 88 #include <machine/md_var.h> 89 #include <machine/psl.h> 90 #include <machine/bat.h> 91 #include <machine/hid.h> 92 #include <machine/pte.h> 93 #include <machine/sr.h> 94 #include <machine/trap.h> 95 #include <machine/mmuvar.h> 96 97 #include "mmu_oea64.h" 98 #include "mmu_if.h" 99 #include "moea64_if.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* 112 * Locking semantics: 113 * 114 * There are two locks of interest: the page locks and the pmap locks, which 115 * protect their individual PVO lists and are locked in that order. The contents 116 * of all PVO entries are protected by the locks of their respective pmaps. 117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 118 * into any list. 119 * 120 */ 121 122 #define PV_LOCK_PER_DOM PA_LOCK_COUNT*3 123 #define PV_LOCK_COUNT PV_LOCK_PER_DOM*MAXMEMDOM 124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 125 126 /* 127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 129 * index at (N << 45). 130 */ 131 #ifdef __powerpc64__ 132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \ 133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM) 134 #else 135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 136 #endif 137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 144 145 struct ofw_map { 146 cell_t om_va; 147 cell_t om_len; 148 uint64_t om_pa; 149 cell_t om_mode; 150 }; 151 152 extern unsigned char _etext[]; 153 extern unsigned char _end[]; 154 155 extern void *slbtrap, *slbtrapend; 156 157 /* 158 * Map of physical memory regions. 159 */ 160 static struct mem_region *regions; 161 static struct mem_region *pregions; 162 static struct numa_mem_region *numa_pregions; 163 static u_int phys_avail_count; 164 static int regions_sz, pregions_sz, numapregions_sz; 165 166 extern void bs_remap_earlyboot(void); 167 168 /* 169 * Lock for the SLB tables. 170 */ 171 struct mtx moea64_slb_mutex; 172 173 /* 174 * PTEG data. 175 */ 176 u_long moea64_pteg_count; 177 u_long moea64_pteg_mask; 178 179 /* 180 * PVO data. 181 */ 182 183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 184 185 static struct pvo_entry *moea64_bpvo_pool; 186 static int moea64_bpvo_pool_index = 0; 187 static int moea64_bpvo_pool_size = 327680; 188 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 190 &moea64_bpvo_pool_index, 0, ""); 191 192 #define VSID_NBPW (sizeof(u_int32_t) * 8) 193 #ifdef __powerpc64__ 194 #define NVSIDS (NPMAPS * 16) 195 #define VSID_HASHMASK 0xffffffffUL 196 #else 197 #define NVSIDS NPMAPS 198 #define VSID_HASHMASK 0xfffffUL 199 #endif 200 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 201 202 static boolean_t moea64_initialized = FALSE; 203 204 #ifdef MOEA64_STATS 205 /* 206 * Statistics. 207 */ 208 u_int moea64_pte_valid = 0; 209 u_int moea64_pte_overflow = 0; 210 u_int moea64_pvo_entries = 0; 211 u_int moea64_pvo_enter_calls = 0; 212 u_int moea64_pvo_remove_calls = 0; 213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 214 &moea64_pte_valid, 0, ""); 215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 216 &moea64_pte_overflow, 0, ""); 217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 218 &moea64_pvo_entries, 0, ""); 219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 220 &moea64_pvo_enter_calls, 0, ""); 221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 222 &moea64_pvo_remove_calls, 0, ""); 223 #endif 224 225 vm_offset_t moea64_scratchpage_va[2]; 226 struct pvo_entry *moea64_scratchpage_pvo[2]; 227 struct mtx moea64_scratchpage_mtx; 228 229 uint64_t moea64_large_page_mask = 0; 230 uint64_t moea64_large_page_size = 0; 231 int moea64_large_page_shift = 0; 232 233 /* 234 * PVO calls. 235 */ 236 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 237 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 238 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 239 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 240 static void moea64_pvo_remove_from_page_locked(mmu_t mmu, 241 struct pvo_entry *pvo, vm_page_t m); 242 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 243 244 /* 245 * Utility routines. 246 */ 247 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 248 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 249 static void moea64_kremove(mmu_t, vm_offset_t); 250 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 251 vm_paddr_t pa, vm_size_t sz); 252 static void moea64_pmap_init_qpages(void); 253 254 /* 255 * Kernel MMU interface 256 */ 257 void moea64_clear_modify(mmu_t, vm_page_t); 258 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 259 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 260 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 261 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 262 u_int flags, int8_t psind); 263 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 264 vm_prot_t); 265 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 266 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 267 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 268 void moea64_init(mmu_t); 269 boolean_t moea64_is_modified(mmu_t, vm_page_t); 270 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 271 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 272 int moea64_ts_referenced(mmu_t, vm_page_t); 273 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 274 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 275 void moea64_page_init(mmu_t, vm_page_t); 276 int moea64_page_wired_mappings(mmu_t, vm_page_t); 277 void moea64_pinit(mmu_t, pmap_t); 278 void moea64_pinit0(mmu_t, pmap_t); 279 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 280 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 281 void moea64_qremove(mmu_t, vm_offset_t, int); 282 void moea64_release(mmu_t, pmap_t); 283 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 284 void moea64_remove_pages(mmu_t, pmap_t); 285 void moea64_remove_all(mmu_t, vm_page_t); 286 void moea64_remove_write(mmu_t, vm_page_t); 287 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 288 void moea64_zero_page(mmu_t, vm_page_t); 289 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 290 void moea64_activate(mmu_t, struct thread *); 291 void moea64_deactivate(mmu_t, struct thread *); 292 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 293 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 294 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 295 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 296 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 297 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 298 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 299 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 300 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 301 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 302 void **va); 303 void moea64_scan_init(mmu_t mmu); 304 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 305 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 306 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm, 307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 308 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 309 int *is_user, vm_offset_t *decoded_addr); 310 311 312 static mmu_method_t moea64_methods[] = { 313 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 314 MMUMETHOD(mmu_copy_page, moea64_copy_page), 315 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 316 MMUMETHOD(mmu_enter, moea64_enter), 317 MMUMETHOD(mmu_enter_object, moea64_enter_object), 318 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 319 MMUMETHOD(mmu_extract, moea64_extract), 320 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 321 MMUMETHOD(mmu_init, moea64_init), 322 MMUMETHOD(mmu_is_modified, moea64_is_modified), 323 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 324 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 325 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 326 MMUMETHOD(mmu_map, moea64_map), 327 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 328 MMUMETHOD(mmu_page_init, moea64_page_init), 329 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 330 MMUMETHOD(mmu_pinit, moea64_pinit), 331 MMUMETHOD(mmu_pinit0, moea64_pinit0), 332 MMUMETHOD(mmu_protect, moea64_protect), 333 MMUMETHOD(mmu_qenter, moea64_qenter), 334 MMUMETHOD(mmu_qremove, moea64_qremove), 335 MMUMETHOD(mmu_release, moea64_release), 336 MMUMETHOD(mmu_remove, moea64_remove), 337 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 338 MMUMETHOD(mmu_remove_all, moea64_remove_all), 339 MMUMETHOD(mmu_remove_write, moea64_remove_write), 340 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 341 MMUMETHOD(mmu_unwire, moea64_unwire), 342 MMUMETHOD(mmu_zero_page, moea64_zero_page), 343 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 344 MMUMETHOD(mmu_activate, moea64_activate), 345 MMUMETHOD(mmu_deactivate, moea64_deactivate), 346 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 347 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 348 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 349 350 /* Internal interfaces */ 351 MMUMETHOD(mmu_mapdev, moea64_mapdev), 352 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 353 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 354 MMUMETHOD(mmu_kextract, moea64_kextract), 355 MMUMETHOD(mmu_kenter, moea64_kenter), 356 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 357 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 358 MMUMETHOD(mmu_scan_init, moea64_scan_init), 359 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 360 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr), 361 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr), 362 363 { 0, 0 } 364 }; 365 366 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 367 368 static struct pvo_head * 369 vm_page_to_pvoh(vm_page_t m) 370 { 371 372 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 373 return (&m->md.mdpg_pvoh); 374 } 375 376 static struct pvo_entry * 377 alloc_pvo_entry(int bootstrap) 378 { 379 struct pvo_entry *pvo; 380 381 if (!moea64_initialized || bootstrap) { 382 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 383 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 384 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 385 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 386 } 387 pvo = &moea64_bpvo_pool[ 388 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 389 bzero(pvo, sizeof(*pvo)); 390 pvo->pvo_vaddr = PVO_BOOTSTRAP; 391 } else 392 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 393 394 return (pvo); 395 } 396 397 398 static void 399 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 400 { 401 uint64_t vsid; 402 uint64_t hash; 403 int shift; 404 405 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 406 407 pvo->pvo_pmap = pmap; 408 va &= ~ADDR_POFF; 409 pvo->pvo_vaddr |= va; 410 vsid = va_to_vsid(pmap, va); 411 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 412 | (vsid << 16); 413 414 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 415 ADDR_PIDX_SHFT; 416 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 417 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 418 } 419 420 static void 421 free_pvo_entry(struct pvo_entry *pvo) 422 { 423 424 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 425 uma_zfree(moea64_pvo_zone, pvo); 426 } 427 428 void 429 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 430 { 431 432 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 433 LPTE_AVPN_MASK; 434 lpte->pte_hi |= LPTE_VALID; 435 436 if (pvo->pvo_vaddr & PVO_LARGE) 437 lpte->pte_hi |= LPTE_BIG; 438 if (pvo->pvo_vaddr & PVO_WIRED) 439 lpte->pte_hi |= LPTE_WIRED; 440 if (pvo->pvo_vaddr & PVO_HID) 441 lpte->pte_hi |= LPTE_HID; 442 443 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 444 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 445 lpte->pte_lo |= LPTE_BW; 446 else 447 lpte->pte_lo |= LPTE_BR; 448 449 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 450 lpte->pte_lo |= LPTE_NOEXEC; 451 } 452 453 static __inline uint64_t 454 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 455 { 456 uint64_t pte_lo; 457 int i; 458 459 if (ma != VM_MEMATTR_DEFAULT) { 460 switch (ma) { 461 case VM_MEMATTR_UNCACHEABLE: 462 return (LPTE_I | LPTE_G); 463 case VM_MEMATTR_CACHEABLE: 464 return (LPTE_M); 465 case VM_MEMATTR_WRITE_COMBINING: 466 case VM_MEMATTR_WRITE_BACK: 467 case VM_MEMATTR_PREFETCHABLE: 468 return (LPTE_I); 469 case VM_MEMATTR_WRITE_THROUGH: 470 return (LPTE_W | LPTE_M); 471 } 472 } 473 474 /* 475 * Assume the page is cache inhibited and access is guarded unless 476 * it's in our available memory array. 477 */ 478 pte_lo = LPTE_I | LPTE_G; 479 for (i = 0; i < pregions_sz; i++) { 480 if ((pa >= pregions[i].mr_start) && 481 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 482 pte_lo &= ~(LPTE_I | LPTE_G); 483 pte_lo |= LPTE_M; 484 break; 485 } 486 } 487 488 return pte_lo; 489 } 490 491 /* 492 * Quick sort callout for comparing memory regions. 493 */ 494 static int om_cmp(const void *a, const void *b); 495 496 static int 497 om_cmp(const void *a, const void *b) 498 { 499 const struct ofw_map *mapa; 500 const struct ofw_map *mapb; 501 502 mapa = a; 503 mapb = b; 504 if (mapa->om_pa < mapb->om_pa) 505 return (-1); 506 else if (mapa->om_pa > mapb->om_pa) 507 return (1); 508 else 509 return (0); 510 } 511 512 static void 513 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 514 { 515 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 516 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 517 struct pvo_entry *pvo; 518 register_t msr; 519 vm_offset_t off; 520 vm_paddr_t pa_base; 521 int i, j; 522 523 bzero(translations, sz); 524 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 525 sizeof(acells)); 526 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 527 panic("moea64_bootstrap: can't get ofw translations"); 528 529 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 530 sz /= sizeof(cell_t); 531 for (i = 0, j = 0; i < sz; j++) { 532 translations[j].om_va = trans_cells[i++]; 533 translations[j].om_len = trans_cells[i++]; 534 translations[j].om_pa = trans_cells[i++]; 535 if (acells == 2) { 536 translations[j].om_pa <<= 32; 537 translations[j].om_pa |= trans_cells[i++]; 538 } 539 translations[j].om_mode = trans_cells[i++]; 540 } 541 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 542 i, sz)); 543 544 sz = j; 545 qsort(translations, sz, sizeof (*translations), om_cmp); 546 547 for (i = 0; i < sz; i++) { 548 pa_base = translations[i].om_pa; 549 #ifndef __powerpc64__ 550 if ((translations[i].om_pa >> 32) != 0) 551 panic("OFW translations above 32-bit boundary!"); 552 #endif 553 554 if (pa_base % PAGE_SIZE) 555 panic("OFW translation not page-aligned (phys)!"); 556 if (translations[i].om_va % PAGE_SIZE) 557 panic("OFW translation not page-aligned (virt)!"); 558 559 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 560 pa_base, translations[i].om_va, translations[i].om_len); 561 562 /* Now enter the pages for this mapping */ 563 564 DISABLE_TRANS(msr); 565 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 566 /* If this address is direct-mapped, skip remapping */ 567 if (hw_direct_map && 568 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 569 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 570 == LPTE_M) 571 continue; 572 573 PMAP_LOCK(kernel_pmap); 574 pvo = moea64_pvo_find_va(kernel_pmap, 575 translations[i].om_va + off); 576 PMAP_UNLOCK(kernel_pmap); 577 if (pvo != NULL) 578 continue; 579 580 moea64_kenter(mmup, translations[i].om_va + off, 581 pa_base + off); 582 } 583 ENABLE_TRANS(msr); 584 } 585 } 586 587 #ifdef __powerpc64__ 588 static void 589 moea64_probe_large_page(void) 590 { 591 uint16_t pvr = mfpvr() >> 16; 592 593 switch (pvr) { 594 case IBM970: 595 case IBM970FX: 596 case IBM970MP: 597 powerpc_sync(); isync(); 598 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 599 powerpc_sync(); isync(); 600 601 /* FALLTHROUGH */ 602 default: 603 if (moea64_large_page_size == 0) { 604 moea64_large_page_size = 0x1000000; /* 16 MB */ 605 moea64_large_page_shift = 24; 606 } 607 } 608 609 moea64_large_page_mask = moea64_large_page_size - 1; 610 } 611 612 static void 613 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 614 { 615 struct slb *cache; 616 struct slb entry; 617 uint64_t esid, slbe; 618 uint64_t i; 619 620 cache = PCPU_GET(aim.slb); 621 esid = va >> ADDR_SR_SHFT; 622 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 623 624 for (i = 0; i < 64; i++) { 625 if (cache[i].slbe == (slbe | i)) 626 return; 627 } 628 629 entry.slbe = slbe; 630 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 631 if (large) 632 entry.slbv |= SLBV_L; 633 634 slb_insert_kernel(entry.slbe, entry.slbv); 635 } 636 #endif 637 638 static void 639 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 640 vm_offset_t kernelend) 641 { 642 struct pvo_entry *pvo; 643 register_t msr; 644 vm_paddr_t pa, pkernelstart, pkernelend; 645 vm_offset_t size, off; 646 uint64_t pte_lo; 647 int i; 648 649 if (moea64_large_page_size == 0) 650 hw_direct_map = 0; 651 652 DISABLE_TRANS(msr); 653 if (hw_direct_map) { 654 PMAP_LOCK(kernel_pmap); 655 for (i = 0; i < pregions_sz; i++) { 656 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 657 pregions[i].mr_size; pa += moea64_large_page_size) { 658 pte_lo = LPTE_M; 659 660 pvo = alloc_pvo_entry(1 /* bootstrap */); 661 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 662 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa)); 663 664 /* 665 * Set memory access as guarded if prefetch within 666 * the page could exit the available physmem area. 667 */ 668 if (pa & moea64_large_page_mask) { 669 pa &= moea64_large_page_mask; 670 pte_lo |= LPTE_G; 671 } 672 if (pa + moea64_large_page_size > 673 pregions[i].mr_start + pregions[i].mr_size) 674 pte_lo |= LPTE_G; 675 676 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 677 VM_PROT_EXECUTE; 678 pvo->pvo_pte.pa = pa | pte_lo; 679 moea64_pvo_enter(mmup, pvo, NULL, NULL); 680 } 681 } 682 PMAP_UNLOCK(kernel_pmap); 683 } 684 685 /* 686 * Make sure the kernel and BPVO pool stay mapped on systems either 687 * without a direct map or on which the kernel is not already executing 688 * out of the direct-mapped region. 689 */ 690 if (kernelstart < DMAP_BASE_ADDRESS) { 691 /* 692 * For pre-dmap execution, we need to use identity mapping 693 * because we will be operating with the mmu on but in the 694 * wrong address configuration until we __restartkernel(). 695 */ 696 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 697 pa += PAGE_SIZE) 698 moea64_kenter(mmup, pa, pa); 699 } else if (!hw_direct_map) { 700 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 701 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 702 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 703 pa += PAGE_SIZE) 704 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 705 } 706 707 if (!hw_direct_map) { 708 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 709 off = (vm_offset_t)(moea64_bpvo_pool); 710 for (pa = off; pa < off + size; pa += PAGE_SIZE) 711 moea64_kenter(mmup, pa, pa); 712 713 /* Map exception vectors */ 714 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 715 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa); 716 } 717 ENABLE_TRANS(msr); 718 719 /* 720 * Allow user to override unmapped_buf_allowed for testing. 721 * XXXKIB Only direct map implementation was tested. 722 */ 723 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 724 &unmapped_buf_allowed)) 725 unmapped_buf_allowed = hw_direct_map; 726 } 727 728 /* Quick sort callout for comparing physical addresses. */ 729 static int 730 pa_cmp(const void *a, const void *b) 731 { 732 const vm_paddr_t *pa = a, *pb = b; 733 734 if (*pa < *pb) 735 return (-1); 736 else if (*pa > *pb) 737 return (1); 738 else 739 return (0); 740 } 741 742 void 743 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 744 { 745 int i, j; 746 vm_size_t physsz, hwphyssz; 747 vm_paddr_t kernelphysstart, kernelphysend; 748 int rm_pavail; 749 750 #ifndef __powerpc64__ 751 /* We don't have a direct map since there is no BAT */ 752 hw_direct_map = 0; 753 754 /* Make sure battable is zero, since we have no BAT */ 755 for (i = 0; i < 16; i++) { 756 battable[i].batu = 0; 757 battable[i].batl = 0; 758 } 759 #else 760 moea64_probe_large_page(); 761 762 /* Use a direct map if we have large page support */ 763 if (moea64_large_page_size > 0) 764 hw_direct_map = 1; 765 else 766 hw_direct_map = 0; 767 768 /* Install trap handlers for SLBs */ 769 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 770 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 771 __syncicache((void *)EXC_DSE, 0x80); 772 __syncicache((void *)EXC_ISE, 0x80); 773 #endif 774 775 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 776 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 777 778 /* Get physical memory regions from firmware */ 779 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 780 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 781 782 if (PHYS_AVAIL_ENTRIES < regions_sz) 783 panic("moea64_bootstrap: phys_avail too small"); 784 785 phys_avail_count = 0; 786 physsz = 0; 787 hwphyssz = 0; 788 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 789 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 790 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 791 regions[i].mr_start, regions[i].mr_start + 792 regions[i].mr_size, regions[i].mr_size); 793 if (hwphyssz != 0 && 794 (physsz + regions[i].mr_size) >= hwphyssz) { 795 if (physsz < hwphyssz) { 796 phys_avail[j] = regions[i].mr_start; 797 phys_avail[j + 1] = regions[i].mr_start + 798 hwphyssz - physsz; 799 physsz = hwphyssz; 800 phys_avail_count++; 801 } 802 break; 803 } 804 phys_avail[j] = regions[i].mr_start; 805 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 806 phys_avail_count++; 807 physsz += regions[i].mr_size; 808 } 809 810 /* Check for overlap with the kernel and exception vectors */ 811 rm_pavail = 0; 812 for (j = 0; j < 2*phys_avail_count; j+=2) { 813 if (phys_avail[j] < EXC_LAST) 814 phys_avail[j] += EXC_LAST; 815 816 if (phys_avail[j] >= kernelphysstart && 817 phys_avail[j+1] <= kernelphysend) { 818 phys_avail[j] = phys_avail[j+1] = ~0; 819 rm_pavail++; 820 continue; 821 } 822 823 if (kernelphysstart >= phys_avail[j] && 824 kernelphysstart < phys_avail[j+1]) { 825 if (kernelphysend < phys_avail[j+1]) { 826 phys_avail[2*phys_avail_count] = 827 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 828 phys_avail[2*phys_avail_count + 1] = 829 phys_avail[j+1]; 830 phys_avail_count++; 831 } 832 833 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 834 } 835 836 if (kernelphysend >= phys_avail[j] && 837 kernelphysend < phys_avail[j+1]) { 838 if (kernelphysstart > phys_avail[j]) { 839 phys_avail[2*phys_avail_count] = phys_avail[j]; 840 phys_avail[2*phys_avail_count + 1] = 841 kernelphysstart & ~PAGE_MASK; 842 phys_avail_count++; 843 } 844 845 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 846 PAGE_SIZE; 847 } 848 } 849 850 /* Remove physical available regions marked for removal (~0) */ 851 if (rm_pavail) { 852 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 853 pa_cmp); 854 phys_avail_count -= rm_pavail; 855 for (i = 2*phys_avail_count; 856 i < 2*(phys_avail_count + rm_pavail); i+=2) 857 phys_avail[i] = phys_avail[i+1] = 0; 858 } 859 860 physmem = btoc(physsz); 861 862 #ifdef PTEGCOUNT 863 moea64_pteg_count = PTEGCOUNT; 864 #else 865 moea64_pteg_count = 0x1000; 866 867 while (moea64_pteg_count < physmem) 868 moea64_pteg_count <<= 1; 869 870 moea64_pteg_count >>= 1; 871 #endif /* PTEGCOUNT */ 872 } 873 874 void 875 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 876 { 877 int i; 878 879 /* 880 * Set PTEG mask 881 */ 882 moea64_pteg_mask = moea64_pteg_count - 1; 883 884 /* 885 * Initialize SLB table lock and page locks 886 */ 887 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 888 for (i = 0; i < PV_LOCK_COUNT; i++) 889 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 890 891 /* 892 * Initialise the bootstrap pvo pool. 893 */ 894 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 895 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 896 moea64_bpvo_pool_index = 0; 897 898 /* Place at address usable through the direct map */ 899 if (hw_direct_map) 900 moea64_bpvo_pool = (struct pvo_entry *) 901 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 902 903 /* 904 * Make sure kernel vsid is allocated as well as VSID 0. 905 */ 906 #ifndef __powerpc64__ 907 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 908 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 909 moea64_vsid_bitmap[0] |= 1; 910 #endif 911 912 /* 913 * Initialize the kernel pmap (which is statically allocated). 914 */ 915 #ifdef __powerpc64__ 916 for (i = 0; i < 64; i++) { 917 pcpup->pc_aim.slb[i].slbv = 0; 918 pcpup->pc_aim.slb[i].slbe = 0; 919 } 920 #else 921 for (i = 0; i < 16; i++) 922 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 923 #endif 924 925 kernel_pmap->pmap_phys = kernel_pmap; 926 CPU_FILL(&kernel_pmap->pm_active); 927 RB_INIT(&kernel_pmap->pmap_pvo); 928 929 PMAP_LOCK_INIT(kernel_pmap); 930 931 /* 932 * Now map in all the other buffers we allocated earlier 933 */ 934 935 moea64_setup_direct_map(mmup, kernelstart, kernelend); 936 } 937 938 void 939 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 940 { 941 ihandle_t mmui; 942 phandle_t chosen; 943 phandle_t mmu; 944 ssize_t sz; 945 int i; 946 vm_offset_t pa, va; 947 void *dpcpu; 948 949 /* 950 * Set up the Open Firmware pmap and add its mappings if not in real 951 * mode. 952 */ 953 954 chosen = OF_finddevice("/chosen"); 955 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 956 mmu = OF_instance_to_package(mmui); 957 if (mmu == -1 || 958 (sz = OF_getproplen(mmu, "translations")) == -1) 959 sz = 0; 960 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 961 panic("moea64_bootstrap: too many ofw translations"); 962 963 if (sz > 0) 964 moea64_add_ofw_mappings(mmup, mmu, sz); 965 } 966 967 /* 968 * Calculate the last available physical address. 969 */ 970 Maxmem = 0; 971 for (i = 0; phys_avail[i + 2] != 0; i += 2) 972 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 973 974 /* 975 * Initialize MMU. 976 */ 977 MMU_CPU_BOOTSTRAP(mmup,0); 978 mtmsr(mfmsr() | PSL_DR | PSL_IR); 979 pmap_bootstrapped++; 980 981 /* 982 * Set the start and end of kva. 983 */ 984 virtual_avail = VM_MIN_KERNEL_ADDRESS; 985 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 986 987 /* 988 * Map the entire KVA range into the SLB. We must not fault there. 989 */ 990 #ifdef __powerpc64__ 991 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 992 moea64_bootstrap_slb_prefault(va, 0); 993 #endif 994 995 /* 996 * Remap any early IO mappings (console framebuffer, etc.) 997 */ 998 bs_remap_earlyboot(); 999 1000 /* 1001 * Figure out how far we can extend virtual_end into segment 16 1002 * without running into existing mappings. Segment 16 is guaranteed 1003 * to contain neither RAM nor devices (at least on Apple hardware), 1004 * but will generally contain some OFW mappings we should not 1005 * step on. 1006 */ 1007 1008 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1009 PMAP_LOCK(kernel_pmap); 1010 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1011 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1012 virtual_end += PAGE_SIZE; 1013 PMAP_UNLOCK(kernel_pmap); 1014 #endif 1015 1016 /* 1017 * Allocate a kernel stack with a guard page for thread0 and map it 1018 * into the kernel page map. 1019 */ 1020 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1021 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1022 virtual_avail = va + kstack_pages * PAGE_SIZE; 1023 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1024 thread0.td_kstack = va; 1025 thread0.td_kstack_pages = kstack_pages; 1026 for (i = 0; i < kstack_pages; i++) { 1027 moea64_kenter(mmup, va, pa); 1028 pa += PAGE_SIZE; 1029 va += PAGE_SIZE; 1030 } 1031 1032 /* 1033 * Allocate virtual address space for the message buffer. 1034 */ 1035 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1036 msgbufp = (struct msgbuf *)virtual_avail; 1037 va = virtual_avail; 1038 virtual_avail += round_page(msgbufsize); 1039 while (va < virtual_avail) { 1040 moea64_kenter(mmup, va, pa); 1041 pa += PAGE_SIZE; 1042 va += PAGE_SIZE; 1043 } 1044 1045 /* 1046 * Allocate virtual address space for the dynamic percpu area. 1047 */ 1048 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1049 dpcpu = (void *)virtual_avail; 1050 va = virtual_avail; 1051 virtual_avail += DPCPU_SIZE; 1052 while (va < virtual_avail) { 1053 moea64_kenter(mmup, va, pa); 1054 pa += PAGE_SIZE; 1055 va += PAGE_SIZE; 1056 } 1057 dpcpu_init(dpcpu, curcpu); 1058 1059 /* 1060 * Allocate some things for page zeroing. We put this directly 1061 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1062 * of the PVO book-keeping or other parts of the VM system 1063 * from even knowing that this hack exists. 1064 */ 1065 1066 if (!hw_direct_map) { 1067 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1068 MTX_DEF); 1069 for (i = 0; i < 2; i++) { 1070 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1071 virtual_end -= PAGE_SIZE; 1072 1073 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 1074 1075 PMAP_LOCK(kernel_pmap); 1076 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1077 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1078 PMAP_UNLOCK(kernel_pmap); 1079 } 1080 } 1081 1082 numa_mem_regions(&numa_pregions, &numapregions_sz); 1083 } 1084 1085 static void 1086 moea64_pmap_init_qpages(void) 1087 { 1088 struct pcpu *pc; 1089 int i; 1090 1091 if (hw_direct_map) 1092 return; 1093 1094 CPU_FOREACH(i) { 1095 pc = pcpu_find(i); 1096 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1097 if (pc->pc_qmap_addr == 0) 1098 panic("pmap_init_qpages: unable to allocate KVA"); 1099 PMAP_LOCK(kernel_pmap); 1100 pc->pc_aim.qmap_pvo = 1101 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1102 PMAP_UNLOCK(kernel_pmap); 1103 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1104 } 1105 } 1106 1107 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1108 1109 /* 1110 * Activate a user pmap. This mostly involves setting some non-CPU 1111 * state. 1112 */ 1113 void 1114 moea64_activate(mmu_t mmu, struct thread *td) 1115 { 1116 pmap_t pm; 1117 1118 pm = &td->td_proc->p_vmspace->vm_pmap; 1119 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1120 1121 #ifdef __powerpc64__ 1122 PCPU_SET(aim.userslb, pm->pm_slb); 1123 __asm __volatile("slbmte %0, %1; isync" :: 1124 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1125 #else 1126 PCPU_SET(curpmap, pm->pmap_phys); 1127 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1128 #endif 1129 } 1130 1131 void 1132 moea64_deactivate(mmu_t mmu, struct thread *td) 1133 { 1134 pmap_t pm; 1135 1136 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1137 1138 pm = &td->td_proc->p_vmspace->vm_pmap; 1139 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1140 #ifdef __powerpc64__ 1141 PCPU_SET(aim.userslb, NULL); 1142 #else 1143 PCPU_SET(curpmap, NULL); 1144 #endif 1145 } 1146 1147 void 1148 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1149 { 1150 struct pvo_entry key, *pvo; 1151 vm_page_t m; 1152 int64_t refchg; 1153 1154 key.pvo_vaddr = sva; 1155 PMAP_LOCK(pm); 1156 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1157 pvo != NULL && PVO_VADDR(pvo) < eva; 1158 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1159 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1160 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1161 pvo); 1162 pvo->pvo_vaddr &= ~PVO_WIRED; 1163 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1164 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1165 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1166 if (refchg < 0) 1167 refchg = LPTE_CHG; 1168 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1169 1170 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1171 if (refchg & LPTE_CHG) 1172 vm_page_dirty(m); 1173 if (refchg & LPTE_REF) 1174 vm_page_aflag_set(m, PGA_REFERENCED); 1175 } 1176 pm->pm_stats.wired_count--; 1177 } 1178 PMAP_UNLOCK(pm); 1179 } 1180 1181 /* 1182 * This goes through and sets the physical address of our 1183 * special scratch PTE to the PA we want to zero or copy. Because 1184 * of locking issues (this can get called in pvo_enter() by 1185 * the UMA allocator), we can't use most other utility functions here 1186 */ 1187 1188 static __inline 1189 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) 1190 { 1191 struct pvo_entry *pvo; 1192 1193 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1194 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1195 1196 pvo = moea64_scratchpage_pvo[which]; 1197 PMAP_LOCK(pvo->pvo_pmap); 1198 pvo->pvo_pte.pa = 1199 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1200 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE); 1201 PMAP_UNLOCK(pvo->pvo_pmap); 1202 isync(); 1203 } 1204 1205 void 1206 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1207 { 1208 vm_offset_t dst; 1209 vm_offset_t src; 1210 1211 dst = VM_PAGE_TO_PHYS(mdst); 1212 src = VM_PAGE_TO_PHYS(msrc); 1213 1214 if (hw_direct_map) { 1215 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1216 PAGE_SIZE); 1217 } else { 1218 mtx_lock(&moea64_scratchpage_mtx); 1219 1220 moea64_set_scratchpage_pa(mmu, 0, src); 1221 moea64_set_scratchpage_pa(mmu, 1, dst); 1222 1223 bcopy((void *)moea64_scratchpage_va[0], 1224 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1225 1226 mtx_unlock(&moea64_scratchpage_mtx); 1227 } 1228 } 1229 1230 static inline void 1231 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1232 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1233 { 1234 void *a_cp, *b_cp; 1235 vm_offset_t a_pg_offset, b_pg_offset; 1236 int cnt; 1237 1238 while (xfersize > 0) { 1239 a_pg_offset = a_offset & PAGE_MASK; 1240 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1241 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1242 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1243 a_pg_offset; 1244 b_pg_offset = b_offset & PAGE_MASK; 1245 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1246 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1247 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1248 b_pg_offset; 1249 bcopy(a_cp, b_cp, cnt); 1250 a_offset += cnt; 1251 b_offset += cnt; 1252 xfersize -= cnt; 1253 } 1254 } 1255 1256 static inline void 1257 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1258 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1259 { 1260 void *a_cp, *b_cp; 1261 vm_offset_t a_pg_offset, b_pg_offset; 1262 int cnt; 1263 1264 mtx_lock(&moea64_scratchpage_mtx); 1265 while (xfersize > 0) { 1266 a_pg_offset = a_offset & PAGE_MASK; 1267 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1268 moea64_set_scratchpage_pa(mmu, 0, 1269 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1270 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1271 b_pg_offset = b_offset & PAGE_MASK; 1272 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1273 moea64_set_scratchpage_pa(mmu, 1, 1274 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1275 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1276 bcopy(a_cp, b_cp, cnt); 1277 a_offset += cnt; 1278 b_offset += cnt; 1279 xfersize -= cnt; 1280 } 1281 mtx_unlock(&moea64_scratchpage_mtx); 1282 } 1283 1284 void 1285 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1286 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1287 { 1288 1289 if (hw_direct_map) { 1290 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1291 xfersize); 1292 } else { 1293 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1294 xfersize); 1295 } 1296 } 1297 1298 void 1299 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1300 { 1301 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1302 1303 if (size + off > PAGE_SIZE) 1304 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1305 1306 if (hw_direct_map) { 1307 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1308 } else { 1309 mtx_lock(&moea64_scratchpage_mtx); 1310 moea64_set_scratchpage_pa(mmu, 0, pa); 1311 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1312 mtx_unlock(&moea64_scratchpage_mtx); 1313 } 1314 } 1315 1316 /* 1317 * Zero a page of physical memory by temporarily mapping it 1318 */ 1319 void 1320 moea64_zero_page(mmu_t mmu, vm_page_t m) 1321 { 1322 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1323 vm_offset_t va, off; 1324 1325 if (!hw_direct_map) { 1326 mtx_lock(&moea64_scratchpage_mtx); 1327 1328 moea64_set_scratchpage_pa(mmu, 0, pa); 1329 va = moea64_scratchpage_va[0]; 1330 } else { 1331 va = PHYS_TO_DMAP(pa); 1332 } 1333 1334 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1335 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1336 1337 if (!hw_direct_map) 1338 mtx_unlock(&moea64_scratchpage_mtx); 1339 } 1340 1341 vm_offset_t 1342 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1343 { 1344 struct pvo_entry *pvo; 1345 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1346 1347 if (hw_direct_map) 1348 return (PHYS_TO_DMAP(pa)); 1349 1350 /* 1351 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1352 * a critical section and access the PCPU data like on i386. 1353 * Instead, pin the thread and grab the PCPU lock to prevent 1354 * a preempting thread from using the same PCPU data. 1355 */ 1356 sched_pin(); 1357 1358 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1359 pvo = PCPU_GET(aim.qmap_pvo); 1360 1361 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1362 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1363 (uint64_t)pa; 1364 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1365 isync(); 1366 1367 return (PCPU_GET(qmap_addr)); 1368 } 1369 1370 void 1371 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1372 { 1373 if (hw_direct_map) 1374 return; 1375 1376 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1377 KASSERT(PCPU_GET(qmap_addr) == addr, 1378 ("moea64_quick_remove_page: invalid address")); 1379 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1380 sched_unpin(); 1381 } 1382 1383 /* 1384 * Map the given physical page at the specified virtual address in the 1385 * target pmap with the protection requested. If specified the page 1386 * will be wired down. 1387 */ 1388 1389 int 1390 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1391 vm_prot_t prot, u_int flags, int8_t psind) 1392 { 1393 struct pvo_entry *pvo, *oldpvo; 1394 struct pvo_head *pvo_head; 1395 uint64_t pte_lo; 1396 int error; 1397 1398 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1399 VM_OBJECT_ASSERT_LOCKED(m->object); 1400 1401 pvo = alloc_pvo_entry(0); 1402 if (pvo == NULL) 1403 return (KERN_RESOURCE_SHORTAGE); 1404 pvo->pvo_pmap = NULL; /* to be filled in later */ 1405 pvo->pvo_pte.prot = prot; 1406 1407 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1408 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1409 1410 if ((flags & PMAP_ENTER_WIRED) != 0) 1411 pvo->pvo_vaddr |= PVO_WIRED; 1412 1413 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1414 pvo_head = NULL; 1415 } else { 1416 pvo_head = &m->md.mdpg_pvoh; 1417 pvo->pvo_vaddr |= PVO_MANAGED; 1418 } 1419 1420 PV_PAGE_LOCK(m); 1421 PMAP_LOCK(pmap); 1422 if (pvo->pvo_pmap == NULL) 1423 init_pvo_entry(pvo, pmap, va); 1424 if (prot & VM_PROT_WRITE) 1425 if (pmap_bootstrapped && 1426 (m->oflags & VPO_UNMANAGED) == 0) 1427 vm_page_aflag_set(m, PGA_WRITEABLE); 1428 1429 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo); 1430 if (error == EEXIST) { 1431 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1432 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1433 oldpvo->pvo_pte.prot == prot) { 1434 /* Identical mapping already exists */ 1435 error = 0; 1436 1437 /* If not in page table, reinsert it */ 1438 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1439 STAT_MOEA64(moea64_pte_overflow--); 1440 MOEA64_PTE_INSERT(mmu, oldpvo); 1441 } 1442 1443 /* Then just clean up and go home */ 1444 PV_PAGE_UNLOCK(m); 1445 PMAP_UNLOCK(pmap); 1446 free_pvo_entry(pvo); 1447 goto out; 1448 } else { 1449 /* Otherwise, need to kill it first */ 1450 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1451 "mapping does not match new mapping")); 1452 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1453 moea64_pvo_enter(mmu, pvo, pvo_head, NULL); 1454 } 1455 } 1456 PV_PAGE_UNLOCK(m); 1457 PMAP_UNLOCK(pmap); 1458 1459 /* Free any dead pages */ 1460 if (error == EEXIST) { 1461 moea64_pvo_remove_from_page(mmu, oldpvo); 1462 free_pvo_entry(oldpvo); 1463 } 1464 1465 out: 1466 /* 1467 * Flush the page from the instruction cache if this page is 1468 * mapped executable and cacheable. 1469 */ 1470 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1471 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1472 vm_page_aflag_set(m, PGA_EXECUTABLE); 1473 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1474 } 1475 return (KERN_SUCCESS); 1476 } 1477 1478 static void 1479 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1480 vm_size_t sz) 1481 { 1482 1483 /* 1484 * This is much trickier than on older systems because 1485 * we can't sync the icache on physical addresses directly 1486 * without a direct map. Instead we check a couple of cases 1487 * where the memory is already mapped in and, failing that, 1488 * use the same trick we use for page zeroing to create 1489 * a temporary mapping for this physical address. 1490 */ 1491 1492 if (!pmap_bootstrapped) { 1493 /* 1494 * If PMAP is not bootstrapped, we are likely to be 1495 * in real mode. 1496 */ 1497 __syncicache((void *)(uintptr_t)pa, sz); 1498 } else if (pmap == kernel_pmap) { 1499 __syncicache((void *)va, sz); 1500 } else if (hw_direct_map) { 1501 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1502 } else { 1503 /* Use the scratch page to set up a temp mapping */ 1504 1505 mtx_lock(&moea64_scratchpage_mtx); 1506 1507 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1508 __syncicache((void *)(moea64_scratchpage_va[1] + 1509 (va & ADDR_POFF)), sz); 1510 1511 mtx_unlock(&moea64_scratchpage_mtx); 1512 } 1513 } 1514 1515 /* 1516 * Maps a sequence of resident pages belonging to the same object. 1517 * The sequence begins with the given page m_start. This page is 1518 * mapped at the given virtual address start. Each subsequent page is 1519 * mapped at a virtual address that is offset from start by the same 1520 * amount as the page is offset from m_start within the object. The 1521 * last page in the sequence is the page with the largest offset from 1522 * m_start that can be mapped at a virtual address less than the given 1523 * virtual address end. Not every virtual page between start and end 1524 * is mapped; only those for which a resident page exists with the 1525 * corresponding offset from m_start are mapped. 1526 */ 1527 void 1528 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1529 vm_page_t m_start, vm_prot_t prot) 1530 { 1531 vm_page_t m; 1532 vm_pindex_t diff, psize; 1533 1534 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1535 1536 psize = atop(end - start); 1537 m = m_start; 1538 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1539 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1540 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1541 m = TAILQ_NEXT(m, listq); 1542 } 1543 } 1544 1545 void 1546 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1547 vm_prot_t prot) 1548 { 1549 1550 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1551 PMAP_ENTER_NOSLEEP, 0); 1552 } 1553 1554 vm_paddr_t 1555 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1556 { 1557 struct pvo_entry *pvo; 1558 vm_paddr_t pa; 1559 1560 PMAP_LOCK(pm); 1561 pvo = moea64_pvo_find_va(pm, va); 1562 if (pvo == NULL) 1563 pa = 0; 1564 else 1565 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1566 PMAP_UNLOCK(pm); 1567 1568 return (pa); 1569 } 1570 1571 /* 1572 * Atomically extract and hold the physical page with the given 1573 * pmap and virtual address pair if that mapping permits the given 1574 * protection. 1575 */ 1576 vm_page_t 1577 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1578 { 1579 struct pvo_entry *pvo; 1580 vm_page_t m; 1581 1582 m = NULL; 1583 PMAP_LOCK(pmap); 1584 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1585 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1586 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1587 if (!vm_page_wire_mapped(m)) 1588 m = NULL; 1589 } 1590 PMAP_UNLOCK(pmap); 1591 return (m); 1592 } 1593 1594 static mmu_t installed_mmu; 1595 1596 static void * 1597 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1598 uint8_t *flags, int wait) 1599 { 1600 struct pvo_entry *pvo; 1601 vm_offset_t va; 1602 vm_page_t m; 1603 int needed_lock; 1604 1605 /* 1606 * This entire routine is a horrible hack to avoid bothering kmem 1607 * for new KVA addresses. Because this can get called from inside 1608 * kmem allocation routines, calling kmem for a new address here 1609 * can lead to multiply locking non-recursive mutexes. 1610 */ 1611 1612 *flags = UMA_SLAB_PRIV; 1613 needed_lock = !PMAP_LOCKED(kernel_pmap); 1614 1615 m = vm_page_alloc_domain(NULL, 0, domain, 1616 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1617 if (m == NULL) 1618 return (NULL); 1619 1620 va = VM_PAGE_TO_PHYS(m); 1621 1622 pvo = alloc_pvo_entry(1 /* bootstrap */); 1623 1624 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1625 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1626 1627 if (needed_lock) 1628 PMAP_LOCK(kernel_pmap); 1629 1630 init_pvo_entry(pvo, kernel_pmap, va); 1631 pvo->pvo_vaddr |= PVO_WIRED; 1632 1633 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL); 1634 1635 if (needed_lock) 1636 PMAP_UNLOCK(kernel_pmap); 1637 1638 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1639 bzero((void *)va, PAGE_SIZE); 1640 1641 return (void *)va; 1642 } 1643 1644 extern int elf32_nxstack; 1645 1646 void 1647 moea64_init(mmu_t mmu) 1648 { 1649 1650 CTR0(KTR_PMAP, "moea64_init"); 1651 1652 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1653 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1654 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1655 1656 if (!hw_direct_map) { 1657 installed_mmu = mmu; 1658 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1659 } 1660 1661 #ifdef COMPAT_FREEBSD32 1662 elf32_nxstack = 1; 1663 #endif 1664 1665 moea64_initialized = TRUE; 1666 } 1667 1668 boolean_t 1669 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1670 { 1671 1672 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1673 ("moea64_is_referenced: page %p is not managed", m)); 1674 1675 return (moea64_query_bit(mmu, m, LPTE_REF)); 1676 } 1677 1678 boolean_t 1679 moea64_is_modified(mmu_t mmu, vm_page_t m) 1680 { 1681 1682 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1683 ("moea64_is_modified: page %p is not managed", m)); 1684 1685 /* 1686 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1687 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1688 * is clear, no PTEs can have LPTE_CHG set. 1689 */ 1690 VM_OBJECT_ASSERT_LOCKED(m->object); 1691 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1692 return (FALSE); 1693 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1694 } 1695 1696 boolean_t 1697 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1698 { 1699 struct pvo_entry *pvo; 1700 boolean_t rv = TRUE; 1701 1702 PMAP_LOCK(pmap); 1703 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1704 if (pvo != NULL) 1705 rv = FALSE; 1706 PMAP_UNLOCK(pmap); 1707 return (rv); 1708 } 1709 1710 void 1711 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1712 { 1713 1714 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1715 ("moea64_clear_modify: page %p is not managed", m)); 1716 VM_OBJECT_ASSERT_WLOCKED(m->object); 1717 KASSERT(!vm_page_xbusied(m), 1718 ("moea64_clear_modify: page %p is exclusive busied", m)); 1719 1720 /* 1721 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1722 * set. If the object containing the page is locked and the page is 1723 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1724 */ 1725 if ((m->aflags & PGA_WRITEABLE) == 0) 1726 return; 1727 moea64_clear_bit(mmu, m, LPTE_CHG); 1728 } 1729 1730 /* 1731 * Clear the write and modified bits in each of the given page's mappings. 1732 */ 1733 void 1734 moea64_remove_write(mmu_t mmu, vm_page_t m) 1735 { 1736 struct pvo_entry *pvo; 1737 int64_t refchg, ret; 1738 pmap_t pmap; 1739 1740 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1741 ("moea64_remove_write: page %p is not managed", m)); 1742 1743 /* 1744 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1745 * set by another thread while the object is locked. Thus, 1746 * if PGA_WRITEABLE is clear, no page table entries need updating. 1747 */ 1748 VM_OBJECT_ASSERT_WLOCKED(m->object); 1749 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1750 return; 1751 powerpc_sync(); 1752 PV_PAGE_LOCK(m); 1753 refchg = 0; 1754 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1755 pmap = pvo->pvo_pmap; 1756 PMAP_LOCK(pmap); 1757 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1758 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1759 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1760 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1761 MOEA64_PTE_PROT_UPDATE); 1762 if (ret < 0) 1763 ret = LPTE_CHG; 1764 refchg |= ret; 1765 if (pvo->pvo_pmap == kernel_pmap) 1766 isync(); 1767 } 1768 PMAP_UNLOCK(pmap); 1769 } 1770 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1771 vm_page_dirty(m); 1772 vm_page_aflag_clear(m, PGA_WRITEABLE); 1773 PV_PAGE_UNLOCK(m); 1774 } 1775 1776 /* 1777 * moea64_ts_referenced: 1778 * 1779 * Return a count of reference bits for a page, clearing those bits. 1780 * It is not necessary for every reference bit to be cleared, but it 1781 * is necessary that 0 only be returned when there are truly no 1782 * reference bits set. 1783 * 1784 * XXX: The exact number of bits to check and clear is a matter that 1785 * should be tested and standardized at some point in the future for 1786 * optimal aging of shared pages. 1787 */ 1788 int 1789 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1790 { 1791 1792 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1793 ("moea64_ts_referenced: page %p is not managed", m)); 1794 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1795 } 1796 1797 /* 1798 * Modify the WIMG settings of all mappings for a page. 1799 */ 1800 void 1801 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1802 { 1803 struct pvo_entry *pvo; 1804 int64_t refchg; 1805 pmap_t pmap; 1806 uint64_t lo; 1807 1808 if ((m->oflags & VPO_UNMANAGED) != 0) { 1809 m->md.mdpg_cache_attrs = ma; 1810 return; 1811 } 1812 1813 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1814 1815 PV_PAGE_LOCK(m); 1816 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1817 pmap = pvo->pvo_pmap; 1818 PMAP_LOCK(pmap); 1819 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1820 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1821 pvo->pvo_pte.pa |= lo; 1822 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1823 MOEA64_PTE_INVALIDATE); 1824 if (refchg < 0) 1825 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1826 LPTE_CHG : 0; 1827 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1828 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1829 refchg |= 1830 atomic_readandclear_32(&m->md.mdpg_attrs); 1831 if (refchg & LPTE_CHG) 1832 vm_page_dirty(m); 1833 if (refchg & LPTE_REF) 1834 vm_page_aflag_set(m, PGA_REFERENCED); 1835 } 1836 if (pvo->pvo_pmap == kernel_pmap) 1837 isync(); 1838 } 1839 PMAP_UNLOCK(pmap); 1840 } 1841 m->md.mdpg_cache_attrs = ma; 1842 PV_PAGE_UNLOCK(m); 1843 } 1844 1845 /* 1846 * Map a wired page into kernel virtual address space. 1847 */ 1848 void 1849 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1850 { 1851 int error; 1852 struct pvo_entry *pvo, *oldpvo; 1853 1854 do { 1855 pvo = alloc_pvo_entry(0); 1856 if (pvo == NULL) 1857 vm_wait(NULL); 1858 } while (pvo == NULL); 1859 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1860 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1861 pvo->pvo_vaddr |= PVO_WIRED; 1862 1863 PMAP_LOCK(kernel_pmap); 1864 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1865 if (oldpvo != NULL) 1866 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1867 init_pvo_entry(pvo, kernel_pmap, va); 1868 error = moea64_pvo_enter(mmu, pvo, NULL, NULL); 1869 PMAP_UNLOCK(kernel_pmap); 1870 1871 /* Free any dead pages */ 1872 if (oldpvo != NULL) { 1873 moea64_pvo_remove_from_page(mmu, oldpvo); 1874 free_pvo_entry(oldpvo); 1875 } 1876 1877 if (error != 0 && error != ENOENT) 1878 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1879 (uintmax_t)pa, error); 1880 } 1881 1882 void 1883 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1884 { 1885 1886 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1887 } 1888 1889 /* 1890 * Extract the physical page address associated with the given kernel virtual 1891 * address. 1892 */ 1893 vm_paddr_t 1894 moea64_kextract(mmu_t mmu, vm_offset_t va) 1895 { 1896 struct pvo_entry *pvo; 1897 vm_paddr_t pa; 1898 1899 /* 1900 * Shortcut the direct-mapped case when applicable. We never put 1901 * anything but 1:1 (or 62-bit aliased) mappings below 1902 * VM_MIN_KERNEL_ADDRESS. 1903 */ 1904 if (va < VM_MIN_KERNEL_ADDRESS) 1905 return (va & ~DMAP_BASE_ADDRESS); 1906 1907 PMAP_LOCK(kernel_pmap); 1908 pvo = moea64_pvo_find_va(kernel_pmap, va); 1909 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1910 va)); 1911 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1912 PMAP_UNLOCK(kernel_pmap); 1913 return (pa); 1914 } 1915 1916 /* 1917 * Remove a wired page from kernel virtual address space. 1918 */ 1919 void 1920 moea64_kremove(mmu_t mmu, vm_offset_t va) 1921 { 1922 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1923 } 1924 1925 /* 1926 * Provide a kernel pointer corresponding to a given userland pointer. 1927 * The returned pointer is valid until the next time this function is 1928 * called in this thread. This is used internally in copyin/copyout. 1929 */ 1930 static int 1931 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1932 void **kaddr, size_t ulen, size_t *klen) 1933 { 1934 size_t l; 1935 #ifdef __powerpc64__ 1936 struct slb *slb; 1937 #endif 1938 register_t slbv; 1939 1940 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1941 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1942 if (l > ulen) 1943 l = ulen; 1944 if (klen) 1945 *klen = l; 1946 else if (l != ulen) 1947 return (EFAULT); 1948 1949 #ifdef __powerpc64__ 1950 /* Try lockless look-up first */ 1951 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1952 1953 if (slb == NULL) { 1954 /* If it isn't there, we need to pre-fault the VSID */ 1955 PMAP_LOCK(pm); 1956 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1957 PMAP_UNLOCK(pm); 1958 } else { 1959 slbv = slb->slbv; 1960 } 1961 1962 /* Mark segment no-execute */ 1963 slbv |= SLBV_N; 1964 #else 1965 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 1966 1967 /* Mark segment no-execute */ 1968 slbv |= SR_N; 1969 #endif 1970 1971 /* If we have already set this VSID, we can just return */ 1972 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 1973 return (0); 1974 1975 __asm __volatile("isync"); 1976 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1977 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1978 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 1979 #ifdef __powerpc64__ 1980 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 1981 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 1982 #else 1983 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 1984 #endif 1985 1986 return (0); 1987 } 1988 1989 /* 1990 * Figure out where a given kernel pointer (usually in a fault) points 1991 * to from the VM's perspective, potentially remapping into userland's 1992 * address space. 1993 */ 1994 static int 1995 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1996 vm_offset_t *decoded_addr) 1997 { 1998 vm_offset_t user_sr; 1999 2000 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2001 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2002 addr &= ADDR_PIDX | ADDR_POFF; 2003 addr |= user_sr << ADDR_SR_SHFT; 2004 *decoded_addr = addr; 2005 *is_user = 1; 2006 } else { 2007 *decoded_addr = addr; 2008 *is_user = 0; 2009 } 2010 2011 return (0); 2012 } 2013 2014 /* 2015 * Map a range of physical addresses into kernel virtual address space. 2016 * 2017 * The value passed in *virt is a suggested virtual address for the mapping. 2018 * Architectures which can support a direct-mapped physical to virtual region 2019 * can return the appropriate address within that region, leaving '*virt' 2020 * unchanged. Other architectures should map the pages starting at '*virt' and 2021 * update '*virt' with the first usable address after the mapped region. 2022 */ 2023 vm_offset_t 2024 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 2025 vm_paddr_t pa_end, int prot) 2026 { 2027 vm_offset_t sva, va; 2028 2029 if (hw_direct_map) { 2030 /* 2031 * Check if every page in the region is covered by the direct 2032 * map. The direct map covers all of physical memory. Use 2033 * moea64_calc_wimg() as a shortcut to see if the page is in 2034 * physical memory as a way to see if the direct map covers it. 2035 */ 2036 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2037 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2038 break; 2039 if (va == pa_end) 2040 return (PHYS_TO_DMAP(pa_start)); 2041 } 2042 sva = *virt; 2043 va = sva; 2044 /* XXX respect prot argument */ 2045 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2046 moea64_kenter(mmu, va, pa_start); 2047 *virt = va; 2048 2049 return (sva); 2050 } 2051 2052 /* 2053 * Returns true if the pmap's pv is one of the first 2054 * 16 pvs linked to from this page. This count may 2055 * be changed upwards or downwards in the future; it 2056 * is only necessary that true be returned for a small 2057 * subset of pmaps for proper page aging. 2058 */ 2059 boolean_t 2060 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2061 { 2062 int loops; 2063 struct pvo_entry *pvo; 2064 boolean_t rv; 2065 2066 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2067 ("moea64_page_exists_quick: page %p is not managed", m)); 2068 loops = 0; 2069 rv = FALSE; 2070 PV_PAGE_LOCK(m); 2071 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2072 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2073 rv = TRUE; 2074 break; 2075 } 2076 if (++loops >= 16) 2077 break; 2078 } 2079 PV_PAGE_UNLOCK(m); 2080 return (rv); 2081 } 2082 2083 void 2084 moea64_page_init(mmu_t mmu __unused, vm_page_t m) 2085 { 2086 2087 m->md.mdpg_attrs = 0; 2088 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2089 LIST_INIT(&m->md.mdpg_pvoh); 2090 } 2091 2092 /* 2093 * Return the number of managed mappings to the given physical page 2094 * that are wired. 2095 */ 2096 int 2097 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 2098 { 2099 struct pvo_entry *pvo; 2100 int count; 2101 2102 count = 0; 2103 if ((m->oflags & VPO_UNMANAGED) != 0) 2104 return (count); 2105 PV_PAGE_LOCK(m); 2106 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2107 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2108 count++; 2109 PV_PAGE_UNLOCK(m); 2110 return (count); 2111 } 2112 2113 static uintptr_t moea64_vsidcontext; 2114 2115 uintptr_t 2116 moea64_get_unique_vsid(void) { 2117 u_int entropy; 2118 register_t hash; 2119 uint32_t mask; 2120 int i; 2121 2122 entropy = 0; 2123 __asm __volatile("mftb %0" : "=r"(entropy)); 2124 2125 mtx_lock(&moea64_slb_mutex); 2126 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2127 u_int n; 2128 2129 /* 2130 * Create a new value by mutiplying by a prime and adding in 2131 * entropy from the timebase register. This is to make the 2132 * VSID more random so that the PT hash function collides 2133 * less often. (Note that the prime casues gcc to do shifts 2134 * instead of a multiply.) 2135 */ 2136 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2137 hash = moea64_vsidcontext & (NVSIDS - 1); 2138 if (hash == 0) /* 0 is special, avoid it */ 2139 continue; 2140 n = hash >> 5; 2141 mask = 1 << (hash & (VSID_NBPW - 1)); 2142 hash = (moea64_vsidcontext & VSID_HASHMASK); 2143 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2144 /* anything free in this bucket? */ 2145 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2146 entropy = (moea64_vsidcontext >> 20); 2147 continue; 2148 } 2149 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2150 mask = 1 << i; 2151 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2152 hash |= i; 2153 } 2154 if (hash == VSID_VRMA) /* also special, avoid this too */ 2155 continue; 2156 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2157 ("Allocating in-use VSID %#zx\n", hash)); 2158 moea64_vsid_bitmap[n] |= mask; 2159 mtx_unlock(&moea64_slb_mutex); 2160 return (hash); 2161 } 2162 2163 mtx_unlock(&moea64_slb_mutex); 2164 panic("%s: out of segments",__func__); 2165 } 2166 2167 #ifdef __powerpc64__ 2168 void 2169 moea64_pinit(mmu_t mmu, pmap_t pmap) 2170 { 2171 2172 RB_INIT(&pmap->pmap_pvo); 2173 2174 pmap->pm_slb_tree_root = slb_alloc_tree(); 2175 pmap->pm_slb = slb_alloc_user_cache(); 2176 pmap->pm_slb_len = 0; 2177 } 2178 #else 2179 void 2180 moea64_pinit(mmu_t mmu, pmap_t pmap) 2181 { 2182 int i; 2183 uint32_t hash; 2184 2185 RB_INIT(&pmap->pmap_pvo); 2186 2187 if (pmap_bootstrapped) 2188 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 2189 (vm_offset_t)pmap); 2190 else 2191 pmap->pmap_phys = pmap; 2192 2193 /* 2194 * Allocate some segment registers for this pmap. 2195 */ 2196 hash = moea64_get_unique_vsid(); 2197 2198 for (i = 0; i < 16; i++) 2199 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2200 2201 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2202 } 2203 #endif 2204 2205 /* 2206 * Initialize the pmap associated with process 0. 2207 */ 2208 void 2209 moea64_pinit0(mmu_t mmu, pmap_t pm) 2210 { 2211 2212 PMAP_LOCK_INIT(pm); 2213 moea64_pinit(mmu, pm); 2214 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2215 } 2216 2217 /* 2218 * Set the physical protection on the specified range of this map as requested. 2219 */ 2220 static void 2221 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2222 { 2223 struct vm_page *pg; 2224 vm_prot_t oldprot; 2225 int32_t refchg; 2226 2227 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2228 2229 /* 2230 * Change the protection of the page. 2231 */ 2232 oldprot = pvo->pvo_pte.prot; 2233 pvo->pvo_pte.prot = prot; 2234 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2235 2236 /* 2237 * If the PVO is in the page table, update mapping 2238 */ 2239 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2240 if (refchg < 0) 2241 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2242 2243 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2244 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2245 if ((pg->oflags & VPO_UNMANAGED) == 0) 2246 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2247 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2248 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2249 } 2250 2251 /* 2252 * Update vm about the REF/CHG bits if the page is managed and we have 2253 * removed write access. 2254 */ 2255 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2256 (oldprot & VM_PROT_WRITE)) { 2257 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2258 if (refchg & LPTE_CHG) 2259 vm_page_dirty(pg); 2260 if (refchg & LPTE_REF) 2261 vm_page_aflag_set(pg, PGA_REFERENCED); 2262 } 2263 } 2264 2265 void 2266 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2267 vm_prot_t prot) 2268 { 2269 struct pvo_entry *pvo, *tpvo, key; 2270 2271 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2272 sva, eva, prot); 2273 2274 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2275 ("moea64_protect: non current pmap")); 2276 2277 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2278 moea64_remove(mmu, pm, sva, eva); 2279 return; 2280 } 2281 2282 PMAP_LOCK(pm); 2283 key.pvo_vaddr = sva; 2284 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2285 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2286 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2287 moea64_pvo_protect(mmu, pm, pvo, prot); 2288 } 2289 PMAP_UNLOCK(pm); 2290 } 2291 2292 /* 2293 * Map a list of wired pages into kernel virtual address space. This is 2294 * intended for temporary mappings which do not need page modification or 2295 * references recorded. Existing mappings in the region are overwritten. 2296 */ 2297 void 2298 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2299 { 2300 while (count-- > 0) { 2301 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2302 va += PAGE_SIZE; 2303 m++; 2304 } 2305 } 2306 2307 /* 2308 * Remove page mappings from kernel virtual address space. Intended for 2309 * temporary mappings entered by moea64_qenter. 2310 */ 2311 void 2312 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2313 { 2314 while (count-- > 0) { 2315 moea64_kremove(mmu, va); 2316 va += PAGE_SIZE; 2317 } 2318 } 2319 2320 void 2321 moea64_release_vsid(uint64_t vsid) 2322 { 2323 int idx, mask; 2324 2325 mtx_lock(&moea64_slb_mutex); 2326 idx = vsid & (NVSIDS-1); 2327 mask = 1 << (idx % VSID_NBPW); 2328 idx /= VSID_NBPW; 2329 KASSERT(moea64_vsid_bitmap[idx] & mask, 2330 ("Freeing unallocated VSID %#jx", vsid)); 2331 moea64_vsid_bitmap[idx] &= ~mask; 2332 mtx_unlock(&moea64_slb_mutex); 2333 } 2334 2335 2336 void 2337 moea64_release(mmu_t mmu, pmap_t pmap) 2338 { 2339 2340 /* 2341 * Free segment registers' VSIDs 2342 */ 2343 #ifdef __powerpc64__ 2344 slb_free_tree(pmap); 2345 slb_free_user_cache(pmap->pm_slb); 2346 #else 2347 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2348 2349 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2350 #endif 2351 } 2352 2353 /* 2354 * Remove all pages mapped by the specified pmap 2355 */ 2356 void 2357 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2358 { 2359 struct pvo_entry *pvo, *tpvo; 2360 struct pvo_dlist tofree; 2361 2362 SLIST_INIT(&tofree); 2363 2364 PMAP_LOCK(pm); 2365 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2366 if (pvo->pvo_vaddr & PVO_WIRED) 2367 continue; 2368 2369 /* 2370 * For locking reasons, remove this from the page table and 2371 * pmap, but save delinking from the vm_page for a second 2372 * pass 2373 */ 2374 moea64_pvo_remove_from_pmap(mmu, pvo); 2375 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2376 } 2377 PMAP_UNLOCK(pm); 2378 2379 while (!SLIST_EMPTY(&tofree)) { 2380 pvo = SLIST_FIRST(&tofree); 2381 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2382 moea64_pvo_remove_from_page(mmu, pvo); 2383 free_pvo_entry(pvo); 2384 } 2385 } 2386 2387 /* 2388 * Remove the given range of addresses from the specified map. 2389 */ 2390 void 2391 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2392 { 2393 struct pvo_entry *pvo, *tpvo, key; 2394 struct pvo_dlist tofree; 2395 2396 /* 2397 * Perform an unsynchronized read. This is, however, safe. 2398 */ 2399 if (pm->pm_stats.resident_count == 0) 2400 return; 2401 2402 key.pvo_vaddr = sva; 2403 2404 SLIST_INIT(&tofree); 2405 2406 PMAP_LOCK(pm); 2407 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2408 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2409 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2410 2411 /* 2412 * For locking reasons, remove this from the page table and 2413 * pmap, but save delinking from the vm_page for a second 2414 * pass 2415 */ 2416 moea64_pvo_remove_from_pmap(mmu, pvo); 2417 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2418 } 2419 PMAP_UNLOCK(pm); 2420 2421 while (!SLIST_EMPTY(&tofree)) { 2422 pvo = SLIST_FIRST(&tofree); 2423 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2424 moea64_pvo_remove_from_page(mmu, pvo); 2425 free_pvo_entry(pvo); 2426 } 2427 } 2428 2429 /* 2430 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2431 * will reflect changes in pte's back to the vm_page. 2432 */ 2433 void 2434 moea64_remove_all(mmu_t mmu, vm_page_t m) 2435 { 2436 struct pvo_entry *pvo, *next_pvo; 2437 struct pvo_head freequeue; 2438 int wasdead; 2439 pmap_t pmap; 2440 2441 LIST_INIT(&freequeue); 2442 2443 PV_PAGE_LOCK(m); 2444 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2445 pmap = pvo->pvo_pmap; 2446 PMAP_LOCK(pmap); 2447 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2448 if (!wasdead) 2449 moea64_pvo_remove_from_pmap(mmu, pvo); 2450 moea64_pvo_remove_from_page_locked(mmu, pvo, m); 2451 if (!wasdead) 2452 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2453 PMAP_UNLOCK(pmap); 2454 2455 } 2456 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2457 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2458 PV_PAGE_UNLOCK(m); 2459 2460 /* Clean up UMA allocations */ 2461 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2462 free_pvo_entry(pvo); 2463 } 2464 2465 /* 2466 * Allocate a physical page of memory directly from the phys_avail map. 2467 * Can only be called from moea64_bootstrap before avail start and end are 2468 * calculated. 2469 */ 2470 vm_offset_t 2471 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2472 { 2473 vm_offset_t s, e; 2474 int i, j; 2475 2476 size = round_page(size); 2477 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2478 if (align != 0) 2479 s = roundup2(phys_avail[i], align); 2480 else 2481 s = phys_avail[i]; 2482 e = s + size; 2483 2484 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2485 continue; 2486 2487 if (s + size > platform_real_maxaddr()) 2488 continue; 2489 2490 if (s == phys_avail[i]) { 2491 phys_avail[i] += size; 2492 } else if (e == phys_avail[i + 1]) { 2493 phys_avail[i + 1] -= size; 2494 } else { 2495 for (j = phys_avail_count * 2; j > i; j -= 2) { 2496 phys_avail[j] = phys_avail[j - 2]; 2497 phys_avail[j + 1] = phys_avail[j - 1]; 2498 } 2499 2500 phys_avail[i + 3] = phys_avail[i + 1]; 2501 phys_avail[i + 1] = s; 2502 phys_avail[i + 2] = e; 2503 phys_avail_count++; 2504 } 2505 2506 return (s); 2507 } 2508 panic("moea64_bootstrap_alloc: could not allocate memory"); 2509 } 2510 2511 static int 2512 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head, 2513 struct pvo_entry **oldpvop) 2514 { 2515 int first, err; 2516 struct pvo_entry *old_pvo; 2517 2518 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2519 2520 STAT_MOEA64(moea64_pvo_enter_calls++); 2521 2522 /* 2523 * Add to pmap list 2524 */ 2525 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2526 2527 if (old_pvo != NULL) { 2528 if (oldpvop != NULL) 2529 *oldpvop = old_pvo; 2530 return (EEXIST); 2531 } 2532 2533 /* 2534 * Remember if the list was empty and therefore will be the first 2535 * item. 2536 */ 2537 if (pvo_head != NULL) { 2538 if (LIST_FIRST(pvo_head) == NULL) 2539 first = 1; 2540 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2541 } 2542 2543 if (pvo->pvo_vaddr & PVO_WIRED) 2544 pvo->pvo_pmap->pm_stats.wired_count++; 2545 pvo->pvo_pmap->pm_stats.resident_count++; 2546 2547 /* 2548 * Insert it into the hardware page table 2549 */ 2550 err = MOEA64_PTE_INSERT(mmu, pvo); 2551 if (err != 0) { 2552 panic("moea64_pvo_enter: overflow"); 2553 } 2554 2555 STAT_MOEA64(moea64_pvo_entries++); 2556 2557 if (pvo->pvo_pmap == kernel_pmap) 2558 isync(); 2559 2560 #ifdef __powerpc64__ 2561 /* 2562 * Make sure all our bootstrap mappings are in the SLB as soon 2563 * as virtual memory is switched on. 2564 */ 2565 if (!pmap_bootstrapped) 2566 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2567 pvo->pvo_vaddr & PVO_LARGE); 2568 #endif 2569 2570 return (first ? ENOENT : 0); 2571 } 2572 2573 static void 2574 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2575 { 2576 struct vm_page *pg; 2577 int32_t refchg; 2578 2579 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2580 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2581 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2582 2583 /* 2584 * If there is an active pte entry, we need to deactivate it 2585 */ 2586 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2587 if (refchg < 0) { 2588 /* 2589 * If it was evicted from the page table, be pessimistic and 2590 * dirty the page. 2591 */ 2592 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2593 refchg = LPTE_CHG; 2594 else 2595 refchg = 0; 2596 } 2597 2598 /* 2599 * Update our statistics. 2600 */ 2601 pvo->pvo_pmap->pm_stats.resident_count--; 2602 if (pvo->pvo_vaddr & PVO_WIRED) 2603 pvo->pvo_pmap->pm_stats.wired_count--; 2604 2605 /* 2606 * Remove this PVO from the pmap list. 2607 */ 2608 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2609 2610 /* 2611 * Mark this for the next sweep 2612 */ 2613 pvo->pvo_vaddr |= PVO_DEAD; 2614 2615 /* Send RC bits to VM */ 2616 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2617 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2618 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2619 if (pg != NULL) { 2620 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2621 if (refchg & LPTE_CHG) 2622 vm_page_dirty(pg); 2623 if (refchg & LPTE_REF) 2624 vm_page_aflag_set(pg, PGA_REFERENCED); 2625 } 2626 } 2627 } 2628 2629 static inline void 2630 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo, 2631 vm_page_t m) 2632 { 2633 2634 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2635 2636 /* Use NULL pmaps as a sentinel for races in page deletion */ 2637 if (pvo->pvo_pmap == NULL) 2638 return; 2639 pvo->pvo_pmap = NULL; 2640 2641 /* 2642 * Update vm about page writeability/executability if managed 2643 */ 2644 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2645 if (pvo->pvo_vaddr & PVO_MANAGED) { 2646 if (m != NULL) { 2647 LIST_REMOVE(pvo, pvo_vlink); 2648 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2649 vm_page_aflag_clear(m, 2650 PGA_WRITEABLE | PGA_EXECUTABLE); 2651 } 2652 } 2653 2654 STAT_MOEA64(moea64_pvo_entries--); 2655 STAT_MOEA64(moea64_pvo_remove_calls++); 2656 } 2657 2658 static void 2659 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2660 { 2661 vm_page_t pg = NULL; 2662 2663 if (pvo->pvo_vaddr & PVO_MANAGED) 2664 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2665 2666 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2667 moea64_pvo_remove_from_page_locked(mmu, pvo, pg); 2668 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2669 } 2670 2671 static struct pvo_entry * 2672 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2673 { 2674 struct pvo_entry key; 2675 2676 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2677 2678 key.pvo_vaddr = va & ~ADDR_POFF; 2679 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2680 } 2681 2682 static boolean_t 2683 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2684 { 2685 struct pvo_entry *pvo; 2686 int64_t ret; 2687 boolean_t rv; 2688 2689 /* 2690 * See if this bit is stored in the page already. 2691 */ 2692 if (m->md.mdpg_attrs & ptebit) 2693 return (TRUE); 2694 2695 /* 2696 * Examine each PTE. Sync so that any pending REF/CHG bits are 2697 * flushed to the PTEs. 2698 */ 2699 rv = FALSE; 2700 powerpc_sync(); 2701 PV_PAGE_LOCK(m); 2702 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2703 ret = 0; 2704 2705 /* 2706 * See if this pvo has a valid PTE. if so, fetch the 2707 * REF/CHG bits from the valid PTE. If the appropriate 2708 * ptebit is set, return success. 2709 */ 2710 PMAP_LOCK(pvo->pvo_pmap); 2711 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2712 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2713 PMAP_UNLOCK(pvo->pvo_pmap); 2714 2715 if (ret > 0) { 2716 atomic_set_32(&m->md.mdpg_attrs, 2717 ret & (LPTE_CHG | LPTE_REF)); 2718 if (ret & ptebit) { 2719 rv = TRUE; 2720 break; 2721 } 2722 } 2723 } 2724 PV_PAGE_UNLOCK(m); 2725 2726 return (rv); 2727 } 2728 2729 static u_int 2730 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2731 { 2732 u_int count; 2733 struct pvo_entry *pvo; 2734 int64_t ret; 2735 2736 /* 2737 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2738 * we can reset the right ones). 2739 */ 2740 powerpc_sync(); 2741 2742 /* 2743 * For each pvo entry, clear the pte's ptebit. 2744 */ 2745 count = 0; 2746 PV_PAGE_LOCK(m); 2747 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2748 ret = 0; 2749 2750 PMAP_LOCK(pvo->pvo_pmap); 2751 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2752 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2753 PMAP_UNLOCK(pvo->pvo_pmap); 2754 2755 if (ret > 0 && (ret & ptebit)) 2756 count++; 2757 } 2758 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2759 PV_PAGE_UNLOCK(m); 2760 2761 return (count); 2762 } 2763 2764 boolean_t 2765 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2766 { 2767 struct pvo_entry *pvo, key; 2768 vm_offset_t ppa; 2769 int error = 0; 2770 2771 if (hw_direct_map && mem_valid(pa, size) == 0) 2772 return (0); 2773 2774 PMAP_LOCK(kernel_pmap); 2775 ppa = pa & ~ADDR_POFF; 2776 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2777 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2778 ppa < pa + size; ppa += PAGE_SIZE, 2779 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2780 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2781 error = EFAULT; 2782 break; 2783 } 2784 } 2785 PMAP_UNLOCK(kernel_pmap); 2786 2787 return (error); 2788 } 2789 2790 /* 2791 * Map a set of physical memory pages into the kernel virtual 2792 * address space. Return a pointer to where it is mapped. This 2793 * routine is intended to be used for mapping device memory, 2794 * NOT real memory. 2795 */ 2796 void * 2797 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2798 { 2799 vm_offset_t va, tmpva, ppa, offset; 2800 2801 ppa = trunc_page(pa); 2802 offset = pa & PAGE_MASK; 2803 size = roundup2(offset + size, PAGE_SIZE); 2804 2805 va = kva_alloc(size); 2806 2807 if (!va) 2808 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2809 2810 for (tmpva = va; size > 0;) { 2811 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2812 size -= PAGE_SIZE; 2813 tmpva += PAGE_SIZE; 2814 ppa += PAGE_SIZE; 2815 } 2816 2817 return ((void *)(va + offset)); 2818 } 2819 2820 void * 2821 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2822 { 2823 2824 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2825 } 2826 2827 void 2828 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2829 { 2830 vm_offset_t base, offset; 2831 2832 base = trunc_page(va); 2833 offset = va & PAGE_MASK; 2834 size = roundup2(offset + size, PAGE_SIZE); 2835 2836 kva_free(base, size); 2837 } 2838 2839 void 2840 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2841 { 2842 struct pvo_entry *pvo; 2843 vm_offset_t lim; 2844 vm_paddr_t pa; 2845 vm_size_t len; 2846 2847 if (__predict_false(pm == NULL)) 2848 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2849 2850 PMAP_LOCK(pm); 2851 while (sz > 0) { 2852 lim = round_page(va+1); 2853 len = MIN(lim - va, sz); 2854 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2855 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2856 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2857 moea64_syncicache(mmu, pm, va, pa, len); 2858 } 2859 va += len; 2860 sz -= len; 2861 } 2862 PMAP_UNLOCK(pm); 2863 } 2864 2865 void 2866 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2867 { 2868 2869 *va = (void *)(uintptr_t)pa; 2870 } 2871 2872 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2873 2874 void 2875 moea64_scan_init(mmu_t mmu) 2876 { 2877 struct pvo_entry *pvo; 2878 vm_offset_t va; 2879 int i; 2880 2881 if (!do_minidump) { 2882 /* Initialize phys. segments for dumpsys(). */ 2883 memset(&dump_map, 0, sizeof(dump_map)); 2884 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2885 for (i = 0; i < pregions_sz; i++) { 2886 dump_map[i].pa_start = pregions[i].mr_start; 2887 dump_map[i].pa_size = pregions[i].mr_size; 2888 } 2889 return; 2890 } 2891 2892 /* Virtual segments for minidumps: */ 2893 memset(&dump_map, 0, sizeof(dump_map)); 2894 2895 /* 1st: kernel .data and .bss. */ 2896 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2897 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2898 dump_map[0].pa_start; 2899 2900 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2901 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2902 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2903 2904 /* 3rd: kernel VM. */ 2905 va = dump_map[1].pa_start + dump_map[1].pa_size; 2906 /* Find start of next chunk (from va). */ 2907 while (va < virtual_end) { 2908 /* Don't dump the buffer cache. */ 2909 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2910 va = kmi.buffer_eva; 2911 continue; 2912 } 2913 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2914 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2915 break; 2916 va += PAGE_SIZE; 2917 } 2918 if (va < virtual_end) { 2919 dump_map[2].pa_start = va; 2920 va += PAGE_SIZE; 2921 /* Find last page in chunk. */ 2922 while (va < virtual_end) { 2923 /* Don't run into the buffer cache. */ 2924 if (va == kmi.buffer_sva) 2925 break; 2926 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2927 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2928 break; 2929 va += PAGE_SIZE; 2930 } 2931 dump_map[2].pa_size = va - dump_map[2].pa_start; 2932 } 2933 } 2934 2935