1 /*- 2 * Copyright (c) 2008-2015 Nathan Whitehorn 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Manages physical address maps. 32 * 33 * Since the information managed by this module is also stored by the 34 * logical address mapping module, this module may throw away valid virtual 35 * to physical mappings at almost any time. However, invalidations of 36 * mappings must be done as requested. 37 * 38 * In order to cope with hardware architectures which make virtual to 39 * physical map invalidates expensive, this module may delay invalidate 40 * reduced protection operations until such time as they are actually 41 * necessary. This module is given full information as to which processors 42 * are currently using which maps, and to when physical maps must be made 43 * correct. 44 */ 45 46 #include "opt_compat.h" 47 #include "opt_kstack_pages.h" 48 49 #include <sys/param.h> 50 #include <sys/kernel.h> 51 #include <sys/conf.h> 52 #include <sys/queue.h> 53 #include <sys/cpuset.h> 54 #include <sys/kerneldump.h> 55 #include <sys/ktr.h> 56 #include <sys/lock.h> 57 #include <sys/msgbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/mutex.h> 60 #include <sys/proc.h> 61 #include <sys/rwlock.h> 62 #include <sys/sched.h> 63 #include <sys/sysctl.h> 64 #include <sys/systm.h> 65 #include <sys/vmmeter.h> 66 67 #include <sys/kdb.h> 68 69 #include <dev/ofw/openfirm.h> 70 71 #include <vm/vm.h> 72 #include <vm/vm_param.h> 73 #include <vm/vm_kern.h> 74 #include <vm/vm_page.h> 75 #include <vm/vm_map.h> 76 #include <vm/vm_object.h> 77 #include <vm/vm_extern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/uma.h> 80 81 #include <machine/_inttypes.h> 82 #include <machine/cpu.h> 83 #include <machine/platform.h> 84 #include <machine/frame.h> 85 #include <machine/md_var.h> 86 #include <machine/psl.h> 87 #include <machine/bat.h> 88 #include <machine/hid.h> 89 #include <machine/pte.h> 90 #include <machine/sr.h> 91 #include <machine/trap.h> 92 #include <machine/mmuvar.h> 93 94 #include "mmu_oea64.h" 95 #include "mmu_if.h" 96 #include "moea64_if.h" 97 98 void moea64_release_vsid(uint64_t vsid); 99 uintptr_t moea64_get_unique_vsid(void); 100 101 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 102 #define ENABLE_TRANS(msr) mtmsr(msr) 103 104 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 105 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 106 #define VSID_HASH_MASK 0x0000007fffffffffULL 107 108 /* 109 * Locking semantics: 110 * 111 * There are two locks of interest: the page locks and the pmap locks, which 112 * protect their individual PVO lists and are locked in that order. The contents 113 * of all PVO entries are protected by the locks of their respective pmaps. 114 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 115 * into any list. 116 * 117 */ 118 119 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 120 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 121 122 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 123 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 124 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 125 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 126 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 127 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 128 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 129 130 struct ofw_map { 131 cell_t om_va; 132 cell_t om_len; 133 uint64_t om_pa; 134 cell_t om_mode; 135 }; 136 137 extern unsigned char _etext[]; 138 extern unsigned char _end[]; 139 140 extern int ofw_real_mode; 141 142 /* 143 * Map of physical memory regions. 144 */ 145 static struct mem_region *regions; 146 static struct mem_region *pregions; 147 static u_int phys_avail_count; 148 static int regions_sz, pregions_sz; 149 150 extern void bs_remap_earlyboot(void); 151 152 /* 153 * Lock for the SLB tables. 154 */ 155 struct mtx moea64_slb_mutex; 156 157 /* 158 * PTEG data. 159 */ 160 u_int moea64_pteg_count; 161 u_int moea64_pteg_mask; 162 163 /* 164 * PVO data. 165 */ 166 167 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 168 169 static struct pvo_entry *moea64_bpvo_pool; 170 static int moea64_bpvo_pool_index = 0; 171 static int moea64_bpvo_pool_size = 327680; 172 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 173 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 174 &moea64_bpvo_pool_index, 0, ""); 175 176 #define VSID_NBPW (sizeof(u_int32_t) * 8) 177 #ifdef __powerpc64__ 178 #define NVSIDS (NPMAPS * 16) 179 #define VSID_HASHMASK 0xffffffffUL 180 #else 181 #define NVSIDS NPMAPS 182 #define VSID_HASHMASK 0xfffffUL 183 #endif 184 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 185 186 static boolean_t moea64_initialized = FALSE; 187 188 /* 189 * Statistics. 190 */ 191 u_int moea64_pte_valid = 0; 192 u_int moea64_pte_overflow = 0; 193 u_int moea64_pvo_entries = 0; 194 u_int moea64_pvo_enter_calls = 0; 195 u_int moea64_pvo_remove_calls = 0; 196 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 197 &moea64_pte_valid, 0, ""); 198 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 199 &moea64_pte_overflow, 0, ""); 200 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 201 &moea64_pvo_entries, 0, ""); 202 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 203 &moea64_pvo_enter_calls, 0, ""); 204 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 205 &moea64_pvo_remove_calls, 0, ""); 206 207 vm_offset_t moea64_scratchpage_va[2]; 208 struct pvo_entry *moea64_scratchpage_pvo[2]; 209 struct mtx moea64_scratchpage_mtx; 210 211 uint64_t moea64_large_page_mask = 0; 212 uint64_t moea64_large_page_size = 0; 213 int moea64_large_page_shift = 0; 214 215 /* 216 * PVO calls. 217 */ 218 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 219 struct pvo_head *pvo_head); 220 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 221 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 222 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 223 224 /* 225 * Utility routines. 226 */ 227 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 228 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 229 static void moea64_kremove(mmu_t, vm_offset_t); 230 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 231 vm_offset_t pa, vm_size_t sz); 232 233 /* 234 * Kernel MMU interface 235 */ 236 void moea64_clear_modify(mmu_t, vm_page_t); 237 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 238 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 239 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 240 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 241 u_int flags, int8_t psind); 242 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 243 vm_prot_t); 244 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 245 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 246 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 247 void moea64_init(mmu_t); 248 boolean_t moea64_is_modified(mmu_t, vm_page_t); 249 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 250 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 251 int moea64_ts_referenced(mmu_t, vm_page_t); 252 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 253 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 254 int moea64_page_wired_mappings(mmu_t, vm_page_t); 255 void moea64_pinit(mmu_t, pmap_t); 256 void moea64_pinit0(mmu_t, pmap_t); 257 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 258 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 259 void moea64_qremove(mmu_t, vm_offset_t, int); 260 void moea64_release(mmu_t, pmap_t); 261 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 262 void moea64_remove_pages(mmu_t, pmap_t); 263 void moea64_remove_all(mmu_t, vm_page_t); 264 void moea64_remove_write(mmu_t, vm_page_t); 265 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 266 void moea64_zero_page(mmu_t, vm_page_t); 267 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 268 void moea64_zero_page_idle(mmu_t, vm_page_t); 269 void moea64_activate(mmu_t, struct thread *); 270 void moea64_deactivate(mmu_t, struct thread *); 271 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 272 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 273 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 274 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 275 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 276 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma); 277 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 278 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 279 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 280 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 281 void **va); 282 void moea64_scan_init(mmu_t mmu); 283 284 static mmu_method_t moea64_methods[] = { 285 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 286 MMUMETHOD(mmu_copy_page, moea64_copy_page), 287 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 288 MMUMETHOD(mmu_enter, moea64_enter), 289 MMUMETHOD(mmu_enter_object, moea64_enter_object), 290 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 291 MMUMETHOD(mmu_extract, moea64_extract), 292 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 293 MMUMETHOD(mmu_init, moea64_init), 294 MMUMETHOD(mmu_is_modified, moea64_is_modified), 295 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 296 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 297 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 298 MMUMETHOD(mmu_map, moea64_map), 299 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 300 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 301 MMUMETHOD(mmu_pinit, moea64_pinit), 302 MMUMETHOD(mmu_pinit0, moea64_pinit0), 303 MMUMETHOD(mmu_protect, moea64_protect), 304 MMUMETHOD(mmu_qenter, moea64_qenter), 305 MMUMETHOD(mmu_qremove, moea64_qremove), 306 MMUMETHOD(mmu_release, moea64_release), 307 MMUMETHOD(mmu_remove, moea64_remove), 308 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 309 MMUMETHOD(mmu_remove_all, moea64_remove_all), 310 MMUMETHOD(mmu_remove_write, moea64_remove_write), 311 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 312 MMUMETHOD(mmu_unwire, moea64_unwire), 313 MMUMETHOD(mmu_zero_page, moea64_zero_page), 314 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 315 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle), 316 MMUMETHOD(mmu_activate, moea64_activate), 317 MMUMETHOD(mmu_deactivate, moea64_deactivate), 318 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 319 320 /* Internal interfaces */ 321 MMUMETHOD(mmu_mapdev, moea64_mapdev), 322 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 323 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 324 MMUMETHOD(mmu_kextract, moea64_kextract), 325 MMUMETHOD(mmu_kenter, moea64_kenter), 326 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 327 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 328 MMUMETHOD(mmu_scan_init, moea64_scan_init), 329 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 330 331 { 0, 0 } 332 }; 333 334 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 335 336 static struct pvo_head * 337 vm_page_to_pvoh(vm_page_t m) 338 { 339 340 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 341 return (&m->md.mdpg_pvoh); 342 } 343 344 static struct pvo_entry * 345 alloc_pvo_entry(int bootstrap) 346 { 347 struct pvo_entry *pvo; 348 349 if (!moea64_initialized || bootstrap) { 350 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 351 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 352 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 353 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 354 } 355 pvo = &moea64_bpvo_pool[ 356 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 357 bzero(pvo, sizeof(*pvo)); 358 pvo->pvo_vaddr = PVO_BOOTSTRAP; 359 } else { 360 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 361 bzero(pvo, sizeof(*pvo)); 362 } 363 364 return (pvo); 365 } 366 367 368 static void 369 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 370 { 371 uint64_t vsid; 372 uint64_t hash; 373 int shift; 374 375 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 376 377 pvo->pvo_pmap = pmap; 378 va &= ~ADDR_POFF; 379 pvo->pvo_vaddr |= va; 380 vsid = va_to_vsid(pmap, va); 381 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 382 | (vsid << 16); 383 384 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 385 ADDR_PIDX_SHFT; 386 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 387 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 388 } 389 390 static void 391 free_pvo_entry(struct pvo_entry *pvo) 392 { 393 394 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 395 uma_zfree(moea64_pvo_zone, pvo); 396 } 397 398 void 399 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 400 { 401 402 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 403 LPTE_AVPN_MASK; 404 lpte->pte_hi |= LPTE_VALID; 405 406 if (pvo->pvo_vaddr & PVO_LARGE) 407 lpte->pte_hi |= LPTE_BIG; 408 if (pvo->pvo_vaddr & PVO_WIRED) 409 lpte->pte_hi |= LPTE_WIRED; 410 if (pvo->pvo_vaddr & PVO_HID) 411 lpte->pte_hi |= LPTE_HID; 412 413 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 414 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 415 lpte->pte_lo |= LPTE_BW; 416 else 417 lpte->pte_lo |= LPTE_BR; 418 419 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 420 lpte->pte_lo |= LPTE_NOEXEC; 421 } 422 423 static __inline uint64_t 424 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 425 { 426 uint64_t pte_lo; 427 int i; 428 429 if (ma != VM_MEMATTR_DEFAULT) { 430 switch (ma) { 431 case VM_MEMATTR_UNCACHEABLE: 432 return (LPTE_I | LPTE_G); 433 case VM_MEMATTR_WRITE_COMBINING: 434 case VM_MEMATTR_WRITE_BACK: 435 case VM_MEMATTR_PREFETCHABLE: 436 return (LPTE_I); 437 case VM_MEMATTR_WRITE_THROUGH: 438 return (LPTE_W | LPTE_M); 439 } 440 } 441 442 /* 443 * Assume the page is cache inhibited and access is guarded unless 444 * it's in our available memory array. 445 */ 446 pte_lo = LPTE_I | LPTE_G; 447 for (i = 0; i < pregions_sz; i++) { 448 if ((pa >= pregions[i].mr_start) && 449 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 450 pte_lo &= ~(LPTE_I | LPTE_G); 451 pte_lo |= LPTE_M; 452 break; 453 } 454 } 455 456 return pte_lo; 457 } 458 459 /* 460 * Quick sort callout for comparing memory regions. 461 */ 462 static int om_cmp(const void *a, const void *b); 463 464 static int 465 om_cmp(const void *a, const void *b) 466 { 467 const struct ofw_map *mapa; 468 const struct ofw_map *mapb; 469 470 mapa = a; 471 mapb = b; 472 if (mapa->om_pa < mapb->om_pa) 473 return (-1); 474 else if (mapa->om_pa > mapb->om_pa) 475 return (1); 476 else 477 return (0); 478 } 479 480 static void 481 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 482 { 483 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 484 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 485 struct pvo_entry *pvo; 486 register_t msr; 487 vm_offset_t off; 488 vm_paddr_t pa_base; 489 int i, j; 490 491 bzero(translations, sz); 492 OF_getprop(OF_finddevice("/"), "#address-cells", &acells, 493 sizeof(acells)); 494 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1) 495 panic("moea64_bootstrap: can't get ofw translations"); 496 497 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 498 sz /= sizeof(cell_t); 499 for (i = 0, j = 0; i < sz; j++) { 500 translations[j].om_va = trans_cells[i++]; 501 translations[j].om_len = trans_cells[i++]; 502 translations[j].om_pa = trans_cells[i++]; 503 if (acells == 2) { 504 translations[j].om_pa <<= 32; 505 translations[j].om_pa |= trans_cells[i++]; 506 } 507 translations[j].om_mode = trans_cells[i++]; 508 } 509 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 510 i, sz)); 511 512 sz = j; 513 qsort(translations, sz, sizeof (*translations), om_cmp); 514 515 for (i = 0; i < sz; i++) { 516 pa_base = translations[i].om_pa; 517 #ifndef __powerpc64__ 518 if ((translations[i].om_pa >> 32) != 0) 519 panic("OFW translations above 32-bit boundary!"); 520 #endif 521 522 if (pa_base % PAGE_SIZE) 523 panic("OFW translation not page-aligned (phys)!"); 524 if (translations[i].om_va % PAGE_SIZE) 525 panic("OFW translation not page-aligned (virt)!"); 526 527 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 528 pa_base, translations[i].om_va, translations[i].om_len); 529 530 /* Now enter the pages for this mapping */ 531 532 DISABLE_TRANS(msr); 533 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 534 /* If this address is direct-mapped, skip remapping */ 535 if (hw_direct_map && translations[i].om_va == pa_base && 536 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 537 continue; 538 539 PMAP_LOCK(kernel_pmap); 540 pvo = moea64_pvo_find_va(kernel_pmap, 541 translations[i].om_va + off); 542 PMAP_UNLOCK(kernel_pmap); 543 if (pvo != NULL) 544 continue; 545 546 moea64_kenter(mmup, translations[i].om_va + off, 547 pa_base + off); 548 } 549 ENABLE_TRANS(msr); 550 } 551 } 552 553 #ifdef __powerpc64__ 554 static void 555 moea64_probe_large_page(void) 556 { 557 uint16_t pvr = mfpvr() >> 16; 558 559 switch (pvr) { 560 case IBM970: 561 case IBM970FX: 562 case IBM970MP: 563 powerpc_sync(); isync(); 564 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 565 powerpc_sync(); isync(); 566 567 /* FALLTHROUGH */ 568 default: 569 moea64_large_page_size = 0x1000000; /* 16 MB */ 570 moea64_large_page_shift = 24; 571 } 572 573 moea64_large_page_mask = moea64_large_page_size - 1; 574 } 575 576 static void 577 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 578 { 579 struct slb *cache; 580 struct slb entry; 581 uint64_t esid, slbe; 582 uint64_t i; 583 584 cache = PCPU_GET(slb); 585 esid = va >> ADDR_SR_SHFT; 586 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 587 588 for (i = 0; i < 64; i++) { 589 if (cache[i].slbe == (slbe | i)) 590 return; 591 } 592 593 entry.slbe = slbe; 594 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 595 if (large) 596 entry.slbv |= SLBV_L; 597 598 slb_insert_kernel(entry.slbe, entry.slbv); 599 } 600 #endif 601 602 static void 603 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 604 vm_offset_t kernelend) 605 { 606 struct pvo_entry *pvo; 607 register_t msr; 608 vm_paddr_t pa; 609 vm_offset_t size, off; 610 uint64_t pte_lo; 611 int i; 612 613 if (moea64_large_page_size == 0) 614 hw_direct_map = 0; 615 616 DISABLE_TRANS(msr); 617 if (hw_direct_map) { 618 PMAP_LOCK(kernel_pmap); 619 for (i = 0; i < pregions_sz; i++) { 620 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 621 pregions[i].mr_size; pa += moea64_large_page_size) { 622 pte_lo = LPTE_M; 623 624 pvo = alloc_pvo_entry(1 /* bootstrap */); 625 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 626 init_pvo_entry(pvo, kernel_pmap, pa); 627 628 /* 629 * Set memory access as guarded if prefetch within 630 * the page could exit the available physmem area. 631 */ 632 if (pa & moea64_large_page_mask) { 633 pa &= moea64_large_page_mask; 634 pte_lo |= LPTE_G; 635 } 636 if (pa + moea64_large_page_size > 637 pregions[i].mr_start + pregions[i].mr_size) 638 pte_lo |= LPTE_G; 639 640 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 641 VM_PROT_EXECUTE; 642 pvo->pvo_pte.pa = pa | pte_lo; 643 moea64_pvo_enter(mmup, pvo, NULL); 644 } 645 } 646 PMAP_UNLOCK(kernel_pmap); 647 } else { 648 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 649 off = (vm_offset_t)(moea64_bpvo_pool); 650 for (pa = off; pa < off + size; pa += PAGE_SIZE) 651 moea64_kenter(mmup, pa, pa); 652 653 /* 654 * Map certain important things, like ourselves. 655 * 656 * NOTE: We do not map the exception vector space. That code is 657 * used only in real mode, and leaving it unmapped allows us to 658 * catch NULL pointer deferences, instead of making NULL a valid 659 * address. 660 */ 661 662 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 663 pa += PAGE_SIZE) 664 moea64_kenter(mmup, pa, pa); 665 } 666 ENABLE_TRANS(msr); 667 668 /* 669 * Allow user to override unmapped_buf_allowed for testing. 670 * XXXKIB Only direct map implementation was tested. 671 */ 672 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 673 &unmapped_buf_allowed)) 674 unmapped_buf_allowed = hw_direct_map; 675 } 676 677 void 678 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 679 { 680 int i, j; 681 vm_size_t physsz, hwphyssz; 682 683 #ifndef __powerpc64__ 684 /* We don't have a direct map since there is no BAT */ 685 hw_direct_map = 0; 686 687 /* Make sure battable is zero, since we have no BAT */ 688 for (i = 0; i < 16; i++) { 689 battable[i].batu = 0; 690 battable[i].batl = 0; 691 } 692 #else 693 moea64_probe_large_page(); 694 695 /* Use a direct map if we have large page support */ 696 if (moea64_large_page_size > 0) 697 hw_direct_map = 1; 698 else 699 hw_direct_map = 0; 700 #endif 701 702 /* Get physical memory regions from firmware */ 703 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 704 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 705 706 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 707 panic("moea64_bootstrap: phys_avail too small"); 708 709 phys_avail_count = 0; 710 physsz = 0; 711 hwphyssz = 0; 712 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 713 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 714 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 715 regions[i].mr_start, regions[i].mr_start + 716 regions[i].mr_size, regions[i].mr_size); 717 if (hwphyssz != 0 && 718 (physsz + regions[i].mr_size) >= hwphyssz) { 719 if (physsz < hwphyssz) { 720 phys_avail[j] = regions[i].mr_start; 721 phys_avail[j + 1] = regions[i].mr_start + 722 hwphyssz - physsz; 723 physsz = hwphyssz; 724 phys_avail_count++; 725 } 726 break; 727 } 728 phys_avail[j] = regions[i].mr_start; 729 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 730 phys_avail_count++; 731 physsz += regions[i].mr_size; 732 } 733 734 /* Check for overlap with the kernel and exception vectors */ 735 for (j = 0; j < 2*phys_avail_count; j+=2) { 736 if (phys_avail[j] < EXC_LAST) 737 phys_avail[j] += EXC_LAST; 738 739 if (kernelstart >= phys_avail[j] && 740 kernelstart < phys_avail[j+1]) { 741 if (kernelend < phys_avail[j+1]) { 742 phys_avail[2*phys_avail_count] = 743 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 744 phys_avail[2*phys_avail_count + 1] = 745 phys_avail[j+1]; 746 phys_avail_count++; 747 } 748 749 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 750 } 751 752 if (kernelend >= phys_avail[j] && 753 kernelend < phys_avail[j+1]) { 754 if (kernelstart > phys_avail[j]) { 755 phys_avail[2*phys_avail_count] = phys_avail[j]; 756 phys_avail[2*phys_avail_count + 1] = 757 kernelstart & ~PAGE_MASK; 758 phys_avail_count++; 759 } 760 761 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 762 } 763 } 764 765 physmem = btoc(physsz); 766 767 #ifdef PTEGCOUNT 768 moea64_pteg_count = PTEGCOUNT; 769 #else 770 moea64_pteg_count = 0x1000; 771 772 while (moea64_pteg_count < physmem) 773 moea64_pteg_count <<= 1; 774 775 moea64_pteg_count >>= 1; 776 #endif /* PTEGCOUNT */ 777 } 778 779 void 780 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 781 { 782 int i; 783 784 /* 785 * Set PTEG mask 786 */ 787 moea64_pteg_mask = moea64_pteg_count - 1; 788 789 /* 790 * Initialize SLB table lock and page locks 791 */ 792 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 793 for (i = 0; i < PV_LOCK_COUNT; i++) 794 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 795 796 /* 797 * Initialise the bootstrap pvo pool. 798 */ 799 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 800 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 801 moea64_bpvo_pool_index = 0; 802 803 /* 804 * Make sure kernel vsid is allocated as well as VSID 0. 805 */ 806 #ifndef __powerpc64__ 807 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 808 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 809 moea64_vsid_bitmap[0] |= 1; 810 #endif 811 812 /* 813 * Initialize the kernel pmap (which is statically allocated). 814 */ 815 #ifdef __powerpc64__ 816 for (i = 0; i < 64; i++) { 817 pcpup->pc_slb[i].slbv = 0; 818 pcpup->pc_slb[i].slbe = 0; 819 } 820 #else 821 for (i = 0; i < 16; i++) 822 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 823 #endif 824 825 kernel_pmap->pmap_phys = kernel_pmap; 826 CPU_FILL(&kernel_pmap->pm_active); 827 RB_INIT(&kernel_pmap->pmap_pvo); 828 829 PMAP_LOCK_INIT(kernel_pmap); 830 831 /* 832 * Now map in all the other buffers we allocated earlier 833 */ 834 835 moea64_setup_direct_map(mmup, kernelstart, kernelend); 836 } 837 838 void 839 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 840 { 841 ihandle_t mmui; 842 phandle_t chosen; 843 phandle_t mmu; 844 ssize_t sz; 845 int i; 846 vm_offset_t pa, va; 847 void *dpcpu; 848 849 /* 850 * Set up the Open Firmware pmap and add its mappings if not in real 851 * mode. 852 */ 853 854 chosen = OF_finddevice("/chosen"); 855 if (!ofw_real_mode && chosen != -1 && 856 OF_getprop(chosen, "mmu", &mmui, 4) != -1) { 857 mmu = OF_instance_to_package(mmui); 858 if (mmu == -1 || 859 (sz = OF_getproplen(mmu, "translations")) == -1) 860 sz = 0; 861 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 862 panic("moea64_bootstrap: too many ofw translations"); 863 864 if (sz > 0) 865 moea64_add_ofw_mappings(mmup, mmu, sz); 866 } 867 868 /* 869 * Calculate the last available physical address. 870 */ 871 for (i = 0; phys_avail[i + 2] != 0; i += 2) 872 ; 873 Maxmem = powerpc_btop(phys_avail[i + 1]); 874 875 /* 876 * Initialize MMU and remap early physical mappings 877 */ 878 MMU_CPU_BOOTSTRAP(mmup,0); 879 mtmsr(mfmsr() | PSL_DR | PSL_IR); 880 pmap_bootstrapped++; 881 bs_remap_earlyboot(); 882 883 /* 884 * Set the start and end of kva. 885 */ 886 virtual_avail = VM_MIN_KERNEL_ADDRESS; 887 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 888 889 /* 890 * Map the entire KVA range into the SLB. We must not fault there. 891 */ 892 #ifdef __powerpc64__ 893 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 894 moea64_bootstrap_slb_prefault(va, 0); 895 #endif 896 897 /* 898 * Figure out how far we can extend virtual_end into segment 16 899 * without running into existing mappings. Segment 16 is guaranteed 900 * to contain neither RAM nor devices (at least on Apple hardware), 901 * but will generally contain some OFW mappings we should not 902 * step on. 903 */ 904 905 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 906 PMAP_LOCK(kernel_pmap); 907 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 908 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 909 virtual_end += PAGE_SIZE; 910 PMAP_UNLOCK(kernel_pmap); 911 #endif 912 913 /* 914 * Allocate a kernel stack with a guard page for thread0 and map it 915 * into the kernel page map. 916 */ 917 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 918 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 919 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 920 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 921 thread0.td_kstack = va; 922 thread0.td_kstack_pages = KSTACK_PAGES; 923 for (i = 0; i < KSTACK_PAGES; i++) { 924 moea64_kenter(mmup, va, pa); 925 pa += PAGE_SIZE; 926 va += PAGE_SIZE; 927 } 928 929 /* 930 * Allocate virtual address space for the message buffer. 931 */ 932 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 933 msgbufp = (struct msgbuf *)virtual_avail; 934 va = virtual_avail; 935 virtual_avail += round_page(msgbufsize); 936 while (va < virtual_avail) { 937 moea64_kenter(mmup, va, pa); 938 pa += PAGE_SIZE; 939 va += PAGE_SIZE; 940 } 941 942 /* 943 * Allocate virtual address space for the dynamic percpu area. 944 */ 945 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 946 dpcpu = (void *)virtual_avail; 947 va = virtual_avail; 948 virtual_avail += DPCPU_SIZE; 949 while (va < virtual_avail) { 950 moea64_kenter(mmup, va, pa); 951 pa += PAGE_SIZE; 952 va += PAGE_SIZE; 953 } 954 dpcpu_init(dpcpu, 0); 955 956 /* 957 * Allocate some things for page zeroing. We put this directly 958 * in the page table and use MOEA64_PTE_REPLACE to avoid any 959 * of the PVO book-keeping or other parts of the VM system 960 * from even knowing that this hack exists. 961 */ 962 963 if (!hw_direct_map) { 964 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 965 MTX_DEF); 966 for (i = 0; i < 2; i++) { 967 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 968 virtual_end -= PAGE_SIZE; 969 970 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 971 972 PMAP_LOCK(kernel_pmap); 973 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 974 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 975 PMAP_UNLOCK(kernel_pmap); 976 } 977 } 978 } 979 980 /* 981 * Activate a user pmap. This mostly involves setting some non-CPU 982 * state. 983 */ 984 void 985 moea64_activate(mmu_t mmu, struct thread *td) 986 { 987 pmap_t pm; 988 989 pm = &td->td_proc->p_vmspace->vm_pmap; 990 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 991 992 #ifdef __powerpc64__ 993 PCPU_SET(userslb, pm->pm_slb); 994 #else 995 PCPU_SET(curpmap, pm->pmap_phys); 996 #endif 997 } 998 999 void 1000 moea64_deactivate(mmu_t mmu, struct thread *td) 1001 { 1002 pmap_t pm; 1003 1004 pm = &td->td_proc->p_vmspace->vm_pmap; 1005 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1006 #ifdef __powerpc64__ 1007 PCPU_SET(userslb, NULL); 1008 #else 1009 PCPU_SET(curpmap, NULL); 1010 #endif 1011 } 1012 1013 void 1014 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1015 { 1016 struct pvo_entry key, *pvo; 1017 vm_page_t m; 1018 int64_t refchg; 1019 1020 key.pvo_vaddr = sva; 1021 PMAP_LOCK(pm); 1022 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1023 pvo != NULL && PVO_VADDR(pvo) < eva; 1024 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1025 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1026 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1027 pvo); 1028 pvo->pvo_vaddr &= ~PVO_WIRED; 1029 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1030 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1031 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1032 if (refchg < 0) 1033 refchg = LPTE_CHG; 1034 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1035 1036 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1037 if (refchg & LPTE_CHG) 1038 vm_page_dirty(m); 1039 if (refchg & LPTE_REF) 1040 vm_page_aflag_set(m, PGA_REFERENCED); 1041 } 1042 pm->pm_stats.wired_count--; 1043 } 1044 PMAP_UNLOCK(pm); 1045 } 1046 1047 /* 1048 * This goes through and sets the physical address of our 1049 * special scratch PTE to the PA we want to zero or copy. Because 1050 * of locking issues (this can get called in pvo_enter() by 1051 * the UMA allocator), we can't use most other utility functions here 1052 */ 1053 1054 static __inline 1055 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) { 1056 1057 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1058 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1059 1060 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1061 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1062 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1063 MOEA64_PTE_INVALIDATE); 1064 isync(); 1065 } 1066 1067 void 1068 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1069 { 1070 vm_offset_t dst; 1071 vm_offset_t src; 1072 1073 dst = VM_PAGE_TO_PHYS(mdst); 1074 src = VM_PAGE_TO_PHYS(msrc); 1075 1076 if (hw_direct_map) { 1077 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1078 } else { 1079 mtx_lock(&moea64_scratchpage_mtx); 1080 1081 moea64_set_scratchpage_pa(mmu, 0, src); 1082 moea64_set_scratchpage_pa(mmu, 1, dst); 1083 1084 bcopy((void *)moea64_scratchpage_va[0], 1085 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1086 1087 mtx_unlock(&moea64_scratchpage_mtx); 1088 } 1089 } 1090 1091 static inline void 1092 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1093 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1094 { 1095 void *a_cp, *b_cp; 1096 vm_offset_t a_pg_offset, b_pg_offset; 1097 int cnt; 1098 1099 while (xfersize > 0) { 1100 a_pg_offset = a_offset & PAGE_MASK; 1101 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1102 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1103 a_pg_offset; 1104 b_pg_offset = b_offset & PAGE_MASK; 1105 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1106 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1107 b_pg_offset; 1108 bcopy(a_cp, b_cp, cnt); 1109 a_offset += cnt; 1110 b_offset += cnt; 1111 xfersize -= cnt; 1112 } 1113 } 1114 1115 static inline void 1116 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1117 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1118 { 1119 void *a_cp, *b_cp; 1120 vm_offset_t a_pg_offset, b_pg_offset; 1121 int cnt; 1122 1123 mtx_lock(&moea64_scratchpage_mtx); 1124 while (xfersize > 0) { 1125 a_pg_offset = a_offset & PAGE_MASK; 1126 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1127 moea64_set_scratchpage_pa(mmu, 0, 1128 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1129 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1130 b_pg_offset = b_offset & PAGE_MASK; 1131 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1132 moea64_set_scratchpage_pa(mmu, 1, 1133 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1134 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1135 bcopy(a_cp, b_cp, cnt); 1136 a_offset += cnt; 1137 b_offset += cnt; 1138 xfersize -= cnt; 1139 } 1140 mtx_unlock(&moea64_scratchpage_mtx); 1141 } 1142 1143 void 1144 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1145 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1146 { 1147 1148 if (hw_direct_map) { 1149 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1150 xfersize); 1151 } else { 1152 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1153 xfersize); 1154 } 1155 } 1156 1157 void 1158 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1159 { 1160 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1161 1162 if (size + off > PAGE_SIZE) 1163 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1164 1165 if (hw_direct_map) { 1166 bzero((caddr_t)pa + off, size); 1167 } else { 1168 mtx_lock(&moea64_scratchpage_mtx); 1169 moea64_set_scratchpage_pa(mmu, 0, pa); 1170 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1171 mtx_unlock(&moea64_scratchpage_mtx); 1172 } 1173 } 1174 1175 /* 1176 * Zero a page of physical memory by temporarily mapping it 1177 */ 1178 void 1179 moea64_zero_page(mmu_t mmu, vm_page_t m) 1180 { 1181 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1182 vm_offset_t va, off; 1183 1184 if (!hw_direct_map) { 1185 mtx_lock(&moea64_scratchpage_mtx); 1186 1187 moea64_set_scratchpage_pa(mmu, 0, pa); 1188 va = moea64_scratchpage_va[0]; 1189 } else { 1190 va = pa; 1191 } 1192 1193 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1194 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1195 1196 if (!hw_direct_map) 1197 mtx_unlock(&moea64_scratchpage_mtx); 1198 } 1199 1200 void 1201 moea64_zero_page_idle(mmu_t mmu, vm_page_t m) 1202 { 1203 1204 moea64_zero_page(mmu, m); 1205 } 1206 1207 /* 1208 * Map the given physical page at the specified virtual address in the 1209 * target pmap with the protection requested. If specified the page 1210 * will be wired down. 1211 */ 1212 1213 int 1214 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1215 vm_prot_t prot, u_int flags, int8_t psind) 1216 { 1217 struct pvo_entry *pvo, *oldpvo; 1218 struct pvo_head *pvo_head; 1219 uint64_t pte_lo; 1220 int error; 1221 1222 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1223 VM_OBJECT_ASSERT_LOCKED(m->object); 1224 1225 pvo = alloc_pvo_entry(0); 1226 pvo->pvo_pmap = NULL; /* to be filled in later */ 1227 pvo->pvo_pte.prot = prot; 1228 1229 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1230 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1231 1232 if ((flags & PMAP_ENTER_WIRED) != 0) 1233 pvo->pvo_vaddr |= PVO_WIRED; 1234 1235 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1236 pvo_head = NULL; 1237 } else { 1238 pvo_head = &m->md.mdpg_pvoh; 1239 pvo->pvo_vaddr |= PVO_MANAGED; 1240 } 1241 1242 for (;;) { 1243 PV_PAGE_LOCK(m); 1244 PMAP_LOCK(pmap); 1245 if (pvo->pvo_pmap == NULL) 1246 init_pvo_entry(pvo, pmap, va); 1247 if (prot & VM_PROT_WRITE) 1248 if (pmap_bootstrapped && 1249 (m->oflags & VPO_UNMANAGED) == 0) 1250 vm_page_aflag_set(m, PGA_WRITEABLE); 1251 1252 oldpvo = moea64_pvo_find_va(pmap, va); 1253 if (oldpvo != NULL) { 1254 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1255 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1256 oldpvo->pvo_pte.prot == prot) { 1257 /* Identical mapping already exists */ 1258 error = 0; 1259 1260 /* If not in page table, reinsert it */ 1261 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1262 moea64_pte_overflow--; 1263 MOEA64_PTE_INSERT(mmu, oldpvo); 1264 } 1265 1266 /* Then just clean up and go home */ 1267 PV_PAGE_UNLOCK(m); 1268 PMAP_UNLOCK(pmap); 1269 free_pvo_entry(pvo); 1270 break; 1271 } 1272 1273 /* Otherwise, need to kill it first */ 1274 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1275 "mapping does not match new mapping")); 1276 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1277 } 1278 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1279 PV_PAGE_UNLOCK(m); 1280 PMAP_UNLOCK(pmap); 1281 1282 /* Free any dead pages */ 1283 if (oldpvo != NULL) { 1284 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1285 moea64_pvo_remove_from_page(mmu, oldpvo); 1286 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1287 free_pvo_entry(oldpvo); 1288 } 1289 1290 if (error != ENOMEM) 1291 break; 1292 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1293 return (KERN_RESOURCE_SHORTAGE); 1294 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1295 VM_WAIT; 1296 } 1297 1298 /* 1299 * Flush the page from the instruction cache if this page is 1300 * mapped executable and cacheable. 1301 */ 1302 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1303 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1304 vm_page_aflag_set(m, PGA_EXECUTABLE); 1305 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1306 } 1307 return (KERN_SUCCESS); 1308 } 1309 1310 static void 1311 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa, 1312 vm_size_t sz) 1313 { 1314 1315 /* 1316 * This is much trickier than on older systems because 1317 * we can't sync the icache on physical addresses directly 1318 * without a direct map. Instead we check a couple of cases 1319 * where the memory is already mapped in and, failing that, 1320 * use the same trick we use for page zeroing to create 1321 * a temporary mapping for this physical address. 1322 */ 1323 1324 if (!pmap_bootstrapped) { 1325 /* 1326 * If PMAP is not bootstrapped, we are likely to be 1327 * in real mode. 1328 */ 1329 __syncicache((void *)pa, sz); 1330 } else if (pmap == kernel_pmap) { 1331 __syncicache((void *)va, sz); 1332 } else if (hw_direct_map) { 1333 __syncicache((void *)pa, sz); 1334 } else { 1335 /* Use the scratch page to set up a temp mapping */ 1336 1337 mtx_lock(&moea64_scratchpage_mtx); 1338 1339 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1340 __syncicache((void *)(moea64_scratchpage_va[1] + 1341 (va & ADDR_POFF)), sz); 1342 1343 mtx_unlock(&moea64_scratchpage_mtx); 1344 } 1345 } 1346 1347 /* 1348 * Maps a sequence of resident pages belonging to the same object. 1349 * The sequence begins with the given page m_start. This page is 1350 * mapped at the given virtual address start. Each subsequent page is 1351 * mapped at a virtual address that is offset from start by the same 1352 * amount as the page is offset from m_start within the object. The 1353 * last page in the sequence is the page with the largest offset from 1354 * m_start that can be mapped at a virtual address less than the given 1355 * virtual address end. Not every virtual page between start and end 1356 * is mapped; only those for which a resident page exists with the 1357 * corresponding offset from m_start are mapped. 1358 */ 1359 void 1360 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1361 vm_page_t m_start, vm_prot_t prot) 1362 { 1363 vm_page_t m; 1364 vm_pindex_t diff, psize; 1365 1366 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1367 1368 psize = atop(end - start); 1369 m = m_start; 1370 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1371 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1372 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1373 m = TAILQ_NEXT(m, listq); 1374 } 1375 } 1376 1377 void 1378 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1379 vm_prot_t prot) 1380 { 1381 1382 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1383 PMAP_ENTER_NOSLEEP, 0); 1384 } 1385 1386 vm_paddr_t 1387 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1388 { 1389 struct pvo_entry *pvo; 1390 vm_paddr_t pa; 1391 1392 PMAP_LOCK(pm); 1393 pvo = moea64_pvo_find_va(pm, va); 1394 if (pvo == NULL) 1395 pa = 0; 1396 else 1397 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1398 PMAP_UNLOCK(pm); 1399 1400 return (pa); 1401 } 1402 1403 /* 1404 * Atomically extract and hold the physical page with the given 1405 * pmap and virtual address pair if that mapping permits the given 1406 * protection. 1407 */ 1408 vm_page_t 1409 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1410 { 1411 struct pvo_entry *pvo; 1412 vm_page_t m; 1413 vm_paddr_t pa; 1414 1415 m = NULL; 1416 pa = 0; 1417 PMAP_LOCK(pmap); 1418 retry: 1419 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1420 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1421 if (vm_page_pa_tryrelock(pmap, 1422 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1423 goto retry; 1424 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1425 vm_page_hold(m); 1426 } 1427 PA_UNLOCK_COND(pa); 1428 PMAP_UNLOCK(pmap); 1429 return (m); 1430 } 1431 1432 static mmu_t installed_mmu; 1433 1434 static void * 1435 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1436 { 1437 struct pvo_entry *pvo; 1438 vm_offset_t va; 1439 vm_page_t m; 1440 int pflags, needed_lock; 1441 1442 /* 1443 * This entire routine is a horrible hack to avoid bothering kmem 1444 * for new KVA addresses. Because this can get called from inside 1445 * kmem allocation routines, calling kmem for a new address here 1446 * can lead to multiply locking non-recursive mutexes. 1447 */ 1448 1449 *flags = UMA_SLAB_PRIV; 1450 needed_lock = !PMAP_LOCKED(kernel_pmap); 1451 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1452 1453 for (;;) { 1454 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1455 if (m == NULL) { 1456 if (wait & M_NOWAIT) 1457 return (NULL); 1458 VM_WAIT; 1459 } else 1460 break; 1461 } 1462 1463 va = VM_PAGE_TO_PHYS(m); 1464 1465 pvo = alloc_pvo_entry(1 /* bootstrap */); 1466 1467 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1468 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1469 1470 if (needed_lock) 1471 PMAP_LOCK(kernel_pmap); 1472 1473 init_pvo_entry(pvo, kernel_pmap, va); 1474 pvo->pvo_vaddr |= PVO_WIRED; 1475 1476 moea64_pvo_enter(installed_mmu, pvo, NULL); 1477 1478 if (needed_lock) 1479 PMAP_UNLOCK(kernel_pmap); 1480 1481 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1482 bzero((void *)va, PAGE_SIZE); 1483 1484 return (void *)va; 1485 } 1486 1487 extern int elf32_nxstack; 1488 1489 void 1490 moea64_init(mmu_t mmu) 1491 { 1492 1493 CTR0(KTR_PMAP, "moea64_init"); 1494 1495 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1496 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1497 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1498 1499 if (!hw_direct_map) { 1500 installed_mmu = mmu; 1501 uma_zone_set_allocf(moea64_pvo_zone,moea64_uma_page_alloc); 1502 } 1503 1504 #ifdef COMPAT_FREEBSD32 1505 elf32_nxstack = 1; 1506 #endif 1507 1508 moea64_initialized = TRUE; 1509 } 1510 1511 boolean_t 1512 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1513 { 1514 1515 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1516 ("moea64_is_referenced: page %p is not managed", m)); 1517 1518 return (moea64_query_bit(mmu, m, LPTE_REF)); 1519 } 1520 1521 boolean_t 1522 moea64_is_modified(mmu_t mmu, vm_page_t m) 1523 { 1524 1525 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1526 ("moea64_is_modified: page %p is not managed", m)); 1527 1528 /* 1529 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1530 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1531 * is clear, no PTEs can have LPTE_CHG set. 1532 */ 1533 VM_OBJECT_ASSERT_LOCKED(m->object); 1534 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1535 return (FALSE); 1536 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1537 } 1538 1539 boolean_t 1540 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1541 { 1542 struct pvo_entry *pvo; 1543 boolean_t rv = TRUE; 1544 1545 PMAP_LOCK(pmap); 1546 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1547 if (pvo != NULL) 1548 rv = FALSE; 1549 PMAP_UNLOCK(pmap); 1550 return (rv); 1551 } 1552 1553 void 1554 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1555 { 1556 1557 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1558 ("moea64_clear_modify: page %p is not managed", m)); 1559 VM_OBJECT_ASSERT_WLOCKED(m->object); 1560 KASSERT(!vm_page_xbusied(m), 1561 ("moea64_clear_modify: page %p is exclusive busied", m)); 1562 1563 /* 1564 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1565 * set. If the object containing the page is locked and the page is 1566 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1567 */ 1568 if ((m->aflags & PGA_WRITEABLE) == 0) 1569 return; 1570 moea64_clear_bit(mmu, m, LPTE_CHG); 1571 } 1572 1573 /* 1574 * Clear the write and modified bits in each of the given page's mappings. 1575 */ 1576 void 1577 moea64_remove_write(mmu_t mmu, vm_page_t m) 1578 { 1579 struct pvo_entry *pvo; 1580 int64_t refchg, ret; 1581 pmap_t pmap; 1582 1583 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1584 ("moea64_remove_write: page %p is not managed", m)); 1585 1586 /* 1587 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1588 * set by another thread while the object is locked. Thus, 1589 * if PGA_WRITEABLE is clear, no page table entries need updating. 1590 */ 1591 VM_OBJECT_ASSERT_WLOCKED(m->object); 1592 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1593 return; 1594 powerpc_sync(); 1595 PV_PAGE_LOCK(m); 1596 refchg = 0; 1597 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1598 pmap = pvo->pvo_pmap; 1599 PMAP_LOCK(pmap); 1600 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1601 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1602 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1603 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1604 MOEA64_PTE_PROT_UPDATE); 1605 if (ret < 0) 1606 ret = LPTE_CHG; 1607 refchg |= ret; 1608 if (pvo->pvo_pmap == kernel_pmap) 1609 isync(); 1610 } 1611 PMAP_UNLOCK(pmap); 1612 } 1613 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1614 vm_page_dirty(m); 1615 vm_page_aflag_clear(m, PGA_WRITEABLE); 1616 PV_PAGE_UNLOCK(m); 1617 } 1618 1619 /* 1620 * moea64_ts_referenced: 1621 * 1622 * Return a count of reference bits for a page, clearing those bits. 1623 * It is not necessary for every reference bit to be cleared, but it 1624 * is necessary that 0 only be returned when there are truly no 1625 * reference bits set. 1626 * 1627 * XXX: The exact number of bits to check and clear is a matter that 1628 * should be tested and standardized at some point in the future for 1629 * optimal aging of shared pages. 1630 */ 1631 int 1632 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1633 { 1634 1635 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1636 ("moea64_ts_referenced: page %p is not managed", m)); 1637 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1638 } 1639 1640 /* 1641 * Modify the WIMG settings of all mappings for a page. 1642 */ 1643 void 1644 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1645 { 1646 struct pvo_entry *pvo; 1647 int64_t refchg; 1648 pmap_t pmap; 1649 uint64_t lo; 1650 1651 if ((m->oflags & VPO_UNMANAGED) != 0) { 1652 m->md.mdpg_cache_attrs = ma; 1653 return; 1654 } 1655 1656 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1657 1658 PV_PAGE_LOCK(m); 1659 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1660 pmap = pvo->pvo_pmap; 1661 PMAP_LOCK(pmap); 1662 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1663 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1664 pvo->pvo_pte.pa |= lo; 1665 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1666 MOEA64_PTE_INVALIDATE); 1667 if (refchg < 0) 1668 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1669 LPTE_CHG : 0; 1670 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1671 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1672 refchg |= 1673 atomic_readandclear_32(&m->md.mdpg_attrs); 1674 if (refchg & LPTE_CHG) 1675 vm_page_dirty(m); 1676 if (refchg & LPTE_REF) 1677 vm_page_aflag_set(m, PGA_REFERENCED); 1678 } 1679 if (pvo->pvo_pmap == kernel_pmap) 1680 isync(); 1681 } 1682 PMAP_UNLOCK(pmap); 1683 } 1684 m->md.mdpg_cache_attrs = ma; 1685 PV_PAGE_UNLOCK(m); 1686 } 1687 1688 /* 1689 * Map a wired page into kernel virtual address space. 1690 */ 1691 void 1692 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1693 { 1694 int error; 1695 struct pvo_entry *pvo, *oldpvo; 1696 1697 pvo = alloc_pvo_entry(0); 1698 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1699 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1700 pvo->pvo_vaddr |= PVO_WIRED; 1701 1702 PMAP_LOCK(kernel_pmap); 1703 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1704 if (oldpvo != NULL) 1705 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1706 init_pvo_entry(pvo, kernel_pmap, va); 1707 error = moea64_pvo_enter(mmu, pvo, NULL); 1708 PMAP_UNLOCK(kernel_pmap); 1709 1710 /* Free any dead pages */ 1711 if (oldpvo != NULL) { 1712 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1713 moea64_pvo_remove_from_page(mmu, oldpvo); 1714 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1715 free_pvo_entry(oldpvo); 1716 } 1717 1718 if (error != 0 && error != ENOENT) 1719 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1720 pa, error); 1721 } 1722 1723 void 1724 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1725 { 1726 1727 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1728 } 1729 1730 /* 1731 * Extract the physical page address associated with the given kernel virtual 1732 * address. 1733 */ 1734 vm_paddr_t 1735 moea64_kextract(mmu_t mmu, vm_offset_t va) 1736 { 1737 struct pvo_entry *pvo; 1738 vm_paddr_t pa; 1739 1740 /* 1741 * Shortcut the direct-mapped case when applicable. We never put 1742 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1743 */ 1744 if (va < VM_MIN_KERNEL_ADDRESS) 1745 return (va); 1746 1747 PMAP_LOCK(kernel_pmap); 1748 pvo = moea64_pvo_find_va(kernel_pmap, va); 1749 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1750 va)); 1751 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1752 PMAP_UNLOCK(kernel_pmap); 1753 return (pa); 1754 } 1755 1756 /* 1757 * Remove a wired page from kernel virtual address space. 1758 */ 1759 void 1760 moea64_kremove(mmu_t mmu, vm_offset_t va) 1761 { 1762 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1763 } 1764 1765 /* 1766 * Map a range of physical addresses into kernel virtual address space. 1767 * 1768 * The value passed in *virt is a suggested virtual address for the mapping. 1769 * Architectures which can support a direct-mapped physical to virtual region 1770 * can return the appropriate address within that region, leaving '*virt' 1771 * unchanged. Other architectures should map the pages starting at '*virt' and 1772 * update '*virt' with the first usable address after the mapped region. 1773 */ 1774 vm_offset_t 1775 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1776 vm_paddr_t pa_end, int prot) 1777 { 1778 vm_offset_t sva, va; 1779 1780 if (hw_direct_map) { 1781 /* 1782 * Check if every page in the region is covered by the direct 1783 * map. The direct map covers all of physical memory. Use 1784 * moea64_calc_wimg() as a shortcut to see if the page is in 1785 * physical memory as a way to see if the direct map covers it. 1786 */ 1787 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1788 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1789 break; 1790 if (va == pa_end) 1791 return (pa_start); 1792 } 1793 sva = *virt; 1794 va = sva; 1795 /* XXX respect prot argument */ 1796 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1797 moea64_kenter(mmu, va, pa_start); 1798 *virt = va; 1799 1800 return (sva); 1801 } 1802 1803 /* 1804 * Returns true if the pmap's pv is one of the first 1805 * 16 pvs linked to from this page. This count may 1806 * be changed upwards or downwards in the future; it 1807 * is only necessary that true be returned for a small 1808 * subset of pmaps for proper page aging. 1809 */ 1810 boolean_t 1811 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1812 { 1813 int loops; 1814 struct pvo_entry *pvo; 1815 boolean_t rv; 1816 1817 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1818 ("moea64_page_exists_quick: page %p is not managed", m)); 1819 loops = 0; 1820 rv = FALSE; 1821 PV_PAGE_LOCK(m); 1822 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1823 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 1824 rv = TRUE; 1825 break; 1826 } 1827 if (++loops >= 16) 1828 break; 1829 } 1830 PV_PAGE_UNLOCK(m); 1831 return (rv); 1832 } 1833 1834 /* 1835 * Return the number of managed mappings to the given physical page 1836 * that are wired. 1837 */ 1838 int 1839 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1840 { 1841 struct pvo_entry *pvo; 1842 int count; 1843 1844 count = 0; 1845 if ((m->oflags & VPO_UNMANAGED) != 0) 1846 return (count); 1847 PV_PAGE_LOCK(m); 1848 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1849 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 1850 count++; 1851 PV_PAGE_UNLOCK(m); 1852 return (count); 1853 } 1854 1855 static uintptr_t moea64_vsidcontext; 1856 1857 uintptr_t 1858 moea64_get_unique_vsid(void) { 1859 u_int entropy; 1860 register_t hash; 1861 uint32_t mask; 1862 int i; 1863 1864 entropy = 0; 1865 __asm __volatile("mftb %0" : "=r"(entropy)); 1866 1867 mtx_lock(&moea64_slb_mutex); 1868 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1869 u_int n; 1870 1871 /* 1872 * Create a new value by mutiplying by a prime and adding in 1873 * entropy from the timebase register. This is to make the 1874 * VSID more random so that the PT hash function collides 1875 * less often. (Note that the prime casues gcc to do shifts 1876 * instead of a multiply.) 1877 */ 1878 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1879 hash = moea64_vsidcontext & (NVSIDS - 1); 1880 if (hash == 0) /* 0 is special, avoid it */ 1881 continue; 1882 n = hash >> 5; 1883 mask = 1 << (hash & (VSID_NBPW - 1)); 1884 hash = (moea64_vsidcontext & VSID_HASHMASK); 1885 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1886 /* anything free in this bucket? */ 1887 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1888 entropy = (moea64_vsidcontext >> 20); 1889 continue; 1890 } 1891 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1892 mask = 1 << i; 1893 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1); 1894 hash |= i; 1895 } 1896 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1897 ("Allocating in-use VSID %#zx\n", hash)); 1898 moea64_vsid_bitmap[n] |= mask; 1899 mtx_unlock(&moea64_slb_mutex); 1900 return (hash); 1901 } 1902 1903 mtx_unlock(&moea64_slb_mutex); 1904 panic("%s: out of segments",__func__); 1905 } 1906 1907 #ifdef __powerpc64__ 1908 void 1909 moea64_pinit(mmu_t mmu, pmap_t pmap) 1910 { 1911 1912 RB_INIT(&pmap->pmap_pvo); 1913 1914 pmap->pm_slb_tree_root = slb_alloc_tree(); 1915 pmap->pm_slb = slb_alloc_user_cache(); 1916 pmap->pm_slb_len = 0; 1917 } 1918 #else 1919 void 1920 moea64_pinit(mmu_t mmu, pmap_t pmap) 1921 { 1922 int i; 1923 uint32_t hash; 1924 1925 RB_INIT(&pmap->pmap_pvo); 1926 1927 if (pmap_bootstrapped) 1928 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1929 (vm_offset_t)pmap); 1930 else 1931 pmap->pmap_phys = pmap; 1932 1933 /* 1934 * Allocate some segment registers for this pmap. 1935 */ 1936 hash = moea64_get_unique_vsid(); 1937 1938 for (i = 0; i < 16; i++) 1939 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1940 1941 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 1942 } 1943 #endif 1944 1945 /* 1946 * Initialize the pmap associated with process 0. 1947 */ 1948 void 1949 moea64_pinit0(mmu_t mmu, pmap_t pm) 1950 { 1951 1952 PMAP_LOCK_INIT(pm); 1953 moea64_pinit(mmu, pm); 1954 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1955 } 1956 1957 /* 1958 * Set the physical protection on the specified range of this map as requested. 1959 */ 1960 static void 1961 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 1962 { 1963 struct vm_page *pg; 1964 vm_prot_t oldprot; 1965 int32_t refchg; 1966 1967 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1968 1969 /* 1970 * Change the protection of the page. 1971 */ 1972 oldprot = pvo->pvo_pte.prot; 1973 pvo->pvo_pte.prot = prot; 1974 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1975 1976 /* 1977 * If the PVO is in the page table, update mapping 1978 */ 1979 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 1980 if (refchg < 0) 1981 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 1982 1983 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 1984 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1985 if ((pg->oflags & VPO_UNMANAGED) == 0) 1986 vm_page_aflag_set(pg, PGA_EXECUTABLE); 1987 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 1988 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 1989 } 1990 1991 /* 1992 * Update vm about the REF/CHG bits if the page is managed and we have 1993 * removed write access. 1994 */ 1995 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 1996 (oldprot & VM_PROT_WRITE)) { 1997 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 1998 if (refchg & LPTE_CHG) 1999 vm_page_dirty(pg); 2000 if (refchg & LPTE_REF) 2001 vm_page_aflag_set(pg, PGA_REFERENCED); 2002 } 2003 } 2004 2005 void 2006 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2007 vm_prot_t prot) 2008 { 2009 struct pvo_entry *pvo, *tpvo, key; 2010 2011 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2012 sva, eva, prot); 2013 2014 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2015 ("moea64_protect: non current pmap")); 2016 2017 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2018 moea64_remove(mmu, pm, sva, eva); 2019 return; 2020 } 2021 2022 PMAP_LOCK(pm); 2023 key.pvo_vaddr = sva; 2024 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2025 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2026 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2027 moea64_pvo_protect(mmu, pm, pvo, prot); 2028 } 2029 PMAP_UNLOCK(pm); 2030 } 2031 2032 /* 2033 * Map a list of wired pages into kernel virtual address space. This is 2034 * intended for temporary mappings which do not need page modification or 2035 * references recorded. Existing mappings in the region are overwritten. 2036 */ 2037 void 2038 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2039 { 2040 while (count-- > 0) { 2041 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2042 va += PAGE_SIZE; 2043 m++; 2044 } 2045 } 2046 2047 /* 2048 * Remove page mappings from kernel virtual address space. Intended for 2049 * temporary mappings entered by moea64_qenter. 2050 */ 2051 void 2052 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2053 { 2054 while (count-- > 0) { 2055 moea64_kremove(mmu, va); 2056 va += PAGE_SIZE; 2057 } 2058 } 2059 2060 void 2061 moea64_release_vsid(uint64_t vsid) 2062 { 2063 int idx, mask; 2064 2065 mtx_lock(&moea64_slb_mutex); 2066 idx = vsid & (NVSIDS-1); 2067 mask = 1 << (idx % VSID_NBPW); 2068 idx /= VSID_NBPW; 2069 KASSERT(moea64_vsid_bitmap[idx] & mask, 2070 ("Freeing unallocated VSID %#jx", vsid)); 2071 moea64_vsid_bitmap[idx] &= ~mask; 2072 mtx_unlock(&moea64_slb_mutex); 2073 } 2074 2075 2076 void 2077 moea64_release(mmu_t mmu, pmap_t pmap) 2078 { 2079 2080 /* 2081 * Free segment registers' VSIDs 2082 */ 2083 #ifdef __powerpc64__ 2084 slb_free_tree(pmap); 2085 slb_free_user_cache(pmap->pm_slb); 2086 #else 2087 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2088 2089 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2090 #endif 2091 } 2092 2093 /* 2094 * Remove all pages mapped by the specified pmap 2095 */ 2096 void 2097 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2098 { 2099 struct pvo_entry *pvo, *tpvo; 2100 struct pvo_tree tofree; 2101 2102 RB_INIT(&tofree); 2103 2104 PMAP_LOCK(pm); 2105 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2106 if (pvo->pvo_vaddr & PVO_WIRED) 2107 continue; 2108 2109 /* 2110 * For locking reasons, remove this from the page table and 2111 * pmap, but save delinking from the vm_page for a second 2112 * pass 2113 */ 2114 moea64_pvo_remove_from_pmap(mmu, pvo); 2115 RB_INSERT(pvo_tree, &tofree, pvo); 2116 } 2117 PMAP_UNLOCK(pm); 2118 2119 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2120 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2121 moea64_pvo_remove_from_page(mmu, pvo); 2122 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2123 RB_REMOVE(pvo_tree, &tofree, pvo); 2124 free_pvo_entry(pvo); 2125 } 2126 } 2127 2128 /* 2129 * Remove the given range of addresses from the specified map. 2130 */ 2131 void 2132 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2133 { 2134 struct pvo_entry *pvo, *tpvo, key; 2135 struct pvo_tree tofree; 2136 2137 /* 2138 * Perform an unsynchronized read. This is, however, safe. 2139 */ 2140 if (pm->pm_stats.resident_count == 0) 2141 return; 2142 2143 key.pvo_vaddr = sva; 2144 2145 RB_INIT(&tofree); 2146 2147 PMAP_LOCK(pm); 2148 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2149 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2150 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2151 2152 /* 2153 * For locking reasons, remove this from the page table and 2154 * pmap, but save delinking from the vm_page for a second 2155 * pass 2156 */ 2157 moea64_pvo_remove_from_pmap(mmu, pvo); 2158 RB_INSERT(pvo_tree, &tofree, pvo); 2159 } 2160 PMAP_UNLOCK(pm); 2161 2162 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2163 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2164 moea64_pvo_remove_from_page(mmu, pvo); 2165 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2166 RB_REMOVE(pvo_tree, &tofree, pvo); 2167 free_pvo_entry(pvo); 2168 } 2169 } 2170 2171 /* 2172 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2173 * will reflect changes in pte's back to the vm_page. 2174 */ 2175 void 2176 moea64_remove_all(mmu_t mmu, vm_page_t m) 2177 { 2178 struct pvo_entry *pvo, *next_pvo; 2179 struct pvo_head freequeue; 2180 int wasdead; 2181 pmap_t pmap; 2182 2183 LIST_INIT(&freequeue); 2184 2185 PV_PAGE_LOCK(m); 2186 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2187 pmap = pvo->pvo_pmap; 2188 PMAP_LOCK(pmap); 2189 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2190 if (!wasdead) 2191 moea64_pvo_remove_from_pmap(mmu, pvo); 2192 moea64_pvo_remove_from_page(mmu, pvo); 2193 if (!wasdead) 2194 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2195 PMAP_UNLOCK(pmap); 2196 2197 } 2198 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2199 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2200 PV_PAGE_UNLOCK(m); 2201 2202 /* Clean up UMA allocations */ 2203 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2204 free_pvo_entry(pvo); 2205 } 2206 2207 /* 2208 * Allocate a physical page of memory directly from the phys_avail map. 2209 * Can only be called from moea64_bootstrap before avail start and end are 2210 * calculated. 2211 */ 2212 vm_offset_t 2213 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2214 { 2215 vm_offset_t s, e; 2216 int i, j; 2217 2218 size = round_page(size); 2219 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2220 if (align != 0) 2221 s = (phys_avail[i] + align - 1) & ~(align - 1); 2222 else 2223 s = phys_avail[i]; 2224 e = s + size; 2225 2226 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2227 continue; 2228 2229 if (s + size > platform_real_maxaddr()) 2230 continue; 2231 2232 if (s == phys_avail[i]) { 2233 phys_avail[i] += size; 2234 } else if (e == phys_avail[i + 1]) { 2235 phys_avail[i + 1] -= size; 2236 } else { 2237 for (j = phys_avail_count * 2; j > i; j -= 2) { 2238 phys_avail[j] = phys_avail[j - 2]; 2239 phys_avail[j + 1] = phys_avail[j - 1]; 2240 } 2241 2242 phys_avail[i + 3] = phys_avail[i + 1]; 2243 phys_avail[i + 1] = s; 2244 phys_avail[i + 2] = e; 2245 phys_avail_count++; 2246 } 2247 2248 return (s); 2249 } 2250 panic("moea64_bootstrap_alloc: could not allocate memory"); 2251 } 2252 2253 static int 2254 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2255 { 2256 int first, err; 2257 2258 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2259 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2260 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2261 2262 moea64_pvo_enter_calls++; 2263 2264 /* 2265 * Add to pmap list 2266 */ 2267 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2268 2269 /* 2270 * Remember if the list was empty and therefore will be the first 2271 * item. 2272 */ 2273 if (pvo_head != NULL) { 2274 if (LIST_FIRST(pvo_head) == NULL) 2275 first = 1; 2276 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2277 } 2278 2279 if (pvo->pvo_vaddr & PVO_WIRED) 2280 pvo->pvo_pmap->pm_stats.wired_count++; 2281 pvo->pvo_pmap->pm_stats.resident_count++; 2282 2283 /* 2284 * Insert it into the hardware page table 2285 */ 2286 err = MOEA64_PTE_INSERT(mmu, pvo); 2287 if (err != 0) { 2288 panic("moea64_pvo_enter: overflow"); 2289 } 2290 2291 moea64_pvo_entries++; 2292 2293 if (pvo->pvo_pmap == kernel_pmap) 2294 isync(); 2295 2296 #ifdef __powerpc64__ 2297 /* 2298 * Make sure all our bootstrap mappings are in the SLB as soon 2299 * as virtual memory is switched on. 2300 */ 2301 if (!pmap_bootstrapped) 2302 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2303 pvo->pvo_vaddr & PVO_LARGE); 2304 #endif 2305 2306 return (first ? ENOENT : 0); 2307 } 2308 2309 static void 2310 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2311 { 2312 struct vm_page *pg; 2313 int32_t refchg; 2314 2315 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2316 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2317 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2318 2319 /* 2320 * If there is an active pte entry, we need to deactivate it 2321 */ 2322 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2323 if (refchg < 0) { 2324 /* 2325 * If it was evicted from the page table, be pessimistic and 2326 * dirty the page. 2327 */ 2328 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2329 refchg = LPTE_CHG; 2330 else 2331 refchg = 0; 2332 } 2333 2334 /* 2335 * Update our statistics. 2336 */ 2337 pvo->pvo_pmap->pm_stats.resident_count--; 2338 if (pvo->pvo_vaddr & PVO_WIRED) 2339 pvo->pvo_pmap->pm_stats.wired_count--; 2340 2341 /* 2342 * Remove this PVO from the pmap list. 2343 */ 2344 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2345 2346 /* 2347 * Mark this for the next sweep 2348 */ 2349 pvo->pvo_vaddr |= PVO_DEAD; 2350 2351 /* Send RC bits to VM */ 2352 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2353 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2354 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2355 if (pg != NULL) { 2356 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2357 if (refchg & LPTE_CHG) 2358 vm_page_dirty(pg); 2359 if (refchg & LPTE_REF) 2360 vm_page_aflag_set(pg, PGA_REFERENCED); 2361 } 2362 } 2363 } 2364 2365 static void 2366 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2367 { 2368 struct vm_page *pg; 2369 2370 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2371 2372 /* Use NULL pmaps as a sentinel for races in page deletion */ 2373 if (pvo->pvo_pmap == NULL) 2374 return; 2375 pvo->pvo_pmap = NULL; 2376 2377 /* 2378 * Update vm about page writeability/executability if managed 2379 */ 2380 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2381 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2382 2383 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) { 2384 LIST_REMOVE(pvo, pvo_vlink); 2385 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2386 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE); 2387 } 2388 2389 moea64_pvo_entries--; 2390 moea64_pvo_remove_calls++; 2391 } 2392 2393 static struct pvo_entry * 2394 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2395 { 2396 struct pvo_entry key; 2397 2398 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2399 2400 key.pvo_vaddr = va & ~ADDR_POFF; 2401 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2402 } 2403 2404 static boolean_t 2405 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2406 { 2407 struct pvo_entry *pvo; 2408 int64_t ret; 2409 boolean_t rv; 2410 2411 /* 2412 * See if this bit is stored in the page already. 2413 */ 2414 if (m->md.mdpg_attrs & ptebit) 2415 return (TRUE); 2416 2417 /* 2418 * Examine each PTE. Sync so that any pending REF/CHG bits are 2419 * flushed to the PTEs. 2420 */ 2421 rv = FALSE; 2422 powerpc_sync(); 2423 PV_PAGE_LOCK(m); 2424 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2425 ret = 0; 2426 2427 /* 2428 * See if this pvo has a valid PTE. if so, fetch the 2429 * REF/CHG bits from the valid PTE. If the appropriate 2430 * ptebit is set, return success. 2431 */ 2432 PMAP_LOCK(pvo->pvo_pmap); 2433 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2434 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2435 PMAP_UNLOCK(pvo->pvo_pmap); 2436 2437 if (ret > 0) { 2438 atomic_set_32(&m->md.mdpg_attrs, 2439 ret & (LPTE_CHG | LPTE_REF)); 2440 if (ret & ptebit) { 2441 rv = TRUE; 2442 break; 2443 } 2444 } 2445 } 2446 PV_PAGE_UNLOCK(m); 2447 2448 return (rv); 2449 } 2450 2451 static u_int 2452 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2453 { 2454 u_int count; 2455 struct pvo_entry *pvo; 2456 int64_t ret; 2457 2458 /* 2459 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2460 * we can reset the right ones). 2461 */ 2462 powerpc_sync(); 2463 2464 /* 2465 * For each pvo entry, clear the pte's ptebit. 2466 */ 2467 count = 0; 2468 PV_PAGE_LOCK(m); 2469 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2470 ret = 0; 2471 2472 PMAP_LOCK(pvo->pvo_pmap); 2473 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2474 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2475 PMAP_UNLOCK(pvo->pvo_pmap); 2476 2477 if (ret > 0 && (ret & ptebit)) 2478 count++; 2479 } 2480 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2481 PV_PAGE_UNLOCK(m); 2482 2483 return (count); 2484 } 2485 2486 boolean_t 2487 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2488 { 2489 struct pvo_entry *pvo, key; 2490 vm_offset_t ppa; 2491 int error = 0; 2492 2493 PMAP_LOCK(kernel_pmap); 2494 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2495 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2496 ppa < pa + size; ppa += PAGE_SIZE, 2497 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2498 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2499 error = EFAULT; 2500 break; 2501 } 2502 } 2503 PMAP_UNLOCK(kernel_pmap); 2504 2505 return (error); 2506 } 2507 2508 /* 2509 * Map a set of physical memory pages into the kernel virtual 2510 * address space. Return a pointer to where it is mapped. This 2511 * routine is intended to be used for mapping device memory, 2512 * NOT real memory. 2513 */ 2514 void * 2515 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2516 { 2517 vm_offset_t va, tmpva, ppa, offset; 2518 2519 ppa = trunc_page(pa); 2520 offset = pa & PAGE_MASK; 2521 size = roundup2(offset + size, PAGE_SIZE); 2522 2523 va = kva_alloc(size); 2524 2525 if (!va) 2526 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2527 2528 for (tmpva = va; size > 0;) { 2529 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2530 size -= PAGE_SIZE; 2531 tmpva += PAGE_SIZE; 2532 ppa += PAGE_SIZE; 2533 } 2534 2535 return ((void *)(va + offset)); 2536 } 2537 2538 void * 2539 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2540 { 2541 2542 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2543 } 2544 2545 void 2546 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2547 { 2548 vm_offset_t base, offset; 2549 2550 base = trunc_page(va); 2551 offset = va & PAGE_MASK; 2552 size = roundup2(offset + size, PAGE_SIZE); 2553 2554 kva_free(base, size); 2555 } 2556 2557 void 2558 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2559 { 2560 struct pvo_entry *pvo; 2561 vm_offset_t lim; 2562 vm_paddr_t pa; 2563 vm_size_t len; 2564 2565 PMAP_LOCK(pm); 2566 while (sz > 0) { 2567 lim = round_page(va); 2568 len = MIN(lim - va, sz); 2569 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2570 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2571 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2572 moea64_syncicache(mmu, pm, va, pa, len); 2573 } 2574 va += len; 2575 sz -= len; 2576 } 2577 PMAP_UNLOCK(pm); 2578 } 2579 2580 void 2581 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2582 { 2583 2584 *va = (void *)pa; 2585 } 2586 2587 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2588 2589 void 2590 moea64_scan_init(mmu_t mmu) 2591 { 2592 struct pvo_entry *pvo; 2593 vm_offset_t va; 2594 int i; 2595 2596 if (!do_minidump) { 2597 /* Initialize phys. segments for dumpsys(). */ 2598 memset(&dump_map, 0, sizeof(dump_map)); 2599 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2600 for (i = 0; i < pregions_sz; i++) { 2601 dump_map[i].pa_start = pregions[i].mr_start; 2602 dump_map[i].pa_size = pregions[i].mr_size; 2603 } 2604 return; 2605 } 2606 2607 /* Virtual segments for minidumps: */ 2608 memset(&dump_map, 0, sizeof(dump_map)); 2609 2610 /* 1st: kernel .data and .bss. */ 2611 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2612 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2613 dump_map[0].pa_start; 2614 2615 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2616 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2617 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2618 2619 /* 3rd: kernel VM. */ 2620 va = dump_map[1].pa_start + dump_map[1].pa_size; 2621 /* Find start of next chunk (from va). */ 2622 while (va < virtual_end) { 2623 /* Don't dump the buffer cache. */ 2624 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2625 va = kmi.buffer_eva; 2626 continue; 2627 } 2628 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2629 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2630 break; 2631 va += PAGE_SIZE; 2632 } 2633 if (va < virtual_end) { 2634 dump_map[2].pa_start = va; 2635 va += PAGE_SIZE; 2636 /* Find last page in chunk. */ 2637 while (va < virtual_end) { 2638 /* Don't run into the buffer cache. */ 2639 if (va == kmi.buffer_sva) 2640 break; 2641 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2642 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2643 break; 2644 va += PAGE_SIZE; 2645 } 2646 dump_map[2].pa_size = va - dump_map[2].pa_start; 2647 } 2648 } 2649 2650