1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/powerpc.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/smp.h> 151 #include <machine/sr.h> 152 #include <machine/mmuvar.h> 153 154 #include "mmu_if.h" 155 156 #define MOEA_DEBUG 157 158 #define TODO panic("%s: not implemented", __func__); 159 160 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 161 #define TLBSYNC() __asm __volatile("tlbsync"); 162 #define SYNC() __asm __volatile("sync"); 163 #define EIEIO() __asm __volatile("eieio"); 164 165 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 166 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 167 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 168 169 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 170 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 171 #define PVO_WIRED 0x010 /* PVO entry is wired */ 172 #define PVO_MANAGED 0x020 /* PVO entry is managed */ 173 #define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 174 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 175 bootstrap */ 176 #define PVO_FAKE 0x100 /* fictitious phys page */ 177 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 178 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 179 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 180 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 181 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 182 #define PVO_PTEGIDX_CLR(pvo) \ 183 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 184 #define PVO_PTEGIDX_SET(pvo, i) \ 185 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 186 187 #define MOEA_PVO_CHECK(pvo) 188 189 struct ofw_map { 190 vm_offset_t om_va; 191 vm_size_t om_len; 192 vm_offset_t om_pa; 193 u_int om_mode; 194 }; 195 196 /* 197 * Map of physical memory regions. 198 */ 199 static struct mem_region *regions; 200 static struct mem_region *pregions; 201 u_int phys_avail_count; 202 int regions_sz, pregions_sz; 203 static struct ofw_map *translations; 204 205 extern struct pmap ofw_pmap; 206 207 /* 208 * Lock for the pteg and pvo tables. 209 */ 210 struct mtx moea_table_mutex; 211 212 /* 213 * PTEG data. 214 */ 215 static struct pteg *moea_pteg_table; 216 u_int moea_pteg_count; 217 u_int moea_pteg_mask; 218 219 /* 220 * PVO data. 221 */ 222 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 223 struct pvo_head moea_pvo_kunmanaged = 224 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 225 struct pvo_head moea_pvo_unmanaged = 226 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 227 228 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 229 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 230 231 #define BPVO_POOL_SIZE 32768 232 static struct pvo_entry *moea_bpvo_pool; 233 static int moea_bpvo_pool_index = 0; 234 235 #define VSID_NBPW (sizeof(u_int32_t) * 8) 236 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 237 238 static boolean_t moea_initialized = FALSE; 239 240 /* 241 * Statistics. 242 */ 243 u_int moea_pte_valid = 0; 244 u_int moea_pte_overflow = 0; 245 u_int moea_pte_replacements = 0; 246 u_int moea_pvo_entries = 0; 247 u_int moea_pvo_enter_calls = 0; 248 u_int moea_pvo_remove_calls = 0; 249 u_int moea_pte_spills = 0; 250 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 251 0, ""); 252 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 253 &moea_pte_overflow, 0, ""); 254 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 255 &moea_pte_replacements, 0, ""); 256 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 257 0, ""); 258 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 259 &moea_pvo_enter_calls, 0, ""); 260 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 261 &moea_pvo_remove_calls, 0, ""); 262 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 263 &moea_pte_spills, 0, ""); 264 265 /* 266 * Allocate physical memory for use in moea_bootstrap. 267 */ 268 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 269 270 /* 271 * PTE calls. 272 */ 273 static int moea_pte_insert(u_int, struct pte *); 274 275 /* 276 * PVO calls. 277 */ 278 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 279 vm_offset_t, vm_offset_t, u_int, int); 280 static void moea_pvo_remove(struct pvo_entry *, int); 281 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 282 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 283 284 /* 285 * Utility routines. 286 */ 287 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 288 vm_prot_t, boolean_t); 289 static void moea_syncicache(vm_offset_t, vm_size_t); 290 static boolean_t moea_query_bit(vm_page_t, int); 291 static u_int moea_clear_bit(vm_page_t, int, int *); 292 static void moea_kremove(mmu_t, vm_offset_t); 293 static void tlbia(void); 294 int moea_pte_spill(vm_offset_t); 295 296 /* 297 * Kernel MMU interface 298 */ 299 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 300 void moea_clear_modify(mmu_t, vm_page_t); 301 void moea_clear_reference(mmu_t, vm_page_t); 302 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 303 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 304 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 305 vm_prot_t); 306 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 307 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 308 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 309 void moea_init(mmu_t); 310 boolean_t moea_is_modified(mmu_t, vm_page_t); 311 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 312 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 313 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 314 int moea_page_wired_mappings(mmu_t, vm_page_t); 315 void moea_pinit(mmu_t, pmap_t); 316 void moea_pinit0(mmu_t, pmap_t); 317 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 318 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 319 void moea_qremove(mmu_t, vm_offset_t, int); 320 void moea_release(mmu_t, pmap_t); 321 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 322 void moea_remove_all(mmu_t, vm_page_t); 323 void moea_remove_write(mmu_t, vm_page_t); 324 void moea_zero_page(mmu_t, vm_page_t); 325 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 326 void moea_zero_page_idle(mmu_t, vm_page_t); 327 void moea_activate(mmu_t, struct thread *); 328 void moea_deactivate(mmu_t, struct thread *); 329 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 330 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 331 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 332 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 333 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 334 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 335 boolean_t moea_page_executable(mmu_t, vm_page_t); 336 337 static mmu_method_t moea_methods[] = { 338 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 339 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 340 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 341 MMUMETHOD(mmu_copy_page, moea_copy_page), 342 MMUMETHOD(mmu_enter, moea_enter), 343 MMUMETHOD(mmu_enter_object, moea_enter_object), 344 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 345 MMUMETHOD(mmu_extract, moea_extract), 346 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 347 MMUMETHOD(mmu_init, moea_init), 348 MMUMETHOD(mmu_is_modified, moea_is_modified), 349 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 350 MMUMETHOD(mmu_map, moea_map), 351 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 352 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 353 MMUMETHOD(mmu_pinit, moea_pinit), 354 MMUMETHOD(mmu_pinit0, moea_pinit0), 355 MMUMETHOD(mmu_protect, moea_protect), 356 MMUMETHOD(mmu_qenter, moea_qenter), 357 MMUMETHOD(mmu_qremove, moea_qremove), 358 MMUMETHOD(mmu_release, moea_release), 359 MMUMETHOD(mmu_remove, moea_remove), 360 MMUMETHOD(mmu_remove_all, moea_remove_all), 361 MMUMETHOD(mmu_remove_write, moea_remove_write), 362 MMUMETHOD(mmu_zero_page, moea_zero_page), 363 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 364 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 365 MMUMETHOD(mmu_activate, moea_activate), 366 MMUMETHOD(mmu_deactivate, moea_deactivate), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 370 MMUMETHOD(mmu_mapdev, moea_mapdev), 371 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 372 MMUMETHOD(mmu_kextract, moea_kextract), 373 MMUMETHOD(mmu_kenter, moea_kenter), 374 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 375 MMUMETHOD(mmu_page_executable, moea_page_executable), 376 377 { 0, 0 } 378 }; 379 380 static mmu_def_t oea_mmu = { 381 MMU_TYPE_OEA, 382 moea_methods, 383 0 384 }; 385 MMU_DEF(oea_mmu); 386 387 388 static __inline int 389 va_to_sr(u_int *sr, vm_offset_t va) 390 { 391 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 392 } 393 394 static __inline u_int 395 va_to_pteg(u_int sr, vm_offset_t addr) 396 { 397 u_int hash; 398 399 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 400 ADDR_PIDX_SHFT); 401 return (hash & moea_pteg_mask); 402 } 403 404 static __inline struct pvo_head * 405 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 406 { 407 struct vm_page *pg; 408 409 pg = PHYS_TO_VM_PAGE(pa); 410 411 if (pg_p != NULL) 412 *pg_p = pg; 413 414 if (pg == NULL) 415 return (&moea_pvo_unmanaged); 416 417 return (&pg->md.mdpg_pvoh); 418 } 419 420 static __inline struct pvo_head * 421 vm_page_to_pvoh(vm_page_t m) 422 { 423 424 return (&m->md.mdpg_pvoh); 425 } 426 427 static __inline void 428 moea_attr_clear(vm_page_t m, int ptebit) 429 { 430 431 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 432 m->md.mdpg_attrs &= ~ptebit; 433 } 434 435 static __inline int 436 moea_attr_fetch(vm_page_t m) 437 { 438 439 return (m->md.mdpg_attrs); 440 } 441 442 static __inline void 443 moea_attr_save(vm_page_t m, int ptebit) 444 { 445 446 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 447 m->md.mdpg_attrs |= ptebit; 448 } 449 450 static __inline int 451 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 452 { 453 if (pt->pte_hi == pvo_pt->pte_hi) 454 return (1); 455 456 return (0); 457 } 458 459 static __inline int 460 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 461 { 462 return (pt->pte_hi & ~PTE_VALID) == 463 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 464 ((va >> ADDR_API_SHFT) & PTE_API) | which); 465 } 466 467 static __inline void 468 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 469 { 470 471 mtx_assert(&moea_table_mutex, MA_OWNED); 472 473 /* 474 * Construct a PTE. Default to IMB initially. Valid bit only gets 475 * set when the real pte is set in memory. 476 * 477 * Note: Don't set the valid bit for correct operation of tlb update. 478 */ 479 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 480 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 481 pt->pte_lo = pte_lo; 482 } 483 484 static __inline void 485 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 486 { 487 488 mtx_assert(&moea_table_mutex, MA_OWNED); 489 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 490 } 491 492 static __inline void 493 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 494 { 495 496 mtx_assert(&moea_table_mutex, MA_OWNED); 497 498 /* 499 * As shown in Section 7.6.3.2.3 500 */ 501 pt->pte_lo &= ~ptebit; 502 TLBIE(va); 503 EIEIO(); 504 TLBSYNC(); 505 SYNC(); 506 } 507 508 static __inline void 509 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 510 { 511 512 mtx_assert(&moea_table_mutex, MA_OWNED); 513 pvo_pt->pte_hi |= PTE_VALID; 514 515 /* 516 * Update the PTE as defined in section 7.6.3.1. 517 * Note that the REF/CHG bits are from pvo_pt and thus should havce 518 * been saved so this routine can restore them (if desired). 519 */ 520 pt->pte_lo = pvo_pt->pte_lo; 521 EIEIO(); 522 pt->pte_hi = pvo_pt->pte_hi; 523 SYNC(); 524 moea_pte_valid++; 525 } 526 527 static __inline void 528 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 529 { 530 531 mtx_assert(&moea_table_mutex, MA_OWNED); 532 pvo_pt->pte_hi &= ~PTE_VALID; 533 534 /* 535 * Force the reg & chg bits back into the PTEs. 536 */ 537 SYNC(); 538 539 /* 540 * Invalidate the pte. 541 */ 542 pt->pte_hi &= ~PTE_VALID; 543 544 SYNC(); 545 TLBIE(va); 546 EIEIO(); 547 TLBSYNC(); 548 SYNC(); 549 550 /* 551 * Save the reg & chg bits. 552 */ 553 moea_pte_synch(pt, pvo_pt); 554 moea_pte_valid--; 555 } 556 557 static __inline void 558 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 559 { 560 561 /* 562 * Invalidate the PTE 563 */ 564 moea_pte_unset(pt, pvo_pt, va); 565 moea_pte_set(pt, pvo_pt); 566 } 567 568 /* 569 * Quick sort callout for comparing memory regions. 570 */ 571 static int mr_cmp(const void *a, const void *b); 572 static int om_cmp(const void *a, const void *b); 573 574 static int 575 mr_cmp(const void *a, const void *b) 576 { 577 const struct mem_region *regiona; 578 const struct mem_region *regionb; 579 580 regiona = a; 581 regionb = b; 582 if (regiona->mr_start < regionb->mr_start) 583 return (-1); 584 else if (regiona->mr_start > regionb->mr_start) 585 return (1); 586 else 587 return (0); 588 } 589 590 static int 591 om_cmp(const void *a, const void *b) 592 { 593 const struct ofw_map *mapa; 594 const struct ofw_map *mapb; 595 596 mapa = a; 597 mapb = b; 598 if (mapa->om_pa < mapb->om_pa) 599 return (-1); 600 else if (mapa->om_pa > mapb->om_pa) 601 return (1); 602 else 603 return (0); 604 } 605 606 void 607 pmap_cpu_bootstrap(volatile uint32_t *trcp, int ap) 608 { 609 u_int sdr; 610 int i; 611 612 trcp[0] = 0x1000; 613 trcp[1] = (uint32_t)&pmap_cpu_bootstrap; 614 615 if (ap) { 616 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 617 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 618 isync(); 619 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 620 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 621 isync(); 622 } 623 624 trcp[0] = 0x1001; 625 626 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 627 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 628 isync(); 629 630 trcp[0] = 0x1002; 631 632 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 633 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 634 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 635 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 636 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 637 isync(); 638 639 trcp[0] = 0x1003; 640 641 for (i = 0; i < 16; i++) 642 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 643 644 trcp[0] = 0x1004; 645 646 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 647 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 648 __asm __volatile("sync"); 649 650 trcp[0] = 0x1005; 651 652 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 653 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 654 isync(); 655 656 trcp[0] = 0x1006; 657 trcp[1] = sdr; 658 659 tlbia(); 660 661 trcp[0] = 0x1007; 662 } 663 664 void 665 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 666 { 667 ihandle_t mmui; 668 phandle_t chosen, mmu; 669 int sz; 670 int i, j; 671 int ofw_mappings; 672 uint32_t trace[2]; 673 vm_size_t size, physsz, hwphyssz; 674 vm_offset_t pa, va, off; 675 676 /* 677 * Set up BAT0 to map the lowest 256 MB area 678 */ 679 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 680 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 681 682 /* 683 * Map PCI memory space. 684 */ 685 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 686 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 687 688 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 689 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 690 691 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 692 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 693 694 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 695 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 696 697 /* 698 * Map obio devices. 699 */ 700 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 701 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 702 703 /* 704 * Use an IBAT and a DBAT to map the bottom segment of memory 705 * where we are. 706 */ 707 __asm (".balign 32; \n" 708 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 709 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 710 :: "r"(battable[0].batu), "r"(battable[0].batl)); 711 712 /* map pci space */ 713 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 714 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 715 isync(); 716 717 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 718 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 719 720 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 721 for (i = 0; i < pregions_sz; i++) { 722 vm_offset_t pa; 723 vm_offset_t end; 724 725 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 726 pregions[i].mr_start, 727 pregions[i].mr_start + pregions[i].mr_size, 728 pregions[i].mr_size); 729 /* 730 * Install entries into the BAT table to allow all 731 * of physmem to be convered by on-demand BAT entries. 732 * The loop will sometimes set the same battable element 733 * twice, but that's fine since they won't be used for 734 * a while yet. 735 */ 736 pa = pregions[i].mr_start & 0xf0000000; 737 end = pregions[i].mr_start + pregions[i].mr_size; 738 do { 739 u_int n = pa >> ADDR_SR_SHFT; 740 741 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 742 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 743 pa += SEGMENT_LENGTH; 744 } while (pa < end); 745 } 746 747 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 748 panic("moea_bootstrap: phys_avail too small"); 749 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 750 phys_avail_count = 0; 751 physsz = 0; 752 hwphyssz = 0; 753 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 754 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 755 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 756 regions[i].mr_start + regions[i].mr_size, 757 regions[i].mr_size); 758 if (hwphyssz != 0 && 759 (physsz + regions[i].mr_size) >= hwphyssz) { 760 if (physsz < hwphyssz) { 761 phys_avail[j] = regions[i].mr_start; 762 phys_avail[j + 1] = regions[i].mr_start + 763 hwphyssz - physsz; 764 physsz = hwphyssz; 765 phys_avail_count++; 766 } 767 break; 768 } 769 phys_avail[j] = regions[i].mr_start; 770 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 771 phys_avail_count++; 772 physsz += regions[i].mr_size; 773 } 774 physmem = btoc(physsz); 775 776 /* 777 * Allocate PTEG table. 778 */ 779 #ifdef PTEGCOUNT 780 moea_pteg_count = PTEGCOUNT; 781 #else 782 moea_pteg_count = 0x1000; 783 784 while (moea_pteg_count < physmem) 785 moea_pteg_count <<= 1; 786 787 moea_pteg_count >>= 1; 788 #endif /* PTEGCOUNT */ 789 790 size = moea_pteg_count * sizeof(struct pteg); 791 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 792 size); 793 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 794 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 795 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 796 moea_pteg_mask = moea_pteg_count - 1; 797 798 /* 799 * Allocate pv/overflow lists. 800 */ 801 size = sizeof(struct pvo_head) * moea_pteg_count; 802 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 803 PAGE_SIZE); 804 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 805 for (i = 0; i < moea_pteg_count; i++) 806 LIST_INIT(&moea_pvo_table[i]); 807 808 /* 809 * Initialize the lock that synchronizes access to the pteg and pvo 810 * tables. 811 */ 812 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 813 MTX_RECURSE); 814 815 /* 816 * Initialise the unmanaged pvo pool. 817 */ 818 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 819 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 820 moea_bpvo_pool_index = 0; 821 822 /* 823 * Make sure kernel vsid is allocated as well as VSID 0. 824 */ 825 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 826 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 827 moea_vsid_bitmap[0] |= 1; 828 829 /* 830 * Set up the Open Firmware pmap and add it's mappings. 831 */ 832 moea_pinit(mmup, &ofw_pmap); 833 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 834 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 835 if ((chosen = OF_finddevice("/chosen")) == -1) 836 panic("moea_bootstrap: can't find /chosen"); 837 OF_getprop(chosen, "mmu", &mmui, 4); 838 if ((mmu = OF_instance_to_package(mmui)) == -1) 839 panic("moea_bootstrap: can't get mmu package"); 840 if ((sz = OF_getproplen(mmu, "translations")) == -1) 841 panic("moea_bootstrap: can't get ofw translation count"); 842 translations = NULL; 843 for (i = 0; phys_avail[i] != 0; i += 2) { 844 if (phys_avail[i + 1] >= sz) { 845 translations = (struct ofw_map *)phys_avail[i]; 846 break; 847 } 848 } 849 if (translations == NULL) 850 panic("moea_bootstrap: no space to copy translations"); 851 bzero(translations, sz); 852 if (OF_getprop(mmu, "translations", translations, sz) == -1) 853 panic("moea_bootstrap: can't get ofw translations"); 854 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 855 sz /= sizeof(*translations); 856 qsort(translations, sz, sizeof (*translations), om_cmp); 857 for (i = 0, ofw_mappings = 0; i < sz; i++) { 858 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 859 translations[i].om_pa, translations[i].om_va, 860 translations[i].om_len); 861 862 /* 863 * If the mapping is 1:1, let the RAM and device on-demand 864 * BAT tables take care of the translation. 865 */ 866 if (translations[i].om_va == translations[i].om_pa) 867 continue; 868 869 /* Enter the pages */ 870 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 871 struct vm_page m; 872 873 m.phys_addr = translations[i].om_pa + off; 874 PMAP_LOCK(&ofw_pmap); 875 moea_enter_locked(&ofw_pmap, 876 translations[i].om_va + off, &m, 877 VM_PROT_ALL, 1); 878 PMAP_UNLOCK(&ofw_pmap); 879 ofw_mappings++; 880 } 881 } 882 883 /* 884 * Calculate the last available physical address. 885 */ 886 for (i = 0; phys_avail[i + 2] != 0; i += 2) 887 ; 888 Maxmem = powerpc_btop(phys_avail[i + 1]); 889 890 /* 891 * Initialize the kernel pmap (which is statically allocated). 892 */ 893 PMAP_LOCK_INIT(kernel_pmap); 894 for (i = 0; i < 16; i++) { 895 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 896 } 897 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 898 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 899 kernel_pmap->pm_active = ~0; 900 901 pmap_cpu_bootstrap(trace, 0); 902 903 pmap_bootstrapped++; 904 905 /* 906 * Set the start and end of kva. 907 */ 908 virtual_avail = VM_MIN_KERNEL_ADDRESS; 909 virtual_end = VM_MAX_KERNEL_ADDRESS; 910 911 /* 912 * Allocate a kernel stack with a guard page for thread0 and map it 913 * into the kernel page map. 914 */ 915 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 916 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 917 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 918 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 919 thread0.td_kstack = va; 920 thread0.td_kstack_pages = KSTACK_PAGES; 921 for (i = 0; i < KSTACK_PAGES; i++) { 922 moea_kenter(mmup, va, pa);; 923 pa += PAGE_SIZE; 924 va += PAGE_SIZE; 925 } 926 927 /* 928 * Allocate virtual address space for the message buffer. 929 */ 930 pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 931 msgbufp = (struct msgbuf *)virtual_avail; 932 va = virtual_avail; 933 virtual_avail += round_page(MSGBUF_SIZE); 934 while (va < virtual_avail) { 935 moea_kenter(mmup, va, pa);; 936 pa += PAGE_SIZE; 937 va += PAGE_SIZE; 938 } 939 } 940 941 /* 942 * Activate a user pmap. The pmap must be activated before it's address 943 * space can be accessed in any way. 944 */ 945 void 946 moea_activate(mmu_t mmu, struct thread *td) 947 { 948 pmap_t pm, pmr; 949 950 /* 951 * Load all the data we need up front to encourage the compiler to 952 * not issue any loads while we have interrupts disabled below. 953 */ 954 pm = &td->td_proc->p_vmspace->vm_pmap; 955 956 if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL) 957 pmr = pm; 958 959 pm->pm_active |= PCPU_GET(cpumask); 960 PCPU_SET(curpmap, pmr); 961 } 962 963 void 964 moea_deactivate(mmu_t mmu, struct thread *td) 965 { 966 pmap_t pm; 967 968 pm = &td->td_proc->p_vmspace->vm_pmap; 969 pm->pm_active &= ~(PCPU_GET(cpumask)); 970 PCPU_SET(curpmap, NULL); 971 } 972 973 void 974 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 975 { 976 struct pvo_entry *pvo; 977 978 PMAP_LOCK(pm); 979 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 980 981 if (pvo != NULL) { 982 if (wired) { 983 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 984 pm->pm_stats.wired_count++; 985 pvo->pvo_vaddr |= PVO_WIRED; 986 } else { 987 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 988 pm->pm_stats.wired_count--; 989 pvo->pvo_vaddr &= ~PVO_WIRED; 990 } 991 } 992 PMAP_UNLOCK(pm); 993 } 994 995 void 996 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 997 { 998 vm_offset_t dst; 999 vm_offset_t src; 1000 1001 dst = VM_PAGE_TO_PHYS(mdst); 1002 src = VM_PAGE_TO_PHYS(msrc); 1003 1004 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1005 } 1006 1007 /* 1008 * Zero a page of physical memory by temporarily mapping it into the tlb. 1009 */ 1010 void 1011 moea_zero_page(mmu_t mmu, vm_page_t m) 1012 { 1013 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1014 void *va = (void *)pa; 1015 1016 bzero(va, PAGE_SIZE); 1017 } 1018 1019 void 1020 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1021 { 1022 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1023 void *va = (void *)(pa + off); 1024 1025 bzero(va, size); 1026 } 1027 1028 void 1029 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1030 { 1031 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1032 void *va = (void *)pa; 1033 1034 bzero(va, PAGE_SIZE); 1035 } 1036 1037 /* 1038 * Map the given physical page at the specified virtual address in the 1039 * target pmap with the protection requested. If specified the page 1040 * will be wired down. 1041 */ 1042 void 1043 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1044 boolean_t wired) 1045 { 1046 1047 vm_page_lock_queues(); 1048 PMAP_LOCK(pmap); 1049 moea_enter_locked(pmap, va, m, prot, wired); 1050 vm_page_unlock_queues(); 1051 PMAP_UNLOCK(pmap); 1052 } 1053 1054 /* 1055 * Map the given physical page at the specified virtual address in the 1056 * target pmap with the protection requested. If specified the page 1057 * will be wired down. 1058 * 1059 * The page queues and pmap must be locked. 1060 */ 1061 static void 1062 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1063 boolean_t wired) 1064 { 1065 struct pvo_head *pvo_head; 1066 uma_zone_t zone; 1067 vm_page_t pg; 1068 u_int pte_lo, pvo_flags, was_exec, i; 1069 int error; 1070 1071 if (!moea_initialized) { 1072 pvo_head = &moea_pvo_kunmanaged; 1073 zone = moea_upvo_zone; 1074 pvo_flags = 0; 1075 pg = NULL; 1076 was_exec = PTE_EXEC; 1077 } else { 1078 pvo_head = vm_page_to_pvoh(m); 1079 pg = m; 1080 zone = moea_mpvo_zone; 1081 pvo_flags = PVO_MANAGED; 1082 was_exec = 0; 1083 } 1084 if (pmap_bootstrapped) 1085 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1086 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1087 1088 /* XXX change the pvo head for fake pages */ 1089 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) 1090 pvo_head = &moea_pvo_kunmanaged; 1091 1092 /* 1093 * If this is a managed page, and it's the first reference to the page, 1094 * clear the execness of the page. Otherwise fetch the execness. 1095 */ 1096 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1097 if (LIST_EMPTY(pvo_head)) { 1098 moea_attr_clear(pg, PTE_EXEC); 1099 } else { 1100 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1101 } 1102 } 1103 1104 /* 1105 * Assume the page is cache inhibited and access is guarded unless 1106 * it's in our available memory array. 1107 */ 1108 pte_lo = PTE_I | PTE_G; 1109 for (i = 0; i < pregions_sz; i++) { 1110 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1111 (VM_PAGE_TO_PHYS(m) < 1112 (pregions[i].mr_start + pregions[i].mr_size))) { 1113 pte_lo &= ~(PTE_I | PTE_G); 1114 break; 1115 } 1116 } 1117 1118 if (prot & VM_PROT_WRITE) { 1119 pte_lo |= PTE_BW; 1120 if (pmap_bootstrapped) 1121 vm_page_flag_set(m, PG_WRITEABLE); 1122 } else 1123 pte_lo |= PTE_BR; 1124 1125 if (prot & VM_PROT_EXECUTE) 1126 pvo_flags |= PVO_EXECUTABLE; 1127 1128 if (wired) 1129 pvo_flags |= PVO_WIRED; 1130 1131 if ((m->flags & PG_FICTITIOUS) != 0) 1132 pvo_flags |= PVO_FAKE; 1133 1134 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1135 pte_lo, pvo_flags); 1136 1137 /* 1138 * Flush the real page from the instruction cache if this page is 1139 * mapped executable and cacheable and was not previously mapped (or 1140 * was not mapped executable). 1141 */ 1142 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1143 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1144 /* 1145 * Flush the real memory from the cache. 1146 */ 1147 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1148 if (pg != NULL) 1149 moea_attr_save(pg, PTE_EXEC); 1150 } 1151 1152 /* XXX syncicache always until problems are sorted */ 1153 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1154 } 1155 1156 /* 1157 * Maps a sequence of resident pages belonging to the same object. 1158 * The sequence begins with the given page m_start. This page is 1159 * mapped at the given virtual address start. Each subsequent page is 1160 * mapped at a virtual address that is offset from start by the same 1161 * amount as the page is offset from m_start within the object. The 1162 * last page in the sequence is the page with the largest offset from 1163 * m_start that can be mapped at a virtual address less than the given 1164 * virtual address end. Not every virtual page between start and end 1165 * is mapped; only those for which a resident page exists with the 1166 * corresponding offset from m_start are mapped. 1167 */ 1168 void 1169 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1170 vm_page_t m_start, vm_prot_t prot) 1171 { 1172 vm_page_t m; 1173 vm_pindex_t diff, psize; 1174 1175 psize = atop(end - start); 1176 m = m_start; 1177 PMAP_LOCK(pm); 1178 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1179 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1180 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1181 m = TAILQ_NEXT(m, listq); 1182 } 1183 PMAP_UNLOCK(pm); 1184 } 1185 1186 void 1187 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1188 vm_prot_t prot) 1189 { 1190 1191 PMAP_LOCK(pm); 1192 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1193 FALSE); 1194 PMAP_UNLOCK(pm); 1195 1196 } 1197 1198 vm_paddr_t 1199 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1200 { 1201 struct pvo_entry *pvo; 1202 vm_paddr_t pa; 1203 1204 PMAP_LOCK(pm); 1205 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1206 if (pvo == NULL) 1207 pa = 0; 1208 else 1209 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1210 PMAP_UNLOCK(pm); 1211 return (pa); 1212 } 1213 1214 /* 1215 * Atomically extract and hold the physical page with the given 1216 * pmap and virtual address pair if that mapping permits the given 1217 * protection. 1218 */ 1219 vm_page_t 1220 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1221 { 1222 struct pvo_entry *pvo; 1223 vm_page_t m; 1224 1225 m = NULL; 1226 vm_page_lock_queues(); 1227 PMAP_LOCK(pmap); 1228 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1229 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) && 1230 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW || 1231 (prot & VM_PROT_WRITE) == 0)) { 1232 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1233 vm_page_hold(m); 1234 } 1235 vm_page_unlock_queues(); 1236 PMAP_UNLOCK(pmap); 1237 return (m); 1238 } 1239 1240 void 1241 moea_init(mmu_t mmu) 1242 { 1243 1244 CTR0(KTR_PMAP, "moea_init"); 1245 1246 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1247 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1248 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1249 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1250 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1251 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1252 moea_initialized = TRUE; 1253 } 1254 1255 boolean_t 1256 moea_is_modified(mmu_t mmu, vm_page_t m) 1257 { 1258 1259 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1260 return (FALSE); 1261 1262 return (moea_query_bit(m, PTE_CHG)); 1263 } 1264 1265 void 1266 moea_clear_reference(mmu_t mmu, vm_page_t m) 1267 { 1268 1269 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1270 return; 1271 moea_clear_bit(m, PTE_REF, NULL); 1272 } 1273 1274 void 1275 moea_clear_modify(mmu_t mmu, vm_page_t m) 1276 { 1277 1278 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1279 return; 1280 moea_clear_bit(m, PTE_CHG, NULL); 1281 } 1282 1283 /* 1284 * Clear the write and modified bits in each of the given page's mappings. 1285 */ 1286 void 1287 moea_remove_write(mmu_t mmu, vm_page_t m) 1288 { 1289 struct pvo_entry *pvo; 1290 struct pte *pt; 1291 pmap_t pmap; 1292 u_int lo; 1293 1294 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1295 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1296 (m->flags & PG_WRITEABLE) == 0) 1297 return; 1298 lo = moea_attr_fetch(m); 1299 SYNC(); 1300 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1301 pmap = pvo->pvo_pmap; 1302 PMAP_LOCK(pmap); 1303 if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) { 1304 pt = moea_pvo_to_pte(pvo, -1); 1305 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1306 pvo->pvo_pte.pte_lo |= PTE_BR; 1307 if (pt != NULL) { 1308 moea_pte_synch(pt, &pvo->pvo_pte); 1309 lo |= pvo->pvo_pte.pte_lo; 1310 pvo->pvo_pte.pte_lo &= ~PTE_CHG; 1311 moea_pte_change(pt, &pvo->pvo_pte, 1312 pvo->pvo_vaddr); 1313 mtx_unlock(&moea_table_mutex); 1314 } 1315 } 1316 PMAP_UNLOCK(pmap); 1317 } 1318 if ((lo & PTE_CHG) != 0) { 1319 moea_attr_clear(m, PTE_CHG); 1320 vm_page_dirty(m); 1321 } 1322 vm_page_flag_clear(m, PG_WRITEABLE); 1323 } 1324 1325 /* 1326 * moea_ts_referenced: 1327 * 1328 * Return a count of reference bits for a page, clearing those bits. 1329 * It is not necessary for every reference bit to be cleared, but it 1330 * is necessary that 0 only be returned when there are truly no 1331 * reference bits set. 1332 * 1333 * XXX: The exact number of bits to check and clear is a matter that 1334 * should be tested and standardized at some point in the future for 1335 * optimal aging of shared pages. 1336 */ 1337 boolean_t 1338 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1339 { 1340 int count; 1341 1342 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1343 return (0); 1344 1345 count = moea_clear_bit(m, PTE_REF, NULL); 1346 1347 return (count); 1348 } 1349 1350 /* 1351 * Map a wired page into kernel virtual address space. 1352 */ 1353 void 1354 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1355 { 1356 u_int pte_lo; 1357 int error; 1358 int i; 1359 1360 #if 0 1361 if (va < VM_MIN_KERNEL_ADDRESS) 1362 panic("moea_kenter: attempt to enter non-kernel address %#x", 1363 va); 1364 #endif 1365 1366 pte_lo = PTE_I | PTE_G; 1367 for (i = 0; i < pregions_sz; i++) { 1368 if ((pa >= pregions[i].mr_start) && 1369 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1370 pte_lo &= ~(PTE_I | PTE_G); 1371 break; 1372 } 1373 } 1374 1375 PMAP_LOCK(kernel_pmap); 1376 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1377 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1378 1379 if (error != 0 && error != ENOENT) 1380 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1381 pa, error); 1382 1383 /* 1384 * Flush the real memory from the instruction cache. 1385 */ 1386 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1387 moea_syncicache(pa, PAGE_SIZE); 1388 } 1389 PMAP_UNLOCK(kernel_pmap); 1390 } 1391 1392 /* 1393 * Extract the physical page address associated with the given kernel virtual 1394 * address. 1395 */ 1396 vm_offset_t 1397 moea_kextract(mmu_t mmu, vm_offset_t va) 1398 { 1399 struct pvo_entry *pvo; 1400 vm_paddr_t pa; 1401 1402 #ifdef UMA_MD_SMALL_ALLOC 1403 /* 1404 * Allow direct mappings 1405 */ 1406 if (va < VM_MIN_KERNEL_ADDRESS) { 1407 return (va); 1408 } 1409 #endif 1410 1411 PMAP_LOCK(kernel_pmap); 1412 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1413 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1414 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1415 PMAP_UNLOCK(kernel_pmap); 1416 return (pa); 1417 } 1418 1419 /* 1420 * Remove a wired page from kernel virtual address space. 1421 */ 1422 void 1423 moea_kremove(mmu_t mmu, vm_offset_t va) 1424 { 1425 1426 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1427 } 1428 1429 /* 1430 * Map a range of physical addresses into kernel virtual address space. 1431 * 1432 * The value passed in *virt is a suggested virtual address for the mapping. 1433 * Architectures which can support a direct-mapped physical to virtual region 1434 * can return the appropriate address within that region, leaving '*virt' 1435 * unchanged. We cannot and therefore do not; *virt is updated with the 1436 * first usable address after the mapped region. 1437 */ 1438 vm_offset_t 1439 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1440 vm_offset_t pa_end, int prot) 1441 { 1442 vm_offset_t sva, va; 1443 1444 sva = *virt; 1445 va = sva; 1446 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1447 moea_kenter(mmu, va, pa_start); 1448 *virt = va; 1449 return (sva); 1450 } 1451 1452 /* 1453 * Returns true if the pmap's pv is one of the first 1454 * 16 pvs linked to from this page. This count may 1455 * be changed upwards or downwards in the future; it 1456 * is only necessary that true be returned for a small 1457 * subset of pmaps for proper page aging. 1458 */ 1459 boolean_t 1460 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1461 { 1462 int loops; 1463 struct pvo_entry *pvo; 1464 1465 if (!moea_initialized || (m->flags & PG_FICTITIOUS)) 1466 return FALSE; 1467 1468 loops = 0; 1469 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1470 if (pvo->pvo_pmap == pmap) 1471 return (TRUE); 1472 if (++loops >= 16) 1473 break; 1474 } 1475 1476 return (FALSE); 1477 } 1478 1479 /* 1480 * Return the number of managed mappings to the given physical page 1481 * that are wired. 1482 */ 1483 int 1484 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1485 { 1486 struct pvo_entry *pvo; 1487 int count; 1488 1489 count = 0; 1490 if (!moea_initialized || (m->flags & PG_FICTITIOUS) != 0) 1491 return (count); 1492 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1493 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1494 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1495 count++; 1496 return (count); 1497 } 1498 1499 static u_int moea_vsidcontext; 1500 1501 void 1502 moea_pinit(mmu_t mmu, pmap_t pmap) 1503 { 1504 int i, mask; 1505 u_int entropy; 1506 1507 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1508 PMAP_LOCK_INIT(pmap); 1509 1510 entropy = 0; 1511 __asm __volatile("mftb %0" : "=r"(entropy)); 1512 1513 /* 1514 * Allocate some segment registers for this pmap. 1515 */ 1516 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1517 u_int hash, n; 1518 1519 /* 1520 * Create a new value by mutiplying by a prime and adding in 1521 * entropy from the timebase register. This is to make the 1522 * VSID more random so that the PT hash function collides 1523 * less often. (Note that the prime casues gcc to do shifts 1524 * instead of a multiply.) 1525 */ 1526 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1527 hash = moea_vsidcontext & (NPMAPS - 1); 1528 if (hash == 0) /* 0 is special, avoid it */ 1529 continue; 1530 n = hash >> 5; 1531 mask = 1 << (hash & (VSID_NBPW - 1)); 1532 hash = (moea_vsidcontext & 0xfffff); 1533 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1534 /* anything free in this bucket? */ 1535 if (moea_vsid_bitmap[n] == 0xffffffff) { 1536 entropy = (moea_vsidcontext >> 20); 1537 continue; 1538 } 1539 i = ffs(~moea_vsid_bitmap[i]) - 1; 1540 mask = 1 << i; 1541 hash &= 0xfffff & ~(VSID_NBPW - 1); 1542 hash |= i; 1543 } 1544 moea_vsid_bitmap[n] |= mask; 1545 for (i = 0; i < 16; i++) 1546 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1547 return; 1548 } 1549 1550 panic("moea_pinit: out of segments"); 1551 } 1552 1553 /* 1554 * Initialize the pmap associated with process 0. 1555 */ 1556 void 1557 moea_pinit0(mmu_t mmu, pmap_t pm) 1558 { 1559 1560 moea_pinit(mmu, pm); 1561 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1562 } 1563 1564 /* 1565 * Set the physical protection on the specified range of this map as requested. 1566 */ 1567 void 1568 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1569 vm_prot_t prot) 1570 { 1571 struct pvo_entry *pvo; 1572 struct pte *pt; 1573 int pteidx; 1574 1575 CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1576 eva, prot); 1577 1578 1579 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1580 ("moea_protect: non current pmap")); 1581 1582 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1583 moea_remove(mmu, pm, sva, eva); 1584 return; 1585 } 1586 1587 vm_page_lock_queues(); 1588 PMAP_LOCK(pm); 1589 for (; sva < eva; sva += PAGE_SIZE) { 1590 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1591 if (pvo == NULL) 1592 continue; 1593 1594 if ((prot & VM_PROT_EXECUTE) == 0) 1595 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1596 1597 /* 1598 * Grab the PTE pointer before we diddle with the cached PTE 1599 * copy. 1600 */ 1601 pt = moea_pvo_to_pte(pvo, pteidx); 1602 /* 1603 * Change the protection of the page. 1604 */ 1605 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1606 pvo->pvo_pte.pte_lo |= PTE_BR; 1607 1608 /* 1609 * If the PVO is in the page table, update that pte as well. 1610 */ 1611 if (pt != NULL) { 1612 moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1613 mtx_unlock(&moea_table_mutex); 1614 } 1615 } 1616 vm_page_unlock_queues(); 1617 PMAP_UNLOCK(pm); 1618 } 1619 1620 /* 1621 * Map a list of wired pages into kernel virtual address space. This is 1622 * intended for temporary mappings which do not need page modification or 1623 * references recorded. Existing mappings in the region are overwritten. 1624 */ 1625 void 1626 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1627 { 1628 vm_offset_t va; 1629 1630 va = sva; 1631 while (count-- > 0) { 1632 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1633 va += PAGE_SIZE; 1634 m++; 1635 } 1636 } 1637 1638 /* 1639 * Remove page mappings from kernel virtual address space. Intended for 1640 * temporary mappings entered by moea_qenter. 1641 */ 1642 void 1643 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1644 { 1645 vm_offset_t va; 1646 1647 va = sva; 1648 while (count-- > 0) { 1649 moea_kremove(mmu, va); 1650 va += PAGE_SIZE; 1651 } 1652 } 1653 1654 void 1655 moea_release(mmu_t mmu, pmap_t pmap) 1656 { 1657 int idx, mask; 1658 1659 /* 1660 * Free segment register's VSID 1661 */ 1662 if (pmap->pm_sr[0] == 0) 1663 panic("moea_release"); 1664 1665 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1666 mask = 1 << (idx % VSID_NBPW); 1667 idx /= VSID_NBPW; 1668 moea_vsid_bitmap[idx] &= ~mask; 1669 PMAP_LOCK_DESTROY(pmap); 1670 } 1671 1672 /* 1673 * Remove the given range of addresses from the specified map. 1674 */ 1675 void 1676 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1677 { 1678 struct pvo_entry *pvo; 1679 int pteidx; 1680 1681 vm_page_lock_queues(); 1682 PMAP_LOCK(pm); 1683 for (; sva < eva; sva += PAGE_SIZE) { 1684 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1685 if (pvo != NULL) { 1686 moea_pvo_remove(pvo, pteidx); 1687 } 1688 } 1689 PMAP_UNLOCK(pm); 1690 vm_page_unlock_queues(); 1691 } 1692 1693 /* 1694 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1695 * will reflect changes in pte's back to the vm_page. 1696 */ 1697 void 1698 moea_remove_all(mmu_t mmu, vm_page_t m) 1699 { 1700 struct pvo_head *pvo_head; 1701 struct pvo_entry *pvo, *next_pvo; 1702 pmap_t pmap; 1703 1704 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1705 1706 pvo_head = vm_page_to_pvoh(m); 1707 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1708 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1709 1710 MOEA_PVO_CHECK(pvo); /* sanity check */ 1711 pmap = pvo->pvo_pmap; 1712 PMAP_LOCK(pmap); 1713 moea_pvo_remove(pvo, -1); 1714 PMAP_UNLOCK(pmap); 1715 } 1716 vm_page_flag_clear(m, PG_WRITEABLE); 1717 } 1718 1719 /* 1720 * Allocate a physical page of memory directly from the phys_avail map. 1721 * Can only be called from moea_bootstrap before avail start and end are 1722 * calculated. 1723 */ 1724 static vm_offset_t 1725 moea_bootstrap_alloc(vm_size_t size, u_int align) 1726 { 1727 vm_offset_t s, e; 1728 int i, j; 1729 1730 size = round_page(size); 1731 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1732 if (align != 0) 1733 s = (phys_avail[i] + align - 1) & ~(align - 1); 1734 else 1735 s = phys_avail[i]; 1736 e = s + size; 1737 1738 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1739 continue; 1740 1741 if (s == phys_avail[i]) { 1742 phys_avail[i] += size; 1743 } else if (e == phys_avail[i + 1]) { 1744 phys_avail[i + 1] -= size; 1745 } else { 1746 for (j = phys_avail_count * 2; j > i; j -= 2) { 1747 phys_avail[j] = phys_avail[j - 2]; 1748 phys_avail[j + 1] = phys_avail[j - 1]; 1749 } 1750 1751 phys_avail[i + 3] = phys_avail[i + 1]; 1752 phys_avail[i + 1] = s; 1753 phys_avail[i + 2] = e; 1754 phys_avail_count++; 1755 } 1756 1757 return (s); 1758 } 1759 panic("moea_bootstrap_alloc: could not allocate memory"); 1760 } 1761 1762 static void 1763 moea_syncicache(vm_offset_t pa, vm_size_t len) 1764 { 1765 __syncicache((void *)pa, len); 1766 } 1767 1768 static void 1769 tlbia(void) 1770 { 1771 caddr_t i; 1772 1773 SYNC(); 1774 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1775 TLBIE(i); 1776 EIEIO(); 1777 } 1778 TLBSYNC(); 1779 SYNC(); 1780 } 1781 1782 static int 1783 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1784 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1785 { 1786 struct pvo_entry *pvo; 1787 u_int sr; 1788 int first; 1789 u_int ptegidx; 1790 int i; 1791 int bootstrap; 1792 1793 moea_pvo_enter_calls++; 1794 first = 0; 1795 bootstrap = 0; 1796 1797 /* 1798 * Compute the PTE Group index. 1799 */ 1800 va &= ~ADDR_POFF; 1801 sr = va_to_sr(pm->pm_sr, va); 1802 ptegidx = va_to_pteg(sr, va); 1803 1804 /* 1805 * Remove any existing mapping for this page. Reuse the pvo entry if 1806 * there is a mapping. 1807 */ 1808 mtx_lock(&moea_table_mutex); 1809 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1810 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1811 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1812 (pvo->pvo_pte.pte_lo & PTE_PP) == 1813 (pte_lo & PTE_PP)) { 1814 mtx_unlock(&moea_table_mutex); 1815 return (0); 1816 } 1817 moea_pvo_remove(pvo, -1); 1818 break; 1819 } 1820 } 1821 1822 /* 1823 * If we aren't overwriting a mapping, try to allocate. 1824 */ 1825 if (moea_initialized) { 1826 pvo = uma_zalloc(zone, M_NOWAIT); 1827 } else { 1828 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1829 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1830 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1831 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1832 } 1833 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1834 moea_bpvo_pool_index++; 1835 bootstrap = 1; 1836 } 1837 1838 if (pvo == NULL) { 1839 mtx_unlock(&moea_table_mutex); 1840 return (ENOMEM); 1841 } 1842 1843 moea_pvo_entries++; 1844 pvo->pvo_vaddr = va; 1845 pvo->pvo_pmap = pm; 1846 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1847 pvo->pvo_vaddr &= ~ADDR_POFF; 1848 if (flags & VM_PROT_EXECUTE) 1849 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1850 if (flags & PVO_WIRED) 1851 pvo->pvo_vaddr |= PVO_WIRED; 1852 if (pvo_head != &moea_pvo_kunmanaged) 1853 pvo->pvo_vaddr |= PVO_MANAGED; 1854 if (bootstrap) 1855 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1856 if (flags & PVO_FAKE) 1857 pvo->pvo_vaddr |= PVO_FAKE; 1858 1859 moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1860 1861 /* 1862 * Remember if the list was empty and therefore will be the first 1863 * item. 1864 */ 1865 if (LIST_FIRST(pvo_head) == NULL) 1866 first = 1; 1867 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1868 1869 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1870 pm->pm_stats.wired_count++; 1871 pm->pm_stats.resident_count++; 1872 1873 /* 1874 * We hope this succeeds but it isn't required. 1875 */ 1876 i = moea_pte_insert(ptegidx, &pvo->pvo_pte); 1877 if (i >= 0) { 1878 PVO_PTEGIDX_SET(pvo, i); 1879 } else { 1880 panic("moea_pvo_enter: overflow"); 1881 moea_pte_overflow++; 1882 } 1883 mtx_unlock(&moea_table_mutex); 1884 1885 return (first ? ENOENT : 0); 1886 } 1887 1888 static void 1889 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1890 { 1891 struct pte *pt; 1892 1893 /* 1894 * If there is an active pte entry, we need to deactivate it (and 1895 * save the ref & cfg bits). 1896 */ 1897 pt = moea_pvo_to_pte(pvo, pteidx); 1898 if (pt != NULL) { 1899 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1900 mtx_unlock(&moea_table_mutex); 1901 PVO_PTEGIDX_CLR(pvo); 1902 } else { 1903 moea_pte_overflow--; 1904 } 1905 1906 /* 1907 * Update our statistics. 1908 */ 1909 pvo->pvo_pmap->pm_stats.resident_count--; 1910 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1911 pvo->pvo_pmap->pm_stats.wired_count--; 1912 1913 /* 1914 * Save the REF/CHG bits into their cache if the page is managed. 1915 */ 1916 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 1917 struct vm_page *pg; 1918 1919 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1920 if (pg != NULL) { 1921 moea_attr_save(pg, pvo->pvo_pte.pte_lo & 1922 (PTE_REF | PTE_CHG)); 1923 } 1924 } 1925 1926 /* 1927 * Remove this PVO from the PV list. 1928 */ 1929 LIST_REMOVE(pvo, pvo_vlink); 1930 1931 /* 1932 * Remove this from the overflow list and return it to the pool 1933 * if we aren't going to reuse it. 1934 */ 1935 LIST_REMOVE(pvo, pvo_olink); 1936 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1937 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 1938 moea_upvo_zone, pvo); 1939 moea_pvo_entries--; 1940 moea_pvo_remove_calls++; 1941 } 1942 1943 static __inline int 1944 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1945 { 1946 int pteidx; 1947 1948 /* 1949 * We can find the actual pte entry without searching by grabbing 1950 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1951 * noticing the HID bit. 1952 */ 1953 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1954 if (pvo->pvo_pte.pte_hi & PTE_HID) 1955 pteidx ^= moea_pteg_mask * 8; 1956 1957 return (pteidx); 1958 } 1959 1960 static struct pvo_entry * 1961 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1962 { 1963 struct pvo_entry *pvo; 1964 int ptegidx; 1965 u_int sr; 1966 1967 va &= ~ADDR_POFF; 1968 sr = va_to_sr(pm->pm_sr, va); 1969 ptegidx = va_to_pteg(sr, va); 1970 1971 mtx_lock(&moea_table_mutex); 1972 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1973 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1974 if (pteidx_p) 1975 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 1976 break; 1977 } 1978 } 1979 mtx_unlock(&moea_table_mutex); 1980 1981 return (pvo); 1982 } 1983 1984 static struct pte * 1985 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 1986 { 1987 struct pte *pt; 1988 1989 /* 1990 * If we haven't been supplied the ptegidx, calculate it. 1991 */ 1992 if (pteidx == -1) { 1993 int ptegidx; 1994 u_int sr; 1995 1996 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 1997 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1998 pteidx = moea_pvo_pte_index(pvo, ptegidx); 1999 } 2000 2001 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2002 mtx_lock(&moea_table_mutex); 2003 2004 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2005 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2006 "valid pte index", pvo); 2007 } 2008 2009 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2010 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2011 "pvo but no valid pte", pvo); 2012 } 2013 2014 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2015 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 2016 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2017 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2018 } 2019 2020 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2021 != 0) { 2022 panic("moea_pvo_to_pte: pvo %p pte does not match " 2023 "pte %p in moea_pteg_table", pvo, pt); 2024 } 2025 2026 mtx_assert(&moea_table_mutex, MA_OWNED); 2027 return (pt); 2028 } 2029 2030 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2031 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2032 "moea_pteg_table but valid in pvo", pvo, pt); 2033 } 2034 2035 mtx_unlock(&moea_table_mutex); 2036 return (NULL); 2037 } 2038 2039 /* 2040 * XXX: THIS STUFF SHOULD BE IN pte.c? 2041 */ 2042 int 2043 moea_pte_spill(vm_offset_t addr) 2044 { 2045 struct pvo_entry *source_pvo, *victim_pvo; 2046 struct pvo_entry *pvo; 2047 int ptegidx, i, j; 2048 u_int sr; 2049 struct pteg *pteg; 2050 struct pte *pt; 2051 2052 moea_pte_spills++; 2053 2054 sr = mfsrin(addr); 2055 ptegidx = va_to_pteg(sr, addr); 2056 2057 /* 2058 * Have to substitute some entry. Use the primary hash for this. 2059 * Use low bits of timebase as random generator. 2060 */ 2061 pteg = &moea_pteg_table[ptegidx]; 2062 mtx_lock(&moea_table_mutex); 2063 __asm __volatile("mftb %0" : "=r"(i)); 2064 i &= 7; 2065 pt = &pteg->pt[i]; 2066 2067 source_pvo = NULL; 2068 victim_pvo = NULL; 2069 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2070 /* 2071 * We need to find a pvo entry for this address. 2072 */ 2073 MOEA_PVO_CHECK(pvo); 2074 if (source_pvo == NULL && 2075 moea_pte_match(&pvo->pvo_pte, sr, addr, 2076 pvo->pvo_pte.pte_hi & PTE_HID)) { 2077 /* 2078 * Now found an entry to be spilled into the pteg. 2079 * The PTE is now valid, so we know it's active. 2080 */ 2081 j = moea_pte_insert(ptegidx, &pvo->pvo_pte); 2082 2083 if (j >= 0) { 2084 PVO_PTEGIDX_SET(pvo, j); 2085 moea_pte_overflow--; 2086 MOEA_PVO_CHECK(pvo); 2087 mtx_unlock(&moea_table_mutex); 2088 return (1); 2089 } 2090 2091 source_pvo = pvo; 2092 2093 if (victim_pvo != NULL) 2094 break; 2095 } 2096 2097 /* 2098 * We also need the pvo entry of the victim we are replacing 2099 * so save the R & C bits of the PTE. 2100 */ 2101 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2102 moea_pte_compare(pt, &pvo->pvo_pte)) { 2103 victim_pvo = pvo; 2104 if (source_pvo != NULL) 2105 break; 2106 } 2107 } 2108 2109 if (source_pvo == NULL) { 2110 mtx_unlock(&moea_table_mutex); 2111 return (0); 2112 } 2113 2114 if (victim_pvo == NULL) { 2115 if ((pt->pte_hi & PTE_HID) == 0) 2116 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2117 "entry", pt); 2118 2119 /* 2120 * If this is a secondary PTE, we need to search it's primary 2121 * pvo bucket for the matching PVO. 2122 */ 2123 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2124 pvo_olink) { 2125 MOEA_PVO_CHECK(pvo); 2126 /* 2127 * We also need the pvo entry of the victim we are 2128 * replacing so save the R & C bits of the PTE. 2129 */ 2130 if (moea_pte_compare(pt, &pvo->pvo_pte)) { 2131 victim_pvo = pvo; 2132 break; 2133 } 2134 } 2135 2136 if (victim_pvo == NULL) 2137 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2138 "entry", pt); 2139 } 2140 2141 /* 2142 * We are invalidating the TLB entry for the EA we are replacing even 2143 * though it's valid. If we don't, we lose any ref/chg bit changes 2144 * contained in the TLB entry. 2145 */ 2146 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2147 2148 moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2149 moea_pte_set(pt, &source_pvo->pvo_pte); 2150 2151 PVO_PTEGIDX_CLR(victim_pvo); 2152 PVO_PTEGIDX_SET(source_pvo, i); 2153 moea_pte_replacements++; 2154 2155 MOEA_PVO_CHECK(victim_pvo); 2156 MOEA_PVO_CHECK(source_pvo); 2157 2158 mtx_unlock(&moea_table_mutex); 2159 return (1); 2160 } 2161 2162 static int 2163 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2164 { 2165 struct pte *pt; 2166 int i; 2167 2168 mtx_assert(&moea_table_mutex, MA_OWNED); 2169 2170 /* 2171 * First try primary hash. 2172 */ 2173 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2174 if ((pt->pte_hi & PTE_VALID) == 0) { 2175 pvo_pt->pte_hi &= ~PTE_HID; 2176 moea_pte_set(pt, pvo_pt); 2177 return (i); 2178 } 2179 } 2180 2181 /* 2182 * Now try secondary hash. 2183 */ 2184 ptegidx ^= moea_pteg_mask; 2185 2186 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2187 if ((pt->pte_hi & PTE_VALID) == 0) { 2188 pvo_pt->pte_hi |= PTE_HID; 2189 moea_pte_set(pt, pvo_pt); 2190 return (i); 2191 } 2192 } 2193 2194 panic("moea_pte_insert: overflow"); 2195 return (-1); 2196 } 2197 2198 static boolean_t 2199 moea_query_bit(vm_page_t m, int ptebit) 2200 { 2201 struct pvo_entry *pvo; 2202 struct pte *pt; 2203 2204 #if 0 2205 if (moea_attr_fetch(m) & ptebit) 2206 return (TRUE); 2207 #endif 2208 2209 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2210 MOEA_PVO_CHECK(pvo); /* sanity check */ 2211 2212 /* 2213 * See if we saved the bit off. If so, cache it and return 2214 * success. 2215 */ 2216 if (pvo->pvo_pte.pte_lo & ptebit) { 2217 moea_attr_save(m, ptebit); 2218 MOEA_PVO_CHECK(pvo); /* sanity check */ 2219 return (TRUE); 2220 } 2221 } 2222 2223 /* 2224 * No luck, now go through the hard part of looking at the PTEs 2225 * themselves. Sync so that any pending REF/CHG bits are flushed to 2226 * the PTEs. 2227 */ 2228 SYNC(); 2229 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2230 MOEA_PVO_CHECK(pvo); /* sanity check */ 2231 2232 /* 2233 * See if this pvo has a valid PTE. if so, fetch the 2234 * REF/CHG bits from the valid PTE. If the appropriate 2235 * ptebit is set, cache it and return success. 2236 */ 2237 pt = moea_pvo_to_pte(pvo, -1); 2238 if (pt != NULL) { 2239 moea_pte_synch(pt, &pvo->pvo_pte); 2240 mtx_unlock(&moea_table_mutex); 2241 if (pvo->pvo_pte.pte_lo & ptebit) { 2242 moea_attr_save(m, ptebit); 2243 MOEA_PVO_CHECK(pvo); /* sanity check */ 2244 return (TRUE); 2245 } 2246 } 2247 } 2248 2249 return (FALSE); 2250 } 2251 2252 static u_int 2253 moea_clear_bit(vm_page_t m, int ptebit, int *origbit) 2254 { 2255 u_int count; 2256 struct pvo_entry *pvo; 2257 struct pte *pt; 2258 int rv; 2259 2260 /* 2261 * Clear the cached value. 2262 */ 2263 rv = moea_attr_fetch(m); 2264 moea_attr_clear(m, ptebit); 2265 2266 /* 2267 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2268 * we can reset the right ones). note that since the pvo entries and 2269 * list heads are accessed via BAT0 and are never placed in the page 2270 * table, we don't have to worry about further accesses setting the 2271 * REF/CHG bits. 2272 */ 2273 SYNC(); 2274 2275 /* 2276 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2277 * valid pte clear the ptebit from the valid pte. 2278 */ 2279 count = 0; 2280 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2281 MOEA_PVO_CHECK(pvo); /* sanity check */ 2282 pt = moea_pvo_to_pte(pvo, -1); 2283 if (pt != NULL) { 2284 moea_pte_synch(pt, &pvo->pvo_pte); 2285 if (pvo->pvo_pte.pte_lo & ptebit) { 2286 count++; 2287 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2288 } 2289 mtx_unlock(&moea_table_mutex); 2290 } 2291 rv |= pvo->pvo_pte.pte_lo; 2292 pvo->pvo_pte.pte_lo &= ~ptebit; 2293 MOEA_PVO_CHECK(pvo); /* sanity check */ 2294 } 2295 2296 if (origbit != NULL) { 2297 *origbit = rv; 2298 } 2299 2300 return (count); 2301 } 2302 2303 /* 2304 * Return true if the physical range is encompassed by the battable[idx] 2305 */ 2306 static int 2307 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2308 { 2309 u_int prot; 2310 u_int32_t start; 2311 u_int32_t end; 2312 u_int32_t bat_ble; 2313 2314 /* 2315 * Return immediately if not a valid mapping 2316 */ 2317 if (!battable[idx].batu & BAT_Vs) 2318 return (EINVAL); 2319 2320 /* 2321 * The BAT entry must be cache-inhibited, guarded, and r/w 2322 * so it can function as an i/o page 2323 */ 2324 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2325 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2326 return (EPERM); 2327 2328 /* 2329 * The address should be within the BAT range. Assume that the 2330 * start address in the BAT has the correct alignment (thus 2331 * not requiring masking) 2332 */ 2333 start = battable[idx].batl & BAT_PBS; 2334 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2335 end = start | (bat_ble << 15) | 0x7fff; 2336 2337 if ((pa < start) || ((pa + size) > end)) 2338 return (ERANGE); 2339 2340 return (0); 2341 } 2342 2343 boolean_t 2344 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2345 { 2346 int i; 2347 2348 /* 2349 * This currently does not work for entries that 2350 * overlap 256M BAT segments. 2351 */ 2352 2353 for(i = 0; i < 16; i++) 2354 if (moea_bat_mapped(i, pa, size) == 0) 2355 return (0); 2356 2357 return (EFAULT); 2358 } 2359 2360 boolean_t 2361 moea_page_executable(mmu_t mmu, vm_page_t pg) 2362 { 2363 return ((moea_attr_fetch(pg) & PTE_EXEC) == PTE_EXEC); 2364 } 2365 2366 /* 2367 * Map a set of physical memory pages into the kernel virtual 2368 * address space. Return a pointer to where it is mapped. This 2369 * routine is intended to be used for mapping device memory, 2370 * NOT real memory. 2371 */ 2372 void * 2373 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2374 { 2375 vm_offset_t va, tmpva, ppa, offset; 2376 int i; 2377 2378 ppa = trunc_page(pa); 2379 offset = pa & PAGE_MASK; 2380 size = roundup(offset + size, PAGE_SIZE); 2381 2382 GIANT_REQUIRED; 2383 2384 /* 2385 * If the physical address lies within a valid BAT table entry, 2386 * return the 1:1 mapping. This currently doesn't work 2387 * for regions that overlap 256M BAT segments. 2388 */ 2389 for (i = 0; i < 16; i++) { 2390 if (moea_bat_mapped(i, pa, size) == 0) 2391 return ((void *) pa); 2392 } 2393 2394 va = kmem_alloc_nofault(kernel_map, size); 2395 if (!va) 2396 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2397 2398 for (tmpva = va; size > 0;) { 2399 moea_kenter(mmu, tmpva, ppa); 2400 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2401 size -= PAGE_SIZE; 2402 tmpva += PAGE_SIZE; 2403 ppa += PAGE_SIZE; 2404 } 2405 2406 return ((void *)(va + offset)); 2407 } 2408 2409 void 2410 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2411 { 2412 vm_offset_t base, offset; 2413 2414 /* 2415 * If this is outside kernel virtual space, then it's a 2416 * battable entry and doesn't require unmapping 2417 */ 2418 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2419 base = trunc_page(va); 2420 offset = va & PAGE_MASK; 2421 size = roundup(offset + size, PAGE_SIZE); 2422 kmem_free(kernel_map, base, size); 2423 } 2424 } 2425