xref: /freebsd/sys/powerpc/aim/mmu_oea.c (revision f0cfa1b168014f56c02b83e5f28412cc5f78d117)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause
3  *
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 /*-
32  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
33  * Copyright (C) 1995, 1996 TooLs GmbH.
34  * All rights reserved.
35  *
36  * Redistribution and use in source and binary forms, with or without
37  * modification, are permitted provided that the following conditions
38  * are met:
39  * 1. Redistributions of source code must retain the above copyright
40  *    notice, this list of conditions and the following disclaimer.
41  * 2. Redistributions in binary form must reproduce the above copyright
42  *    notice, this list of conditions and the following disclaimer in the
43  *    documentation and/or other materials provided with the distribution.
44  * 3. All advertising materials mentioning features or use of this software
45  *    must display the following acknowledgement:
46  *	This product includes software developed by TooLs GmbH.
47  * 4. The name of TooLs GmbH may not be used to endorse or promote products
48  *    derived from this software without specific prior written permission.
49  *
50  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
51  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
52  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
53  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
55  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
56  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
57  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
58  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
59  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60  *
61  * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62  */
63 /*-
64  * Copyright (C) 2001 Benno Rice.
65  * All rights reserved.
66  *
67  * Redistribution and use in source and binary forms, with or without
68  * modification, are permitted provided that the following conditions
69  * are met:
70  * 1. Redistributions of source code must retain the above copyright
71  *    notice, this list of conditions and the following disclaimer.
72  * 2. Redistributions in binary form must reproduce the above copyright
73  *    notice, this list of conditions and the following disclaimer in the
74  *    documentation and/or other materials provided with the distribution.
75  *
76  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
77  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
78  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
79  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
80  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
81  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
82  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
83  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
84  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
85  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86  */
87 
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
90 
91 /*
92  * Manages physical address maps.
93  *
94  * Since the information managed by this module is also stored by the
95  * logical address mapping module, this module may throw away valid virtual
96  * to physical mappings at almost any time.  However, invalidations of
97  * mappings must be done as requested.
98  *
99  * In order to cope with hardware architectures which make virtual to
100  * physical map invalidates expensive, this module may delay invalidate
101  * reduced protection operations until such time as they are actually
102  * necessary.  This module is given full information as to which processors
103  * are currently using which maps, and to when physical maps must be made
104  * correct.
105  */
106 
107 #include "opt_kstack_pages.h"
108 
109 #include <sys/param.h>
110 #include <sys/kernel.h>
111 #include <sys/conf.h>
112 #include <sys/queue.h>
113 #include <sys/cpuset.h>
114 #include <sys/kerneldump.h>
115 #include <sys/ktr.h>
116 #include <sys/lock.h>
117 #include <sys/msgbuf.h>
118 #include <sys/mutex.h>
119 #include <sys/proc.h>
120 #include <sys/rwlock.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
123 #include <sys/systm.h>
124 #include <sys/vmmeter.h>
125 
126 #include <dev/ofw/openfirm.h>
127 
128 #include <vm/vm.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
136 #include <vm/uma.h>
137 
138 #include <machine/cpu.h>
139 #include <machine/platform.h>
140 #include <machine/bat.h>
141 #include <machine/frame.h>
142 #include <machine/md_var.h>
143 #include <machine/psl.h>
144 #include <machine/pte.h>
145 #include <machine/smp.h>
146 #include <machine/sr.h>
147 #include <machine/mmuvar.h>
148 #include <machine/trap.h>
149 
150 #include "mmu_if.h"
151 
152 #define	MOEA_DEBUG
153 
154 #define TODO	panic("%s: not implemented", __func__);
155 
156 #define	VSID_MAKE(sr, hash)	((sr) | (((hash) & 0xfffff) << 4))
157 #define	VSID_TO_SR(vsid)	((vsid) & 0xf)
158 #define	VSID_TO_HASH(vsid)	(((vsid) >> 4) & 0xfffff)
159 
160 struct ofw_map {
161 	vm_offset_t	om_va;
162 	vm_size_t	om_len;
163 	vm_offset_t	om_pa;
164 	u_int		om_mode;
165 };
166 
167 extern unsigned char _etext[];
168 extern unsigned char _end[];
169 
170 /*
171  * Map of physical memory regions.
172  */
173 static struct	mem_region *regions;
174 static struct	mem_region *pregions;
175 static u_int    phys_avail_count;
176 static int	regions_sz, pregions_sz;
177 static struct	ofw_map *translations;
178 
179 /*
180  * Lock for the pteg and pvo tables.
181  */
182 struct mtx	moea_table_mutex;
183 struct mtx	moea_vsid_mutex;
184 
185 /* tlbie instruction synchronization */
186 static struct mtx tlbie_mtx;
187 
188 /*
189  * PTEG data.
190  */
191 static struct	pteg *moea_pteg_table;
192 u_int		moea_pteg_count;
193 u_int		moea_pteg_mask;
194 
195 /*
196  * PVO data.
197  */
198 struct	pvo_head *moea_pvo_table;		/* pvo entries by pteg index */
199 struct	pvo_head moea_pvo_kunmanaged =
200     LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged);	/* list of unmanaged pages */
201 
202 static struct rwlock_padalign pvh_global_lock;
203 
204 uma_zone_t	moea_upvo_zone;	/* zone for pvo entries for unmanaged pages */
205 uma_zone_t	moea_mpvo_zone;	/* zone for pvo entries for managed pages */
206 
207 #define	BPVO_POOL_SIZE	32768
208 static struct	pvo_entry *moea_bpvo_pool;
209 static int	moea_bpvo_pool_index = 0;
210 
211 #define	VSID_NBPW	(sizeof(u_int32_t) * 8)
212 static u_int	moea_vsid_bitmap[NPMAPS / VSID_NBPW];
213 
214 static boolean_t moea_initialized = FALSE;
215 
216 /*
217  * Statistics.
218  */
219 u_int	moea_pte_valid = 0;
220 u_int	moea_pte_overflow = 0;
221 u_int	moea_pte_replacements = 0;
222 u_int	moea_pvo_entries = 0;
223 u_int	moea_pvo_enter_calls = 0;
224 u_int	moea_pvo_remove_calls = 0;
225 u_int	moea_pte_spills = 0;
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
227     0, "");
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
229     &moea_pte_overflow, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
231     &moea_pte_replacements, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
233     0, "");
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
235     &moea_pvo_enter_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
237     &moea_pvo_remove_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
239     &moea_pte_spills, 0, "");
240 
241 /*
242  * Allocate physical memory for use in moea_bootstrap.
243  */
244 static vm_offset_t	moea_bootstrap_alloc(vm_size_t, u_int);
245 
246 /*
247  * PTE calls.
248  */
249 static int		moea_pte_insert(u_int, struct pte *);
250 
251 /*
252  * PVO calls.
253  */
254 static int	moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
255 		    vm_offset_t, vm_paddr_t, u_int, int);
256 static void	moea_pvo_remove(struct pvo_entry *, int);
257 static struct	pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
258 static struct	pte *moea_pvo_to_pte(const struct pvo_entry *, int);
259 
260 /*
261  * Utility routines.
262  */
263 static int		moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
264 			    vm_prot_t, u_int, int8_t);
265 static void		moea_syncicache(vm_paddr_t, vm_size_t);
266 static boolean_t	moea_query_bit(vm_page_t, int);
267 static u_int		moea_clear_bit(vm_page_t, int);
268 static void		moea_kremove(mmu_t, vm_offset_t);
269 int		moea_pte_spill(vm_offset_t);
270 
271 /*
272  * Kernel MMU interface
273  */
274 void moea_clear_modify(mmu_t, vm_page_t);
275 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
276 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
277     vm_page_t *mb, vm_offset_t b_offset, int xfersize);
278 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int,
279     int8_t);
280 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
281     vm_prot_t);
282 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
283 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
284 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
285 void moea_init(mmu_t);
286 boolean_t moea_is_modified(mmu_t, vm_page_t);
287 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
288 boolean_t moea_is_referenced(mmu_t, vm_page_t);
289 int moea_ts_referenced(mmu_t, vm_page_t);
290 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
291 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
292 void moea_page_init(mmu_t, vm_page_t);
293 int moea_page_wired_mappings(mmu_t, vm_page_t);
294 void moea_pinit(mmu_t, pmap_t);
295 void moea_pinit0(mmu_t, pmap_t);
296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
298 void moea_qremove(mmu_t, vm_offset_t, int);
299 void moea_release(mmu_t, pmap_t);
300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_remove_all(mmu_t, vm_page_t);
302 void moea_remove_write(mmu_t, vm_page_t);
303 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
304 void moea_zero_page(mmu_t, vm_page_t);
305 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
306 void moea_activate(mmu_t, struct thread *);
307 void moea_deactivate(mmu_t, struct thread *);
308 void moea_cpu_bootstrap(mmu_t, int);
309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
310 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
311 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
313 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
315 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
317 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
319 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va);
320 void moea_scan_init(mmu_t mmu);
321 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m);
322 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr);
323 
324 static mmu_method_t moea_methods[] = {
325 	MMUMETHOD(mmu_clear_modify,	moea_clear_modify),
326 	MMUMETHOD(mmu_copy_page,	moea_copy_page),
327 	MMUMETHOD(mmu_copy_pages,	moea_copy_pages),
328 	MMUMETHOD(mmu_enter,		moea_enter),
329 	MMUMETHOD(mmu_enter_object,	moea_enter_object),
330 	MMUMETHOD(mmu_enter_quick,	moea_enter_quick),
331 	MMUMETHOD(mmu_extract,		moea_extract),
332 	MMUMETHOD(mmu_extract_and_hold,	moea_extract_and_hold),
333 	MMUMETHOD(mmu_init,		moea_init),
334 	MMUMETHOD(mmu_is_modified,	moea_is_modified),
335 	MMUMETHOD(mmu_is_prefaultable,	moea_is_prefaultable),
336 	MMUMETHOD(mmu_is_referenced,	moea_is_referenced),
337 	MMUMETHOD(mmu_ts_referenced,	moea_ts_referenced),
338 	MMUMETHOD(mmu_map,     		moea_map),
339 	MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
340 	MMUMETHOD(mmu_page_init,	moea_page_init),
341 	MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
342 	MMUMETHOD(mmu_pinit,		moea_pinit),
343 	MMUMETHOD(mmu_pinit0,		moea_pinit0),
344 	MMUMETHOD(mmu_protect,		moea_protect),
345 	MMUMETHOD(mmu_qenter,		moea_qenter),
346 	MMUMETHOD(mmu_qremove,		moea_qremove),
347 	MMUMETHOD(mmu_release,		moea_release),
348 	MMUMETHOD(mmu_remove,		moea_remove),
349 	MMUMETHOD(mmu_remove_all,      	moea_remove_all),
350 	MMUMETHOD(mmu_remove_write,	moea_remove_write),
351 	MMUMETHOD(mmu_sync_icache,	moea_sync_icache),
352 	MMUMETHOD(mmu_unwire,		moea_unwire),
353 	MMUMETHOD(mmu_zero_page,       	moea_zero_page),
354 	MMUMETHOD(mmu_zero_page_area,	moea_zero_page_area),
355 	MMUMETHOD(mmu_activate,		moea_activate),
356 	MMUMETHOD(mmu_deactivate,      	moea_deactivate),
357 	MMUMETHOD(mmu_page_set_memattr,	moea_page_set_memattr),
358 	MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page),
359 	MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page),
360 
361 	/* Internal interfaces */
362 	MMUMETHOD(mmu_bootstrap,       	moea_bootstrap),
363 	MMUMETHOD(mmu_cpu_bootstrap,   	moea_cpu_bootstrap),
364 	MMUMETHOD(mmu_mapdev_attr,	moea_mapdev_attr),
365 	MMUMETHOD(mmu_mapdev,		moea_mapdev),
366 	MMUMETHOD(mmu_unmapdev,		moea_unmapdev),
367 	MMUMETHOD(mmu_kextract,		moea_kextract),
368 	MMUMETHOD(mmu_kenter,		moea_kenter),
369 	MMUMETHOD(mmu_kenter_attr,	moea_kenter_attr),
370 	MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
371 	MMUMETHOD(mmu_scan_init,	moea_scan_init),
372 	MMUMETHOD(mmu_dumpsys_map,	moea_dumpsys_map),
373 
374 	{ 0, 0 }
375 };
376 
377 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
378 
379 static __inline uint32_t
380 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
381 {
382 	uint32_t pte_lo;
383 	int i;
384 
385 	if (ma != VM_MEMATTR_DEFAULT) {
386 		switch (ma) {
387 		case VM_MEMATTR_UNCACHEABLE:
388 			return (PTE_I | PTE_G);
389 		case VM_MEMATTR_CACHEABLE:
390 			return (PTE_M);
391 		case VM_MEMATTR_WRITE_COMBINING:
392 		case VM_MEMATTR_WRITE_BACK:
393 		case VM_MEMATTR_PREFETCHABLE:
394 			return (PTE_I);
395 		case VM_MEMATTR_WRITE_THROUGH:
396 			return (PTE_W | PTE_M);
397 		}
398 	}
399 
400 	/*
401 	 * Assume the page is cache inhibited and access is guarded unless
402 	 * it's in our available memory array.
403 	 */
404 	pte_lo = PTE_I | PTE_G;
405 	for (i = 0; i < pregions_sz; i++) {
406 		if ((pa >= pregions[i].mr_start) &&
407 		    (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
408 			pte_lo = PTE_M;
409 			break;
410 		}
411 	}
412 
413 	return pte_lo;
414 }
415 
416 static void
417 tlbie(vm_offset_t va)
418 {
419 
420 	mtx_lock_spin(&tlbie_mtx);
421 	__asm __volatile("ptesync");
422 	__asm __volatile("tlbie %0" :: "r"(va));
423 	__asm __volatile("eieio; tlbsync; ptesync");
424 	mtx_unlock_spin(&tlbie_mtx);
425 }
426 
427 static void
428 tlbia(void)
429 {
430 	vm_offset_t va;
431 
432 	for (va = 0; va < 0x00040000; va += 0x00001000) {
433 		__asm __volatile("tlbie %0" :: "r"(va));
434 		powerpc_sync();
435 	}
436 	__asm __volatile("tlbsync");
437 	powerpc_sync();
438 }
439 
440 static __inline int
441 va_to_sr(u_int *sr, vm_offset_t va)
442 {
443 	return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
444 }
445 
446 static __inline u_int
447 va_to_pteg(u_int sr, vm_offset_t addr)
448 {
449 	u_int hash;
450 
451 	hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
452 	    ADDR_PIDX_SHFT);
453 	return (hash & moea_pteg_mask);
454 }
455 
456 static __inline struct pvo_head *
457 vm_page_to_pvoh(vm_page_t m)
458 {
459 
460 	return (&m->md.mdpg_pvoh);
461 }
462 
463 static __inline void
464 moea_attr_clear(vm_page_t m, int ptebit)
465 {
466 
467 	rw_assert(&pvh_global_lock, RA_WLOCKED);
468 	m->md.mdpg_attrs &= ~ptebit;
469 }
470 
471 static __inline int
472 moea_attr_fetch(vm_page_t m)
473 {
474 
475 	return (m->md.mdpg_attrs);
476 }
477 
478 static __inline void
479 moea_attr_save(vm_page_t m, int ptebit)
480 {
481 
482 	rw_assert(&pvh_global_lock, RA_WLOCKED);
483 	m->md.mdpg_attrs |= ptebit;
484 }
485 
486 static __inline int
487 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
488 {
489 	if (pt->pte_hi == pvo_pt->pte_hi)
490 		return (1);
491 
492 	return (0);
493 }
494 
495 static __inline int
496 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
497 {
498 	return (pt->pte_hi & ~PTE_VALID) ==
499 	    (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
500 	    ((va >> ADDR_API_SHFT) & PTE_API) | which);
501 }
502 
503 static __inline void
504 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
505 {
506 
507 	mtx_assert(&moea_table_mutex, MA_OWNED);
508 
509 	/*
510 	 * Construct a PTE.  Default to IMB initially.  Valid bit only gets
511 	 * set when the real pte is set in memory.
512 	 *
513 	 * Note: Don't set the valid bit for correct operation of tlb update.
514 	 */
515 	pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
516 	    (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
517 	pt->pte_lo = pte_lo;
518 }
519 
520 static __inline void
521 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
522 {
523 
524 	mtx_assert(&moea_table_mutex, MA_OWNED);
525 	pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
526 }
527 
528 static __inline void
529 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
530 {
531 
532 	mtx_assert(&moea_table_mutex, MA_OWNED);
533 
534 	/*
535 	 * As shown in Section 7.6.3.2.3
536 	 */
537 	pt->pte_lo &= ~ptebit;
538 	tlbie(va);
539 }
540 
541 static __inline void
542 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
543 {
544 
545 	mtx_assert(&moea_table_mutex, MA_OWNED);
546 	pvo_pt->pte_hi |= PTE_VALID;
547 
548 	/*
549 	 * Update the PTE as defined in section 7.6.3.1.
550 	 * Note that the REF/CHG bits are from pvo_pt and thus should have
551 	 * been saved so this routine can restore them (if desired).
552 	 */
553 	pt->pte_lo = pvo_pt->pte_lo;
554 	powerpc_sync();
555 	pt->pte_hi = pvo_pt->pte_hi;
556 	powerpc_sync();
557 	moea_pte_valid++;
558 }
559 
560 static __inline void
561 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
562 {
563 
564 	mtx_assert(&moea_table_mutex, MA_OWNED);
565 	pvo_pt->pte_hi &= ~PTE_VALID;
566 
567 	/*
568 	 * Force the reg & chg bits back into the PTEs.
569 	 */
570 	powerpc_sync();
571 
572 	/*
573 	 * Invalidate the pte.
574 	 */
575 	pt->pte_hi &= ~PTE_VALID;
576 
577 	tlbie(va);
578 
579 	/*
580 	 * Save the reg & chg bits.
581 	 */
582 	moea_pte_synch(pt, pvo_pt);
583 	moea_pte_valid--;
584 }
585 
586 static __inline void
587 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
588 {
589 
590 	/*
591 	 * Invalidate the PTE
592 	 */
593 	moea_pte_unset(pt, pvo_pt, va);
594 	moea_pte_set(pt, pvo_pt);
595 }
596 
597 /*
598  * Quick sort callout for comparing memory regions.
599  */
600 static int	om_cmp(const void *a, const void *b);
601 
602 static int
603 om_cmp(const void *a, const void *b)
604 {
605 	const struct	ofw_map *mapa;
606 	const struct	ofw_map *mapb;
607 
608 	mapa = a;
609 	mapb = b;
610 	if (mapa->om_pa < mapb->om_pa)
611 		return (-1);
612 	else if (mapa->om_pa > mapb->om_pa)
613 		return (1);
614 	else
615 		return (0);
616 }
617 
618 void
619 moea_cpu_bootstrap(mmu_t mmup, int ap)
620 {
621 	u_int sdr;
622 	int i;
623 
624 	if (ap) {
625 		powerpc_sync();
626 		__asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
627 		__asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
628 		isync();
629 		__asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
630 		__asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
631 		isync();
632 	}
633 
634 	__asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
635 	__asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
636 	isync();
637 
638 	__asm __volatile("mtibatu 1,%0" :: "r"(0));
639 	__asm __volatile("mtdbatu 2,%0" :: "r"(0));
640 	__asm __volatile("mtibatu 2,%0" :: "r"(0));
641 	__asm __volatile("mtdbatu 3,%0" :: "r"(0));
642 	__asm __volatile("mtibatu 3,%0" :: "r"(0));
643 	isync();
644 
645 	for (i = 0; i < 16; i++)
646 		mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
647 	powerpc_sync();
648 
649 	sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
650 	__asm __volatile("mtsdr1 %0" :: "r"(sdr));
651 	isync();
652 
653 	tlbia();
654 }
655 
656 void
657 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
658 {
659 	ihandle_t	mmui;
660 	phandle_t	chosen, mmu;
661 	int		sz;
662 	int		i, j;
663 	vm_size_t	size, physsz, hwphyssz;
664 	vm_offset_t	pa, va, off;
665 	void		*dpcpu;
666 	register_t	msr;
667 
668         /*
669          * Set up BAT0 to map the lowest 256 MB area
670          */
671         battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
672         battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
673 
674 	/*
675 	 * Map PCI memory space.
676 	 */
677 	battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
678 	battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
679 
680 	battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
681 	battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
682 
683 	battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
684 	battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
685 
686 	battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
687 	battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
688 
689 	/*
690 	 * Map obio devices.
691 	 */
692 	battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
693 	battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
694 
695 	/*
696 	 * Use an IBAT and a DBAT to map the bottom segment of memory
697 	 * where we are. Turn off instruction relocation temporarily
698 	 * to prevent faults while reprogramming the IBAT.
699 	 */
700 	msr = mfmsr();
701 	mtmsr(msr & ~PSL_IR);
702 	__asm (".balign 32; \n"
703 	       "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
704 	       "mtdbatu 0,%0; mtdbatl 0,%1; isync"
705 	    :: "r"(battable[0].batu), "r"(battable[0].batl));
706 	mtmsr(msr);
707 
708 	/* map pci space */
709 	__asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
710 	__asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
711 	isync();
712 
713 	/* set global direct map flag */
714 	hw_direct_map = 1;
715 
716 	mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
717 	CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
718 
719 	for (i = 0; i < pregions_sz; i++) {
720 		vm_offset_t pa;
721 		vm_offset_t end;
722 
723 		CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
724 			pregions[i].mr_start,
725 			pregions[i].mr_start + pregions[i].mr_size,
726 			pregions[i].mr_size);
727 		/*
728 		 * Install entries into the BAT table to allow all
729 		 * of physmem to be convered by on-demand BAT entries.
730 		 * The loop will sometimes set the same battable element
731 		 * twice, but that's fine since they won't be used for
732 		 * a while yet.
733 		 */
734 		pa = pregions[i].mr_start & 0xf0000000;
735 		end = pregions[i].mr_start + pregions[i].mr_size;
736 		do {
737                         u_int n = pa >> ADDR_SR_SHFT;
738 
739 			battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
740 			battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
741 			pa += SEGMENT_LENGTH;
742 		} while (pa < end);
743 	}
744 
745 	if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
746 		panic("moea_bootstrap: phys_avail too small");
747 
748 	phys_avail_count = 0;
749 	physsz = 0;
750 	hwphyssz = 0;
751 	TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
752 	for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
753 		CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
754 		    regions[i].mr_start + regions[i].mr_size,
755 		    regions[i].mr_size);
756 		if (hwphyssz != 0 &&
757 		    (physsz + regions[i].mr_size) >= hwphyssz) {
758 			if (physsz < hwphyssz) {
759 				phys_avail[j] = regions[i].mr_start;
760 				phys_avail[j + 1] = regions[i].mr_start +
761 				    hwphyssz - physsz;
762 				physsz = hwphyssz;
763 				phys_avail_count++;
764 			}
765 			break;
766 		}
767 		phys_avail[j] = regions[i].mr_start;
768 		phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
769 		phys_avail_count++;
770 		physsz += regions[i].mr_size;
771 	}
772 
773 	/* Check for overlap with the kernel and exception vectors */
774 	for (j = 0; j < 2*phys_avail_count; j+=2) {
775 		if (phys_avail[j] < EXC_LAST)
776 			phys_avail[j] += EXC_LAST;
777 
778 		if (kernelstart >= phys_avail[j] &&
779 		    kernelstart < phys_avail[j+1]) {
780 			if (kernelend < phys_avail[j+1]) {
781 				phys_avail[2*phys_avail_count] =
782 				    (kernelend & ~PAGE_MASK) + PAGE_SIZE;
783 				phys_avail[2*phys_avail_count + 1] =
784 				    phys_avail[j+1];
785 				phys_avail_count++;
786 			}
787 
788 			phys_avail[j+1] = kernelstart & ~PAGE_MASK;
789 		}
790 
791 		if (kernelend >= phys_avail[j] &&
792 		    kernelend < phys_avail[j+1]) {
793 			if (kernelstart > phys_avail[j]) {
794 				phys_avail[2*phys_avail_count] = phys_avail[j];
795 				phys_avail[2*phys_avail_count + 1] =
796 				    kernelstart & ~PAGE_MASK;
797 				phys_avail_count++;
798 			}
799 
800 			phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
801 		}
802 	}
803 
804 	physmem = btoc(physsz);
805 
806 	/*
807 	 * Allocate PTEG table.
808 	 */
809 #ifdef PTEGCOUNT
810 	moea_pteg_count = PTEGCOUNT;
811 #else
812 	moea_pteg_count = 0x1000;
813 
814 	while (moea_pteg_count < physmem)
815 		moea_pteg_count <<= 1;
816 
817 	moea_pteg_count >>= 1;
818 #endif /* PTEGCOUNT */
819 
820 	size = moea_pteg_count * sizeof(struct pteg);
821 	CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
822 	    size);
823 	moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
824 	CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
825 	bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
826 	moea_pteg_mask = moea_pteg_count - 1;
827 
828 	/*
829 	 * Allocate pv/overflow lists.
830 	 */
831 	size = sizeof(struct pvo_head) * moea_pteg_count;
832 	moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
833 	    PAGE_SIZE);
834 	CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
835 	for (i = 0; i < moea_pteg_count; i++)
836 		LIST_INIT(&moea_pvo_table[i]);
837 
838 	/*
839 	 * Initialize the lock that synchronizes access to the pteg and pvo
840 	 * tables.
841 	 */
842 	mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
843 	    MTX_RECURSE);
844 	mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
845 
846 	mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
847 
848 	/*
849 	 * Initialise the unmanaged pvo pool.
850 	 */
851 	moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
852 		BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
853 	moea_bpvo_pool_index = 0;
854 
855 	/*
856 	 * Make sure kernel vsid is allocated as well as VSID 0.
857 	 */
858 	moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
859 		|= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
860 	moea_vsid_bitmap[0] |= 1;
861 
862 	/*
863 	 * Initialize the kernel pmap (which is statically allocated).
864 	 */
865 	PMAP_LOCK_INIT(kernel_pmap);
866 	for (i = 0; i < 16; i++)
867 		kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
868 	CPU_FILL(&kernel_pmap->pm_active);
869 	RB_INIT(&kernel_pmap->pmap_pvo);
870 
871  	/*
872 	 * Initialize the global pv list lock.
873 	 */
874 	rw_init(&pvh_global_lock, "pmap pv global");
875 
876 	/*
877 	 * Set up the Open Firmware mappings
878 	 */
879 	chosen = OF_finddevice("/chosen");
880 	if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
881 	    (mmu = OF_instance_to_package(mmui)) != -1 &&
882 	    (sz = OF_getproplen(mmu, "translations")) != -1) {
883 		translations = NULL;
884 		for (i = 0; phys_avail[i] != 0; i += 2) {
885 			if (phys_avail[i + 1] >= sz) {
886 				translations = (struct ofw_map *)phys_avail[i];
887 				break;
888 			}
889 		}
890 		if (translations == NULL)
891 			panic("moea_bootstrap: no space to copy translations");
892 		bzero(translations, sz);
893 		if (OF_getprop(mmu, "translations", translations, sz) == -1)
894 			panic("moea_bootstrap: can't get ofw translations");
895 		CTR0(KTR_PMAP, "moea_bootstrap: translations");
896 		sz /= sizeof(*translations);
897 		qsort(translations, sz, sizeof (*translations), om_cmp);
898 		for (i = 0; i < sz; i++) {
899 			CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
900 			    translations[i].om_pa, translations[i].om_va,
901 			    translations[i].om_len);
902 
903 			/*
904 			 * If the mapping is 1:1, let the RAM and device
905 			 * on-demand BAT tables take care of the translation.
906 			 */
907 			if (translations[i].om_va == translations[i].om_pa)
908 				continue;
909 
910 			/* Enter the pages */
911 			for (off = 0; off < translations[i].om_len;
912 			    off += PAGE_SIZE)
913 				moea_kenter(mmup, translations[i].om_va + off,
914 					    translations[i].om_pa + off);
915 		}
916 	}
917 
918 	/*
919 	 * Calculate the last available physical address.
920 	 */
921 	for (i = 0; phys_avail[i + 2] != 0; i += 2)
922 		;
923 	Maxmem = powerpc_btop(phys_avail[i + 1]);
924 
925 	moea_cpu_bootstrap(mmup,0);
926 	mtmsr(mfmsr() | PSL_DR | PSL_IR);
927 	pmap_bootstrapped++;
928 
929 	/*
930 	 * Set the start and end of kva.
931 	 */
932 	virtual_avail = VM_MIN_KERNEL_ADDRESS;
933 	virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
934 
935 	/*
936 	 * Allocate a kernel stack with a guard page for thread0 and map it
937 	 * into the kernel page map.
938 	 */
939 	pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
940 	va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
941 	virtual_avail = va + kstack_pages * PAGE_SIZE;
942 	CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
943 	thread0.td_kstack = va;
944 	thread0.td_kstack_pages = kstack_pages;
945 	for (i = 0; i < kstack_pages; i++) {
946 		moea_kenter(mmup, va, pa);
947 		pa += PAGE_SIZE;
948 		va += PAGE_SIZE;
949 	}
950 
951 	/*
952 	 * Allocate virtual address space for the message buffer.
953 	 */
954 	pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
955 	msgbufp = (struct msgbuf *)virtual_avail;
956 	va = virtual_avail;
957 	virtual_avail += round_page(msgbufsize);
958 	while (va < virtual_avail) {
959 		moea_kenter(mmup, va, pa);
960 		pa += PAGE_SIZE;
961 		va += PAGE_SIZE;
962 	}
963 
964 	/*
965 	 * Allocate virtual address space for the dynamic percpu area.
966 	 */
967 	pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
968 	dpcpu = (void *)virtual_avail;
969 	va = virtual_avail;
970 	virtual_avail += DPCPU_SIZE;
971 	while (va < virtual_avail) {
972 		moea_kenter(mmup, va, pa);
973 		pa += PAGE_SIZE;
974 		va += PAGE_SIZE;
975 	}
976 	dpcpu_init(dpcpu, 0);
977 }
978 
979 /*
980  * Activate a user pmap.  The pmap must be activated before it's address
981  * space can be accessed in any way.
982  */
983 void
984 moea_activate(mmu_t mmu, struct thread *td)
985 {
986 	pmap_t	pm, pmr;
987 
988 	/*
989 	 * Load all the data we need up front to encourage the compiler to
990 	 * not issue any loads while we have interrupts disabled below.
991 	 */
992 	pm = &td->td_proc->p_vmspace->vm_pmap;
993 	pmr = pm->pmap_phys;
994 
995 	CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
996 	PCPU_SET(curpmap, pmr);
997 
998 	mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
999 }
1000 
1001 void
1002 moea_deactivate(mmu_t mmu, struct thread *td)
1003 {
1004 	pmap_t	pm;
1005 
1006 	pm = &td->td_proc->p_vmspace->vm_pmap;
1007 	CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1008 	PCPU_SET(curpmap, NULL);
1009 }
1010 
1011 void
1012 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1013 {
1014 	struct	pvo_entry key, *pvo;
1015 
1016 	PMAP_LOCK(pm);
1017 	key.pvo_vaddr = sva;
1018 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1019 	    pvo != NULL && PVO_VADDR(pvo) < eva;
1020 	    pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1021 		if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1022 			panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo);
1023 		pvo->pvo_vaddr &= ~PVO_WIRED;
1024 		pm->pm_stats.wired_count--;
1025 	}
1026 	PMAP_UNLOCK(pm);
1027 }
1028 
1029 void
1030 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1031 {
1032 	vm_offset_t	dst;
1033 	vm_offset_t	src;
1034 
1035 	dst = VM_PAGE_TO_PHYS(mdst);
1036 	src = VM_PAGE_TO_PHYS(msrc);
1037 
1038 	bcopy((void *)src, (void *)dst, PAGE_SIZE);
1039 }
1040 
1041 void
1042 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1043     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1044 {
1045 	void *a_cp, *b_cp;
1046 	vm_offset_t a_pg_offset, b_pg_offset;
1047 	int cnt;
1048 
1049 	while (xfersize > 0) {
1050 		a_pg_offset = a_offset & PAGE_MASK;
1051 		cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1052 		a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1053 		    a_pg_offset;
1054 		b_pg_offset = b_offset & PAGE_MASK;
1055 		cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1056 		b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1057 		    b_pg_offset;
1058 		bcopy(a_cp, b_cp, cnt);
1059 		a_offset += cnt;
1060 		b_offset += cnt;
1061 		xfersize -= cnt;
1062 	}
1063 }
1064 
1065 /*
1066  * Zero a page of physical memory by temporarily mapping it into the tlb.
1067  */
1068 void
1069 moea_zero_page(mmu_t mmu, vm_page_t m)
1070 {
1071 	vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1072 
1073 	for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1074 		__asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1075 }
1076 
1077 void
1078 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1079 {
1080 	vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1081 	void *va = (void *)(pa + off);
1082 
1083 	bzero(va, size);
1084 }
1085 
1086 vm_offset_t
1087 moea_quick_enter_page(mmu_t mmu, vm_page_t m)
1088 {
1089 
1090 	return (VM_PAGE_TO_PHYS(m));
1091 }
1092 
1093 void
1094 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1095 {
1096 }
1097 
1098 /*
1099  * Map the given physical page at the specified virtual address in the
1100  * target pmap with the protection requested.  If specified the page
1101  * will be wired down.
1102  */
1103 int
1104 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1105     u_int flags, int8_t psind)
1106 {
1107 	int error;
1108 
1109 	for (;;) {
1110 		rw_wlock(&pvh_global_lock);
1111 		PMAP_LOCK(pmap);
1112 		error = moea_enter_locked(pmap, va, m, prot, flags, psind);
1113 		rw_wunlock(&pvh_global_lock);
1114 		PMAP_UNLOCK(pmap);
1115 		if (error != ENOMEM)
1116 			return (KERN_SUCCESS);
1117 		if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1118 			return (KERN_RESOURCE_SHORTAGE);
1119 		VM_OBJECT_ASSERT_UNLOCKED(m->object);
1120 		VM_WAIT;
1121 	}
1122 }
1123 
1124 /*
1125  * Map the given physical page at the specified virtual address in the
1126  * target pmap with the protection requested.  If specified the page
1127  * will be wired down.
1128  *
1129  * The global pvh and pmap must be locked.
1130  */
1131 static int
1132 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1133     u_int flags, int8_t psind __unused)
1134 {
1135 	struct		pvo_head *pvo_head;
1136 	uma_zone_t	zone;
1137 	u_int		pte_lo, pvo_flags;
1138 	int		error;
1139 
1140 	if (pmap_bootstrapped)
1141 		rw_assert(&pvh_global_lock, RA_WLOCKED);
1142 	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1143 	if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1144 		VM_OBJECT_ASSERT_LOCKED(m->object);
1145 
1146 	if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) {
1147 		pvo_head = &moea_pvo_kunmanaged;
1148 		zone = moea_upvo_zone;
1149 		pvo_flags = 0;
1150 	} else {
1151 		pvo_head = vm_page_to_pvoh(m);
1152 		zone = moea_mpvo_zone;
1153 		pvo_flags = PVO_MANAGED;
1154 	}
1155 
1156 	pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1157 
1158 	if (prot & VM_PROT_WRITE) {
1159 		pte_lo |= PTE_BW;
1160 		if (pmap_bootstrapped &&
1161 		    (m->oflags & VPO_UNMANAGED) == 0)
1162 			vm_page_aflag_set(m, PGA_WRITEABLE);
1163 	} else
1164 		pte_lo |= PTE_BR;
1165 
1166 	if ((flags & PMAP_ENTER_WIRED) != 0)
1167 		pvo_flags |= PVO_WIRED;
1168 
1169 	error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1170 	    pte_lo, pvo_flags);
1171 
1172 	/*
1173 	 * Flush the real page from the instruction cache. This has be done
1174 	 * for all user mappings to prevent information leakage via the
1175 	 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1176 	 * mapping for a page.
1177 	 */
1178 	if (pmap != kernel_pmap && error == ENOENT &&
1179 	    (pte_lo & (PTE_I | PTE_G)) == 0)
1180 		moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1181 
1182 	return (error);
1183 }
1184 
1185 /*
1186  * Maps a sequence of resident pages belonging to the same object.
1187  * The sequence begins with the given page m_start.  This page is
1188  * mapped at the given virtual address start.  Each subsequent page is
1189  * mapped at a virtual address that is offset from start by the same
1190  * amount as the page is offset from m_start within the object.  The
1191  * last page in the sequence is the page with the largest offset from
1192  * m_start that can be mapped at a virtual address less than the given
1193  * virtual address end.  Not every virtual page between start and end
1194  * is mapped; only those for which a resident page exists with the
1195  * corresponding offset from m_start are mapped.
1196  */
1197 void
1198 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1199     vm_page_t m_start, vm_prot_t prot)
1200 {
1201 	vm_page_t m;
1202 	vm_pindex_t diff, psize;
1203 
1204 	VM_OBJECT_ASSERT_LOCKED(m_start->object);
1205 
1206 	psize = atop(end - start);
1207 	m = m_start;
1208 	rw_wlock(&pvh_global_lock);
1209 	PMAP_LOCK(pm);
1210 	while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1211 		moea_enter_locked(pm, start + ptoa(diff), m, prot &
1212 		    (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1213 		m = TAILQ_NEXT(m, listq);
1214 	}
1215 	rw_wunlock(&pvh_global_lock);
1216 	PMAP_UNLOCK(pm);
1217 }
1218 
1219 void
1220 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1221     vm_prot_t prot)
1222 {
1223 
1224 	rw_wlock(&pvh_global_lock);
1225 	PMAP_LOCK(pm);
1226 	moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1227 	    0, 0);
1228 	rw_wunlock(&pvh_global_lock);
1229 	PMAP_UNLOCK(pm);
1230 }
1231 
1232 vm_paddr_t
1233 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1234 {
1235 	struct	pvo_entry *pvo;
1236 	vm_paddr_t pa;
1237 
1238 	PMAP_LOCK(pm);
1239 	pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1240 	if (pvo == NULL)
1241 		pa = 0;
1242 	else
1243 		pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1244 	PMAP_UNLOCK(pm);
1245 	return (pa);
1246 }
1247 
1248 /*
1249  * Atomically extract and hold the physical page with the given
1250  * pmap and virtual address pair if that mapping permits the given
1251  * protection.
1252  */
1253 vm_page_t
1254 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1255 {
1256 	struct	pvo_entry *pvo;
1257 	vm_page_t m;
1258         vm_paddr_t pa;
1259 
1260 	m = NULL;
1261 	pa = 0;
1262 	PMAP_LOCK(pmap);
1263 retry:
1264 	pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1265 	if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1266 	    ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1267 	     (prot & VM_PROT_WRITE) == 0)) {
1268 		if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1269 			goto retry;
1270 		m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1271 		vm_page_hold(m);
1272 	}
1273 	PA_UNLOCK_COND(pa);
1274 	PMAP_UNLOCK(pmap);
1275 	return (m);
1276 }
1277 
1278 void
1279 moea_init(mmu_t mmu)
1280 {
1281 
1282 	moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1283 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1284 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1285 	moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1286 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1287 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1288 	moea_initialized = TRUE;
1289 }
1290 
1291 boolean_t
1292 moea_is_referenced(mmu_t mmu, vm_page_t m)
1293 {
1294 	boolean_t rv;
1295 
1296 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1297 	    ("moea_is_referenced: page %p is not managed", m));
1298 	rw_wlock(&pvh_global_lock);
1299 	rv = moea_query_bit(m, PTE_REF);
1300 	rw_wunlock(&pvh_global_lock);
1301 	return (rv);
1302 }
1303 
1304 boolean_t
1305 moea_is_modified(mmu_t mmu, vm_page_t m)
1306 {
1307 	boolean_t rv;
1308 
1309 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1310 	    ("moea_is_modified: page %p is not managed", m));
1311 
1312 	/*
1313 	 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1314 	 * concurrently set while the object is locked.  Thus, if PGA_WRITEABLE
1315 	 * is clear, no PTEs can have PTE_CHG set.
1316 	 */
1317 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1318 	if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1319 		return (FALSE);
1320 	rw_wlock(&pvh_global_lock);
1321 	rv = moea_query_bit(m, PTE_CHG);
1322 	rw_wunlock(&pvh_global_lock);
1323 	return (rv);
1324 }
1325 
1326 boolean_t
1327 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1328 {
1329 	struct pvo_entry *pvo;
1330 	boolean_t rv;
1331 
1332 	PMAP_LOCK(pmap);
1333 	pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1334 	rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1335 	PMAP_UNLOCK(pmap);
1336 	return (rv);
1337 }
1338 
1339 void
1340 moea_clear_modify(mmu_t mmu, vm_page_t m)
1341 {
1342 
1343 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1344 	    ("moea_clear_modify: page %p is not managed", m));
1345 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1346 	KASSERT(!vm_page_xbusied(m),
1347 	    ("moea_clear_modify: page %p is exclusive busy", m));
1348 
1349 	/*
1350 	 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1351 	 * set.  If the object containing the page is locked and the page is
1352 	 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1353 	 */
1354 	if ((m->aflags & PGA_WRITEABLE) == 0)
1355 		return;
1356 	rw_wlock(&pvh_global_lock);
1357 	moea_clear_bit(m, PTE_CHG);
1358 	rw_wunlock(&pvh_global_lock);
1359 }
1360 
1361 /*
1362  * Clear the write and modified bits in each of the given page's mappings.
1363  */
1364 void
1365 moea_remove_write(mmu_t mmu, vm_page_t m)
1366 {
1367 	struct	pvo_entry *pvo;
1368 	struct	pte *pt;
1369 	pmap_t	pmap;
1370 	u_int	lo;
1371 
1372 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1373 	    ("moea_remove_write: page %p is not managed", m));
1374 
1375 	/*
1376 	 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1377 	 * set by another thread while the object is locked.  Thus,
1378 	 * if PGA_WRITEABLE is clear, no page table entries need updating.
1379 	 */
1380 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1381 	if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1382 		return;
1383 	rw_wlock(&pvh_global_lock);
1384 	lo = moea_attr_fetch(m);
1385 	powerpc_sync();
1386 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1387 		pmap = pvo->pvo_pmap;
1388 		PMAP_LOCK(pmap);
1389 		if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1390 			pt = moea_pvo_to_pte(pvo, -1);
1391 			pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1392 			pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1393 			if (pt != NULL) {
1394 				moea_pte_synch(pt, &pvo->pvo_pte.pte);
1395 				lo |= pvo->pvo_pte.pte.pte_lo;
1396 				pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1397 				moea_pte_change(pt, &pvo->pvo_pte.pte,
1398 				    pvo->pvo_vaddr);
1399 				mtx_unlock(&moea_table_mutex);
1400 			}
1401 		}
1402 		PMAP_UNLOCK(pmap);
1403 	}
1404 	if ((lo & PTE_CHG) != 0) {
1405 		moea_attr_clear(m, PTE_CHG);
1406 		vm_page_dirty(m);
1407 	}
1408 	vm_page_aflag_clear(m, PGA_WRITEABLE);
1409 	rw_wunlock(&pvh_global_lock);
1410 }
1411 
1412 /*
1413  *	moea_ts_referenced:
1414  *
1415  *	Return a count of reference bits for a page, clearing those bits.
1416  *	It is not necessary for every reference bit to be cleared, but it
1417  *	is necessary that 0 only be returned when there are truly no
1418  *	reference bits set.
1419  *
1420  *	XXX: The exact number of bits to check and clear is a matter that
1421  *	should be tested and standardized at some point in the future for
1422  *	optimal aging of shared pages.
1423  */
1424 int
1425 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1426 {
1427 	int count;
1428 
1429 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1430 	    ("moea_ts_referenced: page %p is not managed", m));
1431 	rw_wlock(&pvh_global_lock);
1432 	count = moea_clear_bit(m, PTE_REF);
1433 	rw_wunlock(&pvh_global_lock);
1434 	return (count);
1435 }
1436 
1437 /*
1438  * Modify the WIMG settings of all mappings for a page.
1439  */
1440 void
1441 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1442 {
1443 	struct	pvo_entry *pvo;
1444 	struct	pvo_head *pvo_head;
1445 	struct	pte *pt;
1446 	pmap_t	pmap;
1447 	u_int	lo;
1448 
1449 	if ((m->oflags & VPO_UNMANAGED) != 0) {
1450 		m->md.mdpg_cache_attrs = ma;
1451 		return;
1452 	}
1453 
1454 	rw_wlock(&pvh_global_lock);
1455 	pvo_head = vm_page_to_pvoh(m);
1456 	lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1457 
1458 	LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1459 		pmap = pvo->pvo_pmap;
1460 		PMAP_LOCK(pmap);
1461 		pt = moea_pvo_to_pte(pvo, -1);
1462 		pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1463 		pvo->pvo_pte.pte.pte_lo |= lo;
1464 		if (pt != NULL) {
1465 			moea_pte_change(pt, &pvo->pvo_pte.pte,
1466 			    pvo->pvo_vaddr);
1467 			if (pvo->pvo_pmap == kernel_pmap)
1468 				isync();
1469 		}
1470 		mtx_unlock(&moea_table_mutex);
1471 		PMAP_UNLOCK(pmap);
1472 	}
1473 	m->md.mdpg_cache_attrs = ma;
1474 	rw_wunlock(&pvh_global_lock);
1475 }
1476 
1477 /*
1478  * Map a wired page into kernel virtual address space.
1479  */
1480 void
1481 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1482 {
1483 
1484 	moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1485 }
1486 
1487 void
1488 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1489 {
1490 	u_int		pte_lo;
1491 	int		error;
1492 
1493 #if 0
1494 	if (va < VM_MIN_KERNEL_ADDRESS)
1495 		panic("moea_kenter: attempt to enter non-kernel address %#x",
1496 		    va);
1497 #endif
1498 
1499 	pte_lo = moea_calc_wimg(pa, ma);
1500 
1501 	PMAP_LOCK(kernel_pmap);
1502 	error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1503 	    &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1504 
1505 	if (error != 0 && error != ENOENT)
1506 		panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1507 		    pa, error);
1508 
1509 	PMAP_UNLOCK(kernel_pmap);
1510 }
1511 
1512 /*
1513  * Extract the physical page address associated with the given kernel virtual
1514  * address.
1515  */
1516 vm_paddr_t
1517 moea_kextract(mmu_t mmu, vm_offset_t va)
1518 {
1519 	struct		pvo_entry *pvo;
1520 	vm_paddr_t pa;
1521 
1522 	/*
1523 	 * Allow direct mappings on 32-bit OEA
1524 	 */
1525 	if (va < VM_MIN_KERNEL_ADDRESS) {
1526 		return (va);
1527 	}
1528 
1529 	PMAP_LOCK(kernel_pmap);
1530 	pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1531 	KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1532 	pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1533 	PMAP_UNLOCK(kernel_pmap);
1534 	return (pa);
1535 }
1536 
1537 /*
1538  * Remove a wired page from kernel virtual address space.
1539  */
1540 void
1541 moea_kremove(mmu_t mmu, vm_offset_t va)
1542 {
1543 
1544 	moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1545 }
1546 
1547 /*
1548  * Map a range of physical addresses into kernel virtual address space.
1549  *
1550  * The value passed in *virt is a suggested virtual address for the mapping.
1551  * Architectures which can support a direct-mapped physical to virtual region
1552  * can return the appropriate address within that region, leaving '*virt'
1553  * unchanged.  We cannot and therefore do not; *virt is updated with the
1554  * first usable address after the mapped region.
1555  */
1556 vm_offset_t
1557 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1558     vm_paddr_t pa_end, int prot)
1559 {
1560 	vm_offset_t	sva, va;
1561 
1562 	sva = *virt;
1563 	va = sva;
1564 	for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1565 		moea_kenter(mmu, va, pa_start);
1566 	*virt = va;
1567 	return (sva);
1568 }
1569 
1570 /*
1571  * Returns true if the pmap's pv is one of the first
1572  * 16 pvs linked to from this page.  This count may
1573  * be changed upwards or downwards in the future; it
1574  * is only necessary that true be returned for a small
1575  * subset of pmaps for proper page aging.
1576  */
1577 boolean_t
1578 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1579 {
1580         int loops;
1581 	struct pvo_entry *pvo;
1582 	boolean_t rv;
1583 
1584 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1585 	    ("moea_page_exists_quick: page %p is not managed", m));
1586 	loops = 0;
1587 	rv = FALSE;
1588 	rw_wlock(&pvh_global_lock);
1589 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1590 		if (pvo->pvo_pmap == pmap) {
1591 			rv = TRUE;
1592 			break;
1593 		}
1594 		if (++loops >= 16)
1595 			break;
1596 	}
1597 	rw_wunlock(&pvh_global_lock);
1598 	return (rv);
1599 }
1600 
1601 void
1602 moea_page_init(mmu_t mmu __unused, vm_page_t m)
1603 {
1604 
1605 	m->md.mdpg_attrs = 0;
1606 	m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
1607 	LIST_INIT(&m->md.mdpg_pvoh);
1608 }
1609 
1610 /*
1611  * Return the number of managed mappings to the given physical page
1612  * that are wired.
1613  */
1614 int
1615 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1616 {
1617 	struct pvo_entry *pvo;
1618 	int count;
1619 
1620 	count = 0;
1621 	if ((m->oflags & VPO_UNMANAGED) != 0)
1622 		return (count);
1623 	rw_wlock(&pvh_global_lock);
1624 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1625 		if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1626 			count++;
1627 	rw_wunlock(&pvh_global_lock);
1628 	return (count);
1629 }
1630 
1631 static u_int	moea_vsidcontext;
1632 
1633 void
1634 moea_pinit(mmu_t mmu, pmap_t pmap)
1635 {
1636 	int	i, mask;
1637 	u_int	entropy;
1638 
1639 	KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1640 	RB_INIT(&pmap->pmap_pvo);
1641 
1642 	entropy = 0;
1643 	__asm __volatile("mftb %0" : "=r"(entropy));
1644 
1645 	if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1646 	    == NULL) {
1647 		pmap->pmap_phys = pmap;
1648 	}
1649 
1650 
1651 	mtx_lock(&moea_vsid_mutex);
1652 	/*
1653 	 * Allocate some segment registers for this pmap.
1654 	 */
1655 	for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1656 		u_int	hash, n;
1657 
1658 		/*
1659 		 * Create a new value by mutiplying by a prime and adding in
1660 		 * entropy from the timebase register.  This is to make the
1661 		 * VSID more random so that the PT hash function collides
1662 		 * less often.  (Note that the prime casues gcc to do shifts
1663 		 * instead of a multiply.)
1664 		 */
1665 		moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1666 		hash = moea_vsidcontext & (NPMAPS - 1);
1667 		if (hash == 0)		/* 0 is special, avoid it */
1668 			continue;
1669 		n = hash >> 5;
1670 		mask = 1 << (hash & (VSID_NBPW - 1));
1671 		hash = (moea_vsidcontext & 0xfffff);
1672 		if (moea_vsid_bitmap[n] & mask) {	/* collision? */
1673 			/* anything free in this bucket? */
1674 			if (moea_vsid_bitmap[n] == 0xffffffff) {
1675 				entropy = (moea_vsidcontext >> 20);
1676 				continue;
1677 			}
1678 			i = ffs(~moea_vsid_bitmap[n]) - 1;
1679 			mask = 1 << i;
1680 			hash &= rounddown2(0xfffff, VSID_NBPW);
1681 			hash |= i;
1682 		}
1683 		KASSERT(!(moea_vsid_bitmap[n] & mask),
1684 		    ("Allocating in-use VSID group %#x\n", hash));
1685 		moea_vsid_bitmap[n] |= mask;
1686 		for (i = 0; i < 16; i++)
1687 			pmap->pm_sr[i] = VSID_MAKE(i, hash);
1688 		mtx_unlock(&moea_vsid_mutex);
1689 		return;
1690 	}
1691 
1692 	mtx_unlock(&moea_vsid_mutex);
1693 	panic("moea_pinit: out of segments");
1694 }
1695 
1696 /*
1697  * Initialize the pmap associated with process 0.
1698  */
1699 void
1700 moea_pinit0(mmu_t mmu, pmap_t pm)
1701 {
1702 
1703 	PMAP_LOCK_INIT(pm);
1704 	moea_pinit(mmu, pm);
1705 	bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1706 }
1707 
1708 /*
1709  * Set the physical protection on the specified range of this map as requested.
1710  */
1711 void
1712 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1713     vm_prot_t prot)
1714 {
1715 	struct	pvo_entry *pvo, *tpvo, key;
1716 	struct	pte *pt;
1717 
1718 	KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1719 	    ("moea_protect: non current pmap"));
1720 
1721 	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1722 		moea_remove(mmu, pm, sva, eva);
1723 		return;
1724 	}
1725 
1726 	rw_wlock(&pvh_global_lock);
1727 	PMAP_LOCK(pm);
1728 	key.pvo_vaddr = sva;
1729 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1730 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1731 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1732 
1733 		/*
1734 		 * Grab the PTE pointer before we diddle with the cached PTE
1735 		 * copy.
1736 		 */
1737 		pt = moea_pvo_to_pte(pvo, -1);
1738 		/*
1739 		 * Change the protection of the page.
1740 		 */
1741 		pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1742 		pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1743 
1744 		/*
1745 		 * If the PVO is in the page table, update that pte as well.
1746 		 */
1747 		if (pt != NULL) {
1748 			moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1749 			mtx_unlock(&moea_table_mutex);
1750 		}
1751 	}
1752 	rw_wunlock(&pvh_global_lock);
1753 	PMAP_UNLOCK(pm);
1754 }
1755 
1756 /*
1757  * Map a list of wired pages into kernel virtual address space.  This is
1758  * intended for temporary mappings which do not need page modification or
1759  * references recorded.  Existing mappings in the region are overwritten.
1760  */
1761 void
1762 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1763 {
1764 	vm_offset_t va;
1765 
1766 	va = sva;
1767 	while (count-- > 0) {
1768 		moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1769 		va += PAGE_SIZE;
1770 		m++;
1771 	}
1772 }
1773 
1774 /*
1775  * Remove page mappings from kernel virtual address space.  Intended for
1776  * temporary mappings entered by moea_qenter.
1777  */
1778 void
1779 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1780 {
1781 	vm_offset_t va;
1782 
1783 	va = sva;
1784 	while (count-- > 0) {
1785 		moea_kremove(mmu, va);
1786 		va += PAGE_SIZE;
1787 	}
1788 }
1789 
1790 void
1791 moea_release(mmu_t mmu, pmap_t pmap)
1792 {
1793         int idx, mask;
1794 
1795 	/*
1796 	 * Free segment register's VSID
1797 	 */
1798         if (pmap->pm_sr[0] == 0)
1799                 panic("moea_release");
1800 
1801 	mtx_lock(&moea_vsid_mutex);
1802         idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1803         mask = 1 << (idx % VSID_NBPW);
1804         idx /= VSID_NBPW;
1805         moea_vsid_bitmap[idx] &= ~mask;
1806 	mtx_unlock(&moea_vsid_mutex);
1807 }
1808 
1809 /*
1810  * Remove the given range of addresses from the specified map.
1811  */
1812 void
1813 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1814 {
1815 	struct	pvo_entry *pvo, *tpvo, key;
1816 
1817 	rw_wlock(&pvh_global_lock);
1818 	PMAP_LOCK(pm);
1819 	key.pvo_vaddr = sva;
1820 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1821 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1822 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1823 		moea_pvo_remove(pvo, -1);
1824 	}
1825 	PMAP_UNLOCK(pm);
1826 	rw_wunlock(&pvh_global_lock);
1827 }
1828 
1829 /*
1830  * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1831  * will reflect changes in pte's back to the vm_page.
1832  */
1833 void
1834 moea_remove_all(mmu_t mmu, vm_page_t m)
1835 {
1836 	struct  pvo_head *pvo_head;
1837 	struct	pvo_entry *pvo, *next_pvo;
1838 	pmap_t	pmap;
1839 
1840 	rw_wlock(&pvh_global_lock);
1841 	pvo_head = vm_page_to_pvoh(m);
1842 	for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1843 		next_pvo = LIST_NEXT(pvo, pvo_vlink);
1844 
1845 		pmap = pvo->pvo_pmap;
1846 		PMAP_LOCK(pmap);
1847 		moea_pvo_remove(pvo, -1);
1848 		PMAP_UNLOCK(pmap);
1849 	}
1850 	if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1851 		moea_attr_clear(m, PTE_CHG);
1852 		vm_page_dirty(m);
1853 	}
1854 	vm_page_aflag_clear(m, PGA_WRITEABLE);
1855 	rw_wunlock(&pvh_global_lock);
1856 }
1857 
1858 /*
1859  * Allocate a physical page of memory directly from the phys_avail map.
1860  * Can only be called from moea_bootstrap before avail start and end are
1861  * calculated.
1862  */
1863 static vm_offset_t
1864 moea_bootstrap_alloc(vm_size_t size, u_int align)
1865 {
1866 	vm_offset_t	s, e;
1867 	int		i, j;
1868 
1869 	size = round_page(size);
1870 	for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1871 		if (align != 0)
1872 			s = roundup2(phys_avail[i], align);
1873 		else
1874 			s = phys_avail[i];
1875 		e = s + size;
1876 
1877 		if (s < phys_avail[i] || e > phys_avail[i + 1])
1878 			continue;
1879 
1880 		if (s == phys_avail[i]) {
1881 			phys_avail[i] += size;
1882 		} else if (e == phys_avail[i + 1]) {
1883 			phys_avail[i + 1] -= size;
1884 		} else {
1885 			for (j = phys_avail_count * 2; j > i; j -= 2) {
1886 				phys_avail[j] = phys_avail[j - 2];
1887 				phys_avail[j + 1] = phys_avail[j - 1];
1888 			}
1889 
1890 			phys_avail[i + 3] = phys_avail[i + 1];
1891 			phys_avail[i + 1] = s;
1892 			phys_avail[i + 2] = e;
1893 			phys_avail_count++;
1894 		}
1895 
1896 		return (s);
1897 	}
1898 	panic("moea_bootstrap_alloc: could not allocate memory");
1899 }
1900 
1901 static void
1902 moea_syncicache(vm_paddr_t pa, vm_size_t len)
1903 {
1904 	__syncicache((void *)pa, len);
1905 }
1906 
1907 static int
1908 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1909     vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags)
1910 {
1911 	struct	pvo_entry *pvo;
1912 	u_int	sr;
1913 	int	first;
1914 	u_int	ptegidx;
1915 	int	i;
1916 	int     bootstrap;
1917 
1918 	moea_pvo_enter_calls++;
1919 	first = 0;
1920 	bootstrap = 0;
1921 
1922 	/*
1923 	 * Compute the PTE Group index.
1924 	 */
1925 	va &= ~ADDR_POFF;
1926 	sr = va_to_sr(pm->pm_sr, va);
1927 	ptegidx = va_to_pteg(sr, va);
1928 
1929 	/*
1930 	 * Remove any existing mapping for this page.  Reuse the pvo entry if
1931 	 * there is a mapping.
1932 	 */
1933 	mtx_lock(&moea_table_mutex);
1934 	LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1935 		if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1936 			if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1937 			    (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1938 			    (pte_lo & PTE_PP)) {
1939 				/*
1940 				 * The PTE is not changing.  Instead, this may
1941 				 * be a request to change the mapping's wired
1942 				 * attribute.
1943 				 */
1944 				mtx_unlock(&moea_table_mutex);
1945 				if ((flags & PVO_WIRED) != 0 &&
1946 				    (pvo->pvo_vaddr & PVO_WIRED) == 0) {
1947 					pvo->pvo_vaddr |= PVO_WIRED;
1948 					pm->pm_stats.wired_count++;
1949 				} else if ((flags & PVO_WIRED) == 0 &&
1950 				    (pvo->pvo_vaddr & PVO_WIRED) != 0) {
1951 					pvo->pvo_vaddr &= ~PVO_WIRED;
1952 					pm->pm_stats.wired_count--;
1953 				}
1954 				return (0);
1955 			}
1956 			moea_pvo_remove(pvo, -1);
1957 			break;
1958 		}
1959 	}
1960 
1961 	/*
1962 	 * If we aren't overwriting a mapping, try to allocate.
1963 	 */
1964 	if (moea_initialized) {
1965 		pvo = uma_zalloc(zone, M_NOWAIT);
1966 	} else {
1967 		if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1968 			panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1969 			      moea_bpvo_pool_index, BPVO_POOL_SIZE,
1970 			      BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1971 		}
1972 		pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1973 		moea_bpvo_pool_index++;
1974 		bootstrap = 1;
1975 	}
1976 
1977 	if (pvo == NULL) {
1978 		mtx_unlock(&moea_table_mutex);
1979 		return (ENOMEM);
1980 	}
1981 
1982 	moea_pvo_entries++;
1983 	pvo->pvo_vaddr = va;
1984 	pvo->pvo_pmap = pm;
1985 	LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1986 	pvo->pvo_vaddr &= ~ADDR_POFF;
1987 	if (flags & PVO_WIRED)
1988 		pvo->pvo_vaddr |= PVO_WIRED;
1989 	if (pvo_head != &moea_pvo_kunmanaged)
1990 		pvo->pvo_vaddr |= PVO_MANAGED;
1991 	if (bootstrap)
1992 		pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1993 
1994 	moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1995 
1996 	/*
1997 	 * Add to pmap list
1998 	 */
1999 	RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2000 
2001 	/*
2002 	 * Remember if the list was empty and therefore will be the first
2003 	 * item.
2004 	 */
2005 	if (LIST_FIRST(pvo_head) == NULL)
2006 		first = 1;
2007 	LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2008 
2009 	if (pvo->pvo_vaddr & PVO_WIRED)
2010 		pm->pm_stats.wired_count++;
2011 	pm->pm_stats.resident_count++;
2012 
2013 	i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2014 	KASSERT(i < 8, ("Invalid PTE index"));
2015 	if (i >= 0) {
2016 		PVO_PTEGIDX_SET(pvo, i);
2017 	} else {
2018 		panic("moea_pvo_enter: overflow");
2019 		moea_pte_overflow++;
2020 	}
2021 	mtx_unlock(&moea_table_mutex);
2022 
2023 	return (first ? ENOENT : 0);
2024 }
2025 
2026 static void
2027 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2028 {
2029 	struct	pte *pt;
2030 
2031 	/*
2032 	 * If there is an active pte entry, we need to deactivate it (and
2033 	 * save the ref & cfg bits).
2034 	 */
2035 	pt = moea_pvo_to_pte(pvo, pteidx);
2036 	if (pt != NULL) {
2037 		moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2038 		mtx_unlock(&moea_table_mutex);
2039 		PVO_PTEGIDX_CLR(pvo);
2040 	} else {
2041 		moea_pte_overflow--;
2042 	}
2043 
2044 	/*
2045 	 * Update our statistics.
2046 	 */
2047 	pvo->pvo_pmap->pm_stats.resident_count--;
2048 	if (pvo->pvo_vaddr & PVO_WIRED)
2049 		pvo->pvo_pmap->pm_stats.wired_count--;
2050 
2051 	/*
2052 	 * Save the REF/CHG bits into their cache if the page is managed.
2053 	 */
2054 	if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2055 		struct	vm_page *pg;
2056 
2057 		pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2058 		if (pg != NULL) {
2059 			moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2060 			    (PTE_REF | PTE_CHG));
2061 		}
2062 	}
2063 
2064 	/*
2065 	 * Remove this PVO from the PV and pmap lists.
2066 	 */
2067 	LIST_REMOVE(pvo, pvo_vlink);
2068 	RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2069 
2070 	/*
2071 	 * Remove this from the overflow list and return it to the pool
2072 	 * if we aren't going to reuse it.
2073 	 */
2074 	LIST_REMOVE(pvo, pvo_olink);
2075 	if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2076 		uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2077 		    moea_upvo_zone, pvo);
2078 	moea_pvo_entries--;
2079 	moea_pvo_remove_calls++;
2080 }
2081 
2082 static __inline int
2083 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2084 {
2085 	int	pteidx;
2086 
2087 	/*
2088 	 * We can find the actual pte entry without searching by grabbing
2089 	 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2090 	 * noticing the HID bit.
2091 	 */
2092 	pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2093 	if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2094 		pteidx ^= moea_pteg_mask * 8;
2095 
2096 	return (pteidx);
2097 }
2098 
2099 static struct pvo_entry *
2100 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2101 {
2102 	struct	pvo_entry *pvo;
2103 	int	ptegidx;
2104 	u_int	sr;
2105 
2106 	va &= ~ADDR_POFF;
2107 	sr = va_to_sr(pm->pm_sr, va);
2108 	ptegidx = va_to_pteg(sr, va);
2109 
2110 	mtx_lock(&moea_table_mutex);
2111 	LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2112 		if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2113 			if (pteidx_p)
2114 				*pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2115 			break;
2116 		}
2117 	}
2118 	mtx_unlock(&moea_table_mutex);
2119 
2120 	return (pvo);
2121 }
2122 
2123 static struct pte *
2124 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2125 {
2126 	struct	pte *pt;
2127 
2128 	/*
2129 	 * If we haven't been supplied the ptegidx, calculate it.
2130 	 */
2131 	if (pteidx == -1) {
2132 		int	ptegidx;
2133 		u_int	sr;
2134 
2135 		sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2136 		ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2137 		pteidx = moea_pvo_pte_index(pvo, ptegidx);
2138 	}
2139 
2140 	pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2141 	mtx_lock(&moea_table_mutex);
2142 
2143 	if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2144 		panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2145 		    "valid pte index", pvo);
2146 	}
2147 
2148 	if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2149 		panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2150 		    "pvo but no valid pte", pvo);
2151 	}
2152 
2153 	if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2154 		if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2155 			panic("moea_pvo_to_pte: pvo %p has valid pte in "
2156 			    "moea_pteg_table %p but invalid in pvo", pvo, pt);
2157 		}
2158 
2159 		if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2160 		    != 0) {
2161 			panic("moea_pvo_to_pte: pvo %p pte does not match "
2162 			    "pte %p in moea_pteg_table", pvo, pt);
2163 		}
2164 
2165 		mtx_assert(&moea_table_mutex, MA_OWNED);
2166 		return (pt);
2167 	}
2168 
2169 	if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2170 		panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2171 		    "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2172 	}
2173 
2174 	mtx_unlock(&moea_table_mutex);
2175 	return (NULL);
2176 }
2177 
2178 /*
2179  * XXX: THIS STUFF SHOULD BE IN pte.c?
2180  */
2181 int
2182 moea_pte_spill(vm_offset_t addr)
2183 {
2184 	struct	pvo_entry *source_pvo, *victim_pvo;
2185 	struct	pvo_entry *pvo;
2186 	int	ptegidx, i, j;
2187 	u_int	sr;
2188 	struct	pteg *pteg;
2189 	struct	pte *pt;
2190 
2191 	moea_pte_spills++;
2192 
2193 	sr = mfsrin(addr);
2194 	ptegidx = va_to_pteg(sr, addr);
2195 
2196 	/*
2197 	 * Have to substitute some entry.  Use the primary hash for this.
2198 	 * Use low bits of timebase as random generator.
2199 	 */
2200 	pteg = &moea_pteg_table[ptegidx];
2201 	mtx_lock(&moea_table_mutex);
2202 	__asm __volatile("mftb %0" : "=r"(i));
2203 	i &= 7;
2204 	pt = &pteg->pt[i];
2205 
2206 	source_pvo = NULL;
2207 	victim_pvo = NULL;
2208 	LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2209 		/*
2210 		 * We need to find a pvo entry for this address.
2211 		 */
2212 		if (source_pvo == NULL &&
2213 		    moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2214 		    pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2215 			/*
2216 			 * Now found an entry to be spilled into the pteg.
2217 			 * The PTE is now valid, so we know it's active.
2218 			 */
2219 			j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2220 
2221 			if (j >= 0) {
2222 				PVO_PTEGIDX_SET(pvo, j);
2223 				moea_pte_overflow--;
2224 				mtx_unlock(&moea_table_mutex);
2225 				return (1);
2226 			}
2227 
2228 			source_pvo = pvo;
2229 
2230 			if (victim_pvo != NULL)
2231 				break;
2232 		}
2233 
2234 		/*
2235 		 * We also need the pvo entry of the victim we are replacing
2236 		 * so save the R & C bits of the PTE.
2237 		 */
2238 		if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2239 		    moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2240 			victim_pvo = pvo;
2241 			if (source_pvo != NULL)
2242 				break;
2243 		}
2244 	}
2245 
2246 	if (source_pvo == NULL) {
2247 		mtx_unlock(&moea_table_mutex);
2248 		return (0);
2249 	}
2250 
2251 	if (victim_pvo == NULL) {
2252 		if ((pt->pte_hi & PTE_HID) == 0)
2253 			panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2254 			    "entry", pt);
2255 
2256 		/*
2257 		 * If this is a secondary PTE, we need to search it's primary
2258 		 * pvo bucket for the matching PVO.
2259 		 */
2260 		LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2261 		    pvo_olink) {
2262 			/*
2263 			 * We also need the pvo entry of the victim we are
2264 			 * replacing so save the R & C bits of the PTE.
2265 			 */
2266 			if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2267 				victim_pvo = pvo;
2268 				break;
2269 			}
2270 		}
2271 
2272 		if (victim_pvo == NULL)
2273 			panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2274 			    "entry", pt);
2275 	}
2276 
2277 	/*
2278 	 * We are invalidating the TLB entry for the EA we are replacing even
2279 	 * though it's valid.  If we don't, we lose any ref/chg bit changes
2280 	 * contained in the TLB entry.
2281 	 */
2282 	source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2283 
2284 	moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2285 	moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2286 
2287 	PVO_PTEGIDX_CLR(victim_pvo);
2288 	PVO_PTEGIDX_SET(source_pvo, i);
2289 	moea_pte_replacements++;
2290 
2291 	mtx_unlock(&moea_table_mutex);
2292 	return (1);
2293 }
2294 
2295 static __inline struct pvo_entry *
2296 moea_pte_spillable_ident(u_int ptegidx)
2297 {
2298 	struct	pte *pt;
2299 	struct	pvo_entry *pvo_walk, *pvo = NULL;
2300 
2301 	LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2302 		if (pvo_walk->pvo_vaddr & PVO_WIRED)
2303 			continue;
2304 
2305 		if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2306 			continue;
2307 
2308 		pt = moea_pvo_to_pte(pvo_walk, -1);
2309 
2310 		if (pt == NULL)
2311 			continue;
2312 
2313 		pvo = pvo_walk;
2314 
2315 		mtx_unlock(&moea_table_mutex);
2316 		if (!(pt->pte_lo & PTE_REF))
2317 			return (pvo_walk);
2318 	}
2319 
2320 	return (pvo);
2321 }
2322 
2323 static int
2324 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2325 {
2326 	struct	pte *pt;
2327 	struct	pvo_entry *victim_pvo;
2328 	int	i;
2329 	int	victim_idx;
2330 	u_int	pteg_bkpidx = ptegidx;
2331 
2332 	mtx_assert(&moea_table_mutex, MA_OWNED);
2333 
2334 	/*
2335 	 * First try primary hash.
2336 	 */
2337 	for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2338 		if ((pt->pte_hi & PTE_VALID) == 0) {
2339 			pvo_pt->pte_hi &= ~PTE_HID;
2340 			moea_pte_set(pt, pvo_pt);
2341 			return (i);
2342 		}
2343 	}
2344 
2345 	/*
2346 	 * Now try secondary hash.
2347 	 */
2348 	ptegidx ^= moea_pteg_mask;
2349 
2350 	for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2351 		if ((pt->pte_hi & PTE_VALID) == 0) {
2352 			pvo_pt->pte_hi |= PTE_HID;
2353 			moea_pte_set(pt, pvo_pt);
2354 			return (i);
2355 		}
2356 	}
2357 
2358 	/* Try again, but this time try to force a PTE out. */
2359 	ptegidx = pteg_bkpidx;
2360 
2361 	victim_pvo = moea_pte_spillable_ident(ptegidx);
2362 	if (victim_pvo == NULL) {
2363 		ptegidx ^= moea_pteg_mask;
2364 		victim_pvo = moea_pte_spillable_ident(ptegidx);
2365 	}
2366 
2367 	if (victim_pvo == NULL) {
2368 		panic("moea_pte_insert: overflow");
2369 		return (-1);
2370 	}
2371 
2372 	victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2373 
2374 	if (pteg_bkpidx == ptegidx)
2375 		pvo_pt->pte_hi &= ~PTE_HID;
2376 	else
2377 		pvo_pt->pte_hi |= PTE_HID;
2378 
2379 	/*
2380 	 * Synchronize the sacrifice PTE with its PVO, then mark both
2381 	 * invalid. The PVO will be reused when/if the VM system comes
2382 	 * here after a fault.
2383 	 */
2384 	pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2385 
2386 	if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2387 	    panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2388 
2389 	/*
2390 	 * Set the new PTE.
2391 	 */
2392 	moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2393 	PVO_PTEGIDX_CLR(victim_pvo);
2394 	moea_pte_overflow++;
2395 	moea_pte_set(pt, pvo_pt);
2396 
2397 	return (victim_idx & 7);
2398 }
2399 
2400 static boolean_t
2401 moea_query_bit(vm_page_t m, int ptebit)
2402 {
2403 	struct	pvo_entry *pvo;
2404 	struct	pte *pt;
2405 
2406 	rw_assert(&pvh_global_lock, RA_WLOCKED);
2407 	if (moea_attr_fetch(m) & ptebit)
2408 		return (TRUE);
2409 
2410 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2411 
2412 		/*
2413 		 * See if we saved the bit off.  If so, cache it and return
2414 		 * success.
2415 		 */
2416 		if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2417 			moea_attr_save(m, ptebit);
2418 			return (TRUE);
2419 		}
2420 	}
2421 
2422 	/*
2423 	 * No luck, now go through the hard part of looking at the PTEs
2424 	 * themselves.  Sync so that any pending REF/CHG bits are flushed to
2425 	 * the PTEs.
2426 	 */
2427 	powerpc_sync();
2428 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2429 
2430 		/*
2431 		 * See if this pvo has a valid PTE.  if so, fetch the
2432 		 * REF/CHG bits from the valid PTE.  If the appropriate
2433 		 * ptebit is set, cache it and return success.
2434 		 */
2435 		pt = moea_pvo_to_pte(pvo, -1);
2436 		if (pt != NULL) {
2437 			moea_pte_synch(pt, &pvo->pvo_pte.pte);
2438 			mtx_unlock(&moea_table_mutex);
2439 			if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2440 				moea_attr_save(m, ptebit);
2441 				return (TRUE);
2442 			}
2443 		}
2444 	}
2445 
2446 	return (FALSE);
2447 }
2448 
2449 static u_int
2450 moea_clear_bit(vm_page_t m, int ptebit)
2451 {
2452 	u_int	count;
2453 	struct	pvo_entry *pvo;
2454 	struct	pte *pt;
2455 
2456 	rw_assert(&pvh_global_lock, RA_WLOCKED);
2457 
2458 	/*
2459 	 * Clear the cached value.
2460 	 */
2461 	moea_attr_clear(m, ptebit);
2462 
2463 	/*
2464 	 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2465 	 * we can reset the right ones).  note that since the pvo entries and
2466 	 * list heads are accessed via BAT0 and are never placed in the page
2467 	 * table, we don't have to worry about further accesses setting the
2468 	 * REF/CHG bits.
2469 	 */
2470 	powerpc_sync();
2471 
2472 	/*
2473 	 * For each pvo entry, clear the pvo's ptebit.  If this pvo has a
2474 	 * valid pte clear the ptebit from the valid pte.
2475 	 */
2476 	count = 0;
2477 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2478 		pt = moea_pvo_to_pte(pvo, -1);
2479 		if (pt != NULL) {
2480 			moea_pte_synch(pt, &pvo->pvo_pte.pte);
2481 			if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2482 				count++;
2483 				moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2484 			}
2485 			mtx_unlock(&moea_table_mutex);
2486 		}
2487 		pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2488 	}
2489 
2490 	return (count);
2491 }
2492 
2493 /*
2494  * Return true if the physical range is encompassed by the battable[idx]
2495  */
2496 static int
2497 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size)
2498 {
2499 	u_int prot;
2500 	u_int32_t start;
2501 	u_int32_t end;
2502 	u_int32_t bat_ble;
2503 
2504 	/*
2505 	 * Return immediately if not a valid mapping
2506 	 */
2507 	if (!(battable[idx].batu & BAT_Vs))
2508 		return (EINVAL);
2509 
2510 	/*
2511 	 * The BAT entry must be cache-inhibited, guarded, and r/w
2512 	 * so it can function as an i/o page
2513 	 */
2514 	prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2515 	if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2516 		return (EPERM);
2517 
2518 	/*
2519 	 * The address should be within the BAT range. Assume that the
2520 	 * start address in the BAT has the correct alignment (thus
2521 	 * not requiring masking)
2522 	 */
2523 	start = battable[idx].batl & BAT_PBS;
2524 	bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2525 	end = start | (bat_ble << 15) | 0x7fff;
2526 
2527 	if ((pa < start) || ((pa + size) > end))
2528 		return (ERANGE);
2529 
2530 	return (0);
2531 }
2532 
2533 boolean_t
2534 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2535 {
2536 	int i;
2537 
2538 	/*
2539 	 * This currently does not work for entries that
2540 	 * overlap 256M BAT segments.
2541 	 */
2542 
2543 	for(i = 0; i < 16; i++)
2544 		if (moea_bat_mapped(i, pa, size) == 0)
2545 			return (0);
2546 
2547 	return (EFAULT);
2548 }
2549 
2550 /*
2551  * Map a set of physical memory pages into the kernel virtual
2552  * address space. Return a pointer to where it is mapped. This
2553  * routine is intended to be used for mapping device memory,
2554  * NOT real memory.
2555  */
2556 void *
2557 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2558 {
2559 
2560 	return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2561 }
2562 
2563 void *
2564 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2565 {
2566 	vm_offset_t va, tmpva, ppa, offset;
2567 	int i;
2568 
2569 	ppa = trunc_page(pa);
2570 	offset = pa & PAGE_MASK;
2571 	size = roundup(offset + size, PAGE_SIZE);
2572 
2573 	/*
2574 	 * If the physical address lies within a valid BAT table entry,
2575 	 * return the 1:1 mapping. This currently doesn't work
2576 	 * for regions that overlap 256M BAT segments.
2577 	 */
2578 	for (i = 0; i < 16; i++) {
2579 		if (moea_bat_mapped(i, pa, size) == 0)
2580 			return ((void *) pa);
2581 	}
2582 
2583 	va = kva_alloc(size);
2584 	if (!va)
2585 		panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2586 
2587 	for (tmpva = va; size > 0;) {
2588 		moea_kenter_attr(mmu, tmpva, ppa, ma);
2589 		tlbie(tmpva);
2590 		size -= PAGE_SIZE;
2591 		tmpva += PAGE_SIZE;
2592 		ppa += PAGE_SIZE;
2593 	}
2594 
2595 	return ((void *)(va + offset));
2596 }
2597 
2598 void
2599 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2600 {
2601 	vm_offset_t base, offset;
2602 
2603 	/*
2604 	 * If this is outside kernel virtual space, then it's a
2605 	 * battable entry and doesn't require unmapping
2606 	 */
2607 	if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2608 		base = trunc_page(va);
2609 		offset = va & PAGE_MASK;
2610 		size = roundup(offset + size, PAGE_SIZE);
2611 		kva_free(base, size);
2612 	}
2613 }
2614 
2615 static void
2616 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2617 {
2618 	struct pvo_entry *pvo;
2619 	vm_offset_t lim;
2620 	vm_paddr_t pa;
2621 	vm_size_t len;
2622 
2623 	PMAP_LOCK(pm);
2624 	while (sz > 0) {
2625 		lim = round_page(va);
2626 		len = MIN(lim - va, sz);
2627 		pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2628 		if (pvo != NULL) {
2629 			pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2630 			    (va & ADDR_POFF);
2631 			moea_syncicache(pa, len);
2632 		}
2633 		va += len;
2634 		sz -= len;
2635 	}
2636 	PMAP_UNLOCK(pm);
2637 }
2638 
2639 void
2640 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2641 {
2642 
2643 	*va = (void *)pa;
2644 }
2645 
2646 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2647 
2648 void
2649 moea_scan_init(mmu_t mmu)
2650 {
2651 	struct pvo_entry *pvo;
2652 	vm_offset_t va;
2653 	int i;
2654 
2655 	if (!do_minidump) {
2656 		/* Initialize phys. segments for dumpsys(). */
2657 		memset(&dump_map, 0, sizeof(dump_map));
2658 		mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
2659 		for (i = 0; i < pregions_sz; i++) {
2660 			dump_map[i].pa_start = pregions[i].mr_start;
2661 			dump_map[i].pa_size = pregions[i].mr_size;
2662 		}
2663 		return;
2664 	}
2665 
2666 	/* Virtual segments for minidumps: */
2667 	memset(&dump_map, 0, sizeof(dump_map));
2668 
2669 	/* 1st: kernel .data and .bss. */
2670 	dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2671 	dump_map[0].pa_size =
2672 	    round_page((uintptr_t)_end) - dump_map[0].pa_start;
2673 
2674 	/* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2675 	dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
2676 	dump_map[1].pa_size = round_page(msgbufp->msg_size);
2677 
2678 	/* 3rd: kernel VM. */
2679 	va = dump_map[1].pa_start + dump_map[1].pa_size;
2680 	/* Find start of next chunk (from va). */
2681 	while (va < virtual_end) {
2682 		/* Don't dump the buffer cache. */
2683 		if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2684 			va = kmi.buffer_eva;
2685 			continue;
2686 		}
2687 		pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
2688 		if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2689 			break;
2690 		va += PAGE_SIZE;
2691 	}
2692 	if (va < virtual_end) {
2693 		dump_map[2].pa_start = va;
2694 		va += PAGE_SIZE;
2695 		/* Find last page in chunk. */
2696 		while (va < virtual_end) {
2697 			/* Don't run into the buffer cache. */
2698 			if (va == kmi.buffer_sva)
2699 				break;
2700 			pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF,
2701 			    NULL);
2702 			if (pvo == NULL ||
2703 			    !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2704 				break;
2705 			va += PAGE_SIZE;
2706 		}
2707 		dump_map[2].pa_size = va - dump_map[2].pa_start;
2708 	}
2709 }
2710