1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/cpu.h> 141 #include <machine/platform.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/smp.h> 148 #include <machine/sr.h> 149 #include <machine/mmuvar.h> 150 #include <machine/trap.h> 151 152 #include "mmu_if.h" 153 154 #define MOEA_DEBUG 155 156 #define TODO panic("%s: not implemented", __func__); 157 158 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 159 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 160 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 161 162 struct ofw_map { 163 vm_offset_t om_va; 164 vm_size_t om_len; 165 vm_offset_t om_pa; 166 u_int om_mode; 167 }; 168 169 extern unsigned char _etext[]; 170 extern unsigned char _end[]; 171 172 /* 173 * Map of physical memory regions. 174 */ 175 static struct mem_region *regions; 176 static struct mem_region *pregions; 177 static u_int phys_avail_count; 178 static int regions_sz, pregions_sz; 179 static struct ofw_map *translations; 180 181 /* 182 * Lock for the pteg and pvo tables. 183 */ 184 struct mtx moea_table_mutex; 185 struct mtx moea_vsid_mutex; 186 187 /* tlbie instruction synchronization */ 188 static struct mtx tlbie_mtx; 189 190 /* 191 * PTEG data. 192 */ 193 static struct pteg *moea_pteg_table; 194 u_int moea_pteg_count; 195 u_int moea_pteg_mask; 196 197 /* 198 * PVO data. 199 */ 200 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 201 struct pvo_head moea_pvo_kunmanaged = 202 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 203 204 static struct rwlock_padalign pvh_global_lock; 205 206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 208 209 #define BPVO_POOL_SIZE 32768 210 static struct pvo_entry *moea_bpvo_pool; 211 static int moea_bpvo_pool_index = 0; 212 213 #define VSID_NBPW (sizeof(u_int32_t) * 8) 214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 215 216 static boolean_t moea_initialized = FALSE; 217 218 /* 219 * Statistics. 220 */ 221 u_int moea_pte_valid = 0; 222 u_int moea_pte_overflow = 0; 223 u_int moea_pte_replacements = 0; 224 u_int moea_pvo_entries = 0; 225 u_int moea_pvo_enter_calls = 0; 226 u_int moea_pvo_remove_calls = 0; 227 u_int moea_pte_spills = 0; 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 229 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 231 &moea_pte_overflow, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 233 &moea_pte_replacements, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 235 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 237 &moea_pvo_enter_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 239 &moea_pvo_remove_calls, 0, ""); 240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 241 &moea_pte_spills, 0, ""); 242 243 /* 244 * Allocate physical memory for use in moea_bootstrap. 245 */ 246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 247 248 /* 249 * PTE calls. 250 */ 251 static int moea_pte_insert(u_int, struct pte *); 252 253 /* 254 * PVO calls. 255 */ 256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 257 vm_offset_t, vm_paddr_t, u_int, int); 258 static void moea_pvo_remove(struct pvo_entry *, int); 259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 261 262 /* 263 * Utility routines. 264 */ 265 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 266 vm_prot_t, u_int, int8_t); 267 static void moea_syncicache(vm_paddr_t, vm_size_t); 268 static boolean_t moea_query_bit(vm_page_t, int); 269 static u_int moea_clear_bit(vm_page_t, int); 270 static void moea_kremove(mmu_t, vm_offset_t); 271 int moea_pte_spill(vm_offset_t); 272 273 /* 274 * Kernel MMU interface 275 */ 276 void moea_clear_modify(mmu_t, vm_page_t); 277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 278 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 279 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 280 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 281 int8_t); 282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 287 void moea_init(mmu_t); 288 boolean_t moea_is_modified(mmu_t, vm_page_t); 289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 boolean_t moea_is_referenced(mmu_t, vm_page_t); 291 int moea_ts_referenced(mmu_t, vm_page_t); 292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 void moea_page_init(mmu_t, vm_page_t); 295 int moea_page_wired_mappings(mmu_t, vm_page_t); 296 void moea_pinit(mmu_t, pmap_t); 297 void moea_pinit0(mmu_t, pmap_t); 298 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 299 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 300 void moea_qremove(mmu_t, vm_offset_t, int); 301 void moea_release(mmu_t, pmap_t); 302 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 303 void moea_remove_all(mmu_t, vm_page_t); 304 void moea_remove_write(mmu_t, vm_page_t); 305 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 306 void moea_zero_page(mmu_t, vm_page_t); 307 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 308 void moea_activate(mmu_t, struct thread *); 309 void moea_deactivate(mmu_t, struct thread *); 310 void moea_cpu_bootstrap(mmu_t, int); 311 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 312 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 313 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 314 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 315 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 316 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 317 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 318 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 319 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 320 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 321 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 322 void moea_scan_init(mmu_t mmu); 323 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 324 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 325 static int moea_map_user_ptr(mmu_t mmu, pmap_t pm, 326 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 327 static int moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 328 int *is_user, vm_offset_t *decoded_addr); 329 330 331 static mmu_method_t moea_methods[] = { 332 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 333 MMUMETHOD(mmu_copy_page, moea_copy_page), 334 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 335 MMUMETHOD(mmu_enter, moea_enter), 336 MMUMETHOD(mmu_enter_object, moea_enter_object), 337 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 338 MMUMETHOD(mmu_extract, moea_extract), 339 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 340 MMUMETHOD(mmu_init, moea_init), 341 MMUMETHOD(mmu_is_modified, moea_is_modified), 342 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 343 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 344 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 345 MMUMETHOD(mmu_map, moea_map), 346 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 347 MMUMETHOD(mmu_page_init, moea_page_init), 348 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 349 MMUMETHOD(mmu_pinit, moea_pinit), 350 MMUMETHOD(mmu_pinit0, moea_pinit0), 351 MMUMETHOD(mmu_protect, moea_protect), 352 MMUMETHOD(mmu_qenter, moea_qenter), 353 MMUMETHOD(mmu_qremove, moea_qremove), 354 MMUMETHOD(mmu_release, moea_release), 355 MMUMETHOD(mmu_remove, moea_remove), 356 MMUMETHOD(mmu_remove_all, moea_remove_all), 357 MMUMETHOD(mmu_remove_write, moea_remove_write), 358 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 359 MMUMETHOD(mmu_unwire, moea_unwire), 360 MMUMETHOD(mmu_zero_page, moea_zero_page), 361 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 362 MMUMETHOD(mmu_activate, moea_activate), 363 MMUMETHOD(mmu_deactivate, moea_deactivate), 364 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 365 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 366 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 370 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 371 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 372 MMUMETHOD(mmu_mapdev, moea_mapdev), 373 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 374 MMUMETHOD(mmu_kextract, moea_kextract), 375 MMUMETHOD(mmu_kenter, moea_kenter), 376 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378 MMUMETHOD(mmu_scan_init, moea_scan_init), 379 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 380 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr), 381 MMUMETHOD(mmu_decode_kernel_ptr, moea_decode_kernel_ptr), 382 383 { 0, 0 } 384 }; 385 386 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 387 388 static __inline uint32_t 389 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 390 { 391 uint32_t pte_lo; 392 int i; 393 394 if (ma != VM_MEMATTR_DEFAULT) { 395 switch (ma) { 396 case VM_MEMATTR_UNCACHEABLE: 397 return (PTE_I | PTE_G); 398 case VM_MEMATTR_CACHEABLE: 399 return (PTE_M); 400 case VM_MEMATTR_WRITE_COMBINING: 401 case VM_MEMATTR_WRITE_BACK: 402 case VM_MEMATTR_PREFETCHABLE: 403 return (PTE_I); 404 case VM_MEMATTR_WRITE_THROUGH: 405 return (PTE_W | PTE_M); 406 } 407 } 408 409 /* 410 * Assume the page is cache inhibited and access is guarded unless 411 * it's in our available memory array. 412 */ 413 pte_lo = PTE_I | PTE_G; 414 for (i = 0; i < pregions_sz; i++) { 415 if ((pa >= pregions[i].mr_start) && 416 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 417 pte_lo = PTE_M; 418 break; 419 } 420 } 421 422 return pte_lo; 423 } 424 425 static void 426 tlbie(vm_offset_t va) 427 { 428 429 mtx_lock_spin(&tlbie_mtx); 430 __asm __volatile("ptesync"); 431 __asm __volatile("tlbie %0" :: "r"(va)); 432 __asm __volatile("eieio; tlbsync; ptesync"); 433 mtx_unlock_spin(&tlbie_mtx); 434 } 435 436 static void 437 tlbia(void) 438 { 439 vm_offset_t va; 440 441 for (va = 0; va < 0x00040000; va += 0x00001000) { 442 __asm __volatile("tlbie %0" :: "r"(va)); 443 powerpc_sync(); 444 } 445 __asm __volatile("tlbsync"); 446 powerpc_sync(); 447 } 448 449 static __inline int 450 va_to_sr(u_int *sr, vm_offset_t va) 451 { 452 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 453 } 454 455 static __inline u_int 456 va_to_pteg(u_int sr, vm_offset_t addr) 457 { 458 u_int hash; 459 460 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 461 ADDR_PIDX_SHFT); 462 return (hash & moea_pteg_mask); 463 } 464 465 static __inline struct pvo_head * 466 vm_page_to_pvoh(vm_page_t m) 467 { 468 469 return (&m->md.mdpg_pvoh); 470 } 471 472 static __inline void 473 moea_attr_clear(vm_page_t m, int ptebit) 474 { 475 476 rw_assert(&pvh_global_lock, RA_WLOCKED); 477 m->md.mdpg_attrs &= ~ptebit; 478 } 479 480 static __inline int 481 moea_attr_fetch(vm_page_t m) 482 { 483 484 return (m->md.mdpg_attrs); 485 } 486 487 static __inline void 488 moea_attr_save(vm_page_t m, int ptebit) 489 { 490 491 rw_assert(&pvh_global_lock, RA_WLOCKED); 492 m->md.mdpg_attrs |= ptebit; 493 } 494 495 static __inline int 496 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 497 { 498 if (pt->pte_hi == pvo_pt->pte_hi) 499 return (1); 500 501 return (0); 502 } 503 504 static __inline int 505 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 506 { 507 return (pt->pte_hi & ~PTE_VALID) == 508 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 509 ((va >> ADDR_API_SHFT) & PTE_API) | which); 510 } 511 512 static __inline void 513 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 514 { 515 516 mtx_assert(&moea_table_mutex, MA_OWNED); 517 518 /* 519 * Construct a PTE. Default to IMB initially. Valid bit only gets 520 * set when the real pte is set in memory. 521 * 522 * Note: Don't set the valid bit for correct operation of tlb update. 523 */ 524 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 525 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 526 pt->pte_lo = pte_lo; 527 } 528 529 static __inline void 530 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 531 { 532 533 mtx_assert(&moea_table_mutex, MA_OWNED); 534 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 535 } 536 537 static __inline void 538 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 539 { 540 541 mtx_assert(&moea_table_mutex, MA_OWNED); 542 543 /* 544 * As shown in Section 7.6.3.2.3 545 */ 546 pt->pte_lo &= ~ptebit; 547 tlbie(va); 548 } 549 550 static __inline void 551 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 552 { 553 554 mtx_assert(&moea_table_mutex, MA_OWNED); 555 pvo_pt->pte_hi |= PTE_VALID; 556 557 /* 558 * Update the PTE as defined in section 7.6.3.1. 559 * Note that the REF/CHG bits are from pvo_pt and thus should have 560 * been saved so this routine can restore them (if desired). 561 */ 562 pt->pte_lo = pvo_pt->pte_lo; 563 powerpc_sync(); 564 pt->pte_hi = pvo_pt->pte_hi; 565 powerpc_sync(); 566 moea_pte_valid++; 567 } 568 569 static __inline void 570 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 571 { 572 573 mtx_assert(&moea_table_mutex, MA_OWNED); 574 pvo_pt->pte_hi &= ~PTE_VALID; 575 576 /* 577 * Force the reg & chg bits back into the PTEs. 578 */ 579 powerpc_sync(); 580 581 /* 582 * Invalidate the pte. 583 */ 584 pt->pte_hi &= ~PTE_VALID; 585 586 tlbie(va); 587 588 /* 589 * Save the reg & chg bits. 590 */ 591 moea_pte_synch(pt, pvo_pt); 592 moea_pte_valid--; 593 } 594 595 static __inline void 596 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 597 { 598 599 /* 600 * Invalidate the PTE 601 */ 602 moea_pte_unset(pt, pvo_pt, va); 603 moea_pte_set(pt, pvo_pt); 604 } 605 606 /* 607 * Quick sort callout for comparing memory regions. 608 */ 609 static int om_cmp(const void *a, const void *b); 610 611 static int 612 om_cmp(const void *a, const void *b) 613 { 614 const struct ofw_map *mapa; 615 const struct ofw_map *mapb; 616 617 mapa = a; 618 mapb = b; 619 if (mapa->om_pa < mapb->om_pa) 620 return (-1); 621 else if (mapa->om_pa > mapb->om_pa) 622 return (1); 623 else 624 return (0); 625 } 626 627 void 628 moea_cpu_bootstrap(mmu_t mmup, int ap) 629 { 630 u_int sdr; 631 int i; 632 633 if (ap) { 634 powerpc_sync(); 635 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 636 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 637 isync(); 638 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 639 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 640 isync(); 641 } 642 643 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 644 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 645 isync(); 646 647 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 648 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 649 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 650 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 651 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 652 isync(); 653 654 for (i = 0; i < 16; i++) 655 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 656 powerpc_sync(); 657 658 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 659 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 660 isync(); 661 662 tlbia(); 663 } 664 665 void 666 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 667 { 668 ihandle_t mmui; 669 phandle_t chosen, mmu; 670 int sz; 671 int i, j; 672 vm_size_t size, physsz, hwphyssz; 673 vm_offset_t pa, va, off; 674 void *dpcpu; 675 register_t msr; 676 677 /* 678 * Set up BAT0 to map the lowest 256 MB area 679 */ 680 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 681 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 682 683 /* 684 * Map PCI memory space. 685 */ 686 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 687 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 688 689 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 690 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 691 692 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 693 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 694 695 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 696 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 697 698 /* 699 * Map obio devices. 700 */ 701 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 702 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 703 704 /* 705 * Use an IBAT and a DBAT to map the bottom segment of memory 706 * where we are. Turn off instruction relocation temporarily 707 * to prevent faults while reprogramming the IBAT. 708 */ 709 msr = mfmsr(); 710 mtmsr(msr & ~PSL_IR); 711 __asm (".balign 32; \n" 712 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 713 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 714 :: "r"(battable[0].batu), "r"(battable[0].batl)); 715 mtmsr(msr); 716 717 /* map pci space */ 718 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 719 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 720 isync(); 721 722 /* set global direct map flag */ 723 hw_direct_map = 1; 724 725 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 726 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 727 728 for (i = 0; i < pregions_sz; i++) { 729 vm_offset_t pa; 730 vm_offset_t end; 731 732 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 733 pregions[i].mr_start, 734 pregions[i].mr_start + pregions[i].mr_size, 735 pregions[i].mr_size); 736 /* 737 * Install entries into the BAT table to allow all 738 * of physmem to be convered by on-demand BAT entries. 739 * The loop will sometimes set the same battable element 740 * twice, but that's fine since they won't be used for 741 * a while yet. 742 */ 743 pa = pregions[i].mr_start & 0xf0000000; 744 end = pregions[i].mr_start + pregions[i].mr_size; 745 do { 746 u_int n = pa >> ADDR_SR_SHFT; 747 748 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 749 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 750 pa += SEGMENT_LENGTH; 751 } while (pa < end); 752 } 753 754 if (PHYS_AVAIL_ENTRIES < regions_sz) 755 panic("moea_bootstrap: phys_avail too small"); 756 757 phys_avail_count = 0; 758 physsz = 0; 759 hwphyssz = 0; 760 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 761 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 762 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 763 regions[i].mr_start + regions[i].mr_size, 764 regions[i].mr_size); 765 if (hwphyssz != 0 && 766 (physsz + regions[i].mr_size) >= hwphyssz) { 767 if (physsz < hwphyssz) { 768 phys_avail[j] = regions[i].mr_start; 769 phys_avail[j + 1] = regions[i].mr_start + 770 hwphyssz - physsz; 771 physsz = hwphyssz; 772 phys_avail_count++; 773 } 774 break; 775 } 776 phys_avail[j] = regions[i].mr_start; 777 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 778 phys_avail_count++; 779 physsz += regions[i].mr_size; 780 } 781 782 /* Check for overlap with the kernel and exception vectors */ 783 for (j = 0; j < 2*phys_avail_count; j+=2) { 784 if (phys_avail[j] < EXC_LAST) 785 phys_avail[j] += EXC_LAST; 786 787 if (kernelstart >= phys_avail[j] && 788 kernelstart < phys_avail[j+1]) { 789 if (kernelend < phys_avail[j+1]) { 790 phys_avail[2*phys_avail_count] = 791 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 phys_avail[2*phys_avail_count + 1] = 793 phys_avail[j+1]; 794 phys_avail_count++; 795 } 796 797 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 798 } 799 800 if (kernelend >= phys_avail[j] && 801 kernelend < phys_avail[j+1]) { 802 if (kernelstart > phys_avail[j]) { 803 phys_avail[2*phys_avail_count] = phys_avail[j]; 804 phys_avail[2*phys_avail_count + 1] = 805 kernelstart & ~PAGE_MASK; 806 phys_avail_count++; 807 } 808 809 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 810 } 811 } 812 813 physmem = btoc(physsz); 814 815 /* 816 * Allocate PTEG table. 817 */ 818 #ifdef PTEGCOUNT 819 moea_pteg_count = PTEGCOUNT; 820 #else 821 moea_pteg_count = 0x1000; 822 823 while (moea_pteg_count < physmem) 824 moea_pteg_count <<= 1; 825 826 moea_pteg_count >>= 1; 827 #endif /* PTEGCOUNT */ 828 829 size = moea_pteg_count * sizeof(struct pteg); 830 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 831 size); 832 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 833 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 834 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 835 moea_pteg_mask = moea_pteg_count - 1; 836 837 /* 838 * Allocate pv/overflow lists. 839 */ 840 size = sizeof(struct pvo_head) * moea_pteg_count; 841 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 842 PAGE_SIZE); 843 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 844 for (i = 0; i < moea_pteg_count; i++) 845 LIST_INIT(&moea_pvo_table[i]); 846 847 /* 848 * Initialize the lock that synchronizes access to the pteg and pvo 849 * tables. 850 */ 851 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 852 MTX_RECURSE); 853 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 854 855 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 856 857 /* 858 * Initialise the unmanaged pvo pool. 859 */ 860 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 861 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 862 moea_bpvo_pool_index = 0; 863 864 /* 865 * Make sure kernel vsid is allocated as well as VSID 0. 866 */ 867 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 868 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 869 moea_vsid_bitmap[0] |= 1; 870 871 /* 872 * Initialize the kernel pmap (which is statically allocated). 873 */ 874 PMAP_LOCK_INIT(kernel_pmap); 875 for (i = 0; i < 16; i++) 876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 877 CPU_FILL(&kernel_pmap->pm_active); 878 RB_INIT(&kernel_pmap->pmap_pvo); 879 880 /* 881 * Initialize the global pv list lock. 882 */ 883 rw_init(&pvh_global_lock, "pmap pv global"); 884 885 /* 886 * Set up the Open Firmware mappings 887 */ 888 chosen = OF_finddevice("/chosen"); 889 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 890 (mmu = OF_instance_to_package(mmui)) != -1 && 891 (sz = OF_getproplen(mmu, "translations")) != -1) { 892 translations = NULL; 893 for (i = 0; phys_avail[i] != 0; i += 2) { 894 if (phys_avail[i + 1] >= sz) { 895 translations = (struct ofw_map *)phys_avail[i]; 896 break; 897 } 898 } 899 if (translations == NULL) 900 panic("moea_bootstrap: no space to copy translations"); 901 bzero(translations, sz); 902 if (OF_getprop(mmu, "translations", translations, sz) == -1) 903 panic("moea_bootstrap: can't get ofw translations"); 904 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 905 sz /= sizeof(*translations); 906 qsort(translations, sz, sizeof (*translations), om_cmp); 907 for (i = 0; i < sz; i++) { 908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 909 translations[i].om_pa, translations[i].om_va, 910 translations[i].om_len); 911 912 /* 913 * If the mapping is 1:1, let the RAM and device 914 * on-demand BAT tables take care of the translation. 915 */ 916 if (translations[i].om_va == translations[i].om_pa) 917 continue; 918 919 /* Enter the pages */ 920 for (off = 0; off < translations[i].om_len; 921 off += PAGE_SIZE) 922 moea_kenter(mmup, translations[i].om_va + off, 923 translations[i].om_pa + off); 924 } 925 } 926 927 /* 928 * Calculate the last available physical address. 929 */ 930 for (i = 0; phys_avail[i + 2] != 0; i += 2) 931 ; 932 Maxmem = powerpc_btop(phys_avail[i + 1]); 933 934 moea_cpu_bootstrap(mmup,0); 935 mtmsr(mfmsr() | PSL_DR | PSL_IR); 936 pmap_bootstrapped++; 937 938 /* 939 * Set the start and end of kva. 940 */ 941 virtual_avail = VM_MIN_KERNEL_ADDRESS; 942 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 943 944 /* 945 * Allocate a kernel stack with a guard page for thread0 and map it 946 * into the kernel page map. 947 */ 948 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 949 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 950 virtual_avail = va + kstack_pages * PAGE_SIZE; 951 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 952 thread0.td_kstack = va; 953 thread0.td_kstack_pages = kstack_pages; 954 for (i = 0; i < kstack_pages; i++) { 955 moea_kenter(mmup, va, pa); 956 pa += PAGE_SIZE; 957 va += PAGE_SIZE; 958 } 959 960 /* 961 * Allocate virtual address space for the message buffer. 962 */ 963 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 964 msgbufp = (struct msgbuf *)virtual_avail; 965 va = virtual_avail; 966 virtual_avail += round_page(msgbufsize); 967 while (va < virtual_avail) { 968 moea_kenter(mmup, va, pa); 969 pa += PAGE_SIZE; 970 va += PAGE_SIZE; 971 } 972 973 /* 974 * Allocate virtual address space for the dynamic percpu area. 975 */ 976 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 977 dpcpu = (void *)virtual_avail; 978 va = virtual_avail; 979 virtual_avail += DPCPU_SIZE; 980 while (va < virtual_avail) { 981 moea_kenter(mmup, va, pa); 982 pa += PAGE_SIZE; 983 va += PAGE_SIZE; 984 } 985 dpcpu_init(dpcpu, 0); 986 } 987 988 /* 989 * Activate a user pmap. The pmap must be activated before it's address 990 * space can be accessed in any way. 991 */ 992 void 993 moea_activate(mmu_t mmu, struct thread *td) 994 { 995 pmap_t pm, pmr; 996 997 /* 998 * Load all the data we need up front to encourage the compiler to 999 * not issue any loads while we have interrupts disabled below. 1000 */ 1001 pm = &td->td_proc->p_vmspace->vm_pmap; 1002 pmr = pm->pmap_phys; 1003 1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1005 PCPU_SET(curpmap, pmr); 1006 1007 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1008 } 1009 1010 void 1011 moea_deactivate(mmu_t mmu, struct thread *td) 1012 { 1013 pmap_t pm; 1014 1015 pm = &td->td_proc->p_vmspace->vm_pmap; 1016 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1017 PCPU_SET(curpmap, NULL); 1018 } 1019 1020 void 1021 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1022 { 1023 struct pvo_entry key, *pvo; 1024 1025 PMAP_LOCK(pm); 1026 key.pvo_vaddr = sva; 1027 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1028 pvo != NULL && PVO_VADDR(pvo) < eva; 1029 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1030 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1031 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1032 pvo->pvo_vaddr &= ~PVO_WIRED; 1033 pm->pm_stats.wired_count--; 1034 } 1035 PMAP_UNLOCK(pm); 1036 } 1037 1038 void 1039 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1040 { 1041 vm_offset_t dst; 1042 vm_offset_t src; 1043 1044 dst = VM_PAGE_TO_PHYS(mdst); 1045 src = VM_PAGE_TO_PHYS(msrc); 1046 1047 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1048 } 1049 1050 void 1051 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1052 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1053 { 1054 void *a_cp, *b_cp; 1055 vm_offset_t a_pg_offset, b_pg_offset; 1056 int cnt; 1057 1058 while (xfersize > 0) { 1059 a_pg_offset = a_offset & PAGE_MASK; 1060 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1061 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1062 a_pg_offset; 1063 b_pg_offset = b_offset & PAGE_MASK; 1064 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1065 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1066 b_pg_offset; 1067 bcopy(a_cp, b_cp, cnt); 1068 a_offset += cnt; 1069 b_offset += cnt; 1070 xfersize -= cnt; 1071 } 1072 } 1073 1074 /* 1075 * Zero a page of physical memory by temporarily mapping it into the tlb. 1076 */ 1077 void 1078 moea_zero_page(mmu_t mmu, vm_page_t m) 1079 { 1080 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1081 1082 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1083 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1084 } 1085 1086 void 1087 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1088 { 1089 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1090 void *va = (void *)(pa + off); 1091 1092 bzero(va, size); 1093 } 1094 1095 vm_offset_t 1096 moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1097 { 1098 1099 return (VM_PAGE_TO_PHYS(m)); 1100 } 1101 1102 void 1103 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1104 { 1105 } 1106 1107 /* 1108 * Map the given physical page at the specified virtual address in the 1109 * target pmap with the protection requested. If specified the page 1110 * will be wired down. 1111 */ 1112 int 1113 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1114 u_int flags, int8_t psind) 1115 { 1116 int error; 1117 1118 for (;;) { 1119 rw_wlock(&pvh_global_lock); 1120 PMAP_LOCK(pmap); 1121 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1122 rw_wunlock(&pvh_global_lock); 1123 PMAP_UNLOCK(pmap); 1124 if (error != ENOMEM) 1125 return (KERN_SUCCESS); 1126 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1127 return (KERN_RESOURCE_SHORTAGE); 1128 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1129 vm_wait(NULL); 1130 } 1131 } 1132 1133 /* 1134 * Map the given physical page at the specified virtual address in the 1135 * target pmap with the protection requested. If specified the page 1136 * will be wired down. 1137 * 1138 * The global pvh and pmap must be locked. 1139 */ 1140 static int 1141 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1142 u_int flags, int8_t psind __unused) 1143 { 1144 struct pvo_head *pvo_head; 1145 uma_zone_t zone; 1146 u_int pte_lo, pvo_flags; 1147 int error; 1148 1149 if (pmap_bootstrapped) 1150 rw_assert(&pvh_global_lock, RA_WLOCKED); 1151 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1152 if ((m->oflags & VPO_UNMANAGED) == 0) { 1153 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1154 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1155 else 1156 VM_OBJECT_ASSERT_LOCKED(m->object); 1157 } 1158 1159 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1160 pvo_head = &moea_pvo_kunmanaged; 1161 zone = moea_upvo_zone; 1162 pvo_flags = 0; 1163 } else { 1164 pvo_head = vm_page_to_pvoh(m); 1165 zone = moea_mpvo_zone; 1166 pvo_flags = PVO_MANAGED; 1167 } 1168 1169 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1170 1171 if (prot & VM_PROT_WRITE) { 1172 pte_lo |= PTE_BW; 1173 if (pmap_bootstrapped && 1174 (m->oflags & VPO_UNMANAGED) == 0) 1175 vm_page_aflag_set(m, PGA_WRITEABLE); 1176 } else 1177 pte_lo |= PTE_BR; 1178 1179 if ((flags & PMAP_ENTER_WIRED) != 0) 1180 pvo_flags |= PVO_WIRED; 1181 1182 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1183 pte_lo, pvo_flags); 1184 1185 /* 1186 * Flush the real page from the instruction cache. This has be done 1187 * for all user mappings to prevent information leakage via the 1188 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1189 * mapping for a page. 1190 */ 1191 if (pmap != kernel_pmap && error == ENOENT && 1192 (pte_lo & (PTE_I | PTE_G)) == 0) 1193 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1194 1195 return (error); 1196 } 1197 1198 /* 1199 * Maps a sequence of resident pages belonging to the same object. 1200 * The sequence begins with the given page m_start. This page is 1201 * mapped at the given virtual address start. Each subsequent page is 1202 * mapped at a virtual address that is offset from start by the same 1203 * amount as the page is offset from m_start within the object. The 1204 * last page in the sequence is the page with the largest offset from 1205 * m_start that can be mapped at a virtual address less than the given 1206 * virtual address end. Not every virtual page between start and end 1207 * is mapped; only those for which a resident page exists with the 1208 * corresponding offset from m_start are mapped. 1209 */ 1210 void 1211 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1212 vm_page_t m_start, vm_prot_t prot) 1213 { 1214 vm_page_t m; 1215 vm_pindex_t diff, psize; 1216 1217 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1218 1219 psize = atop(end - start); 1220 m = m_start; 1221 rw_wlock(&pvh_global_lock); 1222 PMAP_LOCK(pm); 1223 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1224 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1225 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_QUICK_LOCKED, 1226 0); 1227 m = TAILQ_NEXT(m, listq); 1228 } 1229 rw_wunlock(&pvh_global_lock); 1230 PMAP_UNLOCK(pm); 1231 } 1232 1233 void 1234 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1235 vm_prot_t prot) 1236 { 1237 1238 rw_wlock(&pvh_global_lock); 1239 PMAP_LOCK(pm); 1240 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1241 PMAP_ENTER_QUICK_LOCKED, 0); 1242 rw_wunlock(&pvh_global_lock); 1243 PMAP_UNLOCK(pm); 1244 } 1245 1246 vm_paddr_t 1247 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1248 { 1249 struct pvo_entry *pvo; 1250 vm_paddr_t pa; 1251 1252 PMAP_LOCK(pm); 1253 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1254 if (pvo == NULL) 1255 pa = 0; 1256 else 1257 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1258 PMAP_UNLOCK(pm); 1259 return (pa); 1260 } 1261 1262 /* 1263 * Atomically extract and hold the physical page with the given 1264 * pmap and virtual address pair if that mapping permits the given 1265 * protection. 1266 */ 1267 vm_page_t 1268 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1269 { 1270 struct pvo_entry *pvo; 1271 vm_page_t m; 1272 1273 m = NULL; 1274 PMAP_LOCK(pmap); 1275 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1276 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1277 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1278 (prot & VM_PROT_WRITE) == 0)) { 1279 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1280 if (!vm_page_wire_mapped(m)) 1281 m = NULL; 1282 } 1283 PMAP_UNLOCK(pmap); 1284 return (m); 1285 } 1286 1287 void 1288 moea_init(mmu_t mmu) 1289 { 1290 1291 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1292 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1293 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1294 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1295 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1296 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1297 moea_initialized = TRUE; 1298 } 1299 1300 boolean_t 1301 moea_is_referenced(mmu_t mmu, vm_page_t m) 1302 { 1303 boolean_t rv; 1304 1305 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1306 ("moea_is_referenced: page %p is not managed", m)); 1307 rw_wlock(&pvh_global_lock); 1308 rv = moea_query_bit(m, PTE_REF); 1309 rw_wunlock(&pvh_global_lock); 1310 return (rv); 1311 } 1312 1313 boolean_t 1314 moea_is_modified(mmu_t mmu, vm_page_t m) 1315 { 1316 boolean_t rv; 1317 1318 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1319 ("moea_is_modified: page %p is not managed", m)); 1320 1321 /* 1322 * If the page is not busied then this check is racy. 1323 */ 1324 if (!pmap_page_is_write_mapped(m)) 1325 return (FALSE); 1326 1327 rw_wlock(&pvh_global_lock); 1328 rv = moea_query_bit(m, PTE_CHG); 1329 rw_wunlock(&pvh_global_lock); 1330 return (rv); 1331 } 1332 1333 boolean_t 1334 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1335 { 1336 struct pvo_entry *pvo; 1337 boolean_t rv; 1338 1339 PMAP_LOCK(pmap); 1340 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1341 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1342 PMAP_UNLOCK(pmap); 1343 return (rv); 1344 } 1345 1346 void 1347 moea_clear_modify(mmu_t mmu, vm_page_t m) 1348 { 1349 1350 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1351 ("moea_clear_modify: page %p is not managed", m)); 1352 vm_page_assert_busied(m); 1353 1354 if (!pmap_page_is_write_mapped(m)) 1355 return; 1356 rw_wlock(&pvh_global_lock); 1357 moea_clear_bit(m, PTE_CHG); 1358 rw_wunlock(&pvh_global_lock); 1359 } 1360 1361 /* 1362 * Clear the write and modified bits in each of the given page's mappings. 1363 */ 1364 void 1365 moea_remove_write(mmu_t mmu, vm_page_t m) 1366 { 1367 struct pvo_entry *pvo; 1368 struct pte *pt; 1369 pmap_t pmap; 1370 u_int lo; 1371 1372 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1373 ("moea_remove_write: page %p is not managed", m)); 1374 vm_page_assert_busied(m); 1375 1376 if (!pmap_page_is_write_mapped(m)) 1377 return; 1378 rw_wlock(&pvh_global_lock); 1379 lo = moea_attr_fetch(m); 1380 powerpc_sync(); 1381 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1382 pmap = pvo->pvo_pmap; 1383 PMAP_LOCK(pmap); 1384 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1385 pt = moea_pvo_to_pte(pvo, -1); 1386 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1387 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1388 if (pt != NULL) { 1389 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1390 lo |= pvo->pvo_pte.pte.pte_lo; 1391 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1392 moea_pte_change(pt, &pvo->pvo_pte.pte, 1393 pvo->pvo_vaddr); 1394 mtx_unlock(&moea_table_mutex); 1395 } 1396 } 1397 PMAP_UNLOCK(pmap); 1398 } 1399 if ((lo & PTE_CHG) != 0) { 1400 moea_attr_clear(m, PTE_CHG); 1401 vm_page_dirty(m); 1402 } 1403 vm_page_aflag_clear(m, PGA_WRITEABLE); 1404 rw_wunlock(&pvh_global_lock); 1405 } 1406 1407 /* 1408 * moea_ts_referenced: 1409 * 1410 * Return a count of reference bits for a page, clearing those bits. 1411 * It is not necessary for every reference bit to be cleared, but it 1412 * is necessary that 0 only be returned when there are truly no 1413 * reference bits set. 1414 * 1415 * XXX: The exact number of bits to check and clear is a matter that 1416 * should be tested and standardized at some point in the future for 1417 * optimal aging of shared pages. 1418 */ 1419 int 1420 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1421 { 1422 int count; 1423 1424 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1425 ("moea_ts_referenced: page %p is not managed", m)); 1426 rw_wlock(&pvh_global_lock); 1427 count = moea_clear_bit(m, PTE_REF); 1428 rw_wunlock(&pvh_global_lock); 1429 return (count); 1430 } 1431 1432 /* 1433 * Modify the WIMG settings of all mappings for a page. 1434 */ 1435 void 1436 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1437 { 1438 struct pvo_entry *pvo; 1439 struct pvo_head *pvo_head; 1440 struct pte *pt; 1441 pmap_t pmap; 1442 u_int lo; 1443 1444 if ((m->oflags & VPO_UNMANAGED) != 0) { 1445 m->md.mdpg_cache_attrs = ma; 1446 return; 1447 } 1448 1449 rw_wlock(&pvh_global_lock); 1450 pvo_head = vm_page_to_pvoh(m); 1451 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1452 1453 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1454 pmap = pvo->pvo_pmap; 1455 PMAP_LOCK(pmap); 1456 pt = moea_pvo_to_pte(pvo, -1); 1457 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1458 pvo->pvo_pte.pte.pte_lo |= lo; 1459 if (pt != NULL) { 1460 moea_pte_change(pt, &pvo->pvo_pte.pte, 1461 pvo->pvo_vaddr); 1462 if (pvo->pvo_pmap == kernel_pmap) 1463 isync(); 1464 } 1465 mtx_unlock(&moea_table_mutex); 1466 PMAP_UNLOCK(pmap); 1467 } 1468 m->md.mdpg_cache_attrs = ma; 1469 rw_wunlock(&pvh_global_lock); 1470 } 1471 1472 /* 1473 * Map a wired page into kernel virtual address space. 1474 */ 1475 void 1476 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1477 { 1478 1479 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1480 } 1481 1482 void 1483 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1484 { 1485 u_int pte_lo; 1486 int error; 1487 1488 #if 0 1489 if (va < VM_MIN_KERNEL_ADDRESS) 1490 panic("moea_kenter: attempt to enter non-kernel address %#x", 1491 va); 1492 #endif 1493 1494 pte_lo = moea_calc_wimg(pa, ma); 1495 1496 PMAP_LOCK(kernel_pmap); 1497 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1498 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1499 1500 if (error != 0 && error != ENOENT) 1501 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1502 pa, error); 1503 1504 PMAP_UNLOCK(kernel_pmap); 1505 } 1506 1507 /* 1508 * Extract the physical page address associated with the given kernel virtual 1509 * address. 1510 */ 1511 vm_paddr_t 1512 moea_kextract(mmu_t mmu, vm_offset_t va) 1513 { 1514 struct pvo_entry *pvo; 1515 vm_paddr_t pa; 1516 1517 /* 1518 * Allow direct mappings on 32-bit OEA 1519 */ 1520 if (va < VM_MIN_KERNEL_ADDRESS) { 1521 return (va); 1522 } 1523 1524 PMAP_LOCK(kernel_pmap); 1525 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1526 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1527 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1528 PMAP_UNLOCK(kernel_pmap); 1529 return (pa); 1530 } 1531 1532 /* 1533 * Remove a wired page from kernel virtual address space. 1534 */ 1535 void 1536 moea_kremove(mmu_t mmu, vm_offset_t va) 1537 { 1538 1539 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1540 } 1541 1542 /* 1543 * Provide a kernel pointer corresponding to a given userland pointer. 1544 * The returned pointer is valid until the next time this function is 1545 * called in this thread. This is used internally in copyin/copyout. 1546 */ 1547 int 1548 moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1549 void **kaddr, size_t ulen, size_t *klen) 1550 { 1551 size_t l; 1552 register_t vsid; 1553 1554 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1555 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1556 if (l > ulen) 1557 l = ulen; 1558 if (klen) 1559 *klen = l; 1560 else if (l != ulen) 1561 return (EFAULT); 1562 1563 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1564 1565 /* Mark segment no-execute */ 1566 vsid |= SR_N; 1567 1568 /* If we have already set this VSID, we can just return */ 1569 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1570 return (0); 1571 1572 __asm __volatile("isync"); 1573 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1574 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1575 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1576 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1577 1578 return (0); 1579 } 1580 1581 /* 1582 * Figure out where a given kernel pointer (usually in a fault) points 1583 * to from the VM's perspective, potentially remapping into userland's 1584 * address space. 1585 */ 1586 static int 1587 moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1588 vm_offset_t *decoded_addr) 1589 { 1590 vm_offset_t user_sr; 1591 1592 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1593 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1594 addr &= ADDR_PIDX | ADDR_POFF; 1595 addr |= user_sr << ADDR_SR_SHFT; 1596 *decoded_addr = addr; 1597 *is_user = 1; 1598 } else { 1599 *decoded_addr = addr; 1600 *is_user = 0; 1601 } 1602 1603 return (0); 1604 } 1605 1606 /* 1607 * Map a range of physical addresses into kernel virtual address space. 1608 * 1609 * The value passed in *virt is a suggested virtual address for the mapping. 1610 * Architectures which can support a direct-mapped physical to virtual region 1611 * can return the appropriate address within that region, leaving '*virt' 1612 * unchanged. We cannot and therefore do not; *virt is updated with the 1613 * first usable address after the mapped region. 1614 */ 1615 vm_offset_t 1616 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1617 vm_paddr_t pa_end, int prot) 1618 { 1619 vm_offset_t sva, va; 1620 1621 sva = *virt; 1622 va = sva; 1623 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1624 moea_kenter(mmu, va, pa_start); 1625 *virt = va; 1626 return (sva); 1627 } 1628 1629 /* 1630 * Returns true if the pmap's pv is one of the first 1631 * 16 pvs linked to from this page. This count may 1632 * be changed upwards or downwards in the future; it 1633 * is only necessary that true be returned for a small 1634 * subset of pmaps for proper page aging. 1635 */ 1636 boolean_t 1637 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1638 { 1639 int loops; 1640 struct pvo_entry *pvo; 1641 boolean_t rv; 1642 1643 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1644 ("moea_page_exists_quick: page %p is not managed", m)); 1645 loops = 0; 1646 rv = FALSE; 1647 rw_wlock(&pvh_global_lock); 1648 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1649 if (pvo->pvo_pmap == pmap) { 1650 rv = TRUE; 1651 break; 1652 } 1653 if (++loops >= 16) 1654 break; 1655 } 1656 rw_wunlock(&pvh_global_lock); 1657 return (rv); 1658 } 1659 1660 void 1661 moea_page_init(mmu_t mmu __unused, vm_page_t m) 1662 { 1663 1664 m->md.mdpg_attrs = 0; 1665 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1666 LIST_INIT(&m->md.mdpg_pvoh); 1667 } 1668 1669 /* 1670 * Return the number of managed mappings to the given physical page 1671 * that are wired. 1672 */ 1673 int 1674 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1675 { 1676 struct pvo_entry *pvo; 1677 int count; 1678 1679 count = 0; 1680 if ((m->oflags & VPO_UNMANAGED) != 0) 1681 return (count); 1682 rw_wlock(&pvh_global_lock); 1683 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1684 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1685 count++; 1686 rw_wunlock(&pvh_global_lock); 1687 return (count); 1688 } 1689 1690 static u_int moea_vsidcontext; 1691 1692 void 1693 moea_pinit(mmu_t mmu, pmap_t pmap) 1694 { 1695 int i, mask; 1696 u_int entropy; 1697 1698 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1699 RB_INIT(&pmap->pmap_pvo); 1700 1701 entropy = 0; 1702 __asm __volatile("mftb %0" : "=r"(entropy)); 1703 1704 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1705 == NULL) { 1706 pmap->pmap_phys = pmap; 1707 } 1708 1709 1710 mtx_lock(&moea_vsid_mutex); 1711 /* 1712 * Allocate some segment registers for this pmap. 1713 */ 1714 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1715 u_int hash, n; 1716 1717 /* 1718 * Create a new value by mutiplying by a prime and adding in 1719 * entropy from the timebase register. This is to make the 1720 * VSID more random so that the PT hash function collides 1721 * less often. (Note that the prime casues gcc to do shifts 1722 * instead of a multiply.) 1723 */ 1724 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1725 hash = moea_vsidcontext & (NPMAPS - 1); 1726 if (hash == 0) /* 0 is special, avoid it */ 1727 continue; 1728 n = hash >> 5; 1729 mask = 1 << (hash & (VSID_NBPW - 1)); 1730 hash = (moea_vsidcontext & 0xfffff); 1731 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1732 /* anything free in this bucket? */ 1733 if (moea_vsid_bitmap[n] == 0xffffffff) { 1734 entropy = (moea_vsidcontext >> 20); 1735 continue; 1736 } 1737 i = ffs(~moea_vsid_bitmap[n]) - 1; 1738 mask = 1 << i; 1739 hash &= rounddown2(0xfffff, VSID_NBPW); 1740 hash |= i; 1741 } 1742 KASSERT(!(moea_vsid_bitmap[n] & mask), 1743 ("Allocating in-use VSID group %#x\n", hash)); 1744 moea_vsid_bitmap[n] |= mask; 1745 for (i = 0; i < 16; i++) 1746 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1747 mtx_unlock(&moea_vsid_mutex); 1748 return; 1749 } 1750 1751 mtx_unlock(&moea_vsid_mutex); 1752 panic("moea_pinit: out of segments"); 1753 } 1754 1755 /* 1756 * Initialize the pmap associated with process 0. 1757 */ 1758 void 1759 moea_pinit0(mmu_t mmu, pmap_t pm) 1760 { 1761 1762 PMAP_LOCK_INIT(pm); 1763 moea_pinit(mmu, pm); 1764 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1765 } 1766 1767 /* 1768 * Set the physical protection on the specified range of this map as requested. 1769 */ 1770 void 1771 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1772 vm_prot_t prot) 1773 { 1774 struct pvo_entry *pvo, *tpvo, key; 1775 struct pte *pt; 1776 1777 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1778 ("moea_protect: non current pmap")); 1779 1780 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1781 moea_remove(mmu, pm, sva, eva); 1782 return; 1783 } 1784 1785 rw_wlock(&pvh_global_lock); 1786 PMAP_LOCK(pm); 1787 key.pvo_vaddr = sva; 1788 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1789 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1790 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1791 1792 /* 1793 * Grab the PTE pointer before we diddle with the cached PTE 1794 * copy. 1795 */ 1796 pt = moea_pvo_to_pte(pvo, -1); 1797 /* 1798 * Change the protection of the page. 1799 */ 1800 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1801 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1802 1803 /* 1804 * If the PVO is in the page table, update that pte as well. 1805 */ 1806 if (pt != NULL) { 1807 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1808 mtx_unlock(&moea_table_mutex); 1809 } 1810 } 1811 rw_wunlock(&pvh_global_lock); 1812 PMAP_UNLOCK(pm); 1813 } 1814 1815 /* 1816 * Map a list of wired pages into kernel virtual address space. This is 1817 * intended for temporary mappings which do not need page modification or 1818 * references recorded. Existing mappings in the region are overwritten. 1819 */ 1820 void 1821 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1822 { 1823 vm_offset_t va; 1824 1825 va = sva; 1826 while (count-- > 0) { 1827 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1828 va += PAGE_SIZE; 1829 m++; 1830 } 1831 } 1832 1833 /* 1834 * Remove page mappings from kernel virtual address space. Intended for 1835 * temporary mappings entered by moea_qenter. 1836 */ 1837 void 1838 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1839 { 1840 vm_offset_t va; 1841 1842 va = sva; 1843 while (count-- > 0) { 1844 moea_kremove(mmu, va); 1845 va += PAGE_SIZE; 1846 } 1847 } 1848 1849 void 1850 moea_release(mmu_t mmu, pmap_t pmap) 1851 { 1852 int idx, mask; 1853 1854 /* 1855 * Free segment register's VSID 1856 */ 1857 if (pmap->pm_sr[0] == 0) 1858 panic("moea_release"); 1859 1860 mtx_lock(&moea_vsid_mutex); 1861 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1862 mask = 1 << (idx % VSID_NBPW); 1863 idx /= VSID_NBPW; 1864 moea_vsid_bitmap[idx] &= ~mask; 1865 mtx_unlock(&moea_vsid_mutex); 1866 } 1867 1868 /* 1869 * Remove the given range of addresses from the specified map. 1870 */ 1871 void 1872 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1873 { 1874 struct pvo_entry *pvo, *tpvo, key; 1875 1876 rw_wlock(&pvh_global_lock); 1877 PMAP_LOCK(pm); 1878 key.pvo_vaddr = sva; 1879 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1880 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1881 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1882 moea_pvo_remove(pvo, -1); 1883 } 1884 PMAP_UNLOCK(pm); 1885 rw_wunlock(&pvh_global_lock); 1886 } 1887 1888 /* 1889 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1890 * will reflect changes in pte's back to the vm_page. 1891 */ 1892 void 1893 moea_remove_all(mmu_t mmu, vm_page_t m) 1894 { 1895 struct pvo_head *pvo_head; 1896 struct pvo_entry *pvo, *next_pvo; 1897 pmap_t pmap; 1898 1899 rw_wlock(&pvh_global_lock); 1900 pvo_head = vm_page_to_pvoh(m); 1901 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1902 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1903 1904 pmap = pvo->pvo_pmap; 1905 PMAP_LOCK(pmap); 1906 moea_pvo_remove(pvo, -1); 1907 PMAP_UNLOCK(pmap); 1908 } 1909 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1910 moea_attr_clear(m, PTE_CHG); 1911 vm_page_dirty(m); 1912 } 1913 vm_page_aflag_clear(m, PGA_WRITEABLE); 1914 rw_wunlock(&pvh_global_lock); 1915 } 1916 1917 /* 1918 * Allocate a physical page of memory directly from the phys_avail map. 1919 * Can only be called from moea_bootstrap before avail start and end are 1920 * calculated. 1921 */ 1922 static vm_offset_t 1923 moea_bootstrap_alloc(vm_size_t size, u_int align) 1924 { 1925 vm_offset_t s, e; 1926 int i, j; 1927 1928 size = round_page(size); 1929 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1930 if (align != 0) 1931 s = roundup2(phys_avail[i], align); 1932 else 1933 s = phys_avail[i]; 1934 e = s + size; 1935 1936 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1937 continue; 1938 1939 if (s == phys_avail[i]) { 1940 phys_avail[i] += size; 1941 } else if (e == phys_avail[i + 1]) { 1942 phys_avail[i + 1] -= size; 1943 } else { 1944 for (j = phys_avail_count * 2; j > i; j -= 2) { 1945 phys_avail[j] = phys_avail[j - 2]; 1946 phys_avail[j + 1] = phys_avail[j - 1]; 1947 } 1948 1949 phys_avail[i + 3] = phys_avail[i + 1]; 1950 phys_avail[i + 1] = s; 1951 phys_avail[i + 2] = e; 1952 phys_avail_count++; 1953 } 1954 1955 return (s); 1956 } 1957 panic("moea_bootstrap_alloc: could not allocate memory"); 1958 } 1959 1960 static void 1961 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1962 { 1963 __syncicache((void *)pa, len); 1964 } 1965 1966 static int 1967 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1968 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1969 { 1970 struct pvo_entry *pvo; 1971 u_int sr; 1972 int first; 1973 u_int ptegidx; 1974 int i; 1975 int bootstrap; 1976 1977 moea_pvo_enter_calls++; 1978 first = 0; 1979 bootstrap = 0; 1980 1981 /* 1982 * Compute the PTE Group index. 1983 */ 1984 va &= ~ADDR_POFF; 1985 sr = va_to_sr(pm->pm_sr, va); 1986 ptegidx = va_to_pteg(sr, va); 1987 1988 /* 1989 * Remove any existing mapping for this page. Reuse the pvo entry if 1990 * there is a mapping. 1991 */ 1992 mtx_lock(&moea_table_mutex); 1993 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1994 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1995 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1996 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1997 (pte_lo & PTE_PP)) { 1998 /* 1999 * The PTE is not changing. Instead, this may 2000 * be a request to change the mapping's wired 2001 * attribute. 2002 */ 2003 mtx_unlock(&moea_table_mutex); 2004 if ((flags & PVO_WIRED) != 0 && 2005 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2006 pvo->pvo_vaddr |= PVO_WIRED; 2007 pm->pm_stats.wired_count++; 2008 } else if ((flags & PVO_WIRED) == 0 && 2009 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2010 pvo->pvo_vaddr &= ~PVO_WIRED; 2011 pm->pm_stats.wired_count--; 2012 } 2013 return (0); 2014 } 2015 moea_pvo_remove(pvo, -1); 2016 break; 2017 } 2018 } 2019 2020 /* 2021 * If we aren't overwriting a mapping, try to allocate. 2022 */ 2023 if (moea_initialized) { 2024 pvo = uma_zalloc(zone, M_NOWAIT); 2025 } else { 2026 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2027 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2028 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2029 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2030 } 2031 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2032 moea_bpvo_pool_index++; 2033 bootstrap = 1; 2034 } 2035 2036 if (pvo == NULL) { 2037 mtx_unlock(&moea_table_mutex); 2038 return (ENOMEM); 2039 } 2040 2041 moea_pvo_entries++; 2042 pvo->pvo_vaddr = va; 2043 pvo->pvo_pmap = pm; 2044 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2045 pvo->pvo_vaddr &= ~ADDR_POFF; 2046 if (flags & PVO_WIRED) 2047 pvo->pvo_vaddr |= PVO_WIRED; 2048 if (pvo_head != &moea_pvo_kunmanaged) 2049 pvo->pvo_vaddr |= PVO_MANAGED; 2050 if (bootstrap) 2051 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2052 2053 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2054 2055 /* 2056 * Add to pmap list 2057 */ 2058 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2059 2060 /* 2061 * Remember if the list was empty and therefore will be the first 2062 * item. 2063 */ 2064 if (LIST_FIRST(pvo_head) == NULL) 2065 first = 1; 2066 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2067 2068 if (pvo->pvo_vaddr & PVO_WIRED) 2069 pm->pm_stats.wired_count++; 2070 pm->pm_stats.resident_count++; 2071 2072 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2073 KASSERT(i < 8, ("Invalid PTE index")); 2074 if (i >= 0) { 2075 PVO_PTEGIDX_SET(pvo, i); 2076 } else { 2077 panic("moea_pvo_enter: overflow"); 2078 moea_pte_overflow++; 2079 } 2080 mtx_unlock(&moea_table_mutex); 2081 2082 return (first ? ENOENT : 0); 2083 } 2084 2085 static void 2086 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2087 { 2088 struct pte *pt; 2089 2090 /* 2091 * If there is an active pte entry, we need to deactivate it (and 2092 * save the ref & cfg bits). 2093 */ 2094 pt = moea_pvo_to_pte(pvo, pteidx); 2095 if (pt != NULL) { 2096 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2097 mtx_unlock(&moea_table_mutex); 2098 PVO_PTEGIDX_CLR(pvo); 2099 } else { 2100 moea_pte_overflow--; 2101 } 2102 2103 /* 2104 * Update our statistics. 2105 */ 2106 pvo->pvo_pmap->pm_stats.resident_count--; 2107 if (pvo->pvo_vaddr & PVO_WIRED) 2108 pvo->pvo_pmap->pm_stats.wired_count--; 2109 2110 /* 2111 * Save the REF/CHG bits into their cache if the page is managed. 2112 */ 2113 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2114 struct vm_page *pg; 2115 2116 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2117 if (pg != NULL) { 2118 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2119 (PTE_REF | PTE_CHG)); 2120 } 2121 } 2122 2123 /* 2124 * Remove this PVO from the PV and pmap lists. 2125 */ 2126 LIST_REMOVE(pvo, pvo_vlink); 2127 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2128 2129 /* 2130 * Remove this from the overflow list and return it to the pool 2131 * if we aren't going to reuse it. 2132 */ 2133 LIST_REMOVE(pvo, pvo_olink); 2134 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2135 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2136 moea_upvo_zone, pvo); 2137 moea_pvo_entries--; 2138 moea_pvo_remove_calls++; 2139 } 2140 2141 static __inline int 2142 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2143 { 2144 int pteidx; 2145 2146 /* 2147 * We can find the actual pte entry without searching by grabbing 2148 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2149 * noticing the HID bit. 2150 */ 2151 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2152 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2153 pteidx ^= moea_pteg_mask * 8; 2154 2155 return (pteidx); 2156 } 2157 2158 static struct pvo_entry * 2159 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2160 { 2161 struct pvo_entry *pvo; 2162 int ptegidx; 2163 u_int sr; 2164 2165 va &= ~ADDR_POFF; 2166 sr = va_to_sr(pm->pm_sr, va); 2167 ptegidx = va_to_pteg(sr, va); 2168 2169 mtx_lock(&moea_table_mutex); 2170 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2171 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2172 if (pteidx_p) 2173 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2174 break; 2175 } 2176 } 2177 mtx_unlock(&moea_table_mutex); 2178 2179 return (pvo); 2180 } 2181 2182 static struct pte * 2183 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2184 { 2185 struct pte *pt; 2186 2187 /* 2188 * If we haven't been supplied the ptegidx, calculate it. 2189 */ 2190 if (pteidx == -1) { 2191 int ptegidx; 2192 u_int sr; 2193 2194 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2195 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2196 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2197 } 2198 2199 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2200 mtx_lock(&moea_table_mutex); 2201 2202 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2203 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2204 "valid pte index", pvo); 2205 } 2206 2207 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2208 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2209 "pvo but no valid pte", pvo); 2210 } 2211 2212 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2213 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2214 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2215 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2216 } 2217 2218 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2219 != 0) { 2220 panic("moea_pvo_to_pte: pvo %p pte does not match " 2221 "pte %p in moea_pteg_table", pvo, pt); 2222 } 2223 2224 mtx_assert(&moea_table_mutex, MA_OWNED); 2225 return (pt); 2226 } 2227 2228 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2229 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2230 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2231 } 2232 2233 mtx_unlock(&moea_table_mutex); 2234 return (NULL); 2235 } 2236 2237 /* 2238 * XXX: THIS STUFF SHOULD BE IN pte.c? 2239 */ 2240 int 2241 moea_pte_spill(vm_offset_t addr) 2242 { 2243 struct pvo_entry *source_pvo, *victim_pvo; 2244 struct pvo_entry *pvo; 2245 int ptegidx, i, j; 2246 u_int sr; 2247 struct pteg *pteg; 2248 struct pte *pt; 2249 2250 moea_pte_spills++; 2251 2252 sr = mfsrin(addr); 2253 ptegidx = va_to_pteg(sr, addr); 2254 2255 /* 2256 * Have to substitute some entry. Use the primary hash for this. 2257 * Use low bits of timebase as random generator. 2258 */ 2259 pteg = &moea_pteg_table[ptegidx]; 2260 mtx_lock(&moea_table_mutex); 2261 __asm __volatile("mftb %0" : "=r"(i)); 2262 i &= 7; 2263 pt = &pteg->pt[i]; 2264 2265 source_pvo = NULL; 2266 victim_pvo = NULL; 2267 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2268 /* 2269 * We need to find a pvo entry for this address. 2270 */ 2271 if (source_pvo == NULL && 2272 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2273 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2274 /* 2275 * Now found an entry to be spilled into the pteg. 2276 * The PTE is now valid, so we know it's active. 2277 */ 2278 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2279 2280 if (j >= 0) { 2281 PVO_PTEGIDX_SET(pvo, j); 2282 moea_pte_overflow--; 2283 mtx_unlock(&moea_table_mutex); 2284 return (1); 2285 } 2286 2287 source_pvo = pvo; 2288 2289 if (victim_pvo != NULL) 2290 break; 2291 } 2292 2293 /* 2294 * We also need the pvo entry of the victim we are replacing 2295 * so save the R & C bits of the PTE. 2296 */ 2297 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2298 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2299 victim_pvo = pvo; 2300 if (source_pvo != NULL) 2301 break; 2302 } 2303 } 2304 2305 if (source_pvo == NULL) { 2306 mtx_unlock(&moea_table_mutex); 2307 return (0); 2308 } 2309 2310 if (victim_pvo == NULL) { 2311 if ((pt->pte_hi & PTE_HID) == 0) 2312 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2313 "entry", pt); 2314 2315 /* 2316 * If this is a secondary PTE, we need to search it's primary 2317 * pvo bucket for the matching PVO. 2318 */ 2319 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2320 pvo_olink) { 2321 /* 2322 * We also need the pvo entry of the victim we are 2323 * replacing so save the R & C bits of the PTE. 2324 */ 2325 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2326 victim_pvo = pvo; 2327 break; 2328 } 2329 } 2330 2331 if (victim_pvo == NULL) 2332 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2333 "entry", pt); 2334 } 2335 2336 /* 2337 * We are invalidating the TLB entry for the EA we are replacing even 2338 * though it's valid. If we don't, we lose any ref/chg bit changes 2339 * contained in the TLB entry. 2340 */ 2341 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2342 2343 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2344 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2345 2346 PVO_PTEGIDX_CLR(victim_pvo); 2347 PVO_PTEGIDX_SET(source_pvo, i); 2348 moea_pte_replacements++; 2349 2350 mtx_unlock(&moea_table_mutex); 2351 return (1); 2352 } 2353 2354 static __inline struct pvo_entry * 2355 moea_pte_spillable_ident(u_int ptegidx) 2356 { 2357 struct pte *pt; 2358 struct pvo_entry *pvo_walk, *pvo = NULL; 2359 2360 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2361 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2362 continue; 2363 2364 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2365 continue; 2366 2367 pt = moea_pvo_to_pte(pvo_walk, -1); 2368 2369 if (pt == NULL) 2370 continue; 2371 2372 pvo = pvo_walk; 2373 2374 mtx_unlock(&moea_table_mutex); 2375 if (!(pt->pte_lo & PTE_REF)) 2376 return (pvo_walk); 2377 } 2378 2379 return (pvo); 2380 } 2381 2382 static int 2383 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2384 { 2385 struct pte *pt; 2386 struct pvo_entry *victim_pvo; 2387 int i; 2388 int victim_idx; 2389 u_int pteg_bkpidx = ptegidx; 2390 2391 mtx_assert(&moea_table_mutex, MA_OWNED); 2392 2393 /* 2394 * First try primary hash. 2395 */ 2396 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2397 if ((pt->pte_hi & PTE_VALID) == 0) { 2398 pvo_pt->pte_hi &= ~PTE_HID; 2399 moea_pte_set(pt, pvo_pt); 2400 return (i); 2401 } 2402 } 2403 2404 /* 2405 * Now try secondary hash. 2406 */ 2407 ptegidx ^= moea_pteg_mask; 2408 2409 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2410 if ((pt->pte_hi & PTE_VALID) == 0) { 2411 pvo_pt->pte_hi |= PTE_HID; 2412 moea_pte_set(pt, pvo_pt); 2413 return (i); 2414 } 2415 } 2416 2417 /* Try again, but this time try to force a PTE out. */ 2418 ptegidx = pteg_bkpidx; 2419 2420 victim_pvo = moea_pte_spillable_ident(ptegidx); 2421 if (victim_pvo == NULL) { 2422 ptegidx ^= moea_pteg_mask; 2423 victim_pvo = moea_pte_spillable_ident(ptegidx); 2424 } 2425 2426 if (victim_pvo == NULL) { 2427 panic("moea_pte_insert: overflow"); 2428 return (-1); 2429 } 2430 2431 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2432 2433 if (pteg_bkpidx == ptegidx) 2434 pvo_pt->pte_hi &= ~PTE_HID; 2435 else 2436 pvo_pt->pte_hi |= PTE_HID; 2437 2438 /* 2439 * Synchronize the sacrifice PTE with its PVO, then mark both 2440 * invalid. The PVO will be reused when/if the VM system comes 2441 * here after a fault. 2442 */ 2443 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2444 2445 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2446 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2447 2448 /* 2449 * Set the new PTE. 2450 */ 2451 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2452 PVO_PTEGIDX_CLR(victim_pvo); 2453 moea_pte_overflow++; 2454 moea_pte_set(pt, pvo_pt); 2455 2456 return (victim_idx & 7); 2457 } 2458 2459 static boolean_t 2460 moea_query_bit(vm_page_t m, int ptebit) 2461 { 2462 struct pvo_entry *pvo; 2463 struct pte *pt; 2464 2465 rw_assert(&pvh_global_lock, RA_WLOCKED); 2466 if (moea_attr_fetch(m) & ptebit) 2467 return (TRUE); 2468 2469 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2470 2471 /* 2472 * See if we saved the bit off. If so, cache it and return 2473 * success. 2474 */ 2475 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2476 moea_attr_save(m, ptebit); 2477 return (TRUE); 2478 } 2479 } 2480 2481 /* 2482 * No luck, now go through the hard part of looking at the PTEs 2483 * themselves. Sync so that any pending REF/CHG bits are flushed to 2484 * the PTEs. 2485 */ 2486 powerpc_sync(); 2487 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2488 2489 /* 2490 * See if this pvo has a valid PTE. if so, fetch the 2491 * REF/CHG bits from the valid PTE. If the appropriate 2492 * ptebit is set, cache it and return success. 2493 */ 2494 pt = moea_pvo_to_pte(pvo, -1); 2495 if (pt != NULL) { 2496 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2497 mtx_unlock(&moea_table_mutex); 2498 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2499 moea_attr_save(m, ptebit); 2500 return (TRUE); 2501 } 2502 } 2503 } 2504 2505 return (FALSE); 2506 } 2507 2508 static u_int 2509 moea_clear_bit(vm_page_t m, int ptebit) 2510 { 2511 u_int count; 2512 struct pvo_entry *pvo; 2513 struct pte *pt; 2514 2515 rw_assert(&pvh_global_lock, RA_WLOCKED); 2516 2517 /* 2518 * Clear the cached value. 2519 */ 2520 moea_attr_clear(m, ptebit); 2521 2522 /* 2523 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2524 * we can reset the right ones). note that since the pvo entries and 2525 * list heads are accessed via BAT0 and are never placed in the page 2526 * table, we don't have to worry about further accesses setting the 2527 * REF/CHG bits. 2528 */ 2529 powerpc_sync(); 2530 2531 /* 2532 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2533 * valid pte clear the ptebit from the valid pte. 2534 */ 2535 count = 0; 2536 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2537 pt = moea_pvo_to_pte(pvo, -1); 2538 if (pt != NULL) { 2539 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2540 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2541 count++; 2542 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2543 } 2544 mtx_unlock(&moea_table_mutex); 2545 } 2546 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2547 } 2548 2549 return (count); 2550 } 2551 2552 /* 2553 * Return true if the physical range is encompassed by the battable[idx] 2554 */ 2555 static int 2556 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2557 { 2558 u_int prot; 2559 u_int32_t start; 2560 u_int32_t end; 2561 u_int32_t bat_ble; 2562 2563 /* 2564 * Return immediately if not a valid mapping 2565 */ 2566 if (!(battable[idx].batu & BAT_Vs)) 2567 return (EINVAL); 2568 2569 /* 2570 * The BAT entry must be cache-inhibited, guarded, and r/w 2571 * so it can function as an i/o page 2572 */ 2573 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2574 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2575 return (EPERM); 2576 2577 /* 2578 * The address should be within the BAT range. Assume that the 2579 * start address in the BAT has the correct alignment (thus 2580 * not requiring masking) 2581 */ 2582 start = battable[idx].batl & BAT_PBS; 2583 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2584 end = start | (bat_ble << 15) | 0x7fff; 2585 2586 if ((pa < start) || ((pa + size) > end)) 2587 return (ERANGE); 2588 2589 return (0); 2590 } 2591 2592 boolean_t 2593 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2594 { 2595 int i; 2596 2597 /* 2598 * This currently does not work for entries that 2599 * overlap 256M BAT segments. 2600 */ 2601 2602 for(i = 0; i < 16; i++) 2603 if (moea_bat_mapped(i, pa, size) == 0) 2604 return (0); 2605 2606 return (EFAULT); 2607 } 2608 2609 /* 2610 * Map a set of physical memory pages into the kernel virtual 2611 * address space. Return a pointer to where it is mapped. This 2612 * routine is intended to be used for mapping device memory, 2613 * NOT real memory. 2614 */ 2615 void * 2616 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2617 { 2618 2619 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2620 } 2621 2622 void * 2623 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2624 { 2625 vm_offset_t va, tmpva, ppa, offset; 2626 int i; 2627 2628 ppa = trunc_page(pa); 2629 offset = pa & PAGE_MASK; 2630 size = roundup(offset + size, PAGE_SIZE); 2631 2632 /* 2633 * If the physical address lies within a valid BAT table entry, 2634 * return the 1:1 mapping. This currently doesn't work 2635 * for regions that overlap 256M BAT segments. 2636 */ 2637 for (i = 0; i < 16; i++) { 2638 if (moea_bat_mapped(i, pa, size) == 0) 2639 return ((void *) pa); 2640 } 2641 2642 va = kva_alloc(size); 2643 if (!va) 2644 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2645 2646 for (tmpva = va; size > 0;) { 2647 moea_kenter_attr(mmu, tmpva, ppa, ma); 2648 tlbie(tmpva); 2649 size -= PAGE_SIZE; 2650 tmpva += PAGE_SIZE; 2651 ppa += PAGE_SIZE; 2652 } 2653 2654 return ((void *)(va + offset)); 2655 } 2656 2657 void 2658 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2659 { 2660 vm_offset_t base, offset; 2661 2662 /* 2663 * If this is outside kernel virtual space, then it's a 2664 * battable entry and doesn't require unmapping 2665 */ 2666 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2667 base = trunc_page(va); 2668 offset = va & PAGE_MASK; 2669 size = roundup(offset + size, PAGE_SIZE); 2670 kva_free(base, size); 2671 } 2672 } 2673 2674 static void 2675 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2676 { 2677 struct pvo_entry *pvo; 2678 vm_offset_t lim; 2679 vm_paddr_t pa; 2680 vm_size_t len; 2681 2682 PMAP_LOCK(pm); 2683 while (sz > 0) { 2684 lim = round_page(va); 2685 len = MIN(lim - va, sz); 2686 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2687 if (pvo != NULL) { 2688 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2689 (va & ADDR_POFF); 2690 moea_syncicache(pa, len); 2691 } 2692 va += len; 2693 sz -= len; 2694 } 2695 PMAP_UNLOCK(pm); 2696 } 2697 2698 void 2699 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2700 { 2701 2702 *va = (void *)pa; 2703 } 2704 2705 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2706 2707 void 2708 moea_scan_init(mmu_t mmu) 2709 { 2710 struct pvo_entry *pvo; 2711 vm_offset_t va; 2712 int i; 2713 2714 if (!do_minidump) { 2715 /* Initialize phys. segments for dumpsys(). */ 2716 memset(&dump_map, 0, sizeof(dump_map)); 2717 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2718 for (i = 0; i < pregions_sz; i++) { 2719 dump_map[i].pa_start = pregions[i].mr_start; 2720 dump_map[i].pa_size = pregions[i].mr_size; 2721 } 2722 return; 2723 } 2724 2725 /* Virtual segments for minidumps: */ 2726 memset(&dump_map, 0, sizeof(dump_map)); 2727 2728 /* 1st: kernel .data and .bss. */ 2729 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2730 dump_map[0].pa_size = 2731 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2732 2733 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2734 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2735 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2736 2737 /* 3rd: kernel VM. */ 2738 va = dump_map[1].pa_start + dump_map[1].pa_size; 2739 /* Find start of next chunk (from va). */ 2740 while (va < virtual_end) { 2741 /* Don't dump the buffer cache. */ 2742 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2743 va = kmi.buffer_eva; 2744 continue; 2745 } 2746 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2747 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2748 break; 2749 va += PAGE_SIZE; 2750 } 2751 if (va < virtual_end) { 2752 dump_map[2].pa_start = va; 2753 va += PAGE_SIZE; 2754 /* Find last page in chunk. */ 2755 while (va < virtual_end) { 2756 /* Don't run into the buffer cache. */ 2757 if (va == kmi.buffer_sva) 2758 break; 2759 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2760 NULL); 2761 if (pvo == NULL || 2762 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2763 break; 2764 va += PAGE_SIZE; 2765 } 2766 dump_map[2].pa_size = va - dump_map[2].pa_start; 2767 } 2768 } 2769