1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/cpu.h> 141 #include <machine/platform.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/smp.h> 148 #include <machine/sr.h> 149 #include <machine/mmuvar.h> 150 #include <machine/trap.h> 151 152 #define MOEA_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 157 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 159 160 struct ofw_map { 161 vm_offset_t om_va; 162 vm_size_t om_len; 163 vm_offset_t om_pa; 164 u_int om_mode; 165 }; 166 167 extern unsigned char _etext[]; 168 extern unsigned char _end[]; 169 170 /* 171 * Map of physical memory regions. 172 */ 173 static struct mem_region *regions; 174 static struct mem_region *pregions; 175 static u_int phys_avail_count; 176 static int regions_sz, pregions_sz; 177 static struct ofw_map *translations; 178 179 /* 180 * Lock for the pteg and pvo tables. 181 */ 182 struct mtx moea_table_mutex; 183 struct mtx moea_vsid_mutex; 184 185 /* tlbie instruction synchronization */ 186 static struct mtx tlbie_mtx; 187 188 /* 189 * PTEG data. 190 */ 191 static struct pteg *moea_pteg_table; 192 u_int moea_pteg_count; 193 u_int moea_pteg_mask; 194 195 /* 196 * PVO data. 197 */ 198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 199 struct pvo_head moea_pvo_kunmanaged = 200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 201 202 static struct rwlock_padalign pvh_global_lock; 203 204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 206 207 #define BPVO_POOL_SIZE 32768 208 static struct pvo_entry *moea_bpvo_pool; 209 static int moea_bpvo_pool_index = 0; 210 211 #define VSID_NBPW (sizeof(u_int32_t) * 8) 212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 213 214 static boolean_t moea_initialized = FALSE; 215 216 /* 217 * Statistics. 218 */ 219 u_int moea_pte_valid = 0; 220 u_int moea_pte_overflow = 0; 221 u_int moea_pte_replacements = 0; 222 u_int moea_pvo_entries = 0; 223 u_int moea_pvo_enter_calls = 0; 224 u_int moea_pvo_remove_calls = 0; 225 u_int moea_pte_spills = 0; 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 227 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 229 &moea_pte_overflow, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 231 &moea_pte_replacements, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 233 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 235 &moea_pvo_enter_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 237 &moea_pvo_remove_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 239 &moea_pte_spills, 0, ""); 240 241 /* 242 * Allocate physical memory for use in moea_bootstrap. 243 */ 244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 245 246 /* 247 * PTE calls. 248 */ 249 static int moea_pte_insert(u_int, struct pte *); 250 251 /* 252 * PVO calls. 253 */ 254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 255 vm_offset_t, vm_paddr_t, u_int, int); 256 static void moea_pvo_remove(struct pvo_entry *, int); 257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 259 260 /* 261 * Utility routines. 262 */ 263 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 264 vm_prot_t, u_int, int8_t); 265 static void moea_syncicache(vm_paddr_t, vm_size_t); 266 static boolean_t moea_query_bit(vm_page_t, int); 267 static u_int moea_clear_bit(vm_page_t, int); 268 static void moea_kremove(vm_offset_t); 269 int moea_pte_spill(vm_offset_t); 270 271 /* 272 * Kernel MMU interface 273 */ 274 void moea_clear_modify(vm_page_t); 275 void moea_copy_page(vm_page_t, vm_page_t); 276 void moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 277 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 278 int moea_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 279 int8_t); 280 void moea_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 void moea_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283 vm_paddr_t moea_extract(pmap_t, vm_offset_t); 284 vm_page_t moea_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 285 void moea_init(void); 286 boolean_t moea_is_modified(vm_page_t); 287 boolean_t moea_is_prefaultable(pmap_t, vm_offset_t); 288 boolean_t moea_is_referenced(vm_page_t); 289 int moea_ts_referenced(vm_page_t); 290 vm_offset_t moea_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 291 boolean_t moea_page_exists_quick(pmap_t, vm_page_t); 292 void moea_page_init(vm_page_t); 293 int moea_page_wired_mappings(vm_page_t); 294 int moea_pinit(pmap_t); 295 void moea_pinit0(pmap_t); 296 void moea_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(vm_offset_t, vm_page_t *, int); 298 void moea_qremove(vm_offset_t, int); 299 void moea_release(pmap_t); 300 void moea_remove(pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(vm_page_t); 302 void moea_remove_write(vm_page_t); 303 void moea_unwire(pmap_t, vm_offset_t, vm_offset_t); 304 void moea_zero_page(vm_page_t); 305 void moea_zero_page_area(vm_page_t, int, int); 306 void moea_activate(struct thread *); 307 void moea_deactivate(struct thread *); 308 void moea_cpu_bootstrap(int); 309 void moea_bootstrap(vm_offset_t, vm_offset_t); 310 void *moea_mapdev(vm_paddr_t, vm_size_t); 311 void *moea_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(vm_offset_t, vm_size_t); 313 vm_paddr_t moea_kextract(vm_offset_t); 314 void moea_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 315 void moea_kenter(vm_offset_t, vm_paddr_t); 316 void moea_page_set_memattr(vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(vm_paddr_t, vm_size_t); 318 static void moea_sync_icache(pmap_t, vm_offset_t, vm_size_t); 319 void moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va); 320 void moea_scan_init(void); 321 vm_offset_t moea_quick_enter_page(vm_page_t m); 322 void moea_quick_remove_page(vm_offset_t addr); 323 boolean_t moea_page_is_mapped(vm_page_t m); 324 static int moea_map_user_ptr(pmap_t pm, 325 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 326 static int moea_decode_kernel_ptr(vm_offset_t addr, 327 int *is_user, vm_offset_t *decoded_addr); 328 329 static struct pmap_funcs moea_methods = { 330 .clear_modify = moea_clear_modify, 331 .copy_page = moea_copy_page, 332 .copy_pages = moea_copy_pages, 333 .enter = moea_enter, 334 .enter_object = moea_enter_object, 335 .enter_quick = moea_enter_quick, 336 .extract = moea_extract, 337 .extract_and_hold = moea_extract_and_hold, 338 .init = moea_init, 339 .is_modified = moea_is_modified, 340 .is_prefaultable = moea_is_prefaultable, 341 .is_referenced = moea_is_referenced, 342 .ts_referenced = moea_ts_referenced, 343 .map = moea_map, 344 .page_exists_quick = moea_page_exists_quick, 345 .page_init = moea_page_init, 346 .page_wired_mappings = moea_page_wired_mappings, 347 .pinit = moea_pinit, 348 .pinit0 = moea_pinit0, 349 .protect = moea_protect, 350 .qenter = moea_qenter, 351 .qremove = moea_qremove, 352 .release = moea_release, 353 .remove = moea_remove, 354 .remove_all = moea_remove_all, 355 .remove_write = moea_remove_write, 356 .sync_icache = moea_sync_icache, 357 .unwire = moea_unwire, 358 .zero_page = moea_zero_page, 359 .zero_page_area = moea_zero_page_area, 360 .activate = moea_activate, 361 .deactivate = moea_deactivate, 362 .page_set_memattr = moea_page_set_memattr, 363 .quick_enter_page = moea_quick_enter_page, 364 .quick_remove_page = moea_quick_remove_page, 365 .page_is_mapped = moea_page_is_mapped, 366 367 /* Internal interfaces */ 368 .bootstrap = moea_bootstrap, 369 .cpu_bootstrap = moea_cpu_bootstrap, 370 .mapdev_attr = moea_mapdev_attr, 371 .mapdev = moea_mapdev, 372 .unmapdev = moea_unmapdev, 373 .kextract = moea_kextract, 374 .kenter = moea_kenter, 375 .kenter_attr = moea_kenter_attr, 376 .dev_direct_mapped = moea_dev_direct_mapped, 377 .dumpsys_pa_init = moea_scan_init, 378 .dumpsys_map_chunk = moea_dumpsys_map, 379 .map_user_ptr = moea_map_user_ptr, 380 .decode_kernel_ptr = moea_decode_kernel_ptr, 381 }; 382 383 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods); 384 385 static __inline uint32_t 386 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 387 { 388 uint32_t pte_lo; 389 int i; 390 391 if (ma != VM_MEMATTR_DEFAULT) { 392 switch (ma) { 393 case VM_MEMATTR_UNCACHEABLE: 394 return (PTE_I | PTE_G); 395 case VM_MEMATTR_CACHEABLE: 396 return (PTE_M); 397 case VM_MEMATTR_WRITE_COMBINING: 398 case VM_MEMATTR_WRITE_BACK: 399 case VM_MEMATTR_PREFETCHABLE: 400 return (PTE_I); 401 case VM_MEMATTR_WRITE_THROUGH: 402 return (PTE_W | PTE_M); 403 } 404 } 405 406 /* 407 * Assume the page is cache inhibited and access is guarded unless 408 * it's in our available memory array. 409 */ 410 pte_lo = PTE_I | PTE_G; 411 for (i = 0; i < pregions_sz; i++) { 412 if ((pa >= pregions[i].mr_start) && 413 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 414 pte_lo = PTE_M; 415 break; 416 } 417 } 418 419 return pte_lo; 420 } 421 422 /* 423 * Translate OFW translations into VM attributes. 424 */ 425 static __inline vm_memattr_t 426 moea_bootstrap_convert_wimg(uint32_t mode) 427 { 428 429 switch (mode) { 430 case (PTE_I | PTE_G): 431 /* PCI device memory */ 432 return VM_MEMATTR_UNCACHEABLE; 433 case (PTE_M): 434 /* Explicitly coherent */ 435 return VM_MEMATTR_CACHEABLE; 436 case 0: /* Default claim */ 437 case 2: /* Alternate PP bits set by OF for the original payload */ 438 /* "Normal" memory. */ 439 return VM_MEMATTR_DEFAULT; 440 441 default: 442 /* Err on the side of caution for unknowns */ 443 /* XXX should we panic instead? */ 444 return VM_MEMATTR_UNCACHEABLE; 445 } 446 } 447 448 static void 449 tlbie(vm_offset_t va) 450 { 451 452 mtx_lock_spin(&tlbie_mtx); 453 __asm __volatile("ptesync"); 454 __asm __volatile("tlbie %0" :: "r"(va)); 455 __asm __volatile("eieio; tlbsync; ptesync"); 456 mtx_unlock_spin(&tlbie_mtx); 457 } 458 459 static void 460 tlbia(void) 461 { 462 vm_offset_t va; 463 464 for (va = 0; va < 0x00040000; va += 0x00001000) { 465 __asm __volatile("tlbie %0" :: "r"(va)); 466 powerpc_sync(); 467 } 468 __asm __volatile("tlbsync"); 469 powerpc_sync(); 470 } 471 472 static __inline int 473 va_to_sr(u_int *sr, vm_offset_t va) 474 { 475 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 476 } 477 478 static __inline u_int 479 va_to_pteg(u_int sr, vm_offset_t addr) 480 { 481 u_int hash; 482 483 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 484 ADDR_PIDX_SHFT); 485 return (hash & moea_pteg_mask); 486 } 487 488 static __inline struct pvo_head * 489 vm_page_to_pvoh(vm_page_t m) 490 { 491 492 return (&m->md.mdpg_pvoh); 493 } 494 495 static __inline void 496 moea_attr_clear(vm_page_t m, int ptebit) 497 { 498 499 rw_assert(&pvh_global_lock, RA_WLOCKED); 500 m->md.mdpg_attrs &= ~ptebit; 501 } 502 503 static __inline int 504 moea_attr_fetch(vm_page_t m) 505 { 506 507 return (m->md.mdpg_attrs); 508 } 509 510 static __inline void 511 moea_attr_save(vm_page_t m, int ptebit) 512 { 513 514 rw_assert(&pvh_global_lock, RA_WLOCKED); 515 m->md.mdpg_attrs |= ptebit; 516 } 517 518 static __inline int 519 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 520 { 521 if (pt->pte_hi == pvo_pt->pte_hi) 522 return (1); 523 524 return (0); 525 } 526 527 static __inline int 528 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 529 { 530 return (pt->pte_hi & ~PTE_VALID) == 531 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 532 ((va >> ADDR_API_SHFT) & PTE_API) | which); 533 } 534 535 static __inline void 536 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 537 { 538 539 mtx_assert(&moea_table_mutex, MA_OWNED); 540 541 /* 542 * Construct a PTE. Default to IMB initially. Valid bit only gets 543 * set when the real pte is set in memory. 544 * 545 * Note: Don't set the valid bit for correct operation of tlb update. 546 */ 547 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 548 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 549 pt->pte_lo = pte_lo; 550 } 551 552 static __inline void 553 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 554 { 555 556 mtx_assert(&moea_table_mutex, MA_OWNED); 557 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 558 } 559 560 static __inline void 561 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 562 { 563 564 mtx_assert(&moea_table_mutex, MA_OWNED); 565 566 /* 567 * As shown in Section 7.6.3.2.3 568 */ 569 pt->pte_lo &= ~ptebit; 570 tlbie(va); 571 } 572 573 static __inline void 574 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 575 { 576 577 mtx_assert(&moea_table_mutex, MA_OWNED); 578 pvo_pt->pte_hi |= PTE_VALID; 579 580 /* 581 * Update the PTE as defined in section 7.6.3.1. 582 * Note that the REF/CHG bits are from pvo_pt and thus should have 583 * been saved so this routine can restore them (if desired). 584 */ 585 pt->pte_lo = pvo_pt->pte_lo; 586 powerpc_sync(); 587 pt->pte_hi = pvo_pt->pte_hi; 588 powerpc_sync(); 589 moea_pte_valid++; 590 } 591 592 static __inline void 593 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 594 { 595 596 mtx_assert(&moea_table_mutex, MA_OWNED); 597 pvo_pt->pte_hi &= ~PTE_VALID; 598 599 /* 600 * Force the reg & chg bits back into the PTEs. 601 */ 602 powerpc_sync(); 603 604 /* 605 * Invalidate the pte. 606 */ 607 pt->pte_hi &= ~PTE_VALID; 608 609 tlbie(va); 610 611 /* 612 * Save the reg & chg bits. 613 */ 614 moea_pte_synch(pt, pvo_pt); 615 moea_pte_valid--; 616 } 617 618 static __inline void 619 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 620 { 621 622 /* 623 * Invalidate the PTE 624 */ 625 moea_pte_unset(pt, pvo_pt, va); 626 moea_pte_set(pt, pvo_pt); 627 } 628 629 /* 630 * Quick sort callout for comparing memory regions. 631 */ 632 static int om_cmp(const void *a, const void *b); 633 634 static int 635 om_cmp(const void *a, const void *b) 636 { 637 const struct ofw_map *mapa; 638 const struct ofw_map *mapb; 639 640 mapa = a; 641 mapb = b; 642 if (mapa->om_pa < mapb->om_pa) 643 return (-1); 644 else if (mapa->om_pa > mapb->om_pa) 645 return (1); 646 else 647 return (0); 648 } 649 650 void 651 moea_cpu_bootstrap(int ap) 652 { 653 u_int sdr; 654 int i; 655 656 if (ap) { 657 powerpc_sync(); 658 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 659 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 660 isync(); 661 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 662 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 663 isync(); 664 } 665 666 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 667 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 668 isync(); 669 670 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 671 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 672 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 673 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 674 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 675 isync(); 676 677 for (i = 0; i < 16; i++) 678 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 679 powerpc_sync(); 680 681 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 682 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 683 isync(); 684 685 tlbia(); 686 } 687 688 void 689 moea_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 690 { 691 ihandle_t mmui; 692 phandle_t chosen, mmu; 693 int sz; 694 int i, j; 695 vm_size_t size, physsz, hwphyssz; 696 vm_offset_t pa, va, off; 697 void *dpcpu; 698 699 /* 700 * Map PCI memory space. 701 */ 702 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 703 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 704 705 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 706 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 707 708 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 709 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 710 711 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 712 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 713 714 powerpc_sync(); 715 716 /* map pci space */ 717 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 718 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 719 isync(); 720 721 /* set global direct map flag */ 722 hw_direct_map = 1; 723 724 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 725 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 726 727 for (i = 0; i < pregions_sz; i++) { 728 vm_offset_t pa; 729 vm_offset_t end; 730 731 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 732 pregions[i].mr_start, 733 pregions[i].mr_start + pregions[i].mr_size, 734 pregions[i].mr_size); 735 /* 736 * Install entries into the BAT table to allow all 737 * of physmem to be convered by on-demand BAT entries. 738 * The loop will sometimes set the same battable element 739 * twice, but that's fine since they won't be used for 740 * a while yet. 741 */ 742 pa = pregions[i].mr_start & 0xf0000000; 743 end = pregions[i].mr_start + pregions[i].mr_size; 744 do { 745 u_int n = pa >> ADDR_SR_SHFT; 746 747 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 748 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 749 pa += SEGMENT_LENGTH; 750 } while (pa < end); 751 } 752 753 if (PHYS_AVAIL_ENTRIES < regions_sz) 754 panic("moea_bootstrap: phys_avail too small"); 755 756 phys_avail_count = 0; 757 physsz = 0; 758 hwphyssz = 0; 759 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 760 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 761 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 762 regions[i].mr_start + regions[i].mr_size, 763 regions[i].mr_size); 764 if (hwphyssz != 0 && 765 (physsz + regions[i].mr_size) >= hwphyssz) { 766 if (physsz < hwphyssz) { 767 phys_avail[j] = regions[i].mr_start; 768 phys_avail[j + 1] = regions[i].mr_start + 769 hwphyssz - physsz; 770 physsz = hwphyssz; 771 phys_avail_count++; 772 } 773 break; 774 } 775 phys_avail[j] = regions[i].mr_start; 776 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 777 phys_avail_count++; 778 physsz += regions[i].mr_size; 779 } 780 781 /* Check for overlap with the kernel and exception vectors */ 782 for (j = 0; j < 2*phys_avail_count; j+=2) { 783 if (phys_avail[j] < EXC_LAST) 784 phys_avail[j] += EXC_LAST; 785 786 if (kernelstart >= phys_avail[j] && 787 kernelstart < phys_avail[j+1]) { 788 if (kernelend < phys_avail[j+1]) { 789 phys_avail[2*phys_avail_count] = 790 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 791 phys_avail[2*phys_avail_count + 1] = 792 phys_avail[j+1]; 793 phys_avail_count++; 794 } 795 796 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 797 } 798 799 if (kernelend >= phys_avail[j] && 800 kernelend < phys_avail[j+1]) { 801 if (kernelstart > phys_avail[j]) { 802 phys_avail[2*phys_avail_count] = phys_avail[j]; 803 phys_avail[2*phys_avail_count + 1] = 804 kernelstart & ~PAGE_MASK; 805 phys_avail_count++; 806 } 807 808 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 809 } 810 } 811 812 physmem = btoc(physsz); 813 814 /* 815 * Allocate PTEG table. 816 */ 817 #ifdef PTEGCOUNT 818 moea_pteg_count = PTEGCOUNT; 819 #else 820 moea_pteg_count = 0x1000; 821 822 while (moea_pteg_count < physmem) 823 moea_pteg_count <<= 1; 824 825 moea_pteg_count >>= 1; 826 #endif /* PTEGCOUNT */ 827 828 size = moea_pteg_count * sizeof(struct pteg); 829 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 830 size); 831 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 832 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 833 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 834 moea_pteg_mask = moea_pteg_count - 1; 835 836 /* 837 * Allocate pv/overflow lists. 838 */ 839 size = sizeof(struct pvo_head) * moea_pteg_count; 840 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 841 PAGE_SIZE); 842 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 843 for (i = 0; i < moea_pteg_count; i++) 844 LIST_INIT(&moea_pvo_table[i]); 845 846 /* 847 * Initialize the lock that synchronizes access to the pteg and pvo 848 * tables. 849 */ 850 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 851 MTX_RECURSE); 852 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 853 854 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 855 856 /* 857 * Initialise the unmanaged pvo pool. 858 */ 859 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 860 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 861 moea_bpvo_pool_index = 0; 862 863 /* 864 * Make sure kernel vsid is allocated as well as VSID 0. 865 */ 866 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 867 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 868 moea_vsid_bitmap[0] |= 1; 869 870 /* 871 * Initialize the kernel pmap (which is statically allocated). 872 */ 873 PMAP_LOCK_INIT(kernel_pmap); 874 for (i = 0; i < 16; i++) 875 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 876 CPU_FILL(&kernel_pmap->pm_active); 877 RB_INIT(&kernel_pmap->pmap_pvo); 878 879 /* 880 * Initialize the global pv list lock. 881 */ 882 rw_init(&pvh_global_lock, "pmap pv global"); 883 884 /* 885 * Set up the Open Firmware mappings 886 */ 887 chosen = OF_finddevice("/chosen"); 888 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 889 (mmu = OF_instance_to_package(mmui)) != -1 && 890 (sz = OF_getproplen(mmu, "translations")) != -1) { 891 translations = NULL; 892 for (i = 0; phys_avail[i] != 0; i += 2) { 893 if (phys_avail[i + 1] >= sz) { 894 translations = (struct ofw_map *)phys_avail[i]; 895 break; 896 } 897 } 898 if (translations == NULL) 899 panic("moea_bootstrap: no space to copy translations"); 900 bzero(translations, sz); 901 if (OF_getprop(mmu, "translations", translations, sz) == -1) 902 panic("moea_bootstrap: can't get ofw translations"); 903 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 904 sz /= sizeof(*translations); 905 qsort(translations, sz, sizeof (*translations), om_cmp); 906 for (i = 0; i < sz; i++) { 907 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 908 translations[i].om_pa, translations[i].om_va, 909 translations[i].om_len); 910 911 /* 912 * If the mapping is 1:1, let the RAM and device 913 * on-demand BAT tables take care of the translation. 914 * 915 * However, always enter mappings for segment 16, 916 * which is mixed-protection and therefore not 917 * compatible with a BAT entry. 918 */ 919 if ((translations[i].om_va >> ADDR_SR_SHFT) != 0xf && 920 translations[i].om_va == translations[i].om_pa) 921 continue; 922 923 /* Enter the pages */ 924 for (off = 0; off < translations[i].om_len; 925 off += PAGE_SIZE) 926 moea_kenter_attr(translations[i].om_va + off, 927 translations[i].om_pa + off, 928 moea_bootstrap_convert_wimg(translations[i].om_mode)); 929 } 930 } 931 932 /* 933 * Calculate the last available physical address. 934 */ 935 for (i = 0; phys_avail[i + 2] != 0; i += 2) 936 ; 937 Maxmem = powerpc_btop(phys_avail[i + 1]); 938 939 moea_cpu_bootstrap(0); 940 mtmsr(mfmsr() | PSL_DR | PSL_IR); 941 pmap_bootstrapped++; 942 943 /* 944 * Set the start and end of kva. 945 */ 946 virtual_avail = VM_MIN_KERNEL_ADDRESS; 947 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 948 949 /* 950 * Allocate a kernel stack with a guard page for thread0 and map it 951 * into the kernel page map. 952 */ 953 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 954 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 955 virtual_avail = va + kstack_pages * PAGE_SIZE; 956 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 957 thread0.td_kstack = va; 958 thread0.td_kstack_pages = kstack_pages; 959 for (i = 0; i < kstack_pages; i++) { 960 moea_kenter(va, pa); 961 pa += PAGE_SIZE; 962 va += PAGE_SIZE; 963 } 964 965 /* 966 * Allocate virtual address space for the message buffer. 967 */ 968 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 969 msgbufp = (struct msgbuf *)virtual_avail; 970 va = virtual_avail; 971 virtual_avail += round_page(msgbufsize); 972 while (va < virtual_avail) { 973 moea_kenter(va, pa); 974 pa += PAGE_SIZE; 975 va += PAGE_SIZE; 976 } 977 978 /* 979 * Allocate virtual address space for the dynamic percpu area. 980 */ 981 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 982 dpcpu = (void *)virtual_avail; 983 va = virtual_avail; 984 virtual_avail += DPCPU_SIZE; 985 while (va < virtual_avail) { 986 moea_kenter(va, pa); 987 pa += PAGE_SIZE; 988 va += PAGE_SIZE; 989 } 990 dpcpu_init(dpcpu, 0); 991 } 992 993 /* 994 * Activate a user pmap. The pmap must be activated before it's address 995 * space can be accessed in any way. 996 */ 997 void 998 moea_activate(struct thread *td) 999 { 1000 pmap_t pm, pmr; 1001 1002 /* 1003 * Load all the data we need up front to encourage the compiler to 1004 * not issue any loads while we have interrupts disabled below. 1005 */ 1006 pm = &td->td_proc->p_vmspace->vm_pmap; 1007 pmr = pm->pmap_phys; 1008 1009 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1010 PCPU_SET(curpmap, pmr); 1011 1012 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1013 } 1014 1015 void 1016 moea_deactivate(struct thread *td) 1017 { 1018 pmap_t pm; 1019 1020 pm = &td->td_proc->p_vmspace->vm_pmap; 1021 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1022 PCPU_SET(curpmap, NULL); 1023 } 1024 1025 void 1026 moea_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1027 { 1028 struct pvo_entry key, *pvo; 1029 1030 PMAP_LOCK(pm); 1031 key.pvo_vaddr = sva; 1032 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1033 pvo != NULL && PVO_VADDR(pvo) < eva; 1034 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1035 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1036 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1037 pvo->pvo_vaddr &= ~PVO_WIRED; 1038 pm->pm_stats.wired_count--; 1039 } 1040 PMAP_UNLOCK(pm); 1041 } 1042 1043 void 1044 moea_copy_page(vm_page_t msrc, vm_page_t mdst) 1045 { 1046 vm_offset_t dst; 1047 vm_offset_t src; 1048 1049 dst = VM_PAGE_TO_PHYS(mdst); 1050 src = VM_PAGE_TO_PHYS(msrc); 1051 1052 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1053 } 1054 1055 void 1056 moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1057 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1058 { 1059 void *a_cp, *b_cp; 1060 vm_offset_t a_pg_offset, b_pg_offset; 1061 int cnt; 1062 1063 while (xfersize > 0) { 1064 a_pg_offset = a_offset & PAGE_MASK; 1065 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1066 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1067 a_pg_offset; 1068 b_pg_offset = b_offset & PAGE_MASK; 1069 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1070 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1071 b_pg_offset; 1072 bcopy(a_cp, b_cp, cnt); 1073 a_offset += cnt; 1074 b_offset += cnt; 1075 xfersize -= cnt; 1076 } 1077 } 1078 1079 /* 1080 * Zero a page of physical memory by temporarily mapping it into the tlb. 1081 */ 1082 void 1083 moea_zero_page(vm_page_t m) 1084 { 1085 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1086 1087 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1088 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1089 } 1090 1091 void 1092 moea_zero_page_area(vm_page_t m, int off, int size) 1093 { 1094 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1095 void *va = (void *)(pa + off); 1096 1097 bzero(va, size); 1098 } 1099 1100 vm_offset_t 1101 moea_quick_enter_page(vm_page_t m) 1102 { 1103 1104 return (VM_PAGE_TO_PHYS(m)); 1105 } 1106 1107 void 1108 moea_quick_remove_page(vm_offset_t addr) 1109 { 1110 } 1111 1112 boolean_t 1113 moea_page_is_mapped(vm_page_t m) 1114 { 1115 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1116 } 1117 1118 /* 1119 * Map the given physical page at the specified virtual address in the 1120 * target pmap with the protection requested. If specified the page 1121 * will be wired down. 1122 */ 1123 int 1124 moea_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1125 u_int flags, int8_t psind) 1126 { 1127 int error; 1128 1129 for (;;) { 1130 rw_wlock(&pvh_global_lock); 1131 PMAP_LOCK(pmap); 1132 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1133 rw_wunlock(&pvh_global_lock); 1134 PMAP_UNLOCK(pmap); 1135 if (error != ENOMEM) 1136 return (KERN_SUCCESS); 1137 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1138 return (KERN_RESOURCE_SHORTAGE); 1139 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1140 vm_wait(NULL); 1141 } 1142 } 1143 1144 /* 1145 * Map the given physical page at the specified virtual address in the 1146 * target pmap with the protection requested. If specified the page 1147 * will be wired down. 1148 * 1149 * The global pvh and pmap must be locked. 1150 */ 1151 static int 1152 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1153 u_int flags, int8_t psind __unused) 1154 { 1155 struct pvo_head *pvo_head; 1156 uma_zone_t zone; 1157 u_int pte_lo, pvo_flags; 1158 int error; 1159 1160 if (pmap_bootstrapped) 1161 rw_assert(&pvh_global_lock, RA_WLOCKED); 1162 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1163 if ((m->oflags & VPO_UNMANAGED) == 0) { 1164 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1165 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1166 else 1167 VM_OBJECT_ASSERT_LOCKED(m->object); 1168 } 1169 1170 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1171 pvo_head = &moea_pvo_kunmanaged; 1172 zone = moea_upvo_zone; 1173 pvo_flags = 0; 1174 } else { 1175 pvo_head = vm_page_to_pvoh(m); 1176 zone = moea_mpvo_zone; 1177 pvo_flags = PVO_MANAGED; 1178 } 1179 1180 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1181 1182 if (prot & VM_PROT_WRITE) { 1183 pte_lo |= PTE_BW; 1184 if (pmap_bootstrapped && 1185 (m->oflags & VPO_UNMANAGED) == 0) 1186 vm_page_aflag_set(m, PGA_WRITEABLE); 1187 } else 1188 pte_lo |= PTE_BR; 1189 1190 if ((flags & PMAP_ENTER_WIRED) != 0) 1191 pvo_flags |= PVO_WIRED; 1192 1193 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1194 pte_lo, pvo_flags); 1195 1196 /* 1197 * Flush the real page from the instruction cache. This has be done 1198 * for all user mappings to prevent information leakage via the 1199 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1200 * mapping for a page. 1201 */ 1202 if (pmap != kernel_pmap && error == ENOENT && 1203 (pte_lo & (PTE_I | PTE_G)) == 0) 1204 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1205 1206 return (error); 1207 } 1208 1209 /* 1210 * Maps a sequence of resident pages belonging to the same object. 1211 * The sequence begins with the given page m_start. This page is 1212 * mapped at the given virtual address start. Each subsequent page is 1213 * mapped at a virtual address that is offset from start by the same 1214 * amount as the page is offset from m_start within the object. The 1215 * last page in the sequence is the page with the largest offset from 1216 * m_start that can be mapped at a virtual address less than the given 1217 * virtual address end. Not every virtual page between start and end 1218 * is mapped; only those for which a resident page exists with the 1219 * corresponding offset from m_start are mapped. 1220 */ 1221 void 1222 moea_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1223 vm_page_t m_start, vm_prot_t prot) 1224 { 1225 vm_page_t m; 1226 vm_pindex_t diff, psize; 1227 1228 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1229 1230 psize = atop(end - start); 1231 m = m_start; 1232 rw_wlock(&pvh_global_lock); 1233 PMAP_LOCK(pm); 1234 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1235 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1236 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_QUICK_LOCKED, 1237 0); 1238 m = TAILQ_NEXT(m, listq); 1239 } 1240 rw_wunlock(&pvh_global_lock); 1241 PMAP_UNLOCK(pm); 1242 } 1243 1244 void 1245 moea_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1246 vm_prot_t prot) 1247 { 1248 1249 rw_wlock(&pvh_global_lock); 1250 PMAP_LOCK(pm); 1251 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1252 PMAP_ENTER_QUICK_LOCKED, 0); 1253 rw_wunlock(&pvh_global_lock); 1254 PMAP_UNLOCK(pm); 1255 } 1256 1257 vm_paddr_t 1258 moea_extract(pmap_t pm, vm_offset_t va) 1259 { 1260 struct pvo_entry *pvo; 1261 vm_paddr_t pa; 1262 1263 PMAP_LOCK(pm); 1264 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1265 if (pvo == NULL) 1266 pa = 0; 1267 else 1268 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1269 PMAP_UNLOCK(pm); 1270 return (pa); 1271 } 1272 1273 /* 1274 * Atomically extract and hold the physical page with the given 1275 * pmap and virtual address pair if that mapping permits the given 1276 * protection. 1277 */ 1278 vm_page_t 1279 moea_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1280 { 1281 struct pvo_entry *pvo; 1282 vm_page_t m; 1283 1284 m = NULL; 1285 PMAP_LOCK(pmap); 1286 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1287 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1288 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1289 (prot & VM_PROT_WRITE) == 0)) { 1290 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1291 if (!vm_page_wire_mapped(m)) 1292 m = NULL; 1293 } 1294 PMAP_UNLOCK(pmap); 1295 return (m); 1296 } 1297 1298 void 1299 moea_init() 1300 { 1301 1302 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1303 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1304 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1305 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1306 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1307 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1308 moea_initialized = TRUE; 1309 } 1310 1311 boolean_t 1312 moea_is_referenced(vm_page_t m) 1313 { 1314 boolean_t rv; 1315 1316 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1317 ("moea_is_referenced: page %p is not managed", m)); 1318 rw_wlock(&pvh_global_lock); 1319 rv = moea_query_bit(m, PTE_REF); 1320 rw_wunlock(&pvh_global_lock); 1321 return (rv); 1322 } 1323 1324 boolean_t 1325 moea_is_modified(vm_page_t m) 1326 { 1327 boolean_t rv; 1328 1329 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1330 ("moea_is_modified: page %p is not managed", m)); 1331 1332 /* 1333 * If the page is not busied then this check is racy. 1334 */ 1335 if (!pmap_page_is_write_mapped(m)) 1336 return (FALSE); 1337 1338 rw_wlock(&pvh_global_lock); 1339 rv = moea_query_bit(m, PTE_CHG); 1340 rw_wunlock(&pvh_global_lock); 1341 return (rv); 1342 } 1343 1344 boolean_t 1345 moea_is_prefaultable(pmap_t pmap, vm_offset_t va) 1346 { 1347 struct pvo_entry *pvo; 1348 boolean_t rv; 1349 1350 PMAP_LOCK(pmap); 1351 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1352 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1353 PMAP_UNLOCK(pmap); 1354 return (rv); 1355 } 1356 1357 void 1358 moea_clear_modify(vm_page_t m) 1359 { 1360 1361 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1362 ("moea_clear_modify: page %p is not managed", m)); 1363 vm_page_assert_busied(m); 1364 1365 if (!pmap_page_is_write_mapped(m)) 1366 return; 1367 rw_wlock(&pvh_global_lock); 1368 moea_clear_bit(m, PTE_CHG); 1369 rw_wunlock(&pvh_global_lock); 1370 } 1371 1372 /* 1373 * Clear the write and modified bits in each of the given page's mappings. 1374 */ 1375 void 1376 moea_remove_write(vm_page_t m) 1377 { 1378 struct pvo_entry *pvo; 1379 struct pte *pt; 1380 pmap_t pmap; 1381 u_int lo; 1382 1383 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1384 ("moea_remove_write: page %p is not managed", m)); 1385 vm_page_assert_busied(m); 1386 1387 if (!pmap_page_is_write_mapped(m)) 1388 return; 1389 rw_wlock(&pvh_global_lock); 1390 lo = moea_attr_fetch(m); 1391 powerpc_sync(); 1392 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1393 pmap = pvo->pvo_pmap; 1394 PMAP_LOCK(pmap); 1395 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1396 pt = moea_pvo_to_pte(pvo, -1); 1397 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1398 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1399 if (pt != NULL) { 1400 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1401 lo |= pvo->pvo_pte.pte.pte_lo; 1402 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1403 moea_pte_change(pt, &pvo->pvo_pte.pte, 1404 pvo->pvo_vaddr); 1405 mtx_unlock(&moea_table_mutex); 1406 } 1407 } 1408 PMAP_UNLOCK(pmap); 1409 } 1410 if ((lo & PTE_CHG) != 0) { 1411 moea_attr_clear(m, PTE_CHG); 1412 vm_page_dirty(m); 1413 } 1414 vm_page_aflag_clear(m, PGA_WRITEABLE); 1415 rw_wunlock(&pvh_global_lock); 1416 } 1417 1418 /* 1419 * moea_ts_referenced: 1420 * 1421 * Return a count of reference bits for a page, clearing those bits. 1422 * It is not necessary for every reference bit to be cleared, but it 1423 * is necessary that 0 only be returned when there are truly no 1424 * reference bits set. 1425 * 1426 * XXX: The exact number of bits to check and clear is a matter that 1427 * should be tested and standardized at some point in the future for 1428 * optimal aging of shared pages. 1429 */ 1430 int 1431 moea_ts_referenced(vm_page_t m) 1432 { 1433 int count; 1434 1435 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1436 ("moea_ts_referenced: page %p is not managed", m)); 1437 rw_wlock(&pvh_global_lock); 1438 count = moea_clear_bit(m, PTE_REF); 1439 rw_wunlock(&pvh_global_lock); 1440 return (count); 1441 } 1442 1443 /* 1444 * Modify the WIMG settings of all mappings for a page. 1445 */ 1446 void 1447 moea_page_set_memattr(vm_page_t m, vm_memattr_t ma) 1448 { 1449 struct pvo_entry *pvo; 1450 struct pvo_head *pvo_head; 1451 struct pte *pt; 1452 pmap_t pmap; 1453 u_int lo; 1454 1455 if ((m->oflags & VPO_UNMANAGED) != 0) { 1456 m->md.mdpg_cache_attrs = ma; 1457 return; 1458 } 1459 1460 rw_wlock(&pvh_global_lock); 1461 pvo_head = vm_page_to_pvoh(m); 1462 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1463 1464 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1465 pmap = pvo->pvo_pmap; 1466 PMAP_LOCK(pmap); 1467 pt = moea_pvo_to_pte(pvo, -1); 1468 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1469 pvo->pvo_pte.pte.pte_lo |= lo; 1470 if (pt != NULL) { 1471 moea_pte_change(pt, &pvo->pvo_pte.pte, 1472 pvo->pvo_vaddr); 1473 if (pvo->pvo_pmap == kernel_pmap) 1474 isync(); 1475 } 1476 mtx_unlock(&moea_table_mutex); 1477 PMAP_UNLOCK(pmap); 1478 } 1479 m->md.mdpg_cache_attrs = ma; 1480 rw_wunlock(&pvh_global_lock); 1481 } 1482 1483 /* 1484 * Map a wired page into kernel virtual address space. 1485 */ 1486 void 1487 moea_kenter(vm_offset_t va, vm_paddr_t pa) 1488 { 1489 1490 moea_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1491 } 1492 1493 void 1494 moea_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1495 { 1496 u_int pte_lo; 1497 int error; 1498 1499 #if 0 1500 if (va < VM_MIN_KERNEL_ADDRESS) 1501 panic("moea_kenter: attempt to enter non-kernel address %#x", 1502 va); 1503 #endif 1504 1505 pte_lo = moea_calc_wimg(pa, ma); 1506 1507 PMAP_LOCK(kernel_pmap); 1508 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1509 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1510 1511 if (error != 0 && error != ENOENT) 1512 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1513 pa, error); 1514 1515 PMAP_UNLOCK(kernel_pmap); 1516 } 1517 1518 /* 1519 * Extract the physical page address associated with the given kernel virtual 1520 * address. 1521 */ 1522 vm_paddr_t 1523 moea_kextract(vm_offset_t va) 1524 { 1525 struct pvo_entry *pvo; 1526 vm_paddr_t pa; 1527 1528 /* 1529 * Allow direct mappings on 32-bit OEA 1530 */ 1531 if (va < VM_MIN_KERNEL_ADDRESS) { 1532 return (va); 1533 } 1534 1535 PMAP_LOCK(kernel_pmap); 1536 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1537 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1538 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1539 PMAP_UNLOCK(kernel_pmap); 1540 return (pa); 1541 } 1542 1543 /* 1544 * Remove a wired page from kernel virtual address space. 1545 */ 1546 void 1547 moea_kremove(vm_offset_t va) 1548 { 1549 1550 moea_remove(kernel_pmap, va, va + PAGE_SIZE); 1551 } 1552 1553 /* 1554 * Provide a kernel pointer corresponding to a given userland pointer. 1555 * The returned pointer is valid until the next time this function is 1556 * called in this thread. This is used internally in copyin/copyout. 1557 */ 1558 int 1559 moea_map_user_ptr(pmap_t pm, volatile const void *uaddr, 1560 void **kaddr, size_t ulen, size_t *klen) 1561 { 1562 size_t l; 1563 register_t vsid; 1564 1565 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1566 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1567 if (l > ulen) 1568 l = ulen; 1569 if (klen) 1570 *klen = l; 1571 else if (l != ulen) 1572 return (EFAULT); 1573 1574 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1575 1576 /* Mark segment no-execute */ 1577 vsid |= SR_N; 1578 1579 /* If we have already set this VSID, we can just return */ 1580 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1581 return (0); 1582 1583 __asm __volatile("isync"); 1584 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1585 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1586 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1587 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1588 1589 return (0); 1590 } 1591 1592 /* 1593 * Figure out where a given kernel pointer (usually in a fault) points 1594 * to from the VM's perspective, potentially remapping into userland's 1595 * address space. 1596 */ 1597 static int 1598 moea_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1599 vm_offset_t *decoded_addr) 1600 { 1601 vm_offset_t user_sr; 1602 1603 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1604 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1605 addr &= ADDR_PIDX | ADDR_POFF; 1606 addr |= user_sr << ADDR_SR_SHFT; 1607 *decoded_addr = addr; 1608 *is_user = 1; 1609 } else { 1610 *decoded_addr = addr; 1611 *is_user = 0; 1612 } 1613 1614 return (0); 1615 } 1616 1617 /* 1618 * Map a range of physical addresses into kernel virtual address space. 1619 * 1620 * The value passed in *virt is a suggested virtual address for the mapping. 1621 * Architectures which can support a direct-mapped physical to virtual region 1622 * can return the appropriate address within that region, leaving '*virt' 1623 * unchanged. We cannot and therefore do not; *virt is updated with the 1624 * first usable address after the mapped region. 1625 */ 1626 vm_offset_t 1627 moea_map(vm_offset_t *virt, vm_paddr_t pa_start, 1628 vm_paddr_t pa_end, int prot) 1629 { 1630 vm_offset_t sva, va; 1631 1632 sva = *virt; 1633 va = sva; 1634 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1635 moea_kenter(va, pa_start); 1636 *virt = va; 1637 return (sva); 1638 } 1639 1640 /* 1641 * Returns true if the pmap's pv is one of the first 1642 * 16 pvs linked to from this page. This count may 1643 * be changed upwards or downwards in the future; it 1644 * is only necessary that true be returned for a small 1645 * subset of pmaps for proper page aging. 1646 */ 1647 boolean_t 1648 moea_page_exists_quick(pmap_t pmap, vm_page_t m) 1649 { 1650 int loops; 1651 struct pvo_entry *pvo; 1652 boolean_t rv; 1653 1654 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1655 ("moea_page_exists_quick: page %p is not managed", m)); 1656 loops = 0; 1657 rv = FALSE; 1658 rw_wlock(&pvh_global_lock); 1659 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1660 if (pvo->pvo_pmap == pmap) { 1661 rv = TRUE; 1662 break; 1663 } 1664 if (++loops >= 16) 1665 break; 1666 } 1667 rw_wunlock(&pvh_global_lock); 1668 return (rv); 1669 } 1670 1671 void 1672 moea_page_init(vm_page_t m) 1673 { 1674 1675 m->md.mdpg_attrs = 0; 1676 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1677 LIST_INIT(&m->md.mdpg_pvoh); 1678 } 1679 1680 /* 1681 * Return the number of managed mappings to the given physical page 1682 * that are wired. 1683 */ 1684 int 1685 moea_page_wired_mappings(vm_page_t m) 1686 { 1687 struct pvo_entry *pvo; 1688 int count; 1689 1690 count = 0; 1691 if ((m->oflags & VPO_UNMANAGED) != 0) 1692 return (count); 1693 rw_wlock(&pvh_global_lock); 1694 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1695 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1696 count++; 1697 rw_wunlock(&pvh_global_lock); 1698 return (count); 1699 } 1700 1701 static u_int moea_vsidcontext; 1702 1703 int 1704 moea_pinit(pmap_t pmap) 1705 { 1706 int i, mask; 1707 u_int entropy; 1708 1709 RB_INIT(&pmap->pmap_pvo); 1710 1711 entropy = 0; 1712 __asm __volatile("mftb %0" : "=r"(entropy)); 1713 1714 if ((pmap->pmap_phys = (pmap_t)moea_kextract((vm_offset_t)pmap)) 1715 == NULL) { 1716 pmap->pmap_phys = pmap; 1717 } 1718 1719 mtx_lock(&moea_vsid_mutex); 1720 /* 1721 * Allocate some segment registers for this pmap. 1722 */ 1723 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1724 u_int hash, n; 1725 1726 /* 1727 * Create a new value by mutiplying by a prime and adding in 1728 * entropy from the timebase register. This is to make the 1729 * VSID more random so that the PT hash function collides 1730 * less often. (Note that the prime casues gcc to do shifts 1731 * instead of a multiply.) 1732 */ 1733 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1734 hash = moea_vsidcontext & (NPMAPS - 1); 1735 if (hash == 0) /* 0 is special, avoid it */ 1736 continue; 1737 n = hash >> 5; 1738 mask = 1 << (hash & (VSID_NBPW - 1)); 1739 hash = (moea_vsidcontext & 0xfffff); 1740 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1741 /* anything free in this bucket? */ 1742 if (moea_vsid_bitmap[n] == 0xffffffff) { 1743 entropy = (moea_vsidcontext >> 20); 1744 continue; 1745 } 1746 i = ffs(~moea_vsid_bitmap[n]) - 1; 1747 mask = 1 << i; 1748 hash &= rounddown2(0xfffff, VSID_NBPW); 1749 hash |= i; 1750 } 1751 KASSERT(!(moea_vsid_bitmap[n] & mask), 1752 ("Allocating in-use VSID group %#x\n", hash)); 1753 moea_vsid_bitmap[n] |= mask; 1754 for (i = 0; i < 16; i++) 1755 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1756 mtx_unlock(&moea_vsid_mutex); 1757 return (1); 1758 } 1759 1760 mtx_unlock(&moea_vsid_mutex); 1761 panic("moea_pinit: out of segments"); 1762 } 1763 1764 /* 1765 * Initialize the pmap associated with process 0. 1766 */ 1767 void 1768 moea_pinit0(pmap_t pm) 1769 { 1770 1771 PMAP_LOCK_INIT(pm); 1772 moea_pinit(pm); 1773 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1774 } 1775 1776 /* 1777 * Set the physical protection on the specified range of this map as requested. 1778 */ 1779 void 1780 moea_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1781 vm_prot_t prot) 1782 { 1783 struct pvo_entry *pvo, *tpvo, key; 1784 struct pte *pt; 1785 1786 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1787 ("moea_protect: non current pmap")); 1788 1789 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1790 moea_remove(pm, sva, eva); 1791 return; 1792 } 1793 1794 rw_wlock(&pvh_global_lock); 1795 PMAP_LOCK(pm); 1796 key.pvo_vaddr = sva; 1797 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1798 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1799 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1800 1801 /* 1802 * Grab the PTE pointer before we diddle with the cached PTE 1803 * copy. 1804 */ 1805 pt = moea_pvo_to_pte(pvo, -1); 1806 /* 1807 * Change the protection of the page. 1808 */ 1809 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1810 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1811 1812 /* 1813 * If the PVO is in the page table, update that pte as well. 1814 */ 1815 if (pt != NULL) { 1816 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1817 mtx_unlock(&moea_table_mutex); 1818 } 1819 } 1820 rw_wunlock(&pvh_global_lock); 1821 PMAP_UNLOCK(pm); 1822 } 1823 1824 /* 1825 * Map a list of wired pages into kernel virtual address space. This is 1826 * intended for temporary mappings which do not need page modification or 1827 * references recorded. Existing mappings in the region are overwritten. 1828 */ 1829 void 1830 moea_qenter(vm_offset_t sva, vm_page_t *m, int count) 1831 { 1832 vm_offset_t va; 1833 1834 va = sva; 1835 while (count-- > 0) { 1836 moea_kenter(va, VM_PAGE_TO_PHYS(*m)); 1837 va += PAGE_SIZE; 1838 m++; 1839 } 1840 } 1841 1842 /* 1843 * Remove page mappings from kernel virtual address space. Intended for 1844 * temporary mappings entered by moea_qenter. 1845 */ 1846 void 1847 moea_qremove(vm_offset_t sva, int count) 1848 { 1849 vm_offset_t va; 1850 1851 va = sva; 1852 while (count-- > 0) { 1853 moea_kremove(va); 1854 va += PAGE_SIZE; 1855 } 1856 } 1857 1858 void 1859 moea_release(pmap_t pmap) 1860 { 1861 int idx, mask; 1862 1863 /* 1864 * Free segment register's VSID 1865 */ 1866 if (pmap->pm_sr[0] == 0) 1867 panic("moea_release"); 1868 1869 mtx_lock(&moea_vsid_mutex); 1870 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1871 mask = 1 << (idx % VSID_NBPW); 1872 idx /= VSID_NBPW; 1873 moea_vsid_bitmap[idx] &= ~mask; 1874 mtx_unlock(&moea_vsid_mutex); 1875 } 1876 1877 /* 1878 * Remove the given range of addresses from the specified map. 1879 */ 1880 void 1881 moea_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1882 { 1883 struct pvo_entry *pvo, *tpvo, key; 1884 1885 rw_wlock(&pvh_global_lock); 1886 PMAP_LOCK(pm); 1887 key.pvo_vaddr = sva; 1888 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1889 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1890 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1891 moea_pvo_remove(pvo, -1); 1892 } 1893 PMAP_UNLOCK(pm); 1894 rw_wunlock(&pvh_global_lock); 1895 } 1896 1897 /* 1898 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1899 * will reflect changes in pte's back to the vm_page. 1900 */ 1901 void 1902 moea_remove_all(vm_page_t m) 1903 { 1904 struct pvo_head *pvo_head; 1905 struct pvo_entry *pvo, *next_pvo; 1906 pmap_t pmap; 1907 1908 rw_wlock(&pvh_global_lock); 1909 pvo_head = vm_page_to_pvoh(m); 1910 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1911 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1912 1913 pmap = pvo->pvo_pmap; 1914 PMAP_LOCK(pmap); 1915 moea_pvo_remove(pvo, -1); 1916 PMAP_UNLOCK(pmap); 1917 } 1918 if ((m->a.flags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1919 moea_attr_clear(m, PTE_CHG); 1920 vm_page_dirty(m); 1921 } 1922 vm_page_aflag_clear(m, PGA_WRITEABLE); 1923 rw_wunlock(&pvh_global_lock); 1924 } 1925 1926 /* 1927 * Allocate a physical page of memory directly from the phys_avail map. 1928 * Can only be called from moea_bootstrap before avail start and end are 1929 * calculated. 1930 */ 1931 static vm_offset_t 1932 moea_bootstrap_alloc(vm_size_t size, u_int align) 1933 { 1934 vm_offset_t s, e; 1935 int i, j; 1936 1937 size = round_page(size); 1938 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1939 if (align != 0) 1940 s = roundup2(phys_avail[i], align); 1941 else 1942 s = phys_avail[i]; 1943 e = s + size; 1944 1945 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1946 continue; 1947 1948 if (s == phys_avail[i]) { 1949 phys_avail[i] += size; 1950 } else if (e == phys_avail[i + 1]) { 1951 phys_avail[i + 1] -= size; 1952 } else { 1953 for (j = phys_avail_count * 2; j > i; j -= 2) { 1954 phys_avail[j] = phys_avail[j - 2]; 1955 phys_avail[j + 1] = phys_avail[j - 1]; 1956 } 1957 1958 phys_avail[i + 3] = phys_avail[i + 1]; 1959 phys_avail[i + 1] = s; 1960 phys_avail[i + 2] = e; 1961 phys_avail_count++; 1962 } 1963 1964 return (s); 1965 } 1966 panic("moea_bootstrap_alloc: could not allocate memory"); 1967 } 1968 1969 static void 1970 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1971 { 1972 __syncicache((void *)pa, len); 1973 } 1974 1975 static int 1976 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1977 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1978 { 1979 struct pvo_entry *pvo; 1980 u_int sr; 1981 int first; 1982 u_int ptegidx; 1983 int i; 1984 int bootstrap; 1985 1986 moea_pvo_enter_calls++; 1987 first = 0; 1988 bootstrap = 0; 1989 1990 /* 1991 * Compute the PTE Group index. 1992 */ 1993 va &= ~ADDR_POFF; 1994 sr = va_to_sr(pm->pm_sr, va); 1995 ptegidx = va_to_pteg(sr, va); 1996 1997 /* 1998 * Remove any existing mapping for this page. Reuse the pvo entry if 1999 * there is a mapping. 2000 */ 2001 mtx_lock(&moea_table_mutex); 2002 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2003 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2004 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 2005 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2006 (pte_lo & PTE_PP)) { 2007 /* 2008 * The PTE is not changing. Instead, this may 2009 * be a request to change the mapping's wired 2010 * attribute. 2011 */ 2012 mtx_unlock(&moea_table_mutex); 2013 if ((flags & PVO_WIRED) != 0 && 2014 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2015 pvo->pvo_vaddr |= PVO_WIRED; 2016 pm->pm_stats.wired_count++; 2017 } else if ((flags & PVO_WIRED) == 0 && 2018 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2019 pvo->pvo_vaddr &= ~PVO_WIRED; 2020 pm->pm_stats.wired_count--; 2021 } 2022 return (0); 2023 } 2024 moea_pvo_remove(pvo, -1); 2025 break; 2026 } 2027 } 2028 2029 /* 2030 * If we aren't overwriting a mapping, try to allocate. 2031 */ 2032 if (moea_initialized) { 2033 pvo = uma_zalloc(zone, M_NOWAIT); 2034 } else { 2035 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2036 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2037 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2038 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2039 } 2040 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2041 moea_bpvo_pool_index++; 2042 bootstrap = 1; 2043 } 2044 2045 if (pvo == NULL) { 2046 mtx_unlock(&moea_table_mutex); 2047 return (ENOMEM); 2048 } 2049 2050 moea_pvo_entries++; 2051 pvo->pvo_vaddr = va; 2052 pvo->pvo_pmap = pm; 2053 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2054 pvo->pvo_vaddr &= ~ADDR_POFF; 2055 if (flags & PVO_WIRED) 2056 pvo->pvo_vaddr |= PVO_WIRED; 2057 if (pvo_head != &moea_pvo_kunmanaged) 2058 pvo->pvo_vaddr |= PVO_MANAGED; 2059 if (bootstrap) 2060 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2061 2062 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2063 2064 /* 2065 * Add to pmap list 2066 */ 2067 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2068 2069 /* 2070 * Remember if the list was empty and therefore will be the first 2071 * item. 2072 */ 2073 if (LIST_FIRST(pvo_head) == NULL) 2074 first = 1; 2075 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2076 2077 if (pvo->pvo_vaddr & PVO_WIRED) 2078 pm->pm_stats.wired_count++; 2079 pm->pm_stats.resident_count++; 2080 2081 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2082 KASSERT(i < 8, ("Invalid PTE index")); 2083 if (i >= 0) { 2084 PVO_PTEGIDX_SET(pvo, i); 2085 } else { 2086 panic("moea_pvo_enter: overflow"); 2087 moea_pte_overflow++; 2088 } 2089 mtx_unlock(&moea_table_mutex); 2090 2091 return (first ? ENOENT : 0); 2092 } 2093 2094 static void 2095 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2096 { 2097 struct pte *pt; 2098 2099 /* 2100 * If there is an active pte entry, we need to deactivate it (and 2101 * save the ref & cfg bits). 2102 */ 2103 pt = moea_pvo_to_pte(pvo, pteidx); 2104 if (pt != NULL) { 2105 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2106 mtx_unlock(&moea_table_mutex); 2107 PVO_PTEGIDX_CLR(pvo); 2108 } else { 2109 moea_pte_overflow--; 2110 } 2111 2112 /* 2113 * Update our statistics. 2114 */ 2115 pvo->pvo_pmap->pm_stats.resident_count--; 2116 if (pvo->pvo_vaddr & PVO_WIRED) 2117 pvo->pvo_pmap->pm_stats.wired_count--; 2118 2119 /* 2120 * Remove this PVO from the PV and pmap lists. 2121 */ 2122 LIST_REMOVE(pvo, pvo_vlink); 2123 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2124 2125 /* 2126 * Save the REF/CHG bits into their cache if the page is managed. 2127 * Clear PGA_WRITEABLE if all mappings of the page have been removed. 2128 */ 2129 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2130 struct vm_page *pg; 2131 2132 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2133 if (pg != NULL) { 2134 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2135 (PTE_REF | PTE_CHG)); 2136 if (LIST_EMPTY(&pg->md.mdpg_pvoh)) 2137 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2138 } 2139 } 2140 2141 /* 2142 * Remove this from the overflow list and return it to the pool 2143 * if we aren't going to reuse it. 2144 */ 2145 LIST_REMOVE(pvo, pvo_olink); 2146 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2147 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2148 moea_upvo_zone, pvo); 2149 moea_pvo_entries--; 2150 moea_pvo_remove_calls++; 2151 } 2152 2153 static __inline int 2154 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2155 { 2156 int pteidx; 2157 2158 /* 2159 * We can find the actual pte entry without searching by grabbing 2160 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2161 * noticing the HID bit. 2162 */ 2163 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2164 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2165 pteidx ^= moea_pteg_mask * 8; 2166 2167 return (pteidx); 2168 } 2169 2170 static struct pvo_entry * 2171 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2172 { 2173 struct pvo_entry *pvo; 2174 int ptegidx; 2175 u_int sr; 2176 2177 va &= ~ADDR_POFF; 2178 sr = va_to_sr(pm->pm_sr, va); 2179 ptegidx = va_to_pteg(sr, va); 2180 2181 mtx_lock(&moea_table_mutex); 2182 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2183 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2184 if (pteidx_p) 2185 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2186 break; 2187 } 2188 } 2189 mtx_unlock(&moea_table_mutex); 2190 2191 return (pvo); 2192 } 2193 2194 static struct pte * 2195 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2196 { 2197 struct pte *pt; 2198 2199 /* 2200 * If we haven't been supplied the ptegidx, calculate it. 2201 */ 2202 if (pteidx == -1) { 2203 int ptegidx; 2204 u_int sr; 2205 2206 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2207 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2208 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2209 } 2210 2211 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2212 mtx_lock(&moea_table_mutex); 2213 2214 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2215 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2216 "valid pte index", pvo); 2217 } 2218 2219 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2220 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2221 "pvo but no valid pte", pvo); 2222 } 2223 2224 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2225 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2226 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2227 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2228 } 2229 2230 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2231 != 0) { 2232 panic("moea_pvo_to_pte: pvo %p pte does not match " 2233 "pte %p in moea_pteg_table", pvo, pt); 2234 } 2235 2236 mtx_assert(&moea_table_mutex, MA_OWNED); 2237 return (pt); 2238 } 2239 2240 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2241 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2242 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2243 } 2244 2245 mtx_unlock(&moea_table_mutex); 2246 return (NULL); 2247 } 2248 2249 /* 2250 * XXX: THIS STUFF SHOULD BE IN pte.c? 2251 */ 2252 int 2253 moea_pte_spill(vm_offset_t addr) 2254 { 2255 struct pvo_entry *source_pvo, *victim_pvo; 2256 struct pvo_entry *pvo; 2257 int ptegidx, i, j; 2258 u_int sr; 2259 struct pteg *pteg; 2260 struct pte *pt; 2261 2262 moea_pte_spills++; 2263 2264 sr = mfsrin(addr); 2265 ptegidx = va_to_pteg(sr, addr); 2266 2267 /* 2268 * Have to substitute some entry. Use the primary hash for this. 2269 * Use low bits of timebase as random generator. 2270 */ 2271 pteg = &moea_pteg_table[ptegidx]; 2272 mtx_lock(&moea_table_mutex); 2273 __asm __volatile("mftb %0" : "=r"(i)); 2274 i &= 7; 2275 pt = &pteg->pt[i]; 2276 2277 source_pvo = NULL; 2278 victim_pvo = NULL; 2279 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2280 /* 2281 * We need to find a pvo entry for this address. 2282 */ 2283 if (source_pvo == NULL && 2284 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2285 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2286 /* 2287 * Now found an entry to be spilled into the pteg. 2288 * The PTE is now valid, so we know it's active. 2289 */ 2290 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2291 2292 if (j >= 0) { 2293 PVO_PTEGIDX_SET(pvo, j); 2294 moea_pte_overflow--; 2295 mtx_unlock(&moea_table_mutex); 2296 return (1); 2297 } 2298 2299 source_pvo = pvo; 2300 2301 if (victim_pvo != NULL) 2302 break; 2303 } 2304 2305 /* 2306 * We also need the pvo entry of the victim we are replacing 2307 * so save the R & C bits of the PTE. 2308 */ 2309 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2310 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2311 victim_pvo = pvo; 2312 if (source_pvo != NULL) 2313 break; 2314 } 2315 } 2316 2317 if (source_pvo == NULL) { 2318 mtx_unlock(&moea_table_mutex); 2319 return (0); 2320 } 2321 2322 if (victim_pvo == NULL) { 2323 if ((pt->pte_hi & PTE_HID) == 0) 2324 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2325 "entry", pt); 2326 2327 /* 2328 * If this is a secondary PTE, we need to search it's primary 2329 * pvo bucket for the matching PVO. 2330 */ 2331 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2332 pvo_olink) { 2333 /* 2334 * We also need the pvo entry of the victim we are 2335 * replacing so save the R & C bits of the PTE. 2336 */ 2337 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2338 victim_pvo = pvo; 2339 break; 2340 } 2341 } 2342 2343 if (victim_pvo == NULL) 2344 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2345 "entry", pt); 2346 } 2347 2348 /* 2349 * We are invalidating the TLB entry for the EA we are replacing even 2350 * though it's valid. If we don't, we lose any ref/chg bit changes 2351 * contained in the TLB entry. 2352 */ 2353 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2354 2355 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2356 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2357 2358 PVO_PTEGIDX_CLR(victim_pvo); 2359 PVO_PTEGIDX_SET(source_pvo, i); 2360 moea_pte_replacements++; 2361 2362 mtx_unlock(&moea_table_mutex); 2363 return (1); 2364 } 2365 2366 static __inline struct pvo_entry * 2367 moea_pte_spillable_ident(u_int ptegidx) 2368 { 2369 struct pte *pt; 2370 struct pvo_entry *pvo_walk, *pvo = NULL; 2371 2372 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2373 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2374 continue; 2375 2376 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2377 continue; 2378 2379 pt = moea_pvo_to_pte(pvo_walk, -1); 2380 2381 if (pt == NULL) 2382 continue; 2383 2384 pvo = pvo_walk; 2385 2386 mtx_unlock(&moea_table_mutex); 2387 if (!(pt->pte_lo & PTE_REF)) 2388 return (pvo_walk); 2389 } 2390 2391 return (pvo); 2392 } 2393 2394 static int 2395 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2396 { 2397 struct pte *pt; 2398 struct pvo_entry *victim_pvo; 2399 int i; 2400 int victim_idx; 2401 u_int pteg_bkpidx = ptegidx; 2402 2403 mtx_assert(&moea_table_mutex, MA_OWNED); 2404 2405 /* 2406 * First try primary hash. 2407 */ 2408 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2409 if ((pt->pte_hi & PTE_VALID) == 0) { 2410 pvo_pt->pte_hi &= ~PTE_HID; 2411 moea_pte_set(pt, pvo_pt); 2412 return (i); 2413 } 2414 } 2415 2416 /* 2417 * Now try secondary hash. 2418 */ 2419 ptegidx ^= moea_pteg_mask; 2420 2421 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2422 if ((pt->pte_hi & PTE_VALID) == 0) { 2423 pvo_pt->pte_hi |= PTE_HID; 2424 moea_pte_set(pt, pvo_pt); 2425 return (i); 2426 } 2427 } 2428 2429 /* Try again, but this time try to force a PTE out. */ 2430 ptegidx = pteg_bkpidx; 2431 2432 victim_pvo = moea_pte_spillable_ident(ptegidx); 2433 if (victim_pvo == NULL) { 2434 ptegidx ^= moea_pteg_mask; 2435 victim_pvo = moea_pte_spillable_ident(ptegidx); 2436 } 2437 2438 if (victim_pvo == NULL) { 2439 panic("moea_pte_insert: overflow"); 2440 return (-1); 2441 } 2442 2443 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2444 2445 if (pteg_bkpidx == ptegidx) 2446 pvo_pt->pte_hi &= ~PTE_HID; 2447 else 2448 pvo_pt->pte_hi |= PTE_HID; 2449 2450 /* 2451 * Synchronize the sacrifice PTE with its PVO, then mark both 2452 * invalid. The PVO will be reused when/if the VM system comes 2453 * here after a fault. 2454 */ 2455 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2456 2457 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2458 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2459 2460 /* 2461 * Set the new PTE. 2462 */ 2463 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2464 PVO_PTEGIDX_CLR(victim_pvo); 2465 moea_pte_overflow++; 2466 moea_pte_set(pt, pvo_pt); 2467 2468 return (victim_idx & 7); 2469 } 2470 2471 static boolean_t 2472 moea_query_bit(vm_page_t m, int ptebit) 2473 { 2474 struct pvo_entry *pvo; 2475 struct pte *pt; 2476 2477 rw_assert(&pvh_global_lock, RA_WLOCKED); 2478 if (moea_attr_fetch(m) & ptebit) 2479 return (TRUE); 2480 2481 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2482 /* 2483 * See if we saved the bit off. If so, cache it and return 2484 * success. 2485 */ 2486 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2487 moea_attr_save(m, ptebit); 2488 return (TRUE); 2489 } 2490 } 2491 2492 /* 2493 * No luck, now go through the hard part of looking at the PTEs 2494 * themselves. Sync so that any pending REF/CHG bits are flushed to 2495 * the PTEs. 2496 */ 2497 powerpc_sync(); 2498 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2499 /* 2500 * See if this pvo has a valid PTE. if so, fetch the 2501 * REF/CHG bits from the valid PTE. If the appropriate 2502 * ptebit is set, cache it and return success. 2503 */ 2504 pt = moea_pvo_to_pte(pvo, -1); 2505 if (pt != NULL) { 2506 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2507 mtx_unlock(&moea_table_mutex); 2508 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2509 moea_attr_save(m, ptebit); 2510 return (TRUE); 2511 } 2512 } 2513 } 2514 2515 return (FALSE); 2516 } 2517 2518 static u_int 2519 moea_clear_bit(vm_page_t m, int ptebit) 2520 { 2521 u_int count; 2522 struct pvo_entry *pvo; 2523 struct pte *pt; 2524 2525 rw_assert(&pvh_global_lock, RA_WLOCKED); 2526 2527 /* 2528 * Clear the cached value. 2529 */ 2530 moea_attr_clear(m, ptebit); 2531 2532 /* 2533 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2534 * we can reset the right ones). note that since the pvo entries and 2535 * list heads are accessed via BAT0 and are never placed in the page 2536 * table, we don't have to worry about further accesses setting the 2537 * REF/CHG bits. 2538 */ 2539 powerpc_sync(); 2540 2541 /* 2542 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2543 * valid pte clear the ptebit from the valid pte. 2544 */ 2545 count = 0; 2546 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2547 pt = moea_pvo_to_pte(pvo, -1); 2548 if (pt != NULL) { 2549 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2550 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2551 count++; 2552 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2553 } 2554 mtx_unlock(&moea_table_mutex); 2555 } 2556 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2557 } 2558 2559 return (count); 2560 } 2561 2562 /* 2563 * Return true if the physical range is encompassed by the battable[idx] 2564 */ 2565 static int 2566 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2567 { 2568 u_int prot; 2569 u_int32_t start; 2570 u_int32_t end; 2571 u_int32_t bat_ble; 2572 2573 /* 2574 * Return immediately if not a valid mapping 2575 */ 2576 if (!(battable[idx].batu & BAT_Vs)) 2577 return (EINVAL); 2578 2579 /* 2580 * The BAT entry must be cache-inhibited, guarded, and r/w 2581 * so it can function as an i/o page 2582 */ 2583 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2584 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2585 return (EPERM); 2586 2587 /* 2588 * The address should be within the BAT range. Assume that the 2589 * start address in the BAT has the correct alignment (thus 2590 * not requiring masking) 2591 */ 2592 start = battable[idx].batl & BAT_PBS; 2593 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2594 end = start | (bat_ble << 15) | 0x7fff; 2595 2596 if ((pa < start) || ((pa + size) > end)) 2597 return (ERANGE); 2598 2599 return (0); 2600 } 2601 2602 boolean_t 2603 moea_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2604 { 2605 int i; 2606 2607 /* 2608 * This currently does not work for entries that 2609 * overlap 256M BAT segments. 2610 */ 2611 2612 for(i = 0; i < 16; i++) 2613 if (moea_bat_mapped(i, pa, size) == 0) 2614 return (0); 2615 2616 return (EFAULT); 2617 } 2618 2619 /* 2620 * Map a set of physical memory pages into the kernel virtual 2621 * address space. Return a pointer to where it is mapped. This 2622 * routine is intended to be used for mapping device memory, 2623 * NOT real memory. 2624 */ 2625 void * 2626 moea_mapdev(vm_paddr_t pa, vm_size_t size) 2627 { 2628 2629 return (moea_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2630 } 2631 2632 void * 2633 moea_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2634 { 2635 vm_offset_t va, tmpva, ppa, offset; 2636 int i; 2637 2638 ppa = trunc_page(pa); 2639 offset = pa & PAGE_MASK; 2640 size = roundup(offset + size, PAGE_SIZE); 2641 2642 /* 2643 * If the physical address lies within a valid BAT table entry, 2644 * return the 1:1 mapping. This currently doesn't work 2645 * for regions that overlap 256M BAT segments. 2646 */ 2647 for (i = 0; i < 16; i++) { 2648 if (moea_bat_mapped(i, pa, size) == 0) 2649 return ((void *) pa); 2650 } 2651 2652 va = kva_alloc(size); 2653 if (!va) 2654 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2655 2656 for (tmpva = va; size > 0;) { 2657 moea_kenter_attr(tmpva, ppa, ma); 2658 tlbie(tmpva); 2659 size -= PAGE_SIZE; 2660 tmpva += PAGE_SIZE; 2661 ppa += PAGE_SIZE; 2662 } 2663 2664 return ((void *)(va + offset)); 2665 } 2666 2667 void 2668 moea_unmapdev(vm_offset_t va, vm_size_t size) 2669 { 2670 vm_offset_t base, offset; 2671 2672 /* 2673 * If this is outside kernel virtual space, then it's a 2674 * battable entry and doesn't require unmapping 2675 */ 2676 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2677 base = trunc_page(va); 2678 offset = va & PAGE_MASK; 2679 size = roundup(offset + size, PAGE_SIZE); 2680 moea_qremove(base, atop(size)); 2681 kva_free(base, size); 2682 } 2683 } 2684 2685 static void 2686 moea_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2687 { 2688 struct pvo_entry *pvo; 2689 vm_offset_t lim; 2690 vm_paddr_t pa; 2691 vm_size_t len; 2692 2693 PMAP_LOCK(pm); 2694 while (sz > 0) { 2695 lim = round_page(va + 1); 2696 len = MIN(lim - va, sz); 2697 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2698 if (pvo != NULL) { 2699 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2700 (va & ADDR_POFF); 2701 moea_syncicache(pa, len); 2702 } 2703 va += len; 2704 sz -= len; 2705 } 2706 PMAP_UNLOCK(pm); 2707 } 2708 2709 void 2710 moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2711 { 2712 2713 *va = (void *)pa; 2714 } 2715 2716 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2717 2718 void 2719 moea_scan_init() 2720 { 2721 struct pvo_entry *pvo; 2722 vm_offset_t va; 2723 int i; 2724 2725 if (!do_minidump) { 2726 /* Initialize phys. segments for dumpsys(). */ 2727 memset(&dump_map, 0, sizeof(dump_map)); 2728 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2729 for (i = 0; i < pregions_sz; i++) { 2730 dump_map[i].pa_start = pregions[i].mr_start; 2731 dump_map[i].pa_size = pregions[i].mr_size; 2732 } 2733 return; 2734 } 2735 2736 /* Virtual segments for minidumps: */ 2737 memset(&dump_map, 0, sizeof(dump_map)); 2738 2739 /* 1st: kernel .data and .bss. */ 2740 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2741 dump_map[0].pa_size = 2742 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2743 2744 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2745 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2746 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2747 2748 /* 3rd: kernel VM. */ 2749 va = dump_map[1].pa_start + dump_map[1].pa_size; 2750 /* Find start of next chunk (from va). */ 2751 while (va < virtual_end) { 2752 /* Don't dump the buffer cache. */ 2753 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2754 va = kmi.buffer_eva; 2755 continue; 2756 } 2757 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2758 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2759 break; 2760 va += PAGE_SIZE; 2761 } 2762 if (va < virtual_end) { 2763 dump_map[2].pa_start = va; 2764 va += PAGE_SIZE; 2765 /* Find last page in chunk. */ 2766 while (va < virtual_end) { 2767 /* Don't run into the buffer cache. */ 2768 if (va == kmi.buffer_sva) 2769 break; 2770 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2771 NULL); 2772 if (pvo == NULL || 2773 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2774 break; 2775 va += PAGE_SIZE; 2776 } 2777 dump_map[2].pa_size = va - dump_map[2].pa_start; 2778 } 2779 } 2780