1 /* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /* 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /* 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include <sys/param.h> 118 #include <sys/kernel.h> 119 #include <sys/ktr.h> 120 #include <sys/lock.h> 121 #include <sys/msgbuf.h> 122 #include <sys/mutex.h> 123 #include <sys/proc.h> 124 #include <sys/sysctl.h> 125 #include <sys/systm.h> 126 #include <sys/vmmeter.h> 127 128 #include <dev/ofw/openfirm.h> 129 130 #include <vm/vm.h> 131 #include <vm/vm_param.h> 132 #include <vm/vm_kern.h> 133 #include <vm/vm_page.h> 134 #include <vm/vm_map.h> 135 #include <vm/vm_object.h> 136 #include <vm/vm_extern.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/vm_pager.h> 139 #include <vm/uma.h> 140 141 #include <machine/powerpc.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/sr.h> 148 149 #define PMAP_DEBUG 150 151 #define TODO panic("%s: not implemented", __func__); 152 153 #define PMAP_LOCK(pm) 154 #define PMAP_UNLOCK(pm) 155 156 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 157 #define TLBSYNC() __asm __volatile("tlbsync"); 158 #define SYNC() __asm __volatile("sync"); 159 #define EIEIO() __asm __volatile("eieio"); 160 161 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 162 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 163 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 164 165 #define PVO_PTEGIDX_MASK 0x0007 /* which PTEG slot */ 166 #define PVO_PTEGIDX_VALID 0x0008 /* slot is valid */ 167 #define PVO_WIRED 0x0010 /* PVO entry is wired */ 168 #define PVO_MANAGED 0x0020 /* PVO entry is managed */ 169 #define PVO_EXECUTABLE 0x0040 /* PVO entry is executable */ 170 #define PVO_BOOTSTRAP 0x0080 /* PVO entry allocated during 171 bootstrap */ 172 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 173 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 175 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 176 #define PVO_PTEGIDX_CLR(pvo) \ 177 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 178 #define PVO_PTEGIDX_SET(pvo, i) \ 179 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 180 181 #define PMAP_PVO_CHECK(pvo) 182 183 struct ofw_map { 184 vm_offset_t om_va; 185 vm_size_t om_len; 186 vm_offset_t om_pa; 187 u_int om_mode; 188 }; 189 190 int pmap_bootstrapped = 0; 191 192 /* 193 * Virtual and physical address of message buffer. 194 */ 195 struct msgbuf *msgbufp; 196 vm_offset_t msgbuf_phys; 197 198 /* 199 * Physical addresses of first and last available physical page. 200 */ 201 vm_offset_t avail_start; 202 vm_offset_t avail_end; 203 204 int pmap_pagedaemon_waken; 205 206 /* 207 * Map of physical memory regions. 208 */ 209 vm_offset_t phys_avail[128]; 210 u_int phys_avail_count; 211 static struct mem_region *regions; 212 static struct mem_region *pregions; 213 int regions_sz, pregions_sz; 214 static struct ofw_map *translations; 215 216 /* 217 * First and last available kernel virtual addresses. 218 */ 219 vm_offset_t virtual_avail; 220 vm_offset_t virtual_end; 221 vm_offset_t kernel_vm_end; 222 223 /* 224 * Kernel pmap. 225 */ 226 struct pmap kernel_pmap_store; 227 extern struct pmap ofw_pmap; 228 229 /* 230 * PTEG data. 231 */ 232 static struct pteg *pmap_pteg_table; 233 u_int pmap_pteg_count; 234 u_int pmap_pteg_mask; 235 236 /* 237 * PVO data. 238 */ 239 struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 240 struct pvo_head pmap_pvo_kunmanaged = 241 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 242 struct pvo_head pmap_pvo_unmanaged = 243 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 244 245 uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 246 uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 247 struct vm_object pmap_upvo_zone_obj; 248 struct vm_object pmap_mpvo_zone_obj; 249 static vm_object_t pmap_pvo_obj; 250 static u_int pmap_pvo_count; 251 252 #define BPVO_POOL_SIZE 32768 253 static struct pvo_entry *pmap_bpvo_pool; 254 static int pmap_bpvo_pool_index = 0; 255 256 #define VSID_NBPW (sizeof(u_int32_t) * 8) 257 static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 258 259 static boolean_t pmap_initialized = FALSE; 260 261 /* 262 * Statistics. 263 */ 264 u_int pmap_pte_valid = 0; 265 u_int pmap_pte_overflow = 0; 266 u_int pmap_pte_replacements = 0; 267 u_int pmap_pvo_entries = 0; 268 u_int pmap_pvo_enter_calls = 0; 269 u_int pmap_pvo_remove_calls = 0; 270 u_int pmap_pte_spills = 0; 271 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 272 0, ""); 273 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 274 &pmap_pte_overflow, 0, ""); 275 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 276 &pmap_pte_replacements, 0, ""); 277 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 278 0, ""); 279 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 280 &pmap_pvo_enter_calls, 0, ""); 281 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 282 &pmap_pvo_remove_calls, 0, ""); 283 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 284 &pmap_pte_spills, 0, ""); 285 286 struct pvo_entry *pmap_pvo_zeropage; 287 288 vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 289 u_int pmap_rkva_count = 4; 290 291 /* 292 * Allocate physical memory for use in pmap_bootstrap. 293 */ 294 static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 295 296 /* 297 * PTE calls. 298 */ 299 static int pmap_pte_insert(u_int, struct pte *); 300 301 /* 302 * PVO calls. 303 */ 304 static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 305 vm_offset_t, vm_offset_t, u_int, int); 306 static void pmap_pvo_remove(struct pvo_entry *, int); 307 static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 308 static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 309 310 /* 311 * Utility routines. 312 */ 313 static void * pmap_pvo_allocf(uma_zone_t, int, u_int8_t *, int); 314 static struct pvo_entry *pmap_rkva_alloc(void); 315 static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 316 struct pte *, int *); 317 static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 318 static void pmap_syncicache(vm_offset_t, vm_size_t); 319 static boolean_t pmap_query_bit(vm_page_t, int); 320 static u_int pmap_clear_bit(vm_page_t, int, int *); 321 static void tlbia(void); 322 323 static __inline int 324 va_to_sr(u_int *sr, vm_offset_t va) 325 { 326 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 327 } 328 329 static __inline u_int 330 va_to_pteg(u_int sr, vm_offset_t addr) 331 { 332 u_int hash; 333 334 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 335 ADDR_PIDX_SHFT); 336 return (hash & pmap_pteg_mask); 337 } 338 339 static __inline struct pvo_head * 340 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 341 { 342 struct vm_page *pg; 343 344 pg = PHYS_TO_VM_PAGE(pa); 345 346 if (pg_p != NULL) 347 *pg_p = pg; 348 349 if (pg == NULL) 350 return (&pmap_pvo_unmanaged); 351 352 return (&pg->md.mdpg_pvoh); 353 } 354 355 static __inline struct pvo_head * 356 vm_page_to_pvoh(vm_page_t m) 357 { 358 359 return (&m->md.mdpg_pvoh); 360 } 361 362 static __inline void 363 pmap_attr_clear(vm_page_t m, int ptebit) 364 { 365 366 m->md.mdpg_attrs &= ~ptebit; 367 } 368 369 static __inline int 370 pmap_attr_fetch(vm_page_t m) 371 { 372 373 return (m->md.mdpg_attrs); 374 } 375 376 static __inline void 377 pmap_attr_save(vm_page_t m, int ptebit) 378 { 379 380 m->md.mdpg_attrs |= ptebit; 381 } 382 383 static __inline int 384 pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 385 { 386 if (pt->pte_hi == pvo_pt->pte_hi) 387 return (1); 388 389 return (0); 390 } 391 392 static __inline int 393 pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 394 { 395 return (pt->pte_hi & ~PTE_VALID) == 396 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 397 ((va >> ADDR_API_SHFT) & PTE_API) | which); 398 } 399 400 static __inline void 401 pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 402 { 403 /* 404 * Construct a PTE. Default to IMB initially. Valid bit only gets 405 * set when the real pte is set in memory. 406 * 407 * Note: Don't set the valid bit for correct operation of tlb update. 408 */ 409 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 410 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 411 pt->pte_lo = pte_lo; 412 } 413 414 static __inline void 415 pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 416 { 417 418 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 419 } 420 421 static __inline void 422 pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 423 { 424 425 /* 426 * As shown in Section 7.6.3.2.3 427 */ 428 pt->pte_lo &= ~ptebit; 429 TLBIE(va); 430 EIEIO(); 431 TLBSYNC(); 432 SYNC(); 433 } 434 435 static __inline void 436 pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 437 { 438 439 pvo_pt->pte_hi |= PTE_VALID; 440 441 /* 442 * Update the PTE as defined in section 7.6.3.1. 443 * Note that the REF/CHG bits are from pvo_pt and thus should havce 444 * been saved so this routine can restore them (if desired). 445 */ 446 pt->pte_lo = pvo_pt->pte_lo; 447 EIEIO(); 448 pt->pte_hi = pvo_pt->pte_hi; 449 SYNC(); 450 pmap_pte_valid++; 451 } 452 453 static __inline void 454 pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 455 { 456 457 pvo_pt->pte_hi &= ~PTE_VALID; 458 459 /* 460 * Force the reg & chg bits back into the PTEs. 461 */ 462 SYNC(); 463 464 /* 465 * Invalidate the pte. 466 */ 467 pt->pte_hi &= ~PTE_VALID; 468 469 SYNC(); 470 TLBIE(va); 471 EIEIO(); 472 TLBSYNC(); 473 SYNC(); 474 475 /* 476 * Save the reg & chg bits. 477 */ 478 pmap_pte_synch(pt, pvo_pt); 479 pmap_pte_valid--; 480 } 481 482 static __inline void 483 pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 484 { 485 486 /* 487 * Invalidate the PTE 488 */ 489 pmap_pte_unset(pt, pvo_pt, va); 490 pmap_pte_set(pt, pvo_pt); 491 } 492 493 /* 494 * Quick sort callout for comparing memory regions. 495 */ 496 static int mr_cmp(const void *a, const void *b); 497 static int om_cmp(const void *a, const void *b); 498 499 static int 500 mr_cmp(const void *a, const void *b) 501 { 502 const struct mem_region *regiona; 503 const struct mem_region *regionb; 504 505 regiona = a; 506 regionb = b; 507 if (regiona->mr_start < regionb->mr_start) 508 return (-1); 509 else if (regiona->mr_start > regionb->mr_start) 510 return (1); 511 else 512 return (0); 513 } 514 515 static int 516 om_cmp(const void *a, const void *b) 517 { 518 const struct ofw_map *mapa; 519 const struct ofw_map *mapb; 520 521 mapa = a; 522 mapb = b; 523 if (mapa->om_pa < mapb->om_pa) 524 return (-1); 525 else if (mapa->om_pa > mapb->om_pa) 526 return (1); 527 else 528 return (0); 529 } 530 531 void 532 pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 533 { 534 ihandle_t mmui; 535 phandle_t chosen, mmu; 536 int sz; 537 int i, j; 538 int ofw_mappings; 539 vm_size_t size, physsz; 540 vm_offset_t pa, va, off; 541 u_int batl, batu; 542 543 /* 544 * Set up BAT0 to map the lowest 256 MB area 545 */ 546 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 547 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 548 549 /* 550 * Map PCI memory space. 551 */ 552 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 553 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 554 555 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 556 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 557 558 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 559 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 560 561 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 562 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 563 564 /* 565 * Map obio devices. 566 */ 567 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 568 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 569 570 /* 571 * Use an IBAT and a DBAT to map the bottom segment of memory 572 * where we are. 573 */ 574 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 575 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 576 __asm ("mtibatu 0,%0; mtibatl 0,%1; mtdbatu 0,%0; mtdbatl 0,%1" 577 :: "r"(batu), "r"(batl)); 578 579 #if 0 580 /* map frame buffer */ 581 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 582 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 583 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 584 :: "r"(batu), "r"(batl)); 585 #endif 586 587 #if 1 588 /* map pci space */ 589 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 590 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 591 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 592 :: "r"(batu), "r"(batl)); 593 #endif 594 595 /* 596 * Set the start and end of kva. 597 */ 598 virtual_avail = VM_MIN_KERNEL_ADDRESS; 599 virtual_end = VM_MAX_KERNEL_ADDRESS; 600 601 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 602 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 603 604 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 605 for (i = 0; i < pregions_sz; i++) { 606 vm_offset_t pa; 607 vm_offset_t end; 608 609 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 610 pregions[i].mr_start, 611 pregions[i].mr_start + pregions[i].mr_size, 612 pregions[i].mr_size); 613 /* 614 * Install entries into the BAT table to allow all 615 * of physmem to be convered by on-demand BAT entries. 616 * The loop will sometimes set the same battable element 617 * twice, but that's fine since they won't be used for 618 * a while yet. 619 */ 620 pa = pregions[i].mr_start & 0xf0000000; 621 end = pregions[i].mr_start + pregions[i].mr_size; 622 do { 623 u_int n = pa >> ADDR_SR_SHFT; 624 625 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 626 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 627 pa += SEGMENT_LENGTH; 628 } while (pa < end); 629 } 630 631 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 632 panic("pmap_bootstrap: phys_avail too small"); 633 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 634 phys_avail_count = 0; 635 physsz = 0; 636 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 637 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 638 regions[i].mr_start + regions[i].mr_size, 639 regions[i].mr_size); 640 phys_avail[j] = regions[i].mr_start; 641 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 642 phys_avail_count++; 643 physsz += regions[i].mr_size; 644 } 645 physmem = btoc(physsz); 646 647 /* 648 * Allocate PTEG table. 649 */ 650 #ifdef PTEGCOUNT 651 pmap_pteg_count = PTEGCOUNT; 652 #else 653 pmap_pteg_count = 0x1000; 654 655 while (pmap_pteg_count < physmem) 656 pmap_pteg_count <<= 1; 657 658 pmap_pteg_count >>= 1; 659 #endif /* PTEGCOUNT */ 660 661 size = pmap_pteg_count * sizeof(struct pteg); 662 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 663 size); 664 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 665 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 666 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 667 pmap_pteg_mask = pmap_pteg_count - 1; 668 669 /* 670 * Allocate pv/overflow lists. 671 */ 672 size = sizeof(struct pvo_head) * pmap_pteg_count; 673 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 674 PAGE_SIZE); 675 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 676 for (i = 0; i < pmap_pteg_count; i++) 677 LIST_INIT(&pmap_pvo_table[i]); 678 679 /* 680 * Allocate the message buffer. 681 */ 682 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 683 684 /* 685 * Initialise the unmanaged pvo pool. 686 */ 687 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 688 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 689 pmap_bpvo_pool_index = 0; 690 691 /* 692 * Make sure kernel vsid is allocated as well as VSID 0. 693 */ 694 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 695 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 696 pmap_vsid_bitmap[0] |= 1; 697 698 /* 699 * Set up the OpenFirmware pmap and add it's mappings. 700 */ 701 pmap_pinit(&ofw_pmap); 702 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 703 if ((chosen = OF_finddevice("/chosen")) == -1) 704 panic("pmap_bootstrap: can't find /chosen"); 705 OF_getprop(chosen, "mmu", &mmui, 4); 706 if ((mmu = OF_instance_to_package(mmui)) == -1) 707 panic("pmap_bootstrap: can't get mmu package"); 708 if ((sz = OF_getproplen(mmu, "translations")) == -1) 709 panic("pmap_bootstrap: can't get ofw translation count"); 710 translations = NULL; 711 for (i = 0; phys_avail[i + 2] != 0; i += 2) { 712 if (phys_avail[i + 1] >= sz) 713 translations = (struct ofw_map *)phys_avail[i]; 714 } 715 if (translations == NULL) 716 panic("pmap_bootstrap: no space to copy translations"); 717 bzero(translations, sz); 718 if (OF_getprop(mmu, "translations", translations, sz) == -1) 719 panic("pmap_bootstrap: can't get ofw translations"); 720 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 721 sz /= sizeof(*translations); 722 qsort(translations, sz, sizeof (*translations), om_cmp); 723 for (i = 0, ofw_mappings = 0; i < sz; i++) { 724 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 725 translations[i].om_pa, translations[i].om_va, 726 translations[i].om_len); 727 728 /* 729 * If the mapping is 1:1, let the RAM and device on-demand 730 * BAT tables take care of the translation. 731 */ 732 if (translations[i].om_va == translations[i].om_pa) 733 continue; 734 735 /* Enter the pages */ 736 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 737 struct vm_page m; 738 739 m.phys_addr = translations[i].om_pa + off; 740 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 741 VM_PROT_ALL, 1); 742 ofw_mappings++; 743 } 744 } 745 #ifdef SMP 746 TLBSYNC(); 747 #endif 748 749 /* 750 * Initialize the kernel pmap (which is statically allocated). 751 */ 752 for (i = 0; i < 16; i++) { 753 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 754 } 755 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 756 kernel_pmap->pm_active = ~0; 757 758 /* 759 * Allocate a kernel stack with a guard page for thread0 and map it 760 * into the kernel page map. 761 */ 762 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 763 kstack0_phys = pa; 764 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 765 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 766 kstack0); 767 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 768 for (i = 0; i < KSTACK_PAGES; i++) { 769 pa = kstack0_phys + i * PAGE_SIZE; 770 va = kstack0 + i * PAGE_SIZE; 771 pmap_kenter(va, pa); 772 TLBIE(va); 773 } 774 775 /* 776 * Calculate the first and last available physical addresses. 777 */ 778 avail_start = phys_avail[0]; 779 for (i = 0; phys_avail[i + 2] != 0; i += 2) 780 ; 781 avail_end = phys_avail[i + 1]; 782 Maxmem = powerpc_btop(avail_end); 783 784 /* 785 * Allocate virtual address space for the message buffer. 786 */ 787 msgbufp = (struct msgbuf *)virtual_avail; 788 virtual_avail += round_page(MSGBUF_SIZE); 789 790 /* 791 * Initialize hardware. 792 */ 793 for (i = 0; i < 16; i++) { 794 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 795 } 796 __asm __volatile ("mtsr %0,%1" 797 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 798 __asm __volatile ("sync; mtsdr1 %0; isync" 799 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 800 tlbia(); 801 802 pmap_bootstrapped++; 803 } 804 805 /* 806 * Activate a user pmap. The pmap must be activated before it's address 807 * space can be accessed in any way. 808 */ 809 void 810 pmap_activate(struct thread *td) 811 { 812 pmap_t pm, pmr; 813 814 /* 815 * Load all the data we need up front to encourage the compiler to 816 * not issue any loads while we have interrupts disabled below. 817 */ 818 pm = &td->td_proc->p_vmspace->vm_pmap; 819 820 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 821 pmr = pm; 822 823 pm->pm_active |= PCPU_GET(cpumask); 824 PCPU_SET(curpmap, pmr); 825 } 826 827 void 828 pmap_deactivate(struct thread *td) 829 { 830 pmap_t pm; 831 832 pm = &td->td_proc->p_vmspace->vm_pmap; 833 pm->pm_active &= ~(PCPU_GET(cpumask)); 834 PCPU_SET(curpmap, NULL); 835 } 836 837 vm_offset_t 838 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 839 { 840 841 return (va); 842 } 843 844 void 845 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 846 { 847 struct pvo_entry *pvo; 848 849 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 850 851 if (pvo != NULL) { 852 if (wired) { 853 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 854 pm->pm_stats.wired_count++; 855 pvo->pvo_vaddr |= PVO_WIRED; 856 } else { 857 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 858 pm->pm_stats.wired_count--; 859 pvo->pvo_vaddr &= ~PVO_WIRED; 860 } 861 } 862 } 863 864 void 865 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 866 vm_size_t len, vm_offset_t src_addr) 867 { 868 869 /* 870 * This is not needed as it's mainly an optimisation. 871 * It may want to be implemented later though. 872 */ 873 } 874 875 void 876 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 877 { 878 vm_offset_t dst; 879 vm_offset_t src; 880 881 dst = VM_PAGE_TO_PHYS(mdst); 882 src = VM_PAGE_TO_PHYS(msrc); 883 884 kcopy((void *)src, (void *)dst, PAGE_SIZE); 885 } 886 887 /* 888 * Zero a page of physical memory by temporarily mapping it into the tlb. 889 */ 890 void 891 pmap_zero_page(vm_page_t m) 892 { 893 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 894 caddr_t va; 895 896 if (pa < SEGMENT_LENGTH) { 897 va = (caddr_t) pa; 898 } else if (pmap_initialized) { 899 if (pmap_pvo_zeropage == NULL) 900 pmap_pvo_zeropage = pmap_rkva_alloc(); 901 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 902 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 903 } else { 904 panic("pmap_zero_page: can't zero pa %#x", pa); 905 } 906 907 bzero(va, PAGE_SIZE); 908 909 if (pa >= SEGMENT_LENGTH) 910 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 911 } 912 913 void 914 pmap_zero_page_area(vm_page_t m, int off, int size) 915 { 916 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 917 caddr_t va; 918 919 if (pa < SEGMENT_LENGTH) { 920 va = (caddr_t) pa; 921 } else if (pmap_initialized) { 922 if (pmap_pvo_zeropage == NULL) 923 pmap_pvo_zeropage = pmap_rkva_alloc(); 924 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 925 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 926 } else { 927 panic("pmap_zero_page: can't zero pa %#x", pa); 928 } 929 930 bzero(va + off, size); 931 932 if (pa >= SEGMENT_LENGTH) 933 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 934 } 935 936 void 937 pmap_zero_page_idle(vm_page_t m) 938 { 939 940 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 941 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 942 mtx_lock(&Giant); 943 pmap_zero_page(m); 944 mtx_unlock(&Giant); 945 } 946 947 /* 948 * Map the given physical page at the specified virtual address in the 949 * target pmap with the protection requested. If specified the page 950 * will be wired down. 951 */ 952 void 953 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 954 boolean_t wired) 955 { 956 struct pvo_head *pvo_head; 957 uma_zone_t zone; 958 vm_page_t pg; 959 u_int pte_lo, pvo_flags, was_exec, i; 960 int error; 961 962 if (!pmap_initialized) { 963 pvo_head = &pmap_pvo_kunmanaged; 964 zone = pmap_upvo_zone; 965 pvo_flags = 0; 966 pg = NULL; 967 was_exec = PTE_EXEC; 968 } else { 969 pvo_head = vm_page_to_pvoh(m); 970 pg = m; 971 zone = pmap_mpvo_zone; 972 pvo_flags = PVO_MANAGED; 973 was_exec = 0; 974 } 975 976 /* 977 * If this is a managed page, and it's the first reference to the page, 978 * clear the execness of the page. Otherwise fetch the execness. 979 */ 980 if (pg != NULL) { 981 if (LIST_EMPTY(pvo_head)) { 982 pmap_attr_clear(pg, PTE_EXEC); 983 } else { 984 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 985 } 986 } 987 988 989 /* 990 * Assume the page is cache inhibited and access is guarded unless 991 * it's in our available memory array. 992 */ 993 pte_lo = PTE_I | PTE_G; 994 for (i = 0; i < pregions_sz; i++) { 995 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 996 (VM_PAGE_TO_PHYS(m) < 997 (pregions[i].mr_start + pregions[i].mr_size))) { 998 pte_lo &= ~(PTE_I | PTE_G); 999 break; 1000 } 1001 } 1002 1003 if (prot & VM_PROT_WRITE) 1004 pte_lo |= PTE_BW; 1005 else 1006 pte_lo |= PTE_BR; 1007 1008 pvo_flags |= (prot & VM_PROT_EXECUTE); 1009 1010 if (wired) 1011 pvo_flags |= PVO_WIRED; 1012 1013 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1014 pte_lo, pvo_flags); 1015 1016 /* 1017 * Flush the real page from the instruction cache if this page is 1018 * mapped executable and cacheable and was not previously mapped (or 1019 * was not mapped executable). 1020 */ 1021 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1022 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1023 /* 1024 * Flush the real memory from the cache. 1025 */ 1026 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1027 if (pg != NULL) 1028 pmap_attr_save(pg, PTE_EXEC); 1029 } 1030 1031 /* XXX syncicache always until problems are sorted */ 1032 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1033 } 1034 1035 vm_page_t 1036 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_page_t mpte) 1037 { 1038 1039 pmap_enter(pm, va, m, VM_PROT_READ | VM_PROT_EXECUTE, FALSE); 1040 return (NULL); 1041 } 1042 1043 vm_offset_t 1044 pmap_extract(pmap_t pm, vm_offset_t va) 1045 { 1046 struct pvo_entry *pvo; 1047 1048 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1049 1050 if (pvo != NULL) { 1051 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1052 } 1053 1054 return (0); 1055 } 1056 1057 /* 1058 * Grow the number of kernel page table entries. Unneeded. 1059 */ 1060 void 1061 pmap_growkernel(vm_offset_t addr) 1062 { 1063 } 1064 1065 void 1066 pmap_init(vm_offset_t phys_start, vm_offset_t phys_end) 1067 { 1068 1069 CTR0(KTR_PMAP, "pmap_init"); 1070 1071 pmap_pvo_obj = vm_object_allocate(OBJT_PHYS, 16); 1072 pmap_pvo_count = 0; 1073 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1074 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM); 1075 uma_zone_set_allocf(pmap_upvo_zone, pmap_pvo_allocf); 1076 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1077 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM); 1078 uma_zone_set_allocf(pmap_mpvo_zone, pmap_pvo_allocf); 1079 pmap_initialized = TRUE; 1080 } 1081 1082 void 1083 pmap_init2(void) 1084 { 1085 1086 CTR0(KTR_PMAP, "pmap_init2"); 1087 } 1088 1089 boolean_t 1090 pmap_is_modified(vm_page_t m) 1091 { 1092 1093 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1094 return (FALSE); 1095 1096 return (pmap_query_bit(m, PTE_CHG)); 1097 } 1098 1099 void 1100 pmap_clear_reference(vm_page_t m) 1101 { 1102 1103 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1104 return; 1105 pmap_clear_bit(m, PTE_REF, NULL); 1106 } 1107 1108 void 1109 pmap_clear_modify(vm_page_t m) 1110 { 1111 1112 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1113 return; 1114 pmap_clear_bit(m, PTE_CHG, NULL); 1115 } 1116 1117 /* 1118 * pmap_ts_referenced: 1119 * 1120 * Return a count of reference bits for a page, clearing those bits. 1121 * It is not necessary for every reference bit to be cleared, but it 1122 * is necessary that 0 only be returned when there are truly no 1123 * reference bits set. 1124 * 1125 * XXX: The exact number of bits to check and clear is a matter that 1126 * should be tested and standardized at some point in the future for 1127 * optimal aging of shared pages. 1128 */ 1129 int 1130 pmap_ts_referenced(vm_page_t m) 1131 { 1132 int count; 1133 1134 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1135 return (0); 1136 1137 count = pmap_clear_bit(m, PTE_REF, NULL); 1138 1139 return (count); 1140 } 1141 1142 /* 1143 * Map a wired page into kernel virtual address space. 1144 */ 1145 void 1146 pmap_kenter(vm_offset_t va, vm_offset_t pa) 1147 { 1148 u_int pte_lo; 1149 int error; 1150 int i; 1151 1152 #if 0 1153 if (va < VM_MIN_KERNEL_ADDRESS) 1154 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1155 va); 1156 #endif 1157 1158 pte_lo = PTE_I | PTE_G; 1159 for (i = 0; i < pregions_sz; i++) { 1160 if ((pa >= pregions[i].mr_start) && 1161 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1162 pte_lo &= ~(PTE_I | PTE_G); 1163 break; 1164 } 1165 } 1166 1167 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1168 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1169 1170 if (error != 0 && error != ENOENT) 1171 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1172 pa, error); 1173 1174 /* 1175 * Flush the real memory from the instruction cache. 1176 */ 1177 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1178 pmap_syncicache(pa, PAGE_SIZE); 1179 } 1180 } 1181 1182 /* 1183 * Extract the physical page address associated with the given kernel virtual 1184 * address. 1185 */ 1186 vm_offset_t 1187 pmap_kextract(vm_offset_t va) 1188 { 1189 struct pvo_entry *pvo; 1190 1191 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1192 if (pvo == NULL) { 1193 return (0); 1194 } 1195 1196 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1197 } 1198 1199 /* 1200 * Remove a wired page from kernel virtual address space. 1201 */ 1202 void 1203 pmap_kremove(vm_offset_t va) 1204 { 1205 1206 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1207 } 1208 1209 /* 1210 * Map a range of physical addresses into kernel virtual address space. 1211 * 1212 * The value passed in *virt is a suggested virtual address for the mapping. 1213 * Architectures which can support a direct-mapped physical to virtual region 1214 * can return the appropriate address within that region, leaving '*virt' 1215 * unchanged. We cannot and therefore do not; *virt is updated with the 1216 * first usable address after the mapped region. 1217 */ 1218 vm_offset_t 1219 pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1220 { 1221 vm_offset_t sva, va; 1222 1223 sva = *virt; 1224 va = sva; 1225 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1226 pmap_kenter(va, pa_start); 1227 *virt = va; 1228 return (sva); 1229 } 1230 1231 int 1232 pmap_mincore(pmap_t pmap, vm_offset_t addr) 1233 { 1234 TODO; 1235 return (0); 1236 } 1237 1238 void 1239 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1240 vm_pindex_t pindex, vm_size_t size) 1241 { 1242 1243 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 1244 KASSERT(object->type == OBJT_DEVICE, 1245 ("pmap_object_init_pt: non-device object")); 1246 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1247 ("pmap_object_init_pt: non current pmap")); 1248 } 1249 1250 /* 1251 * Lower the permission for all mappings to a given page. 1252 */ 1253 void 1254 pmap_page_protect(vm_page_t m, vm_prot_t prot) 1255 { 1256 struct pvo_head *pvo_head; 1257 struct pvo_entry *pvo, *next_pvo; 1258 struct pte *pt; 1259 1260 /* 1261 * Since the routine only downgrades protection, if the 1262 * maximal protection is desired, there isn't any change 1263 * to be made. 1264 */ 1265 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1266 (VM_PROT_READ|VM_PROT_WRITE)) 1267 return; 1268 1269 pvo_head = vm_page_to_pvoh(m); 1270 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1271 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1272 PMAP_PVO_CHECK(pvo); /* sanity check */ 1273 1274 /* 1275 * Downgrading to no mapping at all, we just remove the entry. 1276 */ 1277 if ((prot & VM_PROT_READ) == 0) { 1278 pmap_pvo_remove(pvo, -1); 1279 continue; 1280 } 1281 1282 /* 1283 * If EXEC permission is being revoked, just clear the flag 1284 * in the PVO. 1285 */ 1286 if ((prot & VM_PROT_EXECUTE) == 0) 1287 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1288 1289 /* 1290 * If this entry is already RO, don't diddle with the page 1291 * table. 1292 */ 1293 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1294 PMAP_PVO_CHECK(pvo); 1295 continue; 1296 } 1297 1298 /* 1299 * Grab the PTE before we diddle the bits so pvo_to_pte can 1300 * verify the pte contents are as expected. 1301 */ 1302 pt = pmap_pvo_to_pte(pvo, -1); 1303 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1304 pvo->pvo_pte.pte_lo |= PTE_BR; 1305 if (pt != NULL) 1306 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1307 PMAP_PVO_CHECK(pvo); /* sanity check */ 1308 } 1309 } 1310 1311 /* 1312 * Returns true if the pmap's pv is one of the first 1313 * 16 pvs linked to from this page. This count may 1314 * be changed upwards or downwards in the future; it 1315 * is only necessary that true be returned for a small 1316 * subset of pmaps for proper page aging. 1317 */ 1318 boolean_t 1319 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1320 { 1321 int loops; 1322 struct pvo_entry *pvo; 1323 1324 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 1325 return FALSE; 1326 1327 loops = 0; 1328 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1329 if (pvo->pvo_pmap == pmap) 1330 return (TRUE); 1331 if (++loops >= 16) 1332 break; 1333 } 1334 1335 return (FALSE); 1336 } 1337 1338 static u_int pmap_vsidcontext; 1339 1340 void 1341 pmap_pinit(pmap_t pmap) 1342 { 1343 int i, mask; 1344 u_int entropy; 1345 1346 entropy = 0; 1347 __asm __volatile("mftb %0" : "=r"(entropy)); 1348 1349 /* 1350 * Allocate some segment registers for this pmap. 1351 */ 1352 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1353 u_int hash, n; 1354 1355 /* 1356 * Create a new value by mutiplying by a prime and adding in 1357 * entropy from the timebase register. This is to make the 1358 * VSID more random so that the PT hash function collides 1359 * less often. (Note that the prime casues gcc to do shifts 1360 * instead of a multiply.) 1361 */ 1362 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1363 hash = pmap_vsidcontext & (NPMAPS - 1); 1364 if (hash == 0) /* 0 is special, avoid it */ 1365 continue; 1366 n = hash >> 5; 1367 mask = 1 << (hash & (VSID_NBPW - 1)); 1368 hash = (pmap_vsidcontext & 0xfffff); 1369 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1370 /* anything free in this bucket? */ 1371 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1372 entropy = (pmap_vsidcontext >> 20); 1373 continue; 1374 } 1375 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1376 mask = 1 << i; 1377 hash &= 0xfffff & ~(VSID_NBPW - 1); 1378 hash |= i; 1379 } 1380 pmap_vsid_bitmap[n] |= mask; 1381 for (i = 0; i < 16; i++) 1382 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1383 return; 1384 } 1385 1386 panic("pmap_pinit: out of segments"); 1387 } 1388 1389 /* 1390 * Initialize the pmap associated with process 0. 1391 */ 1392 void 1393 pmap_pinit0(pmap_t pm) 1394 { 1395 1396 pmap_pinit(pm); 1397 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1398 } 1399 1400 void 1401 pmap_pinit2(pmap_t pmap) 1402 { 1403 /* XXX: Remove this stub when no longer called */ 1404 } 1405 1406 void 1407 pmap_prefault(pmap_t pm, vm_offset_t va, vm_map_entry_t entry) 1408 { 1409 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1410 ("pmap_prefault: non current pmap")); 1411 /* XXX */ 1412 } 1413 1414 /* 1415 * Set the physical protection on the specified range of this map as requested. 1416 */ 1417 void 1418 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1419 { 1420 struct pvo_entry *pvo; 1421 struct pte *pt; 1422 int pteidx; 1423 1424 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1425 eva, prot); 1426 1427 1428 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1429 ("pmap_protect: non current pmap")); 1430 1431 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1432 pmap_remove(pm, sva, eva); 1433 return; 1434 } 1435 1436 for (; sva < eva; sva += PAGE_SIZE) { 1437 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1438 if (pvo == NULL) 1439 continue; 1440 1441 if ((prot & VM_PROT_EXECUTE) == 0) 1442 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1443 1444 /* 1445 * Grab the PTE pointer before we diddle with the cached PTE 1446 * copy. 1447 */ 1448 pt = pmap_pvo_to_pte(pvo, pteidx); 1449 /* 1450 * Change the protection of the page. 1451 */ 1452 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1453 pvo->pvo_pte.pte_lo |= PTE_BR; 1454 1455 /* 1456 * If the PVO is in the page table, update that pte as well. 1457 */ 1458 if (pt != NULL) 1459 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1460 } 1461 } 1462 1463 /* 1464 * Map a list of wired pages into kernel virtual address space. This is 1465 * intended for temporary mappings which do not need page modification or 1466 * references recorded. Existing mappings in the region are overwritten. 1467 */ 1468 void 1469 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1470 { 1471 vm_offset_t va; 1472 1473 va = sva; 1474 while (count-- > 0) { 1475 pmap_kenter(va, VM_PAGE_TO_PHYS(*m)); 1476 va += PAGE_SIZE; 1477 m++; 1478 } 1479 } 1480 1481 /* 1482 * Remove page mappings from kernel virtual address space. Intended for 1483 * temporary mappings entered by pmap_qenter. 1484 */ 1485 void 1486 pmap_qremove(vm_offset_t sva, int count) 1487 { 1488 vm_offset_t va; 1489 1490 va = sva; 1491 while (count-- > 0) { 1492 pmap_kremove(va); 1493 va += PAGE_SIZE; 1494 } 1495 } 1496 1497 void 1498 pmap_release(pmap_t pmap) 1499 { 1500 int idx, mask; 1501 1502 /* 1503 * Free segment register's VSID 1504 */ 1505 if (pmap->pm_sr[0] == 0) 1506 panic("pmap_release"); 1507 1508 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1509 mask = 1 << (idx % VSID_NBPW); 1510 idx /= VSID_NBPW; 1511 pmap_vsid_bitmap[idx] &= ~mask; 1512 } 1513 1514 /* 1515 * Remove the given range of addresses from the specified map. 1516 */ 1517 void 1518 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1519 { 1520 struct pvo_entry *pvo; 1521 int pteidx; 1522 1523 for (; sva < eva; sva += PAGE_SIZE) { 1524 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1525 if (pvo != NULL) { 1526 pmap_pvo_remove(pvo, pteidx); 1527 } 1528 } 1529 } 1530 1531 /* 1532 * Remove physical page from all pmaps in which it resides. pmap_pvo_remove() 1533 * will reflect changes in pte's back to the vm_page. 1534 */ 1535 void 1536 pmap_remove_all(vm_page_t m) 1537 { 1538 struct pvo_head *pvo_head; 1539 struct pvo_entry *pvo, *next_pvo; 1540 1541 KASSERT((m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) == 0, 1542 ("pv_remove_all: illegal for unmanaged page %#x", 1543 VM_PAGE_TO_PHYS(m))); 1544 1545 pvo_head = vm_page_to_pvoh(m); 1546 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1547 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1548 1549 PMAP_PVO_CHECK(pvo); /* sanity check */ 1550 pmap_pvo_remove(pvo, -1); 1551 } 1552 vm_page_flag_clear(m, PG_WRITEABLE); 1553 } 1554 1555 /* 1556 * Remove all pages from specified address space, this aids process exit 1557 * speeds. This is much faster than pmap_remove in the case of running down 1558 * an entire address space. Only works for the current pmap. 1559 */ 1560 void 1561 pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1562 { 1563 1564 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1565 ("pmap_remove_pages: non current pmap")); 1566 pmap_remove(pm, sva, eva); 1567 } 1568 1569 /* 1570 * Allocate a physical page of memory directly from the phys_avail map. 1571 * Can only be called from pmap_bootstrap before avail start and end are 1572 * calculated. 1573 */ 1574 static vm_offset_t 1575 pmap_bootstrap_alloc(vm_size_t size, u_int align) 1576 { 1577 vm_offset_t s, e; 1578 int i, j; 1579 1580 size = round_page(size); 1581 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1582 if (align != 0) 1583 s = (phys_avail[i] + align - 1) & ~(align - 1); 1584 else 1585 s = phys_avail[i]; 1586 e = s + size; 1587 1588 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1589 continue; 1590 1591 if (s == phys_avail[i]) { 1592 phys_avail[i] += size; 1593 } else if (e == phys_avail[i + 1]) { 1594 phys_avail[i + 1] -= size; 1595 } else { 1596 for (j = phys_avail_count * 2; j > i; j -= 2) { 1597 phys_avail[j] = phys_avail[j - 2]; 1598 phys_avail[j + 1] = phys_avail[j - 1]; 1599 } 1600 1601 phys_avail[i + 3] = phys_avail[i + 1]; 1602 phys_avail[i + 1] = s; 1603 phys_avail[i + 2] = e; 1604 phys_avail_count++; 1605 } 1606 1607 return (s); 1608 } 1609 panic("pmap_bootstrap_alloc: could not allocate memory"); 1610 } 1611 1612 /* 1613 * Return an unmapped pvo for a kernel virtual address. 1614 * Used by pmap functions that operate on physical pages. 1615 */ 1616 static struct pvo_entry * 1617 pmap_rkva_alloc(void) 1618 { 1619 struct pvo_entry *pvo; 1620 struct pte *pt; 1621 vm_offset_t kva; 1622 int pteidx; 1623 1624 if (pmap_rkva_count == 0) 1625 panic("pmap_rkva_alloc: no more reserved KVAs"); 1626 1627 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1628 pmap_kenter(kva, 0); 1629 1630 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1631 1632 if (pvo == NULL) 1633 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1634 1635 pt = pmap_pvo_to_pte(pvo, pteidx); 1636 1637 if (pt == NULL) 1638 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1639 1640 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1641 PVO_PTEGIDX_CLR(pvo); 1642 1643 pmap_pte_overflow++; 1644 1645 return (pvo); 1646 } 1647 1648 static void 1649 pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1650 int *depth_p) 1651 { 1652 struct pte *pt; 1653 1654 /* 1655 * If this pvo already has a valid pte, we need to save it so it can 1656 * be restored later. We then just reload the new PTE over the old 1657 * slot. 1658 */ 1659 if (saved_pt != NULL) { 1660 pt = pmap_pvo_to_pte(pvo, -1); 1661 1662 if (pt != NULL) { 1663 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1664 PVO_PTEGIDX_CLR(pvo); 1665 pmap_pte_overflow++; 1666 } 1667 1668 *saved_pt = pvo->pvo_pte; 1669 1670 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1671 } 1672 1673 pvo->pvo_pte.pte_lo |= pa; 1674 1675 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1676 panic("pmap_pa_map: could not spill pvo %p", pvo); 1677 1678 if (depth_p != NULL) 1679 (*depth_p)++; 1680 } 1681 1682 static void 1683 pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1684 { 1685 struct pte *pt; 1686 1687 pt = pmap_pvo_to_pte(pvo, -1); 1688 1689 if (pt != NULL) { 1690 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1691 PVO_PTEGIDX_CLR(pvo); 1692 pmap_pte_overflow++; 1693 } 1694 1695 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1696 1697 /* 1698 * If there is a saved PTE and it's valid, restore it and return. 1699 */ 1700 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1701 if (depth_p != NULL && --(*depth_p) == 0) 1702 panic("pmap_pa_unmap: restoring but depth == 0"); 1703 1704 pvo->pvo_pte = *saved_pt; 1705 1706 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1707 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1708 } 1709 } 1710 1711 static void 1712 pmap_syncicache(vm_offset_t pa, vm_size_t len) 1713 { 1714 __syncicache((void *)pa, len); 1715 } 1716 1717 static void 1718 tlbia(void) 1719 { 1720 caddr_t i; 1721 1722 SYNC(); 1723 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1724 TLBIE(i); 1725 EIEIO(); 1726 } 1727 TLBSYNC(); 1728 SYNC(); 1729 } 1730 1731 static int 1732 pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1733 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1734 { 1735 struct pvo_entry *pvo; 1736 u_int sr; 1737 int first; 1738 u_int ptegidx; 1739 int i; 1740 int bootstrap; 1741 1742 pmap_pvo_enter_calls++; 1743 first = 0; 1744 1745 bootstrap = 0; 1746 1747 /* 1748 * Compute the PTE Group index. 1749 */ 1750 va &= ~ADDR_POFF; 1751 sr = va_to_sr(pm->pm_sr, va); 1752 ptegidx = va_to_pteg(sr, va); 1753 1754 /* 1755 * Remove any existing mapping for this page. Reuse the pvo entry if 1756 * there is a mapping. 1757 */ 1758 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1759 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1760 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1761 (pvo->pvo_pte.pte_lo & PTE_PP) == 1762 (pte_lo & PTE_PP)) { 1763 return (0); 1764 } 1765 pmap_pvo_remove(pvo, -1); 1766 break; 1767 } 1768 } 1769 1770 /* 1771 * If we aren't overwriting a mapping, try to allocate. 1772 */ 1773 if (pmap_initialized) { 1774 pvo = uma_zalloc(zone, M_NOWAIT); 1775 } else { 1776 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1777 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1778 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1779 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1780 } 1781 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1782 pmap_bpvo_pool_index++; 1783 bootstrap = 1; 1784 } 1785 1786 if (pvo == NULL) { 1787 return (ENOMEM); 1788 } 1789 1790 pmap_pvo_entries++; 1791 pvo->pvo_vaddr = va; 1792 pvo->pvo_pmap = pm; 1793 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1794 pvo->pvo_vaddr &= ~ADDR_POFF; 1795 if (flags & VM_PROT_EXECUTE) 1796 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1797 if (flags & PVO_WIRED) 1798 pvo->pvo_vaddr |= PVO_WIRED; 1799 if (pvo_head != &pmap_pvo_kunmanaged) 1800 pvo->pvo_vaddr |= PVO_MANAGED; 1801 if (bootstrap) 1802 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1803 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1804 1805 /* 1806 * Remember if the list was empty and therefore will be the first 1807 * item. 1808 */ 1809 if (LIST_FIRST(pvo_head) == NULL) 1810 first = 1; 1811 1812 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1813 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1814 pvo->pvo_pmap->pm_stats.wired_count++; 1815 pvo->pvo_pmap->pm_stats.resident_count++; 1816 1817 /* 1818 * We hope this succeeds but it isn't required. 1819 */ 1820 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1821 if (i >= 0) { 1822 PVO_PTEGIDX_SET(pvo, i); 1823 } else { 1824 panic("pmap_pvo_enter: overflow"); 1825 pmap_pte_overflow++; 1826 } 1827 1828 return (first ? ENOENT : 0); 1829 } 1830 1831 static void 1832 pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1833 { 1834 struct pte *pt; 1835 1836 /* 1837 * If there is an active pte entry, we need to deactivate it (and 1838 * save the ref & cfg bits). 1839 */ 1840 pt = pmap_pvo_to_pte(pvo, pteidx); 1841 if (pt != NULL) { 1842 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1843 PVO_PTEGIDX_CLR(pvo); 1844 } else { 1845 pmap_pte_overflow--; 1846 } 1847 1848 /* 1849 * Update our statistics. 1850 */ 1851 pvo->pvo_pmap->pm_stats.resident_count--; 1852 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1853 pvo->pvo_pmap->pm_stats.wired_count--; 1854 1855 /* 1856 * Save the REF/CHG bits into their cache if the page is managed. 1857 */ 1858 if (pvo->pvo_vaddr & PVO_MANAGED) { 1859 struct vm_page *pg; 1860 1861 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1862 if (pg != NULL) { 1863 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 1864 (PTE_REF | PTE_CHG)); 1865 } 1866 } 1867 1868 /* 1869 * Remove this PVO from the PV list. 1870 */ 1871 LIST_REMOVE(pvo, pvo_vlink); 1872 1873 /* 1874 * Remove this from the overflow list and return it to the pool 1875 * if we aren't going to reuse it. 1876 */ 1877 LIST_REMOVE(pvo, pvo_olink); 1878 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1879 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 1880 pmap_upvo_zone, pvo); 1881 pmap_pvo_entries--; 1882 pmap_pvo_remove_calls++; 1883 } 1884 1885 static __inline int 1886 pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1887 { 1888 int pteidx; 1889 1890 /* 1891 * We can find the actual pte entry without searching by grabbing 1892 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1893 * noticing the HID bit. 1894 */ 1895 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1896 if (pvo->pvo_pte.pte_hi & PTE_HID) 1897 pteidx ^= pmap_pteg_mask * 8; 1898 1899 return (pteidx); 1900 } 1901 1902 static struct pvo_entry * 1903 pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1904 { 1905 struct pvo_entry *pvo; 1906 int ptegidx; 1907 u_int sr; 1908 1909 va &= ~ADDR_POFF; 1910 sr = va_to_sr(pm->pm_sr, va); 1911 ptegidx = va_to_pteg(sr, va); 1912 1913 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1914 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1915 if (pteidx_p) 1916 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 1917 return (pvo); 1918 } 1919 } 1920 1921 return (NULL); 1922 } 1923 1924 static struct pte * 1925 pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 1926 { 1927 struct pte *pt; 1928 1929 /* 1930 * If we haven't been supplied the ptegidx, calculate it. 1931 */ 1932 if (pteidx == -1) { 1933 int ptegidx; 1934 u_int sr; 1935 1936 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 1937 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1938 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 1939 } 1940 1941 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 1942 1943 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 1944 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 1945 "valid pte index", pvo); 1946 } 1947 1948 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 1949 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 1950 "pvo but no valid pte", pvo); 1951 } 1952 1953 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 1954 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 1955 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 1956 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 1957 } 1958 1959 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 1960 != 0) { 1961 panic("pmap_pvo_to_pte: pvo %p pte does not match " 1962 "pte %p in pmap_pteg_table", pvo, pt); 1963 } 1964 1965 return (pt); 1966 } 1967 1968 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 1969 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 1970 "pmap_pteg_table but valid in pvo", pvo, pt); 1971 } 1972 1973 return (NULL); 1974 } 1975 1976 static void * 1977 pmap_pvo_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1978 { 1979 vm_page_t m; 1980 1981 if (bytes != PAGE_SIZE) 1982 panic("pmap_pvo_allocf: benno was shortsighted. hit him."); 1983 1984 *flags = UMA_SLAB_PRIV; 1985 m = vm_page_alloc(pmap_pvo_obj, pmap_pvo_count, VM_ALLOC_SYSTEM); 1986 if (m == NULL) 1987 return (NULL); 1988 pmap_pvo_count++; 1989 return ((void *)VM_PAGE_TO_PHYS(m)); 1990 } 1991 1992 /* 1993 * XXX: THIS STUFF SHOULD BE IN pte.c? 1994 */ 1995 int 1996 pmap_pte_spill(vm_offset_t addr) 1997 { 1998 struct pvo_entry *source_pvo, *victim_pvo; 1999 struct pvo_entry *pvo; 2000 int ptegidx, i, j; 2001 u_int sr; 2002 struct pteg *pteg; 2003 struct pte *pt; 2004 2005 pmap_pte_spills++; 2006 2007 sr = mfsrin(addr); 2008 ptegidx = va_to_pteg(sr, addr); 2009 2010 /* 2011 * Have to substitute some entry. Use the primary hash for this. 2012 * Use low bits of timebase as random generator. 2013 */ 2014 pteg = &pmap_pteg_table[ptegidx]; 2015 __asm __volatile("mftb %0" : "=r"(i)); 2016 i &= 7; 2017 pt = &pteg->pt[i]; 2018 2019 source_pvo = NULL; 2020 victim_pvo = NULL; 2021 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2022 /* 2023 * We need to find a pvo entry for this address. 2024 */ 2025 PMAP_PVO_CHECK(pvo); 2026 if (source_pvo == NULL && 2027 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2028 pvo->pvo_pte.pte_hi & PTE_HID)) { 2029 /* 2030 * Now found an entry to be spilled into the pteg. 2031 * The PTE is now valid, so we know it's active. 2032 */ 2033 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2034 2035 if (j >= 0) { 2036 PVO_PTEGIDX_SET(pvo, j); 2037 pmap_pte_overflow--; 2038 PMAP_PVO_CHECK(pvo); 2039 return (1); 2040 } 2041 2042 source_pvo = pvo; 2043 2044 if (victim_pvo != NULL) 2045 break; 2046 } 2047 2048 /* 2049 * We also need the pvo entry of the victim we are replacing 2050 * so save the R & C bits of the PTE. 2051 */ 2052 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2053 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2054 victim_pvo = pvo; 2055 if (source_pvo != NULL) 2056 break; 2057 } 2058 } 2059 2060 if (source_pvo == NULL) 2061 return (0); 2062 2063 if (victim_pvo == NULL) { 2064 if ((pt->pte_hi & PTE_HID) == 0) 2065 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2066 "entry", pt); 2067 2068 /* 2069 * If this is a secondary PTE, we need to search it's primary 2070 * pvo bucket for the matching PVO. 2071 */ 2072 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2073 pvo_olink) { 2074 PMAP_PVO_CHECK(pvo); 2075 /* 2076 * We also need the pvo entry of the victim we are 2077 * replacing so save the R & C bits of the PTE. 2078 */ 2079 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2080 victim_pvo = pvo; 2081 break; 2082 } 2083 } 2084 2085 if (victim_pvo == NULL) 2086 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2087 "entry", pt); 2088 } 2089 2090 /* 2091 * We are invalidating the TLB entry for the EA we are replacing even 2092 * though it's valid. If we don't, we lose any ref/chg bit changes 2093 * contained in the TLB entry. 2094 */ 2095 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2096 2097 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2098 pmap_pte_set(pt, &source_pvo->pvo_pte); 2099 2100 PVO_PTEGIDX_CLR(victim_pvo); 2101 PVO_PTEGIDX_SET(source_pvo, i); 2102 pmap_pte_replacements++; 2103 2104 PMAP_PVO_CHECK(victim_pvo); 2105 PMAP_PVO_CHECK(source_pvo); 2106 2107 return (1); 2108 } 2109 2110 static int 2111 pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2112 { 2113 struct pte *pt; 2114 int i; 2115 2116 /* 2117 * First try primary hash. 2118 */ 2119 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2120 if ((pt->pte_hi & PTE_VALID) == 0) { 2121 pvo_pt->pte_hi &= ~PTE_HID; 2122 pmap_pte_set(pt, pvo_pt); 2123 return (i); 2124 } 2125 } 2126 2127 /* 2128 * Now try secondary hash. 2129 */ 2130 ptegidx ^= pmap_pteg_mask; 2131 ptegidx++; 2132 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2133 if ((pt->pte_hi & PTE_VALID) == 0) { 2134 pvo_pt->pte_hi |= PTE_HID; 2135 pmap_pte_set(pt, pvo_pt); 2136 return (i); 2137 } 2138 } 2139 2140 panic("pmap_pte_insert: overflow"); 2141 return (-1); 2142 } 2143 2144 static boolean_t 2145 pmap_query_bit(vm_page_t m, int ptebit) 2146 { 2147 struct pvo_entry *pvo; 2148 struct pte *pt; 2149 2150 if (pmap_attr_fetch(m) & ptebit) 2151 return (TRUE); 2152 2153 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2154 PMAP_PVO_CHECK(pvo); /* sanity check */ 2155 2156 /* 2157 * See if we saved the bit off. If so, cache it and return 2158 * success. 2159 */ 2160 if (pvo->pvo_pte.pte_lo & ptebit) { 2161 pmap_attr_save(m, ptebit); 2162 PMAP_PVO_CHECK(pvo); /* sanity check */ 2163 return (TRUE); 2164 } 2165 } 2166 2167 /* 2168 * No luck, now go through the hard part of looking at the PTEs 2169 * themselves. Sync so that any pending REF/CHG bits are flushed to 2170 * the PTEs. 2171 */ 2172 SYNC(); 2173 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2174 PMAP_PVO_CHECK(pvo); /* sanity check */ 2175 2176 /* 2177 * See if this pvo has a valid PTE. if so, fetch the 2178 * REF/CHG bits from the valid PTE. If the appropriate 2179 * ptebit is set, cache it and return success. 2180 */ 2181 pt = pmap_pvo_to_pte(pvo, -1); 2182 if (pt != NULL) { 2183 pmap_pte_synch(pt, &pvo->pvo_pte); 2184 if (pvo->pvo_pte.pte_lo & ptebit) { 2185 pmap_attr_save(m, ptebit); 2186 PMAP_PVO_CHECK(pvo); /* sanity check */ 2187 return (TRUE); 2188 } 2189 } 2190 } 2191 2192 return (TRUE); 2193 } 2194 2195 static u_int 2196 pmap_clear_bit(vm_page_t m, int ptebit, int *origbit) 2197 { 2198 u_int count; 2199 struct pvo_entry *pvo; 2200 struct pte *pt; 2201 int rv; 2202 2203 /* 2204 * Clear the cached value. 2205 */ 2206 rv = pmap_attr_fetch(m); 2207 pmap_attr_clear(m, ptebit); 2208 2209 /* 2210 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2211 * we can reset the right ones). note that since the pvo entries and 2212 * list heads are accessed via BAT0 and are never placed in the page 2213 * table, we don't have to worry about further accesses setting the 2214 * REF/CHG bits. 2215 */ 2216 SYNC(); 2217 2218 /* 2219 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2220 * valid pte clear the ptebit from the valid pte. 2221 */ 2222 count = 0; 2223 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2224 PMAP_PVO_CHECK(pvo); /* sanity check */ 2225 pt = pmap_pvo_to_pte(pvo, -1); 2226 if (pt != NULL) { 2227 pmap_pte_synch(pt, &pvo->pvo_pte); 2228 if (pvo->pvo_pte.pte_lo & ptebit) { 2229 count++; 2230 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2231 } 2232 } 2233 rv |= pvo->pvo_pte.pte_lo; 2234 pvo->pvo_pte.pte_lo &= ~ptebit; 2235 PMAP_PVO_CHECK(pvo); /* sanity check */ 2236 } 2237 2238 if (origbit != NULL) { 2239 *origbit = rv; 2240 } 2241 2242 return (count); 2243 } 2244 2245 /* 2246 * Return true if the physical range is encompassed by the battable[idx] 2247 */ 2248 static int 2249 pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2250 { 2251 u_int prot; 2252 u_int32_t start; 2253 u_int32_t end; 2254 u_int32_t bat_ble; 2255 2256 /* 2257 * Return immediately if not a valid mapping 2258 */ 2259 if (!battable[idx].batu & BAT_Vs) 2260 return (EINVAL); 2261 2262 /* 2263 * The BAT entry must be cache-inhibited, guarded, and r/w 2264 * so it can function as an i/o page 2265 */ 2266 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2267 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2268 return (EPERM); 2269 2270 /* 2271 * The address should be within the BAT range. Assume that the 2272 * start address in the BAT has the correct alignment (thus 2273 * not requiring masking) 2274 */ 2275 start = battable[idx].batl & BAT_PBS; 2276 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2277 end = start | (bat_ble << 15) | 0x7fff; 2278 2279 if ((pa < start) || ((pa + size) > end)) 2280 return (ERANGE); 2281 2282 return (0); 2283 } 2284 2285 2286 /* 2287 * Map a set of physical memory pages into the kernel virtual 2288 * address space. Return a pointer to where it is mapped. This 2289 * routine is intended to be used for mapping device memory, 2290 * NOT real memory. 2291 */ 2292 void * 2293 pmap_mapdev(vm_offset_t pa, vm_size_t size) 2294 { 2295 vm_offset_t va, tmpva, ppa, offset; 2296 int i; 2297 2298 ppa = trunc_page(pa); 2299 offset = pa & PAGE_MASK; 2300 size = roundup(offset + size, PAGE_SIZE); 2301 2302 GIANT_REQUIRED; 2303 2304 /* 2305 * If the physical address lies within a valid BAT table entry, 2306 * return the 1:1 mapping. This currently doesn't work 2307 * for regions that overlap 256M BAT segments. 2308 */ 2309 for (i = 0; i < 16; i++) { 2310 if (pmap_bat_mapped(i, pa, size) == 0) 2311 return ((void *) pa); 2312 } 2313 2314 va = kmem_alloc_pageable(kernel_map, size); 2315 if (!va) 2316 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2317 2318 for (tmpva = va; size > 0;) { 2319 pmap_kenter(tmpva, ppa); 2320 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2321 size -= PAGE_SIZE; 2322 tmpva += PAGE_SIZE; 2323 ppa += PAGE_SIZE; 2324 } 2325 2326 return ((void *)(va + offset)); 2327 } 2328 2329 void 2330 pmap_unmapdev(vm_offset_t va, vm_size_t size) 2331 { 2332 vm_offset_t base, offset; 2333 2334 /* 2335 * If this is outside kernel virtual space, then it's a 2336 * battable entry and doesn't require unmapping 2337 */ 2338 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2339 base = trunc_page(va); 2340 offset = va & PAGE_MASK; 2341 size = roundup(offset + size, PAGE_SIZE); 2342 kmem_free(kernel_map, base, size); 2343 } 2344 } 2345