1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/conf.h> 110 #include <sys/queue.h> 111 #include <sys/cpuset.h> 112 #include <sys/kerneldump.h> 113 #include <sys/ktr.h> 114 #include <sys/lock.h> 115 #include <sys/msgbuf.h> 116 #include <sys/mutex.h> 117 #include <sys/proc.h> 118 #include <sys/rwlock.h> 119 #include <sys/sched.h> 120 #include <sys/sysctl.h> 121 #include <sys/systm.h> 122 #include <sys/vmmeter.h> 123 124 #include <dev/ofw/openfirm.h> 125 126 #include <vm/vm.h> 127 #include <vm/vm_param.h> 128 #include <vm/vm_kern.h> 129 #include <vm/vm_page.h> 130 #include <vm/vm_map.h> 131 #include <vm/vm_object.h> 132 #include <vm/vm_extern.h> 133 #include <vm/vm_pageout.h> 134 #include <vm/uma.h> 135 136 #include <machine/cpu.h> 137 #include <machine/platform.h> 138 #include <machine/bat.h> 139 #include <machine/frame.h> 140 #include <machine/md_var.h> 141 #include <machine/psl.h> 142 #include <machine/pte.h> 143 #include <machine/smp.h> 144 #include <machine/sr.h> 145 #include <machine/mmuvar.h> 146 #include <machine/trap.h> 147 148 #include "mmu_if.h" 149 150 #define MOEA_DEBUG 151 152 #define TODO panic("%s: not implemented", __func__); 153 154 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 155 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 156 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 157 158 struct ofw_map { 159 vm_offset_t om_va; 160 vm_size_t om_len; 161 vm_offset_t om_pa; 162 u_int om_mode; 163 }; 164 165 extern unsigned char _etext[]; 166 extern unsigned char _end[]; 167 168 /* 169 * Map of physical memory regions. 170 */ 171 static struct mem_region *regions; 172 static struct mem_region *pregions; 173 static u_int phys_avail_count; 174 static int regions_sz, pregions_sz; 175 static struct ofw_map *translations; 176 177 /* 178 * Lock for the pteg and pvo tables. 179 */ 180 struct mtx moea_table_mutex; 181 struct mtx moea_vsid_mutex; 182 183 /* tlbie instruction synchronization */ 184 static struct mtx tlbie_mtx; 185 186 /* 187 * PTEG data. 188 */ 189 static struct pteg *moea_pteg_table; 190 u_int moea_pteg_count; 191 u_int moea_pteg_mask; 192 193 /* 194 * PVO data. 195 */ 196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197 struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200 static struct rwlock_padalign pvh_global_lock; 201 202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205 #define BPVO_POOL_SIZE 32768 206 static struct pvo_entry *moea_bpvo_pool; 207 static int moea_bpvo_pool_index = 0; 208 209 #define VSID_NBPW (sizeof(u_int32_t) * 8) 210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212 static boolean_t moea_initialized = FALSE; 213 214 /* 215 * Statistics. 216 */ 217 u_int moea_pte_valid = 0; 218 u_int moea_pte_overflow = 0; 219 u_int moea_pte_replacements = 0; 220 u_int moea_pvo_entries = 0; 221 u_int moea_pvo_enter_calls = 0; 222 u_int moea_pvo_remove_calls = 0; 223 u_int moea_pte_spills = 0; 224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239 /* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244 /* 245 * PTE calls. 246 */ 247 static int moea_pte_insert(u_int, struct pte *); 248 249 /* 250 * PVO calls. 251 */ 252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_offset_t, u_int, int); 254 static void moea_pvo_remove(struct pvo_entry *, int); 255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258 /* 259 * Utility routines. 260 */ 261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, u_int, int8_t); 263 static void moea_syncicache(vm_offset_t, vm_size_t); 264 static boolean_t moea_query_bit(vm_page_t, int); 265 static u_int moea_clear_bit(vm_page_t, int); 266 static void moea_kremove(mmu_t, vm_offset_t); 267 int moea_pte_spill(vm_offset_t); 268 269 /* 270 * Kernel MMU interface 271 */ 272 void moea_clear_modify(mmu_t, vm_page_t); 273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 275 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 277 int8_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 int moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_zero_page(mmu_t, vm_page_t); 302 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 303 void moea_zero_page_idle(mmu_t, vm_page_t); 304 void moea_activate(mmu_t, struct thread *); 305 void moea_deactivate(mmu_t, struct thread *); 306 void moea_cpu_bootstrap(mmu_t, int); 307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 317 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 318 void moea_scan_init(mmu_t mmu); 319 320 static mmu_method_t moea_methods[] = { 321 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 322 MMUMETHOD(mmu_copy_page, moea_copy_page), 323 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 324 MMUMETHOD(mmu_enter, moea_enter), 325 MMUMETHOD(mmu_enter_object, moea_enter_object), 326 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 327 MMUMETHOD(mmu_extract, moea_extract), 328 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 329 MMUMETHOD(mmu_init, moea_init), 330 MMUMETHOD(mmu_is_modified, moea_is_modified), 331 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 332 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 333 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 334 MMUMETHOD(mmu_map, moea_map), 335 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 336 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 337 MMUMETHOD(mmu_pinit, moea_pinit), 338 MMUMETHOD(mmu_pinit0, moea_pinit0), 339 MMUMETHOD(mmu_protect, moea_protect), 340 MMUMETHOD(mmu_qenter, moea_qenter), 341 MMUMETHOD(mmu_qremove, moea_qremove), 342 MMUMETHOD(mmu_release, moea_release), 343 MMUMETHOD(mmu_remove, moea_remove), 344 MMUMETHOD(mmu_remove_all, moea_remove_all), 345 MMUMETHOD(mmu_remove_write, moea_remove_write), 346 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 347 MMUMETHOD(mmu_unwire, moea_unwire), 348 MMUMETHOD(mmu_zero_page, moea_zero_page), 349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 351 MMUMETHOD(mmu_activate, moea_activate), 352 MMUMETHOD(mmu_deactivate, moea_deactivate), 353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 354 355 /* Internal interfaces */ 356 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 359 MMUMETHOD(mmu_mapdev, moea_mapdev), 360 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 361 MMUMETHOD(mmu_kextract, moea_kextract), 362 MMUMETHOD(mmu_kenter, moea_kenter), 363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 365 MMUMETHOD(mmu_scan_init, moea_scan_init), 366 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 367 368 { 0, 0 } 369 }; 370 371 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 372 373 static __inline uint32_t 374 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 375 { 376 uint32_t pte_lo; 377 int i; 378 379 if (ma != VM_MEMATTR_DEFAULT) { 380 switch (ma) { 381 case VM_MEMATTR_UNCACHEABLE: 382 return (PTE_I | PTE_G); 383 case VM_MEMATTR_WRITE_COMBINING: 384 case VM_MEMATTR_WRITE_BACK: 385 case VM_MEMATTR_PREFETCHABLE: 386 return (PTE_I); 387 case VM_MEMATTR_WRITE_THROUGH: 388 return (PTE_W | PTE_M); 389 } 390 } 391 392 /* 393 * Assume the page is cache inhibited and access is guarded unless 394 * it's in our available memory array. 395 */ 396 pte_lo = PTE_I | PTE_G; 397 for (i = 0; i < pregions_sz; i++) { 398 if ((pa >= pregions[i].mr_start) && 399 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 400 pte_lo = PTE_M; 401 break; 402 } 403 } 404 405 return pte_lo; 406 } 407 408 static void 409 tlbie(vm_offset_t va) 410 { 411 412 mtx_lock_spin(&tlbie_mtx); 413 __asm __volatile("ptesync"); 414 __asm __volatile("tlbie %0" :: "r"(va)); 415 __asm __volatile("eieio; tlbsync; ptesync"); 416 mtx_unlock_spin(&tlbie_mtx); 417 } 418 419 static void 420 tlbia(void) 421 { 422 vm_offset_t va; 423 424 for (va = 0; va < 0x00040000; va += 0x00001000) { 425 __asm __volatile("tlbie %0" :: "r"(va)); 426 powerpc_sync(); 427 } 428 __asm __volatile("tlbsync"); 429 powerpc_sync(); 430 } 431 432 static __inline int 433 va_to_sr(u_int *sr, vm_offset_t va) 434 { 435 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 436 } 437 438 static __inline u_int 439 va_to_pteg(u_int sr, vm_offset_t addr) 440 { 441 u_int hash; 442 443 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 444 ADDR_PIDX_SHFT); 445 return (hash & moea_pteg_mask); 446 } 447 448 static __inline struct pvo_head * 449 vm_page_to_pvoh(vm_page_t m) 450 { 451 452 return (&m->md.mdpg_pvoh); 453 } 454 455 static __inline void 456 moea_attr_clear(vm_page_t m, int ptebit) 457 { 458 459 rw_assert(&pvh_global_lock, RA_WLOCKED); 460 m->md.mdpg_attrs &= ~ptebit; 461 } 462 463 static __inline int 464 moea_attr_fetch(vm_page_t m) 465 { 466 467 return (m->md.mdpg_attrs); 468 } 469 470 static __inline void 471 moea_attr_save(vm_page_t m, int ptebit) 472 { 473 474 rw_assert(&pvh_global_lock, RA_WLOCKED); 475 m->md.mdpg_attrs |= ptebit; 476 } 477 478 static __inline int 479 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 480 { 481 if (pt->pte_hi == pvo_pt->pte_hi) 482 return (1); 483 484 return (0); 485 } 486 487 static __inline int 488 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 489 { 490 return (pt->pte_hi & ~PTE_VALID) == 491 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 492 ((va >> ADDR_API_SHFT) & PTE_API) | which); 493 } 494 495 static __inline void 496 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 497 { 498 499 mtx_assert(&moea_table_mutex, MA_OWNED); 500 501 /* 502 * Construct a PTE. Default to IMB initially. Valid bit only gets 503 * set when the real pte is set in memory. 504 * 505 * Note: Don't set the valid bit for correct operation of tlb update. 506 */ 507 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 508 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 509 pt->pte_lo = pte_lo; 510 } 511 512 static __inline void 513 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 514 { 515 516 mtx_assert(&moea_table_mutex, MA_OWNED); 517 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 518 } 519 520 static __inline void 521 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 522 { 523 524 mtx_assert(&moea_table_mutex, MA_OWNED); 525 526 /* 527 * As shown in Section 7.6.3.2.3 528 */ 529 pt->pte_lo &= ~ptebit; 530 tlbie(va); 531 } 532 533 static __inline void 534 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 535 { 536 537 mtx_assert(&moea_table_mutex, MA_OWNED); 538 pvo_pt->pte_hi |= PTE_VALID; 539 540 /* 541 * Update the PTE as defined in section 7.6.3.1. 542 * Note that the REF/CHG bits are from pvo_pt and thus should have 543 * been saved so this routine can restore them (if desired). 544 */ 545 pt->pte_lo = pvo_pt->pte_lo; 546 powerpc_sync(); 547 pt->pte_hi = pvo_pt->pte_hi; 548 powerpc_sync(); 549 moea_pte_valid++; 550 } 551 552 static __inline void 553 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 554 { 555 556 mtx_assert(&moea_table_mutex, MA_OWNED); 557 pvo_pt->pte_hi &= ~PTE_VALID; 558 559 /* 560 * Force the reg & chg bits back into the PTEs. 561 */ 562 powerpc_sync(); 563 564 /* 565 * Invalidate the pte. 566 */ 567 pt->pte_hi &= ~PTE_VALID; 568 569 tlbie(va); 570 571 /* 572 * Save the reg & chg bits. 573 */ 574 moea_pte_synch(pt, pvo_pt); 575 moea_pte_valid--; 576 } 577 578 static __inline void 579 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 580 { 581 582 /* 583 * Invalidate the PTE 584 */ 585 moea_pte_unset(pt, pvo_pt, va); 586 moea_pte_set(pt, pvo_pt); 587 } 588 589 /* 590 * Quick sort callout for comparing memory regions. 591 */ 592 static int om_cmp(const void *a, const void *b); 593 594 static int 595 om_cmp(const void *a, const void *b) 596 { 597 const struct ofw_map *mapa; 598 const struct ofw_map *mapb; 599 600 mapa = a; 601 mapb = b; 602 if (mapa->om_pa < mapb->om_pa) 603 return (-1); 604 else if (mapa->om_pa > mapb->om_pa) 605 return (1); 606 else 607 return (0); 608 } 609 610 void 611 moea_cpu_bootstrap(mmu_t mmup, int ap) 612 { 613 u_int sdr; 614 int i; 615 616 if (ap) { 617 powerpc_sync(); 618 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 619 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 620 isync(); 621 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 622 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 623 isync(); 624 } 625 626 #ifdef WII 627 /* 628 * Special case for the Wii: don't install the PCI BAT. 629 */ 630 if (strcmp(installed_platform(), "wii") != 0) { 631 #endif 632 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 633 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 634 #ifdef WII 635 } 636 #endif 637 isync(); 638 639 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 640 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 641 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 642 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 643 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 644 isync(); 645 646 for (i = 0; i < 16; i++) 647 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 648 powerpc_sync(); 649 650 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 651 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 652 isync(); 653 654 tlbia(); 655 } 656 657 void 658 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 659 { 660 ihandle_t mmui; 661 phandle_t chosen, mmu; 662 int sz; 663 int i, j; 664 vm_size_t size, physsz, hwphyssz; 665 vm_offset_t pa, va, off; 666 void *dpcpu; 667 register_t msr; 668 669 /* 670 * Set up BAT0 to map the lowest 256 MB area 671 */ 672 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 673 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 674 675 /* 676 * Map PCI memory space. 677 */ 678 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 679 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 680 681 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 682 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 683 684 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 686 687 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 689 690 /* 691 * Map obio devices. 692 */ 693 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 694 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 695 696 /* 697 * Use an IBAT and a DBAT to map the bottom segment of memory 698 * where we are. Turn off instruction relocation temporarily 699 * to prevent faults while reprogramming the IBAT. 700 */ 701 msr = mfmsr(); 702 mtmsr(msr & ~PSL_IR); 703 __asm (".balign 32; \n" 704 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 705 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 706 :: "r"(battable[0].batu), "r"(battable[0].batl)); 707 mtmsr(msr); 708 709 #ifdef WII 710 if (strcmp(installed_platform(), "wii") != 0) { 711 #endif 712 /* map pci space */ 713 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 714 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 715 #ifdef WII 716 } 717 #endif 718 isync(); 719 720 /* set global direct map flag */ 721 hw_direct_map = 1; 722 723 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 724 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 725 726 for (i = 0; i < pregions_sz; i++) { 727 vm_offset_t pa; 728 vm_offset_t end; 729 730 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 731 pregions[i].mr_start, 732 pregions[i].mr_start + pregions[i].mr_size, 733 pregions[i].mr_size); 734 /* 735 * Install entries into the BAT table to allow all 736 * of physmem to be convered by on-demand BAT entries. 737 * The loop will sometimes set the same battable element 738 * twice, but that's fine since they won't be used for 739 * a while yet. 740 */ 741 pa = pregions[i].mr_start & 0xf0000000; 742 end = pregions[i].mr_start + pregions[i].mr_size; 743 do { 744 u_int n = pa >> ADDR_SR_SHFT; 745 746 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 747 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 748 pa += SEGMENT_LENGTH; 749 } while (pa < end); 750 } 751 752 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 753 panic("moea_bootstrap: phys_avail too small"); 754 755 phys_avail_count = 0; 756 physsz = 0; 757 hwphyssz = 0; 758 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 759 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 760 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 761 regions[i].mr_start + regions[i].mr_size, 762 regions[i].mr_size); 763 if (hwphyssz != 0 && 764 (physsz + regions[i].mr_size) >= hwphyssz) { 765 if (physsz < hwphyssz) { 766 phys_avail[j] = regions[i].mr_start; 767 phys_avail[j + 1] = regions[i].mr_start + 768 hwphyssz - physsz; 769 physsz = hwphyssz; 770 phys_avail_count++; 771 } 772 break; 773 } 774 phys_avail[j] = regions[i].mr_start; 775 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 776 phys_avail_count++; 777 physsz += regions[i].mr_size; 778 } 779 780 /* Check for overlap with the kernel and exception vectors */ 781 for (j = 0; j < 2*phys_avail_count; j+=2) { 782 if (phys_avail[j] < EXC_LAST) 783 phys_avail[j] += EXC_LAST; 784 785 if (kernelstart >= phys_avail[j] && 786 kernelstart < phys_avail[j+1]) { 787 if (kernelend < phys_avail[j+1]) { 788 phys_avail[2*phys_avail_count] = 789 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 790 phys_avail[2*phys_avail_count + 1] = 791 phys_avail[j+1]; 792 phys_avail_count++; 793 } 794 795 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 796 } 797 798 if (kernelend >= phys_avail[j] && 799 kernelend < phys_avail[j+1]) { 800 if (kernelstart > phys_avail[j]) { 801 phys_avail[2*phys_avail_count] = phys_avail[j]; 802 phys_avail[2*phys_avail_count + 1] = 803 kernelstart & ~PAGE_MASK; 804 phys_avail_count++; 805 } 806 807 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 808 } 809 } 810 811 physmem = btoc(physsz); 812 813 /* 814 * Allocate PTEG table. 815 */ 816 #ifdef PTEGCOUNT 817 moea_pteg_count = PTEGCOUNT; 818 #else 819 moea_pteg_count = 0x1000; 820 821 while (moea_pteg_count < physmem) 822 moea_pteg_count <<= 1; 823 824 moea_pteg_count >>= 1; 825 #endif /* PTEGCOUNT */ 826 827 size = moea_pteg_count * sizeof(struct pteg); 828 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 829 size); 830 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 831 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 832 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 833 moea_pteg_mask = moea_pteg_count - 1; 834 835 /* 836 * Allocate pv/overflow lists. 837 */ 838 size = sizeof(struct pvo_head) * moea_pteg_count; 839 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 840 PAGE_SIZE); 841 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 842 for (i = 0; i < moea_pteg_count; i++) 843 LIST_INIT(&moea_pvo_table[i]); 844 845 /* 846 * Initialize the lock that synchronizes access to the pteg and pvo 847 * tables. 848 */ 849 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 850 MTX_RECURSE); 851 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 852 853 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 854 855 /* 856 * Initialise the unmanaged pvo pool. 857 */ 858 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 859 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 860 moea_bpvo_pool_index = 0; 861 862 /* 863 * Make sure kernel vsid is allocated as well as VSID 0. 864 */ 865 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 866 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 867 moea_vsid_bitmap[0] |= 1; 868 869 /* 870 * Initialize the kernel pmap (which is statically allocated). 871 */ 872 PMAP_LOCK_INIT(kernel_pmap); 873 for (i = 0; i < 16; i++) 874 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 875 CPU_FILL(&kernel_pmap->pm_active); 876 RB_INIT(&kernel_pmap->pmap_pvo); 877 878 /* 879 * Initialize the global pv list lock. 880 */ 881 rw_init(&pvh_global_lock, "pmap pv global"); 882 883 /* 884 * Set up the Open Firmware mappings 885 */ 886 chosen = OF_finddevice("/chosen"); 887 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 888 (mmu = OF_instance_to_package(mmui)) != -1 && 889 (sz = OF_getproplen(mmu, "translations")) != -1) { 890 translations = NULL; 891 for (i = 0; phys_avail[i] != 0; i += 2) { 892 if (phys_avail[i + 1] >= sz) { 893 translations = (struct ofw_map *)phys_avail[i]; 894 break; 895 } 896 } 897 if (translations == NULL) 898 panic("moea_bootstrap: no space to copy translations"); 899 bzero(translations, sz); 900 if (OF_getprop(mmu, "translations", translations, sz) == -1) 901 panic("moea_bootstrap: can't get ofw translations"); 902 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 903 sz /= sizeof(*translations); 904 qsort(translations, sz, sizeof (*translations), om_cmp); 905 for (i = 0; i < sz; i++) { 906 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 907 translations[i].om_pa, translations[i].om_va, 908 translations[i].om_len); 909 910 /* 911 * If the mapping is 1:1, let the RAM and device 912 * on-demand BAT tables take care of the translation. 913 */ 914 if (translations[i].om_va == translations[i].om_pa) 915 continue; 916 917 /* Enter the pages */ 918 for (off = 0; off < translations[i].om_len; 919 off += PAGE_SIZE) 920 moea_kenter(mmup, translations[i].om_va + off, 921 translations[i].om_pa + off); 922 } 923 } 924 925 /* 926 * Calculate the last available physical address. 927 */ 928 for (i = 0; phys_avail[i + 2] != 0; i += 2) 929 ; 930 Maxmem = powerpc_btop(phys_avail[i + 1]); 931 932 moea_cpu_bootstrap(mmup,0); 933 934 pmap_bootstrapped++; 935 936 /* 937 * Set the start and end of kva. 938 */ 939 virtual_avail = VM_MIN_KERNEL_ADDRESS; 940 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 941 942 /* 943 * Allocate a kernel stack with a guard page for thread0 and map it 944 * into the kernel page map. 945 */ 946 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 947 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 948 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 949 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 950 thread0.td_kstack = va; 951 thread0.td_kstack_pages = KSTACK_PAGES; 952 for (i = 0; i < KSTACK_PAGES; i++) { 953 moea_kenter(mmup, va, pa); 954 pa += PAGE_SIZE; 955 va += PAGE_SIZE; 956 } 957 958 /* 959 * Allocate virtual address space for the message buffer. 960 */ 961 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 962 msgbufp = (struct msgbuf *)virtual_avail; 963 va = virtual_avail; 964 virtual_avail += round_page(msgbufsize); 965 while (va < virtual_avail) { 966 moea_kenter(mmup, va, pa); 967 pa += PAGE_SIZE; 968 va += PAGE_SIZE; 969 } 970 971 /* 972 * Allocate virtual address space for the dynamic percpu area. 973 */ 974 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 975 dpcpu = (void *)virtual_avail; 976 va = virtual_avail; 977 virtual_avail += DPCPU_SIZE; 978 while (va < virtual_avail) { 979 moea_kenter(mmup, va, pa); 980 pa += PAGE_SIZE; 981 va += PAGE_SIZE; 982 } 983 dpcpu_init(dpcpu, 0); 984 } 985 986 /* 987 * Activate a user pmap. The pmap must be activated before it's address 988 * space can be accessed in any way. 989 */ 990 void 991 moea_activate(mmu_t mmu, struct thread *td) 992 { 993 pmap_t pm, pmr; 994 995 /* 996 * Load all the data we need up front to encourage the compiler to 997 * not issue any loads while we have interrupts disabled below. 998 */ 999 pm = &td->td_proc->p_vmspace->vm_pmap; 1000 pmr = pm->pmap_phys; 1001 1002 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1003 PCPU_SET(curpmap, pmr); 1004 } 1005 1006 void 1007 moea_deactivate(mmu_t mmu, struct thread *td) 1008 { 1009 pmap_t pm; 1010 1011 pm = &td->td_proc->p_vmspace->vm_pmap; 1012 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1013 PCPU_SET(curpmap, NULL); 1014 } 1015 1016 void 1017 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1018 { 1019 struct pvo_entry key, *pvo; 1020 1021 PMAP_LOCK(pm); 1022 key.pvo_vaddr = sva; 1023 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1024 pvo != NULL && PVO_VADDR(pvo) < eva; 1025 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1026 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1027 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1028 pvo->pvo_vaddr &= ~PVO_WIRED; 1029 pm->pm_stats.wired_count--; 1030 } 1031 PMAP_UNLOCK(pm); 1032 } 1033 1034 void 1035 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1036 { 1037 vm_offset_t dst; 1038 vm_offset_t src; 1039 1040 dst = VM_PAGE_TO_PHYS(mdst); 1041 src = VM_PAGE_TO_PHYS(msrc); 1042 1043 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1044 } 1045 1046 void 1047 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1048 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1049 { 1050 void *a_cp, *b_cp; 1051 vm_offset_t a_pg_offset, b_pg_offset; 1052 int cnt; 1053 1054 while (xfersize > 0) { 1055 a_pg_offset = a_offset & PAGE_MASK; 1056 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1057 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1058 a_pg_offset; 1059 b_pg_offset = b_offset & PAGE_MASK; 1060 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1061 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1062 b_pg_offset; 1063 bcopy(a_cp, b_cp, cnt); 1064 a_offset += cnt; 1065 b_offset += cnt; 1066 xfersize -= cnt; 1067 } 1068 } 1069 1070 /* 1071 * Zero a page of physical memory by temporarily mapping it into the tlb. 1072 */ 1073 void 1074 moea_zero_page(mmu_t mmu, vm_page_t m) 1075 { 1076 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1077 1078 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1079 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1080 } 1081 1082 void 1083 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1084 { 1085 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1086 void *va = (void *)(pa + off); 1087 1088 bzero(va, size); 1089 } 1090 1091 void 1092 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1093 { 1094 1095 moea_zero_page(mmu, m); 1096 } 1097 1098 /* 1099 * Map the given physical page at the specified virtual address in the 1100 * target pmap with the protection requested. If specified the page 1101 * will be wired down. 1102 */ 1103 int 1104 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1105 u_int flags, int8_t psind) 1106 { 1107 int error; 1108 1109 for (;;) { 1110 rw_wlock(&pvh_global_lock); 1111 PMAP_LOCK(pmap); 1112 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1113 rw_wunlock(&pvh_global_lock); 1114 PMAP_UNLOCK(pmap); 1115 if (error != ENOMEM) 1116 return (KERN_SUCCESS); 1117 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1118 return (KERN_RESOURCE_SHORTAGE); 1119 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1120 VM_WAIT; 1121 } 1122 } 1123 1124 /* 1125 * Map the given physical page at the specified virtual address in the 1126 * target pmap with the protection requested. If specified the page 1127 * will be wired down. 1128 * 1129 * The global pvh and pmap must be locked. 1130 */ 1131 static int 1132 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1133 u_int flags, int8_t psind __unused) 1134 { 1135 struct pvo_head *pvo_head; 1136 uma_zone_t zone; 1137 u_int pte_lo, pvo_flags; 1138 int error; 1139 1140 if (pmap_bootstrapped) 1141 rw_assert(&pvh_global_lock, RA_WLOCKED); 1142 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1143 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1144 VM_OBJECT_ASSERT_LOCKED(m->object); 1145 1146 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1147 pvo_head = &moea_pvo_kunmanaged; 1148 zone = moea_upvo_zone; 1149 pvo_flags = 0; 1150 } else { 1151 pvo_head = vm_page_to_pvoh(m); 1152 zone = moea_mpvo_zone; 1153 pvo_flags = PVO_MANAGED; 1154 } 1155 1156 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1157 1158 if (prot & VM_PROT_WRITE) { 1159 pte_lo |= PTE_BW; 1160 if (pmap_bootstrapped && 1161 (m->oflags & VPO_UNMANAGED) == 0) 1162 vm_page_aflag_set(m, PGA_WRITEABLE); 1163 } else 1164 pte_lo |= PTE_BR; 1165 1166 if ((flags & PMAP_ENTER_WIRED) != 0) 1167 pvo_flags |= PVO_WIRED; 1168 1169 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1170 pte_lo, pvo_flags); 1171 1172 /* 1173 * Flush the real page from the instruction cache. This has be done 1174 * for all user mappings to prevent information leakage via the 1175 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1176 * mapping for a page. 1177 */ 1178 if (pmap != kernel_pmap && error == ENOENT && 1179 (pte_lo & (PTE_I | PTE_G)) == 0) 1180 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1181 1182 return (error); 1183 } 1184 1185 /* 1186 * Maps a sequence of resident pages belonging to the same object. 1187 * The sequence begins with the given page m_start. This page is 1188 * mapped at the given virtual address start. Each subsequent page is 1189 * mapped at a virtual address that is offset from start by the same 1190 * amount as the page is offset from m_start within the object. The 1191 * last page in the sequence is the page with the largest offset from 1192 * m_start that can be mapped at a virtual address less than the given 1193 * virtual address end. Not every virtual page between start and end 1194 * is mapped; only those for which a resident page exists with the 1195 * corresponding offset from m_start are mapped. 1196 */ 1197 void 1198 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1199 vm_page_t m_start, vm_prot_t prot) 1200 { 1201 vm_page_t m; 1202 vm_pindex_t diff, psize; 1203 1204 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1205 1206 psize = atop(end - start); 1207 m = m_start; 1208 rw_wlock(&pvh_global_lock); 1209 PMAP_LOCK(pm); 1210 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1211 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1212 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1213 m = TAILQ_NEXT(m, listq); 1214 } 1215 rw_wunlock(&pvh_global_lock); 1216 PMAP_UNLOCK(pm); 1217 } 1218 1219 void 1220 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1221 vm_prot_t prot) 1222 { 1223 1224 rw_wlock(&pvh_global_lock); 1225 PMAP_LOCK(pm); 1226 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1227 0, 0); 1228 rw_wunlock(&pvh_global_lock); 1229 PMAP_UNLOCK(pm); 1230 } 1231 1232 vm_paddr_t 1233 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1234 { 1235 struct pvo_entry *pvo; 1236 vm_paddr_t pa; 1237 1238 PMAP_LOCK(pm); 1239 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1240 if (pvo == NULL) 1241 pa = 0; 1242 else 1243 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1244 PMAP_UNLOCK(pm); 1245 return (pa); 1246 } 1247 1248 /* 1249 * Atomically extract and hold the physical page with the given 1250 * pmap and virtual address pair if that mapping permits the given 1251 * protection. 1252 */ 1253 vm_page_t 1254 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1255 { 1256 struct pvo_entry *pvo; 1257 vm_page_t m; 1258 vm_paddr_t pa; 1259 1260 m = NULL; 1261 pa = 0; 1262 PMAP_LOCK(pmap); 1263 retry: 1264 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1265 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1266 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1267 (prot & VM_PROT_WRITE) == 0)) { 1268 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1269 goto retry; 1270 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1271 vm_page_hold(m); 1272 } 1273 PA_UNLOCK_COND(pa); 1274 PMAP_UNLOCK(pmap); 1275 return (m); 1276 } 1277 1278 void 1279 moea_init(mmu_t mmu) 1280 { 1281 1282 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1283 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1284 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1285 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1286 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1287 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1288 moea_initialized = TRUE; 1289 } 1290 1291 boolean_t 1292 moea_is_referenced(mmu_t mmu, vm_page_t m) 1293 { 1294 boolean_t rv; 1295 1296 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1297 ("moea_is_referenced: page %p is not managed", m)); 1298 rw_wlock(&pvh_global_lock); 1299 rv = moea_query_bit(m, PTE_REF); 1300 rw_wunlock(&pvh_global_lock); 1301 return (rv); 1302 } 1303 1304 boolean_t 1305 moea_is_modified(mmu_t mmu, vm_page_t m) 1306 { 1307 boolean_t rv; 1308 1309 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1310 ("moea_is_modified: page %p is not managed", m)); 1311 1312 /* 1313 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1314 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1315 * is clear, no PTEs can have PTE_CHG set. 1316 */ 1317 VM_OBJECT_ASSERT_WLOCKED(m->object); 1318 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1319 return (FALSE); 1320 rw_wlock(&pvh_global_lock); 1321 rv = moea_query_bit(m, PTE_CHG); 1322 rw_wunlock(&pvh_global_lock); 1323 return (rv); 1324 } 1325 1326 boolean_t 1327 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1328 { 1329 struct pvo_entry *pvo; 1330 boolean_t rv; 1331 1332 PMAP_LOCK(pmap); 1333 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1334 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1335 PMAP_UNLOCK(pmap); 1336 return (rv); 1337 } 1338 1339 void 1340 moea_clear_modify(mmu_t mmu, vm_page_t m) 1341 { 1342 1343 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1344 ("moea_clear_modify: page %p is not managed", m)); 1345 VM_OBJECT_ASSERT_WLOCKED(m->object); 1346 KASSERT(!vm_page_xbusied(m), 1347 ("moea_clear_modify: page %p is exclusive busy", m)); 1348 1349 /* 1350 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1351 * set. If the object containing the page is locked and the page is 1352 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1353 */ 1354 if ((m->aflags & PGA_WRITEABLE) == 0) 1355 return; 1356 rw_wlock(&pvh_global_lock); 1357 moea_clear_bit(m, PTE_CHG); 1358 rw_wunlock(&pvh_global_lock); 1359 } 1360 1361 /* 1362 * Clear the write and modified bits in each of the given page's mappings. 1363 */ 1364 void 1365 moea_remove_write(mmu_t mmu, vm_page_t m) 1366 { 1367 struct pvo_entry *pvo; 1368 struct pte *pt; 1369 pmap_t pmap; 1370 u_int lo; 1371 1372 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1373 ("moea_remove_write: page %p is not managed", m)); 1374 1375 /* 1376 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1377 * set by another thread while the object is locked. Thus, 1378 * if PGA_WRITEABLE is clear, no page table entries need updating. 1379 */ 1380 VM_OBJECT_ASSERT_WLOCKED(m->object); 1381 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1382 return; 1383 rw_wlock(&pvh_global_lock); 1384 lo = moea_attr_fetch(m); 1385 powerpc_sync(); 1386 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1387 pmap = pvo->pvo_pmap; 1388 PMAP_LOCK(pmap); 1389 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1390 pt = moea_pvo_to_pte(pvo, -1); 1391 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1392 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1393 if (pt != NULL) { 1394 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1395 lo |= pvo->pvo_pte.pte.pte_lo; 1396 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1397 moea_pte_change(pt, &pvo->pvo_pte.pte, 1398 pvo->pvo_vaddr); 1399 mtx_unlock(&moea_table_mutex); 1400 } 1401 } 1402 PMAP_UNLOCK(pmap); 1403 } 1404 if ((lo & PTE_CHG) != 0) { 1405 moea_attr_clear(m, PTE_CHG); 1406 vm_page_dirty(m); 1407 } 1408 vm_page_aflag_clear(m, PGA_WRITEABLE); 1409 rw_wunlock(&pvh_global_lock); 1410 } 1411 1412 /* 1413 * moea_ts_referenced: 1414 * 1415 * Return a count of reference bits for a page, clearing those bits. 1416 * It is not necessary for every reference bit to be cleared, but it 1417 * is necessary that 0 only be returned when there are truly no 1418 * reference bits set. 1419 * 1420 * XXX: The exact number of bits to check and clear is a matter that 1421 * should be tested and standardized at some point in the future for 1422 * optimal aging of shared pages. 1423 */ 1424 int 1425 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1426 { 1427 int count; 1428 1429 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1430 ("moea_ts_referenced: page %p is not managed", m)); 1431 rw_wlock(&pvh_global_lock); 1432 count = moea_clear_bit(m, PTE_REF); 1433 rw_wunlock(&pvh_global_lock); 1434 return (count); 1435 } 1436 1437 /* 1438 * Modify the WIMG settings of all mappings for a page. 1439 */ 1440 void 1441 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1442 { 1443 struct pvo_entry *pvo; 1444 struct pvo_head *pvo_head; 1445 struct pte *pt; 1446 pmap_t pmap; 1447 u_int lo; 1448 1449 if ((m->oflags & VPO_UNMANAGED) != 0) { 1450 m->md.mdpg_cache_attrs = ma; 1451 return; 1452 } 1453 1454 rw_wlock(&pvh_global_lock); 1455 pvo_head = vm_page_to_pvoh(m); 1456 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1457 1458 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1459 pmap = pvo->pvo_pmap; 1460 PMAP_LOCK(pmap); 1461 pt = moea_pvo_to_pte(pvo, -1); 1462 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1463 pvo->pvo_pte.pte.pte_lo |= lo; 1464 if (pt != NULL) { 1465 moea_pte_change(pt, &pvo->pvo_pte.pte, 1466 pvo->pvo_vaddr); 1467 if (pvo->pvo_pmap == kernel_pmap) 1468 isync(); 1469 } 1470 mtx_unlock(&moea_table_mutex); 1471 PMAP_UNLOCK(pmap); 1472 } 1473 m->md.mdpg_cache_attrs = ma; 1474 rw_wunlock(&pvh_global_lock); 1475 } 1476 1477 /* 1478 * Map a wired page into kernel virtual address space. 1479 */ 1480 void 1481 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1482 { 1483 1484 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1485 } 1486 1487 void 1488 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1489 { 1490 u_int pte_lo; 1491 int error; 1492 1493 #if 0 1494 if (va < VM_MIN_KERNEL_ADDRESS) 1495 panic("moea_kenter: attempt to enter non-kernel address %#x", 1496 va); 1497 #endif 1498 1499 pte_lo = moea_calc_wimg(pa, ma); 1500 1501 PMAP_LOCK(kernel_pmap); 1502 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1503 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1504 1505 if (error != 0 && error != ENOENT) 1506 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1507 pa, error); 1508 1509 PMAP_UNLOCK(kernel_pmap); 1510 } 1511 1512 /* 1513 * Extract the physical page address associated with the given kernel virtual 1514 * address. 1515 */ 1516 vm_paddr_t 1517 moea_kextract(mmu_t mmu, vm_offset_t va) 1518 { 1519 struct pvo_entry *pvo; 1520 vm_paddr_t pa; 1521 1522 /* 1523 * Allow direct mappings on 32-bit OEA 1524 */ 1525 if (va < VM_MIN_KERNEL_ADDRESS) { 1526 return (va); 1527 } 1528 1529 PMAP_LOCK(kernel_pmap); 1530 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1531 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1532 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1533 PMAP_UNLOCK(kernel_pmap); 1534 return (pa); 1535 } 1536 1537 /* 1538 * Remove a wired page from kernel virtual address space. 1539 */ 1540 void 1541 moea_kremove(mmu_t mmu, vm_offset_t va) 1542 { 1543 1544 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1545 } 1546 1547 /* 1548 * Map a range of physical addresses into kernel virtual address space. 1549 * 1550 * The value passed in *virt is a suggested virtual address for the mapping. 1551 * Architectures which can support a direct-mapped physical to virtual region 1552 * can return the appropriate address within that region, leaving '*virt' 1553 * unchanged. We cannot and therefore do not; *virt is updated with the 1554 * first usable address after the mapped region. 1555 */ 1556 vm_offset_t 1557 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1558 vm_paddr_t pa_end, int prot) 1559 { 1560 vm_offset_t sva, va; 1561 1562 sva = *virt; 1563 va = sva; 1564 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1565 moea_kenter(mmu, va, pa_start); 1566 *virt = va; 1567 return (sva); 1568 } 1569 1570 /* 1571 * Returns true if the pmap's pv is one of the first 1572 * 16 pvs linked to from this page. This count may 1573 * be changed upwards or downwards in the future; it 1574 * is only necessary that true be returned for a small 1575 * subset of pmaps for proper page aging. 1576 */ 1577 boolean_t 1578 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1579 { 1580 int loops; 1581 struct pvo_entry *pvo; 1582 boolean_t rv; 1583 1584 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1585 ("moea_page_exists_quick: page %p is not managed", m)); 1586 loops = 0; 1587 rv = FALSE; 1588 rw_wlock(&pvh_global_lock); 1589 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1590 if (pvo->pvo_pmap == pmap) { 1591 rv = TRUE; 1592 break; 1593 } 1594 if (++loops >= 16) 1595 break; 1596 } 1597 rw_wunlock(&pvh_global_lock); 1598 return (rv); 1599 } 1600 1601 /* 1602 * Return the number of managed mappings to the given physical page 1603 * that are wired. 1604 */ 1605 int 1606 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1607 { 1608 struct pvo_entry *pvo; 1609 int count; 1610 1611 count = 0; 1612 if ((m->oflags & VPO_UNMANAGED) != 0) 1613 return (count); 1614 rw_wlock(&pvh_global_lock); 1615 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1616 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1617 count++; 1618 rw_wunlock(&pvh_global_lock); 1619 return (count); 1620 } 1621 1622 static u_int moea_vsidcontext; 1623 1624 void 1625 moea_pinit(mmu_t mmu, pmap_t pmap) 1626 { 1627 int i, mask; 1628 u_int entropy; 1629 1630 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1631 RB_INIT(&pmap->pmap_pvo); 1632 1633 entropy = 0; 1634 __asm __volatile("mftb %0" : "=r"(entropy)); 1635 1636 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1637 == NULL) { 1638 pmap->pmap_phys = pmap; 1639 } 1640 1641 1642 mtx_lock(&moea_vsid_mutex); 1643 /* 1644 * Allocate some segment registers for this pmap. 1645 */ 1646 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1647 u_int hash, n; 1648 1649 /* 1650 * Create a new value by mutiplying by a prime and adding in 1651 * entropy from the timebase register. This is to make the 1652 * VSID more random so that the PT hash function collides 1653 * less often. (Note that the prime casues gcc to do shifts 1654 * instead of a multiply.) 1655 */ 1656 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1657 hash = moea_vsidcontext & (NPMAPS - 1); 1658 if (hash == 0) /* 0 is special, avoid it */ 1659 continue; 1660 n = hash >> 5; 1661 mask = 1 << (hash & (VSID_NBPW - 1)); 1662 hash = (moea_vsidcontext & 0xfffff); 1663 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1664 /* anything free in this bucket? */ 1665 if (moea_vsid_bitmap[n] == 0xffffffff) { 1666 entropy = (moea_vsidcontext >> 20); 1667 continue; 1668 } 1669 i = ffs(~moea_vsid_bitmap[n]) - 1; 1670 mask = 1 << i; 1671 hash &= 0xfffff & ~(VSID_NBPW - 1); 1672 hash |= i; 1673 } 1674 KASSERT(!(moea_vsid_bitmap[n] & mask), 1675 ("Allocating in-use VSID group %#x\n", hash)); 1676 moea_vsid_bitmap[n] |= mask; 1677 for (i = 0; i < 16; i++) 1678 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1679 mtx_unlock(&moea_vsid_mutex); 1680 return; 1681 } 1682 1683 mtx_unlock(&moea_vsid_mutex); 1684 panic("moea_pinit: out of segments"); 1685 } 1686 1687 /* 1688 * Initialize the pmap associated with process 0. 1689 */ 1690 void 1691 moea_pinit0(mmu_t mmu, pmap_t pm) 1692 { 1693 1694 PMAP_LOCK_INIT(pm); 1695 moea_pinit(mmu, pm); 1696 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1697 } 1698 1699 /* 1700 * Set the physical protection on the specified range of this map as requested. 1701 */ 1702 void 1703 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1704 vm_prot_t prot) 1705 { 1706 struct pvo_entry *pvo, *tpvo, key; 1707 struct pte *pt; 1708 1709 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1710 ("moea_protect: non current pmap")); 1711 1712 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1713 moea_remove(mmu, pm, sva, eva); 1714 return; 1715 } 1716 1717 rw_wlock(&pvh_global_lock); 1718 PMAP_LOCK(pm); 1719 key.pvo_vaddr = sva; 1720 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1721 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1722 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1723 1724 /* 1725 * Grab the PTE pointer before we diddle with the cached PTE 1726 * copy. 1727 */ 1728 pt = moea_pvo_to_pte(pvo, -1); 1729 /* 1730 * Change the protection of the page. 1731 */ 1732 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1733 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1734 1735 /* 1736 * If the PVO is in the page table, update that pte as well. 1737 */ 1738 if (pt != NULL) { 1739 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1740 mtx_unlock(&moea_table_mutex); 1741 } 1742 } 1743 rw_wunlock(&pvh_global_lock); 1744 PMAP_UNLOCK(pm); 1745 } 1746 1747 /* 1748 * Map a list of wired pages into kernel virtual address space. This is 1749 * intended for temporary mappings which do not need page modification or 1750 * references recorded. Existing mappings in the region are overwritten. 1751 */ 1752 void 1753 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1754 { 1755 vm_offset_t va; 1756 1757 va = sva; 1758 while (count-- > 0) { 1759 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1760 va += PAGE_SIZE; 1761 m++; 1762 } 1763 } 1764 1765 /* 1766 * Remove page mappings from kernel virtual address space. Intended for 1767 * temporary mappings entered by moea_qenter. 1768 */ 1769 void 1770 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1771 { 1772 vm_offset_t va; 1773 1774 va = sva; 1775 while (count-- > 0) { 1776 moea_kremove(mmu, va); 1777 va += PAGE_SIZE; 1778 } 1779 } 1780 1781 void 1782 moea_release(mmu_t mmu, pmap_t pmap) 1783 { 1784 int idx, mask; 1785 1786 /* 1787 * Free segment register's VSID 1788 */ 1789 if (pmap->pm_sr[0] == 0) 1790 panic("moea_release"); 1791 1792 mtx_lock(&moea_vsid_mutex); 1793 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1794 mask = 1 << (idx % VSID_NBPW); 1795 idx /= VSID_NBPW; 1796 moea_vsid_bitmap[idx] &= ~mask; 1797 mtx_unlock(&moea_vsid_mutex); 1798 } 1799 1800 /* 1801 * Remove the given range of addresses from the specified map. 1802 */ 1803 void 1804 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1805 { 1806 struct pvo_entry *pvo, *tpvo, key; 1807 1808 rw_wlock(&pvh_global_lock); 1809 PMAP_LOCK(pm); 1810 key.pvo_vaddr = sva; 1811 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1812 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1813 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1814 moea_pvo_remove(pvo, -1); 1815 } 1816 PMAP_UNLOCK(pm); 1817 rw_wunlock(&pvh_global_lock); 1818 } 1819 1820 /* 1821 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1822 * will reflect changes in pte's back to the vm_page. 1823 */ 1824 void 1825 moea_remove_all(mmu_t mmu, vm_page_t m) 1826 { 1827 struct pvo_head *pvo_head; 1828 struct pvo_entry *pvo, *next_pvo; 1829 pmap_t pmap; 1830 1831 rw_wlock(&pvh_global_lock); 1832 pvo_head = vm_page_to_pvoh(m); 1833 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1834 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1835 1836 pmap = pvo->pvo_pmap; 1837 PMAP_LOCK(pmap); 1838 moea_pvo_remove(pvo, -1); 1839 PMAP_UNLOCK(pmap); 1840 } 1841 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1842 moea_attr_clear(m, PTE_CHG); 1843 vm_page_dirty(m); 1844 } 1845 vm_page_aflag_clear(m, PGA_WRITEABLE); 1846 rw_wunlock(&pvh_global_lock); 1847 } 1848 1849 /* 1850 * Allocate a physical page of memory directly from the phys_avail map. 1851 * Can only be called from moea_bootstrap before avail start and end are 1852 * calculated. 1853 */ 1854 static vm_offset_t 1855 moea_bootstrap_alloc(vm_size_t size, u_int align) 1856 { 1857 vm_offset_t s, e; 1858 int i, j; 1859 1860 size = round_page(size); 1861 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1862 if (align != 0) 1863 s = (phys_avail[i] + align - 1) & ~(align - 1); 1864 else 1865 s = phys_avail[i]; 1866 e = s + size; 1867 1868 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1869 continue; 1870 1871 if (s == phys_avail[i]) { 1872 phys_avail[i] += size; 1873 } else if (e == phys_avail[i + 1]) { 1874 phys_avail[i + 1] -= size; 1875 } else { 1876 for (j = phys_avail_count * 2; j > i; j -= 2) { 1877 phys_avail[j] = phys_avail[j - 2]; 1878 phys_avail[j + 1] = phys_avail[j - 1]; 1879 } 1880 1881 phys_avail[i + 3] = phys_avail[i + 1]; 1882 phys_avail[i + 1] = s; 1883 phys_avail[i + 2] = e; 1884 phys_avail_count++; 1885 } 1886 1887 return (s); 1888 } 1889 panic("moea_bootstrap_alloc: could not allocate memory"); 1890 } 1891 1892 static void 1893 moea_syncicache(vm_offset_t pa, vm_size_t len) 1894 { 1895 __syncicache((void *)pa, len); 1896 } 1897 1898 static int 1899 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1900 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1901 { 1902 struct pvo_entry *pvo; 1903 u_int sr; 1904 int first; 1905 u_int ptegidx; 1906 int i; 1907 int bootstrap; 1908 1909 moea_pvo_enter_calls++; 1910 first = 0; 1911 bootstrap = 0; 1912 1913 /* 1914 * Compute the PTE Group index. 1915 */ 1916 va &= ~ADDR_POFF; 1917 sr = va_to_sr(pm->pm_sr, va); 1918 ptegidx = va_to_pteg(sr, va); 1919 1920 /* 1921 * Remove any existing mapping for this page. Reuse the pvo entry if 1922 * there is a mapping. 1923 */ 1924 mtx_lock(&moea_table_mutex); 1925 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1926 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1927 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1928 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1929 (pte_lo & PTE_PP)) { 1930 /* 1931 * The PTE is not changing. Instead, this may 1932 * be a request to change the mapping's wired 1933 * attribute. 1934 */ 1935 mtx_unlock(&moea_table_mutex); 1936 if ((flags & PVO_WIRED) != 0 && 1937 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1938 pvo->pvo_vaddr |= PVO_WIRED; 1939 pm->pm_stats.wired_count++; 1940 } else if ((flags & PVO_WIRED) == 0 && 1941 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1942 pvo->pvo_vaddr &= ~PVO_WIRED; 1943 pm->pm_stats.wired_count--; 1944 } 1945 return (0); 1946 } 1947 moea_pvo_remove(pvo, -1); 1948 break; 1949 } 1950 } 1951 1952 /* 1953 * If we aren't overwriting a mapping, try to allocate. 1954 */ 1955 if (moea_initialized) { 1956 pvo = uma_zalloc(zone, M_NOWAIT); 1957 } else { 1958 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1959 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1960 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1961 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1962 } 1963 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1964 moea_bpvo_pool_index++; 1965 bootstrap = 1; 1966 } 1967 1968 if (pvo == NULL) { 1969 mtx_unlock(&moea_table_mutex); 1970 return (ENOMEM); 1971 } 1972 1973 moea_pvo_entries++; 1974 pvo->pvo_vaddr = va; 1975 pvo->pvo_pmap = pm; 1976 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1977 pvo->pvo_vaddr &= ~ADDR_POFF; 1978 if (flags & PVO_WIRED) 1979 pvo->pvo_vaddr |= PVO_WIRED; 1980 if (pvo_head != &moea_pvo_kunmanaged) 1981 pvo->pvo_vaddr |= PVO_MANAGED; 1982 if (bootstrap) 1983 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1984 1985 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1986 1987 /* 1988 * Add to pmap list 1989 */ 1990 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1991 1992 /* 1993 * Remember if the list was empty and therefore will be the first 1994 * item. 1995 */ 1996 if (LIST_FIRST(pvo_head) == NULL) 1997 first = 1; 1998 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1999 2000 if (pvo->pvo_vaddr & PVO_WIRED) 2001 pm->pm_stats.wired_count++; 2002 pm->pm_stats.resident_count++; 2003 2004 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2005 KASSERT(i < 8, ("Invalid PTE index")); 2006 if (i >= 0) { 2007 PVO_PTEGIDX_SET(pvo, i); 2008 } else { 2009 panic("moea_pvo_enter: overflow"); 2010 moea_pte_overflow++; 2011 } 2012 mtx_unlock(&moea_table_mutex); 2013 2014 return (first ? ENOENT : 0); 2015 } 2016 2017 static void 2018 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2019 { 2020 struct pte *pt; 2021 2022 /* 2023 * If there is an active pte entry, we need to deactivate it (and 2024 * save the ref & cfg bits). 2025 */ 2026 pt = moea_pvo_to_pte(pvo, pteidx); 2027 if (pt != NULL) { 2028 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2029 mtx_unlock(&moea_table_mutex); 2030 PVO_PTEGIDX_CLR(pvo); 2031 } else { 2032 moea_pte_overflow--; 2033 } 2034 2035 /* 2036 * Update our statistics. 2037 */ 2038 pvo->pvo_pmap->pm_stats.resident_count--; 2039 if (pvo->pvo_vaddr & PVO_WIRED) 2040 pvo->pvo_pmap->pm_stats.wired_count--; 2041 2042 /* 2043 * Save the REF/CHG bits into their cache if the page is managed. 2044 */ 2045 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2046 struct vm_page *pg; 2047 2048 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2049 if (pg != NULL) { 2050 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2051 (PTE_REF | PTE_CHG)); 2052 } 2053 } 2054 2055 /* 2056 * Remove this PVO from the PV and pmap lists. 2057 */ 2058 LIST_REMOVE(pvo, pvo_vlink); 2059 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2060 2061 /* 2062 * Remove this from the overflow list and return it to the pool 2063 * if we aren't going to reuse it. 2064 */ 2065 LIST_REMOVE(pvo, pvo_olink); 2066 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2067 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2068 moea_upvo_zone, pvo); 2069 moea_pvo_entries--; 2070 moea_pvo_remove_calls++; 2071 } 2072 2073 static __inline int 2074 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2075 { 2076 int pteidx; 2077 2078 /* 2079 * We can find the actual pte entry without searching by grabbing 2080 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2081 * noticing the HID bit. 2082 */ 2083 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2084 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2085 pteidx ^= moea_pteg_mask * 8; 2086 2087 return (pteidx); 2088 } 2089 2090 static struct pvo_entry * 2091 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2092 { 2093 struct pvo_entry *pvo; 2094 int ptegidx; 2095 u_int sr; 2096 2097 va &= ~ADDR_POFF; 2098 sr = va_to_sr(pm->pm_sr, va); 2099 ptegidx = va_to_pteg(sr, va); 2100 2101 mtx_lock(&moea_table_mutex); 2102 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2103 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2104 if (pteidx_p) 2105 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2106 break; 2107 } 2108 } 2109 mtx_unlock(&moea_table_mutex); 2110 2111 return (pvo); 2112 } 2113 2114 static struct pte * 2115 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2116 { 2117 struct pte *pt; 2118 2119 /* 2120 * If we haven't been supplied the ptegidx, calculate it. 2121 */ 2122 if (pteidx == -1) { 2123 int ptegidx; 2124 u_int sr; 2125 2126 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2127 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2128 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2129 } 2130 2131 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2132 mtx_lock(&moea_table_mutex); 2133 2134 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2135 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2136 "valid pte index", pvo); 2137 } 2138 2139 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2140 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2141 "pvo but no valid pte", pvo); 2142 } 2143 2144 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2145 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2146 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2147 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2148 } 2149 2150 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2151 != 0) { 2152 panic("moea_pvo_to_pte: pvo %p pte does not match " 2153 "pte %p in moea_pteg_table", pvo, pt); 2154 } 2155 2156 mtx_assert(&moea_table_mutex, MA_OWNED); 2157 return (pt); 2158 } 2159 2160 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2161 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2162 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2163 } 2164 2165 mtx_unlock(&moea_table_mutex); 2166 return (NULL); 2167 } 2168 2169 /* 2170 * XXX: THIS STUFF SHOULD BE IN pte.c? 2171 */ 2172 int 2173 moea_pte_spill(vm_offset_t addr) 2174 { 2175 struct pvo_entry *source_pvo, *victim_pvo; 2176 struct pvo_entry *pvo; 2177 int ptegidx, i, j; 2178 u_int sr; 2179 struct pteg *pteg; 2180 struct pte *pt; 2181 2182 moea_pte_spills++; 2183 2184 sr = mfsrin(addr); 2185 ptegidx = va_to_pteg(sr, addr); 2186 2187 /* 2188 * Have to substitute some entry. Use the primary hash for this. 2189 * Use low bits of timebase as random generator. 2190 */ 2191 pteg = &moea_pteg_table[ptegidx]; 2192 mtx_lock(&moea_table_mutex); 2193 __asm __volatile("mftb %0" : "=r"(i)); 2194 i &= 7; 2195 pt = &pteg->pt[i]; 2196 2197 source_pvo = NULL; 2198 victim_pvo = NULL; 2199 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2200 /* 2201 * We need to find a pvo entry for this address. 2202 */ 2203 if (source_pvo == NULL && 2204 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2205 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2206 /* 2207 * Now found an entry to be spilled into the pteg. 2208 * The PTE is now valid, so we know it's active. 2209 */ 2210 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2211 2212 if (j >= 0) { 2213 PVO_PTEGIDX_SET(pvo, j); 2214 moea_pte_overflow--; 2215 mtx_unlock(&moea_table_mutex); 2216 return (1); 2217 } 2218 2219 source_pvo = pvo; 2220 2221 if (victim_pvo != NULL) 2222 break; 2223 } 2224 2225 /* 2226 * We also need the pvo entry of the victim we are replacing 2227 * so save the R & C bits of the PTE. 2228 */ 2229 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2230 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2231 victim_pvo = pvo; 2232 if (source_pvo != NULL) 2233 break; 2234 } 2235 } 2236 2237 if (source_pvo == NULL) { 2238 mtx_unlock(&moea_table_mutex); 2239 return (0); 2240 } 2241 2242 if (victim_pvo == NULL) { 2243 if ((pt->pte_hi & PTE_HID) == 0) 2244 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2245 "entry", pt); 2246 2247 /* 2248 * If this is a secondary PTE, we need to search it's primary 2249 * pvo bucket for the matching PVO. 2250 */ 2251 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2252 pvo_olink) { 2253 /* 2254 * We also need the pvo entry of the victim we are 2255 * replacing so save the R & C bits of the PTE. 2256 */ 2257 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2258 victim_pvo = pvo; 2259 break; 2260 } 2261 } 2262 2263 if (victim_pvo == NULL) 2264 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2265 "entry", pt); 2266 } 2267 2268 /* 2269 * We are invalidating the TLB entry for the EA we are replacing even 2270 * though it's valid. If we don't, we lose any ref/chg bit changes 2271 * contained in the TLB entry. 2272 */ 2273 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2274 2275 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2276 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2277 2278 PVO_PTEGIDX_CLR(victim_pvo); 2279 PVO_PTEGIDX_SET(source_pvo, i); 2280 moea_pte_replacements++; 2281 2282 mtx_unlock(&moea_table_mutex); 2283 return (1); 2284 } 2285 2286 static __inline struct pvo_entry * 2287 moea_pte_spillable_ident(u_int ptegidx) 2288 { 2289 struct pte *pt; 2290 struct pvo_entry *pvo_walk, *pvo = NULL; 2291 2292 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2293 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2294 continue; 2295 2296 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2297 continue; 2298 2299 pt = moea_pvo_to_pte(pvo_walk, -1); 2300 2301 if (pt == NULL) 2302 continue; 2303 2304 pvo = pvo_walk; 2305 2306 mtx_unlock(&moea_table_mutex); 2307 if (!(pt->pte_lo & PTE_REF)) 2308 return (pvo_walk); 2309 } 2310 2311 return (pvo); 2312 } 2313 2314 static int 2315 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2316 { 2317 struct pte *pt; 2318 struct pvo_entry *victim_pvo; 2319 int i; 2320 int victim_idx; 2321 u_int pteg_bkpidx = ptegidx; 2322 2323 mtx_assert(&moea_table_mutex, MA_OWNED); 2324 2325 /* 2326 * First try primary hash. 2327 */ 2328 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2329 if ((pt->pte_hi & PTE_VALID) == 0) { 2330 pvo_pt->pte_hi &= ~PTE_HID; 2331 moea_pte_set(pt, pvo_pt); 2332 return (i); 2333 } 2334 } 2335 2336 /* 2337 * Now try secondary hash. 2338 */ 2339 ptegidx ^= moea_pteg_mask; 2340 2341 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2342 if ((pt->pte_hi & PTE_VALID) == 0) { 2343 pvo_pt->pte_hi |= PTE_HID; 2344 moea_pte_set(pt, pvo_pt); 2345 return (i); 2346 } 2347 } 2348 2349 /* Try again, but this time try to force a PTE out. */ 2350 ptegidx = pteg_bkpidx; 2351 2352 victim_pvo = moea_pte_spillable_ident(ptegidx); 2353 if (victim_pvo == NULL) { 2354 ptegidx ^= moea_pteg_mask; 2355 victim_pvo = moea_pte_spillable_ident(ptegidx); 2356 } 2357 2358 if (victim_pvo == NULL) { 2359 panic("moea_pte_insert: overflow"); 2360 return (-1); 2361 } 2362 2363 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2364 2365 if (pteg_bkpidx == ptegidx) 2366 pvo_pt->pte_hi &= ~PTE_HID; 2367 else 2368 pvo_pt->pte_hi |= PTE_HID; 2369 2370 /* 2371 * Synchronize the sacrifice PTE with its PVO, then mark both 2372 * invalid. The PVO will be reused when/if the VM system comes 2373 * here after a fault. 2374 */ 2375 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2376 2377 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2378 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2379 2380 /* 2381 * Set the new PTE. 2382 */ 2383 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2384 PVO_PTEGIDX_CLR(victim_pvo); 2385 moea_pte_overflow++; 2386 moea_pte_set(pt, pvo_pt); 2387 2388 return (victim_idx & 7); 2389 } 2390 2391 static boolean_t 2392 moea_query_bit(vm_page_t m, int ptebit) 2393 { 2394 struct pvo_entry *pvo; 2395 struct pte *pt; 2396 2397 rw_assert(&pvh_global_lock, RA_WLOCKED); 2398 if (moea_attr_fetch(m) & ptebit) 2399 return (TRUE); 2400 2401 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2402 2403 /* 2404 * See if we saved the bit off. If so, cache it and return 2405 * success. 2406 */ 2407 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2408 moea_attr_save(m, ptebit); 2409 return (TRUE); 2410 } 2411 } 2412 2413 /* 2414 * No luck, now go through the hard part of looking at the PTEs 2415 * themselves. Sync so that any pending REF/CHG bits are flushed to 2416 * the PTEs. 2417 */ 2418 powerpc_sync(); 2419 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2420 2421 /* 2422 * See if this pvo has a valid PTE. if so, fetch the 2423 * REF/CHG bits from the valid PTE. If the appropriate 2424 * ptebit is set, cache it and return success. 2425 */ 2426 pt = moea_pvo_to_pte(pvo, -1); 2427 if (pt != NULL) { 2428 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2429 mtx_unlock(&moea_table_mutex); 2430 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2431 moea_attr_save(m, ptebit); 2432 return (TRUE); 2433 } 2434 } 2435 } 2436 2437 return (FALSE); 2438 } 2439 2440 static u_int 2441 moea_clear_bit(vm_page_t m, int ptebit) 2442 { 2443 u_int count; 2444 struct pvo_entry *pvo; 2445 struct pte *pt; 2446 2447 rw_assert(&pvh_global_lock, RA_WLOCKED); 2448 2449 /* 2450 * Clear the cached value. 2451 */ 2452 moea_attr_clear(m, ptebit); 2453 2454 /* 2455 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2456 * we can reset the right ones). note that since the pvo entries and 2457 * list heads are accessed via BAT0 and are never placed in the page 2458 * table, we don't have to worry about further accesses setting the 2459 * REF/CHG bits. 2460 */ 2461 powerpc_sync(); 2462 2463 /* 2464 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2465 * valid pte clear the ptebit from the valid pte. 2466 */ 2467 count = 0; 2468 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2469 pt = moea_pvo_to_pte(pvo, -1); 2470 if (pt != NULL) { 2471 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2472 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2473 count++; 2474 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2475 } 2476 mtx_unlock(&moea_table_mutex); 2477 } 2478 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2479 } 2480 2481 return (count); 2482 } 2483 2484 /* 2485 * Return true if the physical range is encompassed by the battable[idx] 2486 */ 2487 static int 2488 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2489 { 2490 u_int prot; 2491 u_int32_t start; 2492 u_int32_t end; 2493 u_int32_t bat_ble; 2494 2495 /* 2496 * Return immediately if not a valid mapping 2497 */ 2498 if (!(battable[idx].batu & BAT_Vs)) 2499 return (EINVAL); 2500 2501 /* 2502 * The BAT entry must be cache-inhibited, guarded, and r/w 2503 * so it can function as an i/o page 2504 */ 2505 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2506 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2507 return (EPERM); 2508 2509 /* 2510 * The address should be within the BAT range. Assume that the 2511 * start address in the BAT has the correct alignment (thus 2512 * not requiring masking) 2513 */ 2514 start = battable[idx].batl & BAT_PBS; 2515 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2516 end = start | (bat_ble << 15) | 0x7fff; 2517 2518 if ((pa < start) || ((pa + size) > end)) 2519 return (ERANGE); 2520 2521 return (0); 2522 } 2523 2524 boolean_t 2525 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2526 { 2527 int i; 2528 2529 /* 2530 * This currently does not work for entries that 2531 * overlap 256M BAT segments. 2532 */ 2533 2534 for(i = 0; i < 16; i++) 2535 if (moea_bat_mapped(i, pa, size) == 0) 2536 return (0); 2537 2538 return (EFAULT); 2539 } 2540 2541 /* 2542 * Map a set of physical memory pages into the kernel virtual 2543 * address space. Return a pointer to where it is mapped. This 2544 * routine is intended to be used for mapping device memory, 2545 * NOT real memory. 2546 */ 2547 void * 2548 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2549 { 2550 2551 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2552 } 2553 2554 void * 2555 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2556 { 2557 vm_offset_t va, tmpva, ppa, offset; 2558 int i; 2559 2560 ppa = trunc_page(pa); 2561 offset = pa & PAGE_MASK; 2562 size = roundup(offset + size, PAGE_SIZE); 2563 2564 /* 2565 * If the physical address lies within a valid BAT table entry, 2566 * return the 1:1 mapping. This currently doesn't work 2567 * for regions that overlap 256M BAT segments. 2568 */ 2569 for (i = 0; i < 16; i++) { 2570 if (moea_bat_mapped(i, pa, size) == 0) 2571 return ((void *) pa); 2572 } 2573 2574 va = kva_alloc(size); 2575 if (!va) 2576 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2577 2578 for (tmpva = va; size > 0;) { 2579 moea_kenter_attr(mmu, tmpva, ppa, ma); 2580 tlbie(tmpva); 2581 size -= PAGE_SIZE; 2582 tmpva += PAGE_SIZE; 2583 ppa += PAGE_SIZE; 2584 } 2585 2586 return ((void *)(va + offset)); 2587 } 2588 2589 void 2590 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2591 { 2592 vm_offset_t base, offset; 2593 2594 /* 2595 * If this is outside kernel virtual space, then it's a 2596 * battable entry and doesn't require unmapping 2597 */ 2598 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2599 base = trunc_page(va); 2600 offset = va & PAGE_MASK; 2601 size = roundup(offset + size, PAGE_SIZE); 2602 kva_free(base, size); 2603 } 2604 } 2605 2606 static void 2607 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2608 { 2609 struct pvo_entry *pvo; 2610 vm_offset_t lim; 2611 vm_paddr_t pa; 2612 vm_size_t len; 2613 2614 PMAP_LOCK(pm); 2615 while (sz > 0) { 2616 lim = round_page(va); 2617 len = MIN(lim - va, sz); 2618 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2619 if (pvo != NULL) { 2620 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2621 (va & ADDR_POFF); 2622 moea_syncicache(pa, len); 2623 } 2624 va += len; 2625 sz -= len; 2626 } 2627 PMAP_UNLOCK(pm); 2628 } 2629 2630 void 2631 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2632 { 2633 2634 *va = (void *)pa; 2635 } 2636 2637 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2638 2639 void 2640 moea_scan_init(mmu_t mmu) 2641 { 2642 struct pvo_entry *pvo; 2643 vm_offset_t va; 2644 int i; 2645 2646 if (!do_minidump) { 2647 /* Initialize phys. segments for dumpsys(). */ 2648 memset(&dump_map, 0, sizeof(dump_map)); 2649 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2650 for (i = 0; i < pregions_sz; i++) { 2651 dump_map[i].pa_start = pregions[i].mr_start; 2652 dump_map[i].pa_size = pregions[i].mr_size; 2653 } 2654 return; 2655 } 2656 2657 /* Virtual segments for minidumps: */ 2658 memset(&dump_map, 0, sizeof(dump_map)); 2659 2660 /* 1st: kernel .data and .bss. */ 2661 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2662 dump_map[0].pa_size = 2663 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2664 2665 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2666 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2667 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2668 2669 /* 3rd: kernel VM. */ 2670 va = dump_map[1].pa_start + dump_map[1].pa_size; 2671 /* Find start of next chunk (from va). */ 2672 while (va < virtual_end) { 2673 /* Don't dump the buffer cache. */ 2674 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2675 va = kmi.buffer_eva; 2676 continue; 2677 } 2678 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2679 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2680 break; 2681 va += PAGE_SIZE; 2682 } 2683 if (va < virtual_end) { 2684 dump_map[2].pa_start = va; 2685 va += PAGE_SIZE; 2686 /* Find last page in chunk. */ 2687 while (va < virtual_end) { 2688 /* Don't run into the buffer cache. */ 2689 if (va == kmi.buffer_sva) 2690 break; 2691 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2692 NULL); 2693 if (pvo == NULL || 2694 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2695 break; 2696 va += PAGE_SIZE; 2697 } 2698 dump_map[2].pa_size = va - dump_map[2].pa_start; 2699 } 2700 } 2701