1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * Since the information managed by this module is also stored by the 100 * logical address mapping module, this module may throw away valid virtual 101 * to physical mappings at almost any time. However, invalidations of 102 * mappings must be done as requested. 103 * 104 * In order to cope with hardware architectures which make virtual to 105 * physical map invalidates expensive, this module may delay invalidate 106 * reduced protection operations until such time as they are actually 107 * necessary. This module is given full information as to which processors 108 * are currently using which maps, and to when physical maps must be made 109 * correct. 110 */ 111 112 #include "opt_kstack_pages.h" 113 114 #include <sys/param.h> 115 #include <sys/kernel.h> 116 #include <sys/queue.h> 117 #include <sys/cpuset.h> 118 #include <sys/ktr.h> 119 #include <sys/lock.h> 120 #include <sys/msgbuf.h> 121 #include <sys/mutex.h> 122 #include <sys/proc.h> 123 #include <sys/rwlock.h> 124 #include <sys/sched.h> 125 #include <sys/sysctl.h> 126 #include <sys/systm.h> 127 #include <sys/vmmeter.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #include <vm/vm.h> 132 #include <vm/vm_param.h> 133 #include <vm/vm_kern.h> 134 #include <vm/vm_page.h> 135 #include <vm/vm_map.h> 136 #include <vm/vm_object.h> 137 #include <vm/vm_extern.h> 138 #include <vm/vm_pageout.h> 139 #include <vm/uma.h> 140 141 #include <machine/cpu.h> 142 #include <machine/platform.h> 143 #include <machine/bat.h> 144 #include <machine/frame.h> 145 #include <machine/md_var.h> 146 #include <machine/psl.h> 147 #include <machine/pte.h> 148 #include <machine/smp.h> 149 #include <machine/sr.h> 150 #include <machine/mmuvar.h> 151 #include <machine/trap_aim.h> 152 153 #include "mmu_if.h" 154 155 #define MOEA_DEBUG 156 157 #define TODO panic("%s: not implemented", __func__); 158 159 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 160 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 161 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 162 163 struct ofw_map { 164 vm_offset_t om_va; 165 vm_size_t om_len; 166 vm_offset_t om_pa; 167 u_int om_mode; 168 }; 169 170 extern unsigned char _etext[]; 171 extern unsigned char _end[]; 172 173 extern int dumpsys_minidump; 174 175 /* 176 * Map of physical memory regions. 177 */ 178 static struct mem_region *regions; 179 static struct mem_region *pregions; 180 static u_int phys_avail_count; 181 static int regions_sz, pregions_sz; 182 static struct ofw_map *translations; 183 184 /* 185 * Lock for the pteg and pvo tables. 186 */ 187 struct mtx moea_table_mutex; 188 struct mtx moea_vsid_mutex; 189 190 /* tlbie instruction synchronization */ 191 static struct mtx tlbie_mtx; 192 193 /* 194 * PTEG data. 195 */ 196 static struct pteg *moea_pteg_table; 197 u_int moea_pteg_count; 198 u_int moea_pteg_mask; 199 200 /* 201 * PVO data. 202 */ 203 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 204 struct pvo_head moea_pvo_kunmanaged = 205 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 206 207 static struct rwlock_padalign pvh_global_lock; 208 209 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 210 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 211 212 #define BPVO_POOL_SIZE 32768 213 static struct pvo_entry *moea_bpvo_pool; 214 static int moea_bpvo_pool_index = 0; 215 216 #define VSID_NBPW (sizeof(u_int32_t) * 8) 217 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 218 219 static boolean_t moea_initialized = FALSE; 220 221 /* 222 * Statistics. 223 */ 224 u_int moea_pte_valid = 0; 225 u_int moea_pte_overflow = 0; 226 u_int moea_pte_replacements = 0; 227 u_int moea_pvo_entries = 0; 228 u_int moea_pvo_enter_calls = 0; 229 u_int moea_pvo_remove_calls = 0; 230 u_int moea_pte_spills = 0; 231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 232 0, ""); 233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 234 &moea_pte_overflow, 0, ""); 235 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 236 &moea_pte_replacements, 0, ""); 237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 238 0, ""); 239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 240 &moea_pvo_enter_calls, 0, ""); 241 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 242 &moea_pvo_remove_calls, 0, ""); 243 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 244 &moea_pte_spills, 0, ""); 245 246 /* 247 * Allocate physical memory for use in moea_bootstrap. 248 */ 249 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 250 251 /* 252 * PTE calls. 253 */ 254 static int moea_pte_insert(u_int, struct pte *); 255 256 /* 257 * PVO calls. 258 */ 259 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 260 vm_offset_t, vm_offset_t, u_int, int); 261 static void moea_pvo_remove(struct pvo_entry *, int); 262 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 263 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 264 265 /* 266 * Utility routines. 267 */ 268 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 269 vm_prot_t, boolean_t); 270 static void moea_syncicache(vm_offset_t, vm_size_t); 271 static boolean_t moea_query_bit(vm_page_t, int); 272 static u_int moea_clear_bit(vm_page_t, int); 273 static void moea_kremove(mmu_t, vm_offset_t); 274 int moea_pte_spill(vm_offset_t); 275 276 /* 277 * Kernel MMU interface 278 */ 279 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 280 void moea_clear_modify(mmu_t, vm_page_t); 281 void moea_clear_reference(mmu_t, vm_page_t); 282 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 283 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 284 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 285 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 286 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 287 vm_prot_t); 288 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 289 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 290 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 291 void moea_init(mmu_t); 292 boolean_t moea_is_modified(mmu_t, vm_page_t); 293 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 294 boolean_t moea_is_referenced(mmu_t, vm_page_t); 295 int moea_ts_referenced(mmu_t, vm_page_t); 296 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 297 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 298 int moea_page_wired_mappings(mmu_t, vm_page_t); 299 void moea_pinit(mmu_t, pmap_t); 300 void moea_pinit0(mmu_t, pmap_t); 301 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 302 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 303 void moea_qremove(mmu_t, vm_offset_t, int); 304 void moea_release(mmu_t, pmap_t); 305 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 306 void moea_remove_all(mmu_t, vm_page_t); 307 void moea_remove_write(mmu_t, vm_page_t); 308 void moea_zero_page(mmu_t, vm_page_t); 309 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 310 void moea_zero_page_idle(mmu_t, vm_page_t); 311 void moea_activate(mmu_t, struct thread *); 312 void moea_deactivate(mmu_t, struct thread *); 313 void moea_cpu_bootstrap(mmu_t, int); 314 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 315 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 316 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 317 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 318 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 319 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 320 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 321 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 322 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 323 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 324 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 325 vm_size_t *sz); 326 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev); 327 328 static mmu_method_t moea_methods[] = { 329 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 330 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 331 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 332 MMUMETHOD(mmu_copy_page, moea_copy_page), 333 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 334 MMUMETHOD(mmu_enter, moea_enter), 335 MMUMETHOD(mmu_enter_object, moea_enter_object), 336 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 337 MMUMETHOD(mmu_extract, moea_extract), 338 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 339 MMUMETHOD(mmu_init, moea_init), 340 MMUMETHOD(mmu_is_modified, moea_is_modified), 341 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 342 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 343 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 344 MMUMETHOD(mmu_map, moea_map), 345 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 346 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 347 MMUMETHOD(mmu_pinit, moea_pinit), 348 MMUMETHOD(mmu_pinit0, moea_pinit0), 349 MMUMETHOD(mmu_protect, moea_protect), 350 MMUMETHOD(mmu_qenter, moea_qenter), 351 MMUMETHOD(mmu_qremove, moea_qremove), 352 MMUMETHOD(mmu_release, moea_release), 353 MMUMETHOD(mmu_remove, moea_remove), 354 MMUMETHOD(mmu_remove_all, moea_remove_all), 355 MMUMETHOD(mmu_remove_write, moea_remove_write), 356 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 357 MMUMETHOD(mmu_zero_page, moea_zero_page), 358 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 359 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 360 MMUMETHOD(mmu_activate, moea_activate), 361 MMUMETHOD(mmu_deactivate, moea_deactivate), 362 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 363 364 /* Internal interfaces */ 365 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 366 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 367 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 368 MMUMETHOD(mmu_mapdev, moea_mapdev), 369 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 370 MMUMETHOD(mmu_kextract, moea_kextract), 371 MMUMETHOD(mmu_kenter, moea_kenter), 372 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 373 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 374 MMUMETHOD(mmu_scan_md, moea_scan_md), 375 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 376 377 { 0, 0 } 378 }; 379 380 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 381 382 static __inline uint32_t 383 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 384 { 385 uint32_t pte_lo; 386 int i; 387 388 if (ma != VM_MEMATTR_DEFAULT) { 389 switch (ma) { 390 case VM_MEMATTR_UNCACHEABLE: 391 return (PTE_I | PTE_G); 392 case VM_MEMATTR_WRITE_COMBINING: 393 case VM_MEMATTR_WRITE_BACK: 394 case VM_MEMATTR_PREFETCHABLE: 395 return (PTE_I); 396 case VM_MEMATTR_WRITE_THROUGH: 397 return (PTE_W | PTE_M); 398 } 399 } 400 401 /* 402 * Assume the page is cache inhibited and access is guarded unless 403 * it's in our available memory array. 404 */ 405 pte_lo = PTE_I | PTE_G; 406 for (i = 0; i < pregions_sz; i++) { 407 if ((pa >= pregions[i].mr_start) && 408 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 409 pte_lo = PTE_M; 410 break; 411 } 412 } 413 414 return pte_lo; 415 } 416 417 static void 418 tlbie(vm_offset_t va) 419 { 420 421 mtx_lock_spin(&tlbie_mtx); 422 __asm __volatile("ptesync"); 423 __asm __volatile("tlbie %0" :: "r"(va)); 424 __asm __volatile("eieio; tlbsync; ptesync"); 425 mtx_unlock_spin(&tlbie_mtx); 426 } 427 428 static void 429 tlbia(void) 430 { 431 vm_offset_t va; 432 433 for (va = 0; va < 0x00040000; va += 0x00001000) { 434 __asm __volatile("tlbie %0" :: "r"(va)); 435 powerpc_sync(); 436 } 437 __asm __volatile("tlbsync"); 438 powerpc_sync(); 439 } 440 441 static __inline int 442 va_to_sr(u_int *sr, vm_offset_t va) 443 { 444 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 445 } 446 447 static __inline u_int 448 va_to_pteg(u_int sr, vm_offset_t addr) 449 { 450 u_int hash; 451 452 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 453 ADDR_PIDX_SHFT); 454 return (hash & moea_pteg_mask); 455 } 456 457 static __inline struct pvo_head * 458 vm_page_to_pvoh(vm_page_t m) 459 { 460 461 return (&m->md.mdpg_pvoh); 462 } 463 464 static __inline void 465 moea_attr_clear(vm_page_t m, int ptebit) 466 { 467 468 rw_assert(&pvh_global_lock, RA_WLOCKED); 469 m->md.mdpg_attrs &= ~ptebit; 470 } 471 472 static __inline int 473 moea_attr_fetch(vm_page_t m) 474 { 475 476 return (m->md.mdpg_attrs); 477 } 478 479 static __inline void 480 moea_attr_save(vm_page_t m, int ptebit) 481 { 482 483 rw_assert(&pvh_global_lock, RA_WLOCKED); 484 m->md.mdpg_attrs |= ptebit; 485 } 486 487 static __inline int 488 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 489 { 490 if (pt->pte_hi == pvo_pt->pte_hi) 491 return (1); 492 493 return (0); 494 } 495 496 static __inline int 497 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 498 { 499 return (pt->pte_hi & ~PTE_VALID) == 500 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 501 ((va >> ADDR_API_SHFT) & PTE_API) | which); 502 } 503 504 static __inline void 505 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 506 { 507 508 mtx_assert(&moea_table_mutex, MA_OWNED); 509 510 /* 511 * Construct a PTE. Default to IMB initially. Valid bit only gets 512 * set when the real pte is set in memory. 513 * 514 * Note: Don't set the valid bit for correct operation of tlb update. 515 */ 516 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 517 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 518 pt->pte_lo = pte_lo; 519 } 520 521 static __inline void 522 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 523 { 524 525 mtx_assert(&moea_table_mutex, MA_OWNED); 526 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 527 } 528 529 static __inline void 530 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 531 { 532 533 mtx_assert(&moea_table_mutex, MA_OWNED); 534 535 /* 536 * As shown in Section 7.6.3.2.3 537 */ 538 pt->pte_lo &= ~ptebit; 539 tlbie(va); 540 } 541 542 static __inline void 543 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 544 { 545 546 mtx_assert(&moea_table_mutex, MA_OWNED); 547 pvo_pt->pte_hi |= PTE_VALID; 548 549 /* 550 * Update the PTE as defined in section 7.6.3.1. 551 * Note that the REF/CHG bits are from pvo_pt and thus should have 552 * been saved so this routine can restore them (if desired). 553 */ 554 pt->pte_lo = pvo_pt->pte_lo; 555 powerpc_sync(); 556 pt->pte_hi = pvo_pt->pte_hi; 557 powerpc_sync(); 558 moea_pte_valid++; 559 } 560 561 static __inline void 562 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 563 { 564 565 mtx_assert(&moea_table_mutex, MA_OWNED); 566 pvo_pt->pte_hi &= ~PTE_VALID; 567 568 /* 569 * Force the reg & chg bits back into the PTEs. 570 */ 571 powerpc_sync(); 572 573 /* 574 * Invalidate the pte. 575 */ 576 pt->pte_hi &= ~PTE_VALID; 577 578 tlbie(va); 579 580 /* 581 * Save the reg & chg bits. 582 */ 583 moea_pte_synch(pt, pvo_pt); 584 moea_pte_valid--; 585 } 586 587 static __inline void 588 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 589 { 590 591 /* 592 * Invalidate the PTE 593 */ 594 moea_pte_unset(pt, pvo_pt, va); 595 moea_pte_set(pt, pvo_pt); 596 } 597 598 /* 599 * Quick sort callout for comparing memory regions. 600 */ 601 static int om_cmp(const void *a, const void *b); 602 603 static int 604 om_cmp(const void *a, const void *b) 605 { 606 const struct ofw_map *mapa; 607 const struct ofw_map *mapb; 608 609 mapa = a; 610 mapb = b; 611 if (mapa->om_pa < mapb->om_pa) 612 return (-1); 613 else if (mapa->om_pa > mapb->om_pa) 614 return (1); 615 else 616 return (0); 617 } 618 619 void 620 moea_cpu_bootstrap(mmu_t mmup, int ap) 621 { 622 u_int sdr; 623 int i; 624 625 if (ap) { 626 powerpc_sync(); 627 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 628 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 629 isync(); 630 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 631 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 632 isync(); 633 } 634 635 #ifdef WII 636 /* 637 * Special case for the Wii: don't install the PCI BAT. 638 */ 639 if (strcmp(installed_platform(), "wii") != 0) { 640 #endif 641 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 642 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 643 #ifdef WII 644 } 645 #endif 646 isync(); 647 648 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 649 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 650 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 651 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 652 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 653 isync(); 654 655 for (i = 0; i < 16; i++) 656 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 657 powerpc_sync(); 658 659 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 660 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 661 isync(); 662 663 tlbia(); 664 } 665 666 void 667 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 668 { 669 ihandle_t mmui; 670 phandle_t chosen, mmu; 671 int sz; 672 int i, j; 673 vm_size_t size, physsz, hwphyssz; 674 vm_offset_t pa, va, off; 675 void *dpcpu; 676 register_t msr; 677 678 /* 679 * Set up BAT0 to map the lowest 256 MB area 680 */ 681 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 682 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 683 684 /* 685 * Map PCI memory space. 686 */ 687 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 689 690 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 692 693 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 694 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 695 696 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 697 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 698 699 /* 700 * Map obio devices. 701 */ 702 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 703 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 704 705 /* 706 * Use an IBAT and a DBAT to map the bottom segment of memory 707 * where we are. Turn off instruction relocation temporarily 708 * to prevent faults while reprogramming the IBAT. 709 */ 710 msr = mfmsr(); 711 mtmsr(msr & ~PSL_IR); 712 __asm (".balign 32; \n" 713 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 714 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 715 :: "r"(battable[0].batu), "r"(battable[0].batl)); 716 mtmsr(msr); 717 718 #ifdef WII 719 if (strcmp(installed_platform(), "wii") != 0) { 720 #endif 721 /* map pci space */ 722 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 723 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 724 #ifdef WII 725 } 726 #endif 727 isync(); 728 729 /* set global direct map flag */ 730 hw_direct_map = 1; 731 732 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 733 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 734 735 for (i = 0; i < pregions_sz; i++) { 736 vm_offset_t pa; 737 vm_offset_t end; 738 739 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 740 pregions[i].mr_start, 741 pregions[i].mr_start + pregions[i].mr_size, 742 pregions[i].mr_size); 743 /* 744 * Install entries into the BAT table to allow all 745 * of physmem to be convered by on-demand BAT entries. 746 * The loop will sometimes set the same battable element 747 * twice, but that's fine since they won't be used for 748 * a while yet. 749 */ 750 pa = pregions[i].mr_start & 0xf0000000; 751 end = pregions[i].mr_start + pregions[i].mr_size; 752 do { 753 u_int n = pa >> ADDR_SR_SHFT; 754 755 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 756 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 757 pa += SEGMENT_LENGTH; 758 } while (pa < end); 759 } 760 761 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 762 panic("moea_bootstrap: phys_avail too small"); 763 764 phys_avail_count = 0; 765 physsz = 0; 766 hwphyssz = 0; 767 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 768 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 769 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 770 regions[i].mr_start + regions[i].mr_size, 771 regions[i].mr_size); 772 if (hwphyssz != 0 && 773 (physsz + regions[i].mr_size) >= hwphyssz) { 774 if (physsz < hwphyssz) { 775 phys_avail[j] = regions[i].mr_start; 776 phys_avail[j + 1] = regions[i].mr_start + 777 hwphyssz - physsz; 778 physsz = hwphyssz; 779 phys_avail_count++; 780 } 781 break; 782 } 783 phys_avail[j] = regions[i].mr_start; 784 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 785 phys_avail_count++; 786 physsz += regions[i].mr_size; 787 } 788 789 /* Check for overlap with the kernel and exception vectors */ 790 for (j = 0; j < 2*phys_avail_count; j+=2) { 791 if (phys_avail[j] < EXC_LAST) 792 phys_avail[j] += EXC_LAST; 793 794 if (kernelstart >= phys_avail[j] && 795 kernelstart < phys_avail[j+1]) { 796 if (kernelend < phys_avail[j+1]) { 797 phys_avail[2*phys_avail_count] = 798 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 799 phys_avail[2*phys_avail_count + 1] = 800 phys_avail[j+1]; 801 phys_avail_count++; 802 } 803 804 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 805 } 806 807 if (kernelend >= phys_avail[j] && 808 kernelend < phys_avail[j+1]) { 809 if (kernelstart > phys_avail[j]) { 810 phys_avail[2*phys_avail_count] = phys_avail[j]; 811 phys_avail[2*phys_avail_count + 1] = 812 kernelstart & ~PAGE_MASK; 813 phys_avail_count++; 814 } 815 816 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 817 } 818 } 819 820 physmem = btoc(physsz); 821 822 /* 823 * Allocate PTEG table. 824 */ 825 #ifdef PTEGCOUNT 826 moea_pteg_count = PTEGCOUNT; 827 #else 828 moea_pteg_count = 0x1000; 829 830 while (moea_pteg_count < physmem) 831 moea_pteg_count <<= 1; 832 833 moea_pteg_count >>= 1; 834 #endif /* PTEGCOUNT */ 835 836 size = moea_pteg_count * sizeof(struct pteg); 837 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 838 size); 839 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 840 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 841 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 842 moea_pteg_mask = moea_pteg_count - 1; 843 844 /* 845 * Allocate pv/overflow lists. 846 */ 847 size = sizeof(struct pvo_head) * moea_pteg_count; 848 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 849 PAGE_SIZE); 850 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 851 for (i = 0; i < moea_pteg_count; i++) 852 LIST_INIT(&moea_pvo_table[i]); 853 854 /* 855 * Initialize the lock that synchronizes access to the pteg and pvo 856 * tables. 857 */ 858 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 859 MTX_RECURSE); 860 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 861 862 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 863 864 /* 865 * Initialise the unmanaged pvo pool. 866 */ 867 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 868 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 869 moea_bpvo_pool_index = 0; 870 871 /* 872 * Make sure kernel vsid is allocated as well as VSID 0. 873 */ 874 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 875 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 876 moea_vsid_bitmap[0] |= 1; 877 878 /* 879 * Initialize the kernel pmap (which is statically allocated). 880 */ 881 PMAP_LOCK_INIT(kernel_pmap); 882 for (i = 0; i < 16; i++) 883 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 884 CPU_FILL(&kernel_pmap->pm_active); 885 RB_INIT(&kernel_pmap->pmap_pvo); 886 887 /* 888 * Initialize the global pv list lock. 889 */ 890 rw_init(&pvh_global_lock, "pmap pv global"); 891 892 /* 893 * Set up the Open Firmware mappings 894 */ 895 chosen = OF_finddevice("/chosen"); 896 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 897 (mmu = OF_instance_to_package(mmui)) != -1 && 898 (sz = OF_getproplen(mmu, "translations")) != -1) { 899 translations = NULL; 900 for (i = 0; phys_avail[i] != 0; i += 2) { 901 if (phys_avail[i + 1] >= sz) { 902 translations = (struct ofw_map *)phys_avail[i]; 903 break; 904 } 905 } 906 if (translations == NULL) 907 panic("moea_bootstrap: no space to copy translations"); 908 bzero(translations, sz); 909 if (OF_getprop(mmu, "translations", translations, sz) == -1) 910 panic("moea_bootstrap: can't get ofw translations"); 911 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 912 sz /= sizeof(*translations); 913 qsort(translations, sz, sizeof (*translations), om_cmp); 914 for (i = 0; i < sz; i++) { 915 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 916 translations[i].om_pa, translations[i].om_va, 917 translations[i].om_len); 918 919 /* 920 * If the mapping is 1:1, let the RAM and device 921 * on-demand BAT tables take care of the translation. 922 */ 923 if (translations[i].om_va == translations[i].om_pa) 924 continue; 925 926 /* Enter the pages */ 927 for (off = 0; off < translations[i].om_len; 928 off += PAGE_SIZE) 929 moea_kenter(mmup, translations[i].om_va + off, 930 translations[i].om_pa + off); 931 } 932 } 933 934 /* 935 * Calculate the last available physical address. 936 */ 937 for (i = 0; phys_avail[i + 2] != 0; i += 2) 938 ; 939 Maxmem = powerpc_btop(phys_avail[i + 1]); 940 941 moea_cpu_bootstrap(mmup,0); 942 943 pmap_bootstrapped++; 944 945 /* 946 * Set the start and end of kva. 947 */ 948 virtual_avail = VM_MIN_KERNEL_ADDRESS; 949 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 950 951 /* 952 * Allocate a kernel stack with a guard page for thread0 and map it 953 * into the kernel page map. 954 */ 955 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 956 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 957 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 958 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 959 thread0.td_kstack = va; 960 thread0.td_kstack_pages = KSTACK_PAGES; 961 for (i = 0; i < KSTACK_PAGES; i++) { 962 moea_kenter(mmup, va, pa); 963 pa += PAGE_SIZE; 964 va += PAGE_SIZE; 965 } 966 967 /* 968 * Allocate virtual address space for the message buffer. 969 */ 970 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 971 msgbufp = (struct msgbuf *)virtual_avail; 972 va = virtual_avail; 973 virtual_avail += round_page(msgbufsize); 974 while (va < virtual_avail) { 975 moea_kenter(mmup, va, pa); 976 pa += PAGE_SIZE; 977 va += PAGE_SIZE; 978 } 979 980 /* 981 * Allocate virtual address space for the dynamic percpu area. 982 */ 983 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 984 dpcpu = (void *)virtual_avail; 985 va = virtual_avail; 986 virtual_avail += DPCPU_SIZE; 987 while (va < virtual_avail) { 988 moea_kenter(mmup, va, pa); 989 pa += PAGE_SIZE; 990 va += PAGE_SIZE; 991 } 992 dpcpu_init(dpcpu, 0); 993 } 994 995 /* 996 * Activate a user pmap. The pmap must be activated before it's address 997 * space can be accessed in any way. 998 */ 999 void 1000 moea_activate(mmu_t mmu, struct thread *td) 1001 { 1002 pmap_t pm, pmr; 1003 1004 /* 1005 * Load all the data we need up front to encourage the compiler to 1006 * not issue any loads while we have interrupts disabled below. 1007 */ 1008 pm = &td->td_proc->p_vmspace->vm_pmap; 1009 pmr = pm->pmap_phys; 1010 1011 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1012 PCPU_SET(curpmap, pmr); 1013 } 1014 1015 void 1016 moea_deactivate(mmu_t mmu, struct thread *td) 1017 { 1018 pmap_t pm; 1019 1020 pm = &td->td_proc->p_vmspace->vm_pmap; 1021 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1022 PCPU_SET(curpmap, NULL); 1023 } 1024 1025 void 1026 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1027 { 1028 struct pvo_entry *pvo; 1029 1030 PMAP_LOCK(pm); 1031 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1032 1033 if (pvo != NULL) { 1034 if (wired) { 1035 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1036 pm->pm_stats.wired_count++; 1037 pvo->pvo_vaddr |= PVO_WIRED; 1038 } else { 1039 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1040 pm->pm_stats.wired_count--; 1041 pvo->pvo_vaddr &= ~PVO_WIRED; 1042 } 1043 } 1044 PMAP_UNLOCK(pm); 1045 } 1046 1047 void 1048 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1049 { 1050 vm_offset_t dst; 1051 vm_offset_t src; 1052 1053 dst = VM_PAGE_TO_PHYS(mdst); 1054 src = VM_PAGE_TO_PHYS(msrc); 1055 1056 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1057 } 1058 1059 void 1060 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1061 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1062 { 1063 void *a_cp, *b_cp; 1064 vm_offset_t a_pg_offset, b_pg_offset; 1065 int cnt; 1066 1067 while (xfersize > 0) { 1068 a_pg_offset = a_offset & PAGE_MASK; 1069 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1070 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1071 a_pg_offset; 1072 b_pg_offset = b_offset & PAGE_MASK; 1073 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1074 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1075 b_pg_offset; 1076 bcopy(a_cp, b_cp, cnt); 1077 a_offset += cnt; 1078 b_offset += cnt; 1079 xfersize -= cnt; 1080 } 1081 } 1082 1083 /* 1084 * Zero a page of physical memory by temporarily mapping it into the tlb. 1085 */ 1086 void 1087 moea_zero_page(mmu_t mmu, vm_page_t m) 1088 { 1089 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1090 void *va = (void *)pa; 1091 1092 bzero(va, PAGE_SIZE); 1093 } 1094 1095 void 1096 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1097 { 1098 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1099 void *va = (void *)(pa + off); 1100 1101 bzero(va, size); 1102 } 1103 1104 void 1105 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1106 { 1107 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1108 void *va = (void *)pa; 1109 1110 bzero(va, PAGE_SIZE); 1111 } 1112 1113 /* 1114 * Map the given physical page at the specified virtual address in the 1115 * target pmap with the protection requested. If specified the page 1116 * will be wired down. 1117 */ 1118 void 1119 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1120 boolean_t wired) 1121 { 1122 1123 rw_wlock(&pvh_global_lock); 1124 PMAP_LOCK(pmap); 1125 moea_enter_locked(pmap, va, m, prot, wired); 1126 rw_wunlock(&pvh_global_lock); 1127 PMAP_UNLOCK(pmap); 1128 } 1129 1130 /* 1131 * Map the given physical page at the specified virtual address in the 1132 * target pmap with the protection requested. If specified the page 1133 * will be wired down. 1134 * 1135 * The page queues and pmap must be locked. 1136 */ 1137 static void 1138 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1139 boolean_t wired) 1140 { 1141 struct pvo_head *pvo_head; 1142 uma_zone_t zone; 1143 vm_page_t pg; 1144 u_int pte_lo, pvo_flags; 1145 int error; 1146 1147 if (!moea_initialized) { 1148 pvo_head = &moea_pvo_kunmanaged; 1149 zone = moea_upvo_zone; 1150 pvo_flags = 0; 1151 pg = NULL; 1152 } else { 1153 pvo_head = vm_page_to_pvoh(m); 1154 pg = m; 1155 zone = moea_mpvo_zone; 1156 pvo_flags = PVO_MANAGED; 1157 } 1158 if (pmap_bootstrapped) 1159 rw_assert(&pvh_global_lock, RA_WLOCKED); 1160 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1161 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1162 VM_OBJECT_ASSERT_LOCKED(m->object); 1163 1164 /* XXX change the pvo head for fake pages */ 1165 if ((m->oflags & VPO_UNMANAGED) != 0) { 1166 pvo_flags &= ~PVO_MANAGED; 1167 pvo_head = &moea_pvo_kunmanaged; 1168 zone = moea_upvo_zone; 1169 } 1170 1171 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1172 1173 if (prot & VM_PROT_WRITE) { 1174 pte_lo |= PTE_BW; 1175 if (pmap_bootstrapped && 1176 (m->oflags & VPO_UNMANAGED) == 0) 1177 vm_page_aflag_set(m, PGA_WRITEABLE); 1178 } else 1179 pte_lo |= PTE_BR; 1180 1181 if (prot & VM_PROT_EXECUTE) 1182 pvo_flags |= PVO_EXECUTABLE; 1183 1184 if (wired) 1185 pvo_flags |= PVO_WIRED; 1186 1187 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1188 pte_lo, pvo_flags); 1189 1190 /* 1191 * Flush the real page from the instruction cache. This has be done 1192 * for all user mappings to prevent information leakage via the 1193 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1194 * mapping for a page. 1195 */ 1196 if (pmap != kernel_pmap && error == ENOENT && 1197 (pte_lo & (PTE_I | PTE_G)) == 0) 1198 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1199 } 1200 1201 /* 1202 * Maps a sequence of resident pages belonging to the same object. 1203 * The sequence begins with the given page m_start. This page is 1204 * mapped at the given virtual address start. Each subsequent page is 1205 * mapped at a virtual address that is offset from start by the same 1206 * amount as the page is offset from m_start within the object. The 1207 * last page in the sequence is the page with the largest offset from 1208 * m_start that can be mapped at a virtual address less than the given 1209 * virtual address end. Not every virtual page between start and end 1210 * is mapped; only those for which a resident page exists with the 1211 * corresponding offset from m_start are mapped. 1212 */ 1213 void 1214 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1215 vm_page_t m_start, vm_prot_t prot) 1216 { 1217 vm_page_t m; 1218 vm_pindex_t diff, psize; 1219 1220 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1221 1222 psize = atop(end - start); 1223 m = m_start; 1224 rw_wlock(&pvh_global_lock); 1225 PMAP_LOCK(pm); 1226 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1227 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1228 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1229 m = TAILQ_NEXT(m, listq); 1230 } 1231 rw_wunlock(&pvh_global_lock); 1232 PMAP_UNLOCK(pm); 1233 } 1234 1235 void 1236 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1237 vm_prot_t prot) 1238 { 1239 1240 rw_wlock(&pvh_global_lock); 1241 PMAP_LOCK(pm); 1242 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1243 FALSE); 1244 rw_wunlock(&pvh_global_lock); 1245 PMAP_UNLOCK(pm); 1246 } 1247 1248 vm_paddr_t 1249 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1250 { 1251 struct pvo_entry *pvo; 1252 vm_paddr_t pa; 1253 1254 PMAP_LOCK(pm); 1255 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1256 if (pvo == NULL) 1257 pa = 0; 1258 else 1259 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1260 PMAP_UNLOCK(pm); 1261 return (pa); 1262 } 1263 1264 /* 1265 * Atomically extract and hold the physical page with the given 1266 * pmap and virtual address pair if that mapping permits the given 1267 * protection. 1268 */ 1269 vm_page_t 1270 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1271 { 1272 struct pvo_entry *pvo; 1273 vm_page_t m; 1274 vm_paddr_t pa; 1275 1276 m = NULL; 1277 pa = 0; 1278 PMAP_LOCK(pmap); 1279 retry: 1280 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1281 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1282 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1283 (prot & VM_PROT_WRITE) == 0)) { 1284 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1285 goto retry; 1286 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1287 vm_page_hold(m); 1288 } 1289 PA_UNLOCK_COND(pa); 1290 PMAP_UNLOCK(pmap); 1291 return (m); 1292 } 1293 1294 void 1295 moea_init(mmu_t mmu) 1296 { 1297 1298 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1299 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1300 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1301 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1302 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1303 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1304 moea_initialized = TRUE; 1305 } 1306 1307 boolean_t 1308 moea_is_referenced(mmu_t mmu, vm_page_t m) 1309 { 1310 boolean_t rv; 1311 1312 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1313 ("moea_is_referenced: page %p is not managed", m)); 1314 rw_wlock(&pvh_global_lock); 1315 rv = moea_query_bit(m, PTE_REF); 1316 rw_wunlock(&pvh_global_lock); 1317 return (rv); 1318 } 1319 1320 boolean_t 1321 moea_is_modified(mmu_t mmu, vm_page_t m) 1322 { 1323 boolean_t rv; 1324 1325 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1326 ("moea_is_modified: page %p is not managed", m)); 1327 1328 /* 1329 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1330 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1331 * is clear, no PTEs can have PTE_CHG set. 1332 */ 1333 VM_OBJECT_ASSERT_WLOCKED(m->object); 1334 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1335 return (FALSE); 1336 rw_wlock(&pvh_global_lock); 1337 rv = moea_query_bit(m, PTE_CHG); 1338 rw_wunlock(&pvh_global_lock); 1339 return (rv); 1340 } 1341 1342 boolean_t 1343 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1344 { 1345 struct pvo_entry *pvo; 1346 boolean_t rv; 1347 1348 PMAP_LOCK(pmap); 1349 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1350 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1351 PMAP_UNLOCK(pmap); 1352 return (rv); 1353 } 1354 1355 void 1356 moea_clear_reference(mmu_t mmu, vm_page_t m) 1357 { 1358 1359 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1360 ("moea_clear_reference: page %p is not managed", m)); 1361 rw_wlock(&pvh_global_lock); 1362 moea_clear_bit(m, PTE_REF); 1363 rw_wunlock(&pvh_global_lock); 1364 } 1365 1366 void 1367 moea_clear_modify(mmu_t mmu, vm_page_t m) 1368 { 1369 1370 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1371 ("moea_clear_modify: page %p is not managed", m)); 1372 VM_OBJECT_ASSERT_WLOCKED(m->object); 1373 KASSERT(!vm_page_xbusied(m), 1374 ("moea_clear_modify: page %p is exclusive busy", m)); 1375 1376 /* 1377 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1378 * set. If the object containing the page is locked and the page is 1379 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1380 */ 1381 if ((m->aflags & PGA_WRITEABLE) == 0) 1382 return; 1383 rw_wlock(&pvh_global_lock); 1384 moea_clear_bit(m, PTE_CHG); 1385 rw_wunlock(&pvh_global_lock); 1386 } 1387 1388 /* 1389 * Clear the write and modified bits in each of the given page's mappings. 1390 */ 1391 void 1392 moea_remove_write(mmu_t mmu, vm_page_t m) 1393 { 1394 struct pvo_entry *pvo; 1395 struct pte *pt; 1396 pmap_t pmap; 1397 u_int lo; 1398 1399 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1400 ("moea_remove_write: page %p is not managed", m)); 1401 1402 /* 1403 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1404 * set by another thread while the object is locked. Thus, 1405 * if PGA_WRITEABLE is clear, no page table entries need updating. 1406 */ 1407 VM_OBJECT_ASSERT_WLOCKED(m->object); 1408 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1409 return; 1410 rw_wlock(&pvh_global_lock); 1411 lo = moea_attr_fetch(m); 1412 powerpc_sync(); 1413 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1414 pmap = pvo->pvo_pmap; 1415 PMAP_LOCK(pmap); 1416 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1417 pt = moea_pvo_to_pte(pvo, -1); 1418 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1419 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1420 if (pt != NULL) { 1421 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1422 lo |= pvo->pvo_pte.pte.pte_lo; 1423 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1424 moea_pte_change(pt, &pvo->pvo_pte.pte, 1425 pvo->pvo_vaddr); 1426 mtx_unlock(&moea_table_mutex); 1427 } 1428 } 1429 PMAP_UNLOCK(pmap); 1430 } 1431 if ((lo & PTE_CHG) != 0) { 1432 moea_attr_clear(m, PTE_CHG); 1433 vm_page_dirty(m); 1434 } 1435 vm_page_aflag_clear(m, PGA_WRITEABLE); 1436 rw_wunlock(&pvh_global_lock); 1437 } 1438 1439 /* 1440 * moea_ts_referenced: 1441 * 1442 * Return a count of reference bits for a page, clearing those bits. 1443 * It is not necessary for every reference bit to be cleared, but it 1444 * is necessary that 0 only be returned when there are truly no 1445 * reference bits set. 1446 * 1447 * XXX: The exact number of bits to check and clear is a matter that 1448 * should be tested and standardized at some point in the future for 1449 * optimal aging of shared pages. 1450 */ 1451 int 1452 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1453 { 1454 int count; 1455 1456 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1457 ("moea_ts_referenced: page %p is not managed", m)); 1458 rw_wlock(&pvh_global_lock); 1459 count = moea_clear_bit(m, PTE_REF); 1460 rw_wunlock(&pvh_global_lock); 1461 return (count); 1462 } 1463 1464 /* 1465 * Modify the WIMG settings of all mappings for a page. 1466 */ 1467 void 1468 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1469 { 1470 struct pvo_entry *pvo; 1471 struct pvo_head *pvo_head; 1472 struct pte *pt; 1473 pmap_t pmap; 1474 u_int lo; 1475 1476 if ((m->oflags & VPO_UNMANAGED) != 0) { 1477 m->md.mdpg_cache_attrs = ma; 1478 return; 1479 } 1480 1481 rw_wlock(&pvh_global_lock); 1482 pvo_head = vm_page_to_pvoh(m); 1483 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1484 1485 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1486 pmap = pvo->pvo_pmap; 1487 PMAP_LOCK(pmap); 1488 pt = moea_pvo_to_pte(pvo, -1); 1489 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1490 pvo->pvo_pte.pte.pte_lo |= lo; 1491 if (pt != NULL) { 1492 moea_pte_change(pt, &pvo->pvo_pte.pte, 1493 pvo->pvo_vaddr); 1494 if (pvo->pvo_pmap == kernel_pmap) 1495 isync(); 1496 } 1497 mtx_unlock(&moea_table_mutex); 1498 PMAP_UNLOCK(pmap); 1499 } 1500 m->md.mdpg_cache_attrs = ma; 1501 rw_wunlock(&pvh_global_lock); 1502 } 1503 1504 /* 1505 * Map a wired page into kernel virtual address space. 1506 */ 1507 void 1508 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1509 { 1510 1511 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1512 } 1513 1514 void 1515 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1516 { 1517 u_int pte_lo; 1518 int error; 1519 1520 #if 0 1521 if (va < VM_MIN_KERNEL_ADDRESS) 1522 panic("moea_kenter: attempt to enter non-kernel address %#x", 1523 va); 1524 #endif 1525 1526 pte_lo = moea_calc_wimg(pa, ma); 1527 1528 PMAP_LOCK(kernel_pmap); 1529 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1530 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1531 1532 if (error != 0 && error != ENOENT) 1533 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1534 pa, error); 1535 1536 PMAP_UNLOCK(kernel_pmap); 1537 } 1538 1539 /* 1540 * Extract the physical page address associated with the given kernel virtual 1541 * address. 1542 */ 1543 vm_paddr_t 1544 moea_kextract(mmu_t mmu, vm_offset_t va) 1545 { 1546 struct pvo_entry *pvo; 1547 vm_paddr_t pa; 1548 1549 /* 1550 * Allow direct mappings on 32-bit OEA 1551 */ 1552 if (va < VM_MIN_KERNEL_ADDRESS) { 1553 return (va); 1554 } 1555 1556 PMAP_LOCK(kernel_pmap); 1557 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1558 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1559 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1560 PMAP_UNLOCK(kernel_pmap); 1561 return (pa); 1562 } 1563 1564 /* 1565 * Remove a wired page from kernel virtual address space. 1566 */ 1567 void 1568 moea_kremove(mmu_t mmu, vm_offset_t va) 1569 { 1570 1571 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1572 } 1573 1574 /* 1575 * Map a range of physical addresses into kernel virtual address space. 1576 * 1577 * The value passed in *virt is a suggested virtual address for the mapping. 1578 * Architectures which can support a direct-mapped physical to virtual region 1579 * can return the appropriate address within that region, leaving '*virt' 1580 * unchanged. We cannot and therefore do not; *virt is updated with the 1581 * first usable address after the mapped region. 1582 */ 1583 vm_offset_t 1584 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1585 vm_paddr_t pa_end, int prot) 1586 { 1587 vm_offset_t sva, va; 1588 1589 sva = *virt; 1590 va = sva; 1591 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1592 moea_kenter(mmu, va, pa_start); 1593 *virt = va; 1594 return (sva); 1595 } 1596 1597 /* 1598 * Returns true if the pmap's pv is one of the first 1599 * 16 pvs linked to from this page. This count may 1600 * be changed upwards or downwards in the future; it 1601 * is only necessary that true be returned for a small 1602 * subset of pmaps for proper page aging. 1603 */ 1604 boolean_t 1605 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1606 { 1607 int loops; 1608 struct pvo_entry *pvo; 1609 boolean_t rv; 1610 1611 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1612 ("moea_page_exists_quick: page %p is not managed", m)); 1613 loops = 0; 1614 rv = FALSE; 1615 rw_wlock(&pvh_global_lock); 1616 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1617 if (pvo->pvo_pmap == pmap) { 1618 rv = TRUE; 1619 break; 1620 } 1621 if (++loops >= 16) 1622 break; 1623 } 1624 rw_wunlock(&pvh_global_lock); 1625 return (rv); 1626 } 1627 1628 /* 1629 * Return the number of managed mappings to the given physical page 1630 * that are wired. 1631 */ 1632 int 1633 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1634 { 1635 struct pvo_entry *pvo; 1636 int count; 1637 1638 count = 0; 1639 if ((m->oflags & VPO_UNMANAGED) != 0) 1640 return (count); 1641 rw_wlock(&pvh_global_lock); 1642 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1643 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1644 count++; 1645 rw_wunlock(&pvh_global_lock); 1646 return (count); 1647 } 1648 1649 static u_int moea_vsidcontext; 1650 1651 void 1652 moea_pinit(mmu_t mmu, pmap_t pmap) 1653 { 1654 int i, mask; 1655 u_int entropy; 1656 1657 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1658 RB_INIT(&pmap->pmap_pvo); 1659 1660 entropy = 0; 1661 __asm __volatile("mftb %0" : "=r"(entropy)); 1662 1663 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1664 == NULL) { 1665 pmap->pmap_phys = pmap; 1666 } 1667 1668 1669 mtx_lock(&moea_vsid_mutex); 1670 /* 1671 * Allocate some segment registers for this pmap. 1672 */ 1673 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1674 u_int hash, n; 1675 1676 /* 1677 * Create a new value by mutiplying by a prime and adding in 1678 * entropy from the timebase register. This is to make the 1679 * VSID more random so that the PT hash function collides 1680 * less often. (Note that the prime casues gcc to do shifts 1681 * instead of a multiply.) 1682 */ 1683 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1684 hash = moea_vsidcontext & (NPMAPS - 1); 1685 if (hash == 0) /* 0 is special, avoid it */ 1686 continue; 1687 n = hash >> 5; 1688 mask = 1 << (hash & (VSID_NBPW - 1)); 1689 hash = (moea_vsidcontext & 0xfffff); 1690 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1691 /* anything free in this bucket? */ 1692 if (moea_vsid_bitmap[n] == 0xffffffff) { 1693 entropy = (moea_vsidcontext >> 20); 1694 continue; 1695 } 1696 i = ffs(~moea_vsid_bitmap[n]) - 1; 1697 mask = 1 << i; 1698 hash &= 0xfffff & ~(VSID_NBPW - 1); 1699 hash |= i; 1700 } 1701 KASSERT(!(moea_vsid_bitmap[n] & mask), 1702 ("Allocating in-use VSID group %#x\n", hash)); 1703 moea_vsid_bitmap[n] |= mask; 1704 for (i = 0; i < 16; i++) 1705 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1706 mtx_unlock(&moea_vsid_mutex); 1707 return; 1708 } 1709 1710 mtx_unlock(&moea_vsid_mutex); 1711 panic("moea_pinit: out of segments"); 1712 } 1713 1714 /* 1715 * Initialize the pmap associated with process 0. 1716 */ 1717 void 1718 moea_pinit0(mmu_t mmu, pmap_t pm) 1719 { 1720 1721 PMAP_LOCK_INIT(pm); 1722 moea_pinit(mmu, pm); 1723 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1724 } 1725 1726 /* 1727 * Set the physical protection on the specified range of this map as requested. 1728 */ 1729 void 1730 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1731 vm_prot_t prot) 1732 { 1733 struct pvo_entry *pvo, *tpvo, key; 1734 struct pte *pt; 1735 1736 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1737 ("moea_protect: non current pmap")); 1738 1739 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1740 moea_remove(mmu, pm, sva, eva); 1741 return; 1742 } 1743 1744 rw_wlock(&pvh_global_lock); 1745 PMAP_LOCK(pm); 1746 key.pvo_vaddr = sva; 1747 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1748 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1749 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1750 if ((prot & VM_PROT_EXECUTE) == 0) 1751 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1752 1753 /* 1754 * Grab the PTE pointer before we diddle with the cached PTE 1755 * copy. 1756 */ 1757 pt = moea_pvo_to_pte(pvo, -1); 1758 /* 1759 * Change the protection of the page. 1760 */ 1761 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1762 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1763 1764 /* 1765 * If the PVO is in the page table, update that pte as well. 1766 */ 1767 if (pt != NULL) { 1768 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1769 mtx_unlock(&moea_table_mutex); 1770 } 1771 } 1772 rw_wunlock(&pvh_global_lock); 1773 PMAP_UNLOCK(pm); 1774 } 1775 1776 /* 1777 * Map a list of wired pages into kernel virtual address space. This is 1778 * intended for temporary mappings which do not need page modification or 1779 * references recorded. Existing mappings in the region are overwritten. 1780 */ 1781 void 1782 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1783 { 1784 vm_offset_t va; 1785 1786 va = sva; 1787 while (count-- > 0) { 1788 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1789 va += PAGE_SIZE; 1790 m++; 1791 } 1792 } 1793 1794 /* 1795 * Remove page mappings from kernel virtual address space. Intended for 1796 * temporary mappings entered by moea_qenter. 1797 */ 1798 void 1799 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1800 { 1801 vm_offset_t va; 1802 1803 va = sva; 1804 while (count-- > 0) { 1805 moea_kremove(mmu, va); 1806 va += PAGE_SIZE; 1807 } 1808 } 1809 1810 void 1811 moea_release(mmu_t mmu, pmap_t pmap) 1812 { 1813 int idx, mask; 1814 1815 /* 1816 * Free segment register's VSID 1817 */ 1818 if (pmap->pm_sr[0] == 0) 1819 panic("moea_release"); 1820 1821 mtx_lock(&moea_vsid_mutex); 1822 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1823 mask = 1 << (idx % VSID_NBPW); 1824 idx /= VSID_NBPW; 1825 moea_vsid_bitmap[idx] &= ~mask; 1826 mtx_unlock(&moea_vsid_mutex); 1827 } 1828 1829 /* 1830 * Remove the given range of addresses from the specified map. 1831 */ 1832 void 1833 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1834 { 1835 struct pvo_entry *pvo, *tpvo, key; 1836 1837 rw_wlock(&pvh_global_lock); 1838 PMAP_LOCK(pm); 1839 key.pvo_vaddr = sva; 1840 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1841 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1842 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1843 moea_pvo_remove(pvo, -1); 1844 } 1845 PMAP_UNLOCK(pm); 1846 rw_wunlock(&pvh_global_lock); 1847 } 1848 1849 /* 1850 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1851 * will reflect changes in pte's back to the vm_page. 1852 */ 1853 void 1854 moea_remove_all(mmu_t mmu, vm_page_t m) 1855 { 1856 struct pvo_head *pvo_head; 1857 struct pvo_entry *pvo, *next_pvo; 1858 pmap_t pmap; 1859 1860 rw_wlock(&pvh_global_lock); 1861 pvo_head = vm_page_to_pvoh(m); 1862 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1863 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1864 1865 pmap = pvo->pvo_pmap; 1866 PMAP_LOCK(pmap); 1867 moea_pvo_remove(pvo, -1); 1868 PMAP_UNLOCK(pmap); 1869 } 1870 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1871 moea_attr_clear(m, PTE_CHG); 1872 vm_page_dirty(m); 1873 } 1874 vm_page_aflag_clear(m, PGA_WRITEABLE); 1875 rw_wunlock(&pvh_global_lock); 1876 } 1877 1878 /* 1879 * Allocate a physical page of memory directly from the phys_avail map. 1880 * Can only be called from moea_bootstrap before avail start and end are 1881 * calculated. 1882 */ 1883 static vm_offset_t 1884 moea_bootstrap_alloc(vm_size_t size, u_int align) 1885 { 1886 vm_offset_t s, e; 1887 int i, j; 1888 1889 size = round_page(size); 1890 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1891 if (align != 0) 1892 s = (phys_avail[i] + align - 1) & ~(align - 1); 1893 else 1894 s = phys_avail[i]; 1895 e = s + size; 1896 1897 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1898 continue; 1899 1900 if (s == phys_avail[i]) { 1901 phys_avail[i] += size; 1902 } else if (e == phys_avail[i + 1]) { 1903 phys_avail[i + 1] -= size; 1904 } else { 1905 for (j = phys_avail_count * 2; j > i; j -= 2) { 1906 phys_avail[j] = phys_avail[j - 2]; 1907 phys_avail[j + 1] = phys_avail[j - 1]; 1908 } 1909 1910 phys_avail[i + 3] = phys_avail[i + 1]; 1911 phys_avail[i + 1] = s; 1912 phys_avail[i + 2] = e; 1913 phys_avail_count++; 1914 } 1915 1916 return (s); 1917 } 1918 panic("moea_bootstrap_alloc: could not allocate memory"); 1919 } 1920 1921 static void 1922 moea_syncicache(vm_offset_t pa, vm_size_t len) 1923 { 1924 __syncicache((void *)pa, len); 1925 } 1926 1927 static int 1928 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1929 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1930 { 1931 struct pvo_entry *pvo; 1932 u_int sr; 1933 int first; 1934 u_int ptegidx; 1935 int i; 1936 int bootstrap; 1937 1938 moea_pvo_enter_calls++; 1939 first = 0; 1940 bootstrap = 0; 1941 1942 /* 1943 * Compute the PTE Group index. 1944 */ 1945 va &= ~ADDR_POFF; 1946 sr = va_to_sr(pm->pm_sr, va); 1947 ptegidx = va_to_pteg(sr, va); 1948 1949 /* 1950 * Remove any existing mapping for this page. Reuse the pvo entry if 1951 * there is a mapping. 1952 */ 1953 mtx_lock(&moea_table_mutex); 1954 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1955 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1956 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1957 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1958 (pte_lo & PTE_PP)) { 1959 mtx_unlock(&moea_table_mutex); 1960 return (0); 1961 } 1962 moea_pvo_remove(pvo, -1); 1963 break; 1964 } 1965 } 1966 1967 /* 1968 * If we aren't overwriting a mapping, try to allocate. 1969 */ 1970 if (moea_initialized) { 1971 pvo = uma_zalloc(zone, M_NOWAIT); 1972 } else { 1973 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1974 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1975 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1976 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1977 } 1978 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1979 moea_bpvo_pool_index++; 1980 bootstrap = 1; 1981 } 1982 1983 if (pvo == NULL) { 1984 mtx_unlock(&moea_table_mutex); 1985 return (ENOMEM); 1986 } 1987 1988 moea_pvo_entries++; 1989 pvo->pvo_vaddr = va; 1990 pvo->pvo_pmap = pm; 1991 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1992 pvo->pvo_vaddr &= ~ADDR_POFF; 1993 if (flags & VM_PROT_EXECUTE) 1994 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1995 if (flags & PVO_WIRED) 1996 pvo->pvo_vaddr |= PVO_WIRED; 1997 if (pvo_head != &moea_pvo_kunmanaged) 1998 pvo->pvo_vaddr |= PVO_MANAGED; 1999 if (bootstrap) 2000 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2001 2002 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2003 2004 /* 2005 * Add to pmap list 2006 */ 2007 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2008 2009 /* 2010 * Remember if the list was empty and therefore will be the first 2011 * item. 2012 */ 2013 if (LIST_FIRST(pvo_head) == NULL) 2014 first = 1; 2015 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2016 2017 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2018 pm->pm_stats.wired_count++; 2019 pm->pm_stats.resident_count++; 2020 2021 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2022 KASSERT(i < 8, ("Invalid PTE index")); 2023 if (i >= 0) { 2024 PVO_PTEGIDX_SET(pvo, i); 2025 } else { 2026 panic("moea_pvo_enter: overflow"); 2027 moea_pte_overflow++; 2028 } 2029 mtx_unlock(&moea_table_mutex); 2030 2031 return (first ? ENOENT : 0); 2032 } 2033 2034 static void 2035 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2036 { 2037 struct pte *pt; 2038 2039 /* 2040 * If there is an active pte entry, we need to deactivate it (and 2041 * save the ref & cfg bits). 2042 */ 2043 pt = moea_pvo_to_pte(pvo, pteidx); 2044 if (pt != NULL) { 2045 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2046 mtx_unlock(&moea_table_mutex); 2047 PVO_PTEGIDX_CLR(pvo); 2048 } else { 2049 moea_pte_overflow--; 2050 } 2051 2052 /* 2053 * Update our statistics. 2054 */ 2055 pvo->pvo_pmap->pm_stats.resident_count--; 2056 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2057 pvo->pvo_pmap->pm_stats.wired_count--; 2058 2059 /* 2060 * Save the REF/CHG bits into their cache if the page is managed. 2061 */ 2062 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2063 struct vm_page *pg; 2064 2065 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2066 if (pg != NULL) { 2067 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2068 (PTE_REF | PTE_CHG)); 2069 } 2070 } 2071 2072 /* 2073 * Remove this PVO from the PV and pmap lists. 2074 */ 2075 LIST_REMOVE(pvo, pvo_vlink); 2076 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2077 2078 /* 2079 * Remove this from the overflow list and return it to the pool 2080 * if we aren't going to reuse it. 2081 */ 2082 LIST_REMOVE(pvo, pvo_olink); 2083 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2084 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2085 moea_upvo_zone, pvo); 2086 moea_pvo_entries--; 2087 moea_pvo_remove_calls++; 2088 } 2089 2090 static __inline int 2091 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2092 { 2093 int pteidx; 2094 2095 /* 2096 * We can find the actual pte entry without searching by grabbing 2097 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2098 * noticing the HID bit. 2099 */ 2100 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2101 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2102 pteidx ^= moea_pteg_mask * 8; 2103 2104 return (pteidx); 2105 } 2106 2107 static struct pvo_entry * 2108 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2109 { 2110 struct pvo_entry *pvo; 2111 int ptegidx; 2112 u_int sr; 2113 2114 va &= ~ADDR_POFF; 2115 sr = va_to_sr(pm->pm_sr, va); 2116 ptegidx = va_to_pteg(sr, va); 2117 2118 mtx_lock(&moea_table_mutex); 2119 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2120 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2121 if (pteidx_p) 2122 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2123 break; 2124 } 2125 } 2126 mtx_unlock(&moea_table_mutex); 2127 2128 return (pvo); 2129 } 2130 2131 static struct pte * 2132 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2133 { 2134 struct pte *pt; 2135 2136 /* 2137 * If we haven't been supplied the ptegidx, calculate it. 2138 */ 2139 if (pteidx == -1) { 2140 int ptegidx; 2141 u_int sr; 2142 2143 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2144 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2145 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2146 } 2147 2148 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2149 mtx_lock(&moea_table_mutex); 2150 2151 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2152 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2153 "valid pte index", pvo); 2154 } 2155 2156 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2157 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2158 "pvo but no valid pte", pvo); 2159 } 2160 2161 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2162 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2163 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2164 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2165 } 2166 2167 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2168 != 0) { 2169 panic("moea_pvo_to_pte: pvo %p pte does not match " 2170 "pte %p in moea_pteg_table", pvo, pt); 2171 } 2172 2173 mtx_assert(&moea_table_mutex, MA_OWNED); 2174 return (pt); 2175 } 2176 2177 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2178 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2179 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2180 } 2181 2182 mtx_unlock(&moea_table_mutex); 2183 return (NULL); 2184 } 2185 2186 /* 2187 * XXX: THIS STUFF SHOULD BE IN pte.c? 2188 */ 2189 int 2190 moea_pte_spill(vm_offset_t addr) 2191 { 2192 struct pvo_entry *source_pvo, *victim_pvo; 2193 struct pvo_entry *pvo; 2194 int ptegidx, i, j; 2195 u_int sr; 2196 struct pteg *pteg; 2197 struct pte *pt; 2198 2199 moea_pte_spills++; 2200 2201 sr = mfsrin(addr); 2202 ptegidx = va_to_pteg(sr, addr); 2203 2204 /* 2205 * Have to substitute some entry. Use the primary hash for this. 2206 * Use low bits of timebase as random generator. 2207 */ 2208 pteg = &moea_pteg_table[ptegidx]; 2209 mtx_lock(&moea_table_mutex); 2210 __asm __volatile("mftb %0" : "=r"(i)); 2211 i &= 7; 2212 pt = &pteg->pt[i]; 2213 2214 source_pvo = NULL; 2215 victim_pvo = NULL; 2216 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2217 /* 2218 * We need to find a pvo entry for this address. 2219 */ 2220 if (source_pvo == NULL && 2221 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2222 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2223 /* 2224 * Now found an entry to be spilled into the pteg. 2225 * The PTE is now valid, so we know it's active. 2226 */ 2227 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2228 2229 if (j >= 0) { 2230 PVO_PTEGIDX_SET(pvo, j); 2231 moea_pte_overflow--; 2232 mtx_unlock(&moea_table_mutex); 2233 return (1); 2234 } 2235 2236 source_pvo = pvo; 2237 2238 if (victim_pvo != NULL) 2239 break; 2240 } 2241 2242 /* 2243 * We also need the pvo entry of the victim we are replacing 2244 * so save the R & C bits of the PTE. 2245 */ 2246 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2247 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2248 victim_pvo = pvo; 2249 if (source_pvo != NULL) 2250 break; 2251 } 2252 } 2253 2254 if (source_pvo == NULL) { 2255 mtx_unlock(&moea_table_mutex); 2256 return (0); 2257 } 2258 2259 if (victim_pvo == NULL) { 2260 if ((pt->pte_hi & PTE_HID) == 0) 2261 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2262 "entry", pt); 2263 2264 /* 2265 * If this is a secondary PTE, we need to search it's primary 2266 * pvo bucket for the matching PVO. 2267 */ 2268 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2269 pvo_olink) { 2270 /* 2271 * We also need the pvo entry of the victim we are 2272 * replacing so save the R & C bits of the PTE. 2273 */ 2274 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2275 victim_pvo = pvo; 2276 break; 2277 } 2278 } 2279 2280 if (victim_pvo == NULL) 2281 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2282 "entry", pt); 2283 } 2284 2285 /* 2286 * We are invalidating the TLB entry for the EA we are replacing even 2287 * though it's valid. If we don't, we lose any ref/chg bit changes 2288 * contained in the TLB entry. 2289 */ 2290 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2291 2292 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2293 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2294 2295 PVO_PTEGIDX_CLR(victim_pvo); 2296 PVO_PTEGIDX_SET(source_pvo, i); 2297 moea_pte_replacements++; 2298 2299 mtx_unlock(&moea_table_mutex); 2300 return (1); 2301 } 2302 2303 static __inline struct pvo_entry * 2304 moea_pte_spillable_ident(u_int ptegidx) 2305 { 2306 struct pte *pt; 2307 struct pvo_entry *pvo_walk, *pvo = NULL; 2308 2309 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2310 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2311 continue; 2312 2313 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2314 continue; 2315 2316 pt = moea_pvo_to_pte(pvo_walk, -1); 2317 2318 if (pt == NULL) 2319 continue; 2320 2321 pvo = pvo_walk; 2322 2323 mtx_unlock(&moea_table_mutex); 2324 if (!(pt->pte_lo & PTE_REF)) 2325 return (pvo_walk); 2326 } 2327 2328 return (pvo); 2329 } 2330 2331 static int 2332 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2333 { 2334 struct pte *pt; 2335 struct pvo_entry *victim_pvo; 2336 int i; 2337 int victim_idx; 2338 u_int pteg_bkpidx = ptegidx; 2339 2340 mtx_assert(&moea_table_mutex, MA_OWNED); 2341 2342 /* 2343 * First try primary hash. 2344 */ 2345 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2346 if ((pt->pte_hi & PTE_VALID) == 0) { 2347 pvo_pt->pte_hi &= ~PTE_HID; 2348 moea_pte_set(pt, pvo_pt); 2349 return (i); 2350 } 2351 } 2352 2353 /* 2354 * Now try secondary hash. 2355 */ 2356 ptegidx ^= moea_pteg_mask; 2357 2358 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2359 if ((pt->pte_hi & PTE_VALID) == 0) { 2360 pvo_pt->pte_hi |= PTE_HID; 2361 moea_pte_set(pt, pvo_pt); 2362 return (i); 2363 } 2364 } 2365 2366 /* Try again, but this time try to force a PTE out. */ 2367 ptegidx = pteg_bkpidx; 2368 2369 victim_pvo = moea_pte_spillable_ident(ptegidx); 2370 if (victim_pvo == NULL) { 2371 ptegidx ^= moea_pteg_mask; 2372 victim_pvo = moea_pte_spillable_ident(ptegidx); 2373 } 2374 2375 if (victim_pvo == NULL) { 2376 panic("moea_pte_insert: overflow"); 2377 return (-1); 2378 } 2379 2380 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2381 2382 if (pteg_bkpidx == ptegidx) 2383 pvo_pt->pte_hi &= ~PTE_HID; 2384 else 2385 pvo_pt->pte_hi |= PTE_HID; 2386 2387 /* 2388 * Synchronize the sacrifice PTE with its PVO, then mark both 2389 * invalid. The PVO will be reused when/if the VM system comes 2390 * here after a fault. 2391 */ 2392 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2393 2394 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2395 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2396 2397 /* 2398 * Set the new PTE. 2399 */ 2400 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2401 PVO_PTEGIDX_CLR(victim_pvo); 2402 moea_pte_overflow++; 2403 moea_pte_set(pt, pvo_pt); 2404 2405 return (victim_idx & 7); 2406 } 2407 2408 static boolean_t 2409 moea_query_bit(vm_page_t m, int ptebit) 2410 { 2411 struct pvo_entry *pvo; 2412 struct pte *pt; 2413 2414 rw_assert(&pvh_global_lock, RA_WLOCKED); 2415 if (moea_attr_fetch(m) & ptebit) 2416 return (TRUE); 2417 2418 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2419 2420 /* 2421 * See if we saved the bit off. If so, cache it and return 2422 * success. 2423 */ 2424 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2425 moea_attr_save(m, ptebit); 2426 return (TRUE); 2427 } 2428 } 2429 2430 /* 2431 * No luck, now go through the hard part of looking at the PTEs 2432 * themselves. Sync so that any pending REF/CHG bits are flushed to 2433 * the PTEs. 2434 */ 2435 powerpc_sync(); 2436 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2437 2438 /* 2439 * See if this pvo has a valid PTE. if so, fetch the 2440 * REF/CHG bits from the valid PTE. If the appropriate 2441 * ptebit is set, cache it and return success. 2442 */ 2443 pt = moea_pvo_to_pte(pvo, -1); 2444 if (pt != NULL) { 2445 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2446 mtx_unlock(&moea_table_mutex); 2447 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2448 moea_attr_save(m, ptebit); 2449 return (TRUE); 2450 } 2451 } 2452 } 2453 2454 return (FALSE); 2455 } 2456 2457 static u_int 2458 moea_clear_bit(vm_page_t m, int ptebit) 2459 { 2460 u_int count; 2461 struct pvo_entry *pvo; 2462 struct pte *pt; 2463 2464 rw_assert(&pvh_global_lock, RA_WLOCKED); 2465 2466 /* 2467 * Clear the cached value. 2468 */ 2469 moea_attr_clear(m, ptebit); 2470 2471 /* 2472 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2473 * we can reset the right ones). note that since the pvo entries and 2474 * list heads are accessed via BAT0 and are never placed in the page 2475 * table, we don't have to worry about further accesses setting the 2476 * REF/CHG bits. 2477 */ 2478 powerpc_sync(); 2479 2480 /* 2481 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2482 * valid pte clear the ptebit from the valid pte. 2483 */ 2484 count = 0; 2485 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2486 pt = moea_pvo_to_pte(pvo, -1); 2487 if (pt != NULL) { 2488 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2489 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2490 count++; 2491 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2492 } 2493 mtx_unlock(&moea_table_mutex); 2494 } 2495 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2496 } 2497 2498 return (count); 2499 } 2500 2501 /* 2502 * Return true if the physical range is encompassed by the battable[idx] 2503 */ 2504 static int 2505 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2506 { 2507 u_int prot; 2508 u_int32_t start; 2509 u_int32_t end; 2510 u_int32_t bat_ble; 2511 2512 /* 2513 * Return immediately if not a valid mapping 2514 */ 2515 if (!(battable[idx].batu & BAT_Vs)) 2516 return (EINVAL); 2517 2518 /* 2519 * The BAT entry must be cache-inhibited, guarded, and r/w 2520 * so it can function as an i/o page 2521 */ 2522 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2523 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2524 return (EPERM); 2525 2526 /* 2527 * The address should be within the BAT range. Assume that the 2528 * start address in the BAT has the correct alignment (thus 2529 * not requiring masking) 2530 */ 2531 start = battable[idx].batl & BAT_PBS; 2532 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2533 end = start | (bat_ble << 15) | 0x7fff; 2534 2535 if ((pa < start) || ((pa + size) > end)) 2536 return (ERANGE); 2537 2538 return (0); 2539 } 2540 2541 boolean_t 2542 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2543 { 2544 int i; 2545 2546 /* 2547 * This currently does not work for entries that 2548 * overlap 256M BAT segments. 2549 */ 2550 2551 for(i = 0; i < 16; i++) 2552 if (moea_bat_mapped(i, pa, size) == 0) 2553 return (0); 2554 2555 return (EFAULT); 2556 } 2557 2558 /* 2559 * Map a set of physical memory pages into the kernel virtual 2560 * address space. Return a pointer to where it is mapped. This 2561 * routine is intended to be used for mapping device memory, 2562 * NOT real memory. 2563 */ 2564 void * 2565 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2566 { 2567 2568 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2569 } 2570 2571 void * 2572 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2573 { 2574 vm_offset_t va, tmpva, ppa, offset; 2575 int i; 2576 2577 ppa = trunc_page(pa); 2578 offset = pa & PAGE_MASK; 2579 size = roundup(offset + size, PAGE_SIZE); 2580 2581 /* 2582 * If the physical address lies within a valid BAT table entry, 2583 * return the 1:1 mapping. This currently doesn't work 2584 * for regions that overlap 256M BAT segments. 2585 */ 2586 for (i = 0; i < 16; i++) { 2587 if (moea_bat_mapped(i, pa, size) == 0) 2588 return ((void *) pa); 2589 } 2590 2591 va = kva_alloc(size); 2592 if (!va) 2593 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2594 2595 for (tmpva = va; size > 0;) { 2596 moea_kenter_attr(mmu, tmpva, ppa, ma); 2597 tlbie(tmpva); 2598 size -= PAGE_SIZE; 2599 tmpva += PAGE_SIZE; 2600 ppa += PAGE_SIZE; 2601 } 2602 2603 return ((void *)(va + offset)); 2604 } 2605 2606 void 2607 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2608 { 2609 vm_offset_t base, offset; 2610 2611 /* 2612 * If this is outside kernel virtual space, then it's a 2613 * battable entry and doesn't require unmapping 2614 */ 2615 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2616 base = trunc_page(va); 2617 offset = va & PAGE_MASK; 2618 size = roundup(offset + size, PAGE_SIZE); 2619 kva_free(base, size); 2620 } 2621 } 2622 2623 static void 2624 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2625 { 2626 struct pvo_entry *pvo; 2627 vm_offset_t lim; 2628 vm_paddr_t pa; 2629 vm_size_t len; 2630 2631 PMAP_LOCK(pm); 2632 while (sz > 0) { 2633 lim = round_page(va); 2634 len = MIN(lim - va, sz); 2635 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2636 if (pvo != NULL) { 2637 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2638 (va & ADDR_POFF); 2639 moea_syncicache(pa, len); 2640 } 2641 va += len; 2642 sz -= len; 2643 } 2644 PMAP_UNLOCK(pm); 2645 } 2646 2647 vm_offset_t 2648 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2649 vm_size_t *sz) 2650 { 2651 if (md->md_vaddr == ~0UL) 2652 return (md->md_paddr + ofs); 2653 else 2654 return (md->md_vaddr + ofs); 2655 } 2656 2657 struct pmap_md * 2658 moea_scan_md(mmu_t mmu, struct pmap_md *prev) 2659 { 2660 static struct pmap_md md; 2661 struct pvo_entry *pvo; 2662 vm_offset_t va; 2663 2664 if (dumpsys_minidump) { 2665 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2666 if (prev == NULL) { 2667 /* 1st: kernel .data and .bss. */ 2668 md.md_index = 1; 2669 md.md_vaddr = trunc_page((uintptr_t)_etext); 2670 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2671 return (&md); 2672 } 2673 switch (prev->md_index) { 2674 case 1: 2675 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2676 md.md_index = 2; 2677 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2678 md.md_size = round_page(msgbufp->msg_size); 2679 break; 2680 case 2: 2681 /* 3rd: kernel VM. */ 2682 va = prev->md_vaddr + prev->md_size; 2683 /* Find start of next chunk (from va). */ 2684 while (va < virtual_end) { 2685 /* Don't dump the buffer cache. */ 2686 if (va >= kmi.buffer_sva && 2687 va < kmi.buffer_eva) { 2688 va = kmi.buffer_eva; 2689 continue; 2690 } 2691 pvo = moea_pvo_find_va(kernel_pmap, 2692 va & ~ADDR_POFF, NULL); 2693 if (pvo != NULL && 2694 (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2695 break; 2696 va += PAGE_SIZE; 2697 } 2698 if (va < virtual_end) { 2699 md.md_vaddr = va; 2700 va += PAGE_SIZE; 2701 /* Find last page in chunk. */ 2702 while (va < virtual_end) { 2703 /* Don't run into the buffer cache. */ 2704 if (va == kmi.buffer_sva) 2705 break; 2706 pvo = moea_pvo_find_va(kernel_pmap, 2707 va & ~ADDR_POFF, NULL); 2708 if (pvo == NULL || 2709 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2710 break; 2711 va += PAGE_SIZE; 2712 } 2713 md.md_size = va - md.md_vaddr; 2714 break; 2715 } 2716 md.md_index = 3; 2717 /* FALLTHROUGH */ 2718 default: 2719 return (NULL); 2720 } 2721 } else { /* minidumps */ 2722 mem_regions(&pregions, &pregions_sz, 2723 ®ions, ®ions_sz); 2724 2725 if (prev == NULL) { 2726 /* first physical chunk. */ 2727 md.md_paddr = pregions[0].mr_start; 2728 md.md_size = pregions[0].mr_size; 2729 md.md_vaddr = ~0UL; 2730 md.md_index = 1; 2731 } else if (md.md_index < pregions_sz) { 2732 md.md_paddr = pregions[md.md_index].mr_start; 2733 md.md_size = pregions[md.md_index].mr_size; 2734 md.md_vaddr = ~0UL; 2735 md.md_index++; 2736 } else { 2737 /* There's no next physical chunk. */ 2738 return (NULL); 2739 } 2740 } 2741 2742 return (&md); 2743 } 2744