1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * Since the information managed by this module is also stored by the 100 * logical address mapping module, this module may throw away valid virtual 101 * to physical mappings at almost any time. However, invalidations of 102 * mappings must be done as requested. 103 * 104 * In order to cope with hardware architectures which make virtual to 105 * physical map invalidates expensive, this module may delay invalidate 106 * reduced protection operations until such time as they are actually 107 * necessary. This module is given full information as to which processors 108 * are currently using which maps, and to when physical maps must be made 109 * correct. 110 */ 111 112 #include "opt_kstack_pages.h" 113 114 #include <sys/param.h> 115 #include <sys/kernel.h> 116 #include <sys/queue.h> 117 #include <sys/cpuset.h> 118 #include <sys/ktr.h> 119 #include <sys/lock.h> 120 #include <sys/msgbuf.h> 121 #include <sys/mutex.h> 122 #include <sys/proc.h> 123 #include <sys/rwlock.h> 124 #include <sys/sched.h> 125 #include <sys/sysctl.h> 126 #include <sys/systm.h> 127 #include <sys/vmmeter.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #include <vm/vm.h> 132 #include <vm/vm_param.h> 133 #include <vm/vm_kern.h> 134 #include <vm/vm_page.h> 135 #include <vm/vm_map.h> 136 #include <vm/vm_object.h> 137 #include <vm/vm_extern.h> 138 #include <vm/vm_pageout.h> 139 #include <vm/uma.h> 140 141 #include <machine/cpu.h> 142 #include <machine/platform.h> 143 #include <machine/bat.h> 144 #include <machine/frame.h> 145 #include <machine/md_var.h> 146 #include <machine/psl.h> 147 #include <machine/pte.h> 148 #include <machine/smp.h> 149 #include <machine/sr.h> 150 #include <machine/mmuvar.h> 151 #include <machine/trap.h> 152 153 #include "mmu_if.h" 154 155 #define MOEA_DEBUG 156 157 #define TODO panic("%s: not implemented", __func__); 158 159 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 160 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 161 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 162 163 struct ofw_map { 164 vm_offset_t om_va; 165 vm_size_t om_len; 166 vm_offset_t om_pa; 167 u_int om_mode; 168 }; 169 170 extern unsigned char _etext[]; 171 extern unsigned char _end[]; 172 173 extern int dumpsys_minidump; 174 175 /* 176 * Map of physical memory regions. 177 */ 178 static struct mem_region *regions; 179 static struct mem_region *pregions; 180 static u_int phys_avail_count; 181 static int regions_sz, pregions_sz; 182 static struct ofw_map *translations; 183 184 /* 185 * Lock for the pteg and pvo tables. 186 */ 187 struct mtx moea_table_mutex; 188 struct mtx moea_vsid_mutex; 189 190 /* tlbie instruction synchronization */ 191 static struct mtx tlbie_mtx; 192 193 /* 194 * PTEG data. 195 */ 196 static struct pteg *moea_pteg_table; 197 u_int moea_pteg_count; 198 u_int moea_pteg_mask; 199 200 /* 201 * PVO data. 202 */ 203 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 204 struct pvo_head moea_pvo_kunmanaged = 205 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 206 207 static struct rwlock_padalign pvh_global_lock; 208 209 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 210 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 211 212 #define BPVO_POOL_SIZE 32768 213 static struct pvo_entry *moea_bpvo_pool; 214 static int moea_bpvo_pool_index = 0; 215 216 #define VSID_NBPW (sizeof(u_int32_t) * 8) 217 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 218 219 static boolean_t moea_initialized = FALSE; 220 221 /* 222 * Statistics. 223 */ 224 u_int moea_pte_valid = 0; 225 u_int moea_pte_overflow = 0; 226 u_int moea_pte_replacements = 0; 227 u_int moea_pvo_entries = 0; 228 u_int moea_pvo_enter_calls = 0; 229 u_int moea_pvo_remove_calls = 0; 230 u_int moea_pte_spills = 0; 231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 232 0, ""); 233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 234 &moea_pte_overflow, 0, ""); 235 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 236 &moea_pte_replacements, 0, ""); 237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 238 0, ""); 239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 240 &moea_pvo_enter_calls, 0, ""); 241 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 242 &moea_pvo_remove_calls, 0, ""); 243 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 244 &moea_pte_spills, 0, ""); 245 246 /* 247 * Allocate physical memory for use in moea_bootstrap. 248 */ 249 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 250 251 /* 252 * PTE calls. 253 */ 254 static int moea_pte_insert(u_int, struct pte *); 255 256 /* 257 * PVO calls. 258 */ 259 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 260 vm_offset_t, vm_offset_t, u_int, int); 261 static void moea_pvo_remove(struct pvo_entry *, int); 262 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 263 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 264 265 /* 266 * Utility routines. 267 */ 268 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 269 vm_prot_t, boolean_t); 270 static void moea_syncicache(vm_offset_t, vm_size_t); 271 static boolean_t moea_query_bit(vm_page_t, int); 272 static u_int moea_clear_bit(vm_page_t, int); 273 static void moea_kremove(mmu_t, vm_offset_t); 274 int moea_pte_spill(vm_offset_t); 275 276 /* 277 * Kernel MMU interface 278 */ 279 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 280 void moea_clear_modify(mmu_t, vm_page_t); 281 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 282 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 283 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 284 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 285 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 286 vm_prot_t); 287 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 288 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 289 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 290 void moea_init(mmu_t); 291 boolean_t moea_is_modified(mmu_t, vm_page_t); 292 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 293 boolean_t moea_is_referenced(mmu_t, vm_page_t); 294 int moea_ts_referenced(mmu_t, vm_page_t); 295 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 296 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297 int moea_page_wired_mappings(mmu_t, vm_page_t); 298 void moea_pinit(mmu_t, pmap_t); 299 void moea_pinit0(mmu_t, pmap_t); 300 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 301 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 302 void moea_qremove(mmu_t, vm_offset_t, int); 303 void moea_release(mmu_t, pmap_t); 304 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 305 void moea_remove_all(mmu_t, vm_page_t); 306 void moea_remove_write(mmu_t, vm_page_t); 307 void moea_zero_page(mmu_t, vm_page_t); 308 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 309 void moea_zero_page_idle(mmu_t, vm_page_t); 310 void moea_activate(mmu_t, struct thread *); 311 void moea_deactivate(mmu_t, struct thread *); 312 void moea_cpu_bootstrap(mmu_t, int); 313 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 314 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 315 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 316 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 317 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 318 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 319 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 320 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 321 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 322 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 323 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 324 vm_size_t *sz); 325 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev); 326 327 static mmu_method_t moea_methods[] = { 328 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 329 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 330 MMUMETHOD(mmu_copy_page, moea_copy_page), 331 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 332 MMUMETHOD(mmu_enter, moea_enter), 333 MMUMETHOD(mmu_enter_object, moea_enter_object), 334 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 335 MMUMETHOD(mmu_extract, moea_extract), 336 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 337 MMUMETHOD(mmu_init, moea_init), 338 MMUMETHOD(mmu_is_modified, moea_is_modified), 339 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 340 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 341 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 342 MMUMETHOD(mmu_map, moea_map), 343 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 344 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 345 MMUMETHOD(mmu_pinit, moea_pinit), 346 MMUMETHOD(mmu_pinit0, moea_pinit0), 347 MMUMETHOD(mmu_protect, moea_protect), 348 MMUMETHOD(mmu_qenter, moea_qenter), 349 MMUMETHOD(mmu_qremove, moea_qremove), 350 MMUMETHOD(mmu_release, moea_release), 351 MMUMETHOD(mmu_remove, moea_remove), 352 MMUMETHOD(mmu_remove_all, moea_remove_all), 353 MMUMETHOD(mmu_remove_write, moea_remove_write), 354 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 355 MMUMETHOD(mmu_zero_page, moea_zero_page), 356 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 357 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 358 MMUMETHOD(mmu_activate, moea_activate), 359 MMUMETHOD(mmu_deactivate, moea_deactivate), 360 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 361 362 /* Internal interfaces */ 363 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 364 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 365 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 366 MMUMETHOD(mmu_mapdev, moea_mapdev), 367 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 368 MMUMETHOD(mmu_kextract, moea_kextract), 369 MMUMETHOD(mmu_kenter, moea_kenter), 370 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 371 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 372 MMUMETHOD(mmu_scan_md, moea_scan_md), 373 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 374 375 { 0, 0 } 376 }; 377 378 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 379 380 static __inline uint32_t 381 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 382 { 383 uint32_t pte_lo; 384 int i; 385 386 if (ma != VM_MEMATTR_DEFAULT) { 387 switch (ma) { 388 case VM_MEMATTR_UNCACHEABLE: 389 return (PTE_I | PTE_G); 390 case VM_MEMATTR_WRITE_COMBINING: 391 case VM_MEMATTR_WRITE_BACK: 392 case VM_MEMATTR_PREFETCHABLE: 393 return (PTE_I); 394 case VM_MEMATTR_WRITE_THROUGH: 395 return (PTE_W | PTE_M); 396 } 397 } 398 399 /* 400 * Assume the page is cache inhibited and access is guarded unless 401 * it's in our available memory array. 402 */ 403 pte_lo = PTE_I | PTE_G; 404 for (i = 0; i < pregions_sz; i++) { 405 if ((pa >= pregions[i].mr_start) && 406 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 407 pte_lo = PTE_M; 408 break; 409 } 410 } 411 412 return pte_lo; 413 } 414 415 static void 416 tlbie(vm_offset_t va) 417 { 418 419 mtx_lock_spin(&tlbie_mtx); 420 __asm __volatile("ptesync"); 421 __asm __volatile("tlbie %0" :: "r"(va)); 422 __asm __volatile("eieio; tlbsync; ptesync"); 423 mtx_unlock_spin(&tlbie_mtx); 424 } 425 426 static void 427 tlbia(void) 428 { 429 vm_offset_t va; 430 431 for (va = 0; va < 0x00040000; va += 0x00001000) { 432 __asm __volatile("tlbie %0" :: "r"(va)); 433 powerpc_sync(); 434 } 435 __asm __volatile("tlbsync"); 436 powerpc_sync(); 437 } 438 439 static __inline int 440 va_to_sr(u_int *sr, vm_offset_t va) 441 { 442 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 443 } 444 445 static __inline u_int 446 va_to_pteg(u_int sr, vm_offset_t addr) 447 { 448 u_int hash; 449 450 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 451 ADDR_PIDX_SHFT); 452 return (hash & moea_pteg_mask); 453 } 454 455 static __inline struct pvo_head * 456 vm_page_to_pvoh(vm_page_t m) 457 { 458 459 return (&m->md.mdpg_pvoh); 460 } 461 462 static __inline void 463 moea_attr_clear(vm_page_t m, int ptebit) 464 { 465 466 rw_assert(&pvh_global_lock, RA_WLOCKED); 467 m->md.mdpg_attrs &= ~ptebit; 468 } 469 470 static __inline int 471 moea_attr_fetch(vm_page_t m) 472 { 473 474 return (m->md.mdpg_attrs); 475 } 476 477 static __inline void 478 moea_attr_save(vm_page_t m, int ptebit) 479 { 480 481 rw_assert(&pvh_global_lock, RA_WLOCKED); 482 m->md.mdpg_attrs |= ptebit; 483 } 484 485 static __inline int 486 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 487 { 488 if (pt->pte_hi == pvo_pt->pte_hi) 489 return (1); 490 491 return (0); 492 } 493 494 static __inline int 495 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 496 { 497 return (pt->pte_hi & ~PTE_VALID) == 498 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 499 ((va >> ADDR_API_SHFT) & PTE_API) | which); 500 } 501 502 static __inline void 503 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 504 { 505 506 mtx_assert(&moea_table_mutex, MA_OWNED); 507 508 /* 509 * Construct a PTE. Default to IMB initially. Valid bit only gets 510 * set when the real pte is set in memory. 511 * 512 * Note: Don't set the valid bit for correct operation of tlb update. 513 */ 514 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 515 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 516 pt->pte_lo = pte_lo; 517 } 518 519 static __inline void 520 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 521 { 522 523 mtx_assert(&moea_table_mutex, MA_OWNED); 524 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 525 } 526 527 static __inline void 528 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 529 { 530 531 mtx_assert(&moea_table_mutex, MA_OWNED); 532 533 /* 534 * As shown in Section 7.6.3.2.3 535 */ 536 pt->pte_lo &= ~ptebit; 537 tlbie(va); 538 } 539 540 static __inline void 541 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 542 { 543 544 mtx_assert(&moea_table_mutex, MA_OWNED); 545 pvo_pt->pte_hi |= PTE_VALID; 546 547 /* 548 * Update the PTE as defined in section 7.6.3.1. 549 * Note that the REF/CHG bits are from pvo_pt and thus should have 550 * been saved so this routine can restore them (if desired). 551 */ 552 pt->pte_lo = pvo_pt->pte_lo; 553 powerpc_sync(); 554 pt->pte_hi = pvo_pt->pte_hi; 555 powerpc_sync(); 556 moea_pte_valid++; 557 } 558 559 static __inline void 560 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 561 { 562 563 mtx_assert(&moea_table_mutex, MA_OWNED); 564 pvo_pt->pte_hi &= ~PTE_VALID; 565 566 /* 567 * Force the reg & chg bits back into the PTEs. 568 */ 569 powerpc_sync(); 570 571 /* 572 * Invalidate the pte. 573 */ 574 pt->pte_hi &= ~PTE_VALID; 575 576 tlbie(va); 577 578 /* 579 * Save the reg & chg bits. 580 */ 581 moea_pte_synch(pt, pvo_pt); 582 moea_pte_valid--; 583 } 584 585 static __inline void 586 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 587 { 588 589 /* 590 * Invalidate the PTE 591 */ 592 moea_pte_unset(pt, pvo_pt, va); 593 moea_pte_set(pt, pvo_pt); 594 } 595 596 /* 597 * Quick sort callout for comparing memory regions. 598 */ 599 static int om_cmp(const void *a, const void *b); 600 601 static int 602 om_cmp(const void *a, const void *b) 603 { 604 const struct ofw_map *mapa; 605 const struct ofw_map *mapb; 606 607 mapa = a; 608 mapb = b; 609 if (mapa->om_pa < mapb->om_pa) 610 return (-1); 611 else if (mapa->om_pa > mapb->om_pa) 612 return (1); 613 else 614 return (0); 615 } 616 617 void 618 moea_cpu_bootstrap(mmu_t mmup, int ap) 619 { 620 u_int sdr; 621 int i; 622 623 if (ap) { 624 powerpc_sync(); 625 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 626 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 627 isync(); 628 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 629 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 630 isync(); 631 } 632 633 #ifdef WII 634 /* 635 * Special case for the Wii: don't install the PCI BAT. 636 */ 637 if (strcmp(installed_platform(), "wii") != 0) { 638 #endif 639 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 640 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 641 #ifdef WII 642 } 643 #endif 644 isync(); 645 646 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 647 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 648 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 649 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 650 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 651 isync(); 652 653 for (i = 0; i < 16; i++) 654 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 655 powerpc_sync(); 656 657 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 658 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 659 isync(); 660 661 tlbia(); 662 } 663 664 void 665 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 666 { 667 ihandle_t mmui; 668 phandle_t chosen, mmu; 669 int sz; 670 int i, j; 671 vm_size_t size, physsz, hwphyssz; 672 vm_offset_t pa, va, off; 673 void *dpcpu; 674 register_t msr; 675 676 /* 677 * Set up BAT0 to map the lowest 256 MB area 678 */ 679 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 680 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 681 682 /* 683 * Map PCI memory space. 684 */ 685 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 686 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 687 688 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 689 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 690 691 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 692 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 693 694 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 695 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 696 697 /* 698 * Map obio devices. 699 */ 700 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 701 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 702 703 /* 704 * Use an IBAT and a DBAT to map the bottom segment of memory 705 * where we are. Turn off instruction relocation temporarily 706 * to prevent faults while reprogramming the IBAT. 707 */ 708 msr = mfmsr(); 709 mtmsr(msr & ~PSL_IR); 710 __asm (".balign 32; \n" 711 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 712 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 713 :: "r"(battable[0].batu), "r"(battable[0].batl)); 714 mtmsr(msr); 715 716 #ifdef WII 717 if (strcmp(installed_platform(), "wii") != 0) { 718 #endif 719 /* map pci space */ 720 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 721 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 722 #ifdef WII 723 } 724 #endif 725 isync(); 726 727 /* set global direct map flag */ 728 hw_direct_map = 1; 729 730 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 731 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 732 733 for (i = 0; i < pregions_sz; i++) { 734 vm_offset_t pa; 735 vm_offset_t end; 736 737 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 738 pregions[i].mr_start, 739 pregions[i].mr_start + pregions[i].mr_size, 740 pregions[i].mr_size); 741 /* 742 * Install entries into the BAT table to allow all 743 * of physmem to be convered by on-demand BAT entries. 744 * The loop will sometimes set the same battable element 745 * twice, but that's fine since they won't be used for 746 * a while yet. 747 */ 748 pa = pregions[i].mr_start & 0xf0000000; 749 end = pregions[i].mr_start + pregions[i].mr_size; 750 do { 751 u_int n = pa >> ADDR_SR_SHFT; 752 753 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 754 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 755 pa += SEGMENT_LENGTH; 756 } while (pa < end); 757 } 758 759 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 760 panic("moea_bootstrap: phys_avail too small"); 761 762 phys_avail_count = 0; 763 physsz = 0; 764 hwphyssz = 0; 765 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 766 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 767 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 768 regions[i].mr_start + regions[i].mr_size, 769 regions[i].mr_size); 770 if (hwphyssz != 0 && 771 (physsz + regions[i].mr_size) >= hwphyssz) { 772 if (physsz < hwphyssz) { 773 phys_avail[j] = regions[i].mr_start; 774 phys_avail[j + 1] = regions[i].mr_start + 775 hwphyssz - physsz; 776 physsz = hwphyssz; 777 phys_avail_count++; 778 } 779 break; 780 } 781 phys_avail[j] = regions[i].mr_start; 782 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 783 phys_avail_count++; 784 physsz += regions[i].mr_size; 785 } 786 787 /* Check for overlap with the kernel and exception vectors */ 788 for (j = 0; j < 2*phys_avail_count; j+=2) { 789 if (phys_avail[j] < EXC_LAST) 790 phys_avail[j] += EXC_LAST; 791 792 if (kernelstart >= phys_avail[j] && 793 kernelstart < phys_avail[j+1]) { 794 if (kernelend < phys_avail[j+1]) { 795 phys_avail[2*phys_avail_count] = 796 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 797 phys_avail[2*phys_avail_count + 1] = 798 phys_avail[j+1]; 799 phys_avail_count++; 800 } 801 802 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 803 } 804 805 if (kernelend >= phys_avail[j] && 806 kernelend < phys_avail[j+1]) { 807 if (kernelstart > phys_avail[j]) { 808 phys_avail[2*phys_avail_count] = phys_avail[j]; 809 phys_avail[2*phys_avail_count + 1] = 810 kernelstart & ~PAGE_MASK; 811 phys_avail_count++; 812 } 813 814 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 815 } 816 } 817 818 physmem = btoc(physsz); 819 820 /* 821 * Allocate PTEG table. 822 */ 823 #ifdef PTEGCOUNT 824 moea_pteg_count = PTEGCOUNT; 825 #else 826 moea_pteg_count = 0x1000; 827 828 while (moea_pteg_count < physmem) 829 moea_pteg_count <<= 1; 830 831 moea_pteg_count >>= 1; 832 #endif /* PTEGCOUNT */ 833 834 size = moea_pteg_count * sizeof(struct pteg); 835 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 836 size); 837 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 838 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 839 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 840 moea_pteg_mask = moea_pteg_count - 1; 841 842 /* 843 * Allocate pv/overflow lists. 844 */ 845 size = sizeof(struct pvo_head) * moea_pteg_count; 846 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 847 PAGE_SIZE); 848 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 849 for (i = 0; i < moea_pteg_count; i++) 850 LIST_INIT(&moea_pvo_table[i]); 851 852 /* 853 * Initialize the lock that synchronizes access to the pteg and pvo 854 * tables. 855 */ 856 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 857 MTX_RECURSE); 858 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 859 860 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 861 862 /* 863 * Initialise the unmanaged pvo pool. 864 */ 865 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 866 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 867 moea_bpvo_pool_index = 0; 868 869 /* 870 * Make sure kernel vsid is allocated as well as VSID 0. 871 */ 872 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 873 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 874 moea_vsid_bitmap[0] |= 1; 875 876 /* 877 * Initialize the kernel pmap (which is statically allocated). 878 */ 879 PMAP_LOCK_INIT(kernel_pmap); 880 for (i = 0; i < 16; i++) 881 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 882 CPU_FILL(&kernel_pmap->pm_active); 883 RB_INIT(&kernel_pmap->pmap_pvo); 884 885 /* 886 * Initialize the global pv list lock. 887 */ 888 rw_init(&pvh_global_lock, "pmap pv global"); 889 890 /* 891 * Set up the Open Firmware mappings 892 */ 893 chosen = OF_finddevice("/chosen"); 894 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 895 (mmu = OF_instance_to_package(mmui)) != -1 && 896 (sz = OF_getproplen(mmu, "translations")) != -1) { 897 translations = NULL; 898 for (i = 0; phys_avail[i] != 0; i += 2) { 899 if (phys_avail[i + 1] >= sz) { 900 translations = (struct ofw_map *)phys_avail[i]; 901 break; 902 } 903 } 904 if (translations == NULL) 905 panic("moea_bootstrap: no space to copy translations"); 906 bzero(translations, sz); 907 if (OF_getprop(mmu, "translations", translations, sz) == -1) 908 panic("moea_bootstrap: can't get ofw translations"); 909 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 910 sz /= sizeof(*translations); 911 qsort(translations, sz, sizeof (*translations), om_cmp); 912 for (i = 0; i < sz; i++) { 913 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 914 translations[i].om_pa, translations[i].om_va, 915 translations[i].om_len); 916 917 /* 918 * If the mapping is 1:1, let the RAM and device 919 * on-demand BAT tables take care of the translation. 920 */ 921 if (translations[i].om_va == translations[i].om_pa) 922 continue; 923 924 /* Enter the pages */ 925 for (off = 0; off < translations[i].om_len; 926 off += PAGE_SIZE) 927 moea_kenter(mmup, translations[i].om_va + off, 928 translations[i].om_pa + off); 929 } 930 } 931 932 /* 933 * Calculate the last available physical address. 934 */ 935 for (i = 0; phys_avail[i + 2] != 0; i += 2) 936 ; 937 Maxmem = powerpc_btop(phys_avail[i + 1]); 938 939 moea_cpu_bootstrap(mmup,0); 940 941 pmap_bootstrapped++; 942 943 /* 944 * Set the start and end of kva. 945 */ 946 virtual_avail = VM_MIN_KERNEL_ADDRESS; 947 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 948 949 /* 950 * Allocate a kernel stack with a guard page for thread0 and map it 951 * into the kernel page map. 952 */ 953 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 954 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 955 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 956 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 957 thread0.td_kstack = va; 958 thread0.td_kstack_pages = KSTACK_PAGES; 959 for (i = 0; i < KSTACK_PAGES; i++) { 960 moea_kenter(mmup, va, pa); 961 pa += PAGE_SIZE; 962 va += PAGE_SIZE; 963 } 964 965 /* 966 * Allocate virtual address space for the message buffer. 967 */ 968 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 969 msgbufp = (struct msgbuf *)virtual_avail; 970 va = virtual_avail; 971 virtual_avail += round_page(msgbufsize); 972 while (va < virtual_avail) { 973 moea_kenter(mmup, va, pa); 974 pa += PAGE_SIZE; 975 va += PAGE_SIZE; 976 } 977 978 /* 979 * Allocate virtual address space for the dynamic percpu area. 980 */ 981 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 982 dpcpu = (void *)virtual_avail; 983 va = virtual_avail; 984 virtual_avail += DPCPU_SIZE; 985 while (va < virtual_avail) { 986 moea_kenter(mmup, va, pa); 987 pa += PAGE_SIZE; 988 va += PAGE_SIZE; 989 } 990 dpcpu_init(dpcpu, 0); 991 } 992 993 /* 994 * Activate a user pmap. The pmap must be activated before it's address 995 * space can be accessed in any way. 996 */ 997 void 998 moea_activate(mmu_t mmu, struct thread *td) 999 { 1000 pmap_t pm, pmr; 1001 1002 /* 1003 * Load all the data we need up front to encourage the compiler to 1004 * not issue any loads while we have interrupts disabled below. 1005 */ 1006 pm = &td->td_proc->p_vmspace->vm_pmap; 1007 pmr = pm->pmap_phys; 1008 1009 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1010 PCPU_SET(curpmap, pmr); 1011 } 1012 1013 void 1014 moea_deactivate(mmu_t mmu, struct thread *td) 1015 { 1016 pmap_t pm; 1017 1018 pm = &td->td_proc->p_vmspace->vm_pmap; 1019 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1020 PCPU_SET(curpmap, NULL); 1021 } 1022 1023 void 1024 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1025 { 1026 struct pvo_entry *pvo; 1027 1028 PMAP_LOCK(pm); 1029 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1030 1031 if (pvo != NULL) { 1032 if (wired) { 1033 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1034 pm->pm_stats.wired_count++; 1035 pvo->pvo_vaddr |= PVO_WIRED; 1036 } else { 1037 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1038 pm->pm_stats.wired_count--; 1039 pvo->pvo_vaddr &= ~PVO_WIRED; 1040 } 1041 } 1042 PMAP_UNLOCK(pm); 1043 } 1044 1045 void 1046 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1047 { 1048 vm_offset_t dst; 1049 vm_offset_t src; 1050 1051 dst = VM_PAGE_TO_PHYS(mdst); 1052 src = VM_PAGE_TO_PHYS(msrc); 1053 1054 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1055 } 1056 1057 void 1058 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1059 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1060 { 1061 void *a_cp, *b_cp; 1062 vm_offset_t a_pg_offset, b_pg_offset; 1063 int cnt; 1064 1065 while (xfersize > 0) { 1066 a_pg_offset = a_offset & PAGE_MASK; 1067 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1068 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1069 a_pg_offset; 1070 b_pg_offset = b_offset & PAGE_MASK; 1071 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1072 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1073 b_pg_offset; 1074 bcopy(a_cp, b_cp, cnt); 1075 a_offset += cnt; 1076 b_offset += cnt; 1077 xfersize -= cnt; 1078 } 1079 } 1080 1081 /* 1082 * Zero a page of physical memory by temporarily mapping it into the tlb. 1083 */ 1084 void 1085 moea_zero_page(mmu_t mmu, vm_page_t m) 1086 { 1087 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1088 1089 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1090 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1091 } 1092 1093 void 1094 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1095 { 1096 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1097 void *va = (void *)(pa + off); 1098 1099 bzero(va, size); 1100 } 1101 1102 void 1103 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1104 { 1105 1106 moea_zero_page(mmu, m); 1107 } 1108 1109 /* 1110 * Map the given physical page at the specified virtual address in the 1111 * target pmap with the protection requested. If specified the page 1112 * will be wired down. 1113 */ 1114 void 1115 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1116 boolean_t wired) 1117 { 1118 1119 rw_wlock(&pvh_global_lock); 1120 PMAP_LOCK(pmap); 1121 moea_enter_locked(pmap, va, m, prot, wired); 1122 rw_wunlock(&pvh_global_lock); 1123 PMAP_UNLOCK(pmap); 1124 } 1125 1126 /* 1127 * Map the given physical page at the specified virtual address in the 1128 * target pmap with the protection requested. If specified the page 1129 * will be wired down. 1130 * 1131 * The page queues and pmap must be locked. 1132 */ 1133 static void 1134 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1135 boolean_t wired) 1136 { 1137 struct pvo_head *pvo_head; 1138 uma_zone_t zone; 1139 vm_page_t pg; 1140 u_int pte_lo, pvo_flags; 1141 int error; 1142 1143 if (!moea_initialized) { 1144 pvo_head = &moea_pvo_kunmanaged; 1145 zone = moea_upvo_zone; 1146 pvo_flags = 0; 1147 pg = NULL; 1148 } else { 1149 pvo_head = vm_page_to_pvoh(m); 1150 pg = m; 1151 zone = moea_mpvo_zone; 1152 pvo_flags = PVO_MANAGED; 1153 } 1154 if (pmap_bootstrapped) 1155 rw_assert(&pvh_global_lock, RA_WLOCKED); 1156 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1157 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1158 VM_OBJECT_ASSERT_LOCKED(m->object); 1159 1160 /* XXX change the pvo head for fake pages */ 1161 if ((m->oflags & VPO_UNMANAGED) != 0) { 1162 pvo_flags &= ~PVO_MANAGED; 1163 pvo_head = &moea_pvo_kunmanaged; 1164 zone = moea_upvo_zone; 1165 } 1166 1167 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1168 1169 if (prot & VM_PROT_WRITE) { 1170 pte_lo |= PTE_BW; 1171 if (pmap_bootstrapped && 1172 (m->oflags & VPO_UNMANAGED) == 0) 1173 vm_page_aflag_set(m, PGA_WRITEABLE); 1174 } else 1175 pte_lo |= PTE_BR; 1176 1177 if (prot & VM_PROT_EXECUTE) 1178 pvo_flags |= PVO_EXECUTABLE; 1179 1180 if (wired) 1181 pvo_flags |= PVO_WIRED; 1182 1183 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1184 pte_lo, pvo_flags); 1185 1186 /* 1187 * Flush the real page from the instruction cache. This has be done 1188 * for all user mappings to prevent information leakage via the 1189 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1190 * mapping for a page. 1191 */ 1192 if (pmap != kernel_pmap && error == ENOENT && 1193 (pte_lo & (PTE_I | PTE_G)) == 0) 1194 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1195 } 1196 1197 /* 1198 * Maps a sequence of resident pages belonging to the same object. 1199 * The sequence begins with the given page m_start. This page is 1200 * mapped at the given virtual address start. Each subsequent page is 1201 * mapped at a virtual address that is offset from start by the same 1202 * amount as the page is offset from m_start within the object. The 1203 * last page in the sequence is the page with the largest offset from 1204 * m_start that can be mapped at a virtual address less than the given 1205 * virtual address end. Not every virtual page between start and end 1206 * is mapped; only those for which a resident page exists with the 1207 * corresponding offset from m_start are mapped. 1208 */ 1209 void 1210 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1211 vm_page_t m_start, vm_prot_t prot) 1212 { 1213 vm_page_t m; 1214 vm_pindex_t diff, psize; 1215 1216 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1217 1218 psize = atop(end - start); 1219 m = m_start; 1220 rw_wlock(&pvh_global_lock); 1221 PMAP_LOCK(pm); 1222 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1223 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1224 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1225 m = TAILQ_NEXT(m, listq); 1226 } 1227 rw_wunlock(&pvh_global_lock); 1228 PMAP_UNLOCK(pm); 1229 } 1230 1231 void 1232 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1233 vm_prot_t prot) 1234 { 1235 1236 rw_wlock(&pvh_global_lock); 1237 PMAP_LOCK(pm); 1238 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1239 FALSE); 1240 rw_wunlock(&pvh_global_lock); 1241 PMAP_UNLOCK(pm); 1242 } 1243 1244 vm_paddr_t 1245 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1246 { 1247 struct pvo_entry *pvo; 1248 vm_paddr_t pa; 1249 1250 PMAP_LOCK(pm); 1251 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1252 if (pvo == NULL) 1253 pa = 0; 1254 else 1255 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1256 PMAP_UNLOCK(pm); 1257 return (pa); 1258 } 1259 1260 /* 1261 * Atomically extract and hold the physical page with the given 1262 * pmap and virtual address pair if that mapping permits the given 1263 * protection. 1264 */ 1265 vm_page_t 1266 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1267 { 1268 struct pvo_entry *pvo; 1269 vm_page_t m; 1270 vm_paddr_t pa; 1271 1272 m = NULL; 1273 pa = 0; 1274 PMAP_LOCK(pmap); 1275 retry: 1276 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1277 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1278 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1279 (prot & VM_PROT_WRITE) == 0)) { 1280 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1281 goto retry; 1282 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1283 vm_page_hold(m); 1284 } 1285 PA_UNLOCK_COND(pa); 1286 PMAP_UNLOCK(pmap); 1287 return (m); 1288 } 1289 1290 void 1291 moea_init(mmu_t mmu) 1292 { 1293 1294 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1295 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1296 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1297 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1298 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1299 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1300 moea_initialized = TRUE; 1301 } 1302 1303 boolean_t 1304 moea_is_referenced(mmu_t mmu, vm_page_t m) 1305 { 1306 boolean_t rv; 1307 1308 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1309 ("moea_is_referenced: page %p is not managed", m)); 1310 rw_wlock(&pvh_global_lock); 1311 rv = moea_query_bit(m, PTE_REF); 1312 rw_wunlock(&pvh_global_lock); 1313 return (rv); 1314 } 1315 1316 boolean_t 1317 moea_is_modified(mmu_t mmu, vm_page_t m) 1318 { 1319 boolean_t rv; 1320 1321 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1322 ("moea_is_modified: page %p is not managed", m)); 1323 1324 /* 1325 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1326 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1327 * is clear, no PTEs can have PTE_CHG set. 1328 */ 1329 VM_OBJECT_ASSERT_WLOCKED(m->object); 1330 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1331 return (FALSE); 1332 rw_wlock(&pvh_global_lock); 1333 rv = moea_query_bit(m, PTE_CHG); 1334 rw_wunlock(&pvh_global_lock); 1335 return (rv); 1336 } 1337 1338 boolean_t 1339 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1340 { 1341 struct pvo_entry *pvo; 1342 boolean_t rv; 1343 1344 PMAP_LOCK(pmap); 1345 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1346 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1347 PMAP_UNLOCK(pmap); 1348 return (rv); 1349 } 1350 1351 void 1352 moea_clear_modify(mmu_t mmu, vm_page_t m) 1353 { 1354 1355 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1356 ("moea_clear_modify: page %p is not managed", m)); 1357 VM_OBJECT_ASSERT_WLOCKED(m->object); 1358 KASSERT(!vm_page_xbusied(m), 1359 ("moea_clear_modify: page %p is exclusive busy", m)); 1360 1361 /* 1362 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1363 * set. If the object containing the page is locked and the page is 1364 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1365 */ 1366 if ((m->aflags & PGA_WRITEABLE) == 0) 1367 return; 1368 rw_wlock(&pvh_global_lock); 1369 moea_clear_bit(m, PTE_CHG); 1370 rw_wunlock(&pvh_global_lock); 1371 } 1372 1373 /* 1374 * Clear the write and modified bits in each of the given page's mappings. 1375 */ 1376 void 1377 moea_remove_write(mmu_t mmu, vm_page_t m) 1378 { 1379 struct pvo_entry *pvo; 1380 struct pte *pt; 1381 pmap_t pmap; 1382 u_int lo; 1383 1384 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1385 ("moea_remove_write: page %p is not managed", m)); 1386 1387 /* 1388 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1389 * set by another thread while the object is locked. Thus, 1390 * if PGA_WRITEABLE is clear, no page table entries need updating. 1391 */ 1392 VM_OBJECT_ASSERT_WLOCKED(m->object); 1393 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1394 return; 1395 rw_wlock(&pvh_global_lock); 1396 lo = moea_attr_fetch(m); 1397 powerpc_sync(); 1398 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1399 pmap = pvo->pvo_pmap; 1400 PMAP_LOCK(pmap); 1401 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1402 pt = moea_pvo_to_pte(pvo, -1); 1403 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1404 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1405 if (pt != NULL) { 1406 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1407 lo |= pvo->pvo_pte.pte.pte_lo; 1408 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1409 moea_pte_change(pt, &pvo->pvo_pte.pte, 1410 pvo->pvo_vaddr); 1411 mtx_unlock(&moea_table_mutex); 1412 } 1413 } 1414 PMAP_UNLOCK(pmap); 1415 } 1416 if ((lo & PTE_CHG) != 0) { 1417 moea_attr_clear(m, PTE_CHG); 1418 vm_page_dirty(m); 1419 } 1420 vm_page_aflag_clear(m, PGA_WRITEABLE); 1421 rw_wunlock(&pvh_global_lock); 1422 } 1423 1424 /* 1425 * moea_ts_referenced: 1426 * 1427 * Return a count of reference bits for a page, clearing those bits. 1428 * It is not necessary for every reference bit to be cleared, but it 1429 * is necessary that 0 only be returned when there are truly no 1430 * reference bits set. 1431 * 1432 * XXX: The exact number of bits to check and clear is a matter that 1433 * should be tested and standardized at some point in the future for 1434 * optimal aging of shared pages. 1435 */ 1436 int 1437 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1438 { 1439 int count; 1440 1441 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1442 ("moea_ts_referenced: page %p is not managed", m)); 1443 rw_wlock(&pvh_global_lock); 1444 count = moea_clear_bit(m, PTE_REF); 1445 rw_wunlock(&pvh_global_lock); 1446 return (count); 1447 } 1448 1449 /* 1450 * Modify the WIMG settings of all mappings for a page. 1451 */ 1452 void 1453 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1454 { 1455 struct pvo_entry *pvo; 1456 struct pvo_head *pvo_head; 1457 struct pte *pt; 1458 pmap_t pmap; 1459 u_int lo; 1460 1461 if ((m->oflags & VPO_UNMANAGED) != 0) { 1462 m->md.mdpg_cache_attrs = ma; 1463 return; 1464 } 1465 1466 rw_wlock(&pvh_global_lock); 1467 pvo_head = vm_page_to_pvoh(m); 1468 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1469 1470 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1471 pmap = pvo->pvo_pmap; 1472 PMAP_LOCK(pmap); 1473 pt = moea_pvo_to_pte(pvo, -1); 1474 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1475 pvo->pvo_pte.pte.pte_lo |= lo; 1476 if (pt != NULL) { 1477 moea_pte_change(pt, &pvo->pvo_pte.pte, 1478 pvo->pvo_vaddr); 1479 if (pvo->pvo_pmap == kernel_pmap) 1480 isync(); 1481 } 1482 mtx_unlock(&moea_table_mutex); 1483 PMAP_UNLOCK(pmap); 1484 } 1485 m->md.mdpg_cache_attrs = ma; 1486 rw_wunlock(&pvh_global_lock); 1487 } 1488 1489 /* 1490 * Map a wired page into kernel virtual address space. 1491 */ 1492 void 1493 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1494 { 1495 1496 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1497 } 1498 1499 void 1500 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1501 { 1502 u_int pte_lo; 1503 int error; 1504 1505 #if 0 1506 if (va < VM_MIN_KERNEL_ADDRESS) 1507 panic("moea_kenter: attempt to enter non-kernel address %#x", 1508 va); 1509 #endif 1510 1511 pte_lo = moea_calc_wimg(pa, ma); 1512 1513 PMAP_LOCK(kernel_pmap); 1514 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1515 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1516 1517 if (error != 0 && error != ENOENT) 1518 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1519 pa, error); 1520 1521 PMAP_UNLOCK(kernel_pmap); 1522 } 1523 1524 /* 1525 * Extract the physical page address associated with the given kernel virtual 1526 * address. 1527 */ 1528 vm_paddr_t 1529 moea_kextract(mmu_t mmu, vm_offset_t va) 1530 { 1531 struct pvo_entry *pvo; 1532 vm_paddr_t pa; 1533 1534 /* 1535 * Allow direct mappings on 32-bit OEA 1536 */ 1537 if (va < VM_MIN_KERNEL_ADDRESS) { 1538 return (va); 1539 } 1540 1541 PMAP_LOCK(kernel_pmap); 1542 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1543 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1544 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1545 PMAP_UNLOCK(kernel_pmap); 1546 return (pa); 1547 } 1548 1549 /* 1550 * Remove a wired page from kernel virtual address space. 1551 */ 1552 void 1553 moea_kremove(mmu_t mmu, vm_offset_t va) 1554 { 1555 1556 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1557 } 1558 1559 /* 1560 * Map a range of physical addresses into kernel virtual address space. 1561 * 1562 * The value passed in *virt is a suggested virtual address for the mapping. 1563 * Architectures which can support a direct-mapped physical to virtual region 1564 * can return the appropriate address within that region, leaving '*virt' 1565 * unchanged. We cannot and therefore do not; *virt is updated with the 1566 * first usable address after the mapped region. 1567 */ 1568 vm_offset_t 1569 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1570 vm_paddr_t pa_end, int prot) 1571 { 1572 vm_offset_t sva, va; 1573 1574 sva = *virt; 1575 va = sva; 1576 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1577 moea_kenter(mmu, va, pa_start); 1578 *virt = va; 1579 return (sva); 1580 } 1581 1582 /* 1583 * Returns true if the pmap's pv is one of the first 1584 * 16 pvs linked to from this page. This count may 1585 * be changed upwards or downwards in the future; it 1586 * is only necessary that true be returned for a small 1587 * subset of pmaps for proper page aging. 1588 */ 1589 boolean_t 1590 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1591 { 1592 int loops; 1593 struct pvo_entry *pvo; 1594 boolean_t rv; 1595 1596 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1597 ("moea_page_exists_quick: page %p is not managed", m)); 1598 loops = 0; 1599 rv = FALSE; 1600 rw_wlock(&pvh_global_lock); 1601 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1602 if (pvo->pvo_pmap == pmap) { 1603 rv = TRUE; 1604 break; 1605 } 1606 if (++loops >= 16) 1607 break; 1608 } 1609 rw_wunlock(&pvh_global_lock); 1610 return (rv); 1611 } 1612 1613 /* 1614 * Return the number of managed mappings to the given physical page 1615 * that are wired. 1616 */ 1617 int 1618 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1619 { 1620 struct pvo_entry *pvo; 1621 int count; 1622 1623 count = 0; 1624 if ((m->oflags & VPO_UNMANAGED) != 0) 1625 return (count); 1626 rw_wlock(&pvh_global_lock); 1627 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1628 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1629 count++; 1630 rw_wunlock(&pvh_global_lock); 1631 return (count); 1632 } 1633 1634 static u_int moea_vsidcontext; 1635 1636 void 1637 moea_pinit(mmu_t mmu, pmap_t pmap) 1638 { 1639 int i, mask; 1640 u_int entropy; 1641 1642 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1643 RB_INIT(&pmap->pmap_pvo); 1644 1645 entropy = 0; 1646 __asm __volatile("mftb %0" : "=r"(entropy)); 1647 1648 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1649 == NULL) { 1650 pmap->pmap_phys = pmap; 1651 } 1652 1653 1654 mtx_lock(&moea_vsid_mutex); 1655 /* 1656 * Allocate some segment registers for this pmap. 1657 */ 1658 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1659 u_int hash, n; 1660 1661 /* 1662 * Create a new value by mutiplying by a prime and adding in 1663 * entropy from the timebase register. This is to make the 1664 * VSID more random so that the PT hash function collides 1665 * less often. (Note that the prime casues gcc to do shifts 1666 * instead of a multiply.) 1667 */ 1668 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1669 hash = moea_vsidcontext & (NPMAPS - 1); 1670 if (hash == 0) /* 0 is special, avoid it */ 1671 continue; 1672 n = hash >> 5; 1673 mask = 1 << (hash & (VSID_NBPW - 1)); 1674 hash = (moea_vsidcontext & 0xfffff); 1675 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1676 /* anything free in this bucket? */ 1677 if (moea_vsid_bitmap[n] == 0xffffffff) { 1678 entropy = (moea_vsidcontext >> 20); 1679 continue; 1680 } 1681 i = ffs(~moea_vsid_bitmap[n]) - 1; 1682 mask = 1 << i; 1683 hash &= 0xfffff & ~(VSID_NBPW - 1); 1684 hash |= i; 1685 } 1686 KASSERT(!(moea_vsid_bitmap[n] & mask), 1687 ("Allocating in-use VSID group %#x\n", hash)); 1688 moea_vsid_bitmap[n] |= mask; 1689 for (i = 0; i < 16; i++) 1690 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1691 mtx_unlock(&moea_vsid_mutex); 1692 return; 1693 } 1694 1695 mtx_unlock(&moea_vsid_mutex); 1696 panic("moea_pinit: out of segments"); 1697 } 1698 1699 /* 1700 * Initialize the pmap associated with process 0. 1701 */ 1702 void 1703 moea_pinit0(mmu_t mmu, pmap_t pm) 1704 { 1705 1706 PMAP_LOCK_INIT(pm); 1707 moea_pinit(mmu, pm); 1708 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1709 } 1710 1711 /* 1712 * Set the physical protection on the specified range of this map as requested. 1713 */ 1714 void 1715 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1716 vm_prot_t prot) 1717 { 1718 struct pvo_entry *pvo, *tpvo, key; 1719 struct pte *pt; 1720 1721 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1722 ("moea_protect: non current pmap")); 1723 1724 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1725 moea_remove(mmu, pm, sva, eva); 1726 return; 1727 } 1728 1729 rw_wlock(&pvh_global_lock); 1730 PMAP_LOCK(pm); 1731 key.pvo_vaddr = sva; 1732 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1733 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1734 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1735 if ((prot & VM_PROT_EXECUTE) == 0) 1736 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1737 1738 /* 1739 * Grab the PTE pointer before we diddle with the cached PTE 1740 * copy. 1741 */ 1742 pt = moea_pvo_to_pte(pvo, -1); 1743 /* 1744 * Change the protection of the page. 1745 */ 1746 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1747 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1748 1749 /* 1750 * If the PVO is in the page table, update that pte as well. 1751 */ 1752 if (pt != NULL) { 1753 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1754 mtx_unlock(&moea_table_mutex); 1755 } 1756 } 1757 rw_wunlock(&pvh_global_lock); 1758 PMAP_UNLOCK(pm); 1759 } 1760 1761 /* 1762 * Map a list of wired pages into kernel virtual address space. This is 1763 * intended for temporary mappings which do not need page modification or 1764 * references recorded. Existing mappings in the region are overwritten. 1765 */ 1766 void 1767 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1768 { 1769 vm_offset_t va; 1770 1771 va = sva; 1772 while (count-- > 0) { 1773 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1774 va += PAGE_SIZE; 1775 m++; 1776 } 1777 } 1778 1779 /* 1780 * Remove page mappings from kernel virtual address space. Intended for 1781 * temporary mappings entered by moea_qenter. 1782 */ 1783 void 1784 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1785 { 1786 vm_offset_t va; 1787 1788 va = sva; 1789 while (count-- > 0) { 1790 moea_kremove(mmu, va); 1791 va += PAGE_SIZE; 1792 } 1793 } 1794 1795 void 1796 moea_release(mmu_t mmu, pmap_t pmap) 1797 { 1798 int idx, mask; 1799 1800 /* 1801 * Free segment register's VSID 1802 */ 1803 if (pmap->pm_sr[0] == 0) 1804 panic("moea_release"); 1805 1806 mtx_lock(&moea_vsid_mutex); 1807 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1808 mask = 1 << (idx % VSID_NBPW); 1809 idx /= VSID_NBPW; 1810 moea_vsid_bitmap[idx] &= ~mask; 1811 mtx_unlock(&moea_vsid_mutex); 1812 } 1813 1814 /* 1815 * Remove the given range of addresses from the specified map. 1816 */ 1817 void 1818 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1819 { 1820 struct pvo_entry *pvo, *tpvo, key; 1821 1822 rw_wlock(&pvh_global_lock); 1823 PMAP_LOCK(pm); 1824 key.pvo_vaddr = sva; 1825 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1826 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1827 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1828 moea_pvo_remove(pvo, -1); 1829 } 1830 PMAP_UNLOCK(pm); 1831 rw_wunlock(&pvh_global_lock); 1832 } 1833 1834 /* 1835 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1836 * will reflect changes in pte's back to the vm_page. 1837 */ 1838 void 1839 moea_remove_all(mmu_t mmu, vm_page_t m) 1840 { 1841 struct pvo_head *pvo_head; 1842 struct pvo_entry *pvo, *next_pvo; 1843 pmap_t pmap; 1844 1845 rw_wlock(&pvh_global_lock); 1846 pvo_head = vm_page_to_pvoh(m); 1847 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1848 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1849 1850 pmap = pvo->pvo_pmap; 1851 PMAP_LOCK(pmap); 1852 moea_pvo_remove(pvo, -1); 1853 PMAP_UNLOCK(pmap); 1854 } 1855 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1856 moea_attr_clear(m, PTE_CHG); 1857 vm_page_dirty(m); 1858 } 1859 vm_page_aflag_clear(m, PGA_WRITEABLE); 1860 rw_wunlock(&pvh_global_lock); 1861 } 1862 1863 /* 1864 * Allocate a physical page of memory directly from the phys_avail map. 1865 * Can only be called from moea_bootstrap before avail start and end are 1866 * calculated. 1867 */ 1868 static vm_offset_t 1869 moea_bootstrap_alloc(vm_size_t size, u_int align) 1870 { 1871 vm_offset_t s, e; 1872 int i, j; 1873 1874 size = round_page(size); 1875 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1876 if (align != 0) 1877 s = (phys_avail[i] + align - 1) & ~(align - 1); 1878 else 1879 s = phys_avail[i]; 1880 e = s + size; 1881 1882 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1883 continue; 1884 1885 if (s == phys_avail[i]) { 1886 phys_avail[i] += size; 1887 } else if (e == phys_avail[i + 1]) { 1888 phys_avail[i + 1] -= size; 1889 } else { 1890 for (j = phys_avail_count * 2; j > i; j -= 2) { 1891 phys_avail[j] = phys_avail[j - 2]; 1892 phys_avail[j + 1] = phys_avail[j - 1]; 1893 } 1894 1895 phys_avail[i + 3] = phys_avail[i + 1]; 1896 phys_avail[i + 1] = s; 1897 phys_avail[i + 2] = e; 1898 phys_avail_count++; 1899 } 1900 1901 return (s); 1902 } 1903 panic("moea_bootstrap_alloc: could not allocate memory"); 1904 } 1905 1906 static void 1907 moea_syncicache(vm_offset_t pa, vm_size_t len) 1908 { 1909 __syncicache((void *)pa, len); 1910 } 1911 1912 static int 1913 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1914 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1915 { 1916 struct pvo_entry *pvo; 1917 u_int sr; 1918 int first; 1919 u_int ptegidx; 1920 int i; 1921 int bootstrap; 1922 1923 moea_pvo_enter_calls++; 1924 first = 0; 1925 bootstrap = 0; 1926 1927 /* 1928 * Compute the PTE Group index. 1929 */ 1930 va &= ~ADDR_POFF; 1931 sr = va_to_sr(pm->pm_sr, va); 1932 ptegidx = va_to_pteg(sr, va); 1933 1934 /* 1935 * Remove any existing mapping for this page. Reuse the pvo entry if 1936 * there is a mapping. 1937 */ 1938 mtx_lock(&moea_table_mutex); 1939 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1940 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1941 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1942 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1943 (pte_lo & PTE_PP)) { 1944 mtx_unlock(&moea_table_mutex); 1945 return (0); 1946 } 1947 moea_pvo_remove(pvo, -1); 1948 break; 1949 } 1950 } 1951 1952 /* 1953 * If we aren't overwriting a mapping, try to allocate. 1954 */ 1955 if (moea_initialized) { 1956 pvo = uma_zalloc(zone, M_NOWAIT); 1957 } else { 1958 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1959 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1960 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1961 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1962 } 1963 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1964 moea_bpvo_pool_index++; 1965 bootstrap = 1; 1966 } 1967 1968 if (pvo == NULL) { 1969 mtx_unlock(&moea_table_mutex); 1970 return (ENOMEM); 1971 } 1972 1973 moea_pvo_entries++; 1974 pvo->pvo_vaddr = va; 1975 pvo->pvo_pmap = pm; 1976 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1977 pvo->pvo_vaddr &= ~ADDR_POFF; 1978 if (flags & VM_PROT_EXECUTE) 1979 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1980 if (flags & PVO_WIRED) 1981 pvo->pvo_vaddr |= PVO_WIRED; 1982 if (pvo_head != &moea_pvo_kunmanaged) 1983 pvo->pvo_vaddr |= PVO_MANAGED; 1984 if (bootstrap) 1985 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1986 1987 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1988 1989 /* 1990 * Add to pmap list 1991 */ 1992 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1993 1994 /* 1995 * Remember if the list was empty and therefore will be the first 1996 * item. 1997 */ 1998 if (LIST_FIRST(pvo_head) == NULL) 1999 first = 1; 2000 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2001 2002 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2003 pm->pm_stats.wired_count++; 2004 pm->pm_stats.resident_count++; 2005 2006 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2007 KASSERT(i < 8, ("Invalid PTE index")); 2008 if (i >= 0) { 2009 PVO_PTEGIDX_SET(pvo, i); 2010 } else { 2011 panic("moea_pvo_enter: overflow"); 2012 moea_pte_overflow++; 2013 } 2014 mtx_unlock(&moea_table_mutex); 2015 2016 return (first ? ENOENT : 0); 2017 } 2018 2019 static void 2020 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2021 { 2022 struct pte *pt; 2023 2024 /* 2025 * If there is an active pte entry, we need to deactivate it (and 2026 * save the ref & cfg bits). 2027 */ 2028 pt = moea_pvo_to_pte(pvo, pteidx); 2029 if (pt != NULL) { 2030 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2031 mtx_unlock(&moea_table_mutex); 2032 PVO_PTEGIDX_CLR(pvo); 2033 } else { 2034 moea_pte_overflow--; 2035 } 2036 2037 /* 2038 * Update our statistics. 2039 */ 2040 pvo->pvo_pmap->pm_stats.resident_count--; 2041 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2042 pvo->pvo_pmap->pm_stats.wired_count--; 2043 2044 /* 2045 * Save the REF/CHG bits into their cache if the page is managed. 2046 */ 2047 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2048 struct vm_page *pg; 2049 2050 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2051 if (pg != NULL) { 2052 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2053 (PTE_REF | PTE_CHG)); 2054 } 2055 } 2056 2057 /* 2058 * Remove this PVO from the PV and pmap lists. 2059 */ 2060 LIST_REMOVE(pvo, pvo_vlink); 2061 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2062 2063 /* 2064 * Remove this from the overflow list and return it to the pool 2065 * if we aren't going to reuse it. 2066 */ 2067 LIST_REMOVE(pvo, pvo_olink); 2068 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2069 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2070 moea_upvo_zone, pvo); 2071 moea_pvo_entries--; 2072 moea_pvo_remove_calls++; 2073 } 2074 2075 static __inline int 2076 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2077 { 2078 int pteidx; 2079 2080 /* 2081 * We can find the actual pte entry without searching by grabbing 2082 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2083 * noticing the HID bit. 2084 */ 2085 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2086 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2087 pteidx ^= moea_pteg_mask * 8; 2088 2089 return (pteidx); 2090 } 2091 2092 static struct pvo_entry * 2093 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2094 { 2095 struct pvo_entry *pvo; 2096 int ptegidx; 2097 u_int sr; 2098 2099 va &= ~ADDR_POFF; 2100 sr = va_to_sr(pm->pm_sr, va); 2101 ptegidx = va_to_pteg(sr, va); 2102 2103 mtx_lock(&moea_table_mutex); 2104 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2105 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2106 if (pteidx_p) 2107 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2108 break; 2109 } 2110 } 2111 mtx_unlock(&moea_table_mutex); 2112 2113 return (pvo); 2114 } 2115 2116 static struct pte * 2117 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2118 { 2119 struct pte *pt; 2120 2121 /* 2122 * If we haven't been supplied the ptegidx, calculate it. 2123 */ 2124 if (pteidx == -1) { 2125 int ptegidx; 2126 u_int sr; 2127 2128 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2129 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2130 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2131 } 2132 2133 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2134 mtx_lock(&moea_table_mutex); 2135 2136 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2137 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2138 "valid pte index", pvo); 2139 } 2140 2141 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2142 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2143 "pvo but no valid pte", pvo); 2144 } 2145 2146 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2147 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2148 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2149 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2150 } 2151 2152 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2153 != 0) { 2154 panic("moea_pvo_to_pte: pvo %p pte does not match " 2155 "pte %p in moea_pteg_table", pvo, pt); 2156 } 2157 2158 mtx_assert(&moea_table_mutex, MA_OWNED); 2159 return (pt); 2160 } 2161 2162 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2163 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2164 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2165 } 2166 2167 mtx_unlock(&moea_table_mutex); 2168 return (NULL); 2169 } 2170 2171 /* 2172 * XXX: THIS STUFF SHOULD BE IN pte.c? 2173 */ 2174 int 2175 moea_pte_spill(vm_offset_t addr) 2176 { 2177 struct pvo_entry *source_pvo, *victim_pvo; 2178 struct pvo_entry *pvo; 2179 int ptegidx, i, j; 2180 u_int sr; 2181 struct pteg *pteg; 2182 struct pte *pt; 2183 2184 moea_pte_spills++; 2185 2186 sr = mfsrin(addr); 2187 ptegidx = va_to_pteg(sr, addr); 2188 2189 /* 2190 * Have to substitute some entry. Use the primary hash for this. 2191 * Use low bits of timebase as random generator. 2192 */ 2193 pteg = &moea_pteg_table[ptegidx]; 2194 mtx_lock(&moea_table_mutex); 2195 __asm __volatile("mftb %0" : "=r"(i)); 2196 i &= 7; 2197 pt = &pteg->pt[i]; 2198 2199 source_pvo = NULL; 2200 victim_pvo = NULL; 2201 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2202 /* 2203 * We need to find a pvo entry for this address. 2204 */ 2205 if (source_pvo == NULL && 2206 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2207 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2208 /* 2209 * Now found an entry to be spilled into the pteg. 2210 * The PTE is now valid, so we know it's active. 2211 */ 2212 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2213 2214 if (j >= 0) { 2215 PVO_PTEGIDX_SET(pvo, j); 2216 moea_pte_overflow--; 2217 mtx_unlock(&moea_table_mutex); 2218 return (1); 2219 } 2220 2221 source_pvo = pvo; 2222 2223 if (victim_pvo != NULL) 2224 break; 2225 } 2226 2227 /* 2228 * We also need the pvo entry of the victim we are replacing 2229 * so save the R & C bits of the PTE. 2230 */ 2231 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2232 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2233 victim_pvo = pvo; 2234 if (source_pvo != NULL) 2235 break; 2236 } 2237 } 2238 2239 if (source_pvo == NULL) { 2240 mtx_unlock(&moea_table_mutex); 2241 return (0); 2242 } 2243 2244 if (victim_pvo == NULL) { 2245 if ((pt->pte_hi & PTE_HID) == 0) 2246 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2247 "entry", pt); 2248 2249 /* 2250 * If this is a secondary PTE, we need to search it's primary 2251 * pvo bucket for the matching PVO. 2252 */ 2253 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2254 pvo_olink) { 2255 /* 2256 * We also need the pvo entry of the victim we are 2257 * replacing so save the R & C bits of the PTE. 2258 */ 2259 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2260 victim_pvo = pvo; 2261 break; 2262 } 2263 } 2264 2265 if (victim_pvo == NULL) 2266 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2267 "entry", pt); 2268 } 2269 2270 /* 2271 * We are invalidating the TLB entry for the EA we are replacing even 2272 * though it's valid. If we don't, we lose any ref/chg bit changes 2273 * contained in the TLB entry. 2274 */ 2275 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2276 2277 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2278 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2279 2280 PVO_PTEGIDX_CLR(victim_pvo); 2281 PVO_PTEGIDX_SET(source_pvo, i); 2282 moea_pte_replacements++; 2283 2284 mtx_unlock(&moea_table_mutex); 2285 return (1); 2286 } 2287 2288 static __inline struct pvo_entry * 2289 moea_pte_spillable_ident(u_int ptegidx) 2290 { 2291 struct pte *pt; 2292 struct pvo_entry *pvo_walk, *pvo = NULL; 2293 2294 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2295 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2296 continue; 2297 2298 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2299 continue; 2300 2301 pt = moea_pvo_to_pte(pvo_walk, -1); 2302 2303 if (pt == NULL) 2304 continue; 2305 2306 pvo = pvo_walk; 2307 2308 mtx_unlock(&moea_table_mutex); 2309 if (!(pt->pte_lo & PTE_REF)) 2310 return (pvo_walk); 2311 } 2312 2313 return (pvo); 2314 } 2315 2316 static int 2317 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2318 { 2319 struct pte *pt; 2320 struct pvo_entry *victim_pvo; 2321 int i; 2322 int victim_idx; 2323 u_int pteg_bkpidx = ptegidx; 2324 2325 mtx_assert(&moea_table_mutex, MA_OWNED); 2326 2327 /* 2328 * First try primary hash. 2329 */ 2330 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2331 if ((pt->pte_hi & PTE_VALID) == 0) { 2332 pvo_pt->pte_hi &= ~PTE_HID; 2333 moea_pte_set(pt, pvo_pt); 2334 return (i); 2335 } 2336 } 2337 2338 /* 2339 * Now try secondary hash. 2340 */ 2341 ptegidx ^= moea_pteg_mask; 2342 2343 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2344 if ((pt->pte_hi & PTE_VALID) == 0) { 2345 pvo_pt->pte_hi |= PTE_HID; 2346 moea_pte_set(pt, pvo_pt); 2347 return (i); 2348 } 2349 } 2350 2351 /* Try again, but this time try to force a PTE out. */ 2352 ptegidx = pteg_bkpidx; 2353 2354 victim_pvo = moea_pte_spillable_ident(ptegidx); 2355 if (victim_pvo == NULL) { 2356 ptegidx ^= moea_pteg_mask; 2357 victim_pvo = moea_pte_spillable_ident(ptegidx); 2358 } 2359 2360 if (victim_pvo == NULL) { 2361 panic("moea_pte_insert: overflow"); 2362 return (-1); 2363 } 2364 2365 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2366 2367 if (pteg_bkpidx == ptegidx) 2368 pvo_pt->pte_hi &= ~PTE_HID; 2369 else 2370 pvo_pt->pte_hi |= PTE_HID; 2371 2372 /* 2373 * Synchronize the sacrifice PTE with its PVO, then mark both 2374 * invalid. The PVO will be reused when/if the VM system comes 2375 * here after a fault. 2376 */ 2377 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2378 2379 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2380 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2381 2382 /* 2383 * Set the new PTE. 2384 */ 2385 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2386 PVO_PTEGIDX_CLR(victim_pvo); 2387 moea_pte_overflow++; 2388 moea_pte_set(pt, pvo_pt); 2389 2390 return (victim_idx & 7); 2391 } 2392 2393 static boolean_t 2394 moea_query_bit(vm_page_t m, int ptebit) 2395 { 2396 struct pvo_entry *pvo; 2397 struct pte *pt; 2398 2399 rw_assert(&pvh_global_lock, RA_WLOCKED); 2400 if (moea_attr_fetch(m) & ptebit) 2401 return (TRUE); 2402 2403 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2404 2405 /* 2406 * See if we saved the bit off. If so, cache it and return 2407 * success. 2408 */ 2409 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2410 moea_attr_save(m, ptebit); 2411 return (TRUE); 2412 } 2413 } 2414 2415 /* 2416 * No luck, now go through the hard part of looking at the PTEs 2417 * themselves. Sync so that any pending REF/CHG bits are flushed to 2418 * the PTEs. 2419 */ 2420 powerpc_sync(); 2421 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2422 2423 /* 2424 * See if this pvo has a valid PTE. if so, fetch the 2425 * REF/CHG bits from the valid PTE. If the appropriate 2426 * ptebit is set, cache it and return success. 2427 */ 2428 pt = moea_pvo_to_pte(pvo, -1); 2429 if (pt != NULL) { 2430 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2431 mtx_unlock(&moea_table_mutex); 2432 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2433 moea_attr_save(m, ptebit); 2434 return (TRUE); 2435 } 2436 } 2437 } 2438 2439 return (FALSE); 2440 } 2441 2442 static u_int 2443 moea_clear_bit(vm_page_t m, int ptebit) 2444 { 2445 u_int count; 2446 struct pvo_entry *pvo; 2447 struct pte *pt; 2448 2449 rw_assert(&pvh_global_lock, RA_WLOCKED); 2450 2451 /* 2452 * Clear the cached value. 2453 */ 2454 moea_attr_clear(m, ptebit); 2455 2456 /* 2457 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2458 * we can reset the right ones). note that since the pvo entries and 2459 * list heads are accessed via BAT0 and are never placed in the page 2460 * table, we don't have to worry about further accesses setting the 2461 * REF/CHG bits. 2462 */ 2463 powerpc_sync(); 2464 2465 /* 2466 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2467 * valid pte clear the ptebit from the valid pte. 2468 */ 2469 count = 0; 2470 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2471 pt = moea_pvo_to_pte(pvo, -1); 2472 if (pt != NULL) { 2473 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2474 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2475 count++; 2476 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2477 } 2478 mtx_unlock(&moea_table_mutex); 2479 } 2480 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2481 } 2482 2483 return (count); 2484 } 2485 2486 /* 2487 * Return true if the physical range is encompassed by the battable[idx] 2488 */ 2489 static int 2490 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2491 { 2492 u_int prot; 2493 u_int32_t start; 2494 u_int32_t end; 2495 u_int32_t bat_ble; 2496 2497 /* 2498 * Return immediately if not a valid mapping 2499 */ 2500 if (!(battable[idx].batu & BAT_Vs)) 2501 return (EINVAL); 2502 2503 /* 2504 * The BAT entry must be cache-inhibited, guarded, and r/w 2505 * so it can function as an i/o page 2506 */ 2507 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2508 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2509 return (EPERM); 2510 2511 /* 2512 * The address should be within the BAT range. Assume that the 2513 * start address in the BAT has the correct alignment (thus 2514 * not requiring masking) 2515 */ 2516 start = battable[idx].batl & BAT_PBS; 2517 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2518 end = start | (bat_ble << 15) | 0x7fff; 2519 2520 if ((pa < start) || ((pa + size) > end)) 2521 return (ERANGE); 2522 2523 return (0); 2524 } 2525 2526 boolean_t 2527 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2528 { 2529 int i; 2530 2531 /* 2532 * This currently does not work for entries that 2533 * overlap 256M BAT segments. 2534 */ 2535 2536 for(i = 0; i < 16; i++) 2537 if (moea_bat_mapped(i, pa, size) == 0) 2538 return (0); 2539 2540 return (EFAULT); 2541 } 2542 2543 /* 2544 * Map a set of physical memory pages into the kernel virtual 2545 * address space. Return a pointer to where it is mapped. This 2546 * routine is intended to be used for mapping device memory, 2547 * NOT real memory. 2548 */ 2549 void * 2550 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2551 { 2552 2553 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2554 } 2555 2556 void * 2557 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2558 { 2559 vm_offset_t va, tmpva, ppa, offset; 2560 int i; 2561 2562 ppa = trunc_page(pa); 2563 offset = pa & PAGE_MASK; 2564 size = roundup(offset + size, PAGE_SIZE); 2565 2566 /* 2567 * If the physical address lies within a valid BAT table entry, 2568 * return the 1:1 mapping. This currently doesn't work 2569 * for regions that overlap 256M BAT segments. 2570 */ 2571 for (i = 0; i < 16; i++) { 2572 if (moea_bat_mapped(i, pa, size) == 0) 2573 return ((void *) pa); 2574 } 2575 2576 va = kva_alloc(size); 2577 if (!va) 2578 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2579 2580 for (tmpva = va; size > 0;) { 2581 moea_kenter_attr(mmu, tmpva, ppa, ma); 2582 tlbie(tmpva); 2583 size -= PAGE_SIZE; 2584 tmpva += PAGE_SIZE; 2585 ppa += PAGE_SIZE; 2586 } 2587 2588 return ((void *)(va + offset)); 2589 } 2590 2591 void 2592 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2593 { 2594 vm_offset_t base, offset; 2595 2596 /* 2597 * If this is outside kernel virtual space, then it's a 2598 * battable entry and doesn't require unmapping 2599 */ 2600 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2601 base = trunc_page(va); 2602 offset = va & PAGE_MASK; 2603 size = roundup(offset + size, PAGE_SIZE); 2604 kva_free(base, size); 2605 } 2606 } 2607 2608 static void 2609 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2610 { 2611 struct pvo_entry *pvo; 2612 vm_offset_t lim; 2613 vm_paddr_t pa; 2614 vm_size_t len; 2615 2616 PMAP_LOCK(pm); 2617 while (sz > 0) { 2618 lim = round_page(va); 2619 len = MIN(lim - va, sz); 2620 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2621 if (pvo != NULL) { 2622 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2623 (va & ADDR_POFF); 2624 moea_syncicache(pa, len); 2625 } 2626 va += len; 2627 sz -= len; 2628 } 2629 PMAP_UNLOCK(pm); 2630 } 2631 2632 vm_offset_t 2633 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2634 vm_size_t *sz) 2635 { 2636 if (md->md_vaddr == ~0UL) 2637 return (md->md_paddr + ofs); 2638 else 2639 return (md->md_vaddr + ofs); 2640 } 2641 2642 struct pmap_md * 2643 moea_scan_md(mmu_t mmu, struct pmap_md *prev) 2644 { 2645 static struct pmap_md md; 2646 struct pvo_entry *pvo; 2647 vm_offset_t va; 2648 2649 if (dumpsys_minidump) { 2650 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2651 if (prev == NULL) { 2652 /* 1st: kernel .data and .bss. */ 2653 md.md_index = 1; 2654 md.md_vaddr = trunc_page((uintptr_t)_etext); 2655 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2656 return (&md); 2657 } 2658 switch (prev->md_index) { 2659 case 1: 2660 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2661 md.md_index = 2; 2662 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2663 md.md_size = round_page(msgbufp->msg_size); 2664 break; 2665 case 2: 2666 /* 3rd: kernel VM. */ 2667 va = prev->md_vaddr + prev->md_size; 2668 /* Find start of next chunk (from va). */ 2669 while (va < virtual_end) { 2670 /* Don't dump the buffer cache. */ 2671 if (va >= kmi.buffer_sva && 2672 va < kmi.buffer_eva) { 2673 va = kmi.buffer_eva; 2674 continue; 2675 } 2676 pvo = moea_pvo_find_va(kernel_pmap, 2677 va & ~ADDR_POFF, NULL); 2678 if (pvo != NULL && 2679 (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2680 break; 2681 va += PAGE_SIZE; 2682 } 2683 if (va < virtual_end) { 2684 md.md_vaddr = va; 2685 va += PAGE_SIZE; 2686 /* Find last page in chunk. */ 2687 while (va < virtual_end) { 2688 /* Don't run into the buffer cache. */ 2689 if (va == kmi.buffer_sva) 2690 break; 2691 pvo = moea_pvo_find_va(kernel_pmap, 2692 va & ~ADDR_POFF, NULL); 2693 if (pvo == NULL || 2694 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2695 break; 2696 va += PAGE_SIZE; 2697 } 2698 md.md_size = va - md.md_vaddr; 2699 break; 2700 } 2701 md.md_index = 3; 2702 /* FALLTHROUGH */ 2703 default: 2704 return (NULL); 2705 } 2706 } else { /* minidumps */ 2707 mem_regions(&pregions, &pregions_sz, 2708 ®ions, ®ions_sz); 2709 2710 if (prev == NULL) { 2711 /* first physical chunk. */ 2712 md.md_paddr = pregions[0].mr_start; 2713 md.md_size = pregions[0].mr_size; 2714 md.md_vaddr = ~0UL; 2715 md.md_index = 1; 2716 } else if (md.md_index < pregions_sz) { 2717 md.md_paddr = pregions[md.md_index].mr_start; 2718 md.md_size = pregions[md.md_index].mr_size; 2719 md.md_vaddr = ~0UL; 2720 md.md_index++; 2721 } else { 2722 /* There's no next physical chunk. */ 2723 return (NULL); 2724 } 2725 } 2726 2727 return (&md); 2728 } 2729