1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/cpu.h> 141 #include <machine/platform.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/smp.h> 148 #include <machine/sr.h> 149 #include <machine/mmuvar.h> 150 #include <machine/trap.h> 151 152 #include "mmu_if.h" 153 154 #define MOEA_DEBUG 155 156 #define TODO panic("%s: not implemented", __func__); 157 158 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 159 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 160 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 161 162 struct ofw_map { 163 vm_offset_t om_va; 164 vm_size_t om_len; 165 vm_offset_t om_pa; 166 u_int om_mode; 167 }; 168 169 extern unsigned char _etext[]; 170 extern unsigned char _end[]; 171 172 /* 173 * Map of physical memory regions. 174 */ 175 static struct mem_region *regions; 176 static struct mem_region *pregions; 177 static u_int phys_avail_count; 178 static int regions_sz, pregions_sz; 179 static struct ofw_map *translations; 180 181 /* 182 * Lock for the pteg and pvo tables. 183 */ 184 struct mtx moea_table_mutex; 185 struct mtx moea_vsid_mutex; 186 187 /* tlbie instruction synchronization */ 188 static struct mtx tlbie_mtx; 189 190 /* 191 * PTEG data. 192 */ 193 static struct pteg *moea_pteg_table; 194 u_int moea_pteg_count; 195 u_int moea_pteg_mask; 196 197 /* 198 * PVO data. 199 */ 200 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 201 struct pvo_head moea_pvo_kunmanaged = 202 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 203 204 static struct rwlock_padalign pvh_global_lock; 205 206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 208 209 #define BPVO_POOL_SIZE 32768 210 static struct pvo_entry *moea_bpvo_pool; 211 static int moea_bpvo_pool_index = 0; 212 213 #define VSID_NBPW (sizeof(u_int32_t) * 8) 214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 215 216 static boolean_t moea_initialized = FALSE; 217 218 /* 219 * Statistics. 220 */ 221 u_int moea_pte_valid = 0; 222 u_int moea_pte_overflow = 0; 223 u_int moea_pte_replacements = 0; 224 u_int moea_pvo_entries = 0; 225 u_int moea_pvo_enter_calls = 0; 226 u_int moea_pvo_remove_calls = 0; 227 u_int moea_pte_spills = 0; 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 229 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 231 &moea_pte_overflow, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 233 &moea_pte_replacements, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 235 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 237 &moea_pvo_enter_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 239 &moea_pvo_remove_calls, 0, ""); 240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 241 &moea_pte_spills, 0, ""); 242 243 /* 244 * Allocate physical memory for use in moea_bootstrap. 245 */ 246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 247 248 /* 249 * PTE calls. 250 */ 251 static int moea_pte_insert(u_int, struct pte *); 252 253 /* 254 * PVO calls. 255 */ 256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 257 vm_offset_t, vm_paddr_t, u_int, int); 258 static void moea_pvo_remove(struct pvo_entry *, int); 259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 261 262 /* 263 * Utility routines. 264 */ 265 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 266 vm_prot_t, u_int, int8_t); 267 static void moea_syncicache(vm_paddr_t, vm_size_t); 268 static boolean_t moea_query_bit(vm_page_t, int); 269 static u_int moea_clear_bit(vm_page_t, int); 270 static void moea_kremove(mmu_t, vm_offset_t); 271 int moea_pte_spill(vm_offset_t); 272 273 /* 274 * Kernel MMU interface 275 */ 276 void moea_clear_modify(mmu_t, vm_page_t); 277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 278 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 279 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 280 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 281 int8_t); 282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 287 void moea_init(mmu_t); 288 boolean_t moea_is_modified(mmu_t, vm_page_t); 289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 boolean_t moea_is_referenced(mmu_t, vm_page_t); 291 int moea_ts_referenced(mmu_t, vm_page_t); 292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 void moea_page_init(mmu_t, vm_page_t); 295 int moea_page_wired_mappings(mmu_t, vm_page_t); 296 void moea_pinit(mmu_t, pmap_t); 297 void moea_pinit0(mmu_t, pmap_t); 298 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 299 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 300 void moea_qremove(mmu_t, vm_offset_t, int); 301 void moea_release(mmu_t, pmap_t); 302 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 303 void moea_remove_all(mmu_t, vm_page_t); 304 void moea_remove_write(mmu_t, vm_page_t); 305 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 306 void moea_zero_page(mmu_t, vm_page_t); 307 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 308 void moea_activate(mmu_t, struct thread *); 309 void moea_deactivate(mmu_t, struct thread *); 310 void moea_cpu_bootstrap(mmu_t, int); 311 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 312 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 313 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 314 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 315 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 316 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 317 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 318 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 319 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 320 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 321 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 322 void moea_scan_init(mmu_t mmu); 323 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 324 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 325 boolean_t moea_page_is_mapped(mmu_t mmu, vm_page_t m); 326 static int moea_map_user_ptr(mmu_t mmu, pmap_t pm, 327 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 328 static int moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 329 int *is_user, vm_offset_t *decoded_addr); 330 331 332 static mmu_method_t moea_methods[] = { 333 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 334 MMUMETHOD(mmu_copy_page, moea_copy_page), 335 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 336 MMUMETHOD(mmu_enter, moea_enter), 337 MMUMETHOD(mmu_enter_object, moea_enter_object), 338 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 339 MMUMETHOD(mmu_extract, moea_extract), 340 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 341 MMUMETHOD(mmu_init, moea_init), 342 MMUMETHOD(mmu_is_modified, moea_is_modified), 343 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 344 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 345 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 346 MMUMETHOD(mmu_map, moea_map), 347 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 348 MMUMETHOD(mmu_page_init, moea_page_init), 349 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 350 MMUMETHOD(mmu_pinit, moea_pinit), 351 MMUMETHOD(mmu_pinit0, moea_pinit0), 352 MMUMETHOD(mmu_protect, moea_protect), 353 MMUMETHOD(mmu_qenter, moea_qenter), 354 MMUMETHOD(mmu_qremove, moea_qremove), 355 MMUMETHOD(mmu_release, moea_release), 356 MMUMETHOD(mmu_remove, moea_remove), 357 MMUMETHOD(mmu_remove_all, moea_remove_all), 358 MMUMETHOD(mmu_remove_write, moea_remove_write), 359 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 360 MMUMETHOD(mmu_unwire, moea_unwire), 361 MMUMETHOD(mmu_zero_page, moea_zero_page), 362 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 363 MMUMETHOD(mmu_activate, moea_activate), 364 MMUMETHOD(mmu_deactivate, moea_deactivate), 365 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 366 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 367 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 368 MMUMETHOD(mmu_page_is_mapped, moea_page_is_mapped), 369 370 /* Internal interfaces */ 371 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 372 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 373 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 374 MMUMETHOD(mmu_mapdev, moea_mapdev), 375 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 376 MMUMETHOD(mmu_kextract, moea_kextract), 377 MMUMETHOD(mmu_kenter, moea_kenter), 378 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 379 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 380 MMUMETHOD(mmu_scan_init, moea_scan_init), 381 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 382 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr), 383 MMUMETHOD(mmu_decode_kernel_ptr, moea_decode_kernel_ptr), 384 385 { 0, 0 } 386 }; 387 388 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 389 390 static __inline uint32_t 391 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 392 { 393 uint32_t pte_lo; 394 int i; 395 396 if (ma != VM_MEMATTR_DEFAULT) { 397 switch (ma) { 398 case VM_MEMATTR_UNCACHEABLE: 399 return (PTE_I | PTE_G); 400 case VM_MEMATTR_CACHEABLE: 401 return (PTE_M); 402 case VM_MEMATTR_WRITE_COMBINING: 403 case VM_MEMATTR_WRITE_BACK: 404 case VM_MEMATTR_PREFETCHABLE: 405 return (PTE_I); 406 case VM_MEMATTR_WRITE_THROUGH: 407 return (PTE_W | PTE_M); 408 } 409 } 410 411 /* 412 * Assume the page is cache inhibited and access is guarded unless 413 * it's in our available memory array. 414 */ 415 pte_lo = PTE_I | PTE_G; 416 for (i = 0; i < pregions_sz; i++) { 417 if ((pa >= pregions[i].mr_start) && 418 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 419 pte_lo = PTE_M; 420 break; 421 } 422 } 423 424 return pte_lo; 425 } 426 427 static void 428 tlbie(vm_offset_t va) 429 { 430 431 mtx_lock_spin(&tlbie_mtx); 432 __asm __volatile("ptesync"); 433 __asm __volatile("tlbie %0" :: "r"(va)); 434 __asm __volatile("eieio; tlbsync; ptesync"); 435 mtx_unlock_spin(&tlbie_mtx); 436 } 437 438 static void 439 tlbia(void) 440 { 441 vm_offset_t va; 442 443 for (va = 0; va < 0x00040000; va += 0x00001000) { 444 __asm __volatile("tlbie %0" :: "r"(va)); 445 powerpc_sync(); 446 } 447 __asm __volatile("tlbsync"); 448 powerpc_sync(); 449 } 450 451 static __inline int 452 va_to_sr(u_int *sr, vm_offset_t va) 453 { 454 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 455 } 456 457 static __inline u_int 458 va_to_pteg(u_int sr, vm_offset_t addr) 459 { 460 u_int hash; 461 462 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 463 ADDR_PIDX_SHFT); 464 return (hash & moea_pteg_mask); 465 } 466 467 static __inline struct pvo_head * 468 vm_page_to_pvoh(vm_page_t m) 469 { 470 471 return (&m->md.mdpg_pvoh); 472 } 473 474 static __inline void 475 moea_attr_clear(vm_page_t m, int ptebit) 476 { 477 478 rw_assert(&pvh_global_lock, RA_WLOCKED); 479 m->md.mdpg_attrs &= ~ptebit; 480 } 481 482 static __inline int 483 moea_attr_fetch(vm_page_t m) 484 { 485 486 return (m->md.mdpg_attrs); 487 } 488 489 static __inline void 490 moea_attr_save(vm_page_t m, int ptebit) 491 { 492 493 rw_assert(&pvh_global_lock, RA_WLOCKED); 494 m->md.mdpg_attrs |= ptebit; 495 } 496 497 static __inline int 498 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 499 { 500 if (pt->pte_hi == pvo_pt->pte_hi) 501 return (1); 502 503 return (0); 504 } 505 506 static __inline int 507 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 508 { 509 return (pt->pte_hi & ~PTE_VALID) == 510 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 511 ((va >> ADDR_API_SHFT) & PTE_API) | which); 512 } 513 514 static __inline void 515 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 516 { 517 518 mtx_assert(&moea_table_mutex, MA_OWNED); 519 520 /* 521 * Construct a PTE. Default to IMB initially. Valid bit only gets 522 * set when the real pte is set in memory. 523 * 524 * Note: Don't set the valid bit for correct operation of tlb update. 525 */ 526 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 527 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 528 pt->pte_lo = pte_lo; 529 } 530 531 static __inline void 532 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 533 { 534 535 mtx_assert(&moea_table_mutex, MA_OWNED); 536 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 537 } 538 539 static __inline void 540 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 541 { 542 543 mtx_assert(&moea_table_mutex, MA_OWNED); 544 545 /* 546 * As shown in Section 7.6.3.2.3 547 */ 548 pt->pte_lo &= ~ptebit; 549 tlbie(va); 550 } 551 552 static __inline void 553 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 554 { 555 556 mtx_assert(&moea_table_mutex, MA_OWNED); 557 pvo_pt->pte_hi |= PTE_VALID; 558 559 /* 560 * Update the PTE as defined in section 7.6.3.1. 561 * Note that the REF/CHG bits are from pvo_pt and thus should have 562 * been saved so this routine can restore them (if desired). 563 */ 564 pt->pte_lo = pvo_pt->pte_lo; 565 powerpc_sync(); 566 pt->pte_hi = pvo_pt->pte_hi; 567 powerpc_sync(); 568 moea_pte_valid++; 569 } 570 571 static __inline void 572 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 573 { 574 575 mtx_assert(&moea_table_mutex, MA_OWNED); 576 pvo_pt->pte_hi &= ~PTE_VALID; 577 578 /* 579 * Force the reg & chg bits back into the PTEs. 580 */ 581 powerpc_sync(); 582 583 /* 584 * Invalidate the pte. 585 */ 586 pt->pte_hi &= ~PTE_VALID; 587 588 tlbie(va); 589 590 /* 591 * Save the reg & chg bits. 592 */ 593 moea_pte_synch(pt, pvo_pt); 594 moea_pte_valid--; 595 } 596 597 static __inline void 598 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 599 { 600 601 /* 602 * Invalidate the PTE 603 */ 604 moea_pte_unset(pt, pvo_pt, va); 605 moea_pte_set(pt, pvo_pt); 606 } 607 608 /* 609 * Quick sort callout for comparing memory regions. 610 */ 611 static int om_cmp(const void *a, const void *b); 612 613 static int 614 om_cmp(const void *a, const void *b) 615 { 616 const struct ofw_map *mapa; 617 const struct ofw_map *mapb; 618 619 mapa = a; 620 mapb = b; 621 if (mapa->om_pa < mapb->om_pa) 622 return (-1); 623 else if (mapa->om_pa > mapb->om_pa) 624 return (1); 625 else 626 return (0); 627 } 628 629 void 630 moea_cpu_bootstrap(mmu_t mmup, int ap) 631 { 632 u_int sdr; 633 int i; 634 635 if (ap) { 636 powerpc_sync(); 637 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 638 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 639 isync(); 640 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 641 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 642 isync(); 643 } 644 645 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 646 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 647 isync(); 648 649 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 650 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 651 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 652 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 653 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 654 isync(); 655 656 for (i = 0; i < 16; i++) 657 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 658 powerpc_sync(); 659 660 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 661 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 662 isync(); 663 664 tlbia(); 665 } 666 667 void 668 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 669 { 670 ihandle_t mmui; 671 phandle_t chosen, mmu; 672 int sz; 673 int i, j; 674 vm_size_t size, physsz, hwphyssz; 675 vm_offset_t pa, va, off; 676 void *dpcpu; 677 register_t msr; 678 679 /* 680 * Set up BAT0 to map the lowest 256 MB area 681 */ 682 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 683 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 684 685 /* 686 * Map PCI memory space. 687 */ 688 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 689 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 690 691 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 692 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 693 694 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 695 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 696 697 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 698 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 699 700 /* 701 * Map obio devices. 702 */ 703 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 704 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 705 706 /* 707 * Use an IBAT and a DBAT to map the bottom segment of memory 708 * where we are. Turn off instruction relocation temporarily 709 * to prevent faults while reprogramming the IBAT. 710 */ 711 msr = mfmsr(); 712 mtmsr(msr & ~PSL_IR); 713 __asm (".balign 32; \n" 714 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 715 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 716 :: "r"(battable[0].batu), "r"(battable[0].batl)); 717 mtmsr(msr); 718 719 /* map pci space */ 720 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 721 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 722 isync(); 723 724 /* set global direct map flag */ 725 hw_direct_map = 1; 726 727 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 728 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 729 730 for (i = 0; i < pregions_sz; i++) { 731 vm_offset_t pa; 732 vm_offset_t end; 733 734 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 735 pregions[i].mr_start, 736 pregions[i].mr_start + pregions[i].mr_size, 737 pregions[i].mr_size); 738 /* 739 * Install entries into the BAT table to allow all 740 * of physmem to be convered by on-demand BAT entries. 741 * The loop will sometimes set the same battable element 742 * twice, but that's fine since they won't be used for 743 * a while yet. 744 */ 745 pa = pregions[i].mr_start & 0xf0000000; 746 end = pregions[i].mr_start + pregions[i].mr_size; 747 do { 748 u_int n = pa >> ADDR_SR_SHFT; 749 750 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 751 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 752 pa += SEGMENT_LENGTH; 753 } while (pa < end); 754 } 755 756 if (PHYS_AVAIL_ENTRIES < regions_sz) 757 panic("moea_bootstrap: phys_avail too small"); 758 759 phys_avail_count = 0; 760 physsz = 0; 761 hwphyssz = 0; 762 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 763 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 764 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 765 regions[i].mr_start + regions[i].mr_size, 766 regions[i].mr_size); 767 if (hwphyssz != 0 && 768 (physsz + regions[i].mr_size) >= hwphyssz) { 769 if (physsz < hwphyssz) { 770 phys_avail[j] = regions[i].mr_start; 771 phys_avail[j + 1] = regions[i].mr_start + 772 hwphyssz - physsz; 773 physsz = hwphyssz; 774 phys_avail_count++; 775 } 776 break; 777 } 778 phys_avail[j] = regions[i].mr_start; 779 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 780 phys_avail_count++; 781 physsz += regions[i].mr_size; 782 } 783 784 /* Check for overlap with the kernel and exception vectors */ 785 for (j = 0; j < 2*phys_avail_count; j+=2) { 786 if (phys_avail[j] < EXC_LAST) 787 phys_avail[j] += EXC_LAST; 788 789 if (kernelstart >= phys_avail[j] && 790 kernelstart < phys_avail[j+1]) { 791 if (kernelend < phys_avail[j+1]) { 792 phys_avail[2*phys_avail_count] = 793 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 794 phys_avail[2*phys_avail_count + 1] = 795 phys_avail[j+1]; 796 phys_avail_count++; 797 } 798 799 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 800 } 801 802 if (kernelend >= phys_avail[j] && 803 kernelend < phys_avail[j+1]) { 804 if (kernelstart > phys_avail[j]) { 805 phys_avail[2*phys_avail_count] = phys_avail[j]; 806 phys_avail[2*phys_avail_count + 1] = 807 kernelstart & ~PAGE_MASK; 808 phys_avail_count++; 809 } 810 811 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 812 } 813 } 814 815 physmem = btoc(physsz); 816 817 /* 818 * Allocate PTEG table. 819 */ 820 #ifdef PTEGCOUNT 821 moea_pteg_count = PTEGCOUNT; 822 #else 823 moea_pteg_count = 0x1000; 824 825 while (moea_pteg_count < physmem) 826 moea_pteg_count <<= 1; 827 828 moea_pteg_count >>= 1; 829 #endif /* PTEGCOUNT */ 830 831 size = moea_pteg_count * sizeof(struct pteg); 832 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 833 size); 834 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 835 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 836 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 837 moea_pteg_mask = moea_pteg_count - 1; 838 839 /* 840 * Allocate pv/overflow lists. 841 */ 842 size = sizeof(struct pvo_head) * moea_pteg_count; 843 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 844 PAGE_SIZE); 845 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 846 for (i = 0; i < moea_pteg_count; i++) 847 LIST_INIT(&moea_pvo_table[i]); 848 849 /* 850 * Initialize the lock that synchronizes access to the pteg and pvo 851 * tables. 852 */ 853 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 854 MTX_RECURSE); 855 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 856 857 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 858 859 /* 860 * Initialise the unmanaged pvo pool. 861 */ 862 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 863 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 864 moea_bpvo_pool_index = 0; 865 866 /* 867 * Make sure kernel vsid is allocated as well as VSID 0. 868 */ 869 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 870 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 871 moea_vsid_bitmap[0] |= 1; 872 873 /* 874 * Initialize the kernel pmap (which is statically allocated). 875 */ 876 PMAP_LOCK_INIT(kernel_pmap); 877 for (i = 0; i < 16; i++) 878 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 879 CPU_FILL(&kernel_pmap->pm_active); 880 RB_INIT(&kernel_pmap->pmap_pvo); 881 882 /* 883 * Initialize the global pv list lock. 884 */ 885 rw_init(&pvh_global_lock, "pmap pv global"); 886 887 /* 888 * Set up the Open Firmware mappings 889 */ 890 chosen = OF_finddevice("/chosen"); 891 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 892 (mmu = OF_instance_to_package(mmui)) != -1 && 893 (sz = OF_getproplen(mmu, "translations")) != -1) { 894 translations = NULL; 895 for (i = 0; phys_avail[i] != 0; i += 2) { 896 if (phys_avail[i + 1] >= sz) { 897 translations = (struct ofw_map *)phys_avail[i]; 898 break; 899 } 900 } 901 if (translations == NULL) 902 panic("moea_bootstrap: no space to copy translations"); 903 bzero(translations, sz); 904 if (OF_getprop(mmu, "translations", translations, sz) == -1) 905 panic("moea_bootstrap: can't get ofw translations"); 906 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 907 sz /= sizeof(*translations); 908 qsort(translations, sz, sizeof (*translations), om_cmp); 909 for (i = 0; i < sz; i++) { 910 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 911 translations[i].om_pa, translations[i].om_va, 912 translations[i].om_len); 913 914 /* 915 * If the mapping is 1:1, let the RAM and device 916 * on-demand BAT tables take care of the translation. 917 */ 918 if (translations[i].om_va == translations[i].om_pa) 919 continue; 920 921 /* Enter the pages */ 922 for (off = 0; off < translations[i].om_len; 923 off += PAGE_SIZE) 924 moea_kenter(mmup, translations[i].om_va + off, 925 translations[i].om_pa + off); 926 } 927 } 928 929 /* 930 * Calculate the last available physical address. 931 */ 932 for (i = 0; phys_avail[i + 2] != 0; i += 2) 933 ; 934 Maxmem = powerpc_btop(phys_avail[i + 1]); 935 936 moea_cpu_bootstrap(mmup,0); 937 mtmsr(mfmsr() | PSL_DR | PSL_IR); 938 pmap_bootstrapped++; 939 940 /* 941 * Set the start and end of kva. 942 */ 943 virtual_avail = VM_MIN_KERNEL_ADDRESS; 944 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 945 946 /* 947 * Allocate a kernel stack with a guard page for thread0 and map it 948 * into the kernel page map. 949 */ 950 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 951 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 952 virtual_avail = va + kstack_pages * PAGE_SIZE; 953 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 954 thread0.td_kstack = va; 955 thread0.td_kstack_pages = kstack_pages; 956 for (i = 0; i < kstack_pages; i++) { 957 moea_kenter(mmup, va, pa); 958 pa += PAGE_SIZE; 959 va += PAGE_SIZE; 960 } 961 962 /* 963 * Allocate virtual address space for the message buffer. 964 */ 965 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 966 msgbufp = (struct msgbuf *)virtual_avail; 967 va = virtual_avail; 968 virtual_avail += round_page(msgbufsize); 969 while (va < virtual_avail) { 970 moea_kenter(mmup, va, pa); 971 pa += PAGE_SIZE; 972 va += PAGE_SIZE; 973 } 974 975 /* 976 * Allocate virtual address space for the dynamic percpu area. 977 */ 978 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 979 dpcpu = (void *)virtual_avail; 980 va = virtual_avail; 981 virtual_avail += DPCPU_SIZE; 982 while (va < virtual_avail) { 983 moea_kenter(mmup, va, pa); 984 pa += PAGE_SIZE; 985 va += PAGE_SIZE; 986 } 987 dpcpu_init(dpcpu, 0); 988 } 989 990 /* 991 * Activate a user pmap. The pmap must be activated before it's address 992 * space can be accessed in any way. 993 */ 994 void 995 moea_activate(mmu_t mmu, struct thread *td) 996 { 997 pmap_t pm, pmr; 998 999 /* 1000 * Load all the data we need up front to encourage the compiler to 1001 * not issue any loads while we have interrupts disabled below. 1002 */ 1003 pm = &td->td_proc->p_vmspace->vm_pmap; 1004 pmr = pm->pmap_phys; 1005 1006 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1007 PCPU_SET(curpmap, pmr); 1008 1009 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1010 } 1011 1012 void 1013 moea_deactivate(mmu_t mmu, struct thread *td) 1014 { 1015 pmap_t pm; 1016 1017 pm = &td->td_proc->p_vmspace->vm_pmap; 1018 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1019 PCPU_SET(curpmap, NULL); 1020 } 1021 1022 void 1023 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1024 { 1025 struct pvo_entry key, *pvo; 1026 1027 PMAP_LOCK(pm); 1028 key.pvo_vaddr = sva; 1029 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1030 pvo != NULL && PVO_VADDR(pvo) < eva; 1031 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1032 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1033 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1034 pvo->pvo_vaddr &= ~PVO_WIRED; 1035 pm->pm_stats.wired_count--; 1036 } 1037 PMAP_UNLOCK(pm); 1038 } 1039 1040 void 1041 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1042 { 1043 vm_offset_t dst; 1044 vm_offset_t src; 1045 1046 dst = VM_PAGE_TO_PHYS(mdst); 1047 src = VM_PAGE_TO_PHYS(msrc); 1048 1049 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1050 } 1051 1052 void 1053 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1054 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1055 { 1056 void *a_cp, *b_cp; 1057 vm_offset_t a_pg_offset, b_pg_offset; 1058 int cnt; 1059 1060 while (xfersize > 0) { 1061 a_pg_offset = a_offset & PAGE_MASK; 1062 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1063 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1064 a_pg_offset; 1065 b_pg_offset = b_offset & PAGE_MASK; 1066 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1067 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1068 b_pg_offset; 1069 bcopy(a_cp, b_cp, cnt); 1070 a_offset += cnt; 1071 b_offset += cnt; 1072 xfersize -= cnt; 1073 } 1074 } 1075 1076 /* 1077 * Zero a page of physical memory by temporarily mapping it into the tlb. 1078 */ 1079 void 1080 moea_zero_page(mmu_t mmu, vm_page_t m) 1081 { 1082 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1083 1084 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1085 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1086 } 1087 1088 void 1089 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1090 { 1091 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1092 void *va = (void *)(pa + off); 1093 1094 bzero(va, size); 1095 } 1096 1097 vm_offset_t 1098 moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1099 { 1100 1101 return (VM_PAGE_TO_PHYS(m)); 1102 } 1103 1104 void 1105 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1106 { 1107 } 1108 1109 boolean_t 1110 moea_page_is_mapped(mmu_t mmu, vm_page_t m) 1111 { 1112 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1113 } 1114 1115 /* 1116 * Map the given physical page at the specified virtual address in the 1117 * target pmap with the protection requested. If specified the page 1118 * will be wired down. 1119 */ 1120 int 1121 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1122 u_int flags, int8_t psind) 1123 { 1124 int error; 1125 1126 for (;;) { 1127 rw_wlock(&pvh_global_lock); 1128 PMAP_LOCK(pmap); 1129 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1130 rw_wunlock(&pvh_global_lock); 1131 PMAP_UNLOCK(pmap); 1132 if (error != ENOMEM) 1133 return (KERN_SUCCESS); 1134 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1135 return (KERN_RESOURCE_SHORTAGE); 1136 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1137 vm_wait(NULL); 1138 } 1139 } 1140 1141 /* 1142 * Map the given physical page at the specified virtual address in the 1143 * target pmap with the protection requested. If specified the page 1144 * will be wired down. 1145 * 1146 * The global pvh and pmap must be locked. 1147 */ 1148 static int 1149 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1150 u_int flags, int8_t psind __unused) 1151 { 1152 struct pvo_head *pvo_head; 1153 uma_zone_t zone; 1154 u_int pte_lo, pvo_flags; 1155 int error; 1156 1157 if (pmap_bootstrapped) 1158 rw_assert(&pvh_global_lock, RA_WLOCKED); 1159 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1160 if ((m->oflags & VPO_UNMANAGED) == 0) { 1161 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1162 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1163 else 1164 VM_OBJECT_ASSERT_LOCKED(m->object); 1165 } 1166 1167 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1168 pvo_head = &moea_pvo_kunmanaged; 1169 zone = moea_upvo_zone; 1170 pvo_flags = 0; 1171 } else { 1172 pvo_head = vm_page_to_pvoh(m); 1173 zone = moea_mpvo_zone; 1174 pvo_flags = PVO_MANAGED; 1175 } 1176 1177 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1178 1179 if (prot & VM_PROT_WRITE) { 1180 pte_lo |= PTE_BW; 1181 if (pmap_bootstrapped && 1182 (m->oflags & VPO_UNMANAGED) == 0) 1183 vm_page_aflag_set(m, PGA_WRITEABLE); 1184 } else 1185 pte_lo |= PTE_BR; 1186 1187 if ((flags & PMAP_ENTER_WIRED) != 0) 1188 pvo_flags |= PVO_WIRED; 1189 1190 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1191 pte_lo, pvo_flags); 1192 1193 /* 1194 * Flush the real page from the instruction cache. This has be done 1195 * for all user mappings to prevent information leakage via the 1196 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1197 * mapping for a page. 1198 */ 1199 if (pmap != kernel_pmap && error == ENOENT && 1200 (pte_lo & (PTE_I | PTE_G)) == 0) 1201 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1202 1203 return (error); 1204 } 1205 1206 /* 1207 * Maps a sequence of resident pages belonging to the same object. 1208 * The sequence begins with the given page m_start. This page is 1209 * mapped at the given virtual address start. Each subsequent page is 1210 * mapped at a virtual address that is offset from start by the same 1211 * amount as the page is offset from m_start within the object. The 1212 * last page in the sequence is the page with the largest offset from 1213 * m_start that can be mapped at a virtual address less than the given 1214 * virtual address end. Not every virtual page between start and end 1215 * is mapped; only those for which a resident page exists with the 1216 * corresponding offset from m_start are mapped. 1217 */ 1218 void 1219 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1220 vm_page_t m_start, vm_prot_t prot) 1221 { 1222 vm_page_t m; 1223 vm_pindex_t diff, psize; 1224 1225 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1226 1227 psize = atop(end - start); 1228 m = m_start; 1229 rw_wlock(&pvh_global_lock); 1230 PMAP_LOCK(pm); 1231 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1232 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1233 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_QUICK_LOCKED, 1234 0); 1235 m = TAILQ_NEXT(m, listq); 1236 } 1237 rw_wunlock(&pvh_global_lock); 1238 PMAP_UNLOCK(pm); 1239 } 1240 1241 void 1242 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1243 vm_prot_t prot) 1244 { 1245 1246 rw_wlock(&pvh_global_lock); 1247 PMAP_LOCK(pm); 1248 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1249 PMAP_ENTER_QUICK_LOCKED, 0); 1250 rw_wunlock(&pvh_global_lock); 1251 PMAP_UNLOCK(pm); 1252 } 1253 1254 vm_paddr_t 1255 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1256 { 1257 struct pvo_entry *pvo; 1258 vm_paddr_t pa; 1259 1260 PMAP_LOCK(pm); 1261 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1262 if (pvo == NULL) 1263 pa = 0; 1264 else 1265 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1266 PMAP_UNLOCK(pm); 1267 return (pa); 1268 } 1269 1270 /* 1271 * Atomically extract and hold the physical page with the given 1272 * pmap and virtual address pair if that mapping permits the given 1273 * protection. 1274 */ 1275 vm_page_t 1276 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1277 { 1278 struct pvo_entry *pvo; 1279 vm_page_t m; 1280 1281 m = NULL; 1282 PMAP_LOCK(pmap); 1283 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1284 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1285 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1286 (prot & VM_PROT_WRITE) == 0)) { 1287 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1288 if (!vm_page_wire_mapped(m)) 1289 m = NULL; 1290 } 1291 PMAP_UNLOCK(pmap); 1292 return (m); 1293 } 1294 1295 void 1296 moea_init(mmu_t mmu) 1297 { 1298 1299 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1300 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1301 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1302 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1303 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1304 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1305 moea_initialized = TRUE; 1306 } 1307 1308 boolean_t 1309 moea_is_referenced(mmu_t mmu, vm_page_t m) 1310 { 1311 boolean_t rv; 1312 1313 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1314 ("moea_is_referenced: page %p is not managed", m)); 1315 rw_wlock(&pvh_global_lock); 1316 rv = moea_query_bit(m, PTE_REF); 1317 rw_wunlock(&pvh_global_lock); 1318 return (rv); 1319 } 1320 1321 boolean_t 1322 moea_is_modified(mmu_t mmu, vm_page_t m) 1323 { 1324 boolean_t rv; 1325 1326 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1327 ("moea_is_modified: page %p is not managed", m)); 1328 1329 /* 1330 * If the page is not busied then this check is racy. 1331 */ 1332 if (!pmap_page_is_write_mapped(m)) 1333 return (FALSE); 1334 1335 rw_wlock(&pvh_global_lock); 1336 rv = moea_query_bit(m, PTE_CHG); 1337 rw_wunlock(&pvh_global_lock); 1338 return (rv); 1339 } 1340 1341 boolean_t 1342 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1343 { 1344 struct pvo_entry *pvo; 1345 boolean_t rv; 1346 1347 PMAP_LOCK(pmap); 1348 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1349 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1350 PMAP_UNLOCK(pmap); 1351 return (rv); 1352 } 1353 1354 void 1355 moea_clear_modify(mmu_t mmu, vm_page_t m) 1356 { 1357 1358 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1359 ("moea_clear_modify: page %p is not managed", m)); 1360 vm_page_assert_busied(m); 1361 1362 if (!pmap_page_is_write_mapped(m)) 1363 return; 1364 rw_wlock(&pvh_global_lock); 1365 moea_clear_bit(m, PTE_CHG); 1366 rw_wunlock(&pvh_global_lock); 1367 } 1368 1369 /* 1370 * Clear the write and modified bits in each of the given page's mappings. 1371 */ 1372 void 1373 moea_remove_write(mmu_t mmu, vm_page_t m) 1374 { 1375 struct pvo_entry *pvo; 1376 struct pte *pt; 1377 pmap_t pmap; 1378 u_int lo; 1379 1380 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1381 ("moea_remove_write: page %p is not managed", m)); 1382 vm_page_assert_busied(m); 1383 1384 if (!pmap_page_is_write_mapped(m)) 1385 return; 1386 rw_wlock(&pvh_global_lock); 1387 lo = moea_attr_fetch(m); 1388 powerpc_sync(); 1389 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1390 pmap = pvo->pvo_pmap; 1391 PMAP_LOCK(pmap); 1392 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1393 pt = moea_pvo_to_pte(pvo, -1); 1394 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1395 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1396 if (pt != NULL) { 1397 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1398 lo |= pvo->pvo_pte.pte.pte_lo; 1399 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1400 moea_pte_change(pt, &pvo->pvo_pte.pte, 1401 pvo->pvo_vaddr); 1402 mtx_unlock(&moea_table_mutex); 1403 } 1404 } 1405 PMAP_UNLOCK(pmap); 1406 } 1407 if ((lo & PTE_CHG) != 0) { 1408 moea_attr_clear(m, PTE_CHG); 1409 vm_page_dirty(m); 1410 } 1411 vm_page_aflag_clear(m, PGA_WRITEABLE); 1412 rw_wunlock(&pvh_global_lock); 1413 } 1414 1415 /* 1416 * moea_ts_referenced: 1417 * 1418 * Return a count of reference bits for a page, clearing those bits. 1419 * It is not necessary for every reference bit to be cleared, but it 1420 * is necessary that 0 only be returned when there are truly no 1421 * reference bits set. 1422 * 1423 * XXX: The exact number of bits to check and clear is a matter that 1424 * should be tested and standardized at some point in the future for 1425 * optimal aging of shared pages. 1426 */ 1427 int 1428 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1429 { 1430 int count; 1431 1432 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1433 ("moea_ts_referenced: page %p is not managed", m)); 1434 rw_wlock(&pvh_global_lock); 1435 count = moea_clear_bit(m, PTE_REF); 1436 rw_wunlock(&pvh_global_lock); 1437 return (count); 1438 } 1439 1440 /* 1441 * Modify the WIMG settings of all mappings for a page. 1442 */ 1443 void 1444 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1445 { 1446 struct pvo_entry *pvo; 1447 struct pvo_head *pvo_head; 1448 struct pte *pt; 1449 pmap_t pmap; 1450 u_int lo; 1451 1452 if ((m->oflags & VPO_UNMANAGED) != 0) { 1453 m->md.mdpg_cache_attrs = ma; 1454 return; 1455 } 1456 1457 rw_wlock(&pvh_global_lock); 1458 pvo_head = vm_page_to_pvoh(m); 1459 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1460 1461 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1462 pmap = pvo->pvo_pmap; 1463 PMAP_LOCK(pmap); 1464 pt = moea_pvo_to_pte(pvo, -1); 1465 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1466 pvo->pvo_pte.pte.pte_lo |= lo; 1467 if (pt != NULL) { 1468 moea_pte_change(pt, &pvo->pvo_pte.pte, 1469 pvo->pvo_vaddr); 1470 if (pvo->pvo_pmap == kernel_pmap) 1471 isync(); 1472 } 1473 mtx_unlock(&moea_table_mutex); 1474 PMAP_UNLOCK(pmap); 1475 } 1476 m->md.mdpg_cache_attrs = ma; 1477 rw_wunlock(&pvh_global_lock); 1478 } 1479 1480 /* 1481 * Map a wired page into kernel virtual address space. 1482 */ 1483 void 1484 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1485 { 1486 1487 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1488 } 1489 1490 void 1491 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1492 { 1493 u_int pte_lo; 1494 int error; 1495 1496 #if 0 1497 if (va < VM_MIN_KERNEL_ADDRESS) 1498 panic("moea_kenter: attempt to enter non-kernel address %#x", 1499 va); 1500 #endif 1501 1502 pte_lo = moea_calc_wimg(pa, ma); 1503 1504 PMAP_LOCK(kernel_pmap); 1505 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1506 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1507 1508 if (error != 0 && error != ENOENT) 1509 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1510 pa, error); 1511 1512 PMAP_UNLOCK(kernel_pmap); 1513 } 1514 1515 /* 1516 * Extract the physical page address associated with the given kernel virtual 1517 * address. 1518 */ 1519 vm_paddr_t 1520 moea_kextract(mmu_t mmu, vm_offset_t va) 1521 { 1522 struct pvo_entry *pvo; 1523 vm_paddr_t pa; 1524 1525 /* 1526 * Allow direct mappings on 32-bit OEA 1527 */ 1528 if (va < VM_MIN_KERNEL_ADDRESS) { 1529 return (va); 1530 } 1531 1532 PMAP_LOCK(kernel_pmap); 1533 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1534 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1535 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1536 PMAP_UNLOCK(kernel_pmap); 1537 return (pa); 1538 } 1539 1540 /* 1541 * Remove a wired page from kernel virtual address space. 1542 */ 1543 void 1544 moea_kremove(mmu_t mmu, vm_offset_t va) 1545 { 1546 1547 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1548 } 1549 1550 /* 1551 * Provide a kernel pointer corresponding to a given userland pointer. 1552 * The returned pointer is valid until the next time this function is 1553 * called in this thread. This is used internally in copyin/copyout. 1554 */ 1555 int 1556 moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1557 void **kaddr, size_t ulen, size_t *klen) 1558 { 1559 size_t l; 1560 register_t vsid; 1561 1562 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1563 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1564 if (l > ulen) 1565 l = ulen; 1566 if (klen) 1567 *klen = l; 1568 else if (l != ulen) 1569 return (EFAULT); 1570 1571 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1572 1573 /* Mark segment no-execute */ 1574 vsid |= SR_N; 1575 1576 /* If we have already set this VSID, we can just return */ 1577 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1578 return (0); 1579 1580 __asm __volatile("isync"); 1581 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1582 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1583 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1584 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1585 1586 return (0); 1587 } 1588 1589 /* 1590 * Figure out where a given kernel pointer (usually in a fault) points 1591 * to from the VM's perspective, potentially remapping into userland's 1592 * address space. 1593 */ 1594 static int 1595 moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1596 vm_offset_t *decoded_addr) 1597 { 1598 vm_offset_t user_sr; 1599 1600 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1601 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1602 addr &= ADDR_PIDX | ADDR_POFF; 1603 addr |= user_sr << ADDR_SR_SHFT; 1604 *decoded_addr = addr; 1605 *is_user = 1; 1606 } else { 1607 *decoded_addr = addr; 1608 *is_user = 0; 1609 } 1610 1611 return (0); 1612 } 1613 1614 /* 1615 * Map a range of physical addresses into kernel virtual address space. 1616 * 1617 * The value passed in *virt is a suggested virtual address for the mapping. 1618 * Architectures which can support a direct-mapped physical to virtual region 1619 * can return the appropriate address within that region, leaving '*virt' 1620 * unchanged. We cannot and therefore do not; *virt is updated with the 1621 * first usable address after the mapped region. 1622 */ 1623 vm_offset_t 1624 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1625 vm_paddr_t pa_end, int prot) 1626 { 1627 vm_offset_t sva, va; 1628 1629 sva = *virt; 1630 va = sva; 1631 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1632 moea_kenter(mmu, va, pa_start); 1633 *virt = va; 1634 return (sva); 1635 } 1636 1637 /* 1638 * Returns true if the pmap's pv is one of the first 1639 * 16 pvs linked to from this page. This count may 1640 * be changed upwards or downwards in the future; it 1641 * is only necessary that true be returned for a small 1642 * subset of pmaps for proper page aging. 1643 */ 1644 boolean_t 1645 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1646 { 1647 int loops; 1648 struct pvo_entry *pvo; 1649 boolean_t rv; 1650 1651 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1652 ("moea_page_exists_quick: page %p is not managed", m)); 1653 loops = 0; 1654 rv = FALSE; 1655 rw_wlock(&pvh_global_lock); 1656 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1657 if (pvo->pvo_pmap == pmap) { 1658 rv = TRUE; 1659 break; 1660 } 1661 if (++loops >= 16) 1662 break; 1663 } 1664 rw_wunlock(&pvh_global_lock); 1665 return (rv); 1666 } 1667 1668 void 1669 moea_page_init(mmu_t mmu __unused, vm_page_t m) 1670 { 1671 1672 m->md.mdpg_attrs = 0; 1673 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1674 LIST_INIT(&m->md.mdpg_pvoh); 1675 } 1676 1677 /* 1678 * Return the number of managed mappings to the given physical page 1679 * that are wired. 1680 */ 1681 int 1682 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1683 { 1684 struct pvo_entry *pvo; 1685 int count; 1686 1687 count = 0; 1688 if ((m->oflags & VPO_UNMANAGED) != 0) 1689 return (count); 1690 rw_wlock(&pvh_global_lock); 1691 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1692 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1693 count++; 1694 rw_wunlock(&pvh_global_lock); 1695 return (count); 1696 } 1697 1698 static u_int moea_vsidcontext; 1699 1700 void 1701 moea_pinit(mmu_t mmu, pmap_t pmap) 1702 { 1703 int i, mask; 1704 u_int entropy; 1705 1706 RB_INIT(&pmap->pmap_pvo); 1707 1708 entropy = 0; 1709 __asm __volatile("mftb %0" : "=r"(entropy)); 1710 1711 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1712 == NULL) { 1713 pmap->pmap_phys = pmap; 1714 } 1715 1716 1717 mtx_lock(&moea_vsid_mutex); 1718 /* 1719 * Allocate some segment registers for this pmap. 1720 */ 1721 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1722 u_int hash, n; 1723 1724 /* 1725 * Create a new value by mutiplying by a prime and adding in 1726 * entropy from the timebase register. This is to make the 1727 * VSID more random so that the PT hash function collides 1728 * less often. (Note that the prime casues gcc to do shifts 1729 * instead of a multiply.) 1730 */ 1731 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1732 hash = moea_vsidcontext & (NPMAPS - 1); 1733 if (hash == 0) /* 0 is special, avoid it */ 1734 continue; 1735 n = hash >> 5; 1736 mask = 1 << (hash & (VSID_NBPW - 1)); 1737 hash = (moea_vsidcontext & 0xfffff); 1738 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1739 /* anything free in this bucket? */ 1740 if (moea_vsid_bitmap[n] == 0xffffffff) { 1741 entropy = (moea_vsidcontext >> 20); 1742 continue; 1743 } 1744 i = ffs(~moea_vsid_bitmap[n]) - 1; 1745 mask = 1 << i; 1746 hash &= rounddown2(0xfffff, VSID_NBPW); 1747 hash |= i; 1748 } 1749 KASSERT(!(moea_vsid_bitmap[n] & mask), 1750 ("Allocating in-use VSID group %#x\n", hash)); 1751 moea_vsid_bitmap[n] |= mask; 1752 for (i = 0; i < 16; i++) 1753 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1754 mtx_unlock(&moea_vsid_mutex); 1755 return; 1756 } 1757 1758 mtx_unlock(&moea_vsid_mutex); 1759 panic("moea_pinit: out of segments"); 1760 } 1761 1762 /* 1763 * Initialize the pmap associated with process 0. 1764 */ 1765 void 1766 moea_pinit0(mmu_t mmu, pmap_t pm) 1767 { 1768 1769 PMAP_LOCK_INIT(pm); 1770 moea_pinit(mmu, pm); 1771 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1772 } 1773 1774 /* 1775 * Set the physical protection on the specified range of this map as requested. 1776 */ 1777 void 1778 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1779 vm_prot_t prot) 1780 { 1781 struct pvo_entry *pvo, *tpvo, key; 1782 struct pte *pt; 1783 1784 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1785 ("moea_protect: non current pmap")); 1786 1787 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1788 moea_remove(mmu, pm, sva, eva); 1789 return; 1790 } 1791 1792 rw_wlock(&pvh_global_lock); 1793 PMAP_LOCK(pm); 1794 key.pvo_vaddr = sva; 1795 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1796 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1797 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1798 1799 /* 1800 * Grab the PTE pointer before we diddle with the cached PTE 1801 * copy. 1802 */ 1803 pt = moea_pvo_to_pte(pvo, -1); 1804 /* 1805 * Change the protection of the page. 1806 */ 1807 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1808 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1809 1810 /* 1811 * If the PVO is in the page table, update that pte as well. 1812 */ 1813 if (pt != NULL) { 1814 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1815 mtx_unlock(&moea_table_mutex); 1816 } 1817 } 1818 rw_wunlock(&pvh_global_lock); 1819 PMAP_UNLOCK(pm); 1820 } 1821 1822 /* 1823 * Map a list of wired pages into kernel virtual address space. This is 1824 * intended for temporary mappings which do not need page modification or 1825 * references recorded. Existing mappings in the region are overwritten. 1826 */ 1827 void 1828 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1829 { 1830 vm_offset_t va; 1831 1832 va = sva; 1833 while (count-- > 0) { 1834 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1835 va += PAGE_SIZE; 1836 m++; 1837 } 1838 } 1839 1840 /* 1841 * Remove page mappings from kernel virtual address space. Intended for 1842 * temporary mappings entered by moea_qenter. 1843 */ 1844 void 1845 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1846 { 1847 vm_offset_t va; 1848 1849 va = sva; 1850 while (count-- > 0) { 1851 moea_kremove(mmu, va); 1852 va += PAGE_SIZE; 1853 } 1854 } 1855 1856 void 1857 moea_release(mmu_t mmu, pmap_t pmap) 1858 { 1859 int idx, mask; 1860 1861 /* 1862 * Free segment register's VSID 1863 */ 1864 if (pmap->pm_sr[0] == 0) 1865 panic("moea_release"); 1866 1867 mtx_lock(&moea_vsid_mutex); 1868 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1869 mask = 1 << (idx % VSID_NBPW); 1870 idx /= VSID_NBPW; 1871 moea_vsid_bitmap[idx] &= ~mask; 1872 mtx_unlock(&moea_vsid_mutex); 1873 } 1874 1875 /* 1876 * Remove the given range of addresses from the specified map. 1877 */ 1878 void 1879 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1880 { 1881 struct pvo_entry *pvo, *tpvo, key; 1882 1883 rw_wlock(&pvh_global_lock); 1884 PMAP_LOCK(pm); 1885 key.pvo_vaddr = sva; 1886 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1887 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1888 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1889 moea_pvo_remove(pvo, -1); 1890 } 1891 PMAP_UNLOCK(pm); 1892 rw_wunlock(&pvh_global_lock); 1893 } 1894 1895 /* 1896 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1897 * will reflect changes in pte's back to the vm_page. 1898 */ 1899 void 1900 moea_remove_all(mmu_t mmu, vm_page_t m) 1901 { 1902 struct pvo_head *pvo_head; 1903 struct pvo_entry *pvo, *next_pvo; 1904 pmap_t pmap; 1905 1906 rw_wlock(&pvh_global_lock); 1907 pvo_head = vm_page_to_pvoh(m); 1908 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1909 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1910 1911 pmap = pvo->pvo_pmap; 1912 PMAP_LOCK(pmap); 1913 moea_pvo_remove(pvo, -1); 1914 PMAP_UNLOCK(pmap); 1915 } 1916 if ((m->a.flags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1917 moea_attr_clear(m, PTE_CHG); 1918 vm_page_dirty(m); 1919 } 1920 vm_page_aflag_clear(m, PGA_WRITEABLE); 1921 rw_wunlock(&pvh_global_lock); 1922 } 1923 1924 /* 1925 * Allocate a physical page of memory directly from the phys_avail map. 1926 * Can only be called from moea_bootstrap before avail start and end are 1927 * calculated. 1928 */ 1929 static vm_offset_t 1930 moea_bootstrap_alloc(vm_size_t size, u_int align) 1931 { 1932 vm_offset_t s, e; 1933 int i, j; 1934 1935 size = round_page(size); 1936 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1937 if (align != 0) 1938 s = roundup2(phys_avail[i], align); 1939 else 1940 s = phys_avail[i]; 1941 e = s + size; 1942 1943 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1944 continue; 1945 1946 if (s == phys_avail[i]) { 1947 phys_avail[i] += size; 1948 } else if (e == phys_avail[i + 1]) { 1949 phys_avail[i + 1] -= size; 1950 } else { 1951 for (j = phys_avail_count * 2; j > i; j -= 2) { 1952 phys_avail[j] = phys_avail[j - 2]; 1953 phys_avail[j + 1] = phys_avail[j - 1]; 1954 } 1955 1956 phys_avail[i + 3] = phys_avail[i + 1]; 1957 phys_avail[i + 1] = s; 1958 phys_avail[i + 2] = e; 1959 phys_avail_count++; 1960 } 1961 1962 return (s); 1963 } 1964 panic("moea_bootstrap_alloc: could not allocate memory"); 1965 } 1966 1967 static void 1968 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1969 { 1970 __syncicache((void *)pa, len); 1971 } 1972 1973 static int 1974 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1975 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1976 { 1977 struct pvo_entry *pvo; 1978 u_int sr; 1979 int first; 1980 u_int ptegidx; 1981 int i; 1982 int bootstrap; 1983 1984 moea_pvo_enter_calls++; 1985 first = 0; 1986 bootstrap = 0; 1987 1988 /* 1989 * Compute the PTE Group index. 1990 */ 1991 va &= ~ADDR_POFF; 1992 sr = va_to_sr(pm->pm_sr, va); 1993 ptegidx = va_to_pteg(sr, va); 1994 1995 /* 1996 * Remove any existing mapping for this page. Reuse the pvo entry if 1997 * there is a mapping. 1998 */ 1999 mtx_lock(&moea_table_mutex); 2000 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2001 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2002 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 2003 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2004 (pte_lo & PTE_PP)) { 2005 /* 2006 * The PTE is not changing. Instead, this may 2007 * be a request to change the mapping's wired 2008 * attribute. 2009 */ 2010 mtx_unlock(&moea_table_mutex); 2011 if ((flags & PVO_WIRED) != 0 && 2012 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2013 pvo->pvo_vaddr |= PVO_WIRED; 2014 pm->pm_stats.wired_count++; 2015 } else if ((flags & PVO_WIRED) == 0 && 2016 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2017 pvo->pvo_vaddr &= ~PVO_WIRED; 2018 pm->pm_stats.wired_count--; 2019 } 2020 return (0); 2021 } 2022 moea_pvo_remove(pvo, -1); 2023 break; 2024 } 2025 } 2026 2027 /* 2028 * If we aren't overwriting a mapping, try to allocate. 2029 */ 2030 if (moea_initialized) { 2031 pvo = uma_zalloc(zone, M_NOWAIT); 2032 } else { 2033 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2034 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2035 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2036 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2037 } 2038 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2039 moea_bpvo_pool_index++; 2040 bootstrap = 1; 2041 } 2042 2043 if (pvo == NULL) { 2044 mtx_unlock(&moea_table_mutex); 2045 return (ENOMEM); 2046 } 2047 2048 moea_pvo_entries++; 2049 pvo->pvo_vaddr = va; 2050 pvo->pvo_pmap = pm; 2051 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2052 pvo->pvo_vaddr &= ~ADDR_POFF; 2053 if (flags & PVO_WIRED) 2054 pvo->pvo_vaddr |= PVO_WIRED; 2055 if (pvo_head != &moea_pvo_kunmanaged) 2056 pvo->pvo_vaddr |= PVO_MANAGED; 2057 if (bootstrap) 2058 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2059 2060 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2061 2062 /* 2063 * Add to pmap list 2064 */ 2065 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2066 2067 /* 2068 * Remember if the list was empty and therefore will be the first 2069 * item. 2070 */ 2071 if (LIST_FIRST(pvo_head) == NULL) 2072 first = 1; 2073 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2074 2075 if (pvo->pvo_vaddr & PVO_WIRED) 2076 pm->pm_stats.wired_count++; 2077 pm->pm_stats.resident_count++; 2078 2079 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2080 KASSERT(i < 8, ("Invalid PTE index")); 2081 if (i >= 0) { 2082 PVO_PTEGIDX_SET(pvo, i); 2083 } else { 2084 panic("moea_pvo_enter: overflow"); 2085 moea_pte_overflow++; 2086 } 2087 mtx_unlock(&moea_table_mutex); 2088 2089 return (first ? ENOENT : 0); 2090 } 2091 2092 static void 2093 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2094 { 2095 struct pte *pt; 2096 2097 /* 2098 * If there is an active pte entry, we need to deactivate it (and 2099 * save the ref & cfg bits). 2100 */ 2101 pt = moea_pvo_to_pte(pvo, pteidx); 2102 if (pt != NULL) { 2103 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2104 mtx_unlock(&moea_table_mutex); 2105 PVO_PTEGIDX_CLR(pvo); 2106 } else { 2107 moea_pte_overflow--; 2108 } 2109 2110 /* 2111 * Update our statistics. 2112 */ 2113 pvo->pvo_pmap->pm_stats.resident_count--; 2114 if (pvo->pvo_vaddr & PVO_WIRED) 2115 pvo->pvo_pmap->pm_stats.wired_count--; 2116 2117 /* 2118 * Remove this PVO from the PV and pmap lists. 2119 */ 2120 LIST_REMOVE(pvo, pvo_vlink); 2121 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2122 2123 /* 2124 * Save the REF/CHG bits into their cache if the page is managed. 2125 * Clear PGA_WRITEABLE if all mappings of the page have been removed. 2126 */ 2127 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2128 struct vm_page *pg; 2129 2130 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2131 if (pg != NULL) { 2132 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2133 (PTE_REF | PTE_CHG)); 2134 if (LIST_EMPTY(&pg->md.mdpg_pvoh)) 2135 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2136 } 2137 } 2138 2139 /* 2140 * Remove this from the overflow list and return it to the pool 2141 * if we aren't going to reuse it. 2142 */ 2143 LIST_REMOVE(pvo, pvo_olink); 2144 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2145 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2146 moea_upvo_zone, pvo); 2147 moea_pvo_entries--; 2148 moea_pvo_remove_calls++; 2149 } 2150 2151 static __inline int 2152 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2153 { 2154 int pteidx; 2155 2156 /* 2157 * We can find the actual pte entry without searching by grabbing 2158 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2159 * noticing the HID bit. 2160 */ 2161 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2162 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2163 pteidx ^= moea_pteg_mask * 8; 2164 2165 return (pteidx); 2166 } 2167 2168 static struct pvo_entry * 2169 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2170 { 2171 struct pvo_entry *pvo; 2172 int ptegidx; 2173 u_int sr; 2174 2175 va &= ~ADDR_POFF; 2176 sr = va_to_sr(pm->pm_sr, va); 2177 ptegidx = va_to_pteg(sr, va); 2178 2179 mtx_lock(&moea_table_mutex); 2180 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2181 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2182 if (pteidx_p) 2183 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2184 break; 2185 } 2186 } 2187 mtx_unlock(&moea_table_mutex); 2188 2189 return (pvo); 2190 } 2191 2192 static struct pte * 2193 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2194 { 2195 struct pte *pt; 2196 2197 /* 2198 * If we haven't been supplied the ptegidx, calculate it. 2199 */ 2200 if (pteidx == -1) { 2201 int ptegidx; 2202 u_int sr; 2203 2204 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2205 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2206 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2207 } 2208 2209 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2210 mtx_lock(&moea_table_mutex); 2211 2212 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2213 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2214 "valid pte index", pvo); 2215 } 2216 2217 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2218 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2219 "pvo but no valid pte", pvo); 2220 } 2221 2222 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2223 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2224 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2225 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2226 } 2227 2228 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2229 != 0) { 2230 panic("moea_pvo_to_pte: pvo %p pte does not match " 2231 "pte %p in moea_pteg_table", pvo, pt); 2232 } 2233 2234 mtx_assert(&moea_table_mutex, MA_OWNED); 2235 return (pt); 2236 } 2237 2238 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2239 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2240 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2241 } 2242 2243 mtx_unlock(&moea_table_mutex); 2244 return (NULL); 2245 } 2246 2247 /* 2248 * XXX: THIS STUFF SHOULD BE IN pte.c? 2249 */ 2250 int 2251 moea_pte_spill(vm_offset_t addr) 2252 { 2253 struct pvo_entry *source_pvo, *victim_pvo; 2254 struct pvo_entry *pvo; 2255 int ptegidx, i, j; 2256 u_int sr; 2257 struct pteg *pteg; 2258 struct pte *pt; 2259 2260 moea_pte_spills++; 2261 2262 sr = mfsrin(addr); 2263 ptegidx = va_to_pteg(sr, addr); 2264 2265 /* 2266 * Have to substitute some entry. Use the primary hash for this. 2267 * Use low bits of timebase as random generator. 2268 */ 2269 pteg = &moea_pteg_table[ptegidx]; 2270 mtx_lock(&moea_table_mutex); 2271 __asm __volatile("mftb %0" : "=r"(i)); 2272 i &= 7; 2273 pt = &pteg->pt[i]; 2274 2275 source_pvo = NULL; 2276 victim_pvo = NULL; 2277 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2278 /* 2279 * We need to find a pvo entry for this address. 2280 */ 2281 if (source_pvo == NULL && 2282 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2283 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2284 /* 2285 * Now found an entry to be spilled into the pteg. 2286 * The PTE is now valid, so we know it's active. 2287 */ 2288 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2289 2290 if (j >= 0) { 2291 PVO_PTEGIDX_SET(pvo, j); 2292 moea_pte_overflow--; 2293 mtx_unlock(&moea_table_mutex); 2294 return (1); 2295 } 2296 2297 source_pvo = pvo; 2298 2299 if (victim_pvo != NULL) 2300 break; 2301 } 2302 2303 /* 2304 * We also need the pvo entry of the victim we are replacing 2305 * so save the R & C bits of the PTE. 2306 */ 2307 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2308 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2309 victim_pvo = pvo; 2310 if (source_pvo != NULL) 2311 break; 2312 } 2313 } 2314 2315 if (source_pvo == NULL) { 2316 mtx_unlock(&moea_table_mutex); 2317 return (0); 2318 } 2319 2320 if (victim_pvo == NULL) { 2321 if ((pt->pte_hi & PTE_HID) == 0) 2322 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2323 "entry", pt); 2324 2325 /* 2326 * If this is a secondary PTE, we need to search it's primary 2327 * pvo bucket for the matching PVO. 2328 */ 2329 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2330 pvo_olink) { 2331 /* 2332 * We also need the pvo entry of the victim we are 2333 * replacing so save the R & C bits of the PTE. 2334 */ 2335 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2336 victim_pvo = pvo; 2337 break; 2338 } 2339 } 2340 2341 if (victim_pvo == NULL) 2342 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2343 "entry", pt); 2344 } 2345 2346 /* 2347 * We are invalidating the TLB entry for the EA we are replacing even 2348 * though it's valid. If we don't, we lose any ref/chg bit changes 2349 * contained in the TLB entry. 2350 */ 2351 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2352 2353 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2354 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2355 2356 PVO_PTEGIDX_CLR(victim_pvo); 2357 PVO_PTEGIDX_SET(source_pvo, i); 2358 moea_pte_replacements++; 2359 2360 mtx_unlock(&moea_table_mutex); 2361 return (1); 2362 } 2363 2364 static __inline struct pvo_entry * 2365 moea_pte_spillable_ident(u_int ptegidx) 2366 { 2367 struct pte *pt; 2368 struct pvo_entry *pvo_walk, *pvo = NULL; 2369 2370 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2371 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2372 continue; 2373 2374 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2375 continue; 2376 2377 pt = moea_pvo_to_pte(pvo_walk, -1); 2378 2379 if (pt == NULL) 2380 continue; 2381 2382 pvo = pvo_walk; 2383 2384 mtx_unlock(&moea_table_mutex); 2385 if (!(pt->pte_lo & PTE_REF)) 2386 return (pvo_walk); 2387 } 2388 2389 return (pvo); 2390 } 2391 2392 static int 2393 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2394 { 2395 struct pte *pt; 2396 struct pvo_entry *victim_pvo; 2397 int i; 2398 int victim_idx; 2399 u_int pteg_bkpidx = ptegidx; 2400 2401 mtx_assert(&moea_table_mutex, MA_OWNED); 2402 2403 /* 2404 * First try primary hash. 2405 */ 2406 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2407 if ((pt->pte_hi & PTE_VALID) == 0) { 2408 pvo_pt->pte_hi &= ~PTE_HID; 2409 moea_pte_set(pt, pvo_pt); 2410 return (i); 2411 } 2412 } 2413 2414 /* 2415 * Now try secondary hash. 2416 */ 2417 ptegidx ^= moea_pteg_mask; 2418 2419 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2420 if ((pt->pte_hi & PTE_VALID) == 0) { 2421 pvo_pt->pte_hi |= PTE_HID; 2422 moea_pte_set(pt, pvo_pt); 2423 return (i); 2424 } 2425 } 2426 2427 /* Try again, but this time try to force a PTE out. */ 2428 ptegidx = pteg_bkpidx; 2429 2430 victim_pvo = moea_pte_spillable_ident(ptegidx); 2431 if (victim_pvo == NULL) { 2432 ptegidx ^= moea_pteg_mask; 2433 victim_pvo = moea_pte_spillable_ident(ptegidx); 2434 } 2435 2436 if (victim_pvo == NULL) { 2437 panic("moea_pte_insert: overflow"); 2438 return (-1); 2439 } 2440 2441 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2442 2443 if (pteg_bkpidx == ptegidx) 2444 pvo_pt->pte_hi &= ~PTE_HID; 2445 else 2446 pvo_pt->pte_hi |= PTE_HID; 2447 2448 /* 2449 * Synchronize the sacrifice PTE with its PVO, then mark both 2450 * invalid. The PVO will be reused when/if the VM system comes 2451 * here after a fault. 2452 */ 2453 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2454 2455 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2456 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2457 2458 /* 2459 * Set the new PTE. 2460 */ 2461 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2462 PVO_PTEGIDX_CLR(victim_pvo); 2463 moea_pte_overflow++; 2464 moea_pte_set(pt, pvo_pt); 2465 2466 return (victim_idx & 7); 2467 } 2468 2469 static boolean_t 2470 moea_query_bit(vm_page_t m, int ptebit) 2471 { 2472 struct pvo_entry *pvo; 2473 struct pte *pt; 2474 2475 rw_assert(&pvh_global_lock, RA_WLOCKED); 2476 if (moea_attr_fetch(m) & ptebit) 2477 return (TRUE); 2478 2479 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2480 2481 /* 2482 * See if we saved the bit off. If so, cache it and return 2483 * success. 2484 */ 2485 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2486 moea_attr_save(m, ptebit); 2487 return (TRUE); 2488 } 2489 } 2490 2491 /* 2492 * No luck, now go through the hard part of looking at the PTEs 2493 * themselves. Sync so that any pending REF/CHG bits are flushed to 2494 * the PTEs. 2495 */ 2496 powerpc_sync(); 2497 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2498 2499 /* 2500 * See if this pvo has a valid PTE. if so, fetch the 2501 * REF/CHG bits from the valid PTE. If the appropriate 2502 * ptebit is set, cache it and return success. 2503 */ 2504 pt = moea_pvo_to_pte(pvo, -1); 2505 if (pt != NULL) { 2506 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2507 mtx_unlock(&moea_table_mutex); 2508 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2509 moea_attr_save(m, ptebit); 2510 return (TRUE); 2511 } 2512 } 2513 } 2514 2515 return (FALSE); 2516 } 2517 2518 static u_int 2519 moea_clear_bit(vm_page_t m, int ptebit) 2520 { 2521 u_int count; 2522 struct pvo_entry *pvo; 2523 struct pte *pt; 2524 2525 rw_assert(&pvh_global_lock, RA_WLOCKED); 2526 2527 /* 2528 * Clear the cached value. 2529 */ 2530 moea_attr_clear(m, ptebit); 2531 2532 /* 2533 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2534 * we can reset the right ones). note that since the pvo entries and 2535 * list heads are accessed via BAT0 and are never placed in the page 2536 * table, we don't have to worry about further accesses setting the 2537 * REF/CHG bits. 2538 */ 2539 powerpc_sync(); 2540 2541 /* 2542 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2543 * valid pte clear the ptebit from the valid pte. 2544 */ 2545 count = 0; 2546 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2547 pt = moea_pvo_to_pte(pvo, -1); 2548 if (pt != NULL) { 2549 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2550 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2551 count++; 2552 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2553 } 2554 mtx_unlock(&moea_table_mutex); 2555 } 2556 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2557 } 2558 2559 return (count); 2560 } 2561 2562 /* 2563 * Return true if the physical range is encompassed by the battable[idx] 2564 */ 2565 static int 2566 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2567 { 2568 u_int prot; 2569 u_int32_t start; 2570 u_int32_t end; 2571 u_int32_t bat_ble; 2572 2573 /* 2574 * Return immediately if not a valid mapping 2575 */ 2576 if (!(battable[idx].batu & BAT_Vs)) 2577 return (EINVAL); 2578 2579 /* 2580 * The BAT entry must be cache-inhibited, guarded, and r/w 2581 * so it can function as an i/o page 2582 */ 2583 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2584 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2585 return (EPERM); 2586 2587 /* 2588 * The address should be within the BAT range. Assume that the 2589 * start address in the BAT has the correct alignment (thus 2590 * not requiring masking) 2591 */ 2592 start = battable[idx].batl & BAT_PBS; 2593 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2594 end = start | (bat_ble << 15) | 0x7fff; 2595 2596 if ((pa < start) || ((pa + size) > end)) 2597 return (ERANGE); 2598 2599 return (0); 2600 } 2601 2602 boolean_t 2603 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2604 { 2605 int i; 2606 2607 /* 2608 * This currently does not work for entries that 2609 * overlap 256M BAT segments. 2610 */ 2611 2612 for(i = 0; i < 16; i++) 2613 if (moea_bat_mapped(i, pa, size) == 0) 2614 return (0); 2615 2616 return (EFAULT); 2617 } 2618 2619 /* 2620 * Map a set of physical memory pages into the kernel virtual 2621 * address space. Return a pointer to where it is mapped. This 2622 * routine is intended to be used for mapping device memory, 2623 * NOT real memory. 2624 */ 2625 void * 2626 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2627 { 2628 2629 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2630 } 2631 2632 void * 2633 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2634 { 2635 vm_offset_t va, tmpva, ppa, offset; 2636 int i; 2637 2638 ppa = trunc_page(pa); 2639 offset = pa & PAGE_MASK; 2640 size = roundup(offset + size, PAGE_SIZE); 2641 2642 /* 2643 * If the physical address lies within a valid BAT table entry, 2644 * return the 1:1 mapping. This currently doesn't work 2645 * for regions that overlap 256M BAT segments. 2646 */ 2647 for (i = 0; i < 16; i++) { 2648 if (moea_bat_mapped(i, pa, size) == 0) 2649 return ((void *) pa); 2650 } 2651 2652 va = kva_alloc(size); 2653 if (!va) 2654 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2655 2656 for (tmpva = va; size > 0;) { 2657 moea_kenter_attr(mmu, tmpva, ppa, ma); 2658 tlbie(tmpva); 2659 size -= PAGE_SIZE; 2660 tmpva += PAGE_SIZE; 2661 ppa += PAGE_SIZE; 2662 } 2663 2664 return ((void *)(va + offset)); 2665 } 2666 2667 void 2668 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2669 { 2670 vm_offset_t base, offset; 2671 2672 /* 2673 * If this is outside kernel virtual space, then it's a 2674 * battable entry and doesn't require unmapping 2675 */ 2676 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2677 base = trunc_page(va); 2678 offset = va & PAGE_MASK; 2679 size = roundup(offset + size, PAGE_SIZE); 2680 kva_free(base, size); 2681 } 2682 } 2683 2684 static void 2685 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2686 { 2687 struct pvo_entry *pvo; 2688 vm_offset_t lim; 2689 vm_paddr_t pa; 2690 vm_size_t len; 2691 2692 PMAP_LOCK(pm); 2693 while (sz > 0) { 2694 lim = round_page(va + 1); 2695 len = MIN(lim - va, sz); 2696 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2697 if (pvo != NULL) { 2698 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2699 (va & ADDR_POFF); 2700 moea_syncicache(pa, len); 2701 } 2702 va += len; 2703 sz -= len; 2704 } 2705 PMAP_UNLOCK(pm); 2706 } 2707 2708 void 2709 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2710 { 2711 2712 *va = (void *)pa; 2713 } 2714 2715 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2716 2717 void 2718 moea_scan_init(mmu_t mmu) 2719 { 2720 struct pvo_entry *pvo; 2721 vm_offset_t va; 2722 int i; 2723 2724 if (!do_minidump) { 2725 /* Initialize phys. segments for dumpsys(). */ 2726 memset(&dump_map, 0, sizeof(dump_map)); 2727 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2728 for (i = 0; i < pregions_sz; i++) { 2729 dump_map[i].pa_start = pregions[i].mr_start; 2730 dump_map[i].pa_size = pregions[i].mr_size; 2731 } 2732 return; 2733 } 2734 2735 /* Virtual segments for minidumps: */ 2736 memset(&dump_map, 0, sizeof(dump_map)); 2737 2738 /* 1st: kernel .data and .bss. */ 2739 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2740 dump_map[0].pa_size = 2741 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2742 2743 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2744 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2745 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2746 2747 /* 3rd: kernel VM. */ 2748 va = dump_map[1].pa_start + dump_map[1].pa_size; 2749 /* Find start of next chunk (from va). */ 2750 while (va < virtual_end) { 2751 /* Don't dump the buffer cache. */ 2752 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2753 va = kmi.buffer_eva; 2754 continue; 2755 } 2756 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2757 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2758 break; 2759 va += PAGE_SIZE; 2760 } 2761 if (va < virtual_end) { 2762 dump_map[2].pa_start = va; 2763 va += PAGE_SIZE; 2764 /* Find last page in chunk. */ 2765 while (va < virtual_end) { 2766 /* Don't run into the buffer cache. */ 2767 if (va == kmi.buffer_sva) 2768 break; 2769 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2770 NULL); 2771 if (pvo == NULL || 2772 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2773 break; 2774 va += PAGE_SIZE; 2775 } 2776 dump_map[2].pa_size = va - dump_map[2].pa_start; 2777 } 2778 } 2779