1 /* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /* 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /* 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/powerpc.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/sr.h> 151 152 #define PMAP_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define PMAP_LOCK(pm) 157 #define PMAP_UNLOCK(pm) 158 159 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 160 #define TLBSYNC() __asm __volatile("tlbsync"); 161 #define SYNC() __asm __volatile("sync"); 162 #define EIEIO() __asm __volatile("eieio"); 163 164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 165 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 167 168 #define PVO_PTEGIDX_MASK 0x0007 /* which PTEG slot */ 169 #define PVO_PTEGIDX_VALID 0x0008 /* slot is valid */ 170 #define PVO_WIRED 0x0010 /* PVO entry is wired */ 171 #define PVO_MANAGED 0x0020 /* PVO entry is managed */ 172 #define PVO_EXECUTABLE 0x0040 /* PVO entry is executable */ 173 #define PVO_BOOTSTRAP 0x0080 /* PVO entry allocated during 174 bootstrap */ 175 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 176 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 177 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 178 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 179 #define PVO_PTEGIDX_CLR(pvo) \ 180 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 181 #define PVO_PTEGIDX_SET(pvo, i) \ 182 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 183 184 #define PMAP_PVO_CHECK(pvo) 185 186 struct ofw_map { 187 vm_offset_t om_va; 188 vm_size_t om_len; 189 vm_offset_t om_pa; 190 u_int om_mode; 191 }; 192 193 int pmap_bootstrapped = 0; 194 195 /* 196 * Virtual and physical address of message buffer. 197 */ 198 struct msgbuf *msgbufp; 199 vm_offset_t msgbuf_phys; 200 201 int pmap_pagedaemon_waken; 202 203 /* 204 * Map of physical memory regions. 205 */ 206 vm_offset_t phys_avail[128]; 207 u_int phys_avail_count; 208 static struct mem_region *regions; 209 static struct mem_region *pregions; 210 int regions_sz, pregions_sz; 211 static struct ofw_map *translations; 212 213 /* 214 * First and last available kernel virtual addresses. 215 */ 216 vm_offset_t virtual_avail; 217 vm_offset_t virtual_end; 218 vm_offset_t kernel_vm_end; 219 220 /* 221 * Kernel pmap. 222 */ 223 struct pmap kernel_pmap_store; 224 extern struct pmap ofw_pmap; 225 226 /* 227 * PTEG data. 228 */ 229 static struct pteg *pmap_pteg_table; 230 u_int pmap_pteg_count; 231 u_int pmap_pteg_mask; 232 233 /* 234 * PVO data. 235 */ 236 struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 237 struct pvo_head pmap_pvo_kunmanaged = 238 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 239 struct pvo_head pmap_pvo_unmanaged = 240 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 241 242 uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 243 uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 244 245 #define BPVO_POOL_SIZE 32768 246 static struct pvo_entry *pmap_bpvo_pool; 247 static int pmap_bpvo_pool_index = 0; 248 249 #define VSID_NBPW (sizeof(u_int32_t) * 8) 250 static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 251 252 static boolean_t pmap_initialized = FALSE; 253 254 /* 255 * Statistics. 256 */ 257 u_int pmap_pte_valid = 0; 258 u_int pmap_pte_overflow = 0; 259 u_int pmap_pte_replacements = 0; 260 u_int pmap_pvo_entries = 0; 261 u_int pmap_pvo_enter_calls = 0; 262 u_int pmap_pvo_remove_calls = 0; 263 u_int pmap_pte_spills = 0; 264 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 265 0, ""); 266 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 267 &pmap_pte_overflow, 0, ""); 268 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 269 &pmap_pte_replacements, 0, ""); 270 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 271 0, ""); 272 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 273 &pmap_pvo_enter_calls, 0, ""); 274 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 275 &pmap_pvo_remove_calls, 0, ""); 276 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 277 &pmap_pte_spills, 0, ""); 278 279 struct pvo_entry *pmap_pvo_zeropage; 280 281 vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 282 u_int pmap_rkva_count = 4; 283 284 /* 285 * Allocate physical memory for use in pmap_bootstrap. 286 */ 287 static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 288 289 /* 290 * PTE calls. 291 */ 292 static int pmap_pte_insert(u_int, struct pte *); 293 294 /* 295 * PVO calls. 296 */ 297 static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 298 vm_offset_t, vm_offset_t, u_int, int); 299 static void pmap_pvo_remove(struct pvo_entry *, int); 300 static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 301 static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 302 303 /* 304 * Utility routines. 305 */ 306 static struct pvo_entry *pmap_rkva_alloc(void); 307 static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 308 struct pte *, int *); 309 static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 310 static void pmap_syncicache(vm_offset_t, vm_size_t); 311 static boolean_t pmap_query_bit(vm_page_t, int); 312 static u_int pmap_clear_bit(vm_page_t, int, int *); 313 static void tlbia(void); 314 315 static __inline int 316 va_to_sr(u_int *sr, vm_offset_t va) 317 { 318 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 319 } 320 321 static __inline u_int 322 va_to_pteg(u_int sr, vm_offset_t addr) 323 { 324 u_int hash; 325 326 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 327 ADDR_PIDX_SHFT); 328 return (hash & pmap_pteg_mask); 329 } 330 331 static __inline struct pvo_head * 332 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 333 { 334 struct vm_page *pg; 335 336 pg = PHYS_TO_VM_PAGE(pa); 337 338 if (pg_p != NULL) 339 *pg_p = pg; 340 341 if (pg == NULL) 342 return (&pmap_pvo_unmanaged); 343 344 return (&pg->md.mdpg_pvoh); 345 } 346 347 static __inline struct pvo_head * 348 vm_page_to_pvoh(vm_page_t m) 349 { 350 351 return (&m->md.mdpg_pvoh); 352 } 353 354 static __inline void 355 pmap_attr_clear(vm_page_t m, int ptebit) 356 { 357 358 m->md.mdpg_attrs &= ~ptebit; 359 } 360 361 static __inline int 362 pmap_attr_fetch(vm_page_t m) 363 { 364 365 return (m->md.mdpg_attrs); 366 } 367 368 static __inline void 369 pmap_attr_save(vm_page_t m, int ptebit) 370 { 371 372 m->md.mdpg_attrs |= ptebit; 373 } 374 375 static __inline int 376 pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 377 { 378 if (pt->pte_hi == pvo_pt->pte_hi) 379 return (1); 380 381 return (0); 382 } 383 384 static __inline int 385 pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 386 { 387 return (pt->pte_hi & ~PTE_VALID) == 388 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 389 ((va >> ADDR_API_SHFT) & PTE_API) | which); 390 } 391 392 static __inline void 393 pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 394 { 395 /* 396 * Construct a PTE. Default to IMB initially. Valid bit only gets 397 * set when the real pte is set in memory. 398 * 399 * Note: Don't set the valid bit for correct operation of tlb update. 400 */ 401 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 402 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 403 pt->pte_lo = pte_lo; 404 } 405 406 static __inline void 407 pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 408 { 409 410 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 411 } 412 413 static __inline void 414 pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 415 { 416 417 /* 418 * As shown in Section 7.6.3.2.3 419 */ 420 pt->pte_lo &= ~ptebit; 421 TLBIE(va); 422 EIEIO(); 423 TLBSYNC(); 424 SYNC(); 425 } 426 427 static __inline void 428 pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 429 { 430 431 pvo_pt->pte_hi |= PTE_VALID; 432 433 /* 434 * Update the PTE as defined in section 7.6.3.1. 435 * Note that the REF/CHG bits are from pvo_pt and thus should havce 436 * been saved so this routine can restore them (if desired). 437 */ 438 pt->pte_lo = pvo_pt->pte_lo; 439 EIEIO(); 440 pt->pte_hi = pvo_pt->pte_hi; 441 SYNC(); 442 pmap_pte_valid++; 443 } 444 445 static __inline void 446 pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 447 { 448 449 pvo_pt->pte_hi &= ~PTE_VALID; 450 451 /* 452 * Force the reg & chg bits back into the PTEs. 453 */ 454 SYNC(); 455 456 /* 457 * Invalidate the pte. 458 */ 459 pt->pte_hi &= ~PTE_VALID; 460 461 SYNC(); 462 TLBIE(va); 463 EIEIO(); 464 TLBSYNC(); 465 SYNC(); 466 467 /* 468 * Save the reg & chg bits. 469 */ 470 pmap_pte_synch(pt, pvo_pt); 471 pmap_pte_valid--; 472 } 473 474 static __inline void 475 pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 476 { 477 478 /* 479 * Invalidate the PTE 480 */ 481 pmap_pte_unset(pt, pvo_pt, va); 482 pmap_pte_set(pt, pvo_pt); 483 } 484 485 /* 486 * Quick sort callout for comparing memory regions. 487 */ 488 static int mr_cmp(const void *a, const void *b); 489 static int om_cmp(const void *a, const void *b); 490 491 static int 492 mr_cmp(const void *a, const void *b) 493 { 494 const struct mem_region *regiona; 495 const struct mem_region *regionb; 496 497 regiona = a; 498 regionb = b; 499 if (regiona->mr_start < regionb->mr_start) 500 return (-1); 501 else if (regiona->mr_start > regionb->mr_start) 502 return (1); 503 else 504 return (0); 505 } 506 507 static int 508 om_cmp(const void *a, const void *b) 509 { 510 const struct ofw_map *mapa; 511 const struct ofw_map *mapb; 512 513 mapa = a; 514 mapb = b; 515 if (mapa->om_pa < mapb->om_pa) 516 return (-1); 517 else if (mapa->om_pa > mapb->om_pa) 518 return (1); 519 else 520 return (0); 521 } 522 523 void 524 pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 525 { 526 ihandle_t mmui; 527 phandle_t chosen, mmu; 528 int sz; 529 int i, j; 530 int ofw_mappings; 531 vm_size_t size, physsz; 532 vm_offset_t pa, va, off; 533 u_int batl, batu; 534 535 /* 536 * Set up BAT0 to map the lowest 256 MB area 537 */ 538 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 539 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 540 541 /* 542 * Map PCI memory space. 543 */ 544 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 545 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 546 547 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 548 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 549 550 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 551 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 552 553 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 554 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 555 556 /* 557 * Map obio devices. 558 */ 559 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 560 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 561 562 /* 563 * Use an IBAT and a DBAT to map the bottom segment of memory 564 * where we are. 565 */ 566 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 567 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 568 __asm ("mtibatu 0,%0; mtibatl 0,%1; mtdbatu 0,%0; mtdbatl 0,%1" 569 :: "r"(batu), "r"(batl)); 570 571 #if 0 572 /* map frame buffer */ 573 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 574 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 575 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 576 :: "r"(batu), "r"(batl)); 577 #endif 578 579 #if 1 580 /* map pci space */ 581 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 582 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 583 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 584 :: "r"(batu), "r"(batl)); 585 #endif 586 587 /* 588 * Set the start and end of kva. 589 */ 590 virtual_avail = VM_MIN_KERNEL_ADDRESS; 591 virtual_end = VM_MAX_KERNEL_ADDRESS; 592 593 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 594 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 595 596 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 597 for (i = 0; i < pregions_sz; i++) { 598 vm_offset_t pa; 599 vm_offset_t end; 600 601 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 602 pregions[i].mr_start, 603 pregions[i].mr_start + pregions[i].mr_size, 604 pregions[i].mr_size); 605 /* 606 * Install entries into the BAT table to allow all 607 * of physmem to be convered by on-demand BAT entries. 608 * The loop will sometimes set the same battable element 609 * twice, but that's fine since they won't be used for 610 * a while yet. 611 */ 612 pa = pregions[i].mr_start & 0xf0000000; 613 end = pregions[i].mr_start + pregions[i].mr_size; 614 do { 615 u_int n = pa >> ADDR_SR_SHFT; 616 617 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 618 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 619 pa += SEGMENT_LENGTH; 620 } while (pa < end); 621 } 622 623 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 624 panic("pmap_bootstrap: phys_avail too small"); 625 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 626 phys_avail_count = 0; 627 physsz = 0; 628 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 629 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 630 regions[i].mr_start + regions[i].mr_size, 631 regions[i].mr_size); 632 phys_avail[j] = regions[i].mr_start; 633 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 634 phys_avail_count++; 635 physsz += regions[i].mr_size; 636 } 637 physmem = btoc(physsz); 638 639 /* 640 * Allocate PTEG table. 641 */ 642 #ifdef PTEGCOUNT 643 pmap_pteg_count = PTEGCOUNT; 644 #else 645 pmap_pteg_count = 0x1000; 646 647 while (pmap_pteg_count < physmem) 648 pmap_pteg_count <<= 1; 649 650 pmap_pteg_count >>= 1; 651 #endif /* PTEGCOUNT */ 652 653 size = pmap_pteg_count * sizeof(struct pteg); 654 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 655 size); 656 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 657 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 658 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 659 pmap_pteg_mask = pmap_pteg_count - 1; 660 661 /* 662 * Allocate pv/overflow lists. 663 */ 664 size = sizeof(struct pvo_head) * pmap_pteg_count; 665 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 666 PAGE_SIZE); 667 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 668 for (i = 0; i < pmap_pteg_count; i++) 669 LIST_INIT(&pmap_pvo_table[i]); 670 671 /* 672 * Allocate the message buffer. 673 */ 674 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 675 676 /* 677 * Initialise the unmanaged pvo pool. 678 */ 679 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 680 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 681 pmap_bpvo_pool_index = 0; 682 683 /* 684 * Make sure kernel vsid is allocated as well as VSID 0. 685 */ 686 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 687 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 688 pmap_vsid_bitmap[0] |= 1; 689 690 /* 691 * Set up the OpenFirmware pmap and add it's mappings. 692 */ 693 pmap_pinit(&ofw_pmap); 694 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 695 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 696 if ((chosen = OF_finddevice("/chosen")) == -1) 697 panic("pmap_bootstrap: can't find /chosen"); 698 OF_getprop(chosen, "mmu", &mmui, 4); 699 if ((mmu = OF_instance_to_package(mmui)) == -1) 700 panic("pmap_bootstrap: can't get mmu package"); 701 if ((sz = OF_getproplen(mmu, "translations")) == -1) 702 panic("pmap_bootstrap: can't get ofw translation count"); 703 translations = NULL; 704 for (i = 0; phys_avail[i] != 0; i += 2) { 705 if (phys_avail[i + 1] >= sz) { 706 translations = (struct ofw_map *)phys_avail[i]; 707 break; 708 } 709 } 710 if (translations == NULL) 711 panic("pmap_bootstrap: no space to copy translations"); 712 bzero(translations, sz); 713 if (OF_getprop(mmu, "translations", translations, sz) == -1) 714 panic("pmap_bootstrap: can't get ofw translations"); 715 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 716 sz /= sizeof(*translations); 717 qsort(translations, sz, sizeof (*translations), om_cmp); 718 for (i = 0, ofw_mappings = 0; i < sz; i++) { 719 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 720 translations[i].om_pa, translations[i].om_va, 721 translations[i].om_len); 722 723 /* 724 * If the mapping is 1:1, let the RAM and device on-demand 725 * BAT tables take care of the translation. 726 */ 727 if (translations[i].om_va == translations[i].om_pa) 728 continue; 729 730 /* Enter the pages */ 731 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 732 struct vm_page m; 733 734 m.phys_addr = translations[i].om_pa + off; 735 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 736 VM_PROT_ALL, 1); 737 ofw_mappings++; 738 } 739 } 740 #ifdef SMP 741 TLBSYNC(); 742 #endif 743 744 /* 745 * Initialize the kernel pmap (which is statically allocated). 746 */ 747 for (i = 0; i < 16; i++) { 748 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 749 } 750 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 751 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL_SEGMENT; 752 kernel_pmap->pm_active = ~0; 753 754 /* 755 * Allocate a kernel stack with a guard page for thread0 and map it 756 * into the kernel page map. 757 */ 758 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 759 kstack0_phys = pa; 760 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 761 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 762 kstack0); 763 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 764 for (i = 0; i < KSTACK_PAGES; i++) { 765 pa = kstack0_phys + i * PAGE_SIZE; 766 va = kstack0 + i * PAGE_SIZE; 767 pmap_kenter(va, pa); 768 TLBIE(va); 769 } 770 771 /* 772 * Calculate the last available physical address. 773 */ 774 for (i = 0; phys_avail[i + 2] != 0; i += 2) 775 ; 776 Maxmem = powerpc_btop(phys_avail[i + 1]); 777 778 /* 779 * Allocate virtual address space for the message buffer. 780 */ 781 msgbufp = (struct msgbuf *)virtual_avail; 782 virtual_avail += round_page(MSGBUF_SIZE); 783 784 /* 785 * Initialize hardware. 786 */ 787 for (i = 0; i < 16; i++) { 788 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 789 } 790 __asm __volatile ("mtsr %0,%1" 791 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 792 __asm __volatile ("sync; mtsdr1 %0; isync" 793 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 794 tlbia(); 795 796 pmap_bootstrapped++; 797 } 798 799 /* 800 * Activate a user pmap. The pmap must be activated before it's address 801 * space can be accessed in any way. 802 */ 803 void 804 pmap_activate(struct thread *td) 805 { 806 pmap_t pm, pmr; 807 808 /* 809 * Load all the data we need up front to encourage the compiler to 810 * not issue any loads while we have interrupts disabled below. 811 */ 812 pm = &td->td_proc->p_vmspace->vm_pmap; 813 814 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 815 pmr = pm; 816 817 pm->pm_active |= PCPU_GET(cpumask); 818 PCPU_SET(curpmap, pmr); 819 } 820 821 void 822 pmap_deactivate(struct thread *td) 823 { 824 pmap_t pm; 825 826 pm = &td->td_proc->p_vmspace->vm_pmap; 827 pm->pm_active &= ~(PCPU_GET(cpumask)); 828 PCPU_SET(curpmap, NULL); 829 } 830 831 vm_offset_t 832 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 833 { 834 835 return (va); 836 } 837 838 void 839 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 840 { 841 struct pvo_entry *pvo; 842 843 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 844 845 if (pvo != NULL) { 846 if (wired) { 847 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 848 pm->pm_stats.wired_count++; 849 pvo->pvo_vaddr |= PVO_WIRED; 850 } else { 851 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 852 pm->pm_stats.wired_count--; 853 pvo->pvo_vaddr &= ~PVO_WIRED; 854 } 855 } 856 } 857 858 void 859 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 860 vm_size_t len, vm_offset_t src_addr) 861 { 862 863 /* 864 * This is not needed as it's mainly an optimisation. 865 * It may want to be implemented later though. 866 */ 867 } 868 869 void 870 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 871 { 872 vm_offset_t dst; 873 vm_offset_t src; 874 875 dst = VM_PAGE_TO_PHYS(mdst); 876 src = VM_PAGE_TO_PHYS(msrc); 877 878 kcopy((void *)src, (void *)dst, PAGE_SIZE); 879 } 880 881 /* 882 * Zero a page of physical memory by temporarily mapping it into the tlb. 883 */ 884 void 885 pmap_zero_page(vm_page_t m) 886 { 887 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 888 caddr_t va; 889 890 if (pa < SEGMENT_LENGTH) { 891 va = (caddr_t) pa; 892 } else if (pmap_initialized) { 893 if (pmap_pvo_zeropage == NULL) 894 pmap_pvo_zeropage = pmap_rkva_alloc(); 895 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 896 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 897 } else { 898 panic("pmap_zero_page: can't zero pa %#x", pa); 899 } 900 901 bzero(va, PAGE_SIZE); 902 903 if (pa >= SEGMENT_LENGTH) 904 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 905 } 906 907 void 908 pmap_zero_page_area(vm_page_t m, int off, int size) 909 { 910 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 911 caddr_t va; 912 913 if (pa < SEGMENT_LENGTH) { 914 va = (caddr_t) pa; 915 } else if (pmap_initialized) { 916 if (pmap_pvo_zeropage == NULL) 917 pmap_pvo_zeropage = pmap_rkva_alloc(); 918 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 919 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 920 } else { 921 panic("pmap_zero_page: can't zero pa %#x", pa); 922 } 923 924 bzero(va + off, size); 925 926 if (pa >= SEGMENT_LENGTH) 927 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 928 } 929 930 void 931 pmap_zero_page_idle(vm_page_t m) 932 { 933 934 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 935 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 936 mtx_lock(&Giant); 937 pmap_zero_page(m); 938 mtx_unlock(&Giant); 939 } 940 941 /* 942 * Map the given physical page at the specified virtual address in the 943 * target pmap with the protection requested. If specified the page 944 * will be wired down. 945 */ 946 void 947 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 948 boolean_t wired) 949 { 950 struct pvo_head *pvo_head; 951 uma_zone_t zone; 952 vm_page_t pg; 953 u_int pte_lo, pvo_flags, was_exec, i; 954 int error; 955 956 if (!pmap_initialized) { 957 pvo_head = &pmap_pvo_kunmanaged; 958 zone = pmap_upvo_zone; 959 pvo_flags = 0; 960 pg = NULL; 961 was_exec = PTE_EXEC; 962 } else { 963 pvo_head = vm_page_to_pvoh(m); 964 pg = m; 965 zone = pmap_mpvo_zone; 966 pvo_flags = PVO_MANAGED; 967 was_exec = 0; 968 } 969 970 /* 971 * If this is a managed page, and it's the first reference to the page, 972 * clear the execness of the page. Otherwise fetch the execness. 973 */ 974 if (pg != NULL) { 975 if (LIST_EMPTY(pvo_head)) { 976 pmap_attr_clear(pg, PTE_EXEC); 977 } else { 978 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 979 } 980 } 981 982 983 /* 984 * Assume the page is cache inhibited and access is guarded unless 985 * it's in our available memory array. 986 */ 987 pte_lo = PTE_I | PTE_G; 988 for (i = 0; i < pregions_sz; i++) { 989 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 990 (VM_PAGE_TO_PHYS(m) < 991 (pregions[i].mr_start + pregions[i].mr_size))) { 992 pte_lo &= ~(PTE_I | PTE_G); 993 break; 994 } 995 } 996 997 if (prot & VM_PROT_WRITE) 998 pte_lo |= PTE_BW; 999 else 1000 pte_lo |= PTE_BR; 1001 1002 pvo_flags |= (prot & VM_PROT_EXECUTE); 1003 1004 if (wired) 1005 pvo_flags |= PVO_WIRED; 1006 1007 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1008 pte_lo, pvo_flags); 1009 1010 /* 1011 * Flush the real page from the instruction cache if this page is 1012 * mapped executable and cacheable and was not previously mapped (or 1013 * was not mapped executable). 1014 */ 1015 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1016 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1017 /* 1018 * Flush the real memory from the cache. 1019 */ 1020 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1021 if (pg != NULL) 1022 pmap_attr_save(pg, PTE_EXEC); 1023 } 1024 1025 /* XXX syncicache always until problems are sorted */ 1026 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1027 } 1028 1029 vm_page_t 1030 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_page_t mpte) 1031 { 1032 1033 pmap_enter(pm, va, m, VM_PROT_READ | VM_PROT_EXECUTE, FALSE); 1034 return (NULL); 1035 } 1036 1037 vm_offset_t 1038 pmap_extract(pmap_t pm, vm_offset_t va) 1039 { 1040 struct pvo_entry *pvo; 1041 1042 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1043 1044 if (pvo != NULL) { 1045 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1046 } 1047 1048 return (0); 1049 } 1050 1051 /* 1052 * Atomically extract and hold the physical page with the given 1053 * pmap and virtual address pair if that mapping permits the given 1054 * protection. 1055 */ 1056 vm_page_t 1057 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1058 { 1059 vm_paddr_t pa; 1060 vm_page_t m; 1061 1062 m = NULL; 1063 mtx_lock(&Giant); 1064 if ((pa = pmap_extract(pmap, va)) != 0) { 1065 m = PHYS_TO_VM_PAGE(pa); 1066 vm_page_lock_queues(); 1067 vm_page_hold(m); 1068 vm_page_unlock_queues(); 1069 } 1070 mtx_unlock(&Giant); 1071 return (m); 1072 } 1073 1074 /* 1075 * Grow the number of kernel page table entries. Unneeded. 1076 */ 1077 void 1078 pmap_growkernel(vm_offset_t addr) 1079 { 1080 } 1081 1082 void 1083 pmap_init(void) 1084 { 1085 1086 CTR0(KTR_PMAP, "pmap_init"); 1087 1088 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1089 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1090 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1091 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1092 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1093 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1094 pmap_initialized = TRUE; 1095 } 1096 1097 void 1098 pmap_init2(void) 1099 { 1100 1101 CTR0(KTR_PMAP, "pmap_init2"); 1102 } 1103 1104 boolean_t 1105 pmap_is_modified(vm_page_t m) 1106 { 1107 1108 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1109 return (FALSE); 1110 1111 return (pmap_query_bit(m, PTE_CHG)); 1112 } 1113 1114 /* 1115 * pmap_is_prefaultable: 1116 * 1117 * Return whether or not the specified virtual address is elgible 1118 * for prefault. 1119 */ 1120 boolean_t 1121 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1122 { 1123 1124 return (FALSE); 1125 } 1126 1127 void 1128 pmap_clear_reference(vm_page_t m) 1129 { 1130 1131 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1132 return; 1133 pmap_clear_bit(m, PTE_REF, NULL); 1134 } 1135 1136 void 1137 pmap_clear_modify(vm_page_t m) 1138 { 1139 1140 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1141 return; 1142 pmap_clear_bit(m, PTE_CHG, NULL); 1143 } 1144 1145 /* 1146 * pmap_ts_referenced: 1147 * 1148 * Return a count of reference bits for a page, clearing those bits. 1149 * It is not necessary for every reference bit to be cleared, but it 1150 * is necessary that 0 only be returned when there are truly no 1151 * reference bits set. 1152 * 1153 * XXX: The exact number of bits to check and clear is a matter that 1154 * should be tested and standardized at some point in the future for 1155 * optimal aging of shared pages. 1156 */ 1157 int 1158 pmap_ts_referenced(vm_page_t m) 1159 { 1160 int count; 1161 1162 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1163 return (0); 1164 1165 count = pmap_clear_bit(m, PTE_REF, NULL); 1166 1167 return (count); 1168 } 1169 1170 /* 1171 * Map a wired page into kernel virtual address space. 1172 */ 1173 void 1174 pmap_kenter(vm_offset_t va, vm_offset_t pa) 1175 { 1176 u_int pte_lo; 1177 int error; 1178 int i; 1179 1180 #if 0 1181 if (va < VM_MIN_KERNEL_ADDRESS) 1182 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1183 va); 1184 #endif 1185 1186 pte_lo = PTE_I | PTE_G; 1187 for (i = 0; i < pregions_sz; i++) { 1188 if ((pa >= pregions[i].mr_start) && 1189 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1190 pte_lo &= ~(PTE_I | PTE_G); 1191 break; 1192 } 1193 } 1194 1195 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1196 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1197 1198 if (error != 0 && error != ENOENT) 1199 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1200 pa, error); 1201 1202 /* 1203 * Flush the real memory from the instruction cache. 1204 */ 1205 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1206 pmap_syncicache(pa, PAGE_SIZE); 1207 } 1208 } 1209 1210 /* 1211 * Extract the physical page address associated with the given kernel virtual 1212 * address. 1213 */ 1214 vm_offset_t 1215 pmap_kextract(vm_offset_t va) 1216 { 1217 struct pvo_entry *pvo; 1218 1219 #ifdef UMA_MD_SMALL_ALLOC 1220 /* 1221 * Allow direct mappings 1222 */ 1223 if (va < VM_MIN_KERNEL_ADDRESS) { 1224 return (va); 1225 } 1226 #endif 1227 1228 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1229 KASSERT(pvo != NULL, ("pmap_kextract: no addr found")); 1230 if (pvo == NULL) { 1231 return (0); 1232 } 1233 1234 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1235 } 1236 1237 /* 1238 * Remove a wired page from kernel virtual address space. 1239 */ 1240 void 1241 pmap_kremove(vm_offset_t va) 1242 { 1243 1244 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1245 } 1246 1247 /* 1248 * Map a range of physical addresses into kernel virtual address space. 1249 * 1250 * The value passed in *virt is a suggested virtual address for the mapping. 1251 * Architectures which can support a direct-mapped physical to virtual region 1252 * can return the appropriate address within that region, leaving '*virt' 1253 * unchanged. We cannot and therefore do not; *virt is updated with the 1254 * first usable address after the mapped region. 1255 */ 1256 vm_offset_t 1257 pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1258 { 1259 vm_offset_t sva, va; 1260 1261 sva = *virt; 1262 va = sva; 1263 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1264 pmap_kenter(va, pa_start); 1265 *virt = va; 1266 return (sva); 1267 } 1268 1269 int 1270 pmap_mincore(pmap_t pmap, vm_offset_t addr) 1271 { 1272 TODO; 1273 return (0); 1274 } 1275 1276 void 1277 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1278 vm_pindex_t pindex, vm_size_t size) 1279 { 1280 1281 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 1282 KASSERT(object->type == OBJT_DEVICE, 1283 ("pmap_object_init_pt: non-device object")); 1284 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1285 ("pmap_object_init_pt: non current pmap")); 1286 } 1287 1288 /* 1289 * Lower the permission for all mappings to a given page. 1290 */ 1291 void 1292 pmap_page_protect(vm_page_t m, vm_prot_t prot) 1293 { 1294 struct pvo_head *pvo_head; 1295 struct pvo_entry *pvo, *next_pvo; 1296 struct pte *pt; 1297 1298 /* 1299 * Since the routine only downgrades protection, if the 1300 * maximal protection is desired, there isn't any change 1301 * to be made. 1302 */ 1303 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1304 (VM_PROT_READ|VM_PROT_WRITE)) 1305 return; 1306 1307 pvo_head = vm_page_to_pvoh(m); 1308 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1309 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1310 PMAP_PVO_CHECK(pvo); /* sanity check */ 1311 1312 /* 1313 * Downgrading to no mapping at all, we just remove the entry. 1314 */ 1315 if ((prot & VM_PROT_READ) == 0) { 1316 pmap_pvo_remove(pvo, -1); 1317 continue; 1318 } 1319 1320 /* 1321 * If EXEC permission is being revoked, just clear the flag 1322 * in the PVO. 1323 */ 1324 if ((prot & VM_PROT_EXECUTE) == 0) 1325 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1326 1327 /* 1328 * If this entry is already RO, don't diddle with the page 1329 * table. 1330 */ 1331 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1332 PMAP_PVO_CHECK(pvo); 1333 continue; 1334 } 1335 1336 /* 1337 * Grab the PTE before we diddle the bits so pvo_to_pte can 1338 * verify the pte contents are as expected. 1339 */ 1340 pt = pmap_pvo_to_pte(pvo, -1); 1341 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1342 pvo->pvo_pte.pte_lo |= PTE_BR; 1343 if (pt != NULL) 1344 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1345 PMAP_PVO_CHECK(pvo); /* sanity check */ 1346 } 1347 } 1348 1349 /* 1350 * Returns true if the pmap's pv is one of the first 1351 * 16 pvs linked to from this page. This count may 1352 * be changed upwards or downwards in the future; it 1353 * is only necessary that true be returned for a small 1354 * subset of pmaps for proper page aging. 1355 */ 1356 boolean_t 1357 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1358 { 1359 int loops; 1360 struct pvo_entry *pvo; 1361 1362 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 1363 return FALSE; 1364 1365 loops = 0; 1366 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1367 if (pvo->pvo_pmap == pmap) 1368 return (TRUE); 1369 if (++loops >= 16) 1370 break; 1371 } 1372 1373 return (FALSE); 1374 } 1375 1376 static u_int pmap_vsidcontext; 1377 1378 void 1379 pmap_pinit(pmap_t pmap) 1380 { 1381 int i, mask; 1382 u_int entropy; 1383 1384 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("pmap_pinit: virt pmap")); 1385 1386 entropy = 0; 1387 __asm __volatile("mftb %0" : "=r"(entropy)); 1388 1389 /* 1390 * Allocate some segment registers for this pmap. 1391 */ 1392 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1393 u_int hash, n; 1394 1395 /* 1396 * Create a new value by mutiplying by a prime and adding in 1397 * entropy from the timebase register. This is to make the 1398 * VSID more random so that the PT hash function collides 1399 * less often. (Note that the prime casues gcc to do shifts 1400 * instead of a multiply.) 1401 */ 1402 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1403 hash = pmap_vsidcontext & (NPMAPS - 1); 1404 if (hash == 0) /* 0 is special, avoid it */ 1405 continue; 1406 n = hash >> 5; 1407 mask = 1 << (hash & (VSID_NBPW - 1)); 1408 hash = (pmap_vsidcontext & 0xfffff); 1409 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1410 /* anything free in this bucket? */ 1411 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1412 entropy = (pmap_vsidcontext >> 20); 1413 continue; 1414 } 1415 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1416 mask = 1 << i; 1417 hash &= 0xfffff & ~(VSID_NBPW - 1); 1418 hash |= i; 1419 } 1420 pmap_vsid_bitmap[n] |= mask; 1421 for (i = 0; i < 16; i++) 1422 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1423 return; 1424 } 1425 1426 panic("pmap_pinit: out of segments"); 1427 } 1428 1429 /* 1430 * Initialize the pmap associated with process 0. 1431 */ 1432 void 1433 pmap_pinit0(pmap_t pm) 1434 { 1435 1436 pmap_pinit(pm); 1437 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1438 } 1439 1440 /* 1441 * Set the physical protection on the specified range of this map as requested. 1442 */ 1443 void 1444 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1445 { 1446 struct pvo_entry *pvo; 1447 struct pte *pt; 1448 int pteidx; 1449 1450 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1451 eva, prot); 1452 1453 1454 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1455 ("pmap_protect: non current pmap")); 1456 1457 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1458 pmap_remove(pm, sva, eva); 1459 return; 1460 } 1461 1462 for (; sva < eva; sva += PAGE_SIZE) { 1463 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1464 if (pvo == NULL) 1465 continue; 1466 1467 if ((prot & VM_PROT_EXECUTE) == 0) 1468 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1469 1470 /* 1471 * Grab the PTE pointer before we diddle with the cached PTE 1472 * copy. 1473 */ 1474 pt = pmap_pvo_to_pte(pvo, pteidx); 1475 /* 1476 * Change the protection of the page. 1477 */ 1478 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1479 pvo->pvo_pte.pte_lo |= PTE_BR; 1480 1481 /* 1482 * If the PVO is in the page table, update that pte as well. 1483 */ 1484 if (pt != NULL) 1485 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1486 } 1487 } 1488 1489 /* 1490 * Map a list of wired pages into kernel virtual address space. This is 1491 * intended for temporary mappings which do not need page modification or 1492 * references recorded. Existing mappings in the region are overwritten. 1493 */ 1494 void 1495 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1496 { 1497 vm_offset_t va; 1498 1499 va = sva; 1500 while (count-- > 0) { 1501 pmap_kenter(va, VM_PAGE_TO_PHYS(*m)); 1502 va += PAGE_SIZE; 1503 m++; 1504 } 1505 } 1506 1507 /* 1508 * Remove page mappings from kernel virtual address space. Intended for 1509 * temporary mappings entered by pmap_qenter. 1510 */ 1511 void 1512 pmap_qremove(vm_offset_t sva, int count) 1513 { 1514 vm_offset_t va; 1515 1516 va = sva; 1517 while (count-- > 0) { 1518 pmap_kremove(va); 1519 va += PAGE_SIZE; 1520 } 1521 } 1522 1523 void 1524 pmap_release(pmap_t pmap) 1525 { 1526 int idx, mask; 1527 1528 /* 1529 * Free segment register's VSID 1530 */ 1531 if (pmap->pm_sr[0] == 0) 1532 panic("pmap_release"); 1533 1534 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1535 mask = 1 << (idx % VSID_NBPW); 1536 idx /= VSID_NBPW; 1537 pmap_vsid_bitmap[idx] &= ~mask; 1538 } 1539 1540 /* 1541 * Remove the given range of addresses from the specified map. 1542 */ 1543 void 1544 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1545 { 1546 struct pvo_entry *pvo; 1547 int pteidx; 1548 1549 for (; sva < eva; sva += PAGE_SIZE) { 1550 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1551 if (pvo != NULL) { 1552 pmap_pvo_remove(pvo, pteidx); 1553 } 1554 } 1555 } 1556 1557 /* 1558 * Remove physical page from all pmaps in which it resides. pmap_pvo_remove() 1559 * will reflect changes in pte's back to the vm_page. 1560 */ 1561 void 1562 pmap_remove_all(vm_page_t m) 1563 { 1564 struct pvo_head *pvo_head; 1565 struct pvo_entry *pvo, *next_pvo; 1566 1567 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1568 1569 pvo_head = vm_page_to_pvoh(m); 1570 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1571 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1572 1573 PMAP_PVO_CHECK(pvo); /* sanity check */ 1574 pmap_pvo_remove(pvo, -1); 1575 } 1576 vm_page_flag_clear(m, PG_WRITEABLE); 1577 } 1578 1579 /* 1580 * Remove all pages from specified address space, this aids process exit 1581 * speeds. This is much faster than pmap_remove in the case of running down 1582 * an entire address space. Only works for the current pmap. 1583 */ 1584 void 1585 pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1586 { 1587 1588 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1589 ("pmap_remove_pages: non current pmap")); 1590 pmap_remove(pm, sva, eva); 1591 } 1592 1593 /* 1594 * Allocate a physical page of memory directly from the phys_avail map. 1595 * Can only be called from pmap_bootstrap before avail start and end are 1596 * calculated. 1597 */ 1598 static vm_offset_t 1599 pmap_bootstrap_alloc(vm_size_t size, u_int align) 1600 { 1601 vm_offset_t s, e; 1602 int i, j; 1603 1604 size = round_page(size); 1605 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1606 if (align != 0) 1607 s = (phys_avail[i] + align - 1) & ~(align - 1); 1608 else 1609 s = phys_avail[i]; 1610 e = s + size; 1611 1612 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1613 continue; 1614 1615 if (s == phys_avail[i]) { 1616 phys_avail[i] += size; 1617 } else if (e == phys_avail[i + 1]) { 1618 phys_avail[i + 1] -= size; 1619 } else { 1620 for (j = phys_avail_count * 2; j > i; j -= 2) { 1621 phys_avail[j] = phys_avail[j - 2]; 1622 phys_avail[j + 1] = phys_avail[j - 1]; 1623 } 1624 1625 phys_avail[i + 3] = phys_avail[i + 1]; 1626 phys_avail[i + 1] = s; 1627 phys_avail[i + 2] = e; 1628 phys_avail_count++; 1629 } 1630 1631 return (s); 1632 } 1633 panic("pmap_bootstrap_alloc: could not allocate memory"); 1634 } 1635 1636 /* 1637 * Return an unmapped pvo for a kernel virtual address. 1638 * Used by pmap functions that operate on physical pages. 1639 */ 1640 static struct pvo_entry * 1641 pmap_rkva_alloc(void) 1642 { 1643 struct pvo_entry *pvo; 1644 struct pte *pt; 1645 vm_offset_t kva; 1646 int pteidx; 1647 1648 if (pmap_rkva_count == 0) 1649 panic("pmap_rkva_alloc: no more reserved KVAs"); 1650 1651 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1652 pmap_kenter(kva, 0); 1653 1654 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1655 1656 if (pvo == NULL) 1657 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1658 1659 pt = pmap_pvo_to_pte(pvo, pteidx); 1660 1661 if (pt == NULL) 1662 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1663 1664 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1665 PVO_PTEGIDX_CLR(pvo); 1666 1667 pmap_pte_overflow++; 1668 1669 return (pvo); 1670 } 1671 1672 static void 1673 pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1674 int *depth_p) 1675 { 1676 struct pte *pt; 1677 1678 /* 1679 * If this pvo already has a valid pte, we need to save it so it can 1680 * be restored later. We then just reload the new PTE over the old 1681 * slot. 1682 */ 1683 if (saved_pt != NULL) { 1684 pt = pmap_pvo_to_pte(pvo, -1); 1685 1686 if (pt != NULL) { 1687 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1688 PVO_PTEGIDX_CLR(pvo); 1689 pmap_pte_overflow++; 1690 } 1691 1692 *saved_pt = pvo->pvo_pte; 1693 1694 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1695 } 1696 1697 pvo->pvo_pte.pte_lo |= pa; 1698 1699 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1700 panic("pmap_pa_map: could not spill pvo %p", pvo); 1701 1702 if (depth_p != NULL) 1703 (*depth_p)++; 1704 } 1705 1706 static void 1707 pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1708 { 1709 struct pte *pt; 1710 1711 pt = pmap_pvo_to_pte(pvo, -1); 1712 1713 if (pt != NULL) { 1714 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1715 PVO_PTEGIDX_CLR(pvo); 1716 pmap_pte_overflow++; 1717 } 1718 1719 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1720 1721 /* 1722 * If there is a saved PTE and it's valid, restore it and return. 1723 */ 1724 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1725 if (depth_p != NULL && --(*depth_p) == 0) 1726 panic("pmap_pa_unmap: restoring but depth == 0"); 1727 1728 pvo->pvo_pte = *saved_pt; 1729 1730 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1731 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1732 } 1733 } 1734 1735 static void 1736 pmap_syncicache(vm_offset_t pa, vm_size_t len) 1737 { 1738 __syncicache((void *)pa, len); 1739 } 1740 1741 static void 1742 tlbia(void) 1743 { 1744 caddr_t i; 1745 1746 SYNC(); 1747 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1748 TLBIE(i); 1749 EIEIO(); 1750 } 1751 TLBSYNC(); 1752 SYNC(); 1753 } 1754 1755 static int 1756 pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1757 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1758 { 1759 struct pvo_entry *pvo; 1760 u_int sr; 1761 int first; 1762 u_int ptegidx; 1763 int i; 1764 int bootstrap; 1765 1766 pmap_pvo_enter_calls++; 1767 first = 0; 1768 1769 bootstrap = 0; 1770 1771 /* 1772 * Compute the PTE Group index. 1773 */ 1774 va &= ~ADDR_POFF; 1775 sr = va_to_sr(pm->pm_sr, va); 1776 ptegidx = va_to_pteg(sr, va); 1777 1778 /* 1779 * Remove any existing mapping for this page. Reuse the pvo entry if 1780 * there is a mapping. 1781 */ 1782 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1783 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1784 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1785 (pvo->pvo_pte.pte_lo & PTE_PP) == 1786 (pte_lo & PTE_PP)) { 1787 return (0); 1788 } 1789 pmap_pvo_remove(pvo, -1); 1790 break; 1791 } 1792 } 1793 1794 /* 1795 * If we aren't overwriting a mapping, try to allocate. 1796 */ 1797 if (pmap_initialized) { 1798 pvo = uma_zalloc(zone, M_NOWAIT); 1799 } else { 1800 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1801 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1802 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1803 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1804 } 1805 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1806 pmap_bpvo_pool_index++; 1807 bootstrap = 1; 1808 } 1809 1810 if (pvo == NULL) { 1811 return (ENOMEM); 1812 } 1813 1814 pmap_pvo_entries++; 1815 pvo->pvo_vaddr = va; 1816 pvo->pvo_pmap = pm; 1817 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1818 pvo->pvo_vaddr &= ~ADDR_POFF; 1819 if (flags & VM_PROT_EXECUTE) 1820 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1821 if (flags & PVO_WIRED) 1822 pvo->pvo_vaddr |= PVO_WIRED; 1823 if (pvo_head != &pmap_pvo_kunmanaged) 1824 pvo->pvo_vaddr |= PVO_MANAGED; 1825 if (bootstrap) 1826 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1827 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1828 1829 /* 1830 * Remember if the list was empty and therefore will be the first 1831 * item. 1832 */ 1833 if (LIST_FIRST(pvo_head) == NULL) 1834 first = 1; 1835 1836 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1837 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1838 pvo->pvo_pmap->pm_stats.wired_count++; 1839 pvo->pvo_pmap->pm_stats.resident_count++; 1840 1841 /* 1842 * We hope this succeeds but it isn't required. 1843 */ 1844 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1845 if (i >= 0) { 1846 PVO_PTEGIDX_SET(pvo, i); 1847 } else { 1848 panic("pmap_pvo_enter: overflow"); 1849 pmap_pte_overflow++; 1850 } 1851 1852 return (first ? ENOENT : 0); 1853 } 1854 1855 static void 1856 pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1857 { 1858 struct pte *pt; 1859 1860 /* 1861 * If there is an active pte entry, we need to deactivate it (and 1862 * save the ref & cfg bits). 1863 */ 1864 pt = pmap_pvo_to_pte(pvo, pteidx); 1865 if (pt != NULL) { 1866 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1867 PVO_PTEGIDX_CLR(pvo); 1868 } else { 1869 pmap_pte_overflow--; 1870 } 1871 1872 /* 1873 * Update our statistics. 1874 */ 1875 pvo->pvo_pmap->pm_stats.resident_count--; 1876 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1877 pvo->pvo_pmap->pm_stats.wired_count--; 1878 1879 /* 1880 * Save the REF/CHG bits into their cache if the page is managed. 1881 */ 1882 if (pvo->pvo_vaddr & PVO_MANAGED) { 1883 struct vm_page *pg; 1884 1885 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1886 if (pg != NULL) { 1887 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 1888 (PTE_REF | PTE_CHG)); 1889 } 1890 } 1891 1892 /* 1893 * Remove this PVO from the PV list. 1894 */ 1895 LIST_REMOVE(pvo, pvo_vlink); 1896 1897 /* 1898 * Remove this from the overflow list and return it to the pool 1899 * if we aren't going to reuse it. 1900 */ 1901 LIST_REMOVE(pvo, pvo_olink); 1902 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1903 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 1904 pmap_upvo_zone, pvo); 1905 pmap_pvo_entries--; 1906 pmap_pvo_remove_calls++; 1907 } 1908 1909 static __inline int 1910 pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1911 { 1912 int pteidx; 1913 1914 /* 1915 * We can find the actual pte entry without searching by grabbing 1916 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1917 * noticing the HID bit. 1918 */ 1919 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1920 if (pvo->pvo_pte.pte_hi & PTE_HID) 1921 pteidx ^= pmap_pteg_mask * 8; 1922 1923 return (pteidx); 1924 } 1925 1926 static struct pvo_entry * 1927 pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1928 { 1929 struct pvo_entry *pvo; 1930 int ptegidx; 1931 u_int sr; 1932 1933 va &= ~ADDR_POFF; 1934 sr = va_to_sr(pm->pm_sr, va); 1935 ptegidx = va_to_pteg(sr, va); 1936 1937 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1938 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1939 if (pteidx_p) 1940 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 1941 return (pvo); 1942 } 1943 } 1944 1945 return (NULL); 1946 } 1947 1948 static struct pte * 1949 pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 1950 { 1951 struct pte *pt; 1952 1953 /* 1954 * If we haven't been supplied the ptegidx, calculate it. 1955 */ 1956 if (pteidx == -1) { 1957 int ptegidx; 1958 u_int sr; 1959 1960 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 1961 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1962 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 1963 } 1964 1965 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 1966 1967 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 1968 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 1969 "valid pte index", pvo); 1970 } 1971 1972 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 1973 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 1974 "pvo but no valid pte", pvo); 1975 } 1976 1977 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 1978 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 1979 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 1980 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 1981 } 1982 1983 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 1984 != 0) { 1985 panic("pmap_pvo_to_pte: pvo %p pte does not match " 1986 "pte %p in pmap_pteg_table", pvo, pt); 1987 } 1988 1989 return (pt); 1990 } 1991 1992 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 1993 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 1994 "pmap_pteg_table but valid in pvo", pvo, pt); 1995 } 1996 1997 return (NULL); 1998 } 1999 2000 /* 2001 * XXX: THIS STUFF SHOULD BE IN pte.c? 2002 */ 2003 int 2004 pmap_pte_spill(vm_offset_t addr) 2005 { 2006 struct pvo_entry *source_pvo, *victim_pvo; 2007 struct pvo_entry *pvo; 2008 int ptegidx, i, j; 2009 u_int sr; 2010 struct pteg *pteg; 2011 struct pte *pt; 2012 2013 pmap_pte_spills++; 2014 2015 sr = mfsrin(addr); 2016 ptegidx = va_to_pteg(sr, addr); 2017 2018 /* 2019 * Have to substitute some entry. Use the primary hash for this. 2020 * Use low bits of timebase as random generator. 2021 */ 2022 pteg = &pmap_pteg_table[ptegidx]; 2023 __asm __volatile("mftb %0" : "=r"(i)); 2024 i &= 7; 2025 pt = &pteg->pt[i]; 2026 2027 source_pvo = NULL; 2028 victim_pvo = NULL; 2029 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2030 /* 2031 * We need to find a pvo entry for this address. 2032 */ 2033 PMAP_PVO_CHECK(pvo); 2034 if (source_pvo == NULL && 2035 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2036 pvo->pvo_pte.pte_hi & PTE_HID)) { 2037 /* 2038 * Now found an entry to be spilled into the pteg. 2039 * The PTE is now valid, so we know it's active. 2040 */ 2041 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2042 2043 if (j >= 0) { 2044 PVO_PTEGIDX_SET(pvo, j); 2045 pmap_pte_overflow--; 2046 PMAP_PVO_CHECK(pvo); 2047 return (1); 2048 } 2049 2050 source_pvo = pvo; 2051 2052 if (victim_pvo != NULL) 2053 break; 2054 } 2055 2056 /* 2057 * We also need the pvo entry of the victim we are replacing 2058 * so save the R & C bits of the PTE. 2059 */ 2060 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2061 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2062 victim_pvo = pvo; 2063 if (source_pvo != NULL) 2064 break; 2065 } 2066 } 2067 2068 if (source_pvo == NULL) 2069 return (0); 2070 2071 if (victim_pvo == NULL) { 2072 if ((pt->pte_hi & PTE_HID) == 0) 2073 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2074 "entry", pt); 2075 2076 /* 2077 * If this is a secondary PTE, we need to search it's primary 2078 * pvo bucket for the matching PVO. 2079 */ 2080 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2081 pvo_olink) { 2082 PMAP_PVO_CHECK(pvo); 2083 /* 2084 * We also need the pvo entry of the victim we are 2085 * replacing so save the R & C bits of the PTE. 2086 */ 2087 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2088 victim_pvo = pvo; 2089 break; 2090 } 2091 } 2092 2093 if (victim_pvo == NULL) 2094 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2095 "entry", pt); 2096 } 2097 2098 /* 2099 * We are invalidating the TLB entry for the EA we are replacing even 2100 * though it's valid. If we don't, we lose any ref/chg bit changes 2101 * contained in the TLB entry. 2102 */ 2103 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2104 2105 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2106 pmap_pte_set(pt, &source_pvo->pvo_pte); 2107 2108 PVO_PTEGIDX_CLR(victim_pvo); 2109 PVO_PTEGIDX_SET(source_pvo, i); 2110 pmap_pte_replacements++; 2111 2112 PMAP_PVO_CHECK(victim_pvo); 2113 PMAP_PVO_CHECK(source_pvo); 2114 2115 return (1); 2116 } 2117 2118 static int 2119 pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2120 { 2121 struct pte *pt; 2122 int i; 2123 2124 /* 2125 * First try primary hash. 2126 */ 2127 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2128 if ((pt->pte_hi & PTE_VALID) == 0) { 2129 pvo_pt->pte_hi &= ~PTE_HID; 2130 pmap_pte_set(pt, pvo_pt); 2131 return (i); 2132 } 2133 } 2134 2135 /* 2136 * Now try secondary hash. 2137 */ 2138 ptegidx ^= pmap_pteg_mask; 2139 ptegidx++; 2140 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2141 if ((pt->pte_hi & PTE_VALID) == 0) { 2142 pvo_pt->pte_hi |= PTE_HID; 2143 pmap_pte_set(pt, pvo_pt); 2144 return (i); 2145 } 2146 } 2147 2148 panic("pmap_pte_insert: overflow"); 2149 return (-1); 2150 } 2151 2152 static boolean_t 2153 pmap_query_bit(vm_page_t m, int ptebit) 2154 { 2155 struct pvo_entry *pvo; 2156 struct pte *pt; 2157 2158 #if 0 2159 if (pmap_attr_fetch(m) & ptebit) 2160 return (TRUE); 2161 #endif 2162 2163 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2164 PMAP_PVO_CHECK(pvo); /* sanity check */ 2165 2166 /* 2167 * See if we saved the bit off. If so, cache it and return 2168 * success. 2169 */ 2170 if (pvo->pvo_pte.pte_lo & ptebit) { 2171 pmap_attr_save(m, ptebit); 2172 PMAP_PVO_CHECK(pvo); /* sanity check */ 2173 return (TRUE); 2174 } 2175 } 2176 2177 /* 2178 * No luck, now go through the hard part of looking at the PTEs 2179 * themselves. Sync so that any pending REF/CHG bits are flushed to 2180 * the PTEs. 2181 */ 2182 SYNC(); 2183 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2184 PMAP_PVO_CHECK(pvo); /* sanity check */ 2185 2186 /* 2187 * See if this pvo has a valid PTE. if so, fetch the 2188 * REF/CHG bits from the valid PTE. If the appropriate 2189 * ptebit is set, cache it and return success. 2190 */ 2191 pt = pmap_pvo_to_pte(pvo, -1); 2192 if (pt != NULL) { 2193 pmap_pte_synch(pt, &pvo->pvo_pte); 2194 if (pvo->pvo_pte.pte_lo & ptebit) { 2195 pmap_attr_save(m, ptebit); 2196 PMAP_PVO_CHECK(pvo); /* sanity check */ 2197 return (TRUE); 2198 } 2199 } 2200 } 2201 2202 return (FALSE); 2203 } 2204 2205 static u_int 2206 pmap_clear_bit(vm_page_t m, int ptebit, int *origbit) 2207 { 2208 u_int count; 2209 struct pvo_entry *pvo; 2210 struct pte *pt; 2211 int rv; 2212 2213 /* 2214 * Clear the cached value. 2215 */ 2216 rv = pmap_attr_fetch(m); 2217 pmap_attr_clear(m, ptebit); 2218 2219 /* 2220 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2221 * we can reset the right ones). note that since the pvo entries and 2222 * list heads are accessed via BAT0 and are never placed in the page 2223 * table, we don't have to worry about further accesses setting the 2224 * REF/CHG bits. 2225 */ 2226 SYNC(); 2227 2228 /* 2229 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2230 * valid pte clear the ptebit from the valid pte. 2231 */ 2232 count = 0; 2233 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2234 PMAP_PVO_CHECK(pvo); /* sanity check */ 2235 pt = pmap_pvo_to_pte(pvo, -1); 2236 if (pt != NULL) { 2237 pmap_pte_synch(pt, &pvo->pvo_pte); 2238 if (pvo->pvo_pte.pte_lo & ptebit) { 2239 count++; 2240 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2241 } 2242 } 2243 rv |= pvo->pvo_pte.pte_lo; 2244 pvo->pvo_pte.pte_lo &= ~ptebit; 2245 PMAP_PVO_CHECK(pvo); /* sanity check */ 2246 } 2247 2248 if (origbit != NULL) { 2249 *origbit = rv; 2250 } 2251 2252 return (count); 2253 } 2254 2255 /* 2256 * Return true if the physical range is encompassed by the battable[idx] 2257 */ 2258 static int 2259 pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2260 { 2261 u_int prot; 2262 u_int32_t start; 2263 u_int32_t end; 2264 u_int32_t bat_ble; 2265 2266 /* 2267 * Return immediately if not a valid mapping 2268 */ 2269 if (!battable[idx].batu & BAT_Vs) 2270 return (EINVAL); 2271 2272 /* 2273 * The BAT entry must be cache-inhibited, guarded, and r/w 2274 * so it can function as an i/o page 2275 */ 2276 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2277 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2278 return (EPERM); 2279 2280 /* 2281 * The address should be within the BAT range. Assume that the 2282 * start address in the BAT has the correct alignment (thus 2283 * not requiring masking) 2284 */ 2285 start = battable[idx].batl & BAT_PBS; 2286 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2287 end = start | (bat_ble << 15) | 0x7fff; 2288 2289 if ((pa < start) || ((pa + size) > end)) 2290 return (ERANGE); 2291 2292 return (0); 2293 } 2294 2295 2296 /* 2297 * Map a set of physical memory pages into the kernel virtual 2298 * address space. Return a pointer to where it is mapped. This 2299 * routine is intended to be used for mapping device memory, 2300 * NOT real memory. 2301 */ 2302 void * 2303 pmap_mapdev(vm_offset_t pa, vm_size_t size) 2304 { 2305 vm_offset_t va, tmpva, ppa, offset; 2306 int i; 2307 2308 ppa = trunc_page(pa); 2309 offset = pa & PAGE_MASK; 2310 size = roundup(offset + size, PAGE_SIZE); 2311 2312 GIANT_REQUIRED; 2313 2314 /* 2315 * If the physical address lies within a valid BAT table entry, 2316 * return the 1:1 mapping. This currently doesn't work 2317 * for regions that overlap 256M BAT segments. 2318 */ 2319 for (i = 0; i < 16; i++) { 2320 if (pmap_bat_mapped(i, pa, size) == 0) 2321 return ((void *) pa); 2322 } 2323 2324 va = kmem_alloc_nofault(kernel_map, size); 2325 if (!va) 2326 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2327 2328 for (tmpva = va; size > 0;) { 2329 pmap_kenter(tmpva, ppa); 2330 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2331 size -= PAGE_SIZE; 2332 tmpva += PAGE_SIZE; 2333 ppa += PAGE_SIZE; 2334 } 2335 2336 return ((void *)(va + offset)); 2337 } 2338 2339 void 2340 pmap_unmapdev(vm_offset_t va, vm_size_t size) 2341 { 2342 vm_offset_t base, offset; 2343 2344 /* 2345 * If this is outside kernel virtual space, then it's a 2346 * battable entry and doesn't require unmapping 2347 */ 2348 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2349 base = trunc_page(va); 2350 offset = va & PAGE_MASK; 2351 size = roundup(offset + size, PAGE_SIZE); 2352 kmem_free(kernel_map, base, size); 2353 } 2354 } 2355