1 /* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /* 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /* 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/powerpc.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/sr.h> 151 152 #define PMAP_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 157 #define TLBSYNC() __asm __volatile("tlbsync"); 158 #define SYNC() __asm __volatile("sync"); 159 #define EIEIO() __asm __volatile("eieio"); 160 161 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 162 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 163 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 164 165 #define PVO_PTEGIDX_MASK 0x0007 /* which PTEG slot */ 166 #define PVO_PTEGIDX_VALID 0x0008 /* slot is valid */ 167 #define PVO_WIRED 0x0010 /* PVO entry is wired */ 168 #define PVO_MANAGED 0x0020 /* PVO entry is managed */ 169 #define PVO_EXECUTABLE 0x0040 /* PVO entry is executable */ 170 #define PVO_BOOTSTRAP 0x0080 /* PVO entry allocated during 171 bootstrap */ 172 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 173 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 175 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 176 #define PVO_PTEGIDX_CLR(pvo) \ 177 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 178 #define PVO_PTEGIDX_SET(pvo, i) \ 179 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 180 181 #define PMAP_PVO_CHECK(pvo) 182 183 struct ofw_map { 184 vm_offset_t om_va; 185 vm_size_t om_len; 186 vm_offset_t om_pa; 187 u_int om_mode; 188 }; 189 190 int pmap_bootstrapped = 0; 191 192 /* 193 * Virtual and physical address of message buffer. 194 */ 195 struct msgbuf *msgbufp; 196 vm_offset_t msgbuf_phys; 197 198 int pmap_pagedaemon_waken; 199 200 /* 201 * Map of physical memory regions. 202 */ 203 vm_offset_t phys_avail[128]; 204 u_int phys_avail_count; 205 static struct mem_region *regions; 206 static struct mem_region *pregions; 207 int regions_sz, pregions_sz; 208 static struct ofw_map *translations; 209 210 /* 211 * First and last available kernel virtual addresses. 212 */ 213 vm_offset_t virtual_avail; 214 vm_offset_t virtual_end; 215 vm_offset_t kernel_vm_end; 216 217 /* 218 * Kernel pmap. 219 */ 220 struct pmap kernel_pmap_store; 221 extern struct pmap ofw_pmap; 222 223 /* 224 * Lock for the pteg and pvo tables. 225 */ 226 struct mtx pmap_table_mutex; 227 228 /* 229 * PTEG data. 230 */ 231 static struct pteg *pmap_pteg_table; 232 u_int pmap_pteg_count; 233 u_int pmap_pteg_mask; 234 235 /* 236 * PVO data. 237 */ 238 struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 239 struct pvo_head pmap_pvo_kunmanaged = 240 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 241 struct pvo_head pmap_pvo_unmanaged = 242 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 243 244 uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 245 uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 246 247 #define BPVO_POOL_SIZE 32768 248 static struct pvo_entry *pmap_bpvo_pool; 249 static int pmap_bpvo_pool_index = 0; 250 251 #define VSID_NBPW (sizeof(u_int32_t) * 8) 252 static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 253 254 static boolean_t pmap_initialized = FALSE; 255 256 /* 257 * Statistics. 258 */ 259 u_int pmap_pte_valid = 0; 260 u_int pmap_pte_overflow = 0; 261 u_int pmap_pte_replacements = 0; 262 u_int pmap_pvo_entries = 0; 263 u_int pmap_pvo_enter_calls = 0; 264 u_int pmap_pvo_remove_calls = 0; 265 u_int pmap_pte_spills = 0; 266 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 267 0, ""); 268 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 269 &pmap_pte_overflow, 0, ""); 270 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 271 &pmap_pte_replacements, 0, ""); 272 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 273 0, ""); 274 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 275 &pmap_pvo_enter_calls, 0, ""); 276 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 277 &pmap_pvo_remove_calls, 0, ""); 278 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 279 &pmap_pte_spills, 0, ""); 280 281 struct pvo_entry *pmap_pvo_zeropage; 282 283 vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 284 u_int pmap_rkva_count = 4; 285 286 /* 287 * Allocate physical memory for use in pmap_bootstrap. 288 */ 289 static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 290 291 /* 292 * PTE calls. 293 */ 294 static int pmap_pte_insert(u_int, struct pte *); 295 296 /* 297 * PVO calls. 298 */ 299 static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 300 vm_offset_t, vm_offset_t, u_int, int); 301 static void pmap_pvo_remove(struct pvo_entry *, int); 302 static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 303 static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 304 305 /* 306 * Utility routines. 307 */ 308 static struct pvo_entry *pmap_rkva_alloc(void); 309 static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 310 struct pte *, int *); 311 static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 312 static void pmap_syncicache(vm_offset_t, vm_size_t); 313 static boolean_t pmap_query_bit(vm_page_t, int); 314 static u_int pmap_clear_bit(vm_page_t, int, int *); 315 static void tlbia(void); 316 317 static __inline int 318 va_to_sr(u_int *sr, vm_offset_t va) 319 { 320 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 321 } 322 323 static __inline u_int 324 va_to_pteg(u_int sr, vm_offset_t addr) 325 { 326 u_int hash; 327 328 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 329 ADDR_PIDX_SHFT); 330 return (hash & pmap_pteg_mask); 331 } 332 333 static __inline struct pvo_head * 334 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 335 { 336 struct vm_page *pg; 337 338 pg = PHYS_TO_VM_PAGE(pa); 339 340 if (pg_p != NULL) 341 *pg_p = pg; 342 343 if (pg == NULL) 344 return (&pmap_pvo_unmanaged); 345 346 return (&pg->md.mdpg_pvoh); 347 } 348 349 static __inline struct pvo_head * 350 vm_page_to_pvoh(vm_page_t m) 351 { 352 353 return (&m->md.mdpg_pvoh); 354 } 355 356 static __inline void 357 pmap_attr_clear(vm_page_t m, int ptebit) 358 { 359 360 m->md.mdpg_attrs &= ~ptebit; 361 } 362 363 static __inline int 364 pmap_attr_fetch(vm_page_t m) 365 { 366 367 return (m->md.mdpg_attrs); 368 } 369 370 static __inline void 371 pmap_attr_save(vm_page_t m, int ptebit) 372 { 373 374 m->md.mdpg_attrs |= ptebit; 375 } 376 377 static __inline int 378 pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 379 { 380 if (pt->pte_hi == pvo_pt->pte_hi) 381 return (1); 382 383 return (0); 384 } 385 386 static __inline int 387 pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 388 { 389 return (pt->pte_hi & ~PTE_VALID) == 390 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 391 ((va >> ADDR_API_SHFT) & PTE_API) | which); 392 } 393 394 static __inline void 395 pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 396 { 397 /* 398 * Construct a PTE. Default to IMB initially. Valid bit only gets 399 * set when the real pte is set in memory. 400 * 401 * Note: Don't set the valid bit for correct operation of tlb update. 402 */ 403 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 404 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 405 pt->pte_lo = pte_lo; 406 } 407 408 static __inline void 409 pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 410 { 411 412 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 413 } 414 415 static __inline void 416 pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 417 { 418 419 /* 420 * As shown in Section 7.6.3.2.3 421 */ 422 pt->pte_lo &= ~ptebit; 423 TLBIE(va); 424 EIEIO(); 425 TLBSYNC(); 426 SYNC(); 427 } 428 429 static __inline void 430 pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 431 { 432 433 pvo_pt->pte_hi |= PTE_VALID; 434 435 /* 436 * Update the PTE as defined in section 7.6.3.1. 437 * Note that the REF/CHG bits are from pvo_pt and thus should havce 438 * been saved so this routine can restore them (if desired). 439 */ 440 pt->pte_lo = pvo_pt->pte_lo; 441 EIEIO(); 442 pt->pte_hi = pvo_pt->pte_hi; 443 SYNC(); 444 pmap_pte_valid++; 445 } 446 447 static __inline void 448 pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 449 { 450 451 pvo_pt->pte_hi &= ~PTE_VALID; 452 453 /* 454 * Force the reg & chg bits back into the PTEs. 455 */ 456 SYNC(); 457 458 /* 459 * Invalidate the pte. 460 */ 461 pt->pte_hi &= ~PTE_VALID; 462 463 SYNC(); 464 TLBIE(va); 465 EIEIO(); 466 TLBSYNC(); 467 SYNC(); 468 469 /* 470 * Save the reg & chg bits. 471 */ 472 pmap_pte_synch(pt, pvo_pt); 473 pmap_pte_valid--; 474 } 475 476 static __inline void 477 pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 478 { 479 480 /* 481 * Invalidate the PTE 482 */ 483 pmap_pte_unset(pt, pvo_pt, va); 484 pmap_pte_set(pt, pvo_pt); 485 } 486 487 /* 488 * Quick sort callout for comparing memory regions. 489 */ 490 static int mr_cmp(const void *a, const void *b); 491 static int om_cmp(const void *a, const void *b); 492 493 static int 494 mr_cmp(const void *a, const void *b) 495 { 496 const struct mem_region *regiona; 497 const struct mem_region *regionb; 498 499 regiona = a; 500 regionb = b; 501 if (regiona->mr_start < regionb->mr_start) 502 return (-1); 503 else if (regiona->mr_start > regionb->mr_start) 504 return (1); 505 else 506 return (0); 507 } 508 509 static int 510 om_cmp(const void *a, const void *b) 511 { 512 const struct ofw_map *mapa; 513 const struct ofw_map *mapb; 514 515 mapa = a; 516 mapb = b; 517 if (mapa->om_pa < mapb->om_pa) 518 return (-1); 519 else if (mapa->om_pa > mapb->om_pa) 520 return (1); 521 else 522 return (0); 523 } 524 525 void 526 pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 527 { 528 ihandle_t mmui; 529 phandle_t chosen, mmu; 530 int sz; 531 int i, j; 532 int ofw_mappings; 533 vm_size_t size, physsz; 534 vm_offset_t pa, va, off; 535 u_int batl, batu; 536 537 /* 538 * Set up BAT0 to map the lowest 256 MB area 539 */ 540 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 541 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 542 543 /* 544 * Map PCI memory space. 545 */ 546 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 547 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 548 549 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 550 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 551 552 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 553 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 554 555 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 556 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 557 558 /* 559 * Map obio devices. 560 */ 561 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 562 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 563 564 /* 565 * Use an IBAT and a DBAT to map the bottom segment of memory 566 * where we are. 567 */ 568 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 569 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 570 __asm ("mtibatu 0,%0; mtibatl 0,%1; isync; \n" 571 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 572 :: "r"(batu), "r"(batl)); 573 574 #if 0 575 /* map frame buffer */ 576 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 577 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 578 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 579 :: "r"(batu), "r"(batl)); 580 #endif 581 582 #if 1 583 /* map pci space */ 584 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 585 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 586 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 587 :: "r"(batu), "r"(batl)); 588 #endif 589 590 /* 591 * Set the start and end of kva. 592 */ 593 virtual_avail = VM_MIN_KERNEL_ADDRESS; 594 virtual_end = VM_MAX_KERNEL_ADDRESS; 595 596 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 597 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 598 599 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 600 for (i = 0; i < pregions_sz; i++) { 601 vm_offset_t pa; 602 vm_offset_t end; 603 604 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 605 pregions[i].mr_start, 606 pregions[i].mr_start + pregions[i].mr_size, 607 pregions[i].mr_size); 608 /* 609 * Install entries into the BAT table to allow all 610 * of physmem to be convered by on-demand BAT entries. 611 * The loop will sometimes set the same battable element 612 * twice, but that's fine since they won't be used for 613 * a while yet. 614 */ 615 pa = pregions[i].mr_start & 0xf0000000; 616 end = pregions[i].mr_start + pregions[i].mr_size; 617 do { 618 u_int n = pa >> ADDR_SR_SHFT; 619 620 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 621 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 622 pa += SEGMENT_LENGTH; 623 } while (pa < end); 624 } 625 626 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 627 panic("pmap_bootstrap: phys_avail too small"); 628 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 629 phys_avail_count = 0; 630 physsz = 0; 631 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 632 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 633 regions[i].mr_start + regions[i].mr_size, 634 regions[i].mr_size); 635 phys_avail[j] = regions[i].mr_start; 636 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 637 phys_avail_count++; 638 physsz += regions[i].mr_size; 639 } 640 physmem = btoc(physsz); 641 642 /* 643 * Allocate PTEG table. 644 */ 645 #ifdef PTEGCOUNT 646 pmap_pteg_count = PTEGCOUNT; 647 #else 648 pmap_pteg_count = 0x1000; 649 650 while (pmap_pteg_count < physmem) 651 pmap_pteg_count <<= 1; 652 653 pmap_pteg_count >>= 1; 654 #endif /* PTEGCOUNT */ 655 656 size = pmap_pteg_count * sizeof(struct pteg); 657 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 658 size); 659 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 660 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 661 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 662 pmap_pteg_mask = pmap_pteg_count - 1; 663 664 /* 665 * Allocate pv/overflow lists. 666 */ 667 size = sizeof(struct pvo_head) * pmap_pteg_count; 668 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 669 PAGE_SIZE); 670 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 671 for (i = 0; i < pmap_pteg_count; i++) 672 LIST_INIT(&pmap_pvo_table[i]); 673 674 /* 675 * Initialize the lock that synchronizes access to the pteg and pvo 676 * tables. 677 */ 678 mtx_init(&pmap_table_mutex, "pmap table", NULL, MTX_DEF); 679 680 /* 681 * Allocate the message buffer. 682 */ 683 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 684 685 /* 686 * Initialise the unmanaged pvo pool. 687 */ 688 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 689 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 690 pmap_bpvo_pool_index = 0; 691 692 /* 693 * Make sure kernel vsid is allocated as well as VSID 0. 694 */ 695 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 696 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 697 pmap_vsid_bitmap[0] |= 1; 698 699 /* 700 * Set up the Open Firmware pmap and add it's mappings. 701 */ 702 pmap_pinit(&ofw_pmap); 703 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 704 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 705 if ((chosen = OF_finddevice("/chosen")) == -1) 706 panic("pmap_bootstrap: can't find /chosen"); 707 OF_getprop(chosen, "mmu", &mmui, 4); 708 if ((mmu = OF_instance_to_package(mmui)) == -1) 709 panic("pmap_bootstrap: can't get mmu package"); 710 if ((sz = OF_getproplen(mmu, "translations")) == -1) 711 panic("pmap_bootstrap: can't get ofw translation count"); 712 translations = NULL; 713 for (i = 0; phys_avail[i] != 0; i += 2) { 714 if (phys_avail[i + 1] >= sz) { 715 translations = (struct ofw_map *)phys_avail[i]; 716 break; 717 } 718 } 719 if (translations == NULL) 720 panic("pmap_bootstrap: no space to copy translations"); 721 bzero(translations, sz); 722 if (OF_getprop(mmu, "translations", translations, sz) == -1) 723 panic("pmap_bootstrap: can't get ofw translations"); 724 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 725 sz /= sizeof(*translations); 726 qsort(translations, sz, sizeof (*translations), om_cmp); 727 for (i = 0, ofw_mappings = 0; i < sz; i++) { 728 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 729 translations[i].om_pa, translations[i].om_va, 730 translations[i].om_len); 731 732 /* 733 * If the mapping is 1:1, let the RAM and device on-demand 734 * BAT tables take care of the translation. 735 */ 736 if (translations[i].om_va == translations[i].om_pa) 737 continue; 738 739 /* Enter the pages */ 740 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 741 struct vm_page m; 742 743 m.phys_addr = translations[i].om_pa + off; 744 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 745 VM_PROT_ALL, 1); 746 ofw_mappings++; 747 } 748 } 749 #ifdef SMP 750 TLBSYNC(); 751 #endif 752 753 /* 754 * Initialize the kernel pmap (which is statically allocated). 755 */ 756 PMAP_LOCK_INIT(kernel_pmap); 757 for (i = 0; i < 16; i++) { 758 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 759 } 760 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 761 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL_SEGMENT; 762 kernel_pmap->pm_active = ~0; 763 764 /* 765 * Allocate a kernel stack with a guard page for thread0 and map it 766 * into the kernel page map. 767 */ 768 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 769 kstack0_phys = pa; 770 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 771 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 772 kstack0); 773 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 774 for (i = 0; i < KSTACK_PAGES; i++) { 775 pa = kstack0_phys + i * PAGE_SIZE; 776 va = kstack0 + i * PAGE_SIZE; 777 pmap_kenter(va, pa); 778 TLBIE(va); 779 } 780 781 /* 782 * Calculate the last available physical address. 783 */ 784 for (i = 0; phys_avail[i + 2] != 0; i += 2) 785 ; 786 Maxmem = powerpc_btop(phys_avail[i + 1]); 787 788 /* 789 * Allocate virtual address space for the message buffer. 790 */ 791 msgbufp = (struct msgbuf *)virtual_avail; 792 virtual_avail += round_page(MSGBUF_SIZE); 793 794 /* 795 * Initialize hardware. 796 */ 797 for (i = 0; i < 16; i++) { 798 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 799 } 800 __asm __volatile ("mtsr %0,%1" 801 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 802 __asm __volatile ("sync; mtsdr1 %0; isync" 803 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 804 tlbia(); 805 806 pmap_bootstrapped++; 807 } 808 809 /* 810 * Activate a user pmap. The pmap must be activated before it's address 811 * space can be accessed in any way. 812 */ 813 void 814 pmap_activate(struct thread *td) 815 { 816 pmap_t pm, pmr; 817 818 /* 819 * Load all the data we need up front to encourage the compiler to 820 * not issue any loads while we have interrupts disabled below. 821 */ 822 pm = &td->td_proc->p_vmspace->vm_pmap; 823 824 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 825 pmr = pm; 826 827 pm->pm_active |= PCPU_GET(cpumask); 828 PCPU_SET(curpmap, pmr); 829 } 830 831 void 832 pmap_deactivate(struct thread *td) 833 { 834 pmap_t pm; 835 836 pm = &td->td_proc->p_vmspace->vm_pmap; 837 pm->pm_active &= ~(PCPU_GET(cpumask)); 838 PCPU_SET(curpmap, NULL); 839 } 840 841 vm_offset_t 842 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 843 { 844 845 return (va); 846 } 847 848 void 849 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 850 { 851 struct pvo_entry *pvo; 852 853 PMAP_LOCK(pm); 854 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 855 856 if (pvo != NULL) { 857 if (wired) { 858 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 859 pm->pm_stats.wired_count++; 860 pvo->pvo_vaddr |= PVO_WIRED; 861 } else { 862 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 863 pm->pm_stats.wired_count--; 864 pvo->pvo_vaddr &= ~PVO_WIRED; 865 } 866 } 867 PMAP_UNLOCK(pm); 868 } 869 870 void 871 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 872 vm_size_t len, vm_offset_t src_addr) 873 { 874 875 /* 876 * This is not needed as it's mainly an optimisation. 877 * It may want to be implemented later though. 878 */ 879 } 880 881 void 882 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 883 { 884 vm_offset_t dst; 885 vm_offset_t src; 886 887 dst = VM_PAGE_TO_PHYS(mdst); 888 src = VM_PAGE_TO_PHYS(msrc); 889 890 kcopy((void *)src, (void *)dst, PAGE_SIZE); 891 } 892 893 /* 894 * Zero a page of physical memory by temporarily mapping it into the tlb. 895 */ 896 void 897 pmap_zero_page(vm_page_t m) 898 { 899 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 900 caddr_t va; 901 902 if (pa < SEGMENT_LENGTH) { 903 va = (caddr_t) pa; 904 } else if (pmap_initialized) { 905 if (pmap_pvo_zeropage == NULL) 906 pmap_pvo_zeropage = pmap_rkva_alloc(); 907 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 908 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 909 } else { 910 panic("pmap_zero_page: can't zero pa %#x", pa); 911 } 912 913 bzero(va, PAGE_SIZE); 914 915 if (pa >= SEGMENT_LENGTH) 916 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 917 } 918 919 void 920 pmap_zero_page_area(vm_page_t m, int off, int size) 921 { 922 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 923 caddr_t va; 924 925 if (pa < SEGMENT_LENGTH) { 926 va = (caddr_t) pa; 927 } else if (pmap_initialized) { 928 if (pmap_pvo_zeropage == NULL) 929 pmap_pvo_zeropage = pmap_rkva_alloc(); 930 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 931 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 932 } else { 933 panic("pmap_zero_page: can't zero pa %#x", pa); 934 } 935 936 bzero(va + off, size); 937 938 if (pa >= SEGMENT_LENGTH) 939 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 940 } 941 942 void 943 pmap_zero_page_idle(vm_page_t m) 944 { 945 946 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 947 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 948 mtx_lock(&Giant); 949 pmap_zero_page(m); 950 mtx_unlock(&Giant); 951 } 952 953 /* 954 * Map the given physical page at the specified virtual address in the 955 * target pmap with the protection requested. If specified the page 956 * will be wired down. 957 */ 958 void 959 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 960 boolean_t wired) 961 { 962 struct pvo_head *pvo_head; 963 uma_zone_t zone; 964 vm_page_t pg; 965 u_int pte_lo, pvo_flags, was_exec, i; 966 int error; 967 968 if (!pmap_initialized) { 969 pvo_head = &pmap_pvo_kunmanaged; 970 zone = pmap_upvo_zone; 971 pvo_flags = 0; 972 pg = NULL; 973 was_exec = PTE_EXEC; 974 } else { 975 pvo_head = vm_page_to_pvoh(m); 976 pg = m; 977 zone = pmap_mpvo_zone; 978 pvo_flags = PVO_MANAGED; 979 was_exec = 0; 980 } 981 if (pmap_bootstrapped) 982 vm_page_lock_queues(); 983 PMAP_LOCK(pmap); 984 985 /* 986 * If this is a managed page, and it's the first reference to the page, 987 * clear the execness of the page. Otherwise fetch the execness. 988 */ 989 if (pg != NULL) { 990 if (LIST_EMPTY(pvo_head)) { 991 pmap_attr_clear(pg, PTE_EXEC); 992 } else { 993 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 994 } 995 } 996 997 998 /* 999 * Assume the page is cache inhibited and access is guarded unless 1000 * it's in our available memory array. 1001 */ 1002 pte_lo = PTE_I | PTE_G; 1003 for (i = 0; i < pregions_sz; i++) { 1004 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1005 (VM_PAGE_TO_PHYS(m) < 1006 (pregions[i].mr_start + pregions[i].mr_size))) { 1007 pte_lo &= ~(PTE_I | PTE_G); 1008 break; 1009 } 1010 } 1011 1012 if (prot & VM_PROT_WRITE) 1013 pte_lo |= PTE_BW; 1014 else 1015 pte_lo |= PTE_BR; 1016 1017 pvo_flags |= (prot & VM_PROT_EXECUTE); 1018 1019 if (wired) 1020 pvo_flags |= PVO_WIRED; 1021 1022 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1023 pte_lo, pvo_flags); 1024 1025 /* 1026 * Flush the real page from the instruction cache if this page is 1027 * mapped executable and cacheable and was not previously mapped (or 1028 * was not mapped executable). 1029 */ 1030 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1031 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1032 /* 1033 * Flush the real memory from the cache. 1034 */ 1035 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1036 if (pg != NULL) 1037 pmap_attr_save(pg, PTE_EXEC); 1038 } 1039 if (pmap_bootstrapped) 1040 vm_page_unlock_queues(); 1041 1042 /* XXX syncicache always until problems are sorted */ 1043 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1044 PMAP_UNLOCK(pmap); 1045 } 1046 1047 vm_page_t 1048 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_page_t mpte) 1049 { 1050 1051 mtx_lock(&Giant); 1052 pmap_enter(pm, va, m, VM_PROT_READ | VM_PROT_EXECUTE, FALSE); 1053 mtx_unlock(&Giant); 1054 return (NULL); 1055 } 1056 1057 vm_paddr_t 1058 pmap_extract(pmap_t pm, vm_offset_t va) 1059 { 1060 struct pvo_entry *pvo; 1061 vm_paddr_t pa; 1062 1063 PMAP_LOCK(pm); 1064 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1065 if (pvo == NULL) 1066 pa = 0; 1067 else 1068 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1069 PMAP_UNLOCK(pm); 1070 return (pa); 1071 } 1072 1073 /* 1074 * Atomically extract and hold the physical page with the given 1075 * pmap and virtual address pair if that mapping permits the given 1076 * protection. 1077 */ 1078 vm_page_t 1079 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1080 { 1081 struct pvo_entry *pvo; 1082 vm_page_t m; 1083 1084 m = NULL; 1085 mtx_lock(&Giant); 1086 vm_page_lock_queues(); 1087 PMAP_LOCK(pmap); 1088 pvo = pmap_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1089 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) && 1090 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW || 1091 (prot & VM_PROT_WRITE) == 0)) { 1092 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1093 vm_page_hold(m); 1094 } 1095 vm_page_unlock_queues(); 1096 PMAP_UNLOCK(pmap); 1097 mtx_unlock(&Giant); 1098 return (m); 1099 } 1100 1101 /* 1102 * Grow the number of kernel page table entries. Unneeded. 1103 */ 1104 void 1105 pmap_growkernel(vm_offset_t addr) 1106 { 1107 } 1108 1109 void 1110 pmap_init(void) 1111 { 1112 1113 CTR0(KTR_PMAP, "pmap_init"); 1114 1115 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1116 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1117 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1118 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1119 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1120 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1121 pmap_initialized = TRUE; 1122 } 1123 1124 void 1125 pmap_init2(void) 1126 { 1127 1128 CTR0(KTR_PMAP, "pmap_init2"); 1129 } 1130 1131 boolean_t 1132 pmap_is_modified(vm_page_t m) 1133 { 1134 1135 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1136 return (FALSE); 1137 1138 return (pmap_query_bit(m, PTE_CHG)); 1139 } 1140 1141 /* 1142 * pmap_is_prefaultable: 1143 * 1144 * Return whether or not the specified virtual address is elgible 1145 * for prefault. 1146 */ 1147 boolean_t 1148 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1149 { 1150 1151 return (FALSE); 1152 } 1153 1154 void 1155 pmap_clear_reference(vm_page_t m) 1156 { 1157 1158 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1159 return; 1160 pmap_clear_bit(m, PTE_REF, NULL); 1161 } 1162 1163 void 1164 pmap_clear_modify(vm_page_t m) 1165 { 1166 1167 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1168 return; 1169 pmap_clear_bit(m, PTE_CHG, NULL); 1170 } 1171 1172 /* 1173 * pmap_ts_referenced: 1174 * 1175 * Return a count of reference bits for a page, clearing those bits. 1176 * It is not necessary for every reference bit to be cleared, but it 1177 * is necessary that 0 only be returned when there are truly no 1178 * reference bits set. 1179 * 1180 * XXX: The exact number of bits to check and clear is a matter that 1181 * should be tested and standardized at some point in the future for 1182 * optimal aging of shared pages. 1183 */ 1184 int 1185 pmap_ts_referenced(vm_page_t m) 1186 { 1187 int count; 1188 1189 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1190 return (0); 1191 1192 count = pmap_clear_bit(m, PTE_REF, NULL); 1193 1194 return (count); 1195 } 1196 1197 /* 1198 * Map a wired page into kernel virtual address space. 1199 */ 1200 void 1201 pmap_kenter(vm_offset_t va, vm_offset_t pa) 1202 { 1203 u_int pte_lo; 1204 int error; 1205 int i; 1206 1207 #if 0 1208 if (va < VM_MIN_KERNEL_ADDRESS) 1209 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1210 va); 1211 #endif 1212 1213 pte_lo = PTE_I | PTE_G; 1214 for (i = 0; i < pregions_sz; i++) { 1215 if ((pa >= pregions[i].mr_start) && 1216 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1217 pte_lo &= ~(PTE_I | PTE_G); 1218 break; 1219 } 1220 } 1221 1222 PMAP_LOCK(kernel_pmap); 1223 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1224 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1225 1226 if (error != 0 && error != ENOENT) 1227 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1228 pa, error); 1229 1230 /* 1231 * Flush the real memory from the instruction cache. 1232 */ 1233 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1234 pmap_syncicache(pa, PAGE_SIZE); 1235 } 1236 PMAP_UNLOCK(kernel_pmap); 1237 } 1238 1239 /* 1240 * Extract the physical page address associated with the given kernel virtual 1241 * address. 1242 */ 1243 vm_offset_t 1244 pmap_kextract(vm_offset_t va) 1245 { 1246 struct pvo_entry *pvo; 1247 vm_paddr_t pa; 1248 1249 #ifdef UMA_MD_SMALL_ALLOC 1250 /* 1251 * Allow direct mappings 1252 */ 1253 if (va < VM_MIN_KERNEL_ADDRESS) { 1254 return (va); 1255 } 1256 #endif 1257 1258 PMAP_LOCK(kernel_pmap); 1259 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1260 KASSERT(pvo != NULL, ("pmap_kextract: no addr found")); 1261 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1262 PMAP_UNLOCK(kernel_pmap); 1263 return (pa); 1264 } 1265 1266 /* 1267 * Remove a wired page from kernel virtual address space. 1268 */ 1269 void 1270 pmap_kremove(vm_offset_t va) 1271 { 1272 1273 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1274 } 1275 1276 /* 1277 * Map a range of physical addresses into kernel virtual address space. 1278 * 1279 * The value passed in *virt is a suggested virtual address for the mapping. 1280 * Architectures which can support a direct-mapped physical to virtual region 1281 * can return the appropriate address within that region, leaving '*virt' 1282 * unchanged. We cannot and therefore do not; *virt is updated with the 1283 * first usable address after the mapped region. 1284 */ 1285 vm_offset_t 1286 pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1287 { 1288 vm_offset_t sva, va; 1289 1290 sva = *virt; 1291 va = sva; 1292 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1293 pmap_kenter(va, pa_start); 1294 *virt = va; 1295 return (sva); 1296 } 1297 1298 int 1299 pmap_mincore(pmap_t pmap, vm_offset_t addr) 1300 { 1301 TODO; 1302 return (0); 1303 } 1304 1305 void 1306 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1307 vm_pindex_t pindex, vm_size_t size) 1308 { 1309 1310 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 1311 KASSERT(object->type == OBJT_DEVICE, 1312 ("pmap_object_init_pt: non-device object")); 1313 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1314 ("pmap_object_init_pt: non current pmap")); 1315 } 1316 1317 /* 1318 * Lower the permission for all mappings to a given page. 1319 */ 1320 void 1321 pmap_page_protect(vm_page_t m, vm_prot_t prot) 1322 { 1323 struct pvo_head *pvo_head; 1324 struct pvo_entry *pvo, *next_pvo; 1325 struct pte *pt; 1326 pmap_t pmap; 1327 1328 /* 1329 * Since the routine only downgrades protection, if the 1330 * maximal protection is desired, there isn't any change 1331 * to be made. 1332 */ 1333 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1334 (VM_PROT_READ|VM_PROT_WRITE)) 1335 return; 1336 1337 pvo_head = vm_page_to_pvoh(m); 1338 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1339 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1340 PMAP_PVO_CHECK(pvo); /* sanity check */ 1341 pmap = pvo->pvo_pmap; 1342 PMAP_LOCK(pmap); 1343 1344 /* 1345 * Downgrading to no mapping at all, we just remove the entry. 1346 */ 1347 if ((prot & VM_PROT_READ) == 0) { 1348 pmap_pvo_remove(pvo, -1); 1349 PMAP_UNLOCK(pmap); 1350 continue; 1351 } 1352 1353 /* 1354 * If EXEC permission is being revoked, just clear the flag 1355 * in the PVO. 1356 */ 1357 if ((prot & VM_PROT_EXECUTE) == 0) 1358 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1359 1360 /* 1361 * If this entry is already RO, don't diddle with the page 1362 * table. 1363 */ 1364 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1365 PMAP_UNLOCK(pmap); 1366 PMAP_PVO_CHECK(pvo); 1367 continue; 1368 } 1369 1370 /* 1371 * Grab the PTE before we diddle the bits so pvo_to_pte can 1372 * verify the pte contents are as expected. 1373 */ 1374 pt = pmap_pvo_to_pte(pvo, -1); 1375 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1376 pvo->pvo_pte.pte_lo |= PTE_BR; 1377 if (pt != NULL) 1378 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1379 PMAP_UNLOCK(pmap); 1380 PMAP_PVO_CHECK(pvo); /* sanity check */ 1381 } 1382 1383 /* 1384 * Downgrading from writeable: clear the VM page flag 1385 */ 1386 if ((prot & VM_PROT_WRITE) != VM_PROT_WRITE) 1387 vm_page_flag_clear(m, PG_WRITEABLE); 1388 } 1389 1390 /* 1391 * Returns true if the pmap's pv is one of the first 1392 * 16 pvs linked to from this page. This count may 1393 * be changed upwards or downwards in the future; it 1394 * is only necessary that true be returned for a small 1395 * subset of pmaps for proper page aging. 1396 */ 1397 boolean_t 1398 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1399 { 1400 int loops; 1401 struct pvo_entry *pvo; 1402 1403 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 1404 return FALSE; 1405 1406 loops = 0; 1407 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1408 if (pvo->pvo_pmap == pmap) 1409 return (TRUE); 1410 if (++loops >= 16) 1411 break; 1412 } 1413 1414 return (FALSE); 1415 } 1416 1417 static u_int pmap_vsidcontext; 1418 1419 void 1420 pmap_pinit(pmap_t pmap) 1421 { 1422 int i, mask; 1423 u_int entropy; 1424 1425 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("pmap_pinit: virt pmap")); 1426 PMAP_LOCK_INIT(pmap); 1427 1428 entropy = 0; 1429 __asm __volatile("mftb %0" : "=r"(entropy)); 1430 1431 /* 1432 * Allocate some segment registers for this pmap. 1433 */ 1434 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1435 u_int hash, n; 1436 1437 /* 1438 * Create a new value by mutiplying by a prime and adding in 1439 * entropy from the timebase register. This is to make the 1440 * VSID more random so that the PT hash function collides 1441 * less often. (Note that the prime casues gcc to do shifts 1442 * instead of a multiply.) 1443 */ 1444 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1445 hash = pmap_vsidcontext & (NPMAPS - 1); 1446 if (hash == 0) /* 0 is special, avoid it */ 1447 continue; 1448 n = hash >> 5; 1449 mask = 1 << (hash & (VSID_NBPW - 1)); 1450 hash = (pmap_vsidcontext & 0xfffff); 1451 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1452 /* anything free in this bucket? */ 1453 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1454 entropy = (pmap_vsidcontext >> 20); 1455 continue; 1456 } 1457 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1458 mask = 1 << i; 1459 hash &= 0xfffff & ~(VSID_NBPW - 1); 1460 hash |= i; 1461 } 1462 pmap_vsid_bitmap[n] |= mask; 1463 for (i = 0; i < 16; i++) 1464 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1465 return; 1466 } 1467 1468 panic("pmap_pinit: out of segments"); 1469 } 1470 1471 /* 1472 * Initialize the pmap associated with process 0. 1473 */ 1474 void 1475 pmap_pinit0(pmap_t pm) 1476 { 1477 1478 pmap_pinit(pm); 1479 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1480 } 1481 1482 /* 1483 * Set the physical protection on the specified range of this map as requested. 1484 */ 1485 void 1486 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1487 { 1488 struct pvo_entry *pvo; 1489 struct pte *pt; 1490 int pteidx; 1491 1492 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1493 eva, prot); 1494 1495 1496 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1497 ("pmap_protect: non current pmap")); 1498 1499 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1500 mtx_lock(&Giant); 1501 pmap_remove(pm, sva, eva); 1502 mtx_unlock(&Giant); 1503 return; 1504 } 1505 1506 mtx_lock(&Giant); 1507 vm_page_lock_queues(); 1508 PMAP_LOCK(pm); 1509 for (; sva < eva; sva += PAGE_SIZE) { 1510 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1511 if (pvo == NULL) 1512 continue; 1513 1514 if ((prot & VM_PROT_EXECUTE) == 0) 1515 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1516 1517 /* 1518 * Grab the PTE pointer before we diddle with the cached PTE 1519 * copy. 1520 */ 1521 pt = pmap_pvo_to_pte(pvo, pteidx); 1522 /* 1523 * Change the protection of the page. 1524 */ 1525 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1526 pvo->pvo_pte.pte_lo |= PTE_BR; 1527 1528 /* 1529 * If the PVO is in the page table, update that pte as well. 1530 */ 1531 if (pt != NULL) 1532 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1533 } 1534 vm_page_unlock_queues(); 1535 PMAP_UNLOCK(pm); 1536 mtx_unlock(&Giant); 1537 } 1538 1539 /* 1540 * Map a list of wired pages into kernel virtual address space. This is 1541 * intended for temporary mappings which do not need page modification or 1542 * references recorded. Existing mappings in the region are overwritten. 1543 */ 1544 void 1545 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1546 { 1547 vm_offset_t va; 1548 1549 va = sva; 1550 while (count-- > 0) { 1551 pmap_kenter(va, VM_PAGE_TO_PHYS(*m)); 1552 va += PAGE_SIZE; 1553 m++; 1554 } 1555 } 1556 1557 /* 1558 * Remove page mappings from kernel virtual address space. Intended for 1559 * temporary mappings entered by pmap_qenter. 1560 */ 1561 void 1562 pmap_qremove(vm_offset_t sva, int count) 1563 { 1564 vm_offset_t va; 1565 1566 va = sva; 1567 while (count-- > 0) { 1568 pmap_kremove(va); 1569 va += PAGE_SIZE; 1570 } 1571 } 1572 1573 void 1574 pmap_release(pmap_t pmap) 1575 { 1576 int idx, mask; 1577 1578 /* 1579 * Free segment register's VSID 1580 */ 1581 if (pmap->pm_sr[0] == 0) 1582 panic("pmap_release"); 1583 1584 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1585 mask = 1 << (idx % VSID_NBPW); 1586 idx /= VSID_NBPW; 1587 pmap_vsid_bitmap[idx] &= ~mask; 1588 PMAP_LOCK_DESTROY(pmap); 1589 } 1590 1591 /* 1592 * Remove the given range of addresses from the specified map. 1593 */ 1594 void 1595 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1596 { 1597 struct pvo_entry *pvo; 1598 int pteidx; 1599 1600 vm_page_lock_queues(); 1601 PMAP_LOCK(pm); 1602 for (; sva < eva; sva += PAGE_SIZE) { 1603 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1604 if (pvo != NULL) { 1605 pmap_pvo_remove(pvo, pteidx); 1606 } 1607 } 1608 vm_page_unlock_queues(); 1609 PMAP_UNLOCK(pm); 1610 } 1611 1612 /* 1613 * Remove physical page from all pmaps in which it resides. pmap_pvo_remove() 1614 * will reflect changes in pte's back to the vm_page. 1615 */ 1616 void 1617 pmap_remove_all(vm_page_t m) 1618 { 1619 struct pvo_head *pvo_head; 1620 struct pvo_entry *pvo, *next_pvo; 1621 pmap_t pmap; 1622 1623 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1624 1625 pvo_head = vm_page_to_pvoh(m); 1626 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1627 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1628 1629 PMAP_PVO_CHECK(pvo); /* sanity check */ 1630 pmap = pvo->pvo_pmap; 1631 PMAP_LOCK(pmap); 1632 pmap_pvo_remove(pvo, -1); 1633 PMAP_UNLOCK(pmap); 1634 } 1635 vm_page_flag_clear(m, PG_WRITEABLE); 1636 } 1637 1638 /* 1639 * Remove all pages from specified address space, this aids process exit 1640 * speeds. This is much faster than pmap_remove in the case of running down 1641 * an entire address space. Only works for the current pmap. 1642 */ 1643 void 1644 pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1645 { 1646 } 1647 1648 /* 1649 * Allocate a physical page of memory directly from the phys_avail map. 1650 * Can only be called from pmap_bootstrap before avail start and end are 1651 * calculated. 1652 */ 1653 static vm_offset_t 1654 pmap_bootstrap_alloc(vm_size_t size, u_int align) 1655 { 1656 vm_offset_t s, e; 1657 int i, j; 1658 1659 size = round_page(size); 1660 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1661 if (align != 0) 1662 s = (phys_avail[i] + align - 1) & ~(align - 1); 1663 else 1664 s = phys_avail[i]; 1665 e = s + size; 1666 1667 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1668 continue; 1669 1670 if (s == phys_avail[i]) { 1671 phys_avail[i] += size; 1672 } else if (e == phys_avail[i + 1]) { 1673 phys_avail[i + 1] -= size; 1674 } else { 1675 for (j = phys_avail_count * 2; j > i; j -= 2) { 1676 phys_avail[j] = phys_avail[j - 2]; 1677 phys_avail[j + 1] = phys_avail[j - 1]; 1678 } 1679 1680 phys_avail[i + 3] = phys_avail[i + 1]; 1681 phys_avail[i + 1] = s; 1682 phys_avail[i + 2] = e; 1683 phys_avail_count++; 1684 } 1685 1686 return (s); 1687 } 1688 panic("pmap_bootstrap_alloc: could not allocate memory"); 1689 } 1690 1691 /* 1692 * Return an unmapped pvo for a kernel virtual address. 1693 * Used by pmap functions that operate on physical pages. 1694 */ 1695 static struct pvo_entry * 1696 pmap_rkva_alloc(void) 1697 { 1698 struct pvo_entry *pvo; 1699 struct pte *pt; 1700 vm_offset_t kva; 1701 int pteidx; 1702 1703 if (pmap_rkva_count == 0) 1704 panic("pmap_rkva_alloc: no more reserved KVAs"); 1705 1706 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1707 pmap_kenter(kva, 0); 1708 1709 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1710 1711 if (pvo == NULL) 1712 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1713 1714 pt = pmap_pvo_to_pte(pvo, pteidx); 1715 1716 if (pt == NULL) 1717 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1718 1719 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1720 PVO_PTEGIDX_CLR(pvo); 1721 1722 pmap_pte_overflow++; 1723 1724 return (pvo); 1725 } 1726 1727 static void 1728 pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1729 int *depth_p) 1730 { 1731 struct pte *pt; 1732 1733 /* 1734 * If this pvo already has a valid pte, we need to save it so it can 1735 * be restored later. We then just reload the new PTE over the old 1736 * slot. 1737 */ 1738 if (saved_pt != NULL) { 1739 pt = pmap_pvo_to_pte(pvo, -1); 1740 1741 if (pt != NULL) { 1742 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1743 PVO_PTEGIDX_CLR(pvo); 1744 pmap_pte_overflow++; 1745 } 1746 1747 *saved_pt = pvo->pvo_pte; 1748 1749 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1750 } 1751 1752 pvo->pvo_pte.pte_lo |= pa; 1753 1754 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1755 panic("pmap_pa_map: could not spill pvo %p", pvo); 1756 1757 if (depth_p != NULL) 1758 (*depth_p)++; 1759 } 1760 1761 static void 1762 pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1763 { 1764 struct pte *pt; 1765 1766 pt = pmap_pvo_to_pte(pvo, -1); 1767 1768 if (pt != NULL) { 1769 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1770 PVO_PTEGIDX_CLR(pvo); 1771 pmap_pte_overflow++; 1772 } 1773 1774 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1775 1776 /* 1777 * If there is a saved PTE and it's valid, restore it and return. 1778 */ 1779 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1780 if (depth_p != NULL && --(*depth_p) == 0) 1781 panic("pmap_pa_unmap: restoring but depth == 0"); 1782 1783 pvo->pvo_pte = *saved_pt; 1784 1785 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1786 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1787 } 1788 } 1789 1790 static void 1791 pmap_syncicache(vm_offset_t pa, vm_size_t len) 1792 { 1793 __syncicache((void *)pa, len); 1794 } 1795 1796 static void 1797 tlbia(void) 1798 { 1799 caddr_t i; 1800 1801 SYNC(); 1802 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1803 TLBIE(i); 1804 EIEIO(); 1805 } 1806 TLBSYNC(); 1807 SYNC(); 1808 } 1809 1810 static int 1811 pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1812 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1813 { 1814 struct pvo_entry *pvo; 1815 u_int sr; 1816 int first; 1817 u_int ptegidx; 1818 int i; 1819 int bootstrap; 1820 1821 pmap_pvo_enter_calls++; 1822 first = 0; 1823 1824 bootstrap = 0; 1825 1826 /* 1827 * Compute the PTE Group index. 1828 */ 1829 va &= ~ADDR_POFF; 1830 sr = va_to_sr(pm->pm_sr, va); 1831 ptegidx = va_to_pteg(sr, va); 1832 1833 /* 1834 * Remove any existing mapping for this page. Reuse the pvo entry if 1835 * there is a mapping. 1836 */ 1837 mtx_lock(&pmap_table_mutex); 1838 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1839 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1840 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1841 (pvo->pvo_pte.pte_lo & PTE_PP) == 1842 (pte_lo & PTE_PP)) { 1843 mtx_unlock(&pmap_table_mutex); 1844 return (0); 1845 } 1846 pmap_pvo_remove(pvo, -1); 1847 break; 1848 } 1849 } 1850 1851 /* 1852 * If we aren't overwriting a mapping, try to allocate. 1853 */ 1854 if (pmap_initialized) { 1855 pvo = uma_zalloc(zone, M_NOWAIT); 1856 } else { 1857 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1858 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1859 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1860 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1861 } 1862 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1863 pmap_bpvo_pool_index++; 1864 bootstrap = 1; 1865 } 1866 1867 if (pvo == NULL) { 1868 mtx_unlock(&pmap_table_mutex); 1869 return (ENOMEM); 1870 } 1871 1872 pmap_pvo_entries++; 1873 pvo->pvo_vaddr = va; 1874 pvo->pvo_pmap = pm; 1875 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1876 pvo->pvo_vaddr &= ~ADDR_POFF; 1877 if (flags & VM_PROT_EXECUTE) 1878 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1879 if (flags & PVO_WIRED) 1880 pvo->pvo_vaddr |= PVO_WIRED; 1881 if (pvo_head != &pmap_pvo_kunmanaged) 1882 pvo->pvo_vaddr |= PVO_MANAGED; 1883 if (bootstrap) 1884 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1885 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1886 1887 /* 1888 * Remember if the list was empty and therefore will be the first 1889 * item. 1890 */ 1891 if (LIST_FIRST(pvo_head) == NULL) 1892 first = 1; 1893 1894 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1895 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1896 pm->pm_stats.wired_count++; 1897 pm->pm_stats.resident_count++; 1898 1899 /* 1900 * We hope this succeeds but it isn't required. 1901 */ 1902 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1903 if (i >= 0) { 1904 PVO_PTEGIDX_SET(pvo, i); 1905 } else { 1906 panic("pmap_pvo_enter: overflow"); 1907 pmap_pte_overflow++; 1908 } 1909 1910 mtx_unlock(&pmap_table_mutex); 1911 return (first ? ENOENT : 0); 1912 } 1913 1914 static void 1915 pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1916 { 1917 struct pte *pt; 1918 1919 /* 1920 * If there is an active pte entry, we need to deactivate it (and 1921 * save the ref & cfg bits). 1922 */ 1923 pt = pmap_pvo_to_pte(pvo, pteidx); 1924 if (pt != NULL) { 1925 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1926 PVO_PTEGIDX_CLR(pvo); 1927 } else { 1928 pmap_pte_overflow--; 1929 } 1930 1931 /* 1932 * Update our statistics. 1933 */ 1934 pvo->pvo_pmap->pm_stats.resident_count--; 1935 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1936 pvo->pvo_pmap->pm_stats.wired_count--; 1937 1938 /* 1939 * Save the REF/CHG bits into their cache if the page is managed. 1940 */ 1941 if (pvo->pvo_vaddr & PVO_MANAGED) { 1942 struct vm_page *pg; 1943 1944 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1945 if (pg != NULL) { 1946 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 1947 (PTE_REF | PTE_CHG)); 1948 } 1949 } 1950 1951 /* 1952 * Remove this PVO from the PV list. 1953 */ 1954 LIST_REMOVE(pvo, pvo_vlink); 1955 1956 /* 1957 * Remove this from the overflow list and return it to the pool 1958 * if we aren't going to reuse it. 1959 */ 1960 LIST_REMOVE(pvo, pvo_olink); 1961 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1962 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 1963 pmap_upvo_zone, pvo); 1964 pmap_pvo_entries--; 1965 pmap_pvo_remove_calls++; 1966 } 1967 1968 static __inline int 1969 pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1970 { 1971 int pteidx; 1972 1973 /* 1974 * We can find the actual pte entry without searching by grabbing 1975 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1976 * noticing the HID bit. 1977 */ 1978 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1979 if (pvo->pvo_pte.pte_hi & PTE_HID) 1980 pteidx ^= pmap_pteg_mask * 8; 1981 1982 return (pteidx); 1983 } 1984 1985 static struct pvo_entry * 1986 pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1987 { 1988 struct pvo_entry *pvo; 1989 int ptegidx; 1990 u_int sr; 1991 1992 va &= ~ADDR_POFF; 1993 sr = va_to_sr(pm->pm_sr, va); 1994 ptegidx = va_to_pteg(sr, va); 1995 1996 mtx_lock(&pmap_table_mutex); 1997 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1998 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1999 if (pteidx_p) 2000 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 2001 break; 2002 } 2003 } 2004 mtx_unlock(&pmap_table_mutex); 2005 2006 return (pvo); 2007 } 2008 2009 static struct pte * 2010 pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2011 { 2012 struct pte *pt; 2013 2014 /* 2015 * If we haven't been supplied the ptegidx, calculate it. 2016 */ 2017 if (pteidx == -1) { 2018 int ptegidx; 2019 u_int sr; 2020 2021 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2022 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2023 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 2024 } 2025 2026 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2027 2028 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2029 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 2030 "valid pte index", pvo); 2031 } 2032 2033 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2034 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 2035 "pvo but no valid pte", pvo); 2036 } 2037 2038 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2039 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 2040 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 2041 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 2042 } 2043 2044 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2045 != 0) { 2046 panic("pmap_pvo_to_pte: pvo %p pte does not match " 2047 "pte %p in pmap_pteg_table", pvo, pt); 2048 } 2049 2050 return (pt); 2051 } 2052 2053 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2054 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 2055 "pmap_pteg_table but valid in pvo", pvo, pt); 2056 } 2057 2058 return (NULL); 2059 } 2060 2061 /* 2062 * XXX: THIS STUFF SHOULD BE IN pte.c? 2063 */ 2064 int 2065 pmap_pte_spill(vm_offset_t addr) 2066 { 2067 struct pvo_entry *source_pvo, *victim_pvo; 2068 struct pvo_entry *pvo; 2069 int ptegidx, i, j; 2070 u_int sr; 2071 struct pteg *pteg; 2072 struct pte *pt; 2073 2074 pmap_pte_spills++; 2075 2076 sr = mfsrin(addr); 2077 ptegidx = va_to_pteg(sr, addr); 2078 2079 /* 2080 * Have to substitute some entry. Use the primary hash for this. 2081 * Use low bits of timebase as random generator. 2082 */ 2083 pteg = &pmap_pteg_table[ptegidx]; 2084 mtx_lock(&pmap_table_mutex); 2085 __asm __volatile("mftb %0" : "=r"(i)); 2086 i &= 7; 2087 pt = &pteg->pt[i]; 2088 2089 source_pvo = NULL; 2090 victim_pvo = NULL; 2091 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2092 /* 2093 * We need to find a pvo entry for this address. 2094 */ 2095 PMAP_PVO_CHECK(pvo); 2096 if (source_pvo == NULL && 2097 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2098 pvo->pvo_pte.pte_hi & PTE_HID)) { 2099 /* 2100 * Now found an entry to be spilled into the pteg. 2101 * The PTE is now valid, so we know it's active. 2102 */ 2103 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2104 2105 if (j >= 0) { 2106 PVO_PTEGIDX_SET(pvo, j); 2107 pmap_pte_overflow--; 2108 PMAP_PVO_CHECK(pvo); 2109 mtx_unlock(&pmap_table_mutex); 2110 return (1); 2111 } 2112 2113 source_pvo = pvo; 2114 2115 if (victim_pvo != NULL) 2116 break; 2117 } 2118 2119 /* 2120 * We also need the pvo entry of the victim we are replacing 2121 * so save the R & C bits of the PTE. 2122 */ 2123 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2124 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2125 victim_pvo = pvo; 2126 if (source_pvo != NULL) 2127 break; 2128 } 2129 } 2130 2131 if (source_pvo == NULL) { 2132 mtx_unlock(&pmap_table_mutex); 2133 return (0); 2134 } 2135 2136 if (victim_pvo == NULL) { 2137 if ((pt->pte_hi & PTE_HID) == 0) 2138 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2139 "entry", pt); 2140 2141 /* 2142 * If this is a secondary PTE, we need to search it's primary 2143 * pvo bucket for the matching PVO. 2144 */ 2145 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2146 pvo_olink) { 2147 PMAP_PVO_CHECK(pvo); 2148 /* 2149 * We also need the pvo entry of the victim we are 2150 * replacing so save the R & C bits of the PTE. 2151 */ 2152 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2153 victim_pvo = pvo; 2154 break; 2155 } 2156 } 2157 2158 if (victim_pvo == NULL) 2159 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2160 "entry", pt); 2161 } 2162 2163 /* 2164 * We are invalidating the TLB entry for the EA we are replacing even 2165 * though it's valid. If we don't, we lose any ref/chg bit changes 2166 * contained in the TLB entry. 2167 */ 2168 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2169 2170 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2171 pmap_pte_set(pt, &source_pvo->pvo_pte); 2172 2173 PVO_PTEGIDX_CLR(victim_pvo); 2174 PVO_PTEGIDX_SET(source_pvo, i); 2175 pmap_pte_replacements++; 2176 2177 PMAP_PVO_CHECK(victim_pvo); 2178 PMAP_PVO_CHECK(source_pvo); 2179 2180 mtx_unlock(&pmap_table_mutex); 2181 return (1); 2182 } 2183 2184 static int 2185 pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2186 { 2187 struct pte *pt; 2188 int i; 2189 2190 /* 2191 * First try primary hash. 2192 */ 2193 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2194 if ((pt->pte_hi & PTE_VALID) == 0) { 2195 pvo_pt->pte_hi &= ~PTE_HID; 2196 pmap_pte_set(pt, pvo_pt); 2197 return (i); 2198 } 2199 } 2200 2201 /* 2202 * Now try secondary hash. 2203 */ 2204 ptegidx ^= pmap_pteg_mask; 2205 ptegidx++; 2206 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2207 if ((pt->pte_hi & PTE_VALID) == 0) { 2208 pvo_pt->pte_hi |= PTE_HID; 2209 pmap_pte_set(pt, pvo_pt); 2210 return (i); 2211 } 2212 } 2213 2214 panic("pmap_pte_insert: overflow"); 2215 return (-1); 2216 } 2217 2218 static boolean_t 2219 pmap_query_bit(vm_page_t m, int ptebit) 2220 { 2221 struct pvo_entry *pvo; 2222 struct pte *pt; 2223 2224 #if 0 2225 if (pmap_attr_fetch(m) & ptebit) 2226 return (TRUE); 2227 #endif 2228 2229 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2230 PMAP_PVO_CHECK(pvo); /* sanity check */ 2231 2232 /* 2233 * See if we saved the bit off. If so, cache it and return 2234 * success. 2235 */ 2236 if (pvo->pvo_pte.pte_lo & ptebit) { 2237 pmap_attr_save(m, ptebit); 2238 PMAP_PVO_CHECK(pvo); /* sanity check */ 2239 return (TRUE); 2240 } 2241 } 2242 2243 /* 2244 * No luck, now go through the hard part of looking at the PTEs 2245 * themselves. Sync so that any pending REF/CHG bits are flushed to 2246 * the PTEs. 2247 */ 2248 SYNC(); 2249 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2250 PMAP_PVO_CHECK(pvo); /* sanity check */ 2251 2252 /* 2253 * See if this pvo has a valid PTE. if so, fetch the 2254 * REF/CHG bits from the valid PTE. If the appropriate 2255 * ptebit is set, cache it and return success. 2256 */ 2257 pt = pmap_pvo_to_pte(pvo, -1); 2258 if (pt != NULL) { 2259 pmap_pte_synch(pt, &pvo->pvo_pte); 2260 if (pvo->pvo_pte.pte_lo & ptebit) { 2261 pmap_attr_save(m, ptebit); 2262 PMAP_PVO_CHECK(pvo); /* sanity check */ 2263 return (TRUE); 2264 } 2265 } 2266 } 2267 2268 return (FALSE); 2269 } 2270 2271 static u_int 2272 pmap_clear_bit(vm_page_t m, int ptebit, int *origbit) 2273 { 2274 u_int count; 2275 struct pvo_entry *pvo; 2276 struct pte *pt; 2277 int rv; 2278 2279 /* 2280 * Clear the cached value. 2281 */ 2282 rv = pmap_attr_fetch(m); 2283 pmap_attr_clear(m, ptebit); 2284 2285 /* 2286 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2287 * we can reset the right ones). note that since the pvo entries and 2288 * list heads are accessed via BAT0 and are never placed in the page 2289 * table, we don't have to worry about further accesses setting the 2290 * REF/CHG bits. 2291 */ 2292 SYNC(); 2293 2294 /* 2295 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2296 * valid pte clear the ptebit from the valid pte. 2297 */ 2298 count = 0; 2299 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2300 PMAP_PVO_CHECK(pvo); /* sanity check */ 2301 pt = pmap_pvo_to_pte(pvo, -1); 2302 if (pt != NULL) { 2303 pmap_pte_synch(pt, &pvo->pvo_pte); 2304 if (pvo->pvo_pte.pte_lo & ptebit) { 2305 count++; 2306 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2307 } 2308 } 2309 rv |= pvo->pvo_pte.pte_lo; 2310 pvo->pvo_pte.pte_lo &= ~ptebit; 2311 PMAP_PVO_CHECK(pvo); /* sanity check */ 2312 } 2313 2314 if (origbit != NULL) { 2315 *origbit = rv; 2316 } 2317 2318 return (count); 2319 } 2320 2321 /* 2322 * Return true if the physical range is encompassed by the battable[idx] 2323 */ 2324 static int 2325 pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2326 { 2327 u_int prot; 2328 u_int32_t start; 2329 u_int32_t end; 2330 u_int32_t bat_ble; 2331 2332 /* 2333 * Return immediately if not a valid mapping 2334 */ 2335 if (!battable[idx].batu & BAT_Vs) 2336 return (EINVAL); 2337 2338 /* 2339 * The BAT entry must be cache-inhibited, guarded, and r/w 2340 * so it can function as an i/o page 2341 */ 2342 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2343 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2344 return (EPERM); 2345 2346 /* 2347 * The address should be within the BAT range. Assume that the 2348 * start address in the BAT has the correct alignment (thus 2349 * not requiring masking) 2350 */ 2351 start = battable[idx].batl & BAT_PBS; 2352 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2353 end = start | (bat_ble << 15) | 0x7fff; 2354 2355 if ((pa < start) || ((pa + size) > end)) 2356 return (ERANGE); 2357 2358 return (0); 2359 } 2360 2361 int 2362 pmap_dev_direct_mapped(vm_offset_t pa, vm_size_t size) 2363 { 2364 int i; 2365 2366 /* 2367 * This currently does not work for entries that 2368 * overlap 256M BAT segments. 2369 */ 2370 2371 for(i = 0; i < 16; i++) 2372 if (pmap_bat_mapped(i, pa, size) == 0) 2373 return (0); 2374 2375 return (EFAULT); 2376 } 2377 2378 /* 2379 * Map a set of physical memory pages into the kernel virtual 2380 * address space. Return a pointer to where it is mapped. This 2381 * routine is intended to be used for mapping device memory, 2382 * NOT real memory. 2383 */ 2384 void * 2385 pmap_mapdev(vm_offset_t pa, vm_size_t size) 2386 { 2387 vm_offset_t va, tmpva, ppa, offset; 2388 int i; 2389 2390 ppa = trunc_page(pa); 2391 offset = pa & PAGE_MASK; 2392 size = roundup(offset + size, PAGE_SIZE); 2393 2394 GIANT_REQUIRED; 2395 2396 /* 2397 * If the physical address lies within a valid BAT table entry, 2398 * return the 1:1 mapping. This currently doesn't work 2399 * for regions that overlap 256M BAT segments. 2400 */ 2401 for (i = 0; i < 16; i++) { 2402 if (pmap_bat_mapped(i, pa, size) == 0) 2403 return ((void *) pa); 2404 } 2405 2406 va = kmem_alloc_nofault(kernel_map, size); 2407 if (!va) 2408 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2409 2410 for (tmpva = va; size > 0;) { 2411 pmap_kenter(tmpva, ppa); 2412 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2413 size -= PAGE_SIZE; 2414 tmpva += PAGE_SIZE; 2415 ppa += PAGE_SIZE; 2416 } 2417 2418 return ((void *)(va + offset)); 2419 } 2420 2421 void 2422 pmap_unmapdev(vm_offset_t va, vm_size_t size) 2423 { 2424 vm_offset_t base, offset; 2425 2426 /* 2427 * If this is outside kernel virtual space, then it's a 2428 * battable entry and doesn't require unmapping 2429 */ 2430 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2431 base = trunc_page(va); 2432 offset = va & PAGE_MASK; 2433 size = roundup(offset + size, PAGE_SIZE); 2434 kmem_free(kernel_map, base, size); 2435 } 2436 } 2437