1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/queue.h> 122 #include <sys/cpuset.h> 123 #include <sys/ktr.h> 124 #include <sys/lock.h> 125 #include <sys/msgbuf.h> 126 #include <sys/mutex.h> 127 #include <sys/proc.h> 128 #include <sys/sched.h> 129 #include <sys/sysctl.h> 130 #include <sys/systm.h> 131 #include <sys/vmmeter.h> 132 133 #include <dev/ofw/openfirm.h> 134 135 #include <vm/vm.h> 136 #include <vm/vm_param.h> 137 #include <vm/vm_kern.h> 138 #include <vm/vm_page.h> 139 #include <vm/vm_map.h> 140 #include <vm/vm_object.h> 141 #include <vm/vm_extern.h> 142 #include <vm/vm_pageout.h> 143 #include <vm/vm_pager.h> 144 #include <vm/uma.h> 145 146 #include <machine/cpu.h> 147 #include <machine/platform.h> 148 #include <machine/bat.h> 149 #include <machine/frame.h> 150 #include <machine/md_var.h> 151 #include <machine/psl.h> 152 #include <machine/pte.h> 153 #include <machine/smp.h> 154 #include <machine/sr.h> 155 #include <machine/mmuvar.h> 156 157 #include "mmu_if.h" 158 159 #define MOEA_DEBUG 160 161 #define TODO panic("%s: not implemented", __func__); 162 163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 165 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 166 167 struct ofw_map { 168 vm_offset_t om_va; 169 vm_size_t om_len; 170 vm_offset_t om_pa; 171 u_int om_mode; 172 }; 173 174 /* 175 * Map of physical memory regions. 176 */ 177 static struct mem_region *regions; 178 static struct mem_region *pregions; 179 static u_int phys_avail_count; 180 static int regions_sz, pregions_sz; 181 static struct ofw_map *translations; 182 183 /* 184 * Lock for the pteg and pvo tables. 185 */ 186 struct mtx moea_table_mutex; 187 struct mtx moea_vsid_mutex; 188 189 /* tlbie instruction synchronization */ 190 static struct mtx tlbie_mtx; 191 192 /* 193 * PTEG data. 194 */ 195 static struct pteg *moea_pteg_table; 196 u_int moea_pteg_count; 197 u_int moea_pteg_mask; 198 199 /* 200 * PVO data. 201 */ 202 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 203 struct pvo_head moea_pvo_kunmanaged = 204 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 205 206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 208 209 #define BPVO_POOL_SIZE 32768 210 static struct pvo_entry *moea_bpvo_pool; 211 static int moea_bpvo_pool_index = 0; 212 213 #define VSID_NBPW (sizeof(u_int32_t) * 8) 214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 215 216 static boolean_t moea_initialized = FALSE; 217 218 /* 219 * Statistics. 220 */ 221 u_int moea_pte_valid = 0; 222 u_int moea_pte_overflow = 0; 223 u_int moea_pte_replacements = 0; 224 u_int moea_pvo_entries = 0; 225 u_int moea_pvo_enter_calls = 0; 226 u_int moea_pvo_remove_calls = 0; 227 u_int moea_pte_spills = 0; 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 229 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 231 &moea_pte_overflow, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 233 &moea_pte_replacements, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 235 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 237 &moea_pvo_enter_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 239 &moea_pvo_remove_calls, 0, ""); 240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 241 &moea_pte_spills, 0, ""); 242 243 /* 244 * Allocate physical memory for use in moea_bootstrap. 245 */ 246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 247 248 /* 249 * PTE calls. 250 */ 251 static int moea_pte_insert(u_int, struct pte *); 252 253 /* 254 * PVO calls. 255 */ 256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 257 vm_offset_t, vm_offset_t, u_int, int); 258 static void moea_pvo_remove(struct pvo_entry *, int); 259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 261 262 /* 263 * Utility routines. 264 */ 265 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 266 vm_prot_t, boolean_t); 267 static void moea_syncicache(vm_offset_t, vm_size_t); 268 static boolean_t moea_query_bit(vm_page_t, int); 269 static u_int moea_clear_bit(vm_page_t, int); 270 static void moea_kremove(mmu_t, vm_offset_t); 271 int moea_pte_spill(vm_offset_t); 272 273 /* 274 * Kernel MMU interface 275 */ 276 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 277 void moea_clear_modify(mmu_t, vm_page_t); 278 void moea_clear_reference(mmu_t, vm_page_t); 279 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 280 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 281 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 282 vm_prot_t); 283 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 284 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 285 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 286 void moea_init(mmu_t); 287 boolean_t moea_is_modified(mmu_t, vm_page_t); 288 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 289 boolean_t moea_is_referenced(mmu_t, vm_page_t); 290 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 291 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 292 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 293 int moea_page_wired_mappings(mmu_t, vm_page_t); 294 void moea_pinit(mmu_t, pmap_t); 295 void moea_pinit0(mmu_t, pmap_t); 296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 298 void moea_qremove(mmu_t, vm_offset_t, int); 299 void moea_release(mmu_t, pmap_t); 300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(mmu_t, vm_page_t); 302 void moea_remove_write(mmu_t, vm_page_t); 303 void moea_zero_page(mmu_t, vm_page_t); 304 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 305 void moea_zero_page_idle(mmu_t, vm_page_t); 306 void moea_activate(mmu_t, struct thread *); 307 void moea_deactivate(mmu_t, struct thread *); 308 void moea_cpu_bootstrap(mmu_t, int); 309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 310 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 311 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 313 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 315 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 319 320 static mmu_method_t moea_methods[] = { 321 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 322 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 323 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 324 MMUMETHOD(mmu_copy_page, moea_copy_page), 325 MMUMETHOD(mmu_enter, moea_enter), 326 MMUMETHOD(mmu_enter_object, moea_enter_object), 327 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 328 MMUMETHOD(mmu_extract, moea_extract), 329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 330 MMUMETHOD(mmu_init, moea_init), 331 MMUMETHOD(mmu_is_modified, moea_is_modified), 332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 333 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 335 MMUMETHOD(mmu_map, moea_map), 336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 338 MMUMETHOD(mmu_pinit, moea_pinit), 339 MMUMETHOD(mmu_pinit0, moea_pinit0), 340 MMUMETHOD(mmu_protect, moea_protect), 341 MMUMETHOD(mmu_qenter, moea_qenter), 342 MMUMETHOD(mmu_qremove, moea_qremove), 343 MMUMETHOD(mmu_release, moea_release), 344 MMUMETHOD(mmu_remove, moea_remove), 345 MMUMETHOD(mmu_remove_all, moea_remove_all), 346 MMUMETHOD(mmu_remove_write, moea_remove_write), 347 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 348 MMUMETHOD(mmu_zero_page, moea_zero_page), 349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 351 MMUMETHOD(mmu_activate, moea_activate), 352 MMUMETHOD(mmu_deactivate, moea_deactivate), 353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 354 355 /* Internal interfaces */ 356 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 359 MMUMETHOD(mmu_mapdev, moea_mapdev), 360 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 361 MMUMETHOD(mmu_kextract, moea_kextract), 362 MMUMETHOD(mmu_kenter, moea_kenter), 363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 365 366 { 0, 0 } 367 }; 368 369 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 370 371 static __inline uint32_t 372 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 373 { 374 uint32_t pte_lo; 375 int i; 376 377 if (ma != VM_MEMATTR_DEFAULT) { 378 switch (ma) { 379 case VM_MEMATTR_UNCACHEABLE: 380 return (PTE_I | PTE_G); 381 case VM_MEMATTR_WRITE_COMBINING: 382 case VM_MEMATTR_WRITE_BACK: 383 case VM_MEMATTR_PREFETCHABLE: 384 return (PTE_I); 385 case VM_MEMATTR_WRITE_THROUGH: 386 return (PTE_W | PTE_M); 387 } 388 } 389 390 /* 391 * Assume the page is cache inhibited and access is guarded unless 392 * it's in our available memory array. 393 */ 394 pte_lo = PTE_I | PTE_G; 395 for (i = 0; i < pregions_sz; i++) { 396 if ((pa >= pregions[i].mr_start) && 397 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 398 pte_lo = PTE_M; 399 break; 400 } 401 } 402 403 return pte_lo; 404 } 405 406 static void 407 tlbie(vm_offset_t va) 408 { 409 410 mtx_lock_spin(&tlbie_mtx); 411 __asm __volatile("ptesync"); 412 __asm __volatile("tlbie %0" :: "r"(va)); 413 __asm __volatile("eieio; tlbsync; ptesync"); 414 mtx_unlock_spin(&tlbie_mtx); 415 } 416 417 static void 418 tlbia(void) 419 { 420 vm_offset_t va; 421 422 for (va = 0; va < 0x00040000; va += 0x00001000) { 423 __asm __volatile("tlbie %0" :: "r"(va)); 424 powerpc_sync(); 425 } 426 __asm __volatile("tlbsync"); 427 powerpc_sync(); 428 } 429 430 static __inline int 431 va_to_sr(u_int *sr, vm_offset_t va) 432 { 433 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 434 } 435 436 static __inline u_int 437 va_to_pteg(u_int sr, vm_offset_t addr) 438 { 439 u_int hash; 440 441 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 442 ADDR_PIDX_SHFT); 443 return (hash & moea_pteg_mask); 444 } 445 446 static __inline struct pvo_head * 447 vm_page_to_pvoh(vm_page_t m) 448 { 449 450 return (&m->md.mdpg_pvoh); 451 } 452 453 static __inline void 454 moea_attr_clear(vm_page_t m, int ptebit) 455 { 456 457 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 458 m->md.mdpg_attrs &= ~ptebit; 459 } 460 461 static __inline int 462 moea_attr_fetch(vm_page_t m) 463 { 464 465 return (m->md.mdpg_attrs); 466 } 467 468 static __inline void 469 moea_attr_save(vm_page_t m, int ptebit) 470 { 471 472 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 473 m->md.mdpg_attrs |= ptebit; 474 } 475 476 static __inline int 477 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 478 { 479 if (pt->pte_hi == pvo_pt->pte_hi) 480 return (1); 481 482 return (0); 483 } 484 485 static __inline int 486 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 487 { 488 return (pt->pte_hi & ~PTE_VALID) == 489 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 490 ((va >> ADDR_API_SHFT) & PTE_API) | which); 491 } 492 493 static __inline void 494 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 495 { 496 497 mtx_assert(&moea_table_mutex, MA_OWNED); 498 499 /* 500 * Construct a PTE. Default to IMB initially. Valid bit only gets 501 * set when the real pte is set in memory. 502 * 503 * Note: Don't set the valid bit for correct operation of tlb update. 504 */ 505 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 506 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 507 pt->pte_lo = pte_lo; 508 } 509 510 static __inline void 511 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 512 { 513 514 mtx_assert(&moea_table_mutex, MA_OWNED); 515 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 516 } 517 518 static __inline void 519 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 520 { 521 522 mtx_assert(&moea_table_mutex, MA_OWNED); 523 524 /* 525 * As shown in Section 7.6.3.2.3 526 */ 527 pt->pte_lo &= ~ptebit; 528 tlbie(va); 529 } 530 531 static __inline void 532 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 533 { 534 535 mtx_assert(&moea_table_mutex, MA_OWNED); 536 pvo_pt->pte_hi |= PTE_VALID; 537 538 /* 539 * Update the PTE as defined in section 7.6.3.1. 540 * Note that the REF/CHG bits are from pvo_pt and thus should havce 541 * been saved so this routine can restore them (if desired). 542 */ 543 pt->pte_lo = pvo_pt->pte_lo; 544 powerpc_sync(); 545 pt->pte_hi = pvo_pt->pte_hi; 546 powerpc_sync(); 547 moea_pte_valid++; 548 } 549 550 static __inline void 551 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 552 { 553 554 mtx_assert(&moea_table_mutex, MA_OWNED); 555 pvo_pt->pte_hi &= ~PTE_VALID; 556 557 /* 558 * Force the reg & chg bits back into the PTEs. 559 */ 560 powerpc_sync(); 561 562 /* 563 * Invalidate the pte. 564 */ 565 pt->pte_hi &= ~PTE_VALID; 566 567 tlbie(va); 568 569 /* 570 * Save the reg & chg bits. 571 */ 572 moea_pte_synch(pt, pvo_pt); 573 moea_pte_valid--; 574 } 575 576 static __inline void 577 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 578 { 579 580 /* 581 * Invalidate the PTE 582 */ 583 moea_pte_unset(pt, pvo_pt, va); 584 moea_pte_set(pt, pvo_pt); 585 } 586 587 /* 588 * Quick sort callout for comparing memory regions. 589 */ 590 static int mr_cmp(const void *a, const void *b); 591 static int om_cmp(const void *a, const void *b); 592 593 static int 594 mr_cmp(const void *a, const void *b) 595 { 596 const struct mem_region *regiona; 597 const struct mem_region *regionb; 598 599 regiona = a; 600 regionb = b; 601 if (regiona->mr_start < regionb->mr_start) 602 return (-1); 603 else if (regiona->mr_start > regionb->mr_start) 604 return (1); 605 else 606 return (0); 607 } 608 609 static int 610 om_cmp(const void *a, const void *b) 611 { 612 const struct ofw_map *mapa; 613 const struct ofw_map *mapb; 614 615 mapa = a; 616 mapb = b; 617 if (mapa->om_pa < mapb->om_pa) 618 return (-1); 619 else if (mapa->om_pa > mapb->om_pa) 620 return (1); 621 else 622 return (0); 623 } 624 625 void 626 moea_cpu_bootstrap(mmu_t mmup, int ap) 627 { 628 u_int sdr; 629 int i; 630 631 if (ap) { 632 powerpc_sync(); 633 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 634 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 635 isync(); 636 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 637 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 638 isync(); 639 } 640 641 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 642 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 643 isync(); 644 645 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 646 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 647 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 648 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 649 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 650 isync(); 651 652 for (i = 0; i < 16; i++) 653 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 654 powerpc_sync(); 655 656 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 657 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 658 isync(); 659 660 tlbia(); 661 } 662 663 void 664 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 665 { 666 ihandle_t mmui; 667 phandle_t chosen, mmu; 668 int sz; 669 int i, j; 670 vm_size_t size, physsz, hwphyssz; 671 vm_offset_t pa, va, off; 672 void *dpcpu; 673 register_t msr; 674 675 /* 676 * Set up BAT0 to map the lowest 256 MB area 677 */ 678 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 679 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 680 681 /* 682 * Map PCI memory space. 683 */ 684 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 686 687 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 689 690 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 692 693 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 694 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 695 696 /* 697 * Map obio devices. 698 */ 699 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 700 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 701 702 /* 703 * Use an IBAT and a DBAT to map the bottom segment of memory 704 * where we are. Turn off instruction relocation temporarily 705 * to prevent faults while reprogramming the IBAT. 706 */ 707 msr = mfmsr(); 708 mtmsr(msr & ~PSL_IR); 709 __asm (".balign 32; \n" 710 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 711 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 712 :: "r"(battable[0].batu), "r"(battable[0].batl)); 713 mtmsr(msr); 714 715 /* map pci space */ 716 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 717 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 718 isync(); 719 720 /* set global direct map flag */ 721 hw_direct_map = 1; 722 723 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 724 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 725 726 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 727 for (i = 0; i < pregions_sz; i++) { 728 vm_offset_t pa; 729 vm_offset_t end; 730 731 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 732 pregions[i].mr_start, 733 pregions[i].mr_start + pregions[i].mr_size, 734 pregions[i].mr_size); 735 /* 736 * Install entries into the BAT table to allow all 737 * of physmem to be convered by on-demand BAT entries. 738 * The loop will sometimes set the same battable element 739 * twice, but that's fine since they won't be used for 740 * a while yet. 741 */ 742 pa = pregions[i].mr_start & 0xf0000000; 743 end = pregions[i].mr_start + pregions[i].mr_size; 744 do { 745 u_int n = pa >> ADDR_SR_SHFT; 746 747 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 748 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 749 pa += SEGMENT_LENGTH; 750 } while (pa < end); 751 } 752 753 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 754 panic("moea_bootstrap: phys_avail too small"); 755 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 756 phys_avail_count = 0; 757 physsz = 0; 758 hwphyssz = 0; 759 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 760 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 761 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 762 regions[i].mr_start + regions[i].mr_size, 763 regions[i].mr_size); 764 if (hwphyssz != 0 && 765 (physsz + regions[i].mr_size) >= hwphyssz) { 766 if (physsz < hwphyssz) { 767 phys_avail[j] = regions[i].mr_start; 768 phys_avail[j + 1] = regions[i].mr_start + 769 hwphyssz - physsz; 770 physsz = hwphyssz; 771 phys_avail_count++; 772 } 773 break; 774 } 775 phys_avail[j] = regions[i].mr_start; 776 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 777 phys_avail_count++; 778 physsz += regions[i].mr_size; 779 } 780 physmem = btoc(physsz); 781 782 /* 783 * Allocate PTEG table. 784 */ 785 #ifdef PTEGCOUNT 786 moea_pteg_count = PTEGCOUNT; 787 #else 788 moea_pteg_count = 0x1000; 789 790 while (moea_pteg_count < physmem) 791 moea_pteg_count <<= 1; 792 793 moea_pteg_count >>= 1; 794 #endif /* PTEGCOUNT */ 795 796 size = moea_pteg_count * sizeof(struct pteg); 797 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 798 size); 799 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 800 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 801 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 802 moea_pteg_mask = moea_pteg_count - 1; 803 804 /* 805 * Allocate pv/overflow lists. 806 */ 807 size = sizeof(struct pvo_head) * moea_pteg_count; 808 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 809 PAGE_SIZE); 810 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 811 for (i = 0; i < moea_pteg_count; i++) 812 LIST_INIT(&moea_pvo_table[i]); 813 814 /* 815 * Initialize the lock that synchronizes access to the pteg and pvo 816 * tables. 817 */ 818 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 819 MTX_RECURSE); 820 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 821 822 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 823 824 /* 825 * Initialise the unmanaged pvo pool. 826 */ 827 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 828 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 829 moea_bpvo_pool_index = 0; 830 831 /* 832 * Make sure kernel vsid is allocated as well as VSID 0. 833 */ 834 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 835 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 836 moea_vsid_bitmap[0] |= 1; 837 838 /* 839 * Initialize the kernel pmap (which is statically allocated). 840 */ 841 PMAP_LOCK_INIT(kernel_pmap); 842 for (i = 0; i < 16; i++) 843 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 844 CPU_FILL(&kernel_pmap->pm_active); 845 846 /* 847 * Set up the Open Firmware mappings 848 */ 849 if ((chosen = OF_finddevice("/chosen")) == -1) 850 panic("moea_bootstrap: can't find /chosen"); 851 OF_getprop(chosen, "mmu", &mmui, 4); 852 if ((mmu = OF_instance_to_package(mmui)) == -1) 853 panic("moea_bootstrap: can't get mmu package"); 854 if ((sz = OF_getproplen(mmu, "translations")) == -1) 855 panic("moea_bootstrap: can't get ofw translation count"); 856 translations = NULL; 857 for (i = 0; phys_avail[i] != 0; i += 2) { 858 if (phys_avail[i + 1] >= sz) { 859 translations = (struct ofw_map *)phys_avail[i]; 860 break; 861 } 862 } 863 if (translations == NULL) 864 panic("moea_bootstrap: no space to copy translations"); 865 bzero(translations, sz); 866 if (OF_getprop(mmu, "translations", translations, sz) == -1) 867 panic("moea_bootstrap: can't get ofw translations"); 868 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 869 sz /= sizeof(*translations); 870 qsort(translations, sz, sizeof (*translations), om_cmp); 871 for (i = 0; i < sz; i++) { 872 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 873 translations[i].om_pa, translations[i].om_va, 874 translations[i].om_len); 875 876 /* 877 * If the mapping is 1:1, let the RAM and device on-demand 878 * BAT tables take care of the translation. 879 */ 880 if (translations[i].om_va == translations[i].om_pa) 881 continue; 882 883 /* Enter the pages */ 884 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) 885 moea_kenter(mmup, translations[i].om_va + off, 886 translations[i].om_pa + off); 887 } 888 889 /* 890 * Calculate the last available physical address. 891 */ 892 for (i = 0; phys_avail[i + 2] != 0; i += 2) 893 ; 894 Maxmem = powerpc_btop(phys_avail[i + 1]); 895 896 moea_cpu_bootstrap(mmup,0); 897 898 pmap_bootstrapped++; 899 900 /* 901 * Set the start and end of kva. 902 */ 903 virtual_avail = VM_MIN_KERNEL_ADDRESS; 904 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 905 906 /* 907 * Allocate a kernel stack with a guard page for thread0 and map it 908 * into the kernel page map. 909 */ 910 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 911 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 912 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 913 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 914 thread0.td_kstack = va; 915 thread0.td_kstack_pages = KSTACK_PAGES; 916 for (i = 0; i < KSTACK_PAGES; i++) { 917 moea_kenter(mmup, va, pa); 918 pa += PAGE_SIZE; 919 va += PAGE_SIZE; 920 } 921 922 /* 923 * Allocate virtual address space for the message buffer. 924 */ 925 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 926 msgbufp = (struct msgbuf *)virtual_avail; 927 va = virtual_avail; 928 virtual_avail += round_page(msgbufsize); 929 while (va < virtual_avail) { 930 moea_kenter(mmup, va, pa); 931 pa += PAGE_SIZE; 932 va += PAGE_SIZE; 933 } 934 935 /* 936 * Allocate virtual address space for the dynamic percpu area. 937 */ 938 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 939 dpcpu = (void *)virtual_avail; 940 va = virtual_avail; 941 virtual_avail += DPCPU_SIZE; 942 while (va < virtual_avail) { 943 moea_kenter(mmup, va, pa); 944 pa += PAGE_SIZE; 945 va += PAGE_SIZE; 946 } 947 dpcpu_init(dpcpu, 0); 948 } 949 950 /* 951 * Activate a user pmap. The pmap must be activated before it's address 952 * space can be accessed in any way. 953 */ 954 void 955 moea_activate(mmu_t mmu, struct thread *td) 956 { 957 pmap_t pm, pmr; 958 959 /* 960 * Load all the data we need up front to encourage the compiler to 961 * not issue any loads while we have interrupts disabled below. 962 */ 963 pm = &td->td_proc->p_vmspace->vm_pmap; 964 pmr = pm->pmap_phys; 965 966 sched_pin(); 967 CPU_OR(&pm->pm_active, PCPU_PTR(cpumask)); 968 sched_unpin(); 969 PCPU_SET(curpmap, pmr); 970 } 971 972 void 973 moea_deactivate(mmu_t mmu, struct thread *td) 974 { 975 pmap_t pm; 976 977 pm = &td->td_proc->p_vmspace->vm_pmap; 978 sched_pin(); 979 CPU_NAND(&pm->pm_active, PCPU_PTR(cpumask)); 980 sched_unpin(); 981 PCPU_SET(curpmap, NULL); 982 } 983 984 void 985 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 986 { 987 struct pvo_entry *pvo; 988 989 PMAP_LOCK(pm); 990 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 991 992 if (pvo != NULL) { 993 if (wired) { 994 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 995 pm->pm_stats.wired_count++; 996 pvo->pvo_vaddr |= PVO_WIRED; 997 } else { 998 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 999 pm->pm_stats.wired_count--; 1000 pvo->pvo_vaddr &= ~PVO_WIRED; 1001 } 1002 } 1003 PMAP_UNLOCK(pm); 1004 } 1005 1006 void 1007 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1008 { 1009 vm_offset_t dst; 1010 vm_offset_t src; 1011 1012 dst = VM_PAGE_TO_PHYS(mdst); 1013 src = VM_PAGE_TO_PHYS(msrc); 1014 1015 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1016 } 1017 1018 /* 1019 * Zero a page of physical memory by temporarily mapping it into the tlb. 1020 */ 1021 void 1022 moea_zero_page(mmu_t mmu, vm_page_t m) 1023 { 1024 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1025 void *va = (void *)pa; 1026 1027 bzero(va, PAGE_SIZE); 1028 } 1029 1030 void 1031 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1032 { 1033 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1034 void *va = (void *)(pa + off); 1035 1036 bzero(va, size); 1037 } 1038 1039 void 1040 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1041 { 1042 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1043 void *va = (void *)pa; 1044 1045 bzero(va, PAGE_SIZE); 1046 } 1047 1048 /* 1049 * Map the given physical page at the specified virtual address in the 1050 * target pmap with the protection requested. If specified the page 1051 * will be wired down. 1052 */ 1053 void 1054 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1055 boolean_t wired) 1056 { 1057 1058 vm_page_lock_queues(); 1059 PMAP_LOCK(pmap); 1060 moea_enter_locked(pmap, va, m, prot, wired); 1061 vm_page_unlock_queues(); 1062 PMAP_UNLOCK(pmap); 1063 } 1064 1065 /* 1066 * Map the given physical page at the specified virtual address in the 1067 * target pmap with the protection requested. If specified the page 1068 * will be wired down. 1069 * 1070 * The page queues and pmap must be locked. 1071 */ 1072 static void 1073 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1074 boolean_t wired) 1075 { 1076 struct pvo_head *pvo_head; 1077 uma_zone_t zone; 1078 vm_page_t pg; 1079 u_int pte_lo, pvo_flags, was_exec; 1080 int error; 1081 1082 if (!moea_initialized) { 1083 pvo_head = &moea_pvo_kunmanaged; 1084 zone = moea_upvo_zone; 1085 pvo_flags = 0; 1086 pg = NULL; 1087 was_exec = PTE_EXEC; 1088 } else { 1089 pvo_head = vm_page_to_pvoh(m); 1090 pg = m; 1091 zone = moea_mpvo_zone; 1092 pvo_flags = PVO_MANAGED; 1093 was_exec = 0; 1094 } 1095 if (pmap_bootstrapped) 1096 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1097 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1098 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1099 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1100 ("moea_enter_locked: page %p is not busy", m)); 1101 1102 /* XXX change the pvo head for fake pages */ 1103 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1104 pvo_flags &= ~PVO_MANAGED; 1105 pvo_head = &moea_pvo_kunmanaged; 1106 zone = moea_upvo_zone; 1107 } 1108 1109 /* 1110 * If this is a managed page, and it's the first reference to the page, 1111 * clear the execness of the page. Otherwise fetch the execness. 1112 */ 1113 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1114 if (LIST_EMPTY(pvo_head)) { 1115 moea_attr_clear(pg, PTE_EXEC); 1116 } else { 1117 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1118 } 1119 } 1120 1121 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1122 1123 if (prot & VM_PROT_WRITE) { 1124 pte_lo |= PTE_BW; 1125 if (pmap_bootstrapped && 1126 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1127 vm_page_flag_set(m, PG_WRITEABLE); 1128 } else 1129 pte_lo |= PTE_BR; 1130 1131 if (prot & VM_PROT_EXECUTE) 1132 pvo_flags |= PVO_EXECUTABLE; 1133 1134 if (wired) 1135 pvo_flags |= PVO_WIRED; 1136 1137 if ((m->flags & PG_FICTITIOUS) != 0) 1138 pvo_flags |= PVO_FAKE; 1139 1140 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1141 pte_lo, pvo_flags); 1142 1143 /* 1144 * Flush the real page from the instruction cache if this page is 1145 * mapped executable and cacheable and was not previously mapped (or 1146 * was not mapped executable). 1147 */ 1148 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1149 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1150 /* 1151 * Flush the real memory from the cache. 1152 */ 1153 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1154 if (pg != NULL) 1155 moea_attr_save(pg, PTE_EXEC); 1156 } 1157 1158 /* XXX syncicache always until problems are sorted */ 1159 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1160 } 1161 1162 /* 1163 * Maps a sequence of resident pages belonging to the same object. 1164 * The sequence begins with the given page m_start. This page is 1165 * mapped at the given virtual address start. Each subsequent page is 1166 * mapped at a virtual address that is offset from start by the same 1167 * amount as the page is offset from m_start within the object. The 1168 * last page in the sequence is the page with the largest offset from 1169 * m_start that can be mapped at a virtual address less than the given 1170 * virtual address end. Not every virtual page between start and end 1171 * is mapped; only those for which a resident page exists with the 1172 * corresponding offset from m_start are mapped. 1173 */ 1174 void 1175 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1176 vm_page_t m_start, vm_prot_t prot) 1177 { 1178 vm_page_t m; 1179 vm_pindex_t diff, psize; 1180 1181 psize = atop(end - start); 1182 m = m_start; 1183 vm_page_lock_queues(); 1184 PMAP_LOCK(pm); 1185 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1186 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1187 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1188 m = TAILQ_NEXT(m, listq); 1189 } 1190 vm_page_unlock_queues(); 1191 PMAP_UNLOCK(pm); 1192 } 1193 1194 void 1195 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1196 vm_prot_t prot) 1197 { 1198 1199 vm_page_lock_queues(); 1200 PMAP_LOCK(pm); 1201 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1202 FALSE); 1203 vm_page_unlock_queues(); 1204 PMAP_UNLOCK(pm); 1205 } 1206 1207 vm_paddr_t 1208 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1209 { 1210 struct pvo_entry *pvo; 1211 vm_paddr_t pa; 1212 1213 PMAP_LOCK(pm); 1214 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1215 if (pvo == NULL) 1216 pa = 0; 1217 else 1218 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1219 PMAP_UNLOCK(pm); 1220 return (pa); 1221 } 1222 1223 /* 1224 * Atomically extract and hold the physical page with the given 1225 * pmap and virtual address pair if that mapping permits the given 1226 * protection. 1227 */ 1228 vm_page_t 1229 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1230 { 1231 struct pvo_entry *pvo; 1232 vm_page_t m; 1233 vm_paddr_t pa; 1234 1235 m = NULL; 1236 pa = 0; 1237 PMAP_LOCK(pmap); 1238 retry: 1239 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1240 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1241 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1242 (prot & VM_PROT_WRITE) == 0)) { 1243 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1244 goto retry; 1245 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1246 vm_page_hold(m); 1247 } 1248 PA_UNLOCK_COND(pa); 1249 PMAP_UNLOCK(pmap); 1250 return (m); 1251 } 1252 1253 void 1254 moea_init(mmu_t mmu) 1255 { 1256 1257 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1258 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1259 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1260 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1261 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1262 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1263 moea_initialized = TRUE; 1264 } 1265 1266 boolean_t 1267 moea_is_referenced(mmu_t mmu, vm_page_t m) 1268 { 1269 1270 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1271 ("moea_is_referenced: page %p is not managed", m)); 1272 return (moea_query_bit(m, PTE_REF)); 1273 } 1274 1275 boolean_t 1276 moea_is_modified(mmu_t mmu, vm_page_t m) 1277 { 1278 1279 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1280 ("moea_is_modified: page %p is not managed", m)); 1281 1282 /* 1283 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1284 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1285 * is clear, no PTEs can have PTE_CHG set. 1286 */ 1287 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1288 if ((m->oflags & VPO_BUSY) == 0 && 1289 (m->flags & PG_WRITEABLE) == 0) 1290 return (FALSE); 1291 return (moea_query_bit(m, PTE_CHG)); 1292 } 1293 1294 boolean_t 1295 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1296 { 1297 struct pvo_entry *pvo; 1298 boolean_t rv; 1299 1300 PMAP_LOCK(pmap); 1301 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1302 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1303 PMAP_UNLOCK(pmap); 1304 return (rv); 1305 } 1306 1307 void 1308 moea_clear_reference(mmu_t mmu, vm_page_t m) 1309 { 1310 1311 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1312 ("moea_clear_reference: page %p is not managed", m)); 1313 moea_clear_bit(m, PTE_REF); 1314 } 1315 1316 void 1317 moea_clear_modify(mmu_t mmu, vm_page_t m) 1318 { 1319 1320 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1321 ("moea_clear_modify: page %p is not managed", m)); 1322 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1323 KASSERT((m->oflags & VPO_BUSY) == 0, 1324 ("moea_clear_modify: page %p is busy", m)); 1325 1326 /* 1327 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1328 * set. If the object containing the page is locked and the page is 1329 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1330 */ 1331 if ((m->flags & PG_WRITEABLE) == 0) 1332 return; 1333 moea_clear_bit(m, PTE_CHG); 1334 } 1335 1336 /* 1337 * Clear the write and modified bits in each of the given page's mappings. 1338 */ 1339 void 1340 moea_remove_write(mmu_t mmu, vm_page_t m) 1341 { 1342 struct pvo_entry *pvo; 1343 struct pte *pt; 1344 pmap_t pmap; 1345 u_int lo; 1346 1347 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1348 ("moea_remove_write: page %p is not managed", m)); 1349 1350 /* 1351 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1352 * another thread while the object is locked. Thus, if PG_WRITEABLE 1353 * is clear, no page table entries need updating. 1354 */ 1355 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1356 if ((m->oflags & VPO_BUSY) == 0 && 1357 (m->flags & PG_WRITEABLE) == 0) 1358 return; 1359 vm_page_lock_queues(); 1360 lo = moea_attr_fetch(m); 1361 powerpc_sync(); 1362 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1363 pmap = pvo->pvo_pmap; 1364 PMAP_LOCK(pmap); 1365 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1366 pt = moea_pvo_to_pte(pvo, -1); 1367 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1368 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1369 if (pt != NULL) { 1370 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1371 lo |= pvo->pvo_pte.pte.pte_lo; 1372 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1373 moea_pte_change(pt, &pvo->pvo_pte.pte, 1374 pvo->pvo_vaddr); 1375 mtx_unlock(&moea_table_mutex); 1376 } 1377 } 1378 PMAP_UNLOCK(pmap); 1379 } 1380 if ((lo & PTE_CHG) != 0) { 1381 moea_attr_clear(m, PTE_CHG); 1382 vm_page_dirty(m); 1383 } 1384 vm_page_flag_clear(m, PG_WRITEABLE); 1385 vm_page_unlock_queues(); 1386 } 1387 1388 /* 1389 * moea_ts_referenced: 1390 * 1391 * Return a count of reference bits for a page, clearing those bits. 1392 * It is not necessary for every reference bit to be cleared, but it 1393 * is necessary that 0 only be returned when there are truly no 1394 * reference bits set. 1395 * 1396 * XXX: The exact number of bits to check and clear is a matter that 1397 * should be tested and standardized at some point in the future for 1398 * optimal aging of shared pages. 1399 */ 1400 boolean_t 1401 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1402 { 1403 1404 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1405 ("moea_ts_referenced: page %p is not managed", m)); 1406 return (moea_clear_bit(m, PTE_REF)); 1407 } 1408 1409 /* 1410 * Modify the WIMG settings of all mappings for a page. 1411 */ 1412 void 1413 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1414 { 1415 struct pvo_entry *pvo; 1416 struct pvo_head *pvo_head; 1417 struct pte *pt; 1418 pmap_t pmap; 1419 u_int lo; 1420 1421 if (m->flags & PG_FICTITIOUS) { 1422 m->md.mdpg_cache_attrs = ma; 1423 return; 1424 } 1425 1426 vm_page_lock_queues(); 1427 pvo_head = vm_page_to_pvoh(m); 1428 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1429 1430 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1431 pmap = pvo->pvo_pmap; 1432 PMAP_LOCK(pmap); 1433 pt = moea_pvo_to_pte(pvo, -1); 1434 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1435 pvo->pvo_pte.pte.pte_lo |= lo; 1436 if (pt != NULL) { 1437 moea_pte_change(pt, &pvo->pvo_pte.pte, 1438 pvo->pvo_vaddr); 1439 if (pvo->pvo_pmap == kernel_pmap) 1440 isync(); 1441 } 1442 mtx_unlock(&moea_table_mutex); 1443 PMAP_UNLOCK(pmap); 1444 } 1445 m->md.mdpg_cache_attrs = ma; 1446 vm_page_unlock_queues(); 1447 } 1448 1449 /* 1450 * Map a wired page into kernel virtual address space. 1451 */ 1452 void 1453 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1454 { 1455 1456 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1457 } 1458 1459 void 1460 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1461 { 1462 u_int pte_lo; 1463 int error; 1464 1465 #if 0 1466 if (va < VM_MIN_KERNEL_ADDRESS) 1467 panic("moea_kenter: attempt to enter non-kernel address %#x", 1468 va); 1469 #endif 1470 1471 pte_lo = moea_calc_wimg(pa, ma); 1472 1473 PMAP_LOCK(kernel_pmap); 1474 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1475 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1476 1477 if (error != 0 && error != ENOENT) 1478 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1479 pa, error); 1480 1481 /* 1482 * Flush the real memory from the instruction cache. 1483 */ 1484 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1485 moea_syncicache(pa, PAGE_SIZE); 1486 } 1487 PMAP_UNLOCK(kernel_pmap); 1488 } 1489 1490 /* 1491 * Extract the physical page address associated with the given kernel virtual 1492 * address. 1493 */ 1494 vm_offset_t 1495 moea_kextract(mmu_t mmu, vm_offset_t va) 1496 { 1497 struct pvo_entry *pvo; 1498 vm_paddr_t pa; 1499 1500 /* 1501 * Allow direct mappings on 32-bit OEA 1502 */ 1503 if (va < VM_MIN_KERNEL_ADDRESS) { 1504 return (va); 1505 } 1506 1507 PMAP_LOCK(kernel_pmap); 1508 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1509 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1510 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1511 PMAP_UNLOCK(kernel_pmap); 1512 return (pa); 1513 } 1514 1515 /* 1516 * Remove a wired page from kernel virtual address space. 1517 */ 1518 void 1519 moea_kremove(mmu_t mmu, vm_offset_t va) 1520 { 1521 1522 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1523 } 1524 1525 /* 1526 * Map a range of physical addresses into kernel virtual address space. 1527 * 1528 * The value passed in *virt is a suggested virtual address for the mapping. 1529 * Architectures which can support a direct-mapped physical to virtual region 1530 * can return the appropriate address within that region, leaving '*virt' 1531 * unchanged. We cannot and therefore do not; *virt is updated with the 1532 * first usable address after the mapped region. 1533 */ 1534 vm_offset_t 1535 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1536 vm_offset_t pa_end, int prot) 1537 { 1538 vm_offset_t sva, va; 1539 1540 sva = *virt; 1541 va = sva; 1542 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1543 moea_kenter(mmu, va, pa_start); 1544 *virt = va; 1545 return (sva); 1546 } 1547 1548 /* 1549 * Returns true if the pmap's pv is one of the first 1550 * 16 pvs linked to from this page. This count may 1551 * be changed upwards or downwards in the future; it 1552 * is only necessary that true be returned for a small 1553 * subset of pmaps for proper page aging. 1554 */ 1555 boolean_t 1556 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1557 { 1558 int loops; 1559 struct pvo_entry *pvo; 1560 boolean_t rv; 1561 1562 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1563 ("moea_page_exists_quick: page %p is not managed", m)); 1564 loops = 0; 1565 rv = FALSE; 1566 vm_page_lock_queues(); 1567 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1568 if (pvo->pvo_pmap == pmap) { 1569 rv = TRUE; 1570 break; 1571 } 1572 if (++loops >= 16) 1573 break; 1574 } 1575 vm_page_unlock_queues(); 1576 return (rv); 1577 } 1578 1579 /* 1580 * Return the number of managed mappings to the given physical page 1581 * that are wired. 1582 */ 1583 int 1584 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1585 { 1586 struct pvo_entry *pvo; 1587 int count; 1588 1589 count = 0; 1590 if ((m->flags & PG_FICTITIOUS) != 0) 1591 return (count); 1592 vm_page_lock_queues(); 1593 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1594 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1595 count++; 1596 vm_page_unlock_queues(); 1597 return (count); 1598 } 1599 1600 static u_int moea_vsidcontext; 1601 1602 void 1603 moea_pinit(mmu_t mmu, pmap_t pmap) 1604 { 1605 int i, mask; 1606 u_int entropy; 1607 1608 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1609 PMAP_LOCK_INIT(pmap); 1610 1611 entropy = 0; 1612 __asm __volatile("mftb %0" : "=r"(entropy)); 1613 1614 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1615 == NULL) { 1616 pmap->pmap_phys = pmap; 1617 } 1618 1619 1620 mtx_lock(&moea_vsid_mutex); 1621 /* 1622 * Allocate some segment registers for this pmap. 1623 */ 1624 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1625 u_int hash, n; 1626 1627 /* 1628 * Create a new value by mutiplying by a prime and adding in 1629 * entropy from the timebase register. This is to make the 1630 * VSID more random so that the PT hash function collides 1631 * less often. (Note that the prime casues gcc to do shifts 1632 * instead of a multiply.) 1633 */ 1634 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1635 hash = moea_vsidcontext & (NPMAPS - 1); 1636 if (hash == 0) /* 0 is special, avoid it */ 1637 continue; 1638 n = hash >> 5; 1639 mask = 1 << (hash & (VSID_NBPW - 1)); 1640 hash = (moea_vsidcontext & 0xfffff); 1641 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1642 /* anything free in this bucket? */ 1643 if (moea_vsid_bitmap[n] == 0xffffffff) { 1644 entropy = (moea_vsidcontext >> 20); 1645 continue; 1646 } 1647 i = ffs(~moea_vsid_bitmap[n]) - 1; 1648 mask = 1 << i; 1649 hash &= 0xfffff & ~(VSID_NBPW - 1); 1650 hash |= i; 1651 } 1652 moea_vsid_bitmap[n] |= mask; 1653 for (i = 0; i < 16; i++) 1654 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1655 mtx_unlock(&moea_vsid_mutex); 1656 return; 1657 } 1658 1659 mtx_unlock(&moea_vsid_mutex); 1660 panic("moea_pinit: out of segments"); 1661 } 1662 1663 /* 1664 * Initialize the pmap associated with process 0. 1665 */ 1666 void 1667 moea_pinit0(mmu_t mmu, pmap_t pm) 1668 { 1669 1670 moea_pinit(mmu, pm); 1671 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1672 } 1673 1674 /* 1675 * Set the physical protection on the specified range of this map as requested. 1676 */ 1677 void 1678 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1679 vm_prot_t prot) 1680 { 1681 struct pvo_entry *pvo; 1682 struct pte *pt; 1683 int pteidx; 1684 1685 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1686 ("moea_protect: non current pmap")); 1687 1688 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1689 moea_remove(mmu, pm, sva, eva); 1690 return; 1691 } 1692 1693 vm_page_lock_queues(); 1694 PMAP_LOCK(pm); 1695 for (; sva < eva; sva += PAGE_SIZE) { 1696 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1697 if (pvo == NULL) 1698 continue; 1699 1700 if ((prot & VM_PROT_EXECUTE) == 0) 1701 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1702 1703 /* 1704 * Grab the PTE pointer before we diddle with the cached PTE 1705 * copy. 1706 */ 1707 pt = moea_pvo_to_pte(pvo, pteidx); 1708 /* 1709 * Change the protection of the page. 1710 */ 1711 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1712 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1713 1714 /* 1715 * If the PVO is in the page table, update that pte as well. 1716 */ 1717 if (pt != NULL) { 1718 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1719 mtx_unlock(&moea_table_mutex); 1720 } 1721 } 1722 vm_page_unlock_queues(); 1723 PMAP_UNLOCK(pm); 1724 } 1725 1726 /* 1727 * Map a list of wired pages into kernel virtual address space. This is 1728 * intended for temporary mappings which do not need page modification or 1729 * references recorded. Existing mappings in the region are overwritten. 1730 */ 1731 void 1732 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1733 { 1734 vm_offset_t va; 1735 1736 va = sva; 1737 while (count-- > 0) { 1738 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1739 va += PAGE_SIZE; 1740 m++; 1741 } 1742 } 1743 1744 /* 1745 * Remove page mappings from kernel virtual address space. Intended for 1746 * temporary mappings entered by moea_qenter. 1747 */ 1748 void 1749 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1750 { 1751 vm_offset_t va; 1752 1753 va = sva; 1754 while (count-- > 0) { 1755 moea_kremove(mmu, va); 1756 va += PAGE_SIZE; 1757 } 1758 } 1759 1760 void 1761 moea_release(mmu_t mmu, pmap_t pmap) 1762 { 1763 int idx, mask; 1764 1765 /* 1766 * Free segment register's VSID 1767 */ 1768 if (pmap->pm_sr[0] == 0) 1769 panic("moea_release"); 1770 1771 mtx_lock(&moea_vsid_mutex); 1772 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1773 mask = 1 << (idx % VSID_NBPW); 1774 idx /= VSID_NBPW; 1775 moea_vsid_bitmap[idx] &= ~mask; 1776 mtx_unlock(&moea_vsid_mutex); 1777 PMAP_LOCK_DESTROY(pmap); 1778 } 1779 1780 /* 1781 * Remove the given range of addresses from the specified map. 1782 */ 1783 void 1784 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1785 { 1786 struct pvo_entry *pvo; 1787 int pteidx; 1788 1789 vm_page_lock_queues(); 1790 PMAP_LOCK(pm); 1791 for (; sva < eva; sva += PAGE_SIZE) { 1792 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1793 if (pvo != NULL) { 1794 moea_pvo_remove(pvo, pteidx); 1795 } 1796 } 1797 PMAP_UNLOCK(pm); 1798 vm_page_unlock_queues(); 1799 } 1800 1801 /* 1802 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1803 * will reflect changes in pte's back to the vm_page. 1804 */ 1805 void 1806 moea_remove_all(mmu_t mmu, vm_page_t m) 1807 { 1808 struct pvo_head *pvo_head; 1809 struct pvo_entry *pvo, *next_pvo; 1810 pmap_t pmap; 1811 1812 vm_page_lock_queues(); 1813 pvo_head = vm_page_to_pvoh(m); 1814 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1815 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1816 1817 pmap = pvo->pvo_pmap; 1818 PMAP_LOCK(pmap); 1819 moea_pvo_remove(pvo, -1); 1820 PMAP_UNLOCK(pmap); 1821 } 1822 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1823 moea_attr_clear(m, PTE_CHG); 1824 vm_page_dirty(m); 1825 } 1826 vm_page_flag_clear(m, PG_WRITEABLE); 1827 vm_page_unlock_queues(); 1828 } 1829 1830 /* 1831 * Allocate a physical page of memory directly from the phys_avail map. 1832 * Can only be called from moea_bootstrap before avail start and end are 1833 * calculated. 1834 */ 1835 static vm_offset_t 1836 moea_bootstrap_alloc(vm_size_t size, u_int align) 1837 { 1838 vm_offset_t s, e; 1839 int i, j; 1840 1841 size = round_page(size); 1842 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1843 if (align != 0) 1844 s = (phys_avail[i] + align - 1) & ~(align - 1); 1845 else 1846 s = phys_avail[i]; 1847 e = s + size; 1848 1849 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1850 continue; 1851 1852 if (s == phys_avail[i]) { 1853 phys_avail[i] += size; 1854 } else if (e == phys_avail[i + 1]) { 1855 phys_avail[i + 1] -= size; 1856 } else { 1857 for (j = phys_avail_count * 2; j > i; j -= 2) { 1858 phys_avail[j] = phys_avail[j - 2]; 1859 phys_avail[j + 1] = phys_avail[j - 1]; 1860 } 1861 1862 phys_avail[i + 3] = phys_avail[i + 1]; 1863 phys_avail[i + 1] = s; 1864 phys_avail[i + 2] = e; 1865 phys_avail_count++; 1866 } 1867 1868 return (s); 1869 } 1870 panic("moea_bootstrap_alloc: could not allocate memory"); 1871 } 1872 1873 static void 1874 moea_syncicache(vm_offset_t pa, vm_size_t len) 1875 { 1876 __syncicache((void *)pa, len); 1877 } 1878 1879 static int 1880 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1881 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1882 { 1883 struct pvo_entry *pvo; 1884 u_int sr; 1885 int first; 1886 u_int ptegidx; 1887 int i; 1888 int bootstrap; 1889 1890 moea_pvo_enter_calls++; 1891 first = 0; 1892 bootstrap = 0; 1893 1894 /* 1895 * Compute the PTE Group index. 1896 */ 1897 va &= ~ADDR_POFF; 1898 sr = va_to_sr(pm->pm_sr, va); 1899 ptegidx = va_to_pteg(sr, va); 1900 1901 /* 1902 * Remove any existing mapping for this page. Reuse the pvo entry if 1903 * there is a mapping. 1904 */ 1905 mtx_lock(&moea_table_mutex); 1906 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1907 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1908 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1909 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1910 (pte_lo & PTE_PP)) { 1911 mtx_unlock(&moea_table_mutex); 1912 return (0); 1913 } 1914 moea_pvo_remove(pvo, -1); 1915 break; 1916 } 1917 } 1918 1919 /* 1920 * If we aren't overwriting a mapping, try to allocate. 1921 */ 1922 if (moea_initialized) { 1923 pvo = uma_zalloc(zone, M_NOWAIT); 1924 } else { 1925 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1926 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1927 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1928 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1929 } 1930 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1931 moea_bpvo_pool_index++; 1932 bootstrap = 1; 1933 } 1934 1935 if (pvo == NULL) { 1936 mtx_unlock(&moea_table_mutex); 1937 return (ENOMEM); 1938 } 1939 1940 moea_pvo_entries++; 1941 pvo->pvo_vaddr = va; 1942 pvo->pvo_pmap = pm; 1943 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1944 pvo->pvo_vaddr &= ~ADDR_POFF; 1945 if (flags & VM_PROT_EXECUTE) 1946 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1947 if (flags & PVO_WIRED) 1948 pvo->pvo_vaddr |= PVO_WIRED; 1949 if (pvo_head != &moea_pvo_kunmanaged) 1950 pvo->pvo_vaddr |= PVO_MANAGED; 1951 if (bootstrap) 1952 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1953 if (flags & PVO_FAKE) 1954 pvo->pvo_vaddr |= PVO_FAKE; 1955 1956 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1957 1958 /* 1959 * Remember if the list was empty and therefore will be the first 1960 * item. 1961 */ 1962 if (LIST_FIRST(pvo_head) == NULL) 1963 first = 1; 1964 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1965 1966 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1967 pm->pm_stats.wired_count++; 1968 pm->pm_stats.resident_count++; 1969 1970 /* 1971 * We hope this succeeds but it isn't required. 1972 */ 1973 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1974 if (i >= 0) { 1975 PVO_PTEGIDX_SET(pvo, i); 1976 } else { 1977 panic("moea_pvo_enter: overflow"); 1978 moea_pte_overflow++; 1979 } 1980 mtx_unlock(&moea_table_mutex); 1981 1982 return (first ? ENOENT : 0); 1983 } 1984 1985 static void 1986 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1987 { 1988 struct pte *pt; 1989 1990 /* 1991 * If there is an active pte entry, we need to deactivate it (and 1992 * save the ref & cfg bits). 1993 */ 1994 pt = moea_pvo_to_pte(pvo, pteidx); 1995 if (pt != NULL) { 1996 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1997 mtx_unlock(&moea_table_mutex); 1998 PVO_PTEGIDX_CLR(pvo); 1999 } else { 2000 moea_pte_overflow--; 2001 } 2002 2003 /* 2004 * Update our statistics. 2005 */ 2006 pvo->pvo_pmap->pm_stats.resident_count--; 2007 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2008 pvo->pvo_pmap->pm_stats.wired_count--; 2009 2010 /* 2011 * Save the REF/CHG bits into their cache if the page is managed. 2012 */ 2013 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2014 struct vm_page *pg; 2015 2016 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2017 if (pg != NULL) { 2018 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2019 (PTE_REF | PTE_CHG)); 2020 } 2021 } 2022 2023 /* 2024 * Remove this PVO from the PV list. 2025 */ 2026 LIST_REMOVE(pvo, pvo_vlink); 2027 2028 /* 2029 * Remove this from the overflow list and return it to the pool 2030 * if we aren't going to reuse it. 2031 */ 2032 LIST_REMOVE(pvo, pvo_olink); 2033 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2034 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2035 moea_upvo_zone, pvo); 2036 moea_pvo_entries--; 2037 moea_pvo_remove_calls++; 2038 } 2039 2040 static __inline int 2041 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2042 { 2043 int pteidx; 2044 2045 /* 2046 * We can find the actual pte entry without searching by grabbing 2047 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2048 * noticing the HID bit. 2049 */ 2050 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2051 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2052 pteidx ^= moea_pteg_mask * 8; 2053 2054 return (pteidx); 2055 } 2056 2057 static struct pvo_entry * 2058 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2059 { 2060 struct pvo_entry *pvo; 2061 int ptegidx; 2062 u_int sr; 2063 2064 va &= ~ADDR_POFF; 2065 sr = va_to_sr(pm->pm_sr, va); 2066 ptegidx = va_to_pteg(sr, va); 2067 2068 mtx_lock(&moea_table_mutex); 2069 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2070 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2071 if (pteidx_p) 2072 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2073 break; 2074 } 2075 } 2076 mtx_unlock(&moea_table_mutex); 2077 2078 return (pvo); 2079 } 2080 2081 static struct pte * 2082 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2083 { 2084 struct pte *pt; 2085 2086 /* 2087 * If we haven't been supplied the ptegidx, calculate it. 2088 */ 2089 if (pteidx == -1) { 2090 int ptegidx; 2091 u_int sr; 2092 2093 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2094 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2095 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2096 } 2097 2098 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2099 mtx_lock(&moea_table_mutex); 2100 2101 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2102 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2103 "valid pte index", pvo); 2104 } 2105 2106 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2107 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2108 "pvo but no valid pte", pvo); 2109 } 2110 2111 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2112 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2113 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2114 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2115 } 2116 2117 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2118 != 0) { 2119 panic("moea_pvo_to_pte: pvo %p pte does not match " 2120 "pte %p in moea_pteg_table", pvo, pt); 2121 } 2122 2123 mtx_assert(&moea_table_mutex, MA_OWNED); 2124 return (pt); 2125 } 2126 2127 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2128 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2129 "moea_pteg_table but valid in pvo", pvo, pt); 2130 } 2131 2132 mtx_unlock(&moea_table_mutex); 2133 return (NULL); 2134 } 2135 2136 /* 2137 * XXX: THIS STUFF SHOULD BE IN pte.c? 2138 */ 2139 int 2140 moea_pte_spill(vm_offset_t addr) 2141 { 2142 struct pvo_entry *source_pvo, *victim_pvo; 2143 struct pvo_entry *pvo; 2144 int ptegidx, i, j; 2145 u_int sr; 2146 struct pteg *pteg; 2147 struct pte *pt; 2148 2149 moea_pte_spills++; 2150 2151 sr = mfsrin(addr); 2152 ptegidx = va_to_pteg(sr, addr); 2153 2154 /* 2155 * Have to substitute some entry. Use the primary hash for this. 2156 * Use low bits of timebase as random generator. 2157 */ 2158 pteg = &moea_pteg_table[ptegidx]; 2159 mtx_lock(&moea_table_mutex); 2160 __asm __volatile("mftb %0" : "=r"(i)); 2161 i &= 7; 2162 pt = &pteg->pt[i]; 2163 2164 source_pvo = NULL; 2165 victim_pvo = NULL; 2166 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2167 /* 2168 * We need to find a pvo entry for this address. 2169 */ 2170 if (source_pvo == NULL && 2171 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2172 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2173 /* 2174 * Now found an entry to be spilled into the pteg. 2175 * The PTE is now valid, so we know it's active. 2176 */ 2177 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2178 2179 if (j >= 0) { 2180 PVO_PTEGIDX_SET(pvo, j); 2181 moea_pte_overflow--; 2182 mtx_unlock(&moea_table_mutex); 2183 return (1); 2184 } 2185 2186 source_pvo = pvo; 2187 2188 if (victim_pvo != NULL) 2189 break; 2190 } 2191 2192 /* 2193 * We also need the pvo entry of the victim we are replacing 2194 * so save the R & C bits of the PTE. 2195 */ 2196 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2197 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2198 victim_pvo = pvo; 2199 if (source_pvo != NULL) 2200 break; 2201 } 2202 } 2203 2204 if (source_pvo == NULL) { 2205 mtx_unlock(&moea_table_mutex); 2206 return (0); 2207 } 2208 2209 if (victim_pvo == NULL) { 2210 if ((pt->pte_hi & PTE_HID) == 0) 2211 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2212 "entry", pt); 2213 2214 /* 2215 * If this is a secondary PTE, we need to search it's primary 2216 * pvo bucket for the matching PVO. 2217 */ 2218 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2219 pvo_olink) { 2220 /* 2221 * We also need the pvo entry of the victim we are 2222 * replacing so save the R & C bits of the PTE. 2223 */ 2224 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2225 victim_pvo = pvo; 2226 break; 2227 } 2228 } 2229 2230 if (victim_pvo == NULL) 2231 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2232 "entry", pt); 2233 } 2234 2235 /* 2236 * We are invalidating the TLB entry for the EA we are replacing even 2237 * though it's valid. If we don't, we lose any ref/chg bit changes 2238 * contained in the TLB entry. 2239 */ 2240 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2241 2242 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2243 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2244 2245 PVO_PTEGIDX_CLR(victim_pvo); 2246 PVO_PTEGIDX_SET(source_pvo, i); 2247 moea_pte_replacements++; 2248 2249 mtx_unlock(&moea_table_mutex); 2250 return (1); 2251 } 2252 2253 static int 2254 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2255 { 2256 struct pte *pt; 2257 int i; 2258 2259 mtx_assert(&moea_table_mutex, MA_OWNED); 2260 2261 /* 2262 * First try primary hash. 2263 */ 2264 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2265 if ((pt->pte_hi & PTE_VALID) == 0) { 2266 pvo_pt->pte_hi &= ~PTE_HID; 2267 moea_pte_set(pt, pvo_pt); 2268 return (i); 2269 } 2270 } 2271 2272 /* 2273 * Now try secondary hash. 2274 */ 2275 ptegidx ^= moea_pteg_mask; 2276 2277 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2278 if ((pt->pte_hi & PTE_VALID) == 0) { 2279 pvo_pt->pte_hi |= PTE_HID; 2280 moea_pte_set(pt, pvo_pt); 2281 return (i); 2282 } 2283 } 2284 2285 panic("moea_pte_insert: overflow"); 2286 return (-1); 2287 } 2288 2289 static boolean_t 2290 moea_query_bit(vm_page_t m, int ptebit) 2291 { 2292 struct pvo_entry *pvo; 2293 struct pte *pt; 2294 2295 if (moea_attr_fetch(m) & ptebit) 2296 return (TRUE); 2297 2298 vm_page_lock_queues(); 2299 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2300 2301 /* 2302 * See if we saved the bit off. If so, cache it and return 2303 * success. 2304 */ 2305 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2306 moea_attr_save(m, ptebit); 2307 vm_page_unlock_queues(); 2308 return (TRUE); 2309 } 2310 } 2311 2312 /* 2313 * No luck, now go through the hard part of looking at the PTEs 2314 * themselves. Sync so that any pending REF/CHG bits are flushed to 2315 * the PTEs. 2316 */ 2317 powerpc_sync(); 2318 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2319 2320 /* 2321 * See if this pvo has a valid PTE. if so, fetch the 2322 * REF/CHG bits from the valid PTE. If the appropriate 2323 * ptebit is set, cache it and return success. 2324 */ 2325 pt = moea_pvo_to_pte(pvo, -1); 2326 if (pt != NULL) { 2327 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2328 mtx_unlock(&moea_table_mutex); 2329 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2330 moea_attr_save(m, ptebit); 2331 vm_page_unlock_queues(); 2332 return (TRUE); 2333 } 2334 } 2335 } 2336 2337 vm_page_unlock_queues(); 2338 return (FALSE); 2339 } 2340 2341 static u_int 2342 moea_clear_bit(vm_page_t m, int ptebit) 2343 { 2344 u_int count; 2345 struct pvo_entry *pvo; 2346 struct pte *pt; 2347 2348 vm_page_lock_queues(); 2349 2350 /* 2351 * Clear the cached value. 2352 */ 2353 moea_attr_clear(m, ptebit); 2354 2355 /* 2356 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2357 * we can reset the right ones). note that since the pvo entries and 2358 * list heads are accessed via BAT0 and are never placed in the page 2359 * table, we don't have to worry about further accesses setting the 2360 * REF/CHG bits. 2361 */ 2362 powerpc_sync(); 2363 2364 /* 2365 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2366 * valid pte clear the ptebit from the valid pte. 2367 */ 2368 count = 0; 2369 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2370 pt = moea_pvo_to_pte(pvo, -1); 2371 if (pt != NULL) { 2372 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2373 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2374 count++; 2375 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2376 } 2377 mtx_unlock(&moea_table_mutex); 2378 } 2379 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2380 } 2381 2382 vm_page_unlock_queues(); 2383 return (count); 2384 } 2385 2386 /* 2387 * Return true if the physical range is encompassed by the battable[idx] 2388 */ 2389 static int 2390 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2391 { 2392 u_int prot; 2393 u_int32_t start; 2394 u_int32_t end; 2395 u_int32_t bat_ble; 2396 2397 /* 2398 * Return immediately if not a valid mapping 2399 */ 2400 if (!(battable[idx].batu & BAT_Vs)) 2401 return (EINVAL); 2402 2403 /* 2404 * The BAT entry must be cache-inhibited, guarded, and r/w 2405 * so it can function as an i/o page 2406 */ 2407 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2408 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2409 return (EPERM); 2410 2411 /* 2412 * The address should be within the BAT range. Assume that the 2413 * start address in the BAT has the correct alignment (thus 2414 * not requiring masking) 2415 */ 2416 start = battable[idx].batl & BAT_PBS; 2417 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2418 end = start | (bat_ble << 15) | 0x7fff; 2419 2420 if ((pa < start) || ((pa + size) > end)) 2421 return (ERANGE); 2422 2423 return (0); 2424 } 2425 2426 boolean_t 2427 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2428 { 2429 int i; 2430 2431 /* 2432 * This currently does not work for entries that 2433 * overlap 256M BAT segments. 2434 */ 2435 2436 for(i = 0; i < 16; i++) 2437 if (moea_bat_mapped(i, pa, size) == 0) 2438 return (0); 2439 2440 return (EFAULT); 2441 } 2442 2443 /* 2444 * Map a set of physical memory pages into the kernel virtual 2445 * address space. Return a pointer to where it is mapped. This 2446 * routine is intended to be used for mapping device memory, 2447 * NOT real memory. 2448 */ 2449 void * 2450 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2451 { 2452 2453 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2454 } 2455 2456 void * 2457 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2458 { 2459 vm_offset_t va, tmpva, ppa, offset; 2460 int i; 2461 2462 ppa = trunc_page(pa); 2463 offset = pa & PAGE_MASK; 2464 size = roundup(offset + size, PAGE_SIZE); 2465 2466 /* 2467 * If the physical address lies within a valid BAT table entry, 2468 * return the 1:1 mapping. This currently doesn't work 2469 * for regions that overlap 256M BAT segments. 2470 */ 2471 for (i = 0; i < 16; i++) { 2472 if (moea_bat_mapped(i, pa, size) == 0) 2473 return ((void *) pa); 2474 } 2475 2476 va = kmem_alloc_nofault(kernel_map, size); 2477 if (!va) 2478 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2479 2480 for (tmpva = va; size > 0;) { 2481 moea_kenter_attr(mmu, tmpva, ppa, ma); 2482 tlbie(tmpva); 2483 size -= PAGE_SIZE; 2484 tmpva += PAGE_SIZE; 2485 ppa += PAGE_SIZE; 2486 } 2487 2488 return ((void *)(va + offset)); 2489 } 2490 2491 void 2492 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2493 { 2494 vm_offset_t base, offset; 2495 2496 /* 2497 * If this is outside kernel virtual space, then it's a 2498 * battable entry and doesn't require unmapping 2499 */ 2500 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2501 base = trunc_page(va); 2502 offset = va & PAGE_MASK; 2503 size = roundup(offset + size, PAGE_SIZE); 2504 kmem_free(kernel_map, base, size); 2505 } 2506 } 2507 2508 static void 2509 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2510 { 2511 struct pvo_entry *pvo; 2512 vm_offset_t lim; 2513 vm_paddr_t pa; 2514 vm_size_t len; 2515 2516 PMAP_LOCK(pm); 2517 while (sz > 0) { 2518 lim = round_page(va); 2519 len = MIN(lim - va, sz); 2520 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2521 if (pvo != NULL) { 2522 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2523 (va & ADDR_POFF); 2524 moea_syncicache(pa, len); 2525 } 2526 va += len; 2527 sz -= len; 2528 } 2529 PMAP_UNLOCK(pm); 2530 } 2531