1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/queue.h> 122 #include <sys/cpuset.h> 123 #include <sys/ktr.h> 124 #include <sys/lock.h> 125 #include <sys/msgbuf.h> 126 #include <sys/mutex.h> 127 #include <sys/proc.h> 128 #include <sys/rwlock.h> 129 #include <sys/sched.h> 130 #include <sys/sysctl.h> 131 #include <sys/systm.h> 132 #include <sys/vmmeter.h> 133 134 #include <dev/ofw/openfirm.h> 135 136 #include <vm/vm.h> 137 #include <vm/vm_param.h> 138 #include <vm/vm_kern.h> 139 #include <vm/vm_page.h> 140 #include <vm/vm_map.h> 141 #include <vm/vm_object.h> 142 #include <vm/vm_extern.h> 143 #include <vm/vm_pageout.h> 144 #include <vm/vm_pager.h> 145 #include <vm/uma.h> 146 147 #include <machine/cpu.h> 148 #include <machine/platform.h> 149 #include <machine/bat.h> 150 #include <machine/frame.h> 151 #include <machine/md_var.h> 152 #include <machine/psl.h> 153 #include <machine/pte.h> 154 #include <machine/smp.h> 155 #include <machine/sr.h> 156 #include <machine/mmuvar.h> 157 #include <machine/trap_aim.h> 158 159 #include "mmu_if.h" 160 161 #define MOEA_DEBUG 162 163 #define TODO panic("%s: not implemented", __func__); 164 165 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 166 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 167 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 168 169 struct ofw_map { 170 vm_offset_t om_va; 171 vm_size_t om_len; 172 vm_offset_t om_pa; 173 u_int om_mode; 174 }; 175 176 /* 177 * Map of physical memory regions. 178 */ 179 static struct mem_region *regions; 180 static struct mem_region *pregions; 181 static u_int phys_avail_count; 182 static int regions_sz, pregions_sz; 183 static struct ofw_map *translations; 184 185 /* 186 * Lock for the pteg and pvo tables. 187 */ 188 struct mtx moea_table_mutex; 189 struct mtx moea_vsid_mutex; 190 191 /* tlbie instruction synchronization */ 192 static struct mtx tlbie_mtx; 193 194 /* 195 * PTEG data. 196 */ 197 static struct pteg *moea_pteg_table; 198 u_int moea_pteg_count; 199 u_int moea_pteg_mask; 200 201 /* 202 * PVO data. 203 */ 204 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 205 struct pvo_head moea_pvo_kunmanaged = 206 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 207 208 /* 209 * Isolate the global pv list lock from data and other locks to prevent false 210 * sharing within the cache. 211 */ 212 static struct { 213 struct rwlock lock; 214 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)]; 215 } pvh_global __aligned(CACHE_LINE_SIZE); 216 217 #define pvh_global_lock pvh_global.lock 218 219 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 220 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 221 222 #define BPVO_POOL_SIZE 32768 223 static struct pvo_entry *moea_bpvo_pool; 224 static int moea_bpvo_pool_index = 0; 225 226 #define VSID_NBPW (sizeof(u_int32_t) * 8) 227 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 228 229 static boolean_t moea_initialized = FALSE; 230 231 /* 232 * Statistics. 233 */ 234 u_int moea_pte_valid = 0; 235 u_int moea_pte_overflow = 0; 236 u_int moea_pte_replacements = 0; 237 u_int moea_pvo_entries = 0; 238 u_int moea_pvo_enter_calls = 0; 239 u_int moea_pvo_remove_calls = 0; 240 u_int moea_pte_spills = 0; 241 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 242 0, ""); 243 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 244 &moea_pte_overflow, 0, ""); 245 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 246 &moea_pte_replacements, 0, ""); 247 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 248 0, ""); 249 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 250 &moea_pvo_enter_calls, 0, ""); 251 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 252 &moea_pvo_remove_calls, 0, ""); 253 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 254 &moea_pte_spills, 0, ""); 255 256 /* 257 * Allocate physical memory for use in moea_bootstrap. 258 */ 259 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 260 261 /* 262 * PTE calls. 263 */ 264 static int moea_pte_insert(u_int, struct pte *); 265 266 /* 267 * PVO calls. 268 */ 269 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 270 vm_offset_t, vm_offset_t, u_int, int); 271 static void moea_pvo_remove(struct pvo_entry *, int); 272 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 273 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 274 275 /* 276 * Utility routines. 277 */ 278 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 279 vm_prot_t, boolean_t); 280 static void moea_syncicache(vm_offset_t, vm_size_t); 281 static boolean_t moea_query_bit(vm_page_t, int); 282 static u_int moea_clear_bit(vm_page_t, int); 283 static void moea_kremove(mmu_t, vm_offset_t); 284 int moea_pte_spill(vm_offset_t); 285 286 /* 287 * Kernel MMU interface 288 */ 289 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 290 void moea_clear_modify(mmu_t, vm_page_t); 291 void moea_clear_reference(mmu_t, vm_page_t); 292 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 293 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 294 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 295 vm_prot_t); 296 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 297 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 298 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 299 void moea_init(mmu_t); 300 boolean_t moea_is_modified(mmu_t, vm_page_t); 301 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 302 boolean_t moea_is_referenced(mmu_t, vm_page_t); 303 int moea_ts_referenced(mmu_t, vm_page_t); 304 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 305 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 306 int moea_page_wired_mappings(mmu_t, vm_page_t); 307 void moea_pinit(mmu_t, pmap_t); 308 void moea_pinit0(mmu_t, pmap_t); 309 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 310 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 311 void moea_qremove(mmu_t, vm_offset_t, int); 312 void moea_release(mmu_t, pmap_t); 313 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 314 void moea_remove_all(mmu_t, vm_page_t); 315 void moea_remove_write(mmu_t, vm_page_t); 316 void moea_zero_page(mmu_t, vm_page_t); 317 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 318 void moea_zero_page_idle(mmu_t, vm_page_t); 319 void moea_activate(mmu_t, struct thread *); 320 void moea_deactivate(mmu_t, struct thread *); 321 void moea_cpu_bootstrap(mmu_t, int); 322 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 323 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 324 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 325 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 326 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 327 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 328 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 329 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 330 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 331 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 332 333 static mmu_method_t moea_methods[] = { 334 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 335 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 336 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 337 MMUMETHOD(mmu_copy_page, moea_copy_page), 338 MMUMETHOD(mmu_enter, moea_enter), 339 MMUMETHOD(mmu_enter_object, moea_enter_object), 340 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 341 MMUMETHOD(mmu_extract, moea_extract), 342 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 343 MMUMETHOD(mmu_init, moea_init), 344 MMUMETHOD(mmu_is_modified, moea_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 348 MMUMETHOD(mmu_map, moea_map), 349 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 350 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 351 MMUMETHOD(mmu_pinit, moea_pinit), 352 MMUMETHOD(mmu_pinit0, moea_pinit0), 353 MMUMETHOD(mmu_protect, moea_protect), 354 MMUMETHOD(mmu_qenter, moea_qenter), 355 MMUMETHOD(mmu_qremove, moea_qremove), 356 MMUMETHOD(mmu_release, moea_release), 357 MMUMETHOD(mmu_remove, moea_remove), 358 MMUMETHOD(mmu_remove_all, moea_remove_all), 359 MMUMETHOD(mmu_remove_write, moea_remove_write), 360 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 361 MMUMETHOD(mmu_zero_page, moea_zero_page), 362 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 363 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 364 MMUMETHOD(mmu_activate, moea_activate), 365 MMUMETHOD(mmu_deactivate, moea_deactivate), 366 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 370 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 371 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 372 MMUMETHOD(mmu_mapdev, moea_mapdev), 373 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 374 MMUMETHOD(mmu_kextract, moea_kextract), 375 MMUMETHOD(mmu_kenter, moea_kenter), 376 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378 379 { 0, 0 } 380 }; 381 382 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 383 384 static __inline uint32_t 385 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 386 { 387 uint32_t pte_lo; 388 int i; 389 390 if (ma != VM_MEMATTR_DEFAULT) { 391 switch (ma) { 392 case VM_MEMATTR_UNCACHEABLE: 393 return (PTE_I | PTE_G); 394 case VM_MEMATTR_WRITE_COMBINING: 395 case VM_MEMATTR_WRITE_BACK: 396 case VM_MEMATTR_PREFETCHABLE: 397 return (PTE_I); 398 case VM_MEMATTR_WRITE_THROUGH: 399 return (PTE_W | PTE_M); 400 } 401 } 402 403 /* 404 * Assume the page is cache inhibited and access is guarded unless 405 * it's in our available memory array. 406 */ 407 pte_lo = PTE_I | PTE_G; 408 for (i = 0; i < pregions_sz; i++) { 409 if ((pa >= pregions[i].mr_start) && 410 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 411 pte_lo = PTE_M; 412 break; 413 } 414 } 415 416 return pte_lo; 417 } 418 419 static void 420 tlbie(vm_offset_t va) 421 { 422 423 mtx_lock_spin(&tlbie_mtx); 424 __asm __volatile("ptesync"); 425 __asm __volatile("tlbie %0" :: "r"(va)); 426 __asm __volatile("eieio; tlbsync; ptesync"); 427 mtx_unlock_spin(&tlbie_mtx); 428 } 429 430 static void 431 tlbia(void) 432 { 433 vm_offset_t va; 434 435 for (va = 0; va < 0x00040000; va += 0x00001000) { 436 __asm __volatile("tlbie %0" :: "r"(va)); 437 powerpc_sync(); 438 } 439 __asm __volatile("tlbsync"); 440 powerpc_sync(); 441 } 442 443 static __inline int 444 va_to_sr(u_int *sr, vm_offset_t va) 445 { 446 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 447 } 448 449 static __inline u_int 450 va_to_pteg(u_int sr, vm_offset_t addr) 451 { 452 u_int hash; 453 454 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 455 ADDR_PIDX_SHFT); 456 return (hash & moea_pteg_mask); 457 } 458 459 static __inline struct pvo_head * 460 vm_page_to_pvoh(vm_page_t m) 461 { 462 463 return (&m->md.mdpg_pvoh); 464 } 465 466 static __inline void 467 moea_attr_clear(vm_page_t m, int ptebit) 468 { 469 470 rw_assert(&pvh_global_lock, RA_WLOCKED); 471 m->md.mdpg_attrs &= ~ptebit; 472 } 473 474 static __inline int 475 moea_attr_fetch(vm_page_t m) 476 { 477 478 return (m->md.mdpg_attrs); 479 } 480 481 static __inline void 482 moea_attr_save(vm_page_t m, int ptebit) 483 { 484 485 rw_assert(&pvh_global_lock, RA_WLOCKED); 486 m->md.mdpg_attrs |= ptebit; 487 } 488 489 static __inline int 490 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 491 { 492 if (pt->pte_hi == pvo_pt->pte_hi) 493 return (1); 494 495 return (0); 496 } 497 498 static __inline int 499 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 500 { 501 return (pt->pte_hi & ~PTE_VALID) == 502 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 503 ((va >> ADDR_API_SHFT) & PTE_API) | which); 504 } 505 506 static __inline void 507 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 508 { 509 510 mtx_assert(&moea_table_mutex, MA_OWNED); 511 512 /* 513 * Construct a PTE. Default to IMB initially. Valid bit only gets 514 * set when the real pte is set in memory. 515 * 516 * Note: Don't set the valid bit for correct operation of tlb update. 517 */ 518 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 519 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 520 pt->pte_lo = pte_lo; 521 } 522 523 static __inline void 524 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 525 { 526 527 mtx_assert(&moea_table_mutex, MA_OWNED); 528 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 529 } 530 531 static __inline void 532 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 533 { 534 535 mtx_assert(&moea_table_mutex, MA_OWNED); 536 537 /* 538 * As shown in Section 7.6.3.2.3 539 */ 540 pt->pte_lo &= ~ptebit; 541 tlbie(va); 542 } 543 544 static __inline void 545 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 546 { 547 548 mtx_assert(&moea_table_mutex, MA_OWNED); 549 pvo_pt->pte_hi |= PTE_VALID; 550 551 /* 552 * Update the PTE as defined in section 7.6.3.1. 553 * Note that the REF/CHG bits are from pvo_pt and thus should havce 554 * been saved so this routine can restore them (if desired). 555 */ 556 pt->pte_lo = pvo_pt->pte_lo; 557 powerpc_sync(); 558 pt->pte_hi = pvo_pt->pte_hi; 559 powerpc_sync(); 560 moea_pte_valid++; 561 } 562 563 static __inline void 564 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 565 { 566 567 mtx_assert(&moea_table_mutex, MA_OWNED); 568 pvo_pt->pte_hi &= ~PTE_VALID; 569 570 /* 571 * Force the reg & chg bits back into the PTEs. 572 */ 573 powerpc_sync(); 574 575 /* 576 * Invalidate the pte. 577 */ 578 pt->pte_hi &= ~PTE_VALID; 579 580 tlbie(va); 581 582 /* 583 * Save the reg & chg bits. 584 */ 585 moea_pte_synch(pt, pvo_pt); 586 moea_pte_valid--; 587 } 588 589 static __inline void 590 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 591 { 592 593 /* 594 * Invalidate the PTE 595 */ 596 moea_pte_unset(pt, pvo_pt, va); 597 moea_pte_set(pt, pvo_pt); 598 } 599 600 /* 601 * Quick sort callout for comparing memory regions. 602 */ 603 static int om_cmp(const void *a, const void *b); 604 605 static int 606 om_cmp(const void *a, const void *b) 607 { 608 const struct ofw_map *mapa; 609 const struct ofw_map *mapb; 610 611 mapa = a; 612 mapb = b; 613 if (mapa->om_pa < mapb->om_pa) 614 return (-1); 615 else if (mapa->om_pa > mapb->om_pa) 616 return (1); 617 else 618 return (0); 619 } 620 621 void 622 moea_cpu_bootstrap(mmu_t mmup, int ap) 623 { 624 u_int sdr; 625 int i; 626 627 if (ap) { 628 powerpc_sync(); 629 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 630 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 631 isync(); 632 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 633 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 634 isync(); 635 } 636 637 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 638 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 639 isync(); 640 641 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 642 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 643 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 644 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 645 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 646 isync(); 647 648 for (i = 0; i < 16; i++) 649 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 650 powerpc_sync(); 651 652 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 653 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 654 isync(); 655 656 tlbia(); 657 } 658 659 void 660 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 661 { 662 ihandle_t mmui; 663 phandle_t chosen, mmu; 664 int sz; 665 int i, j; 666 vm_size_t size, physsz, hwphyssz; 667 vm_offset_t pa, va, off; 668 void *dpcpu; 669 register_t msr; 670 671 /* 672 * Set up BAT0 to map the lowest 256 MB area 673 */ 674 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 675 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 676 677 /* 678 * Map PCI memory space. 679 */ 680 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 681 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 682 683 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 684 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 685 686 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 687 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 688 689 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 690 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 691 692 /* 693 * Map obio devices. 694 */ 695 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 696 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 697 698 /* 699 * Use an IBAT and a DBAT to map the bottom segment of memory 700 * where we are. Turn off instruction relocation temporarily 701 * to prevent faults while reprogramming the IBAT. 702 */ 703 msr = mfmsr(); 704 mtmsr(msr & ~PSL_IR); 705 __asm (".balign 32; \n" 706 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 707 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 708 :: "r"(battable[0].batu), "r"(battable[0].batl)); 709 mtmsr(msr); 710 711 /* map pci space */ 712 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 713 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 714 isync(); 715 716 /* set global direct map flag */ 717 hw_direct_map = 1; 718 719 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 720 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 721 722 for (i = 0; i < pregions_sz; i++) { 723 vm_offset_t pa; 724 vm_offset_t end; 725 726 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 727 pregions[i].mr_start, 728 pregions[i].mr_start + pregions[i].mr_size, 729 pregions[i].mr_size); 730 /* 731 * Install entries into the BAT table to allow all 732 * of physmem to be convered by on-demand BAT entries. 733 * The loop will sometimes set the same battable element 734 * twice, but that's fine since they won't be used for 735 * a while yet. 736 */ 737 pa = pregions[i].mr_start & 0xf0000000; 738 end = pregions[i].mr_start + pregions[i].mr_size; 739 do { 740 u_int n = pa >> ADDR_SR_SHFT; 741 742 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 743 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 744 pa += SEGMENT_LENGTH; 745 } while (pa < end); 746 } 747 748 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 749 panic("moea_bootstrap: phys_avail too small"); 750 751 phys_avail_count = 0; 752 physsz = 0; 753 hwphyssz = 0; 754 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 755 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 756 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 757 regions[i].mr_start + regions[i].mr_size, 758 regions[i].mr_size); 759 if (hwphyssz != 0 && 760 (physsz + regions[i].mr_size) >= hwphyssz) { 761 if (physsz < hwphyssz) { 762 phys_avail[j] = regions[i].mr_start; 763 phys_avail[j + 1] = regions[i].mr_start + 764 hwphyssz - physsz; 765 physsz = hwphyssz; 766 phys_avail_count++; 767 } 768 break; 769 } 770 phys_avail[j] = regions[i].mr_start; 771 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 772 phys_avail_count++; 773 physsz += regions[i].mr_size; 774 } 775 776 /* Check for overlap with the kernel and exception vectors */ 777 for (j = 0; j < 2*phys_avail_count; j+=2) { 778 if (phys_avail[j] < EXC_LAST) 779 phys_avail[j] += EXC_LAST; 780 781 if (kernelstart >= phys_avail[j] && 782 kernelstart < phys_avail[j+1]) { 783 if (kernelend < phys_avail[j+1]) { 784 phys_avail[2*phys_avail_count] = 785 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 786 phys_avail[2*phys_avail_count + 1] = 787 phys_avail[j+1]; 788 phys_avail_count++; 789 } 790 791 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 792 } 793 794 if (kernelend >= phys_avail[j] && 795 kernelend < phys_avail[j+1]) { 796 if (kernelstart > phys_avail[j]) { 797 phys_avail[2*phys_avail_count] = phys_avail[j]; 798 phys_avail[2*phys_avail_count + 1] = 799 kernelstart & ~PAGE_MASK; 800 phys_avail_count++; 801 } 802 803 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 804 } 805 } 806 807 physmem = btoc(physsz); 808 809 /* 810 * Allocate PTEG table. 811 */ 812 #ifdef PTEGCOUNT 813 moea_pteg_count = PTEGCOUNT; 814 #else 815 moea_pteg_count = 0x1000; 816 817 while (moea_pteg_count < physmem) 818 moea_pteg_count <<= 1; 819 820 moea_pteg_count >>= 1; 821 #endif /* PTEGCOUNT */ 822 823 size = moea_pteg_count * sizeof(struct pteg); 824 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 825 size); 826 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 827 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 828 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 829 moea_pteg_mask = moea_pteg_count - 1; 830 831 /* 832 * Allocate pv/overflow lists. 833 */ 834 size = sizeof(struct pvo_head) * moea_pteg_count; 835 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 836 PAGE_SIZE); 837 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 838 for (i = 0; i < moea_pteg_count; i++) 839 LIST_INIT(&moea_pvo_table[i]); 840 841 /* 842 * Initialize the lock that synchronizes access to the pteg and pvo 843 * tables. 844 */ 845 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 846 MTX_RECURSE); 847 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 848 849 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 850 851 /* 852 * Initialise the unmanaged pvo pool. 853 */ 854 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 855 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 856 moea_bpvo_pool_index = 0; 857 858 /* 859 * Make sure kernel vsid is allocated as well as VSID 0. 860 */ 861 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 862 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 863 moea_vsid_bitmap[0] |= 1; 864 865 /* 866 * Initialize the kernel pmap (which is statically allocated). 867 */ 868 PMAP_LOCK_INIT(kernel_pmap); 869 for (i = 0; i < 16; i++) 870 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 871 CPU_FILL(&kernel_pmap->pm_active); 872 RB_INIT(&kernel_pmap->pmap_pvo); 873 874 /* 875 * Initialize the global pv list lock. 876 */ 877 rw_init(&pvh_global_lock, "pmap pv global"); 878 879 /* 880 * Set up the Open Firmware mappings 881 */ 882 chosen = OF_finddevice("/chosen"); 883 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 884 (mmu = OF_instance_to_package(mmui)) != -1 && 885 (sz = OF_getproplen(mmu, "translations")) != -1) { 886 translations = NULL; 887 for (i = 0; phys_avail[i] != 0; i += 2) { 888 if (phys_avail[i + 1] >= sz) { 889 translations = (struct ofw_map *)phys_avail[i]; 890 break; 891 } 892 } 893 if (translations == NULL) 894 panic("moea_bootstrap: no space to copy translations"); 895 bzero(translations, sz); 896 if (OF_getprop(mmu, "translations", translations, sz) == -1) 897 panic("moea_bootstrap: can't get ofw translations"); 898 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 899 sz /= sizeof(*translations); 900 qsort(translations, sz, sizeof (*translations), om_cmp); 901 for (i = 0; i < sz; i++) { 902 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 903 translations[i].om_pa, translations[i].om_va, 904 translations[i].om_len); 905 906 /* 907 * If the mapping is 1:1, let the RAM and device 908 * on-demand BAT tables take care of the translation. 909 */ 910 if (translations[i].om_va == translations[i].om_pa) 911 continue; 912 913 /* Enter the pages */ 914 for (off = 0; off < translations[i].om_len; 915 off += PAGE_SIZE) 916 moea_kenter(mmup, translations[i].om_va + off, 917 translations[i].om_pa + off); 918 } 919 } 920 921 /* 922 * Calculate the last available physical address. 923 */ 924 for (i = 0; phys_avail[i + 2] != 0; i += 2) 925 ; 926 Maxmem = powerpc_btop(phys_avail[i + 1]); 927 928 moea_cpu_bootstrap(mmup,0); 929 930 pmap_bootstrapped++; 931 932 /* 933 * Set the start and end of kva. 934 */ 935 virtual_avail = VM_MIN_KERNEL_ADDRESS; 936 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 937 938 /* 939 * Allocate a kernel stack with a guard page for thread0 and map it 940 * into the kernel page map. 941 */ 942 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 943 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 944 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 945 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 946 thread0.td_kstack = va; 947 thread0.td_kstack_pages = KSTACK_PAGES; 948 for (i = 0; i < KSTACK_PAGES; i++) { 949 moea_kenter(mmup, va, pa); 950 pa += PAGE_SIZE; 951 va += PAGE_SIZE; 952 } 953 954 /* 955 * Allocate virtual address space for the message buffer. 956 */ 957 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 958 msgbufp = (struct msgbuf *)virtual_avail; 959 va = virtual_avail; 960 virtual_avail += round_page(msgbufsize); 961 while (va < virtual_avail) { 962 moea_kenter(mmup, va, pa); 963 pa += PAGE_SIZE; 964 va += PAGE_SIZE; 965 } 966 967 /* 968 * Allocate virtual address space for the dynamic percpu area. 969 */ 970 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 971 dpcpu = (void *)virtual_avail; 972 va = virtual_avail; 973 virtual_avail += DPCPU_SIZE; 974 while (va < virtual_avail) { 975 moea_kenter(mmup, va, pa); 976 pa += PAGE_SIZE; 977 va += PAGE_SIZE; 978 } 979 dpcpu_init(dpcpu, 0); 980 } 981 982 /* 983 * Activate a user pmap. The pmap must be activated before it's address 984 * space can be accessed in any way. 985 */ 986 void 987 moea_activate(mmu_t mmu, struct thread *td) 988 { 989 pmap_t pm, pmr; 990 991 /* 992 * Load all the data we need up front to encourage the compiler to 993 * not issue any loads while we have interrupts disabled below. 994 */ 995 pm = &td->td_proc->p_vmspace->vm_pmap; 996 pmr = pm->pmap_phys; 997 998 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 999 PCPU_SET(curpmap, pmr); 1000 } 1001 1002 void 1003 moea_deactivate(mmu_t mmu, struct thread *td) 1004 { 1005 pmap_t pm; 1006 1007 pm = &td->td_proc->p_vmspace->vm_pmap; 1008 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1009 PCPU_SET(curpmap, NULL); 1010 } 1011 1012 void 1013 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1014 { 1015 struct pvo_entry *pvo; 1016 1017 PMAP_LOCK(pm); 1018 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1019 1020 if (pvo != NULL) { 1021 if (wired) { 1022 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1023 pm->pm_stats.wired_count++; 1024 pvo->pvo_vaddr |= PVO_WIRED; 1025 } else { 1026 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1027 pm->pm_stats.wired_count--; 1028 pvo->pvo_vaddr &= ~PVO_WIRED; 1029 } 1030 } 1031 PMAP_UNLOCK(pm); 1032 } 1033 1034 void 1035 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1036 { 1037 vm_offset_t dst; 1038 vm_offset_t src; 1039 1040 dst = VM_PAGE_TO_PHYS(mdst); 1041 src = VM_PAGE_TO_PHYS(msrc); 1042 1043 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1044 } 1045 1046 /* 1047 * Zero a page of physical memory by temporarily mapping it into the tlb. 1048 */ 1049 void 1050 moea_zero_page(mmu_t mmu, vm_page_t m) 1051 { 1052 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1053 void *va = (void *)pa; 1054 1055 bzero(va, PAGE_SIZE); 1056 } 1057 1058 void 1059 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1060 { 1061 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1062 void *va = (void *)(pa + off); 1063 1064 bzero(va, size); 1065 } 1066 1067 void 1068 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1069 { 1070 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1071 void *va = (void *)pa; 1072 1073 bzero(va, PAGE_SIZE); 1074 } 1075 1076 /* 1077 * Map the given physical page at the specified virtual address in the 1078 * target pmap with the protection requested. If specified the page 1079 * will be wired down. 1080 */ 1081 void 1082 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1083 boolean_t wired) 1084 { 1085 1086 rw_wlock(&pvh_global_lock); 1087 PMAP_LOCK(pmap); 1088 moea_enter_locked(pmap, va, m, prot, wired); 1089 rw_wunlock(&pvh_global_lock); 1090 PMAP_UNLOCK(pmap); 1091 } 1092 1093 /* 1094 * Map the given physical page at the specified virtual address in the 1095 * target pmap with the protection requested. If specified the page 1096 * will be wired down. 1097 * 1098 * The page queues and pmap must be locked. 1099 */ 1100 static void 1101 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1102 boolean_t wired) 1103 { 1104 struct pvo_head *pvo_head; 1105 uma_zone_t zone; 1106 vm_page_t pg; 1107 u_int pte_lo, pvo_flags; 1108 int error; 1109 1110 if (!moea_initialized) { 1111 pvo_head = &moea_pvo_kunmanaged; 1112 zone = moea_upvo_zone; 1113 pvo_flags = 0; 1114 pg = NULL; 1115 } else { 1116 pvo_head = vm_page_to_pvoh(m); 1117 pg = m; 1118 zone = moea_mpvo_zone; 1119 pvo_flags = PVO_MANAGED; 1120 } 1121 if (pmap_bootstrapped) 1122 rw_assert(&pvh_global_lock, RA_WLOCKED); 1123 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1124 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1125 VM_OBJECT_LOCKED(m->object), 1126 ("moea_enter_locked: page %p is not busy", m)); 1127 1128 /* XXX change the pvo head for fake pages */ 1129 if ((m->oflags & VPO_UNMANAGED) != 0) { 1130 pvo_flags &= ~PVO_MANAGED; 1131 pvo_head = &moea_pvo_kunmanaged; 1132 zone = moea_upvo_zone; 1133 } 1134 1135 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1136 1137 if (prot & VM_PROT_WRITE) { 1138 pte_lo |= PTE_BW; 1139 if (pmap_bootstrapped && 1140 (m->oflags & VPO_UNMANAGED) == 0) 1141 vm_page_aflag_set(m, PGA_WRITEABLE); 1142 } else 1143 pte_lo |= PTE_BR; 1144 1145 if (prot & VM_PROT_EXECUTE) 1146 pvo_flags |= PVO_EXECUTABLE; 1147 1148 if (wired) 1149 pvo_flags |= PVO_WIRED; 1150 1151 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1152 pte_lo, pvo_flags); 1153 1154 /* 1155 * Flush the real page from the instruction cache. This has be done 1156 * for all user mappings to prevent information leakage via the 1157 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1158 * mapping for a page. 1159 */ 1160 if (pmap != kernel_pmap && error == ENOENT && 1161 (pte_lo & (PTE_I | PTE_G)) == 0) 1162 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1163 } 1164 1165 /* 1166 * Maps a sequence of resident pages belonging to the same object. 1167 * The sequence begins with the given page m_start. This page is 1168 * mapped at the given virtual address start. Each subsequent page is 1169 * mapped at a virtual address that is offset from start by the same 1170 * amount as the page is offset from m_start within the object. The 1171 * last page in the sequence is the page with the largest offset from 1172 * m_start that can be mapped at a virtual address less than the given 1173 * virtual address end. Not every virtual page between start and end 1174 * is mapped; only those for which a resident page exists with the 1175 * corresponding offset from m_start are mapped. 1176 */ 1177 void 1178 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1179 vm_page_t m_start, vm_prot_t prot) 1180 { 1181 vm_page_t m; 1182 vm_pindex_t diff, psize; 1183 1184 psize = atop(end - start); 1185 m = m_start; 1186 rw_wlock(&pvh_global_lock); 1187 PMAP_LOCK(pm); 1188 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1189 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1190 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1191 m = TAILQ_NEXT(m, listq); 1192 } 1193 rw_wunlock(&pvh_global_lock); 1194 PMAP_UNLOCK(pm); 1195 } 1196 1197 void 1198 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1199 vm_prot_t prot) 1200 { 1201 1202 rw_wlock(&pvh_global_lock); 1203 PMAP_LOCK(pm); 1204 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1205 FALSE); 1206 rw_wunlock(&pvh_global_lock); 1207 PMAP_UNLOCK(pm); 1208 } 1209 1210 vm_paddr_t 1211 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1212 { 1213 struct pvo_entry *pvo; 1214 vm_paddr_t pa; 1215 1216 PMAP_LOCK(pm); 1217 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1218 if (pvo == NULL) 1219 pa = 0; 1220 else 1221 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1222 PMAP_UNLOCK(pm); 1223 return (pa); 1224 } 1225 1226 /* 1227 * Atomically extract and hold the physical page with the given 1228 * pmap and virtual address pair if that mapping permits the given 1229 * protection. 1230 */ 1231 vm_page_t 1232 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1233 { 1234 struct pvo_entry *pvo; 1235 vm_page_t m; 1236 vm_paddr_t pa; 1237 1238 m = NULL; 1239 pa = 0; 1240 PMAP_LOCK(pmap); 1241 retry: 1242 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1243 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1244 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1245 (prot & VM_PROT_WRITE) == 0)) { 1246 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1247 goto retry; 1248 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1249 vm_page_hold(m); 1250 } 1251 PA_UNLOCK_COND(pa); 1252 PMAP_UNLOCK(pmap); 1253 return (m); 1254 } 1255 1256 void 1257 moea_init(mmu_t mmu) 1258 { 1259 1260 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1261 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1262 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1263 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1264 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1265 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1266 moea_initialized = TRUE; 1267 } 1268 1269 boolean_t 1270 moea_is_referenced(mmu_t mmu, vm_page_t m) 1271 { 1272 boolean_t rv; 1273 1274 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1275 ("moea_is_referenced: page %p is not managed", m)); 1276 rw_wlock(&pvh_global_lock); 1277 rv = moea_query_bit(m, PTE_REF); 1278 rw_wunlock(&pvh_global_lock); 1279 return (rv); 1280 } 1281 1282 boolean_t 1283 moea_is_modified(mmu_t mmu, vm_page_t m) 1284 { 1285 boolean_t rv; 1286 1287 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1288 ("moea_is_modified: page %p is not managed", m)); 1289 1290 /* 1291 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1292 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1293 * is clear, no PTEs can have PTE_CHG set. 1294 */ 1295 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1296 if ((m->oflags & VPO_BUSY) == 0 && 1297 (m->aflags & PGA_WRITEABLE) == 0) 1298 return (FALSE); 1299 rw_wlock(&pvh_global_lock); 1300 rv = moea_query_bit(m, PTE_CHG); 1301 rw_wunlock(&pvh_global_lock); 1302 return (rv); 1303 } 1304 1305 boolean_t 1306 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1307 { 1308 struct pvo_entry *pvo; 1309 boolean_t rv; 1310 1311 PMAP_LOCK(pmap); 1312 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1313 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1314 PMAP_UNLOCK(pmap); 1315 return (rv); 1316 } 1317 1318 void 1319 moea_clear_reference(mmu_t mmu, vm_page_t m) 1320 { 1321 1322 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1323 ("moea_clear_reference: page %p is not managed", m)); 1324 rw_wlock(&pvh_global_lock); 1325 moea_clear_bit(m, PTE_REF); 1326 rw_wunlock(&pvh_global_lock); 1327 } 1328 1329 void 1330 moea_clear_modify(mmu_t mmu, vm_page_t m) 1331 { 1332 1333 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1334 ("moea_clear_modify: page %p is not managed", m)); 1335 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1336 KASSERT((m->oflags & VPO_BUSY) == 0, 1337 ("moea_clear_modify: page %p is busy", m)); 1338 1339 /* 1340 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1341 * set. If the object containing the page is locked and the page is 1342 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1343 */ 1344 if ((m->aflags & PGA_WRITEABLE) == 0) 1345 return; 1346 rw_wlock(&pvh_global_lock); 1347 moea_clear_bit(m, PTE_CHG); 1348 rw_wunlock(&pvh_global_lock); 1349 } 1350 1351 /* 1352 * Clear the write and modified bits in each of the given page's mappings. 1353 */ 1354 void 1355 moea_remove_write(mmu_t mmu, vm_page_t m) 1356 { 1357 struct pvo_entry *pvo; 1358 struct pte *pt; 1359 pmap_t pmap; 1360 u_int lo; 1361 1362 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1363 ("moea_remove_write: page %p is not managed", m)); 1364 1365 /* 1366 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1367 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1368 * is clear, no page table entries need updating. 1369 */ 1370 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1371 if ((m->oflags & VPO_BUSY) == 0 && 1372 (m->aflags & PGA_WRITEABLE) == 0) 1373 return; 1374 rw_wlock(&pvh_global_lock); 1375 lo = moea_attr_fetch(m); 1376 powerpc_sync(); 1377 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1378 pmap = pvo->pvo_pmap; 1379 PMAP_LOCK(pmap); 1380 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1381 pt = moea_pvo_to_pte(pvo, -1); 1382 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1383 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1384 if (pt != NULL) { 1385 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1386 lo |= pvo->pvo_pte.pte.pte_lo; 1387 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1388 moea_pte_change(pt, &pvo->pvo_pte.pte, 1389 pvo->pvo_vaddr); 1390 mtx_unlock(&moea_table_mutex); 1391 } 1392 } 1393 PMAP_UNLOCK(pmap); 1394 } 1395 if ((lo & PTE_CHG) != 0) { 1396 moea_attr_clear(m, PTE_CHG); 1397 vm_page_dirty(m); 1398 } 1399 vm_page_aflag_clear(m, PGA_WRITEABLE); 1400 rw_wunlock(&pvh_global_lock); 1401 } 1402 1403 /* 1404 * moea_ts_referenced: 1405 * 1406 * Return a count of reference bits for a page, clearing those bits. 1407 * It is not necessary for every reference bit to be cleared, but it 1408 * is necessary that 0 only be returned when there are truly no 1409 * reference bits set. 1410 * 1411 * XXX: The exact number of bits to check and clear is a matter that 1412 * should be tested and standardized at some point in the future for 1413 * optimal aging of shared pages. 1414 */ 1415 int 1416 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1417 { 1418 int count; 1419 1420 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1421 ("moea_ts_referenced: page %p is not managed", m)); 1422 rw_wlock(&pvh_global_lock); 1423 count = moea_clear_bit(m, PTE_REF); 1424 rw_wunlock(&pvh_global_lock); 1425 return (count); 1426 } 1427 1428 /* 1429 * Modify the WIMG settings of all mappings for a page. 1430 */ 1431 void 1432 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1433 { 1434 struct pvo_entry *pvo; 1435 struct pvo_head *pvo_head; 1436 struct pte *pt; 1437 pmap_t pmap; 1438 u_int lo; 1439 1440 if ((m->oflags & VPO_UNMANAGED) != 0) { 1441 m->md.mdpg_cache_attrs = ma; 1442 return; 1443 } 1444 1445 rw_wlock(&pvh_global_lock); 1446 pvo_head = vm_page_to_pvoh(m); 1447 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1448 1449 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1450 pmap = pvo->pvo_pmap; 1451 PMAP_LOCK(pmap); 1452 pt = moea_pvo_to_pte(pvo, -1); 1453 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1454 pvo->pvo_pte.pte.pte_lo |= lo; 1455 if (pt != NULL) { 1456 moea_pte_change(pt, &pvo->pvo_pte.pte, 1457 pvo->pvo_vaddr); 1458 if (pvo->pvo_pmap == kernel_pmap) 1459 isync(); 1460 } 1461 mtx_unlock(&moea_table_mutex); 1462 PMAP_UNLOCK(pmap); 1463 } 1464 m->md.mdpg_cache_attrs = ma; 1465 rw_wunlock(&pvh_global_lock); 1466 } 1467 1468 /* 1469 * Map a wired page into kernel virtual address space. 1470 */ 1471 void 1472 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1473 { 1474 1475 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1476 } 1477 1478 void 1479 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1480 { 1481 u_int pte_lo; 1482 int error; 1483 1484 #if 0 1485 if (va < VM_MIN_KERNEL_ADDRESS) 1486 panic("moea_kenter: attempt to enter non-kernel address %#x", 1487 va); 1488 #endif 1489 1490 pte_lo = moea_calc_wimg(pa, ma); 1491 1492 PMAP_LOCK(kernel_pmap); 1493 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1494 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1495 1496 if (error != 0 && error != ENOENT) 1497 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1498 pa, error); 1499 1500 PMAP_UNLOCK(kernel_pmap); 1501 } 1502 1503 /* 1504 * Extract the physical page address associated with the given kernel virtual 1505 * address. 1506 */ 1507 vm_paddr_t 1508 moea_kextract(mmu_t mmu, vm_offset_t va) 1509 { 1510 struct pvo_entry *pvo; 1511 vm_paddr_t pa; 1512 1513 /* 1514 * Allow direct mappings on 32-bit OEA 1515 */ 1516 if (va < VM_MIN_KERNEL_ADDRESS) { 1517 return (va); 1518 } 1519 1520 PMAP_LOCK(kernel_pmap); 1521 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1522 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1523 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1524 PMAP_UNLOCK(kernel_pmap); 1525 return (pa); 1526 } 1527 1528 /* 1529 * Remove a wired page from kernel virtual address space. 1530 */ 1531 void 1532 moea_kremove(mmu_t mmu, vm_offset_t va) 1533 { 1534 1535 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1536 } 1537 1538 /* 1539 * Map a range of physical addresses into kernel virtual address space. 1540 * 1541 * The value passed in *virt is a suggested virtual address for the mapping. 1542 * Architectures which can support a direct-mapped physical to virtual region 1543 * can return the appropriate address within that region, leaving '*virt' 1544 * unchanged. We cannot and therefore do not; *virt is updated with the 1545 * first usable address after the mapped region. 1546 */ 1547 vm_offset_t 1548 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1549 vm_paddr_t pa_end, int prot) 1550 { 1551 vm_offset_t sva, va; 1552 1553 sva = *virt; 1554 va = sva; 1555 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1556 moea_kenter(mmu, va, pa_start); 1557 *virt = va; 1558 return (sva); 1559 } 1560 1561 /* 1562 * Returns true if the pmap's pv is one of the first 1563 * 16 pvs linked to from this page. This count may 1564 * be changed upwards or downwards in the future; it 1565 * is only necessary that true be returned for a small 1566 * subset of pmaps for proper page aging. 1567 */ 1568 boolean_t 1569 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1570 { 1571 int loops; 1572 struct pvo_entry *pvo; 1573 boolean_t rv; 1574 1575 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1576 ("moea_page_exists_quick: page %p is not managed", m)); 1577 loops = 0; 1578 rv = FALSE; 1579 rw_wlock(&pvh_global_lock); 1580 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1581 if (pvo->pvo_pmap == pmap) { 1582 rv = TRUE; 1583 break; 1584 } 1585 if (++loops >= 16) 1586 break; 1587 } 1588 rw_wunlock(&pvh_global_lock); 1589 return (rv); 1590 } 1591 1592 /* 1593 * Return the number of managed mappings to the given physical page 1594 * that are wired. 1595 */ 1596 int 1597 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1598 { 1599 struct pvo_entry *pvo; 1600 int count; 1601 1602 count = 0; 1603 if ((m->oflags & VPO_UNMANAGED) != 0) 1604 return (count); 1605 rw_wlock(&pvh_global_lock); 1606 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1607 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1608 count++; 1609 rw_wunlock(&pvh_global_lock); 1610 return (count); 1611 } 1612 1613 static u_int moea_vsidcontext; 1614 1615 void 1616 moea_pinit(mmu_t mmu, pmap_t pmap) 1617 { 1618 int i, mask; 1619 u_int entropy; 1620 1621 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1622 PMAP_LOCK_INIT(pmap); 1623 RB_INIT(&pmap->pmap_pvo); 1624 1625 entropy = 0; 1626 __asm __volatile("mftb %0" : "=r"(entropy)); 1627 1628 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1629 == NULL) { 1630 pmap->pmap_phys = pmap; 1631 } 1632 1633 1634 mtx_lock(&moea_vsid_mutex); 1635 /* 1636 * Allocate some segment registers for this pmap. 1637 */ 1638 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1639 u_int hash, n; 1640 1641 /* 1642 * Create a new value by mutiplying by a prime and adding in 1643 * entropy from the timebase register. This is to make the 1644 * VSID more random so that the PT hash function collides 1645 * less often. (Note that the prime casues gcc to do shifts 1646 * instead of a multiply.) 1647 */ 1648 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1649 hash = moea_vsidcontext & (NPMAPS - 1); 1650 if (hash == 0) /* 0 is special, avoid it */ 1651 continue; 1652 n = hash >> 5; 1653 mask = 1 << (hash & (VSID_NBPW - 1)); 1654 hash = (moea_vsidcontext & 0xfffff); 1655 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1656 /* anything free in this bucket? */ 1657 if (moea_vsid_bitmap[n] == 0xffffffff) { 1658 entropy = (moea_vsidcontext >> 20); 1659 continue; 1660 } 1661 i = ffs(~moea_vsid_bitmap[n]) - 1; 1662 mask = 1 << i; 1663 hash &= 0xfffff & ~(VSID_NBPW - 1); 1664 hash |= i; 1665 } 1666 KASSERT(!(moea_vsid_bitmap[n] & mask), 1667 ("Allocating in-use VSID group %#x\n", hash)); 1668 moea_vsid_bitmap[n] |= mask; 1669 for (i = 0; i < 16; i++) 1670 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1671 mtx_unlock(&moea_vsid_mutex); 1672 return; 1673 } 1674 1675 mtx_unlock(&moea_vsid_mutex); 1676 panic("moea_pinit: out of segments"); 1677 } 1678 1679 /* 1680 * Initialize the pmap associated with process 0. 1681 */ 1682 void 1683 moea_pinit0(mmu_t mmu, pmap_t pm) 1684 { 1685 1686 moea_pinit(mmu, pm); 1687 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1688 } 1689 1690 /* 1691 * Set the physical protection on the specified range of this map as requested. 1692 */ 1693 void 1694 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1695 vm_prot_t prot) 1696 { 1697 struct pvo_entry *pvo, *tpvo, key; 1698 struct pte *pt; 1699 1700 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1701 ("moea_protect: non current pmap")); 1702 1703 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1704 moea_remove(mmu, pm, sva, eva); 1705 return; 1706 } 1707 1708 rw_wlock(&pvh_global_lock); 1709 PMAP_LOCK(pm); 1710 key.pvo_vaddr = sva; 1711 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1712 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1713 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1714 if ((prot & VM_PROT_EXECUTE) == 0) 1715 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1716 1717 /* 1718 * Grab the PTE pointer before we diddle with the cached PTE 1719 * copy. 1720 */ 1721 pt = moea_pvo_to_pte(pvo, -1); 1722 /* 1723 * Change the protection of the page. 1724 */ 1725 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1726 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1727 1728 /* 1729 * If the PVO is in the page table, update that pte as well. 1730 */ 1731 if (pt != NULL) { 1732 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1733 mtx_unlock(&moea_table_mutex); 1734 } 1735 } 1736 rw_wunlock(&pvh_global_lock); 1737 PMAP_UNLOCK(pm); 1738 } 1739 1740 /* 1741 * Map a list of wired pages into kernel virtual address space. This is 1742 * intended for temporary mappings which do not need page modification or 1743 * references recorded. Existing mappings in the region are overwritten. 1744 */ 1745 void 1746 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1747 { 1748 vm_offset_t va; 1749 1750 va = sva; 1751 while (count-- > 0) { 1752 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1753 va += PAGE_SIZE; 1754 m++; 1755 } 1756 } 1757 1758 /* 1759 * Remove page mappings from kernel virtual address space. Intended for 1760 * temporary mappings entered by moea_qenter. 1761 */ 1762 void 1763 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1764 { 1765 vm_offset_t va; 1766 1767 va = sva; 1768 while (count-- > 0) { 1769 moea_kremove(mmu, va); 1770 va += PAGE_SIZE; 1771 } 1772 } 1773 1774 void 1775 moea_release(mmu_t mmu, pmap_t pmap) 1776 { 1777 int idx, mask; 1778 1779 /* 1780 * Free segment register's VSID 1781 */ 1782 if (pmap->pm_sr[0] == 0) 1783 panic("moea_release"); 1784 1785 mtx_lock(&moea_vsid_mutex); 1786 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1787 mask = 1 << (idx % VSID_NBPW); 1788 idx /= VSID_NBPW; 1789 moea_vsid_bitmap[idx] &= ~mask; 1790 mtx_unlock(&moea_vsid_mutex); 1791 PMAP_LOCK_DESTROY(pmap); 1792 } 1793 1794 /* 1795 * Remove the given range of addresses from the specified map. 1796 */ 1797 void 1798 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1799 { 1800 struct pvo_entry *pvo, *tpvo, key; 1801 1802 rw_wlock(&pvh_global_lock); 1803 PMAP_LOCK(pm); 1804 key.pvo_vaddr = sva; 1805 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1806 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1807 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1808 moea_pvo_remove(pvo, -1); 1809 } 1810 PMAP_UNLOCK(pm); 1811 rw_wunlock(&pvh_global_lock); 1812 } 1813 1814 /* 1815 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1816 * will reflect changes in pte's back to the vm_page. 1817 */ 1818 void 1819 moea_remove_all(mmu_t mmu, vm_page_t m) 1820 { 1821 struct pvo_head *pvo_head; 1822 struct pvo_entry *pvo, *next_pvo; 1823 pmap_t pmap; 1824 1825 rw_wlock(&pvh_global_lock); 1826 pvo_head = vm_page_to_pvoh(m); 1827 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1828 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1829 1830 pmap = pvo->pvo_pmap; 1831 PMAP_LOCK(pmap); 1832 moea_pvo_remove(pvo, -1); 1833 PMAP_UNLOCK(pmap); 1834 } 1835 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1836 moea_attr_clear(m, PTE_CHG); 1837 vm_page_dirty(m); 1838 } 1839 vm_page_aflag_clear(m, PGA_WRITEABLE); 1840 rw_wunlock(&pvh_global_lock); 1841 } 1842 1843 /* 1844 * Allocate a physical page of memory directly from the phys_avail map. 1845 * Can only be called from moea_bootstrap before avail start and end are 1846 * calculated. 1847 */ 1848 static vm_offset_t 1849 moea_bootstrap_alloc(vm_size_t size, u_int align) 1850 { 1851 vm_offset_t s, e; 1852 int i, j; 1853 1854 size = round_page(size); 1855 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1856 if (align != 0) 1857 s = (phys_avail[i] + align - 1) & ~(align - 1); 1858 else 1859 s = phys_avail[i]; 1860 e = s + size; 1861 1862 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1863 continue; 1864 1865 if (s == phys_avail[i]) { 1866 phys_avail[i] += size; 1867 } else if (e == phys_avail[i + 1]) { 1868 phys_avail[i + 1] -= size; 1869 } else { 1870 for (j = phys_avail_count * 2; j > i; j -= 2) { 1871 phys_avail[j] = phys_avail[j - 2]; 1872 phys_avail[j + 1] = phys_avail[j - 1]; 1873 } 1874 1875 phys_avail[i + 3] = phys_avail[i + 1]; 1876 phys_avail[i + 1] = s; 1877 phys_avail[i + 2] = e; 1878 phys_avail_count++; 1879 } 1880 1881 return (s); 1882 } 1883 panic("moea_bootstrap_alloc: could not allocate memory"); 1884 } 1885 1886 static void 1887 moea_syncicache(vm_offset_t pa, vm_size_t len) 1888 { 1889 __syncicache((void *)pa, len); 1890 } 1891 1892 static int 1893 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1894 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1895 { 1896 struct pvo_entry *pvo; 1897 u_int sr; 1898 int first; 1899 u_int ptegidx; 1900 int i; 1901 int bootstrap; 1902 1903 moea_pvo_enter_calls++; 1904 first = 0; 1905 bootstrap = 0; 1906 1907 /* 1908 * Compute the PTE Group index. 1909 */ 1910 va &= ~ADDR_POFF; 1911 sr = va_to_sr(pm->pm_sr, va); 1912 ptegidx = va_to_pteg(sr, va); 1913 1914 /* 1915 * Remove any existing mapping for this page. Reuse the pvo entry if 1916 * there is a mapping. 1917 */ 1918 mtx_lock(&moea_table_mutex); 1919 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1920 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1921 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1922 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1923 (pte_lo & PTE_PP)) { 1924 mtx_unlock(&moea_table_mutex); 1925 return (0); 1926 } 1927 moea_pvo_remove(pvo, -1); 1928 break; 1929 } 1930 } 1931 1932 /* 1933 * If we aren't overwriting a mapping, try to allocate. 1934 */ 1935 if (moea_initialized) { 1936 pvo = uma_zalloc(zone, M_NOWAIT); 1937 } else { 1938 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1939 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1940 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1941 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1942 } 1943 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1944 moea_bpvo_pool_index++; 1945 bootstrap = 1; 1946 } 1947 1948 if (pvo == NULL) { 1949 mtx_unlock(&moea_table_mutex); 1950 return (ENOMEM); 1951 } 1952 1953 moea_pvo_entries++; 1954 pvo->pvo_vaddr = va; 1955 pvo->pvo_pmap = pm; 1956 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1957 pvo->pvo_vaddr &= ~ADDR_POFF; 1958 if (flags & VM_PROT_EXECUTE) 1959 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1960 if (flags & PVO_WIRED) 1961 pvo->pvo_vaddr |= PVO_WIRED; 1962 if (pvo_head != &moea_pvo_kunmanaged) 1963 pvo->pvo_vaddr |= PVO_MANAGED; 1964 if (bootstrap) 1965 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1966 1967 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1968 1969 /* 1970 * Add to pmap list 1971 */ 1972 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1973 1974 /* 1975 * Remember if the list was empty and therefore will be the first 1976 * item. 1977 */ 1978 if (LIST_FIRST(pvo_head) == NULL) 1979 first = 1; 1980 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1981 1982 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1983 pm->pm_stats.wired_count++; 1984 pm->pm_stats.resident_count++; 1985 1986 /* 1987 * We hope this succeeds but it isn't required. 1988 */ 1989 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1990 if (i >= 0) { 1991 PVO_PTEGIDX_SET(pvo, i); 1992 } else { 1993 panic("moea_pvo_enter: overflow"); 1994 moea_pte_overflow++; 1995 } 1996 mtx_unlock(&moea_table_mutex); 1997 1998 return (first ? ENOENT : 0); 1999 } 2000 2001 static void 2002 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2003 { 2004 struct pte *pt; 2005 2006 /* 2007 * If there is an active pte entry, we need to deactivate it (and 2008 * save the ref & cfg bits). 2009 */ 2010 pt = moea_pvo_to_pte(pvo, pteidx); 2011 if (pt != NULL) { 2012 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2013 mtx_unlock(&moea_table_mutex); 2014 PVO_PTEGIDX_CLR(pvo); 2015 } else { 2016 moea_pte_overflow--; 2017 } 2018 2019 /* 2020 * Update our statistics. 2021 */ 2022 pvo->pvo_pmap->pm_stats.resident_count--; 2023 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2024 pvo->pvo_pmap->pm_stats.wired_count--; 2025 2026 /* 2027 * Save the REF/CHG bits into their cache if the page is managed. 2028 */ 2029 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2030 struct vm_page *pg; 2031 2032 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2033 if (pg != NULL) { 2034 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2035 (PTE_REF | PTE_CHG)); 2036 } 2037 } 2038 2039 /* 2040 * Remove this PVO from the PV and pmap lists. 2041 */ 2042 LIST_REMOVE(pvo, pvo_vlink); 2043 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2044 2045 /* 2046 * Remove this from the overflow list and return it to the pool 2047 * if we aren't going to reuse it. 2048 */ 2049 LIST_REMOVE(pvo, pvo_olink); 2050 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2051 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2052 moea_upvo_zone, pvo); 2053 moea_pvo_entries--; 2054 moea_pvo_remove_calls++; 2055 } 2056 2057 static __inline int 2058 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2059 { 2060 int pteidx; 2061 2062 /* 2063 * We can find the actual pte entry without searching by grabbing 2064 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2065 * noticing the HID bit. 2066 */ 2067 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2068 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2069 pteidx ^= moea_pteg_mask * 8; 2070 2071 return (pteidx); 2072 } 2073 2074 static struct pvo_entry * 2075 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2076 { 2077 struct pvo_entry *pvo; 2078 int ptegidx; 2079 u_int sr; 2080 2081 va &= ~ADDR_POFF; 2082 sr = va_to_sr(pm->pm_sr, va); 2083 ptegidx = va_to_pteg(sr, va); 2084 2085 mtx_lock(&moea_table_mutex); 2086 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2087 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2088 if (pteidx_p) 2089 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2090 break; 2091 } 2092 } 2093 mtx_unlock(&moea_table_mutex); 2094 2095 return (pvo); 2096 } 2097 2098 static struct pte * 2099 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2100 { 2101 struct pte *pt; 2102 2103 /* 2104 * If we haven't been supplied the ptegidx, calculate it. 2105 */ 2106 if (pteidx == -1) { 2107 int ptegidx; 2108 u_int sr; 2109 2110 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2111 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2112 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2113 } 2114 2115 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2116 mtx_lock(&moea_table_mutex); 2117 2118 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2119 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2120 "valid pte index", pvo); 2121 } 2122 2123 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2124 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2125 "pvo but no valid pte", pvo); 2126 } 2127 2128 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2129 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2130 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2131 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2132 } 2133 2134 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2135 != 0) { 2136 panic("moea_pvo_to_pte: pvo %p pte does not match " 2137 "pte %p in moea_pteg_table", pvo, pt); 2138 } 2139 2140 mtx_assert(&moea_table_mutex, MA_OWNED); 2141 return (pt); 2142 } 2143 2144 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2145 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2146 "moea_pteg_table but valid in pvo", pvo, pt); 2147 } 2148 2149 mtx_unlock(&moea_table_mutex); 2150 return (NULL); 2151 } 2152 2153 /* 2154 * XXX: THIS STUFF SHOULD BE IN pte.c? 2155 */ 2156 int 2157 moea_pte_spill(vm_offset_t addr) 2158 { 2159 struct pvo_entry *source_pvo, *victim_pvo; 2160 struct pvo_entry *pvo; 2161 int ptegidx, i, j; 2162 u_int sr; 2163 struct pteg *pteg; 2164 struct pte *pt; 2165 2166 moea_pte_spills++; 2167 2168 sr = mfsrin(addr); 2169 ptegidx = va_to_pteg(sr, addr); 2170 2171 /* 2172 * Have to substitute some entry. Use the primary hash for this. 2173 * Use low bits of timebase as random generator. 2174 */ 2175 pteg = &moea_pteg_table[ptegidx]; 2176 mtx_lock(&moea_table_mutex); 2177 __asm __volatile("mftb %0" : "=r"(i)); 2178 i &= 7; 2179 pt = &pteg->pt[i]; 2180 2181 source_pvo = NULL; 2182 victim_pvo = NULL; 2183 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2184 /* 2185 * We need to find a pvo entry for this address. 2186 */ 2187 if (source_pvo == NULL && 2188 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2189 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2190 /* 2191 * Now found an entry to be spilled into the pteg. 2192 * The PTE is now valid, so we know it's active. 2193 */ 2194 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2195 2196 if (j >= 0) { 2197 PVO_PTEGIDX_SET(pvo, j); 2198 moea_pte_overflow--; 2199 mtx_unlock(&moea_table_mutex); 2200 return (1); 2201 } 2202 2203 source_pvo = pvo; 2204 2205 if (victim_pvo != NULL) 2206 break; 2207 } 2208 2209 /* 2210 * We also need the pvo entry of the victim we are replacing 2211 * so save the R & C bits of the PTE. 2212 */ 2213 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2214 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2215 victim_pvo = pvo; 2216 if (source_pvo != NULL) 2217 break; 2218 } 2219 } 2220 2221 if (source_pvo == NULL) { 2222 mtx_unlock(&moea_table_mutex); 2223 return (0); 2224 } 2225 2226 if (victim_pvo == NULL) { 2227 if ((pt->pte_hi & PTE_HID) == 0) 2228 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2229 "entry", pt); 2230 2231 /* 2232 * If this is a secondary PTE, we need to search it's primary 2233 * pvo bucket for the matching PVO. 2234 */ 2235 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2236 pvo_olink) { 2237 /* 2238 * We also need the pvo entry of the victim we are 2239 * replacing so save the R & C bits of the PTE. 2240 */ 2241 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2242 victim_pvo = pvo; 2243 break; 2244 } 2245 } 2246 2247 if (victim_pvo == NULL) 2248 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2249 "entry", pt); 2250 } 2251 2252 /* 2253 * We are invalidating the TLB entry for the EA we are replacing even 2254 * though it's valid. If we don't, we lose any ref/chg bit changes 2255 * contained in the TLB entry. 2256 */ 2257 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2258 2259 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2260 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2261 2262 PVO_PTEGIDX_CLR(victim_pvo); 2263 PVO_PTEGIDX_SET(source_pvo, i); 2264 moea_pte_replacements++; 2265 2266 mtx_unlock(&moea_table_mutex); 2267 return (1); 2268 } 2269 2270 static int 2271 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2272 { 2273 struct pte *pt; 2274 int i; 2275 2276 mtx_assert(&moea_table_mutex, MA_OWNED); 2277 2278 /* 2279 * First try primary hash. 2280 */ 2281 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2282 if ((pt->pte_hi & PTE_VALID) == 0) { 2283 pvo_pt->pte_hi &= ~PTE_HID; 2284 moea_pte_set(pt, pvo_pt); 2285 return (i); 2286 } 2287 } 2288 2289 /* 2290 * Now try secondary hash. 2291 */ 2292 ptegidx ^= moea_pteg_mask; 2293 2294 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2295 if ((pt->pte_hi & PTE_VALID) == 0) { 2296 pvo_pt->pte_hi |= PTE_HID; 2297 moea_pte_set(pt, pvo_pt); 2298 return (i); 2299 } 2300 } 2301 2302 panic("moea_pte_insert: overflow"); 2303 return (-1); 2304 } 2305 2306 static boolean_t 2307 moea_query_bit(vm_page_t m, int ptebit) 2308 { 2309 struct pvo_entry *pvo; 2310 struct pte *pt; 2311 2312 rw_assert(&pvh_global_lock, RA_WLOCKED); 2313 if (moea_attr_fetch(m) & ptebit) 2314 return (TRUE); 2315 2316 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2317 2318 /* 2319 * See if we saved the bit off. If so, cache it and return 2320 * success. 2321 */ 2322 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2323 moea_attr_save(m, ptebit); 2324 return (TRUE); 2325 } 2326 } 2327 2328 /* 2329 * No luck, now go through the hard part of looking at the PTEs 2330 * themselves. Sync so that any pending REF/CHG bits are flushed to 2331 * the PTEs. 2332 */ 2333 powerpc_sync(); 2334 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2335 2336 /* 2337 * See if this pvo has a valid PTE. if so, fetch the 2338 * REF/CHG bits from the valid PTE. If the appropriate 2339 * ptebit is set, cache it and return success. 2340 */ 2341 pt = moea_pvo_to_pte(pvo, -1); 2342 if (pt != NULL) { 2343 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2344 mtx_unlock(&moea_table_mutex); 2345 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2346 moea_attr_save(m, ptebit); 2347 return (TRUE); 2348 } 2349 } 2350 } 2351 2352 return (FALSE); 2353 } 2354 2355 static u_int 2356 moea_clear_bit(vm_page_t m, int ptebit) 2357 { 2358 u_int count; 2359 struct pvo_entry *pvo; 2360 struct pte *pt; 2361 2362 rw_assert(&pvh_global_lock, RA_WLOCKED); 2363 2364 /* 2365 * Clear the cached value. 2366 */ 2367 moea_attr_clear(m, ptebit); 2368 2369 /* 2370 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2371 * we can reset the right ones). note that since the pvo entries and 2372 * list heads are accessed via BAT0 and are never placed in the page 2373 * table, we don't have to worry about further accesses setting the 2374 * REF/CHG bits. 2375 */ 2376 powerpc_sync(); 2377 2378 /* 2379 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2380 * valid pte clear the ptebit from the valid pte. 2381 */ 2382 count = 0; 2383 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2384 pt = moea_pvo_to_pte(pvo, -1); 2385 if (pt != NULL) { 2386 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2387 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2388 count++; 2389 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2390 } 2391 mtx_unlock(&moea_table_mutex); 2392 } 2393 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2394 } 2395 2396 return (count); 2397 } 2398 2399 /* 2400 * Return true if the physical range is encompassed by the battable[idx] 2401 */ 2402 static int 2403 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2404 { 2405 u_int prot; 2406 u_int32_t start; 2407 u_int32_t end; 2408 u_int32_t bat_ble; 2409 2410 /* 2411 * Return immediately if not a valid mapping 2412 */ 2413 if (!(battable[idx].batu & BAT_Vs)) 2414 return (EINVAL); 2415 2416 /* 2417 * The BAT entry must be cache-inhibited, guarded, and r/w 2418 * so it can function as an i/o page 2419 */ 2420 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2421 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2422 return (EPERM); 2423 2424 /* 2425 * The address should be within the BAT range. Assume that the 2426 * start address in the BAT has the correct alignment (thus 2427 * not requiring masking) 2428 */ 2429 start = battable[idx].batl & BAT_PBS; 2430 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2431 end = start | (bat_ble << 15) | 0x7fff; 2432 2433 if ((pa < start) || ((pa + size) > end)) 2434 return (ERANGE); 2435 2436 return (0); 2437 } 2438 2439 boolean_t 2440 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2441 { 2442 int i; 2443 2444 /* 2445 * This currently does not work for entries that 2446 * overlap 256M BAT segments. 2447 */ 2448 2449 for(i = 0; i < 16; i++) 2450 if (moea_bat_mapped(i, pa, size) == 0) 2451 return (0); 2452 2453 return (EFAULT); 2454 } 2455 2456 /* 2457 * Map a set of physical memory pages into the kernel virtual 2458 * address space. Return a pointer to where it is mapped. This 2459 * routine is intended to be used for mapping device memory, 2460 * NOT real memory. 2461 */ 2462 void * 2463 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2464 { 2465 2466 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2467 } 2468 2469 void * 2470 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2471 { 2472 vm_offset_t va, tmpva, ppa, offset; 2473 int i; 2474 2475 ppa = trunc_page(pa); 2476 offset = pa & PAGE_MASK; 2477 size = roundup(offset + size, PAGE_SIZE); 2478 2479 /* 2480 * If the physical address lies within a valid BAT table entry, 2481 * return the 1:1 mapping. This currently doesn't work 2482 * for regions that overlap 256M BAT segments. 2483 */ 2484 for (i = 0; i < 16; i++) { 2485 if (moea_bat_mapped(i, pa, size) == 0) 2486 return ((void *) pa); 2487 } 2488 2489 va = kmem_alloc_nofault(kernel_map, size); 2490 if (!va) 2491 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2492 2493 for (tmpva = va; size > 0;) { 2494 moea_kenter_attr(mmu, tmpva, ppa, ma); 2495 tlbie(tmpva); 2496 size -= PAGE_SIZE; 2497 tmpva += PAGE_SIZE; 2498 ppa += PAGE_SIZE; 2499 } 2500 2501 return ((void *)(va + offset)); 2502 } 2503 2504 void 2505 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2506 { 2507 vm_offset_t base, offset; 2508 2509 /* 2510 * If this is outside kernel virtual space, then it's a 2511 * battable entry and doesn't require unmapping 2512 */ 2513 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2514 base = trunc_page(va); 2515 offset = va & PAGE_MASK; 2516 size = roundup(offset + size, PAGE_SIZE); 2517 kmem_free(kernel_map, base, size); 2518 } 2519 } 2520 2521 static void 2522 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2523 { 2524 struct pvo_entry *pvo; 2525 vm_offset_t lim; 2526 vm_paddr_t pa; 2527 vm_size_t len; 2528 2529 PMAP_LOCK(pm); 2530 while (sz > 0) { 2531 lim = round_page(va); 2532 len = MIN(lim - va, sz); 2533 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2534 if (pvo != NULL) { 2535 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2536 (va & ADDR_POFF); 2537 moea_syncicache(pa, len); 2538 } 2539 va += len; 2540 sz -= len; 2541 } 2542 PMAP_UNLOCK(pm); 2543 } 2544