1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/cpu.h> 141 #include <machine/platform.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/smp.h> 148 #include <machine/sr.h> 149 #include <machine/mmuvar.h> 150 #include <machine/trap.h> 151 152 #include "mmu_if.h" 153 154 #define MOEA_DEBUG 155 156 #define TODO panic("%s: not implemented", __func__); 157 158 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 159 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 160 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 161 162 struct ofw_map { 163 vm_offset_t om_va; 164 vm_size_t om_len; 165 vm_offset_t om_pa; 166 u_int om_mode; 167 }; 168 169 extern unsigned char _etext[]; 170 extern unsigned char _end[]; 171 172 /* 173 * Map of physical memory regions. 174 */ 175 static struct mem_region *regions; 176 static struct mem_region *pregions; 177 static u_int phys_avail_count; 178 static int regions_sz, pregions_sz; 179 static struct ofw_map *translations; 180 181 /* 182 * Lock for the pteg and pvo tables. 183 */ 184 struct mtx moea_table_mutex; 185 struct mtx moea_vsid_mutex; 186 187 /* tlbie instruction synchronization */ 188 static struct mtx tlbie_mtx; 189 190 /* 191 * PTEG data. 192 */ 193 static struct pteg *moea_pteg_table; 194 u_int moea_pteg_count; 195 u_int moea_pteg_mask; 196 197 /* 198 * PVO data. 199 */ 200 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 201 struct pvo_head moea_pvo_kunmanaged = 202 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 203 204 static struct rwlock_padalign pvh_global_lock; 205 206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 208 209 #define BPVO_POOL_SIZE 32768 210 static struct pvo_entry *moea_bpvo_pool; 211 static int moea_bpvo_pool_index = 0; 212 213 #define VSID_NBPW (sizeof(u_int32_t) * 8) 214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 215 216 static boolean_t moea_initialized = FALSE; 217 218 /* 219 * Statistics. 220 */ 221 u_int moea_pte_valid = 0; 222 u_int moea_pte_overflow = 0; 223 u_int moea_pte_replacements = 0; 224 u_int moea_pvo_entries = 0; 225 u_int moea_pvo_enter_calls = 0; 226 u_int moea_pvo_remove_calls = 0; 227 u_int moea_pte_spills = 0; 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 229 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 231 &moea_pte_overflow, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 233 &moea_pte_replacements, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 235 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 237 &moea_pvo_enter_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 239 &moea_pvo_remove_calls, 0, ""); 240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 241 &moea_pte_spills, 0, ""); 242 243 /* 244 * Allocate physical memory for use in moea_bootstrap. 245 */ 246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 247 248 /* 249 * PTE calls. 250 */ 251 static int moea_pte_insert(u_int, struct pte *); 252 253 /* 254 * PVO calls. 255 */ 256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 257 vm_offset_t, vm_paddr_t, u_int, int); 258 static void moea_pvo_remove(struct pvo_entry *, int); 259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 261 262 /* 263 * Utility routines. 264 */ 265 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 266 vm_prot_t, u_int, int8_t); 267 static void moea_syncicache(vm_paddr_t, vm_size_t); 268 static boolean_t moea_query_bit(vm_page_t, int); 269 static u_int moea_clear_bit(vm_page_t, int); 270 static void moea_kremove(mmu_t, vm_offset_t); 271 int moea_pte_spill(vm_offset_t); 272 273 /* 274 * Kernel MMU interface 275 */ 276 void moea_clear_modify(mmu_t, vm_page_t); 277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 278 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 279 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 280 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 281 int8_t); 282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 287 void moea_init(mmu_t); 288 boolean_t moea_is_modified(mmu_t, vm_page_t); 289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 boolean_t moea_is_referenced(mmu_t, vm_page_t); 291 int moea_ts_referenced(mmu_t, vm_page_t); 292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 void moea_page_init(mmu_t, vm_page_t); 295 int moea_page_wired_mappings(mmu_t, vm_page_t); 296 void moea_pinit(mmu_t, pmap_t); 297 void moea_pinit0(mmu_t, pmap_t); 298 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 299 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 300 void moea_qremove(mmu_t, vm_offset_t, int); 301 void moea_release(mmu_t, pmap_t); 302 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 303 void moea_remove_all(mmu_t, vm_page_t); 304 void moea_remove_write(mmu_t, vm_page_t); 305 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 306 void moea_zero_page(mmu_t, vm_page_t); 307 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 308 void moea_activate(mmu_t, struct thread *); 309 void moea_deactivate(mmu_t, struct thread *); 310 void moea_cpu_bootstrap(mmu_t, int); 311 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 312 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 313 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 314 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 315 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 316 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 317 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 318 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 319 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 320 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 321 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 322 void moea_scan_init(mmu_t mmu); 323 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 324 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 325 static int moea_map_user_ptr(mmu_t mmu, pmap_t pm, 326 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 327 static int moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 328 int *is_user, vm_offset_t *decoded_addr); 329 330 331 static mmu_method_t moea_methods[] = { 332 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 333 MMUMETHOD(mmu_copy_page, moea_copy_page), 334 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 335 MMUMETHOD(mmu_enter, moea_enter), 336 MMUMETHOD(mmu_enter_object, moea_enter_object), 337 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 338 MMUMETHOD(mmu_extract, moea_extract), 339 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 340 MMUMETHOD(mmu_init, moea_init), 341 MMUMETHOD(mmu_is_modified, moea_is_modified), 342 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 343 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 344 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 345 MMUMETHOD(mmu_map, moea_map), 346 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 347 MMUMETHOD(mmu_page_init, moea_page_init), 348 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 349 MMUMETHOD(mmu_pinit, moea_pinit), 350 MMUMETHOD(mmu_pinit0, moea_pinit0), 351 MMUMETHOD(mmu_protect, moea_protect), 352 MMUMETHOD(mmu_qenter, moea_qenter), 353 MMUMETHOD(mmu_qremove, moea_qremove), 354 MMUMETHOD(mmu_release, moea_release), 355 MMUMETHOD(mmu_remove, moea_remove), 356 MMUMETHOD(mmu_remove_all, moea_remove_all), 357 MMUMETHOD(mmu_remove_write, moea_remove_write), 358 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 359 MMUMETHOD(mmu_unwire, moea_unwire), 360 MMUMETHOD(mmu_zero_page, moea_zero_page), 361 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 362 MMUMETHOD(mmu_activate, moea_activate), 363 MMUMETHOD(mmu_deactivate, moea_deactivate), 364 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 365 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 366 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 370 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 371 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 372 MMUMETHOD(mmu_mapdev, moea_mapdev), 373 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 374 MMUMETHOD(mmu_kextract, moea_kextract), 375 MMUMETHOD(mmu_kenter, moea_kenter), 376 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378 MMUMETHOD(mmu_scan_init, moea_scan_init), 379 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 380 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr), 381 MMUMETHOD(mmu_decode_kernel_ptr, moea_decode_kernel_ptr), 382 383 { 0, 0 } 384 }; 385 386 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 387 388 static __inline uint32_t 389 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 390 { 391 uint32_t pte_lo; 392 int i; 393 394 if (ma != VM_MEMATTR_DEFAULT) { 395 switch (ma) { 396 case VM_MEMATTR_UNCACHEABLE: 397 return (PTE_I | PTE_G); 398 case VM_MEMATTR_CACHEABLE: 399 return (PTE_M); 400 case VM_MEMATTR_WRITE_COMBINING: 401 case VM_MEMATTR_WRITE_BACK: 402 case VM_MEMATTR_PREFETCHABLE: 403 return (PTE_I); 404 case VM_MEMATTR_WRITE_THROUGH: 405 return (PTE_W | PTE_M); 406 } 407 } 408 409 /* 410 * Assume the page is cache inhibited and access is guarded unless 411 * it's in our available memory array. 412 */ 413 pte_lo = PTE_I | PTE_G; 414 for (i = 0; i < pregions_sz; i++) { 415 if ((pa >= pregions[i].mr_start) && 416 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 417 pte_lo = PTE_M; 418 break; 419 } 420 } 421 422 return pte_lo; 423 } 424 425 static void 426 tlbie(vm_offset_t va) 427 { 428 429 mtx_lock_spin(&tlbie_mtx); 430 __asm __volatile("ptesync"); 431 __asm __volatile("tlbie %0" :: "r"(va)); 432 __asm __volatile("eieio; tlbsync; ptesync"); 433 mtx_unlock_spin(&tlbie_mtx); 434 } 435 436 static void 437 tlbia(void) 438 { 439 vm_offset_t va; 440 441 for (va = 0; va < 0x00040000; va += 0x00001000) { 442 __asm __volatile("tlbie %0" :: "r"(va)); 443 powerpc_sync(); 444 } 445 __asm __volatile("tlbsync"); 446 powerpc_sync(); 447 } 448 449 static __inline int 450 va_to_sr(u_int *sr, vm_offset_t va) 451 { 452 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 453 } 454 455 static __inline u_int 456 va_to_pteg(u_int sr, vm_offset_t addr) 457 { 458 u_int hash; 459 460 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 461 ADDR_PIDX_SHFT); 462 return (hash & moea_pteg_mask); 463 } 464 465 static __inline struct pvo_head * 466 vm_page_to_pvoh(vm_page_t m) 467 { 468 469 return (&m->md.mdpg_pvoh); 470 } 471 472 static __inline void 473 moea_attr_clear(vm_page_t m, int ptebit) 474 { 475 476 rw_assert(&pvh_global_lock, RA_WLOCKED); 477 m->md.mdpg_attrs &= ~ptebit; 478 } 479 480 static __inline int 481 moea_attr_fetch(vm_page_t m) 482 { 483 484 return (m->md.mdpg_attrs); 485 } 486 487 static __inline void 488 moea_attr_save(vm_page_t m, int ptebit) 489 { 490 491 rw_assert(&pvh_global_lock, RA_WLOCKED); 492 m->md.mdpg_attrs |= ptebit; 493 } 494 495 static __inline int 496 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 497 { 498 if (pt->pte_hi == pvo_pt->pte_hi) 499 return (1); 500 501 return (0); 502 } 503 504 static __inline int 505 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 506 { 507 return (pt->pte_hi & ~PTE_VALID) == 508 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 509 ((va >> ADDR_API_SHFT) & PTE_API) | which); 510 } 511 512 static __inline void 513 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 514 { 515 516 mtx_assert(&moea_table_mutex, MA_OWNED); 517 518 /* 519 * Construct a PTE. Default to IMB initially. Valid bit only gets 520 * set when the real pte is set in memory. 521 * 522 * Note: Don't set the valid bit for correct operation of tlb update. 523 */ 524 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 525 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 526 pt->pte_lo = pte_lo; 527 } 528 529 static __inline void 530 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 531 { 532 533 mtx_assert(&moea_table_mutex, MA_OWNED); 534 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 535 } 536 537 static __inline void 538 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 539 { 540 541 mtx_assert(&moea_table_mutex, MA_OWNED); 542 543 /* 544 * As shown in Section 7.6.3.2.3 545 */ 546 pt->pte_lo &= ~ptebit; 547 tlbie(va); 548 } 549 550 static __inline void 551 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 552 { 553 554 mtx_assert(&moea_table_mutex, MA_OWNED); 555 pvo_pt->pte_hi |= PTE_VALID; 556 557 /* 558 * Update the PTE as defined in section 7.6.3.1. 559 * Note that the REF/CHG bits are from pvo_pt and thus should have 560 * been saved so this routine can restore them (if desired). 561 */ 562 pt->pte_lo = pvo_pt->pte_lo; 563 powerpc_sync(); 564 pt->pte_hi = pvo_pt->pte_hi; 565 powerpc_sync(); 566 moea_pte_valid++; 567 } 568 569 static __inline void 570 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 571 { 572 573 mtx_assert(&moea_table_mutex, MA_OWNED); 574 pvo_pt->pte_hi &= ~PTE_VALID; 575 576 /* 577 * Force the reg & chg bits back into the PTEs. 578 */ 579 powerpc_sync(); 580 581 /* 582 * Invalidate the pte. 583 */ 584 pt->pte_hi &= ~PTE_VALID; 585 586 tlbie(va); 587 588 /* 589 * Save the reg & chg bits. 590 */ 591 moea_pte_synch(pt, pvo_pt); 592 moea_pte_valid--; 593 } 594 595 static __inline void 596 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 597 { 598 599 /* 600 * Invalidate the PTE 601 */ 602 moea_pte_unset(pt, pvo_pt, va); 603 moea_pte_set(pt, pvo_pt); 604 } 605 606 /* 607 * Quick sort callout for comparing memory regions. 608 */ 609 static int om_cmp(const void *a, const void *b); 610 611 static int 612 om_cmp(const void *a, const void *b) 613 { 614 const struct ofw_map *mapa; 615 const struct ofw_map *mapb; 616 617 mapa = a; 618 mapb = b; 619 if (mapa->om_pa < mapb->om_pa) 620 return (-1); 621 else if (mapa->om_pa > mapb->om_pa) 622 return (1); 623 else 624 return (0); 625 } 626 627 void 628 moea_cpu_bootstrap(mmu_t mmup, int ap) 629 { 630 u_int sdr; 631 int i; 632 633 if (ap) { 634 powerpc_sync(); 635 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 636 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 637 isync(); 638 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 639 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 640 isync(); 641 } 642 643 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 644 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 645 isync(); 646 647 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 648 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 649 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 650 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 651 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 652 isync(); 653 654 for (i = 0; i < 16; i++) 655 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 656 powerpc_sync(); 657 658 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 659 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 660 isync(); 661 662 tlbia(); 663 } 664 665 void 666 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 667 { 668 ihandle_t mmui; 669 phandle_t chosen, mmu; 670 int sz; 671 int i, j; 672 vm_size_t size, physsz, hwphyssz; 673 vm_offset_t pa, va, off; 674 void *dpcpu; 675 register_t msr; 676 677 /* 678 * Set up BAT0 to map the lowest 256 MB area 679 */ 680 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 681 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 682 683 /* 684 * Map PCI memory space. 685 */ 686 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 687 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 688 689 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 690 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 691 692 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 693 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 694 695 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 696 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 697 698 /* 699 * Map obio devices. 700 */ 701 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 702 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 703 704 /* 705 * Use an IBAT and a DBAT to map the bottom segment of memory 706 * where we are. Turn off instruction relocation temporarily 707 * to prevent faults while reprogramming the IBAT. 708 */ 709 msr = mfmsr(); 710 mtmsr(msr & ~PSL_IR); 711 __asm (".balign 32; \n" 712 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 713 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 714 :: "r"(battable[0].batu), "r"(battable[0].batl)); 715 mtmsr(msr); 716 717 /* map pci space */ 718 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 719 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 720 isync(); 721 722 /* set global direct map flag */ 723 hw_direct_map = 1; 724 725 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 726 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 727 728 for (i = 0; i < pregions_sz; i++) { 729 vm_offset_t pa; 730 vm_offset_t end; 731 732 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 733 pregions[i].mr_start, 734 pregions[i].mr_start + pregions[i].mr_size, 735 pregions[i].mr_size); 736 /* 737 * Install entries into the BAT table to allow all 738 * of physmem to be convered by on-demand BAT entries. 739 * The loop will sometimes set the same battable element 740 * twice, but that's fine since they won't be used for 741 * a while yet. 742 */ 743 pa = pregions[i].mr_start & 0xf0000000; 744 end = pregions[i].mr_start + pregions[i].mr_size; 745 do { 746 u_int n = pa >> ADDR_SR_SHFT; 747 748 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 749 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 750 pa += SEGMENT_LENGTH; 751 } while (pa < end); 752 } 753 754 if (PHYS_AVAIL_ENTRIES < regions_sz) 755 panic("moea_bootstrap: phys_avail too small"); 756 757 phys_avail_count = 0; 758 physsz = 0; 759 hwphyssz = 0; 760 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 761 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 762 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 763 regions[i].mr_start + regions[i].mr_size, 764 regions[i].mr_size); 765 if (hwphyssz != 0 && 766 (physsz + regions[i].mr_size) >= hwphyssz) { 767 if (physsz < hwphyssz) { 768 phys_avail[j] = regions[i].mr_start; 769 phys_avail[j + 1] = regions[i].mr_start + 770 hwphyssz - physsz; 771 physsz = hwphyssz; 772 phys_avail_count++; 773 } 774 break; 775 } 776 phys_avail[j] = regions[i].mr_start; 777 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 778 phys_avail_count++; 779 physsz += regions[i].mr_size; 780 } 781 782 /* Check for overlap with the kernel and exception vectors */ 783 for (j = 0; j < 2*phys_avail_count; j+=2) { 784 if (phys_avail[j] < EXC_LAST) 785 phys_avail[j] += EXC_LAST; 786 787 if (kernelstart >= phys_avail[j] && 788 kernelstart < phys_avail[j+1]) { 789 if (kernelend < phys_avail[j+1]) { 790 phys_avail[2*phys_avail_count] = 791 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 phys_avail[2*phys_avail_count + 1] = 793 phys_avail[j+1]; 794 phys_avail_count++; 795 } 796 797 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 798 } 799 800 if (kernelend >= phys_avail[j] && 801 kernelend < phys_avail[j+1]) { 802 if (kernelstart > phys_avail[j]) { 803 phys_avail[2*phys_avail_count] = phys_avail[j]; 804 phys_avail[2*phys_avail_count + 1] = 805 kernelstart & ~PAGE_MASK; 806 phys_avail_count++; 807 } 808 809 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 810 } 811 } 812 813 physmem = btoc(physsz); 814 815 /* 816 * Allocate PTEG table. 817 */ 818 #ifdef PTEGCOUNT 819 moea_pteg_count = PTEGCOUNT; 820 #else 821 moea_pteg_count = 0x1000; 822 823 while (moea_pteg_count < physmem) 824 moea_pteg_count <<= 1; 825 826 moea_pteg_count >>= 1; 827 #endif /* PTEGCOUNT */ 828 829 size = moea_pteg_count * sizeof(struct pteg); 830 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 831 size); 832 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 833 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 834 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 835 moea_pteg_mask = moea_pteg_count - 1; 836 837 /* 838 * Allocate pv/overflow lists. 839 */ 840 size = sizeof(struct pvo_head) * moea_pteg_count; 841 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 842 PAGE_SIZE); 843 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 844 for (i = 0; i < moea_pteg_count; i++) 845 LIST_INIT(&moea_pvo_table[i]); 846 847 /* 848 * Initialize the lock that synchronizes access to the pteg and pvo 849 * tables. 850 */ 851 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 852 MTX_RECURSE); 853 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 854 855 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 856 857 /* 858 * Initialise the unmanaged pvo pool. 859 */ 860 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 861 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 862 moea_bpvo_pool_index = 0; 863 864 /* 865 * Make sure kernel vsid is allocated as well as VSID 0. 866 */ 867 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 868 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 869 moea_vsid_bitmap[0] |= 1; 870 871 /* 872 * Initialize the kernel pmap (which is statically allocated). 873 */ 874 PMAP_LOCK_INIT(kernel_pmap); 875 for (i = 0; i < 16; i++) 876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 877 CPU_FILL(&kernel_pmap->pm_active); 878 RB_INIT(&kernel_pmap->pmap_pvo); 879 880 /* 881 * Initialize the global pv list lock. 882 */ 883 rw_init(&pvh_global_lock, "pmap pv global"); 884 885 /* 886 * Set up the Open Firmware mappings 887 */ 888 chosen = OF_finddevice("/chosen"); 889 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 890 (mmu = OF_instance_to_package(mmui)) != -1 && 891 (sz = OF_getproplen(mmu, "translations")) != -1) { 892 translations = NULL; 893 for (i = 0; phys_avail[i] != 0; i += 2) { 894 if (phys_avail[i + 1] >= sz) { 895 translations = (struct ofw_map *)phys_avail[i]; 896 break; 897 } 898 } 899 if (translations == NULL) 900 panic("moea_bootstrap: no space to copy translations"); 901 bzero(translations, sz); 902 if (OF_getprop(mmu, "translations", translations, sz) == -1) 903 panic("moea_bootstrap: can't get ofw translations"); 904 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 905 sz /= sizeof(*translations); 906 qsort(translations, sz, sizeof (*translations), om_cmp); 907 for (i = 0; i < sz; i++) { 908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 909 translations[i].om_pa, translations[i].om_va, 910 translations[i].om_len); 911 912 /* 913 * If the mapping is 1:1, let the RAM and device 914 * on-demand BAT tables take care of the translation. 915 */ 916 if (translations[i].om_va == translations[i].om_pa) 917 continue; 918 919 /* Enter the pages */ 920 for (off = 0; off < translations[i].om_len; 921 off += PAGE_SIZE) 922 moea_kenter(mmup, translations[i].om_va + off, 923 translations[i].om_pa + off); 924 } 925 } 926 927 /* 928 * Calculate the last available physical address. 929 */ 930 for (i = 0; phys_avail[i + 2] != 0; i += 2) 931 ; 932 Maxmem = powerpc_btop(phys_avail[i + 1]); 933 934 moea_cpu_bootstrap(mmup,0); 935 mtmsr(mfmsr() | PSL_DR | PSL_IR); 936 pmap_bootstrapped++; 937 938 /* 939 * Set the start and end of kva. 940 */ 941 virtual_avail = VM_MIN_KERNEL_ADDRESS; 942 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 943 944 /* 945 * Allocate a kernel stack with a guard page for thread0 and map it 946 * into the kernel page map. 947 */ 948 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 949 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 950 virtual_avail = va + kstack_pages * PAGE_SIZE; 951 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 952 thread0.td_kstack = va; 953 thread0.td_kstack_pages = kstack_pages; 954 for (i = 0; i < kstack_pages; i++) { 955 moea_kenter(mmup, va, pa); 956 pa += PAGE_SIZE; 957 va += PAGE_SIZE; 958 } 959 960 /* 961 * Allocate virtual address space for the message buffer. 962 */ 963 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 964 msgbufp = (struct msgbuf *)virtual_avail; 965 va = virtual_avail; 966 virtual_avail += round_page(msgbufsize); 967 while (va < virtual_avail) { 968 moea_kenter(mmup, va, pa); 969 pa += PAGE_SIZE; 970 va += PAGE_SIZE; 971 } 972 973 /* 974 * Allocate virtual address space for the dynamic percpu area. 975 */ 976 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 977 dpcpu = (void *)virtual_avail; 978 va = virtual_avail; 979 virtual_avail += DPCPU_SIZE; 980 while (va < virtual_avail) { 981 moea_kenter(mmup, va, pa); 982 pa += PAGE_SIZE; 983 va += PAGE_SIZE; 984 } 985 dpcpu_init(dpcpu, 0); 986 } 987 988 /* 989 * Activate a user pmap. The pmap must be activated before it's address 990 * space can be accessed in any way. 991 */ 992 void 993 moea_activate(mmu_t mmu, struct thread *td) 994 { 995 pmap_t pm, pmr; 996 997 /* 998 * Load all the data we need up front to encourage the compiler to 999 * not issue any loads while we have interrupts disabled below. 1000 */ 1001 pm = &td->td_proc->p_vmspace->vm_pmap; 1002 pmr = pm->pmap_phys; 1003 1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1005 PCPU_SET(curpmap, pmr); 1006 1007 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1008 } 1009 1010 void 1011 moea_deactivate(mmu_t mmu, struct thread *td) 1012 { 1013 pmap_t pm; 1014 1015 pm = &td->td_proc->p_vmspace->vm_pmap; 1016 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1017 PCPU_SET(curpmap, NULL); 1018 } 1019 1020 void 1021 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1022 { 1023 struct pvo_entry key, *pvo; 1024 1025 PMAP_LOCK(pm); 1026 key.pvo_vaddr = sva; 1027 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1028 pvo != NULL && PVO_VADDR(pvo) < eva; 1029 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1030 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1031 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1032 pvo->pvo_vaddr &= ~PVO_WIRED; 1033 pm->pm_stats.wired_count--; 1034 } 1035 PMAP_UNLOCK(pm); 1036 } 1037 1038 void 1039 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1040 { 1041 vm_offset_t dst; 1042 vm_offset_t src; 1043 1044 dst = VM_PAGE_TO_PHYS(mdst); 1045 src = VM_PAGE_TO_PHYS(msrc); 1046 1047 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1048 } 1049 1050 void 1051 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1052 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1053 { 1054 void *a_cp, *b_cp; 1055 vm_offset_t a_pg_offset, b_pg_offset; 1056 int cnt; 1057 1058 while (xfersize > 0) { 1059 a_pg_offset = a_offset & PAGE_MASK; 1060 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1061 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1062 a_pg_offset; 1063 b_pg_offset = b_offset & PAGE_MASK; 1064 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1065 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1066 b_pg_offset; 1067 bcopy(a_cp, b_cp, cnt); 1068 a_offset += cnt; 1069 b_offset += cnt; 1070 xfersize -= cnt; 1071 } 1072 } 1073 1074 /* 1075 * Zero a page of physical memory by temporarily mapping it into the tlb. 1076 */ 1077 void 1078 moea_zero_page(mmu_t mmu, vm_page_t m) 1079 { 1080 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1081 1082 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1083 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1084 } 1085 1086 void 1087 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1088 { 1089 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1090 void *va = (void *)(pa + off); 1091 1092 bzero(va, size); 1093 } 1094 1095 vm_offset_t 1096 moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1097 { 1098 1099 return (VM_PAGE_TO_PHYS(m)); 1100 } 1101 1102 void 1103 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1104 { 1105 } 1106 1107 /* 1108 * Map the given physical page at the specified virtual address in the 1109 * target pmap with the protection requested. If specified the page 1110 * will be wired down. 1111 */ 1112 int 1113 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1114 u_int flags, int8_t psind) 1115 { 1116 int error; 1117 1118 for (;;) { 1119 rw_wlock(&pvh_global_lock); 1120 PMAP_LOCK(pmap); 1121 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1122 rw_wunlock(&pvh_global_lock); 1123 PMAP_UNLOCK(pmap); 1124 if (error != ENOMEM) 1125 return (KERN_SUCCESS); 1126 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1127 return (KERN_RESOURCE_SHORTAGE); 1128 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1129 vm_wait(NULL); 1130 } 1131 } 1132 1133 /* 1134 * Map the given physical page at the specified virtual address in the 1135 * target pmap with the protection requested. If specified the page 1136 * will be wired down. 1137 * 1138 * The global pvh and pmap must be locked. 1139 */ 1140 static int 1141 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1142 u_int flags, int8_t psind __unused) 1143 { 1144 struct pvo_head *pvo_head; 1145 uma_zone_t zone; 1146 u_int pte_lo, pvo_flags; 1147 int error; 1148 1149 if (pmap_bootstrapped) 1150 rw_assert(&pvh_global_lock, RA_WLOCKED); 1151 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1152 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1153 VM_OBJECT_ASSERT_LOCKED(m->object); 1154 1155 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1156 pvo_head = &moea_pvo_kunmanaged; 1157 zone = moea_upvo_zone; 1158 pvo_flags = 0; 1159 } else { 1160 pvo_head = vm_page_to_pvoh(m); 1161 zone = moea_mpvo_zone; 1162 pvo_flags = PVO_MANAGED; 1163 } 1164 1165 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1166 1167 if (prot & VM_PROT_WRITE) { 1168 pte_lo |= PTE_BW; 1169 if (pmap_bootstrapped && 1170 (m->oflags & VPO_UNMANAGED) == 0) 1171 vm_page_aflag_set(m, PGA_WRITEABLE); 1172 } else 1173 pte_lo |= PTE_BR; 1174 1175 if ((flags & PMAP_ENTER_WIRED) != 0) 1176 pvo_flags |= PVO_WIRED; 1177 1178 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1179 pte_lo, pvo_flags); 1180 1181 /* 1182 * Flush the real page from the instruction cache. This has be done 1183 * for all user mappings to prevent information leakage via the 1184 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1185 * mapping for a page. 1186 */ 1187 if (pmap != kernel_pmap && error == ENOENT && 1188 (pte_lo & (PTE_I | PTE_G)) == 0) 1189 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1190 1191 return (error); 1192 } 1193 1194 /* 1195 * Maps a sequence of resident pages belonging to the same object. 1196 * The sequence begins with the given page m_start. This page is 1197 * mapped at the given virtual address start. Each subsequent page is 1198 * mapped at a virtual address that is offset from start by the same 1199 * amount as the page is offset from m_start within the object. The 1200 * last page in the sequence is the page with the largest offset from 1201 * m_start that can be mapped at a virtual address less than the given 1202 * virtual address end. Not every virtual page between start and end 1203 * is mapped; only those for which a resident page exists with the 1204 * corresponding offset from m_start are mapped. 1205 */ 1206 void 1207 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1208 vm_page_t m_start, vm_prot_t prot) 1209 { 1210 vm_page_t m; 1211 vm_pindex_t diff, psize; 1212 1213 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1214 1215 psize = atop(end - start); 1216 m = m_start; 1217 rw_wlock(&pvh_global_lock); 1218 PMAP_LOCK(pm); 1219 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1220 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1221 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1222 m = TAILQ_NEXT(m, listq); 1223 } 1224 rw_wunlock(&pvh_global_lock); 1225 PMAP_UNLOCK(pm); 1226 } 1227 1228 void 1229 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1230 vm_prot_t prot) 1231 { 1232 1233 rw_wlock(&pvh_global_lock); 1234 PMAP_LOCK(pm); 1235 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1236 0, 0); 1237 rw_wunlock(&pvh_global_lock); 1238 PMAP_UNLOCK(pm); 1239 } 1240 1241 vm_paddr_t 1242 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1243 { 1244 struct pvo_entry *pvo; 1245 vm_paddr_t pa; 1246 1247 PMAP_LOCK(pm); 1248 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1249 if (pvo == NULL) 1250 pa = 0; 1251 else 1252 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1253 PMAP_UNLOCK(pm); 1254 return (pa); 1255 } 1256 1257 /* 1258 * Atomically extract and hold the physical page with the given 1259 * pmap and virtual address pair if that mapping permits the given 1260 * protection. 1261 */ 1262 vm_page_t 1263 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1264 { 1265 struct pvo_entry *pvo; 1266 vm_page_t m; 1267 vm_paddr_t pa; 1268 1269 m = NULL; 1270 pa = 0; 1271 PMAP_LOCK(pmap); 1272 retry: 1273 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1274 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1275 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1276 (prot & VM_PROT_WRITE) == 0)) { 1277 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1278 goto retry; 1279 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1280 vm_page_wire(m); 1281 } 1282 PA_UNLOCK_COND(pa); 1283 PMAP_UNLOCK(pmap); 1284 return (m); 1285 } 1286 1287 void 1288 moea_init(mmu_t mmu) 1289 { 1290 1291 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1292 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1293 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1294 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1295 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1296 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1297 moea_initialized = TRUE; 1298 } 1299 1300 boolean_t 1301 moea_is_referenced(mmu_t mmu, vm_page_t m) 1302 { 1303 boolean_t rv; 1304 1305 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1306 ("moea_is_referenced: page %p is not managed", m)); 1307 rw_wlock(&pvh_global_lock); 1308 rv = moea_query_bit(m, PTE_REF); 1309 rw_wunlock(&pvh_global_lock); 1310 return (rv); 1311 } 1312 1313 boolean_t 1314 moea_is_modified(mmu_t mmu, vm_page_t m) 1315 { 1316 boolean_t rv; 1317 1318 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1319 ("moea_is_modified: page %p is not managed", m)); 1320 1321 /* 1322 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1323 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1324 * is clear, no PTEs can have PTE_CHG set. 1325 */ 1326 VM_OBJECT_ASSERT_WLOCKED(m->object); 1327 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1328 return (FALSE); 1329 rw_wlock(&pvh_global_lock); 1330 rv = moea_query_bit(m, PTE_CHG); 1331 rw_wunlock(&pvh_global_lock); 1332 return (rv); 1333 } 1334 1335 boolean_t 1336 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1337 { 1338 struct pvo_entry *pvo; 1339 boolean_t rv; 1340 1341 PMAP_LOCK(pmap); 1342 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1343 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1344 PMAP_UNLOCK(pmap); 1345 return (rv); 1346 } 1347 1348 void 1349 moea_clear_modify(mmu_t mmu, vm_page_t m) 1350 { 1351 1352 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1353 ("moea_clear_modify: page %p is not managed", m)); 1354 VM_OBJECT_ASSERT_WLOCKED(m->object); 1355 KASSERT(!vm_page_xbusied(m), 1356 ("moea_clear_modify: page %p is exclusive busy", m)); 1357 1358 /* 1359 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1360 * set. If the object containing the page is locked and the page is 1361 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1362 */ 1363 if ((m->aflags & PGA_WRITEABLE) == 0) 1364 return; 1365 rw_wlock(&pvh_global_lock); 1366 moea_clear_bit(m, PTE_CHG); 1367 rw_wunlock(&pvh_global_lock); 1368 } 1369 1370 /* 1371 * Clear the write and modified bits in each of the given page's mappings. 1372 */ 1373 void 1374 moea_remove_write(mmu_t mmu, vm_page_t m) 1375 { 1376 struct pvo_entry *pvo; 1377 struct pte *pt; 1378 pmap_t pmap; 1379 u_int lo; 1380 1381 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1382 ("moea_remove_write: page %p is not managed", m)); 1383 1384 /* 1385 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1386 * set by another thread while the object is locked. Thus, 1387 * if PGA_WRITEABLE is clear, no page table entries need updating. 1388 */ 1389 VM_OBJECT_ASSERT_WLOCKED(m->object); 1390 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1391 return; 1392 rw_wlock(&pvh_global_lock); 1393 lo = moea_attr_fetch(m); 1394 powerpc_sync(); 1395 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1396 pmap = pvo->pvo_pmap; 1397 PMAP_LOCK(pmap); 1398 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1399 pt = moea_pvo_to_pte(pvo, -1); 1400 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1401 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1402 if (pt != NULL) { 1403 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1404 lo |= pvo->pvo_pte.pte.pte_lo; 1405 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1406 moea_pte_change(pt, &pvo->pvo_pte.pte, 1407 pvo->pvo_vaddr); 1408 mtx_unlock(&moea_table_mutex); 1409 } 1410 } 1411 PMAP_UNLOCK(pmap); 1412 } 1413 if ((lo & PTE_CHG) != 0) { 1414 moea_attr_clear(m, PTE_CHG); 1415 vm_page_dirty(m); 1416 } 1417 vm_page_aflag_clear(m, PGA_WRITEABLE); 1418 rw_wunlock(&pvh_global_lock); 1419 } 1420 1421 /* 1422 * moea_ts_referenced: 1423 * 1424 * Return a count of reference bits for a page, clearing those bits. 1425 * It is not necessary for every reference bit to be cleared, but it 1426 * is necessary that 0 only be returned when there are truly no 1427 * reference bits set. 1428 * 1429 * XXX: The exact number of bits to check and clear is a matter that 1430 * should be tested and standardized at some point in the future for 1431 * optimal aging of shared pages. 1432 */ 1433 int 1434 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1435 { 1436 int count; 1437 1438 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1439 ("moea_ts_referenced: page %p is not managed", m)); 1440 rw_wlock(&pvh_global_lock); 1441 count = moea_clear_bit(m, PTE_REF); 1442 rw_wunlock(&pvh_global_lock); 1443 return (count); 1444 } 1445 1446 /* 1447 * Modify the WIMG settings of all mappings for a page. 1448 */ 1449 void 1450 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1451 { 1452 struct pvo_entry *pvo; 1453 struct pvo_head *pvo_head; 1454 struct pte *pt; 1455 pmap_t pmap; 1456 u_int lo; 1457 1458 if ((m->oflags & VPO_UNMANAGED) != 0) { 1459 m->md.mdpg_cache_attrs = ma; 1460 return; 1461 } 1462 1463 rw_wlock(&pvh_global_lock); 1464 pvo_head = vm_page_to_pvoh(m); 1465 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1466 1467 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1468 pmap = pvo->pvo_pmap; 1469 PMAP_LOCK(pmap); 1470 pt = moea_pvo_to_pte(pvo, -1); 1471 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1472 pvo->pvo_pte.pte.pte_lo |= lo; 1473 if (pt != NULL) { 1474 moea_pte_change(pt, &pvo->pvo_pte.pte, 1475 pvo->pvo_vaddr); 1476 if (pvo->pvo_pmap == kernel_pmap) 1477 isync(); 1478 } 1479 mtx_unlock(&moea_table_mutex); 1480 PMAP_UNLOCK(pmap); 1481 } 1482 m->md.mdpg_cache_attrs = ma; 1483 rw_wunlock(&pvh_global_lock); 1484 } 1485 1486 /* 1487 * Map a wired page into kernel virtual address space. 1488 */ 1489 void 1490 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1491 { 1492 1493 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1494 } 1495 1496 void 1497 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1498 { 1499 u_int pte_lo; 1500 int error; 1501 1502 #if 0 1503 if (va < VM_MIN_KERNEL_ADDRESS) 1504 panic("moea_kenter: attempt to enter non-kernel address %#x", 1505 va); 1506 #endif 1507 1508 pte_lo = moea_calc_wimg(pa, ma); 1509 1510 PMAP_LOCK(kernel_pmap); 1511 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1512 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1513 1514 if (error != 0 && error != ENOENT) 1515 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1516 pa, error); 1517 1518 PMAP_UNLOCK(kernel_pmap); 1519 } 1520 1521 /* 1522 * Extract the physical page address associated with the given kernel virtual 1523 * address. 1524 */ 1525 vm_paddr_t 1526 moea_kextract(mmu_t mmu, vm_offset_t va) 1527 { 1528 struct pvo_entry *pvo; 1529 vm_paddr_t pa; 1530 1531 /* 1532 * Allow direct mappings on 32-bit OEA 1533 */ 1534 if (va < VM_MIN_KERNEL_ADDRESS) { 1535 return (va); 1536 } 1537 1538 PMAP_LOCK(kernel_pmap); 1539 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1540 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1541 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1542 PMAP_UNLOCK(kernel_pmap); 1543 return (pa); 1544 } 1545 1546 /* 1547 * Remove a wired page from kernel virtual address space. 1548 */ 1549 void 1550 moea_kremove(mmu_t mmu, vm_offset_t va) 1551 { 1552 1553 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1554 } 1555 1556 /* 1557 * Provide a kernel pointer corresponding to a given userland pointer. 1558 * The returned pointer is valid until the next time this function is 1559 * called in this thread. This is used internally in copyin/copyout. 1560 */ 1561 int 1562 moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1563 void **kaddr, size_t ulen, size_t *klen) 1564 { 1565 size_t l; 1566 register_t vsid; 1567 1568 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1569 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1570 if (l > ulen) 1571 l = ulen; 1572 if (klen) 1573 *klen = l; 1574 else if (l != ulen) 1575 return (EFAULT); 1576 1577 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1578 1579 /* Mark segment no-execute */ 1580 vsid |= SR_N; 1581 1582 /* If we have already set this VSID, we can just return */ 1583 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1584 return (0); 1585 1586 __asm __volatile("isync"); 1587 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1588 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1589 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1590 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1591 1592 return (0); 1593 } 1594 1595 /* 1596 * Figure out where a given kernel pointer (usually in a fault) points 1597 * to from the VM's perspective, potentially remapping into userland's 1598 * address space. 1599 */ 1600 static int 1601 moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1602 vm_offset_t *decoded_addr) 1603 { 1604 vm_offset_t user_sr; 1605 1606 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1607 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1608 addr &= ADDR_PIDX | ADDR_POFF; 1609 addr |= user_sr << ADDR_SR_SHFT; 1610 *decoded_addr = addr; 1611 *is_user = 1; 1612 } else { 1613 *decoded_addr = addr; 1614 *is_user = 0; 1615 } 1616 1617 return (0); 1618 } 1619 1620 /* 1621 * Map a range of physical addresses into kernel virtual address space. 1622 * 1623 * The value passed in *virt is a suggested virtual address for the mapping. 1624 * Architectures which can support a direct-mapped physical to virtual region 1625 * can return the appropriate address within that region, leaving '*virt' 1626 * unchanged. We cannot and therefore do not; *virt is updated with the 1627 * first usable address after the mapped region. 1628 */ 1629 vm_offset_t 1630 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1631 vm_paddr_t pa_end, int prot) 1632 { 1633 vm_offset_t sva, va; 1634 1635 sva = *virt; 1636 va = sva; 1637 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1638 moea_kenter(mmu, va, pa_start); 1639 *virt = va; 1640 return (sva); 1641 } 1642 1643 /* 1644 * Returns true if the pmap's pv is one of the first 1645 * 16 pvs linked to from this page. This count may 1646 * be changed upwards or downwards in the future; it 1647 * is only necessary that true be returned for a small 1648 * subset of pmaps for proper page aging. 1649 */ 1650 boolean_t 1651 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1652 { 1653 int loops; 1654 struct pvo_entry *pvo; 1655 boolean_t rv; 1656 1657 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1658 ("moea_page_exists_quick: page %p is not managed", m)); 1659 loops = 0; 1660 rv = FALSE; 1661 rw_wlock(&pvh_global_lock); 1662 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1663 if (pvo->pvo_pmap == pmap) { 1664 rv = TRUE; 1665 break; 1666 } 1667 if (++loops >= 16) 1668 break; 1669 } 1670 rw_wunlock(&pvh_global_lock); 1671 return (rv); 1672 } 1673 1674 void 1675 moea_page_init(mmu_t mmu __unused, vm_page_t m) 1676 { 1677 1678 m->md.mdpg_attrs = 0; 1679 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1680 LIST_INIT(&m->md.mdpg_pvoh); 1681 } 1682 1683 /* 1684 * Return the number of managed mappings to the given physical page 1685 * that are wired. 1686 */ 1687 int 1688 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1689 { 1690 struct pvo_entry *pvo; 1691 int count; 1692 1693 count = 0; 1694 if ((m->oflags & VPO_UNMANAGED) != 0) 1695 return (count); 1696 rw_wlock(&pvh_global_lock); 1697 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1698 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1699 count++; 1700 rw_wunlock(&pvh_global_lock); 1701 return (count); 1702 } 1703 1704 static u_int moea_vsidcontext; 1705 1706 void 1707 moea_pinit(mmu_t mmu, pmap_t pmap) 1708 { 1709 int i, mask; 1710 u_int entropy; 1711 1712 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1713 RB_INIT(&pmap->pmap_pvo); 1714 1715 entropy = 0; 1716 __asm __volatile("mftb %0" : "=r"(entropy)); 1717 1718 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1719 == NULL) { 1720 pmap->pmap_phys = pmap; 1721 } 1722 1723 1724 mtx_lock(&moea_vsid_mutex); 1725 /* 1726 * Allocate some segment registers for this pmap. 1727 */ 1728 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1729 u_int hash, n; 1730 1731 /* 1732 * Create a new value by mutiplying by a prime and adding in 1733 * entropy from the timebase register. This is to make the 1734 * VSID more random so that the PT hash function collides 1735 * less often. (Note that the prime casues gcc to do shifts 1736 * instead of a multiply.) 1737 */ 1738 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1739 hash = moea_vsidcontext & (NPMAPS - 1); 1740 if (hash == 0) /* 0 is special, avoid it */ 1741 continue; 1742 n = hash >> 5; 1743 mask = 1 << (hash & (VSID_NBPW - 1)); 1744 hash = (moea_vsidcontext & 0xfffff); 1745 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1746 /* anything free in this bucket? */ 1747 if (moea_vsid_bitmap[n] == 0xffffffff) { 1748 entropy = (moea_vsidcontext >> 20); 1749 continue; 1750 } 1751 i = ffs(~moea_vsid_bitmap[n]) - 1; 1752 mask = 1 << i; 1753 hash &= rounddown2(0xfffff, VSID_NBPW); 1754 hash |= i; 1755 } 1756 KASSERT(!(moea_vsid_bitmap[n] & mask), 1757 ("Allocating in-use VSID group %#x\n", hash)); 1758 moea_vsid_bitmap[n] |= mask; 1759 for (i = 0; i < 16; i++) 1760 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1761 mtx_unlock(&moea_vsid_mutex); 1762 return; 1763 } 1764 1765 mtx_unlock(&moea_vsid_mutex); 1766 panic("moea_pinit: out of segments"); 1767 } 1768 1769 /* 1770 * Initialize the pmap associated with process 0. 1771 */ 1772 void 1773 moea_pinit0(mmu_t mmu, pmap_t pm) 1774 { 1775 1776 PMAP_LOCK_INIT(pm); 1777 moea_pinit(mmu, pm); 1778 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1779 } 1780 1781 /* 1782 * Set the physical protection on the specified range of this map as requested. 1783 */ 1784 void 1785 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1786 vm_prot_t prot) 1787 { 1788 struct pvo_entry *pvo, *tpvo, key; 1789 struct pte *pt; 1790 1791 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1792 ("moea_protect: non current pmap")); 1793 1794 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1795 moea_remove(mmu, pm, sva, eva); 1796 return; 1797 } 1798 1799 rw_wlock(&pvh_global_lock); 1800 PMAP_LOCK(pm); 1801 key.pvo_vaddr = sva; 1802 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1803 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1804 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1805 1806 /* 1807 * Grab the PTE pointer before we diddle with the cached PTE 1808 * copy. 1809 */ 1810 pt = moea_pvo_to_pte(pvo, -1); 1811 /* 1812 * Change the protection of the page. 1813 */ 1814 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1815 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1816 1817 /* 1818 * If the PVO is in the page table, update that pte as well. 1819 */ 1820 if (pt != NULL) { 1821 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1822 mtx_unlock(&moea_table_mutex); 1823 } 1824 } 1825 rw_wunlock(&pvh_global_lock); 1826 PMAP_UNLOCK(pm); 1827 } 1828 1829 /* 1830 * Map a list of wired pages into kernel virtual address space. This is 1831 * intended for temporary mappings which do not need page modification or 1832 * references recorded. Existing mappings in the region are overwritten. 1833 */ 1834 void 1835 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1836 { 1837 vm_offset_t va; 1838 1839 va = sva; 1840 while (count-- > 0) { 1841 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1842 va += PAGE_SIZE; 1843 m++; 1844 } 1845 } 1846 1847 /* 1848 * Remove page mappings from kernel virtual address space. Intended for 1849 * temporary mappings entered by moea_qenter. 1850 */ 1851 void 1852 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1853 { 1854 vm_offset_t va; 1855 1856 va = sva; 1857 while (count-- > 0) { 1858 moea_kremove(mmu, va); 1859 va += PAGE_SIZE; 1860 } 1861 } 1862 1863 void 1864 moea_release(mmu_t mmu, pmap_t pmap) 1865 { 1866 int idx, mask; 1867 1868 /* 1869 * Free segment register's VSID 1870 */ 1871 if (pmap->pm_sr[0] == 0) 1872 panic("moea_release"); 1873 1874 mtx_lock(&moea_vsid_mutex); 1875 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1876 mask = 1 << (idx % VSID_NBPW); 1877 idx /= VSID_NBPW; 1878 moea_vsid_bitmap[idx] &= ~mask; 1879 mtx_unlock(&moea_vsid_mutex); 1880 } 1881 1882 /* 1883 * Remove the given range of addresses from the specified map. 1884 */ 1885 void 1886 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1887 { 1888 struct pvo_entry *pvo, *tpvo, key; 1889 1890 rw_wlock(&pvh_global_lock); 1891 PMAP_LOCK(pm); 1892 key.pvo_vaddr = sva; 1893 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1894 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1895 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1896 moea_pvo_remove(pvo, -1); 1897 } 1898 PMAP_UNLOCK(pm); 1899 rw_wunlock(&pvh_global_lock); 1900 } 1901 1902 /* 1903 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1904 * will reflect changes in pte's back to the vm_page. 1905 */ 1906 void 1907 moea_remove_all(mmu_t mmu, vm_page_t m) 1908 { 1909 struct pvo_head *pvo_head; 1910 struct pvo_entry *pvo, *next_pvo; 1911 pmap_t pmap; 1912 1913 rw_wlock(&pvh_global_lock); 1914 pvo_head = vm_page_to_pvoh(m); 1915 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1916 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1917 1918 pmap = pvo->pvo_pmap; 1919 PMAP_LOCK(pmap); 1920 moea_pvo_remove(pvo, -1); 1921 PMAP_UNLOCK(pmap); 1922 } 1923 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1924 moea_attr_clear(m, PTE_CHG); 1925 vm_page_dirty(m); 1926 } 1927 vm_page_aflag_clear(m, PGA_WRITEABLE); 1928 rw_wunlock(&pvh_global_lock); 1929 } 1930 1931 /* 1932 * Allocate a physical page of memory directly from the phys_avail map. 1933 * Can only be called from moea_bootstrap before avail start and end are 1934 * calculated. 1935 */ 1936 static vm_offset_t 1937 moea_bootstrap_alloc(vm_size_t size, u_int align) 1938 { 1939 vm_offset_t s, e; 1940 int i, j; 1941 1942 size = round_page(size); 1943 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1944 if (align != 0) 1945 s = roundup2(phys_avail[i], align); 1946 else 1947 s = phys_avail[i]; 1948 e = s + size; 1949 1950 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1951 continue; 1952 1953 if (s == phys_avail[i]) { 1954 phys_avail[i] += size; 1955 } else if (e == phys_avail[i + 1]) { 1956 phys_avail[i + 1] -= size; 1957 } else { 1958 for (j = phys_avail_count * 2; j > i; j -= 2) { 1959 phys_avail[j] = phys_avail[j - 2]; 1960 phys_avail[j + 1] = phys_avail[j - 1]; 1961 } 1962 1963 phys_avail[i + 3] = phys_avail[i + 1]; 1964 phys_avail[i + 1] = s; 1965 phys_avail[i + 2] = e; 1966 phys_avail_count++; 1967 } 1968 1969 return (s); 1970 } 1971 panic("moea_bootstrap_alloc: could not allocate memory"); 1972 } 1973 1974 static void 1975 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1976 { 1977 __syncicache((void *)pa, len); 1978 } 1979 1980 static int 1981 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1982 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1983 { 1984 struct pvo_entry *pvo; 1985 u_int sr; 1986 int first; 1987 u_int ptegidx; 1988 int i; 1989 int bootstrap; 1990 1991 moea_pvo_enter_calls++; 1992 first = 0; 1993 bootstrap = 0; 1994 1995 /* 1996 * Compute the PTE Group index. 1997 */ 1998 va &= ~ADDR_POFF; 1999 sr = va_to_sr(pm->pm_sr, va); 2000 ptegidx = va_to_pteg(sr, va); 2001 2002 /* 2003 * Remove any existing mapping for this page. Reuse the pvo entry if 2004 * there is a mapping. 2005 */ 2006 mtx_lock(&moea_table_mutex); 2007 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2008 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2009 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 2010 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2011 (pte_lo & PTE_PP)) { 2012 /* 2013 * The PTE is not changing. Instead, this may 2014 * be a request to change the mapping's wired 2015 * attribute. 2016 */ 2017 mtx_unlock(&moea_table_mutex); 2018 if ((flags & PVO_WIRED) != 0 && 2019 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2020 pvo->pvo_vaddr |= PVO_WIRED; 2021 pm->pm_stats.wired_count++; 2022 } else if ((flags & PVO_WIRED) == 0 && 2023 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2024 pvo->pvo_vaddr &= ~PVO_WIRED; 2025 pm->pm_stats.wired_count--; 2026 } 2027 return (0); 2028 } 2029 moea_pvo_remove(pvo, -1); 2030 break; 2031 } 2032 } 2033 2034 /* 2035 * If we aren't overwriting a mapping, try to allocate. 2036 */ 2037 if (moea_initialized) { 2038 pvo = uma_zalloc(zone, M_NOWAIT); 2039 } else { 2040 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2041 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2042 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2043 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2044 } 2045 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2046 moea_bpvo_pool_index++; 2047 bootstrap = 1; 2048 } 2049 2050 if (pvo == NULL) { 2051 mtx_unlock(&moea_table_mutex); 2052 return (ENOMEM); 2053 } 2054 2055 moea_pvo_entries++; 2056 pvo->pvo_vaddr = va; 2057 pvo->pvo_pmap = pm; 2058 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2059 pvo->pvo_vaddr &= ~ADDR_POFF; 2060 if (flags & PVO_WIRED) 2061 pvo->pvo_vaddr |= PVO_WIRED; 2062 if (pvo_head != &moea_pvo_kunmanaged) 2063 pvo->pvo_vaddr |= PVO_MANAGED; 2064 if (bootstrap) 2065 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2066 2067 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2068 2069 /* 2070 * Add to pmap list 2071 */ 2072 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2073 2074 /* 2075 * Remember if the list was empty and therefore will be the first 2076 * item. 2077 */ 2078 if (LIST_FIRST(pvo_head) == NULL) 2079 first = 1; 2080 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2081 2082 if (pvo->pvo_vaddr & PVO_WIRED) 2083 pm->pm_stats.wired_count++; 2084 pm->pm_stats.resident_count++; 2085 2086 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2087 KASSERT(i < 8, ("Invalid PTE index")); 2088 if (i >= 0) { 2089 PVO_PTEGIDX_SET(pvo, i); 2090 } else { 2091 panic("moea_pvo_enter: overflow"); 2092 moea_pte_overflow++; 2093 } 2094 mtx_unlock(&moea_table_mutex); 2095 2096 return (first ? ENOENT : 0); 2097 } 2098 2099 static void 2100 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2101 { 2102 struct pte *pt; 2103 2104 /* 2105 * If there is an active pte entry, we need to deactivate it (and 2106 * save the ref & cfg bits). 2107 */ 2108 pt = moea_pvo_to_pte(pvo, pteidx); 2109 if (pt != NULL) { 2110 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2111 mtx_unlock(&moea_table_mutex); 2112 PVO_PTEGIDX_CLR(pvo); 2113 } else { 2114 moea_pte_overflow--; 2115 } 2116 2117 /* 2118 * Update our statistics. 2119 */ 2120 pvo->pvo_pmap->pm_stats.resident_count--; 2121 if (pvo->pvo_vaddr & PVO_WIRED) 2122 pvo->pvo_pmap->pm_stats.wired_count--; 2123 2124 /* 2125 * Save the REF/CHG bits into their cache if the page is managed. 2126 */ 2127 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2128 struct vm_page *pg; 2129 2130 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2131 if (pg != NULL) { 2132 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2133 (PTE_REF | PTE_CHG)); 2134 } 2135 } 2136 2137 /* 2138 * Remove this PVO from the PV and pmap lists. 2139 */ 2140 LIST_REMOVE(pvo, pvo_vlink); 2141 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2142 2143 /* 2144 * Remove this from the overflow list and return it to the pool 2145 * if we aren't going to reuse it. 2146 */ 2147 LIST_REMOVE(pvo, pvo_olink); 2148 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2149 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2150 moea_upvo_zone, pvo); 2151 moea_pvo_entries--; 2152 moea_pvo_remove_calls++; 2153 } 2154 2155 static __inline int 2156 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2157 { 2158 int pteidx; 2159 2160 /* 2161 * We can find the actual pte entry without searching by grabbing 2162 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2163 * noticing the HID bit. 2164 */ 2165 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2166 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2167 pteidx ^= moea_pteg_mask * 8; 2168 2169 return (pteidx); 2170 } 2171 2172 static struct pvo_entry * 2173 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2174 { 2175 struct pvo_entry *pvo; 2176 int ptegidx; 2177 u_int sr; 2178 2179 va &= ~ADDR_POFF; 2180 sr = va_to_sr(pm->pm_sr, va); 2181 ptegidx = va_to_pteg(sr, va); 2182 2183 mtx_lock(&moea_table_mutex); 2184 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2185 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2186 if (pteidx_p) 2187 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2188 break; 2189 } 2190 } 2191 mtx_unlock(&moea_table_mutex); 2192 2193 return (pvo); 2194 } 2195 2196 static struct pte * 2197 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2198 { 2199 struct pte *pt; 2200 2201 /* 2202 * If we haven't been supplied the ptegidx, calculate it. 2203 */ 2204 if (pteidx == -1) { 2205 int ptegidx; 2206 u_int sr; 2207 2208 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2209 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2210 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2211 } 2212 2213 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2214 mtx_lock(&moea_table_mutex); 2215 2216 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2217 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2218 "valid pte index", pvo); 2219 } 2220 2221 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2222 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2223 "pvo but no valid pte", pvo); 2224 } 2225 2226 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2227 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2228 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2229 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2230 } 2231 2232 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2233 != 0) { 2234 panic("moea_pvo_to_pte: pvo %p pte does not match " 2235 "pte %p in moea_pteg_table", pvo, pt); 2236 } 2237 2238 mtx_assert(&moea_table_mutex, MA_OWNED); 2239 return (pt); 2240 } 2241 2242 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2243 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2244 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2245 } 2246 2247 mtx_unlock(&moea_table_mutex); 2248 return (NULL); 2249 } 2250 2251 /* 2252 * XXX: THIS STUFF SHOULD BE IN pte.c? 2253 */ 2254 int 2255 moea_pte_spill(vm_offset_t addr) 2256 { 2257 struct pvo_entry *source_pvo, *victim_pvo; 2258 struct pvo_entry *pvo; 2259 int ptegidx, i, j; 2260 u_int sr; 2261 struct pteg *pteg; 2262 struct pte *pt; 2263 2264 moea_pte_spills++; 2265 2266 sr = mfsrin(addr); 2267 ptegidx = va_to_pteg(sr, addr); 2268 2269 /* 2270 * Have to substitute some entry. Use the primary hash for this. 2271 * Use low bits of timebase as random generator. 2272 */ 2273 pteg = &moea_pteg_table[ptegidx]; 2274 mtx_lock(&moea_table_mutex); 2275 __asm __volatile("mftb %0" : "=r"(i)); 2276 i &= 7; 2277 pt = &pteg->pt[i]; 2278 2279 source_pvo = NULL; 2280 victim_pvo = NULL; 2281 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2282 /* 2283 * We need to find a pvo entry for this address. 2284 */ 2285 if (source_pvo == NULL && 2286 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2287 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2288 /* 2289 * Now found an entry to be spilled into the pteg. 2290 * The PTE is now valid, so we know it's active. 2291 */ 2292 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2293 2294 if (j >= 0) { 2295 PVO_PTEGIDX_SET(pvo, j); 2296 moea_pte_overflow--; 2297 mtx_unlock(&moea_table_mutex); 2298 return (1); 2299 } 2300 2301 source_pvo = pvo; 2302 2303 if (victim_pvo != NULL) 2304 break; 2305 } 2306 2307 /* 2308 * We also need the pvo entry of the victim we are replacing 2309 * so save the R & C bits of the PTE. 2310 */ 2311 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2312 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2313 victim_pvo = pvo; 2314 if (source_pvo != NULL) 2315 break; 2316 } 2317 } 2318 2319 if (source_pvo == NULL) { 2320 mtx_unlock(&moea_table_mutex); 2321 return (0); 2322 } 2323 2324 if (victim_pvo == NULL) { 2325 if ((pt->pte_hi & PTE_HID) == 0) 2326 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2327 "entry", pt); 2328 2329 /* 2330 * If this is a secondary PTE, we need to search it's primary 2331 * pvo bucket for the matching PVO. 2332 */ 2333 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2334 pvo_olink) { 2335 /* 2336 * We also need the pvo entry of the victim we are 2337 * replacing so save the R & C bits of the PTE. 2338 */ 2339 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2340 victim_pvo = pvo; 2341 break; 2342 } 2343 } 2344 2345 if (victim_pvo == NULL) 2346 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2347 "entry", pt); 2348 } 2349 2350 /* 2351 * We are invalidating the TLB entry for the EA we are replacing even 2352 * though it's valid. If we don't, we lose any ref/chg bit changes 2353 * contained in the TLB entry. 2354 */ 2355 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2356 2357 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2358 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2359 2360 PVO_PTEGIDX_CLR(victim_pvo); 2361 PVO_PTEGIDX_SET(source_pvo, i); 2362 moea_pte_replacements++; 2363 2364 mtx_unlock(&moea_table_mutex); 2365 return (1); 2366 } 2367 2368 static __inline struct pvo_entry * 2369 moea_pte_spillable_ident(u_int ptegidx) 2370 { 2371 struct pte *pt; 2372 struct pvo_entry *pvo_walk, *pvo = NULL; 2373 2374 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2375 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2376 continue; 2377 2378 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2379 continue; 2380 2381 pt = moea_pvo_to_pte(pvo_walk, -1); 2382 2383 if (pt == NULL) 2384 continue; 2385 2386 pvo = pvo_walk; 2387 2388 mtx_unlock(&moea_table_mutex); 2389 if (!(pt->pte_lo & PTE_REF)) 2390 return (pvo_walk); 2391 } 2392 2393 return (pvo); 2394 } 2395 2396 static int 2397 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2398 { 2399 struct pte *pt; 2400 struct pvo_entry *victim_pvo; 2401 int i; 2402 int victim_idx; 2403 u_int pteg_bkpidx = ptegidx; 2404 2405 mtx_assert(&moea_table_mutex, MA_OWNED); 2406 2407 /* 2408 * First try primary hash. 2409 */ 2410 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2411 if ((pt->pte_hi & PTE_VALID) == 0) { 2412 pvo_pt->pte_hi &= ~PTE_HID; 2413 moea_pte_set(pt, pvo_pt); 2414 return (i); 2415 } 2416 } 2417 2418 /* 2419 * Now try secondary hash. 2420 */ 2421 ptegidx ^= moea_pteg_mask; 2422 2423 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2424 if ((pt->pte_hi & PTE_VALID) == 0) { 2425 pvo_pt->pte_hi |= PTE_HID; 2426 moea_pte_set(pt, pvo_pt); 2427 return (i); 2428 } 2429 } 2430 2431 /* Try again, but this time try to force a PTE out. */ 2432 ptegidx = pteg_bkpidx; 2433 2434 victim_pvo = moea_pte_spillable_ident(ptegidx); 2435 if (victim_pvo == NULL) { 2436 ptegidx ^= moea_pteg_mask; 2437 victim_pvo = moea_pte_spillable_ident(ptegidx); 2438 } 2439 2440 if (victim_pvo == NULL) { 2441 panic("moea_pte_insert: overflow"); 2442 return (-1); 2443 } 2444 2445 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2446 2447 if (pteg_bkpidx == ptegidx) 2448 pvo_pt->pte_hi &= ~PTE_HID; 2449 else 2450 pvo_pt->pte_hi |= PTE_HID; 2451 2452 /* 2453 * Synchronize the sacrifice PTE with its PVO, then mark both 2454 * invalid. The PVO will be reused when/if the VM system comes 2455 * here after a fault. 2456 */ 2457 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2458 2459 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2460 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2461 2462 /* 2463 * Set the new PTE. 2464 */ 2465 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2466 PVO_PTEGIDX_CLR(victim_pvo); 2467 moea_pte_overflow++; 2468 moea_pte_set(pt, pvo_pt); 2469 2470 return (victim_idx & 7); 2471 } 2472 2473 static boolean_t 2474 moea_query_bit(vm_page_t m, int ptebit) 2475 { 2476 struct pvo_entry *pvo; 2477 struct pte *pt; 2478 2479 rw_assert(&pvh_global_lock, RA_WLOCKED); 2480 if (moea_attr_fetch(m) & ptebit) 2481 return (TRUE); 2482 2483 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2484 2485 /* 2486 * See if we saved the bit off. If so, cache it and return 2487 * success. 2488 */ 2489 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2490 moea_attr_save(m, ptebit); 2491 return (TRUE); 2492 } 2493 } 2494 2495 /* 2496 * No luck, now go through the hard part of looking at the PTEs 2497 * themselves. Sync so that any pending REF/CHG bits are flushed to 2498 * the PTEs. 2499 */ 2500 powerpc_sync(); 2501 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2502 2503 /* 2504 * See if this pvo has a valid PTE. if so, fetch the 2505 * REF/CHG bits from the valid PTE. If the appropriate 2506 * ptebit is set, cache it and return success. 2507 */ 2508 pt = moea_pvo_to_pte(pvo, -1); 2509 if (pt != NULL) { 2510 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2511 mtx_unlock(&moea_table_mutex); 2512 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2513 moea_attr_save(m, ptebit); 2514 return (TRUE); 2515 } 2516 } 2517 } 2518 2519 return (FALSE); 2520 } 2521 2522 static u_int 2523 moea_clear_bit(vm_page_t m, int ptebit) 2524 { 2525 u_int count; 2526 struct pvo_entry *pvo; 2527 struct pte *pt; 2528 2529 rw_assert(&pvh_global_lock, RA_WLOCKED); 2530 2531 /* 2532 * Clear the cached value. 2533 */ 2534 moea_attr_clear(m, ptebit); 2535 2536 /* 2537 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2538 * we can reset the right ones). note that since the pvo entries and 2539 * list heads are accessed via BAT0 and are never placed in the page 2540 * table, we don't have to worry about further accesses setting the 2541 * REF/CHG bits. 2542 */ 2543 powerpc_sync(); 2544 2545 /* 2546 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2547 * valid pte clear the ptebit from the valid pte. 2548 */ 2549 count = 0; 2550 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2551 pt = moea_pvo_to_pte(pvo, -1); 2552 if (pt != NULL) { 2553 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2554 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2555 count++; 2556 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2557 } 2558 mtx_unlock(&moea_table_mutex); 2559 } 2560 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2561 } 2562 2563 return (count); 2564 } 2565 2566 /* 2567 * Return true if the physical range is encompassed by the battable[idx] 2568 */ 2569 static int 2570 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2571 { 2572 u_int prot; 2573 u_int32_t start; 2574 u_int32_t end; 2575 u_int32_t bat_ble; 2576 2577 /* 2578 * Return immediately if not a valid mapping 2579 */ 2580 if (!(battable[idx].batu & BAT_Vs)) 2581 return (EINVAL); 2582 2583 /* 2584 * The BAT entry must be cache-inhibited, guarded, and r/w 2585 * so it can function as an i/o page 2586 */ 2587 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2588 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2589 return (EPERM); 2590 2591 /* 2592 * The address should be within the BAT range. Assume that the 2593 * start address in the BAT has the correct alignment (thus 2594 * not requiring masking) 2595 */ 2596 start = battable[idx].batl & BAT_PBS; 2597 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2598 end = start | (bat_ble << 15) | 0x7fff; 2599 2600 if ((pa < start) || ((pa + size) > end)) 2601 return (ERANGE); 2602 2603 return (0); 2604 } 2605 2606 boolean_t 2607 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2608 { 2609 int i; 2610 2611 /* 2612 * This currently does not work for entries that 2613 * overlap 256M BAT segments. 2614 */ 2615 2616 for(i = 0; i < 16; i++) 2617 if (moea_bat_mapped(i, pa, size) == 0) 2618 return (0); 2619 2620 return (EFAULT); 2621 } 2622 2623 /* 2624 * Map a set of physical memory pages into the kernel virtual 2625 * address space. Return a pointer to where it is mapped. This 2626 * routine is intended to be used for mapping device memory, 2627 * NOT real memory. 2628 */ 2629 void * 2630 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2631 { 2632 2633 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2634 } 2635 2636 void * 2637 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2638 { 2639 vm_offset_t va, tmpva, ppa, offset; 2640 int i; 2641 2642 ppa = trunc_page(pa); 2643 offset = pa & PAGE_MASK; 2644 size = roundup(offset + size, PAGE_SIZE); 2645 2646 /* 2647 * If the physical address lies within a valid BAT table entry, 2648 * return the 1:1 mapping. This currently doesn't work 2649 * for regions that overlap 256M BAT segments. 2650 */ 2651 for (i = 0; i < 16; i++) { 2652 if (moea_bat_mapped(i, pa, size) == 0) 2653 return ((void *) pa); 2654 } 2655 2656 va = kva_alloc(size); 2657 if (!va) 2658 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2659 2660 for (tmpva = va; size > 0;) { 2661 moea_kenter_attr(mmu, tmpva, ppa, ma); 2662 tlbie(tmpva); 2663 size -= PAGE_SIZE; 2664 tmpva += PAGE_SIZE; 2665 ppa += PAGE_SIZE; 2666 } 2667 2668 return ((void *)(va + offset)); 2669 } 2670 2671 void 2672 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2673 { 2674 vm_offset_t base, offset; 2675 2676 /* 2677 * If this is outside kernel virtual space, then it's a 2678 * battable entry and doesn't require unmapping 2679 */ 2680 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2681 base = trunc_page(va); 2682 offset = va & PAGE_MASK; 2683 size = roundup(offset + size, PAGE_SIZE); 2684 kva_free(base, size); 2685 } 2686 } 2687 2688 static void 2689 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2690 { 2691 struct pvo_entry *pvo; 2692 vm_offset_t lim; 2693 vm_paddr_t pa; 2694 vm_size_t len; 2695 2696 PMAP_LOCK(pm); 2697 while (sz > 0) { 2698 lim = round_page(va); 2699 len = MIN(lim - va, sz); 2700 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2701 if (pvo != NULL) { 2702 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2703 (va & ADDR_POFF); 2704 moea_syncicache(pa, len); 2705 } 2706 va += len; 2707 sz -= len; 2708 } 2709 PMAP_UNLOCK(pm); 2710 } 2711 2712 void 2713 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2714 { 2715 2716 *va = (void *)pa; 2717 } 2718 2719 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2720 2721 void 2722 moea_scan_init(mmu_t mmu) 2723 { 2724 struct pvo_entry *pvo; 2725 vm_offset_t va; 2726 int i; 2727 2728 if (!do_minidump) { 2729 /* Initialize phys. segments for dumpsys(). */ 2730 memset(&dump_map, 0, sizeof(dump_map)); 2731 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2732 for (i = 0; i < pregions_sz; i++) { 2733 dump_map[i].pa_start = pregions[i].mr_start; 2734 dump_map[i].pa_size = pregions[i].mr_size; 2735 } 2736 return; 2737 } 2738 2739 /* Virtual segments for minidumps: */ 2740 memset(&dump_map, 0, sizeof(dump_map)); 2741 2742 /* 1st: kernel .data and .bss. */ 2743 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2744 dump_map[0].pa_size = 2745 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2746 2747 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2748 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2749 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2750 2751 /* 3rd: kernel VM. */ 2752 va = dump_map[1].pa_start + dump_map[1].pa_size; 2753 /* Find start of next chunk (from va). */ 2754 while (va < virtual_end) { 2755 /* Don't dump the buffer cache. */ 2756 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2757 va = kmi.buffer_eva; 2758 continue; 2759 } 2760 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2761 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2762 break; 2763 va += PAGE_SIZE; 2764 } 2765 if (va < virtual_end) { 2766 dump_map[2].pa_start = va; 2767 va += PAGE_SIZE; 2768 /* Find last page in chunk. */ 2769 while (va < virtual_end) { 2770 /* Don't run into the buffer cache. */ 2771 if (va == kmi.buffer_sva) 2772 break; 2773 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2774 NULL); 2775 if (pvo == NULL || 2776 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2777 break; 2778 va += PAGE_SIZE; 2779 } 2780 dump_map[2].pa_size = va - dump_map[2].pa_start; 2781 } 2782 } 2783