1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/conf.h> 110 #include <sys/queue.h> 111 #include <sys/cpuset.h> 112 #include <sys/kerneldump.h> 113 #include <sys/ktr.h> 114 #include <sys/lock.h> 115 #include <sys/msgbuf.h> 116 #include <sys/mutex.h> 117 #include <sys/proc.h> 118 #include <sys/rwlock.h> 119 #include <sys/sched.h> 120 #include <sys/sysctl.h> 121 #include <sys/systm.h> 122 #include <sys/vmmeter.h> 123 124 #include <dev/ofw/openfirm.h> 125 126 #include <vm/vm.h> 127 #include <vm/vm_param.h> 128 #include <vm/vm_kern.h> 129 #include <vm/vm_page.h> 130 #include <vm/vm_map.h> 131 #include <vm/vm_object.h> 132 #include <vm/vm_extern.h> 133 #include <vm/vm_pageout.h> 134 #include <vm/uma.h> 135 136 #include <machine/cpu.h> 137 #include <machine/platform.h> 138 #include <machine/bat.h> 139 #include <machine/frame.h> 140 #include <machine/md_var.h> 141 #include <machine/psl.h> 142 #include <machine/pte.h> 143 #include <machine/smp.h> 144 #include <machine/sr.h> 145 #include <machine/mmuvar.h> 146 #include <machine/trap.h> 147 148 #include "mmu_if.h" 149 150 #define MOEA_DEBUG 151 152 #define TODO panic("%s: not implemented", __func__); 153 154 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 155 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 156 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 157 158 struct ofw_map { 159 vm_offset_t om_va; 160 vm_size_t om_len; 161 vm_offset_t om_pa; 162 u_int om_mode; 163 }; 164 165 extern unsigned char _etext[]; 166 extern unsigned char _end[]; 167 168 /* 169 * Map of physical memory regions. 170 */ 171 static struct mem_region *regions; 172 static struct mem_region *pregions; 173 static u_int phys_avail_count; 174 static int regions_sz, pregions_sz; 175 static struct ofw_map *translations; 176 177 /* 178 * Lock for the pteg and pvo tables. 179 */ 180 struct mtx moea_table_mutex; 181 struct mtx moea_vsid_mutex; 182 183 /* tlbie instruction synchronization */ 184 static struct mtx tlbie_mtx; 185 186 /* 187 * PTEG data. 188 */ 189 static struct pteg *moea_pteg_table; 190 u_int moea_pteg_count; 191 u_int moea_pteg_mask; 192 193 /* 194 * PVO data. 195 */ 196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197 struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200 static struct rwlock_padalign pvh_global_lock; 201 202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205 #define BPVO_POOL_SIZE 32768 206 static struct pvo_entry *moea_bpvo_pool; 207 static int moea_bpvo_pool_index = 0; 208 209 #define VSID_NBPW (sizeof(u_int32_t) * 8) 210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212 static boolean_t moea_initialized = FALSE; 213 214 /* 215 * Statistics. 216 */ 217 u_int moea_pte_valid = 0; 218 u_int moea_pte_overflow = 0; 219 u_int moea_pte_replacements = 0; 220 u_int moea_pvo_entries = 0; 221 u_int moea_pvo_enter_calls = 0; 222 u_int moea_pvo_remove_calls = 0; 223 u_int moea_pte_spills = 0; 224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239 /* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244 /* 245 * PTE calls. 246 */ 247 static int moea_pte_insert(u_int, struct pte *); 248 249 /* 250 * PVO calls. 251 */ 252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_offset_t, u_int, int); 254 static void moea_pvo_remove(struct pvo_entry *, int); 255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258 /* 259 * Utility routines. 260 */ 261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, u_int, int8_t); 263 static void moea_syncicache(vm_offset_t, vm_size_t); 264 static boolean_t moea_query_bit(vm_page_t, int); 265 static u_int moea_clear_bit(vm_page_t, int); 266 static void moea_kremove(mmu_t, vm_offset_t); 267 int moea_pte_spill(vm_offset_t); 268 269 /* 270 * Kernel MMU interface 271 */ 272 void moea_clear_modify(mmu_t, vm_page_t); 273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 275 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 277 int8_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 int moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_zero_page(mmu_t, vm_page_t); 302 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 303 void moea_zero_page_idle(mmu_t, vm_page_t); 304 void moea_activate(mmu_t, struct thread *); 305 void moea_deactivate(mmu_t, struct thread *); 306 void moea_cpu_bootstrap(mmu_t, int); 307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 317 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 318 void moea_scan_init(mmu_t mmu); 319 320 static mmu_method_t moea_methods[] = { 321 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 322 MMUMETHOD(mmu_copy_page, moea_copy_page), 323 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 324 MMUMETHOD(mmu_enter, moea_enter), 325 MMUMETHOD(mmu_enter_object, moea_enter_object), 326 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 327 MMUMETHOD(mmu_extract, moea_extract), 328 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 329 MMUMETHOD(mmu_init, moea_init), 330 MMUMETHOD(mmu_is_modified, moea_is_modified), 331 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 332 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 333 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 334 MMUMETHOD(mmu_map, moea_map), 335 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 336 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 337 MMUMETHOD(mmu_pinit, moea_pinit), 338 MMUMETHOD(mmu_pinit0, moea_pinit0), 339 MMUMETHOD(mmu_protect, moea_protect), 340 MMUMETHOD(mmu_qenter, moea_qenter), 341 MMUMETHOD(mmu_qremove, moea_qremove), 342 MMUMETHOD(mmu_release, moea_release), 343 MMUMETHOD(mmu_remove, moea_remove), 344 MMUMETHOD(mmu_remove_all, moea_remove_all), 345 MMUMETHOD(mmu_remove_write, moea_remove_write), 346 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 347 MMUMETHOD(mmu_unwire, moea_unwire), 348 MMUMETHOD(mmu_zero_page, moea_zero_page), 349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 351 MMUMETHOD(mmu_activate, moea_activate), 352 MMUMETHOD(mmu_deactivate, moea_deactivate), 353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 354 355 /* Internal interfaces */ 356 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 359 MMUMETHOD(mmu_mapdev, moea_mapdev), 360 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 361 MMUMETHOD(mmu_kextract, moea_kextract), 362 MMUMETHOD(mmu_kenter, moea_kenter), 363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 365 MMUMETHOD(mmu_scan_init, moea_scan_init), 366 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 367 368 { 0, 0 } 369 }; 370 371 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 372 373 static __inline uint32_t 374 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 375 { 376 uint32_t pte_lo; 377 int i; 378 379 if (ma != VM_MEMATTR_DEFAULT) { 380 switch (ma) { 381 case VM_MEMATTR_UNCACHEABLE: 382 return (PTE_I | PTE_G); 383 case VM_MEMATTR_WRITE_COMBINING: 384 case VM_MEMATTR_WRITE_BACK: 385 case VM_MEMATTR_PREFETCHABLE: 386 return (PTE_I); 387 case VM_MEMATTR_WRITE_THROUGH: 388 return (PTE_W | PTE_M); 389 } 390 } 391 392 /* 393 * Assume the page is cache inhibited and access is guarded unless 394 * it's in our available memory array. 395 */ 396 pte_lo = PTE_I | PTE_G; 397 for (i = 0; i < pregions_sz; i++) { 398 if ((pa >= pregions[i].mr_start) && 399 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 400 pte_lo = PTE_M; 401 break; 402 } 403 } 404 405 return pte_lo; 406 } 407 408 static void 409 tlbie(vm_offset_t va) 410 { 411 412 mtx_lock_spin(&tlbie_mtx); 413 __asm __volatile("ptesync"); 414 __asm __volatile("tlbie %0" :: "r"(va)); 415 __asm __volatile("eieio; tlbsync; ptesync"); 416 mtx_unlock_spin(&tlbie_mtx); 417 } 418 419 static void 420 tlbia(void) 421 { 422 vm_offset_t va; 423 424 for (va = 0; va < 0x00040000; va += 0x00001000) { 425 __asm __volatile("tlbie %0" :: "r"(va)); 426 powerpc_sync(); 427 } 428 __asm __volatile("tlbsync"); 429 powerpc_sync(); 430 } 431 432 static __inline int 433 va_to_sr(u_int *sr, vm_offset_t va) 434 { 435 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 436 } 437 438 static __inline u_int 439 va_to_pteg(u_int sr, vm_offset_t addr) 440 { 441 u_int hash; 442 443 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 444 ADDR_PIDX_SHFT); 445 return (hash & moea_pteg_mask); 446 } 447 448 static __inline struct pvo_head * 449 vm_page_to_pvoh(vm_page_t m) 450 { 451 452 return (&m->md.mdpg_pvoh); 453 } 454 455 static __inline void 456 moea_attr_clear(vm_page_t m, int ptebit) 457 { 458 459 rw_assert(&pvh_global_lock, RA_WLOCKED); 460 m->md.mdpg_attrs &= ~ptebit; 461 } 462 463 static __inline int 464 moea_attr_fetch(vm_page_t m) 465 { 466 467 return (m->md.mdpg_attrs); 468 } 469 470 static __inline void 471 moea_attr_save(vm_page_t m, int ptebit) 472 { 473 474 rw_assert(&pvh_global_lock, RA_WLOCKED); 475 m->md.mdpg_attrs |= ptebit; 476 } 477 478 static __inline int 479 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 480 { 481 if (pt->pte_hi == pvo_pt->pte_hi) 482 return (1); 483 484 return (0); 485 } 486 487 static __inline int 488 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 489 { 490 return (pt->pte_hi & ~PTE_VALID) == 491 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 492 ((va >> ADDR_API_SHFT) & PTE_API) | which); 493 } 494 495 static __inline void 496 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 497 { 498 499 mtx_assert(&moea_table_mutex, MA_OWNED); 500 501 /* 502 * Construct a PTE. Default to IMB initially. Valid bit only gets 503 * set when the real pte is set in memory. 504 * 505 * Note: Don't set the valid bit for correct operation of tlb update. 506 */ 507 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 508 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 509 pt->pte_lo = pte_lo; 510 } 511 512 static __inline void 513 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 514 { 515 516 mtx_assert(&moea_table_mutex, MA_OWNED); 517 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 518 } 519 520 static __inline void 521 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 522 { 523 524 mtx_assert(&moea_table_mutex, MA_OWNED); 525 526 /* 527 * As shown in Section 7.6.3.2.3 528 */ 529 pt->pte_lo &= ~ptebit; 530 tlbie(va); 531 } 532 533 static __inline void 534 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 535 { 536 537 mtx_assert(&moea_table_mutex, MA_OWNED); 538 pvo_pt->pte_hi |= PTE_VALID; 539 540 /* 541 * Update the PTE as defined in section 7.6.3.1. 542 * Note that the REF/CHG bits are from pvo_pt and thus should have 543 * been saved so this routine can restore them (if desired). 544 */ 545 pt->pte_lo = pvo_pt->pte_lo; 546 powerpc_sync(); 547 pt->pte_hi = pvo_pt->pte_hi; 548 powerpc_sync(); 549 moea_pte_valid++; 550 } 551 552 static __inline void 553 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 554 { 555 556 mtx_assert(&moea_table_mutex, MA_OWNED); 557 pvo_pt->pte_hi &= ~PTE_VALID; 558 559 /* 560 * Force the reg & chg bits back into the PTEs. 561 */ 562 powerpc_sync(); 563 564 /* 565 * Invalidate the pte. 566 */ 567 pt->pte_hi &= ~PTE_VALID; 568 569 tlbie(va); 570 571 /* 572 * Save the reg & chg bits. 573 */ 574 moea_pte_synch(pt, pvo_pt); 575 moea_pte_valid--; 576 } 577 578 static __inline void 579 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 580 { 581 582 /* 583 * Invalidate the PTE 584 */ 585 moea_pte_unset(pt, pvo_pt, va); 586 moea_pte_set(pt, pvo_pt); 587 } 588 589 /* 590 * Quick sort callout for comparing memory regions. 591 */ 592 static int om_cmp(const void *a, const void *b); 593 594 static int 595 om_cmp(const void *a, const void *b) 596 { 597 const struct ofw_map *mapa; 598 const struct ofw_map *mapb; 599 600 mapa = a; 601 mapb = b; 602 if (mapa->om_pa < mapb->om_pa) 603 return (-1); 604 else if (mapa->om_pa > mapb->om_pa) 605 return (1); 606 else 607 return (0); 608 } 609 610 void 611 moea_cpu_bootstrap(mmu_t mmup, int ap) 612 { 613 u_int sdr; 614 int i; 615 616 if (ap) { 617 powerpc_sync(); 618 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 619 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 620 isync(); 621 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 622 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 623 isync(); 624 } 625 626 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 627 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 628 isync(); 629 630 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 631 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 632 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 633 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 634 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 635 isync(); 636 637 for (i = 0; i < 16; i++) 638 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 639 powerpc_sync(); 640 641 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 642 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 643 isync(); 644 645 tlbia(); 646 } 647 648 void 649 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 650 { 651 ihandle_t mmui; 652 phandle_t chosen, mmu; 653 int sz; 654 int i, j; 655 vm_size_t size, physsz, hwphyssz; 656 vm_offset_t pa, va, off; 657 void *dpcpu; 658 register_t msr; 659 660 /* 661 * Set up BAT0 to map the lowest 256 MB area 662 */ 663 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 664 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 665 666 /* 667 * Map PCI memory space. 668 */ 669 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 670 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 671 672 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 673 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 674 675 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 676 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 677 678 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 679 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 680 681 /* 682 * Map obio devices. 683 */ 684 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 686 687 /* 688 * Use an IBAT and a DBAT to map the bottom segment of memory 689 * where we are. Turn off instruction relocation temporarily 690 * to prevent faults while reprogramming the IBAT. 691 */ 692 msr = mfmsr(); 693 mtmsr(msr & ~PSL_IR); 694 __asm (".balign 32; \n" 695 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 696 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 697 :: "r"(battable[0].batu), "r"(battable[0].batl)); 698 mtmsr(msr); 699 700 /* map pci space */ 701 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 702 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 703 isync(); 704 705 /* set global direct map flag */ 706 hw_direct_map = 1; 707 708 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 709 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 710 711 for (i = 0; i < pregions_sz; i++) { 712 vm_offset_t pa; 713 vm_offset_t end; 714 715 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 716 pregions[i].mr_start, 717 pregions[i].mr_start + pregions[i].mr_size, 718 pregions[i].mr_size); 719 /* 720 * Install entries into the BAT table to allow all 721 * of physmem to be convered by on-demand BAT entries. 722 * The loop will sometimes set the same battable element 723 * twice, but that's fine since they won't be used for 724 * a while yet. 725 */ 726 pa = pregions[i].mr_start & 0xf0000000; 727 end = pregions[i].mr_start + pregions[i].mr_size; 728 do { 729 u_int n = pa >> ADDR_SR_SHFT; 730 731 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 732 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 733 pa += SEGMENT_LENGTH; 734 } while (pa < end); 735 } 736 737 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 738 panic("moea_bootstrap: phys_avail too small"); 739 740 phys_avail_count = 0; 741 physsz = 0; 742 hwphyssz = 0; 743 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 744 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 745 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 746 regions[i].mr_start + regions[i].mr_size, 747 regions[i].mr_size); 748 if (hwphyssz != 0 && 749 (physsz + regions[i].mr_size) >= hwphyssz) { 750 if (physsz < hwphyssz) { 751 phys_avail[j] = regions[i].mr_start; 752 phys_avail[j + 1] = regions[i].mr_start + 753 hwphyssz - physsz; 754 physsz = hwphyssz; 755 phys_avail_count++; 756 } 757 break; 758 } 759 phys_avail[j] = regions[i].mr_start; 760 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 761 phys_avail_count++; 762 physsz += regions[i].mr_size; 763 } 764 765 /* Check for overlap with the kernel and exception vectors */ 766 for (j = 0; j < 2*phys_avail_count; j+=2) { 767 if (phys_avail[j] < EXC_LAST) 768 phys_avail[j] += EXC_LAST; 769 770 if (kernelstart >= phys_avail[j] && 771 kernelstart < phys_avail[j+1]) { 772 if (kernelend < phys_avail[j+1]) { 773 phys_avail[2*phys_avail_count] = 774 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 775 phys_avail[2*phys_avail_count + 1] = 776 phys_avail[j+1]; 777 phys_avail_count++; 778 } 779 780 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 781 } 782 783 if (kernelend >= phys_avail[j] && 784 kernelend < phys_avail[j+1]) { 785 if (kernelstart > phys_avail[j]) { 786 phys_avail[2*phys_avail_count] = phys_avail[j]; 787 phys_avail[2*phys_avail_count + 1] = 788 kernelstart & ~PAGE_MASK; 789 phys_avail_count++; 790 } 791 792 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 793 } 794 } 795 796 physmem = btoc(physsz); 797 798 /* 799 * Allocate PTEG table. 800 */ 801 #ifdef PTEGCOUNT 802 moea_pteg_count = PTEGCOUNT; 803 #else 804 moea_pteg_count = 0x1000; 805 806 while (moea_pteg_count < physmem) 807 moea_pteg_count <<= 1; 808 809 moea_pteg_count >>= 1; 810 #endif /* PTEGCOUNT */ 811 812 size = moea_pteg_count * sizeof(struct pteg); 813 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 814 size); 815 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 816 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 817 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 818 moea_pteg_mask = moea_pteg_count - 1; 819 820 /* 821 * Allocate pv/overflow lists. 822 */ 823 size = sizeof(struct pvo_head) * moea_pteg_count; 824 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 825 PAGE_SIZE); 826 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 827 for (i = 0; i < moea_pteg_count; i++) 828 LIST_INIT(&moea_pvo_table[i]); 829 830 /* 831 * Initialize the lock that synchronizes access to the pteg and pvo 832 * tables. 833 */ 834 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 835 MTX_RECURSE); 836 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 837 838 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 839 840 /* 841 * Initialise the unmanaged pvo pool. 842 */ 843 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 844 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 845 moea_bpvo_pool_index = 0; 846 847 /* 848 * Make sure kernel vsid is allocated as well as VSID 0. 849 */ 850 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 851 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 852 moea_vsid_bitmap[0] |= 1; 853 854 /* 855 * Initialize the kernel pmap (which is statically allocated). 856 */ 857 PMAP_LOCK_INIT(kernel_pmap); 858 for (i = 0; i < 16; i++) 859 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 860 CPU_FILL(&kernel_pmap->pm_active); 861 RB_INIT(&kernel_pmap->pmap_pvo); 862 863 /* 864 * Initialize the global pv list lock. 865 */ 866 rw_init(&pvh_global_lock, "pmap pv global"); 867 868 /* 869 * Set up the Open Firmware mappings 870 */ 871 chosen = OF_finddevice("/chosen"); 872 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 873 (mmu = OF_instance_to_package(mmui)) != -1 && 874 (sz = OF_getproplen(mmu, "translations")) != -1) { 875 translations = NULL; 876 for (i = 0; phys_avail[i] != 0; i += 2) { 877 if (phys_avail[i + 1] >= sz) { 878 translations = (struct ofw_map *)phys_avail[i]; 879 break; 880 } 881 } 882 if (translations == NULL) 883 panic("moea_bootstrap: no space to copy translations"); 884 bzero(translations, sz); 885 if (OF_getprop(mmu, "translations", translations, sz) == -1) 886 panic("moea_bootstrap: can't get ofw translations"); 887 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 888 sz /= sizeof(*translations); 889 qsort(translations, sz, sizeof (*translations), om_cmp); 890 for (i = 0; i < sz; i++) { 891 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 892 translations[i].om_pa, translations[i].om_va, 893 translations[i].om_len); 894 895 /* 896 * If the mapping is 1:1, let the RAM and device 897 * on-demand BAT tables take care of the translation. 898 */ 899 if (translations[i].om_va == translations[i].om_pa) 900 continue; 901 902 /* Enter the pages */ 903 for (off = 0; off < translations[i].om_len; 904 off += PAGE_SIZE) 905 moea_kenter(mmup, translations[i].om_va + off, 906 translations[i].om_pa + off); 907 } 908 } 909 910 /* 911 * Calculate the last available physical address. 912 */ 913 for (i = 0; phys_avail[i + 2] != 0; i += 2) 914 ; 915 Maxmem = powerpc_btop(phys_avail[i + 1]); 916 917 moea_cpu_bootstrap(mmup,0); 918 919 pmap_bootstrapped++; 920 921 /* 922 * Set the start and end of kva. 923 */ 924 virtual_avail = VM_MIN_KERNEL_ADDRESS; 925 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 926 927 /* 928 * Allocate a kernel stack with a guard page for thread0 and map it 929 * into the kernel page map. 930 */ 931 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 932 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 933 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 934 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 935 thread0.td_kstack = va; 936 thread0.td_kstack_pages = KSTACK_PAGES; 937 for (i = 0; i < KSTACK_PAGES; i++) { 938 moea_kenter(mmup, va, pa); 939 pa += PAGE_SIZE; 940 va += PAGE_SIZE; 941 } 942 943 /* 944 * Allocate virtual address space for the message buffer. 945 */ 946 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 947 msgbufp = (struct msgbuf *)virtual_avail; 948 va = virtual_avail; 949 virtual_avail += round_page(msgbufsize); 950 while (va < virtual_avail) { 951 moea_kenter(mmup, va, pa); 952 pa += PAGE_SIZE; 953 va += PAGE_SIZE; 954 } 955 956 /* 957 * Allocate virtual address space for the dynamic percpu area. 958 */ 959 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 960 dpcpu = (void *)virtual_avail; 961 va = virtual_avail; 962 virtual_avail += DPCPU_SIZE; 963 while (va < virtual_avail) { 964 moea_kenter(mmup, va, pa); 965 pa += PAGE_SIZE; 966 va += PAGE_SIZE; 967 } 968 dpcpu_init(dpcpu, 0); 969 } 970 971 /* 972 * Activate a user pmap. The pmap must be activated before it's address 973 * space can be accessed in any way. 974 */ 975 void 976 moea_activate(mmu_t mmu, struct thread *td) 977 { 978 pmap_t pm, pmr; 979 980 /* 981 * Load all the data we need up front to encourage the compiler to 982 * not issue any loads while we have interrupts disabled below. 983 */ 984 pm = &td->td_proc->p_vmspace->vm_pmap; 985 pmr = pm->pmap_phys; 986 987 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 988 PCPU_SET(curpmap, pmr); 989 990 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 991 } 992 993 void 994 moea_deactivate(mmu_t mmu, struct thread *td) 995 { 996 pmap_t pm; 997 998 pm = &td->td_proc->p_vmspace->vm_pmap; 999 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1000 PCPU_SET(curpmap, NULL); 1001 } 1002 1003 void 1004 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1005 { 1006 struct pvo_entry key, *pvo; 1007 1008 PMAP_LOCK(pm); 1009 key.pvo_vaddr = sva; 1010 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1011 pvo != NULL && PVO_VADDR(pvo) < eva; 1012 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1013 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1014 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1015 pvo->pvo_vaddr &= ~PVO_WIRED; 1016 pm->pm_stats.wired_count--; 1017 } 1018 PMAP_UNLOCK(pm); 1019 } 1020 1021 void 1022 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1023 { 1024 vm_offset_t dst; 1025 vm_offset_t src; 1026 1027 dst = VM_PAGE_TO_PHYS(mdst); 1028 src = VM_PAGE_TO_PHYS(msrc); 1029 1030 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1031 } 1032 1033 void 1034 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1035 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1036 { 1037 void *a_cp, *b_cp; 1038 vm_offset_t a_pg_offset, b_pg_offset; 1039 int cnt; 1040 1041 while (xfersize > 0) { 1042 a_pg_offset = a_offset & PAGE_MASK; 1043 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1044 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1045 a_pg_offset; 1046 b_pg_offset = b_offset & PAGE_MASK; 1047 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1048 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1049 b_pg_offset; 1050 bcopy(a_cp, b_cp, cnt); 1051 a_offset += cnt; 1052 b_offset += cnt; 1053 xfersize -= cnt; 1054 } 1055 } 1056 1057 /* 1058 * Zero a page of physical memory by temporarily mapping it into the tlb. 1059 */ 1060 void 1061 moea_zero_page(mmu_t mmu, vm_page_t m) 1062 { 1063 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1064 1065 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1066 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1067 } 1068 1069 void 1070 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1071 { 1072 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1073 void *va = (void *)(pa + off); 1074 1075 bzero(va, size); 1076 } 1077 1078 void 1079 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1080 { 1081 1082 moea_zero_page(mmu, m); 1083 } 1084 1085 /* 1086 * Map the given physical page at the specified virtual address in the 1087 * target pmap with the protection requested. If specified the page 1088 * will be wired down. 1089 */ 1090 int 1091 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1092 u_int flags, int8_t psind) 1093 { 1094 int error; 1095 1096 for (;;) { 1097 rw_wlock(&pvh_global_lock); 1098 PMAP_LOCK(pmap); 1099 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1100 rw_wunlock(&pvh_global_lock); 1101 PMAP_UNLOCK(pmap); 1102 if (error != ENOMEM) 1103 return (KERN_SUCCESS); 1104 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1105 return (KERN_RESOURCE_SHORTAGE); 1106 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1107 VM_WAIT; 1108 } 1109 } 1110 1111 /* 1112 * Map the given physical page at the specified virtual address in the 1113 * target pmap with the protection requested. If specified the page 1114 * will be wired down. 1115 * 1116 * The global pvh and pmap must be locked. 1117 */ 1118 static int 1119 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1120 u_int flags, int8_t psind __unused) 1121 { 1122 struct pvo_head *pvo_head; 1123 uma_zone_t zone; 1124 u_int pte_lo, pvo_flags; 1125 int error; 1126 1127 if (pmap_bootstrapped) 1128 rw_assert(&pvh_global_lock, RA_WLOCKED); 1129 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1130 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1131 VM_OBJECT_ASSERT_LOCKED(m->object); 1132 1133 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1134 pvo_head = &moea_pvo_kunmanaged; 1135 zone = moea_upvo_zone; 1136 pvo_flags = 0; 1137 } else { 1138 pvo_head = vm_page_to_pvoh(m); 1139 zone = moea_mpvo_zone; 1140 pvo_flags = PVO_MANAGED; 1141 } 1142 1143 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1144 1145 if (prot & VM_PROT_WRITE) { 1146 pte_lo |= PTE_BW; 1147 if (pmap_bootstrapped && 1148 (m->oflags & VPO_UNMANAGED) == 0) 1149 vm_page_aflag_set(m, PGA_WRITEABLE); 1150 } else 1151 pte_lo |= PTE_BR; 1152 1153 if ((flags & PMAP_ENTER_WIRED) != 0) 1154 pvo_flags |= PVO_WIRED; 1155 1156 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1157 pte_lo, pvo_flags); 1158 1159 /* 1160 * Flush the real page from the instruction cache. This has be done 1161 * for all user mappings to prevent information leakage via the 1162 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1163 * mapping for a page. 1164 */ 1165 if (pmap != kernel_pmap && error == ENOENT && 1166 (pte_lo & (PTE_I | PTE_G)) == 0) 1167 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1168 1169 return (error); 1170 } 1171 1172 /* 1173 * Maps a sequence of resident pages belonging to the same object. 1174 * The sequence begins with the given page m_start. This page is 1175 * mapped at the given virtual address start. Each subsequent page is 1176 * mapped at a virtual address that is offset from start by the same 1177 * amount as the page is offset from m_start within the object. The 1178 * last page in the sequence is the page with the largest offset from 1179 * m_start that can be mapped at a virtual address less than the given 1180 * virtual address end. Not every virtual page between start and end 1181 * is mapped; only those for which a resident page exists with the 1182 * corresponding offset from m_start are mapped. 1183 */ 1184 void 1185 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1186 vm_page_t m_start, vm_prot_t prot) 1187 { 1188 vm_page_t m; 1189 vm_pindex_t diff, psize; 1190 1191 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1192 1193 psize = atop(end - start); 1194 m = m_start; 1195 rw_wlock(&pvh_global_lock); 1196 PMAP_LOCK(pm); 1197 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1198 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1199 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1200 m = TAILQ_NEXT(m, listq); 1201 } 1202 rw_wunlock(&pvh_global_lock); 1203 PMAP_UNLOCK(pm); 1204 } 1205 1206 void 1207 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1208 vm_prot_t prot) 1209 { 1210 1211 rw_wlock(&pvh_global_lock); 1212 PMAP_LOCK(pm); 1213 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1214 0, 0); 1215 rw_wunlock(&pvh_global_lock); 1216 PMAP_UNLOCK(pm); 1217 } 1218 1219 vm_paddr_t 1220 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1221 { 1222 struct pvo_entry *pvo; 1223 vm_paddr_t pa; 1224 1225 PMAP_LOCK(pm); 1226 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1227 if (pvo == NULL) 1228 pa = 0; 1229 else 1230 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1231 PMAP_UNLOCK(pm); 1232 return (pa); 1233 } 1234 1235 /* 1236 * Atomically extract and hold the physical page with the given 1237 * pmap and virtual address pair if that mapping permits the given 1238 * protection. 1239 */ 1240 vm_page_t 1241 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1242 { 1243 struct pvo_entry *pvo; 1244 vm_page_t m; 1245 vm_paddr_t pa; 1246 1247 m = NULL; 1248 pa = 0; 1249 PMAP_LOCK(pmap); 1250 retry: 1251 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1252 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1253 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1254 (prot & VM_PROT_WRITE) == 0)) { 1255 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1256 goto retry; 1257 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1258 vm_page_hold(m); 1259 } 1260 PA_UNLOCK_COND(pa); 1261 PMAP_UNLOCK(pmap); 1262 return (m); 1263 } 1264 1265 void 1266 moea_init(mmu_t mmu) 1267 { 1268 1269 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1270 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1271 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1272 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1273 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1274 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1275 moea_initialized = TRUE; 1276 } 1277 1278 boolean_t 1279 moea_is_referenced(mmu_t mmu, vm_page_t m) 1280 { 1281 boolean_t rv; 1282 1283 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1284 ("moea_is_referenced: page %p is not managed", m)); 1285 rw_wlock(&pvh_global_lock); 1286 rv = moea_query_bit(m, PTE_REF); 1287 rw_wunlock(&pvh_global_lock); 1288 return (rv); 1289 } 1290 1291 boolean_t 1292 moea_is_modified(mmu_t mmu, vm_page_t m) 1293 { 1294 boolean_t rv; 1295 1296 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1297 ("moea_is_modified: page %p is not managed", m)); 1298 1299 /* 1300 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1301 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1302 * is clear, no PTEs can have PTE_CHG set. 1303 */ 1304 VM_OBJECT_ASSERT_WLOCKED(m->object); 1305 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1306 return (FALSE); 1307 rw_wlock(&pvh_global_lock); 1308 rv = moea_query_bit(m, PTE_CHG); 1309 rw_wunlock(&pvh_global_lock); 1310 return (rv); 1311 } 1312 1313 boolean_t 1314 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1315 { 1316 struct pvo_entry *pvo; 1317 boolean_t rv; 1318 1319 PMAP_LOCK(pmap); 1320 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1321 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1322 PMAP_UNLOCK(pmap); 1323 return (rv); 1324 } 1325 1326 void 1327 moea_clear_modify(mmu_t mmu, vm_page_t m) 1328 { 1329 1330 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1331 ("moea_clear_modify: page %p is not managed", m)); 1332 VM_OBJECT_ASSERT_WLOCKED(m->object); 1333 KASSERT(!vm_page_xbusied(m), 1334 ("moea_clear_modify: page %p is exclusive busy", m)); 1335 1336 /* 1337 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1338 * set. If the object containing the page is locked and the page is 1339 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1340 */ 1341 if ((m->aflags & PGA_WRITEABLE) == 0) 1342 return; 1343 rw_wlock(&pvh_global_lock); 1344 moea_clear_bit(m, PTE_CHG); 1345 rw_wunlock(&pvh_global_lock); 1346 } 1347 1348 /* 1349 * Clear the write and modified bits in each of the given page's mappings. 1350 */ 1351 void 1352 moea_remove_write(mmu_t mmu, vm_page_t m) 1353 { 1354 struct pvo_entry *pvo; 1355 struct pte *pt; 1356 pmap_t pmap; 1357 u_int lo; 1358 1359 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1360 ("moea_remove_write: page %p is not managed", m)); 1361 1362 /* 1363 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1364 * set by another thread while the object is locked. Thus, 1365 * if PGA_WRITEABLE is clear, no page table entries need updating. 1366 */ 1367 VM_OBJECT_ASSERT_WLOCKED(m->object); 1368 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1369 return; 1370 rw_wlock(&pvh_global_lock); 1371 lo = moea_attr_fetch(m); 1372 powerpc_sync(); 1373 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1374 pmap = pvo->pvo_pmap; 1375 PMAP_LOCK(pmap); 1376 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1377 pt = moea_pvo_to_pte(pvo, -1); 1378 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1379 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1380 if (pt != NULL) { 1381 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1382 lo |= pvo->pvo_pte.pte.pte_lo; 1383 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1384 moea_pte_change(pt, &pvo->pvo_pte.pte, 1385 pvo->pvo_vaddr); 1386 mtx_unlock(&moea_table_mutex); 1387 } 1388 } 1389 PMAP_UNLOCK(pmap); 1390 } 1391 if ((lo & PTE_CHG) != 0) { 1392 moea_attr_clear(m, PTE_CHG); 1393 vm_page_dirty(m); 1394 } 1395 vm_page_aflag_clear(m, PGA_WRITEABLE); 1396 rw_wunlock(&pvh_global_lock); 1397 } 1398 1399 /* 1400 * moea_ts_referenced: 1401 * 1402 * Return a count of reference bits for a page, clearing those bits. 1403 * It is not necessary for every reference bit to be cleared, but it 1404 * is necessary that 0 only be returned when there are truly no 1405 * reference bits set. 1406 * 1407 * XXX: The exact number of bits to check and clear is a matter that 1408 * should be tested and standardized at some point in the future for 1409 * optimal aging of shared pages. 1410 */ 1411 int 1412 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1413 { 1414 int count; 1415 1416 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1417 ("moea_ts_referenced: page %p is not managed", m)); 1418 rw_wlock(&pvh_global_lock); 1419 count = moea_clear_bit(m, PTE_REF); 1420 rw_wunlock(&pvh_global_lock); 1421 return (count); 1422 } 1423 1424 /* 1425 * Modify the WIMG settings of all mappings for a page. 1426 */ 1427 void 1428 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1429 { 1430 struct pvo_entry *pvo; 1431 struct pvo_head *pvo_head; 1432 struct pte *pt; 1433 pmap_t pmap; 1434 u_int lo; 1435 1436 if ((m->oflags & VPO_UNMANAGED) != 0) { 1437 m->md.mdpg_cache_attrs = ma; 1438 return; 1439 } 1440 1441 rw_wlock(&pvh_global_lock); 1442 pvo_head = vm_page_to_pvoh(m); 1443 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1444 1445 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1446 pmap = pvo->pvo_pmap; 1447 PMAP_LOCK(pmap); 1448 pt = moea_pvo_to_pte(pvo, -1); 1449 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1450 pvo->pvo_pte.pte.pte_lo |= lo; 1451 if (pt != NULL) { 1452 moea_pte_change(pt, &pvo->pvo_pte.pte, 1453 pvo->pvo_vaddr); 1454 if (pvo->pvo_pmap == kernel_pmap) 1455 isync(); 1456 } 1457 mtx_unlock(&moea_table_mutex); 1458 PMAP_UNLOCK(pmap); 1459 } 1460 m->md.mdpg_cache_attrs = ma; 1461 rw_wunlock(&pvh_global_lock); 1462 } 1463 1464 /* 1465 * Map a wired page into kernel virtual address space. 1466 */ 1467 void 1468 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1469 { 1470 1471 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1472 } 1473 1474 void 1475 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1476 { 1477 u_int pte_lo; 1478 int error; 1479 1480 #if 0 1481 if (va < VM_MIN_KERNEL_ADDRESS) 1482 panic("moea_kenter: attempt to enter non-kernel address %#x", 1483 va); 1484 #endif 1485 1486 pte_lo = moea_calc_wimg(pa, ma); 1487 1488 PMAP_LOCK(kernel_pmap); 1489 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1490 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1491 1492 if (error != 0 && error != ENOENT) 1493 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1494 pa, error); 1495 1496 PMAP_UNLOCK(kernel_pmap); 1497 } 1498 1499 /* 1500 * Extract the physical page address associated with the given kernel virtual 1501 * address. 1502 */ 1503 vm_paddr_t 1504 moea_kextract(mmu_t mmu, vm_offset_t va) 1505 { 1506 struct pvo_entry *pvo; 1507 vm_paddr_t pa; 1508 1509 /* 1510 * Allow direct mappings on 32-bit OEA 1511 */ 1512 if (va < VM_MIN_KERNEL_ADDRESS) { 1513 return (va); 1514 } 1515 1516 PMAP_LOCK(kernel_pmap); 1517 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1518 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1519 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1520 PMAP_UNLOCK(kernel_pmap); 1521 return (pa); 1522 } 1523 1524 /* 1525 * Remove a wired page from kernel virtual address space. 1526 */ 1527 void 1528 moea_kremove(mmu_t mmu, vm_offset_t va) 1529 { 1530 1531 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1532 } 1533 1534 /* 1535 * Map a range of physical addresses into kernel virtual address space. 1536 * 1537 * The value passed in *virt is a suggested virtual address for the mapping. 1538 * Architectures which can support a direct-mapped physical to virtual region 1539 * can return the appropriate address within that region, leaving '*virt' 1540 * unchanged. We cannot and therefore do not; *virt is updated with the 1541 * first usable address after the mapped region. 1542 */ 1543 vm_offset_t 1544 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1545 vm_paddr_t pa_end, int prot) 1546 { 1547 vm_offset_t sva, va; 1548 1549 sva = *virt; 1550 va = sva; 1551 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1552 moea_kenter(mmu, va, pa_start); 1553 *virt = va; 1554 return (sva); 1555 } 1556 1557 /* 1558 * Returns true if the pmap's pv is one of the first 1559 * 16 pvs linked to from this page. This count may 1560 * be changed upwards or downwards in the future; it 1561 * is only necessary that true be returned for a small 1562 * subset of pmaps for proper page aging. 1563 */ 1564 boolean_t 1565 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1566 { 1567 int loops; 1568 struct pvo_entry *pvo; 1569 boolean_t rv; 1570 1571 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1572 ("moea_page_exists_quick: page %p is not managed", m)); 1573 loops = 0; 1574 rv = FALSE; 1575 rw_wlock(&pvh_global_lock); 1576 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1577 if (pvo->pvo_pmap == pmap) { 1578 rv = TRUE; 1579 break; 1580 } 1581 if (++loops >= 16) 1582 break; 1583 } 1584 rw_wunlock(&pvh_global_lock); 1585 return (rv); 1586 } 1587 1588 /* 1589 * Return the number of managed mappings to the given physical page 1590 * that are wired. 1591 */ 1592 int 1593 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1594 { 1595 struct pvo_entry *pvo; 1596 int count; 1597 1598 count = 0; 1599 if ((m->oflags & VPO_UNMANAGED) != 0) 1600 return (count); 1601 rw_wlock(&pvh_global_lock); 1602 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1603 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1604 count++; 1605 rw_wunlock(&pvh_global_lock); 1606 return (count); 1607 } 1608 1609 static u_int moea_vsidcontext; 1610 1611 void 1612 moea_pinit(mmu_t mmu, pmap_t pmap) 1613 { 1614 int i, mask; 1615 u_int entropy; 1616 1617 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1618 RB_INIT(&pmap->pmap_pvo); 1619 1620 entropy = 0; 1621 __asm __volatile("mftb %0" : "=r"(entropy)); 1622 1623 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1624 == NULL) { 1625 pmap->pmap_phys = pmap; 1626 } 1627 1628 1629 mtx_lock(&moea_vsid_mutex); 1630 /* 1631 * Allocate some segment registers for this pmap. 1632 */ 1633 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1634 u_int hash, n; 1635 1636 /* 1637 * Create a new value by mutiplying by a prime and adding in 1638 * entropy from the timebase register. This is to make the 1639 * VSID more random so that the PT hash function collides 1640 * less often. (Note that the prime casues gcc to do shifts 1641 * instead of a multiply.) 1642 */ 1643 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1644 hash = moea_vsidcontext & (NPMAPS - 1); 1645 if (hash == 0) /* 0 is special, avoid it */ 1646 continue; 1647 n = hash >> 5; 1648 mask = 1 << (hash & (VSID_NBPW - 1)); 1649 hash = (moea_vsidcontext & 0xfffff); 1650 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1651 /* anything free in this bucket? */ 1652 if (moea_vsid_bitmap[n] == 0xffffffff) { 1653 entropy = (moea_vsidcontext >> 20); 1654 continue; 1655 } 1656 i = ffs(~moea_vsid_bitmap[n]) - 1; 1657 mask = 1 << i; 1658 hash &= 0xfffff & ~(VSID_NBPW - 1); 1659 hash |= i; 1660 } 1661 KASSERT(!(moea_vsid_bitmap[n] & mask), 1662 ("Allocating in-use VSID group %#x\n", hash)); 1663 moea_vsid_bitmap[n] |= mask; 1664 for (i = 0; i < 16; i++) 1665 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1666 mtx_unlock(&moea_vsid_mutex); 1667 return; 1668 } 1669 1670 mtx_unlock(&moea_vsid_mutex); 1671 panic("moea_pinit: out of segments"); 1672 } 1673 1674 /* 1675 * Initialize the pmap associated with process 0. 1676 */ 1677 void 1678 moea_pinit0(mmu_t mmu, pmap_t pm) 1679 { 1680 1681 PMAP_LOCK_INIT(pm); 1682 moea_pinit(mmu, pm); 1683 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1684 } 1685 1686 /* 1687 * Set the physical protection on the specified range of this map as requested. 1688 */ 1689 void 1690 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1691 vm_prot_t prot) 1692 { 1693 struct pvo_entry *pvo, *tpvo, key; 1694 struct pte *pt; 1695 1696 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1697 ("moea_protect: non current pmap")); 1698 1699 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1700 moea_remove(mmu, pm, sva, eva); 1701 return; 1702 } 1703 1704 rw_wlock(&pvh_global_lock); 1705 PMAP_LOCK(pm); 1706 key.pvo_vaddr = sva; 1707 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1708 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1709 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1710 1711 /* 1712 * Grab the PTE pointer before we diddle with the cached PTE 1713 * copy. 1714 */ 1715 pt = moea_pvo_to_pte(pvo, -1); 1716 /* 1717 * Change the protection of the page. 1718 */ 1719 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1720 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1721 1722 /* 1723 * If the PVO is in the page table, update that pte as well. 1724 */ 1725 if (pt != NULL) { 1726 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1727 mtx_unlock(&moea_table_mutex); 1728 } 1729 } 1730 rw_wunlock(&pvh_global_lock); 1731 PMAP_UNLOCK(pm); 1732 } 1733 1734 /* 1735 * Map a list of wired pages into kernel virtual address space. This is 1736 * intended for temporary mappings which do not need page modification or 1737 * references recorded. Existing mappings in the region are overwritten. 1738 */ 1739 void 1740 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1741 { 1742 vm_offset_t va; 1743 1744 va = sva; 1745 while (count-- > 0) { 1746 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1747 va += PAGE_SIZE; 1748 m++; 1749 } 1750 } 1751 1752 /* 1753 * Remove page mappings from kernel virtual address space. Intended for 1754 * temporary mappings entered by moea_qenter. 1755 */ 1756 void 1757 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1758 { 1759 vm_offset_t va; 1760 1761 va = sva; 1762 while (count-- > 0) { 1763 moea_kremove(mmu, va); 1764 va += PAGE_SIZE; 1765 } 1766 } 1767 1768 void 1769 moea_release(mmu_t mmu, pmap_t pmap) 1770 { 1771 int idx, mask; 1772 1773 /* 1774 * Free segment register's VSID 1775 */ 1776 if (pmap->pm_sr[0] == 0) 1777 panic("moea_release"); 1778 1779 mtx_lock(&moea_vsid_mutex); 1780 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1781 mask = 1 << (idx % VSID_NBPW); 1782 idx /= VSID_NBPW; 1783 moea_vsid_bitmap[idx] &= ~mask; 1784 mtx_unlock(&moea_vsid_mutex); 1785 } 1786 1787 /* 1788 * Remove the given range of addresses from the specified map. 1789 */ 1790 void 1791 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1792 { 1793 struct pvo_entry *pvo, *tpvo, key; 1794 1795 rw_wlock(&pvh_global_lock); 1796 PMAP_LOCK(pm); 1797 key.pvo_vaddr = sva; 1798 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1799 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1800 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1801 moea_pvo_remove(pvo, -1); 1802 } 1803 PMAP_UNLOCK(pm); 1804 rw_wunlock(&pvh_global_lock); 1805 } 1806 1807 /* 1808 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1809 * will reflect changes in pte's back to the vm_page. 1810 */ 1811 void 1812 moea_remove_all(mmu_t mmu, vm_page_t m) 1813 { 1814 struct pvo_head *pvo_head; 1815 struct pvo_entry *pvo, *next_pvo; 1816 pmap_t pmap; 1817 1818 rw_wlock(&pvh_global_lock); 1819 pvo_head = vm_page_to_pvoh(m); 1820 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1821 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1822 1823 pmap = pvo->pvo_pmap; 1824 PMAP_LOCK(pmap); 1825 moea_pvo_remove(pvo, -1); 1826 PMAP_UNLOCK(pmap); 1827 } 1828 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1829 moea_attr_clear(m, PTE_CHG); 1830 vm_page_dirty(m); 1831 } 1832 vm_page_aflag_clear(m, PGA_WRITEABLE); 1833 rw_wunlock(&pvh_global_lock); 1834 } 1835 1836 /* 1837 * Allocate a physical page of memory directly from the phys_avail map. 1838 * Can only be called from moea_bootstrap before avail start and end are 1839 * calculated. 1840 */ 1841 static vm_offset_t 1842 moea_bootstrap_alloc(vm_size_t size, u_int align) 1843 { 1844 vm_offset_t s, e; 1845 int i, j; 1846 1847 size = round_page(size); 1848 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1849 if (align != 0) 1850 s = (phys_avail[i] + align - 1) & ~(align - 1); 1851 else 1852 s = phys_avail[i]; 1853 e = s + size; 1854 1855 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1856 continue; 1857 1858 if (s == phys_avail[i]) { 1859 phys_avail[i] += size; 1860 } else if (e == phys_avail[i + 1]) { 1861 phys_avail[i + 1] -= size; 1862 } else { 1863 for (j = phys_avail_count * 2; j > i; j -= 2) { 1864 phys_avail[j] = phys_avail[j - 2]; 1865 phys_avail[j + 1] = phys_avail[j - 1]; 1866 } 1867 1868 phys_avail[i + 3] = phys_avail[i + 1]; 1869 phys_avail[i + 1] = s; 1870 phys_avail[i + 2] = e; 1871 phys_avail_count++; 1872 } 1873 1874 return (s); 1875 } 1876 panic("moea_bootstrap_alloc: could not allocate memory"); 1877 } 1878 1879 static void 1880 moea_syncicache(vm_offset_t pa, vm_size_t len) 1881 { 1882 __syncicache((void *)pa, len); 1883 } 1884 1885 static int 1886 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1887 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1888 { 1889 struct pvo_entry *pvo; 1890 u_int sr; 1891 int first; 1892 u_int ptegidx; 1893 int i; 1894 int bootstrap; 1895 1896 moea_pvo_enter_calls++; 1897 first = 0; 1898 bootstrap = 0; 1899 1900 /* 1901 * Compute the PTE Group index. 1902 */ 1903 va &= ~ADDR_POFF; 1904 sr = va_to_sr(pm->pm_sr, va); 1905 ptegidx = va_to_pteg(sr, va); 1906 1907 /* 1908 * Remove any existing mapping for this page. Reuse the pvo entry if 1909 * there is a mapping. 1910 */ 1911 mtx_lock(&moea_table_mutex); 1912 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1913 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1914 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1915 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1916 (pte_lo & PTE_PP)) { 1917 /* 1918 * The PTE is not changing. Instead, this may 1919 * be a request to change the mapping's wired 1920 * attribute. 1921 */ 1922 mtx_unlock(&moea_table_mutex); 1923 if ((flags & PVO_WIRED) != 0 && 1924 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1925 pvo->pvo_vaddr |= PVO_WIRED; 1926 pm->pm_stats.wired_count++; 1927 } else if ((flags & PVO_WIRED) == 0 && 1928 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1929 pvo->pvo_vaddr &= ~PVO_WIRED; 1930 pm->pm_stats.wired_count--; 1931 } 1932 return (0); 1933 } 1934 moea_pvo_remove(pvo, -1); 1935 break; 1936 } 1937 } 1938 1939 /* 1940 * If we aren't overwriting a mapping, try to allocate. 1941 */ 1942 if (moea_initialized) { 1943 pvo = uma_zalloc(zone, M_NOWAIT); 1944 } else { 1945 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1946 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1947 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1948 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1949 } 1950 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1951 moea_bpvo_pool_index++; 1952 bootstrap = 1; 1953 } 1954 1955 if (pvo == NULL) { 1956 mtx_unlock(&moea_table_mutex); 1957 return (ENOMEM); 1958 } 1959 1960 moea_pvo_entries++; 1961 pvo->pvo_vaddr = va; 1962 pvo->pvo_pmap = pm; 1963 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1964 pvo->pvo_vaddr &= ~ADDR_POFF; 1965 if (flags & PVO_WIRED) 1966 pvo->pvo_vaddr |= PVO_WIRED; 1967 if (pvo_head != &moea_pvo_kunmanaged) 1968 pvo->pvo_vaddr |= PVO_MANAGED; 1969 if (bootstrap) 1970 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1971 1972 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1973 1974 /* 1975 * Add to pmap list 1976 */ 1977 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1978 1979 /* 1980 * Remember if the list was empty and therefore will be the first 1981 * item. 1982 */ 1983 if (LIST_FIRST(pvo_head) == NULL) 1984 first = 1; 1985 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1986 1987 if (pvo->pvo_vaddr & PVO_WIRED) 1988 pm->pm_stats.wired_count++; 1989 pm->pm_stats.resident_count++; 1990 1991 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1992 KASSERT(i < 8, ("Invalid PTE index")); 1993 if (i >= 0) { 1994 PVO_PTEGIDX_SET(pvo, i); 1995 } else { 1996 panic("moea_pvo_enter: overflow"); 1997 moea_pte_overflow++; 1998 } 1999 mtx_unlock(&moea_table_mutex); 2000 2001 return (first ? ENOENT : 0); 2002 } 2003 2004 static void 2005 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2006 { 2007 struct pte *pt; 2008 2009 /* 2010 * If there is an active pte entry, we need to deactivate it (and 2011 * save the ref & cfg bits). 2012 */ 2013 pt = moea_pvo_to_pte(pvo, pteidx); 2014 if (pt != NULL) { 2015 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2016 mtx_unlock(&moea_table_mutex); 2017 PVO_PTEGIDX_CLR(pvo); 2018 } else { 2019 moea_pte_overflow--; 2020 } 2021 2022 /* 2023 * Update our statistics. 2024 */ 2025 pvo->pvo_pmap->pm_stats.resident_count--; 2026 if (pvo->pvo_vaddr & PVO_WIRED) 2027 pvo->pvo_pmap->pm_stats.wired_count--; 2028 2029 /* 2030 * Save the REF/CHG bits into their cache if the page is managed. 2031 */ 2032 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2033 struct vm_page *pg; 2034 2035 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2036 if (pg != NULL) { 2037 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2038 (PTE_REF | PTE_CHG)); 2039 } 2040 } 2041 2042 /* 2043 * Remove this PVO from the PV and pmap lists. 2044 */ 2045 LIST_REMOVE(pvo, pvo_vlink); 2046 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2047 2048 /* 2049 * Remove this from the overflow list and return it to the pool 2050 * if we aren't going to reuse it. 2051 */ 2052 LIST_REMOVE(pvo, pvo_olink); 2053 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2054 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2055 moea_upvo_zone, pvo); 2056 moea_pvo_entries--; 2057 moea_pvo_remove_calls++; 2058 } 2059 2060 static __inline int 2061 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2062 { 2063 int pteidx; 2064 2065 /* 2066 * We can find the actual pte entry without searching by grabbing 2067 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2068 * noticing the HID bit. 2069 */ 2070 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2071 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2072 pteidx ^= moea_pteg_mask * 8; 2073 2074 return (pteidx); 2075 } 2076 2077 static struct pvo_entry * 2078 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2079 { 2080 struct pvo_entry *pvo; 2081 int ptegidx; 2082 u_int sr; 2083 2084 va &= ~ADDR_POFF; 2085 sr = va_to_sr(pm->pm_sr, va); 2086 ptegidx = va_to_pteg(sr, va); 2087 2088 mtx_lock(&moea_table_mutex); 2089 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2090 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2091 if (pteidx_p) 2092 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2093 break; 2094 } 2095 } 2096 mtx_unlock(&moea_table_mutex); 2097 2098 return (pvo); 2099 } 2100 2101 static struct pte * 2102 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2103 { 2104 struct pte *pt; 2105 2106 /* 2107 * If we haven't been supplied the ptegidx, calculate it. 2108 */ 2109 if (pteidx == -1) { 2110 int ptegidx; 2111 u_int sr; 2112 2113 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2114 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2115 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2116 } 2117 2118 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2119 mtx_lock(&moea_table_mutex); 2120 2121 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2122 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2123 "valid pte index", pvo); 2124 } 2125 2126 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2127 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2128 "pvo but no valid pte", pvo); 2129 } 2130 2131 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2132 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2133 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2134 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2135 } 2136 2137 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2138 != 0) { 2139 panic("moea_pvo_to_pte: pvo %p pte does not match " 2140 "pte %p in moea_pteg_table", pvo, pt); 2141 } 2142 2143 mtx_assert(&moea_table_mutex, MA_OWNED); 2144 return (pt); 2145 } 2146 2147 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2148 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2149 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2150 } 2151 2152 mtx_unlock(&moea_table_mutex); 2153 return (NULL); 2154 } 2155 2156 /* 2157 * XXX: THIS STUFF SHOULD BE IN pte.c? 2158 */ 2159 int 2160 moea_pte_spill(vm_offset_t addr) 2161 { 2162 struct pvo_entry *source_pvo, *victim_pvo; 2163 struct pvo_entry *pvo; 2164 int ptegidx, i, j; 2165 u_int sr; 2166 struct pteg *pteg; 2167 struct pte *pt; 2168 2169 moea_pte_spills++; 2170 2171 sr = mfsrin(addr); 2172 ptegidx = va_to_pteg(sr, addr); 2173 2174 /* 2175 * Have to substitute some entry. Use the primary hash for this. 2176 * Use low bits of timebase as random generator. 2177 */ 2178 pteg = &moea_pteg_table[ptegidx]; 2179 mtx_lock(&moea_table_mutex); 2180 __asm __volatile("mftb %0" : "=r"(i)); 2181 i &= 7; 2182 pt = &pteg->pt[i]; 2183 2184 source_pvo = NULL; 2185 victim_pvo = NULL; 2186 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2187 /* 2188 * We need to find a pvo entry for this address. 2189 */ 2190 if (source_pvo == NULL && 2191 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2192 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2193 /* 2194 * Now found an entry to be spilled into the pteg. 2195 * The PTE is now valid, so we know it's active. 2196 */ 2197 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2198 2199 if (j >= 0) { 2200 PVO_PTEGIDX_SET(pvo, j); 2201 moea_pte_overflow--; 2202 mtx_unlock(&moea_table_mutex); 2203 return (1); 2204 } 2205 2206 source_pvo = pvo; 2207 2208 if (victim_pvo != NULL) 2209 break; 2210 } 2211 2212 /* 2213 * We also need the pvo entry of the victim we are replacing 2214 * so save the R & C bits of the PTE. 2215 */ 2216 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2217 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2218 victim_pvo = pvo; 2219 if (source_pvo != NULL) 2220 break; 2221 } 2222 } 2223 2224 if (source_pvo == NULL) { 2225 mtx_unlock(&moea_table_mutex); 2226 return (0); 2227 } 2228 2229 if (victim_pvo == NULL) { 2230 if ((pt->pte_hi & PTE_HID) == 0) 2231 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2232 "entry", pt); 2233 2234 /* 2235 * If this is a secondary PTE, we need to search it's primary 2236 * pvo bucket for the matching PVO. 2237 */ 2238 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2239 pvo_olink) { 2240 /* 2241 * We also need the pvo entry of the victim we are 2242 * replacing so save the R & C bits of the PTE. 2243 */ 2244 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2245 victim_pvo = pvo; 2246 break; 2247 } 2248 } 2249 2250 if (victim_pvo == NULL) 2251 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2252 "entry", pt); 2253 } 2254 2255 /* 2256 * We are invalidating the TLB entry for the EA we are replacing even 2257 * though it's valid. If we don't, we lose any ref/chg bit changes 2258 * contained in the TLB entry. 2259 */ 2260 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2261 2262 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2263 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2264 2265 PVO_PTEGIDX_CLR(victim_pvo); 2266 PVO_PTEGIDX_SET(source_pvo, i); 2267 moea_pte_replacements++; 2268 2269 mtx_unlock(&moea_table_mutex); 2270 return (1); 2271 } 2272 2273 static __inline struct pvo_entry * 2274 moea_pte_spillable_ident(u_int ptegidx) 2275 { 2276 struct pte *pt; 2277 struct pvo_entry *pvo_walk, *pvo = NULL; 2278 2279 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2280 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2281 continue; 2282 2283 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2284 continue; 2285 2286 pt = moea_pvo_to_pte(pvo_walk, -1); 2287 2288 if (pt == NULL) 2289 continue; 2290 2291 pvo = pvo_walk; 2292 2293 mtx_unlock(&moea_table_mutex); 2294 if (!(pt->pte_lo & PTE_REF)) 2295 return (pvo_walk); 2296 } 2297 2298 return (pvo); 2299 } 2300 2301 static int 2302 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2303 { 2304 struct pte *pt; 2305 struct pvo_entry *victim_pvo; 2306 int i; 2307 int victim_idx; 2308 u_int pteg_bkpidx = ptegidx; 2309 2310 mtx_assert(&moea_table_mutex, MA_OWNED); 2311 2312 /* 2313 * First try primary hash. 2314 */ 2315 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2316 if ((pt->pte_hi & PTE_VALID) == 0) { 2317 pvo_pt->pte_hi &= ~PTE_HID; 2318 moea_pte_set(pt, pvo_pt); 2319 return (i); 2320 } 2321 } 2322 2323 /* 2324 * Now try secondary hash. 2325 */ 2326 ptegidx ^= moea_pteg_mask; 2327 2328 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2329 if ((pt->pte_hi & PTE_VALID) == 0) { 2330 pvo_pt->pte_hi |= PTE_HID; 2331 moea_pte_set(pt, pvo_pt); 2332 return (i); 2333 } 2334 } 2335 2336 /* Try again, but this time try to force a PTE out. */ 2337 ptegidx = pteg_bkpidx; 2338 2339 victim_pvo = moea_pte_spillable_ident(ptegidx); 2340 if (victim_pvo == NULL) { 2341 ptegidx ^= moea_pteg_mask; 2342 victim_pvo = moea_pte_spillable_ident(ptegidx); 2343 } 2344 2345 if (victim_pvo == NULL) { 2346 panic("moea_pte_insert: overflow"); 2347 return (-1); 2348 } 2349 2350 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2351 2352 if (pteg_bkpidx == ptegidx) 2353 pvo_pt->pte_hi &= ~PTE_HID; 2354 else 2355 pvo_pt->pte_hi |= PTE_HID; 2356 2357 /* 2358 * Synchronize the sacrifice PTE with its PVO, then mark both 2359 * invalid. The PVO will be reused when/if the VM system comes 2360 * here after a fault. 2361 */ 2362 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2363 2364 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2365 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2366 2367 /* 2368 * Set the new PTE. 2369 */ 2370 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2371 PVO_PTEGIDX_CLR(victim_pvo); 2372 moea_pte_overflow++; 2373 moea_pte_set(pt, pvo_pt); 2374 2375 return (victim_idx & 7); 2376 } 2377 2378 static boolean_t 2379 moea_query_bit(vm_page_t m, int ptebit) 2380 { 2381 struct pvo_entry *pvo; 2382 struct pte *pt; 2383 2384 rw_assert(&pvh_global_lock, RA_WLOCKED); 2385 if (moea_attr_fetch(m) & ptebit) 2386 return (TRUE); 2387 2388 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2389 2390 /* 2391 * See if we saved the bit off. If so, cache it and return 2392 * success. 2393 */ 2394 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2395 moea_attr_save(m, ptebit); 2396 return (TRUE); 2397 } 2398 } 2399 2400 /* 2401 * No luck, now go through the hard part of looking at the PTEs 2402 * themselves. Sync so that any pending REF/CHG bits are flushed to 2403 * the PTEs. 2404 */ 2405 powerpc_sync(); 2406 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2407 2408 /* 2409 * See if this pvo has a valid PTE. if so, fetch the 2410 * REF/CHG bits from the valid PTE. If the appropriate 2411 * ptebit is set, cache it and return success. 2412 */ 2413 pt = moea_pvo_to_pte(pvo, -1); 2414 if (pt != NULL) { 2415 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2416 mtx_unlock(&moea_table_mutex); 2417 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2418 moea_attr_save(m, ptebit); 2419 return (TRUE); 2420 } 2421 } 2422 } 2423 2424 return (FALSE); 2425 } 2426 2427 static u_int 2428 moea_clear_bit(vm_page_t m, int ptebit) 2429 { 2430 u_int count; 2431 struct pvo_entry *pvo; 2432 struct pte *pt; 2433 2434 rw_assert(&pvh_global_lock, RA_WLOCKED); 2435 2436 /* 2437 * Clear the cached value. 2438 */ 2439 moea_attr_clear(m, ptebit); 2440 2441 /* 2442 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2443 * we can reset the right ones). note that since the pvo entries and 2444 * list heads are accessed via BAT0 and are never placed in the page 2445 * table, we don't have to worry about further accesses setting the 2446 * REF/CHG bits. 2447 */ 2448 powerpc_sync(); 2449 2450 /* 2451 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2452 * valid pte clear the ptebit from the valid pte. 2453 */ 2454 count = 0; 2455 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2456 pt = moea_pvo_to_pte(pvo, -1); 2457 if (pt != NULL) { 2458 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2459 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2460 count++; 2461 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2462 } 2463 mtx_unlock(&moea_table_mutex); 2464 } 2465 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2466 } 2467 2468 return (count); 2469 } 2470 2471 /* 2472 * Return true if the physical range is encompassed by the battable[idx] 2473 */ 2474 static int 2475 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2476 { 2477 u_int prot; 2478 u_int32_t start; 2479 u_int32_t end; 2480 u_int32_t bat_ble; 2481 2482 /* 2483 * Return immediately if not a valid mapping 2484 */ 2485 if (!(battable[idx].batu & BAT_Vs)) 2486 return (EINVAL); 2487 2488 /* 2489 * The BAT entry must be cache-inhibited, guarded, and r/w 2490 * so it can function as an i/o page 2491 */ 2492 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2493 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2494 return (EPERM); 2495 2496 /* 2497 * The address should be within the BAT range. Assume that the 2498 * start address in the BAT has the correct alignment (thus 2499 * not requiring masking) 2500 */ 2501 start = battable[idx].batl & BAT_PBS; 2502 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2503 end = start | (bat_ble << 15) | 0x7fff; 2504 2505 if ((pa < start) || ((pa + size) > end)) 2506 return (ERANGE); 2507 2508 return (0); 2509 } 2510 2511 boolean_t 2512 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2513 { 2514 int i; 2515 2516 /* 2517 * This currently does not work for entries that 2518 * overlap 256M BAT segments. 2519 */ 2520 2521 for(i = 0; i < 16; i++) 2522 if (moea_bat_mapped(i, pa, size) == 0) 2523 return (0); 2524 2525 return (EFAULT); 2526 } 2527 2528 /* 2529 * Map a set of physical memory pages into the kernel virtual 2530 * address space. Return a pointer to where it is mapped. This 2531 * routine is intended to be used for mapping device memory, 2532 * NOT real memory. 2533 */ 2534 void * 2535 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2536 { 2537 2538 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2539 } 2540 2541 void * 2542 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2543 { 2544 vm_offset_t va, tmpva, ppa, offset; 2545 int i; 2546 2547 ppa = trunc_page(pa); 2548 offset = pa & PAGE_MASK; 2549 size = roundup(offset + size, PAGE_SIZE); 2550 2551 /* 2552 * If the physical address lies within a valid BAT table entry, 2553 * return the 1:1 mapping. This currently doesn't work 2554 * for regions that overlap 256M BAT segments. 2555 */ 2556 for (i = 0; i < 16; i++) { 2557 if (moea_bat_mapped(i, pa, size) == 0) 2558 return ((void *) pa); 2559 } 2560 2561 va = kva_alloc(size); 2562 if (!va) 2563 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2564 2565 for (tmpva = va; size > 0;) { 2566 moea_kenter_attr(mmu, tmpva, ppa, ma); 2567 tlbie(tmpva); 2568 size -= PAGE_SIZE; 2569 tmpva += PAGE_SIZE; 2570 ppa += PAGE_SIZE; 2571 } 2572 2573 return ((void *)(va + offset)); 2574 } 2575 2576 void 2577 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2578 { 2579 vm_offset_t base, offset; 2580 2581 /* 2582 * If this is outside kernel virtual space, then it's a 2583 * battable entry and doesn't require unmapping 2584 */ 2585 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2586 base = trunc_page(va); 2587 offset = va & PAGE_MASK; 2588 size = roundup(offset + size, PAGE_SIZE); 2589 kva_free(base, size); 2590 } 2591 } 2592 2593 static void 2594 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2595 { 2596 struct pvo_entry *pvo; 2597 vm_offset_t lim; 2598 vm_paddr_t pa; 2599 vm_size_t len; 2600 2601 PMAP_LOCK(pm); 2602 while (sz > 0) { 2603 lim = round_page(va); 2604 len = MIN(lim - va, sz); 2605 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2606 if (pvo != NULL) { 2607 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2608 (va & ADDR_POFF); 2609 moea_syncicache(pa, len); 2610 } 2611 va += len; 2612 sz -= len; 2613 } 2614 PMAP_UNLOCK(pm); 2615 } 2616 2617 void 2618 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2619 { 2620 2621 *va = (void *)pa; 2622 } 2623 2624 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2625 2626 void 2627 moea_scan_init(mmu_t mmu) 2628 { 2629 struct pvo_entry *pvo; 2630 vm_offset_t va; 2631 int i; 2632 2633 if (!do_minidump) { 2634 /* Initialize phys. segments for dumpsys(). */ 2635 memset(&dump_map, 0, sizeof(dump_map)); 2636 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2637 for (i = 0; i < pregions_sz; i++) { 2638 dump_map[i].pa_start = pregions[i].mr_start; 2639 dump_map[i].pa_size = pregions[i].mr_size; 2640 } 2641 return; 2642 } 2643 2644 /* Virtual segments for minidumps: */ 2645 memset(&dump_map, 0, sizeof(dump_map)); 2646 2647 /* 1st: kernel .data and .bss. */ 2648 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2649 dump_map[0].pa_size = 2650 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2651 2652 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2653 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2654 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2655 2656 /* 3rd: kernel VM. */ 2657 va = dump_map[1].pa_start + dump_map[1].pa_size; 2658 /* Find start of next chunk (from va). */ 2659 while (va < virtual_end) { 2660 /* Don't dump the buffer cache. */ 2661 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2662 va = kmi.buffer_eva; 2663 continue; 2664 } 2665 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2666 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2667 break; 2668 va += PAGE_SIZE; 2669 } 2670 if (va < virtual_end) { 2671 dump_map[2].pa_start = va; 2672 va += PAGE_SIZE; 2673 /* Find last page in chunk. */ 2674 while (va < virtual_end) { 2675 /* Don't run into the buffer cache. */ 2676 if (va == kmi.buffer_sva) 2677 break; 2678 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2679 NULL); 2680 if (pvo == NULL || 2681 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2682 break; 2683 va += PAGE_SIZE; 2684 } 2685 dump_map[2].pa_size = va - dump_map[2].pa_start; 2686 } 2687 } 2688