1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_pageout.h> 136 #include <vm/uma.h> 137 138 #include <machine/cpu.h> 139 #include <machine/platform.h> 140 #include <machine/bat.h> 141 #include <machine/frame.h> 142 #include <machine/md_var.h> 143 #include <machine/psl.h> 144 #include <machine/pte.h> 145 #include <machine/smp.h> 146 #include <machine/sr.h> 147 #include <machine/mmuvar.h> 148 #include <machine/trap.h> 149 150 #include "mmu_if.h" 151 152 #define MOEA_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 157 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 159 160 struct ofw_map { 161 vm_offset_t om_va; 162 vm_size_t om_len; 163 vm_offset_t om_pa; 164 u_int om_mode; 165 }; 166 167 extern unsigned char _etext[]; 168 extern unsigned char _end[]; 169 170 /* 171 * Map of physical memory regions. 172 */ 173 static struct mem_region *regions; 174 static struct mem_region *pregions; 175 static u_int phys_avail_count; 176 static int regions_sz, pregions_sz; 177 static struct ofw_map *translations; 178 179 /* 180 * Lock for the pteg and pvo tables. 181 */ 182 struct mtx moea_table_mutex; 183 struct mtx moea_vsid_mutex; 184 185 /* tlbie instruction synchronization */ 186 static struct mtx tlbie_mtx; 187 188 /* 189 * PTEG data. 190 */ 191 static struct pteg *moea_pteg_table; 192 u_int moea_pteg_count; 193 u_int moea_pteg_mask; 194 195 /* 196 * PVO data. 197 */ 198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 199 struct pvo_head moea_pvo_kunmanaged = 200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 201 202 static struct rwlock_padalign pvh_global_lock; 203 204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 206 207 #define BPVO_POOL_SIZE 32768 208 static struct pvo_entry *moea_bpvo_pool; 209 static int moea_bpvo_pool_index = 0; 210 211 #define VSID_NBPW (sizeof(u_int32_t) * 8) 212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 213 214 static boolean_t moea_initialized = FALSE; 215 216 /* 217 * Statistics. 218 */ 219 u_int moea_pte_valid = 0; 220 u_int moea_pte_overflow = 0; 221 u_int moea_pte_replacements = 0; 222 u_int moea_pvo_entries = 0; 223 u_int moea_pvo_enter_calls = 0; 224 u_int moea_pvo_remove_calls = 0; 225 u_int moea_pte_spills = 0; 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 227 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 229 &moea_pte_overflow, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 231 &moea_pte_replacements, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 233 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 235 &moea_pvo_enter_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 237 &moea_pvo_remove_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 239 &moea_pte_spills, 0, ""); 240 241 /* 242 * Allocate physical memory for use in moea_bootstrap. 243 */ 244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 245 246 /* 247 * PTE calls. 248 */ 249 static int moea_pte_insert(u_int, struct pte *); 250 251 /* 252 * PVO calls. 253 */ 254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 255 vm_offset_t, vm_paddr_t, u_int, int); 256 static void moea_pvo_remove(struct pvo_entry *, int); 257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 259 260 /* 261 * Utility routines. 262 */ 263 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 264 vm_prot_t, u_int, int8_t); 265 static void moea_syncicache(vm_paddr_t, vm_size_t); 266 static boolean_t moea_query_bit(vm_page_t, int); 267 static u_int moea_clear_bit(vm_page_t, int); 268 static void moea_kremove(mmu_t, vm_offset_t); 269 int moea_pte_spill(vm_offset_t); 270 271 /* 272 * Kernel MMU interface 273 */ 274 void moea_clear_modify(mmu_t, vm_page_t); 275 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 276 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 277 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 278 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 279 int8_t); 280 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 284 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 285 void moea_init(mmu_t); 286 boolean_t moea_is_modified(mmu_t, vm_page_t); 287 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288 boolean_t moea_is_referenced(mmu_t, vm_page_t); 289 int moea_ts_referenced(mmu_t, vm_page_t); 290 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 291 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 292 void moea_page_init(mmu_t, vm_page_t); 293 int moea_page_wired_mappings(mmu_t, vm_page_t); 294 void moea_pinit(mmu_t, pmap_t); 295 void moea_pinit0(mmu_t, pmap_t); 296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 298 void moea_qremove(mmu_t, vm_offset_t, int); 299 void moea_release(mmu_t, pmap_t); 300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(mmu_t, vm_page_t); 302 void moea_remove_write(mmu_t, vm_page_t); 303 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 304 void moea_zero_page(mmu_t, vm_page_t); 305 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 306 void moea_activate(mmu_t, struct thread *); 307 void moea_deactivate(mmu_t, struct thread *); 308 void moea_cpu_bootstrap(mmu_t, int); 309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 310 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 311 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 313 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 315 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 319 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 320 void moea_scan_init(mmu_t mmu); 321 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 322 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 323 static int moea_map_user_ptr(mmu_t mmu, pmap_t pm, 324 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 325 326 327 static mmu_method_t moea_methods[] = { 328 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 329 MMUMETHOD(mmu_copy_page, moea_copy_page), 330 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 331 MMUMETHOD(mmu_enter, moea_enter), 332 MMUMETHOD(mmu_enter_object, moea_enter_object), 333 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 334 MMUMETHOD(mmu_extract, moea_extract), 335 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 336 MMUMETHOD(mmu_init, moea_init), 337 MMUMETHOD(mmu_is_modified, moea_is_modified), 338 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 339 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 340 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 341 MMUMETHOD(mmu_map, moea_map), 342 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 343 MMUMETHOD(mmu_page_init, moea_page_init), 344 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 345 MMUMETHOD(mmu_pinit, moea_pinit), 346 MMUMETHOD(mmu_pinit0, moea_pinit0), 347 MMUMETHOD(mmu_protect, moea_protect), 348 MMUMETHOD(mmu_qenter, moea_qenter), 349 MMUMETHOD(mmu_qremove, moea_qremove), 350 MMUMETHOD(mmu_release, moea_release), 351 MMUMETHOD(mmu_remove, moea_remove), 352 MMUMETHOD(mmu_remove_all, moea_remove_all), 353 MMUMETHOD(mmu_remove_write, moea_remove_write), 354 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 355 MMUMETHOD(mmu_unwire, moea_unwire), 356 MMUMETHOD(mmu_zero_page, moea_zero_page), 357 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 358 MMUMETHOD(mmu_activate, moea_activate), 359 MMUMETHOD(mmu_deactivate, moea_deactivate), 360 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 361 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 362 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 363 364 /* Internal interfaces */ 365 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 366 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 367 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 368 MMUMETHOD(mmu_mapdev, moea_mapdev), 369 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 370 MMUMETHOD(mmu_kextract, moea_kextract), 371 MMUMETHOD(mmu_kenter, moea_kenter), 372 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 373 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 374 MMUMETHOD(mmu_scan_init, moea_scan_init), 375 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 376 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr), 377 378 { 0, 0 } 379 }; 380 381 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 382 383 static __inline uint32_t 384 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 385 { 386 uint32_t pte_lo; 387 int i; 388 389 if (ma != VM_MEMATTR_DEFAULT) { 390 switch (ma) { 391 case VM_MEMATTR_UNCACHEABLE: 392 return (PTE_I | PTE_G); 393 case VM_MEMATTR_CACHEABLE: 394 return (PTE_M); 395 case VM_MEMATTR_WRITE_COMBINING: 396 case VM_MEMATTR_WRITE_BACK: 397 case VM_MEMATTR_PREFETCHABLE: 398 return (PTE_I); 399 case VM_MEMATTR_WRITE_THROUGH: 400 return (PTE_W | PTE_M); 401 } 402 } 403 404 /* 405 * Assume the page is cache inhibited and access is guarded unless 406 * it's in our available memory array. 407 */ 408 pte_lo = PTE_I | PTE_G; 409 for (i = 0; i < pregions_sz; i++) { 410 if ((pa >= pregions[i].mr_start) && 411 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 412 pte_lo = PTE_M; 413 break; 414 } 415 } 416 417 return pte_lo; 418 } 419 420 static void 421 tlbie(vm_offset_t va) 422 { 423 424 mtx_lock_spin(&tlbie_mtx); 425 __asm __volatile("ptesync"); 426 __asm __volatile("tlbie %0" :: "r"(va)); 427 __asm __volatile("eieio; tlbsync; ptesync"); 428 mtx_unlock_spin(&tlbie_mtx); 429 } 430 431 static void 432 tlbia(void) 433 { 434 vm_offset_t va; 435 436 for (va = 0; va < 0x00040000; va += 0x00001000) { 437 __asm __volatile("tlbie %0" :: "r"(va)); 438 powerpc_sync(); 439 } 440 __asm __volatile("tlbsync"); 441 powerpc_sync(); 442 } 443 444 static __inline int 445 va_to_sr(u_int *sr, vm_offset_t va) 446 { 447 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 448 } 449 450 static __inline u_int 451 va_to_pteg(u_int sr, vm_offset_t addr) 452 { 453 u_int hash; 454 455 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 456 ADDR_PIDX_SHFT); 457 return (hash & moea_pteg_mask); 458 } 459 460 static __inline struct pvo_head * 461 vm_page_to_pvoh(vm_page_t m) 462 { 463 464 return (&m->md.mdpg_pvoh); 465 } 466 467 static __inline void 468 moea_attr_clear(vm_page_t m, int ptebit) 469 { 470 471 rw_assert(&pvh_global_lock, RA_WLOCKED); 472 m->md.mdpg_attrs &= ~ptebit; 473 } 474 475 static __inline int 476 moea_attr_fetch(vm_page_t m) 477 { 478 479 return (m->md.mdpg_attrs); 480 } 481 482 static __inline void 483 moea_attr_save(vm_page_t m, int ptebit) 484 { 485 486 rw_assert(&pvh_global_lock, RA_WLOCKED); 487 m->md.mdpg_attrs |= ptebit; 488 } 489 490 static __inline int 491 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 492 { 493 if (pt->pte_hi == pvo_pt->pte_hi) 494 return (1); 495 496 return (0); 497 } 498 499 static __inline int 500 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 501 { 502 return (pt->pte_hi & ~PTE_VALID) == 503 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 504 ((va >> ADDR_API_SHFT) & PTE_API) | which); 505 } 506 507 static __inline void 508 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 509 { 510 511 mtx_assert(&moea_table_mutex, MA_OWNED); 512 513 /* 514 * Construct a PTE. Default to IMB initially. Valid bit only gets 515 * set when the real pte is set in memory. 516 * 517 * Note: Don't set the valid bit for correct operation of tlb update. 518 */ 519 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 520 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 521 pt->pte_lo = pte_lo; 522 } 523 524 static __inline void 525 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 526 { 527 528 mtx_assert(&moea_table_mutex, MA_OWNED); 529 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 530 } 531 532 static __inline void 533 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 534 { 535 536 mtx_assert(&moea_table_mutex, MA_OWNED); 537 538 /* 539 * As shown in Section 7.6.3.2.3 540 */ 541 pt->pte_lo &= ~ptebit; 542 tlbie(va); 543 } 544 545 static __inline void 546 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 547 { 548 549 mtx_assert(&moea_table_mutex, MA_OWNED); 550 pvo_pt->pte_hi |= PTE_VALID; 551 552 /* 553 * Update the PTE as defined in section 7.6.3.1. 554 * Note that the REF/CHG bits are from pvo_pt and thus should have 555 * been saved so this routine can restore them (if desired). 556 */ 557 pt->pte_lo = pvo_pt->pte_lo; 558 powerpc_sync(); 559 pt->pte_hi = pvo_pt->pte_hi; 560 powerpc_sync(); 561 moea_pte_valid++; 562 } 563 564 static __inline void 565 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 566 { 567 568 mtx_assert(&moea_table_mutex, MA_OWNED); 569 pvo_pt->pte_hi &= ~PTE_VALID; 570 571 /* 572 * Force the reg & chg bits back into the PTEs. 573 */ 574 powerpc_sync(); 575 576 /* 577 * Invalidate the pte. 578 */ 579 pt->pte_hi &= ~PTE_VALID; 580 581 tlbie(va); 582 583 /* 584 * Save the reg & chg bits. 585 */ 586 moea_pte_synch(pt, pvo_pt); 587 moea_pte_valid--; 588 } 589 590 static __inline void 591 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 592 { 593 594 /* 595 * Invalidate the PTE 596 */ 597 moea_pte_unset(pt, pvo_pt, va); 598 moea_pte_set(pt, pvo_pt); 599 } 600 601 /* 602 * Quick sort callout for comparing memory regions. 603 */ 604 static int om_cmp(const void *a, const void *b); 605 606 static int 607 om_cmp(const void *a, const void *b) 608 { 609 const struct ofw_map *mapa; 610 const struct ofw_map *mapb; 611 612 mapa = a; 613 mapb = b; 614 if (mapa->om_pa < mapb->om_pa) 615 return (-1); 616 else if (mapa->om_pa > mapb->om_pa) 617 return (1); 618 else 619 return (0); 620 } 621 622 void 623 moea_cpu_bootstrap(mmu_t mmup, int ap) 624 { 625 u_int sdr; 626 int i; 627 628 if (ap) { 629 powerpc_sync(); 630 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 631 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 632 isync(); 633 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 634 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 635 isync(); 636 } 637 638 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 639 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 640 isync(); 641 642 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 643 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 644 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 645 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 646 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 647 isync(); 648 649 for (i = 0; i < 16; i++) 650 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 651 powerpc_sync(); 652 653 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 654 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 655 isync(); 656 657 tlbia(); 658 } 659 660 void 661 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 662 { 663 ihandle_t mmui; 664 phandle_t chosen, mmu; 665 int sz; 666 int i, j; 667 vm_size_t size, physsz, hwphyssz; 668 vm_offset_t pa, va, off; 669 void *dpcpu; 670 register_t msr; 671 672 /* 673 * Set up BAT0 to map the lowest 256 MB area 674 */ 675 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 676 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 677 678 /* 679 * Map PCI memory space. 680 */ 681 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 682 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 683 684 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 686 687 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 689 690 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 692 693 /* 694 * Map obio devices. 695 */ 696 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 697 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 698 699 /* 700 * Use an IBAT and a DBAT to map the bottom segment of memory 701 * where we are. Turn off instruction relocation temporarily 702 * to prevent faults while reprogramming the IBAT. 703 */ 704 msr = mfmsr(); 705 mtmsr(msr & ~PSL_IR); 706 __asm (".balign 32; \n" 707 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 708 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 709 :: "r"(battable[0].batu), "r"(battable[0].batl)); 710 mtmsr(msr); 711 712 /* map pci space */ 713 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 714 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 715 isync(); 716 717 /* set global direct map flag */ 718 hw_direct_map = 1; 719 720 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 721 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 722 723 for (i = 0; i < pregions_sz; i++) { 724 vm_offset_t pa; 725 vm_offset_t end; 726 727 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 728 pregions[i].mr_start, 729 pregions[i].mr_start + pregions[i].mr_size, 730 pregions[i].mr_size); 731 /* 732 * Install entries into the BAT table to allow all 733 * of physmem to be convered by on-demand BAT entries. 734 * The loop will sometimes set the same battable element 735 * twice, but that's fine since they won't be used for 736 * a while yet. 737 */ 738 pa = pregions[i].mr_start & 0xf0000000; 739 end = pregions[i].mr_start + pregions[i].mr_size; 740 do { 741 u_int n = pa >> ADDR_SR_SHFT; 742 743 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 744 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 745 pa += SEGMENT_LENGTH; 746 } while (pa < end); 747 } 748 749 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 750 panic("moea_bootstrap: phys_avail too small"); 751 752 phys_avail_count = 0; 753 physsz = 0; 754 hwphyssz = 0; 755 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 756 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 757 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 758 regions[i].mr_start + regions[i].mr_size, 759 regions[i].mr_size); 760 if (hwphyssz != 0 && 761 (physsz + regions[i].mr_size) >= hwphyssz) { 762 if (physsz < hwphyssz) { 763 phys_avail[j] = regions[i].mr_start; 764 phys_avail[j + 1] = regions[i].mr_start + 765 hwphyssz - physsz; 766 physsz = hwphyssz; 767 phys_avail_count++; 768 } 769 break; 770 } 771 phys_avail[j] = regions[i].mr_start; 772 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 773 phys_avail_count++; 774 physsz += regions[i].mr_size; 775 } 776 777 /* Check for overlap with the kernel and exception vectors */ 778 for (j = 0; j < 2*phys_avail_count; j+=2) { 779 if (phys_avail[j] < EXC_LAST) 780 phys_avail[j] += EXC_LAST; 781 782 if (kernelstart >= phys_avail[j] && 783 kernelstart < phys_avail[j+1]) { 784 if (kernelend < phys_avail[j+1]) { 785 phys_avail[2*phys_avail_count] = 786 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 787 phys_avail[2*phys_avail_count + 1] = 788 phys_avail[j+1]; 789 phys_avail_count++; 790 } 791 792 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 793 } 794 795 if (kernelend >= phys_avail[j] && 796 kernelend < phys_avail[j+1]) { 797 if (kernelstart > phys_avail[j]) { 798 phys_avail[2*phys_avail_count] = phys_avail[j]; 799 phys_avail[2*phys_avail_count + 1] = 800 kernelstart & ~PAGE_MASK; 801 phys_avail_count++; 802 } 803 804 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 805 } 806 } 807 808 physmem = btoc(physsz); 809 810 /* 811 * Allocate PTEG table. 812 */ 813 #ifdef PTEGCOUNT 814 moea_pteg_count = PTEGCOUNT; 815 #else 816 moea_pteg_count = 0x1000; 817 818 while (moea_pteg_count < physmem) 819 moea_pteg_count <<= 1; 820 821 moea_pteg_count >>= 1; 822 #endif /* PTEGCOUNT */ 823 824 size = moea_pteg_count * sizeof(struct pteg); 825 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 826 size); 827 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 828 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 829 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 830 moea_pteg_mask = moea_pteg_count - 1; 831 832 /* 833 * Allocate pv/overflow lists. 834 */ 835 size = sizeof(struct pvo_head) * moea_pteg_count; 836 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 837 PAGE_SIZE); 838 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 839 for (i = 0; i < moea_pteg_count; i++) 840 LIST_INIT(&moea_pvo_table[i]); 841 842 /* 843 * Initialize the lock that synchronizes access to the pteg and pvo 844 * tables. 845 */ 846 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 847 MTX_RECURSE); 848 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 849 850 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 851 852 /* 853 * Initialise the unmanaged pvo pool. 854 */ 855 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 856 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 857 moea_bpvo_pool_index = 0; 858 859 /* 860 * Make sure kernel vsid is allocated as well as VSID 0. 861 */ 862 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 863 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 864 moea_vsid_bitmap[0] |= 1; 865 866 /* 867 * Initialize the kernel pmap (which is statically allocated). 868 */ 869 PMAP_LOCK_INIT(kernel_pmap); 870 for (i = 0; i < 16; i++) 871 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 872 CPU_FILL(&kernel_pmap->pm_active); 873 RB_INIT(&kernel_pmap->pmap_pvo); 874 875 /* 876 * Initialize the global pv list lock. 877 */ 878 rw_init(&pvh_global_lock, "pmap pv global"); 879 880 /* 881 * Set up the Open Firmware mappings 882 */ 883 chosen = OF_finddevice("/chosen"); 884 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 885 (mmu = OF_instance_to_package(mmui)) != -1 && 886 (sz = OF_getproplen(mmu, "translations")) != -1) { 887 translations = NULL; 888 for (i = 0; phys_avail[i] != 0; i += 2) { 889 if (phys_avail[i + 1] >= sz) { 890 translations = (struct ofw_map *)phys_avail[i]; 891 break; 892 } 893 } 894 if (translations == NULL) 895 panic("moea_bootstrap: no space to copy translations"); 896 bzero(translations, sz); 897 if (OF_getprop(mmu, "translations", translations, sz) == -1) 898 panic("moea_bootstrap: can't get ofw translations"); 899 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 900 sz /= sizeof(*translations); 901 qsort(translations, sz, sizeof (*translations), om_cmp); 902 for (i = 0; i < sz; i++) { 903 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 904 translations[i].om_pa, translations[i].om_va, 905 translations[i].om_len); 906 907 /* 908 * If the mapping is 1:1, let the RAM and device 909 * on-demand BAT tables take care of the translation. 910 */ 911 if (translations[i].om_va == translations[i].om_pa) 912 continue; 913 914 /* Enter the pages */ 915 for (off = 0; off < translations[i].om_len; 916 off += PAGE_SIZE) 917 moea_kenter(mmup, translations[i].om_va + off, 918 translations[i].om_pa + off); 919 } 920 } 921 922 /* 923 * Calculate the last available physical address. 924 */ 925 for (i = 0; phys_avail[i + 2] != 0; i += 2) 926 ; 927 Maxmem = powerpc_btop(phys_avail[i + 1]); 928 929 moea_cpu_bootstrap(mmup,0); 930 mtmsr(mfmsr() | PSL_DR | PSL_IR); 931 pmap_bootstrapped++; 932 933 /* 934 * Set the start and end of kva. 935 */ 936 virtual_avail = VM_MIN_KERNEL_ADDRESS; 937 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 938 939 /* 940 * Allocate a kernel stack with a guard page for thread0 and map it 941 * into the kernel page map. 942 */ 943 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 944 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 945 virtual_avail = va + kstack_pages * PAGE_SIZE; 946 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 947 thread0.td_kstack = va; 948 thread0.td_kstack_pages = kstack_pages; 949 for (i = 0; i < kstack_pages; i++) { 950 moea_kenter(mmup, va, pa); 951 pa += PAGE_SIZE; 952 va += PAGE_SIZE; 953 } 954 955 /* 956 * Allocate virtual address space for the message buffer. 957 */ 958 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 959 msgbufp = (struct msgbuf *)virtual_avail; 960 va = virtual_avail; 961 virtual_avail += round_page(msgbufsize); 962 while (va < virtual_avail) { 963 moea_kenter(mmup, va, pa); 964 pa += PAGE_SIZE; 965 va += PAGE_SIZE; 966 } 967 968 /* 969 * Allocate virtual address space for the dynamic percpu area. 970 */ 971 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 972 dpcpu = (void *)virtual_avail; 973 va = virtual_avail; 974 virtual_avail += DPCPU_SIZE; 975 while (va < virtual_avail) { 976 moea_kenter(mmup, va, pa); 977 pa += PAGE_SIZE; 978 va += PAGE_SIZE; 979 } 980 dpcpu_init(dpcpu, 0); 981 } 982 983 /* 984 * Activate a user pmap. The pmap must be activated before it's address 985 * space can be accessed in any way. 986 */ 987 void 988 moea_activate(mmu_t mmu, struct thread *td) 989 { 990 pmap_t pm, pmr; 991 992 /* 993 * Load all the data we need up front to encourage the compiler to 994 * not issue any loads while we have interrupts disabled below. 995 */ 996 pm = &td->td_proc->p_vmspace->vm_pmap; 997 pmr = pm->pmap_phys; 998 999 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1000 PCPU_SET(curpmap, pmr); 1001 1002 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1003 } 1004 1005 void 1006 moea_deactivate(mmu_t mmu, struct thread *td) 1007 { 1008 pmap_t pm; 1009 1010 pm = &td->td_proc->p_vmspace->vm_pmap; 1011 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1012 PCPU_SET(curpmap, NULL); 1013 } 1014 1015 void 1016 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1017 { 1018 struct pvo_entry key, *pvo; 1019 1020 PMAP_LOCK(pm); 1021 key.pvo_vaddr = sva; 1022 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1023 pvo != NULL && PVO_VADDR(pvo) < eva; 1024 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1025 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1026 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1027 pvo->pvo_vaddr &= ~PVO_WIRED; 1028 pm->pm_stats.wired_count--; 1029 } 1030 PMAP_UNLOCK(pm); 1031 } 1032 1033 void 1034 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1035 { 1036 vm_offset_t dst; 1037 vm_offset_t src; 1038 1039 dst = VM_PAGE_TO_PHYS(mdst); 1040 src = VM_PAGE_TO_PHYS(msrc); 1041 1042 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1043 } 1044 1045 void 1046 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1047 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1048 { 1049 void *a_cp, *b_cp; 1050 vm_offset_t a_pg_offset, b_pg_offset; 1051 int cnt; 1052 1053 while (xfersize > 0) { 1054 a_pg_offset = a_offset & PAGE_MASK; 1055 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1056 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1057 a_pg_offset; 1058 b_pg_offset = b_offset & PAGE_MASK; 1059 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1060 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1061 b_pg_offset; 1062 bcopy(a_cp, b_cp, cnt); 1063 a_offset += cnt; 1064 b_offset += cnt; 1065 xfersize -= cnt; 1066 } 1067 } 1068 1069 /* 1070 * Zero a page of physical memory by temporarily mapping it into the tlb. 1071 */ 1072 void 1073 moea_zero_page(mmu_t mmu, vm_page_t m) 1074 { 1075 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1076 1077 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1078 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1079 } 1080 1081 void 1082 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1083 { 1084 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1085 void *va = (void *)(pa + off); 1086 1087 bzero(va, size); 1088 } 1089 1090 vm_offset_t 1091 moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1092 { 1093 1094 return (VM_PAGE_TO_PHYS(m)); 1095 } 1096 1097 void 1098 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1099 { 1100 } 1101 1102 /* 1103 * Map the given physical page at the specified virtual address in the 1104 * target pmap with the protection requested. If specified the page 1105 * will be wired down. 1106 */ 1107 int 1108 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1109 u_int flags, int8_t psind) 1110 { 1111 int error; 1112 1113 for (;;) { 1114 rw_wlock(&pvh_global_lock); 1115 PMAP_LOCK(pmap); 1116 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1117 rw_wunlock(&pvh_global_lock); 1118 PMAP_UNLOCK(pmap); 1119 if (error != ENOMEM) 1120 return (KERN_SUCCESS); 1121 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1122 return (KERN_RESOURCE_SHORTAGE); 1123 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1124 VM_WAIT; 1125 } 1126 } 1127 1128 /* 1129 * Map the given physical page at the specified virtual address in the 1130 * target pmap with the protection requested. If specified the page 1131 * will be wired down. 1132 * 1133 * The global pvh and pmap must be locked. 1134 */ 1135 static int 1136 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1137 u_int flags, int8_t psind __unused) 1138 { 1139 struct pvo_head *pvo_head; 1140 uma_zone_t zone; 1141 u_int pte_lo, pvo_flags; 1142 int error; 1143 1144 if (pmap_bootstrapped) 1145 rw_assert(&pvh_global_lock, RA_WLOCKED); 1146 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1147 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1148 VM_OBJECT_ASSERT_LOCKED(m->object); 1149 1150 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1151 pvo_head = &moea_pvo_kunmanaged; 1152 zone = moea_upvo_zone; 1153 pvo_flags = 0; 1154 } else { 1155 pvo_head = vm_page_to_pvoh(m); 1156 zone = moea_mpvo_zone; 1157 pvo_flags = PVO_MANAGED; 1158 } 1159 1160 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1161 1162 if (prot & VM_PROT_WRITE) { 1163 pte_lo |= PTE_BW; 1164 if (pmap_bootstrapped && 1165 (m->oflags & VPO_UNMANAGED) == 0) 1166 vm_page_aflag_set(m, PGA_WRITEABLE); 1167 } else 1168 pte_lo |= PTE_BR; 1169 1170 if ((flags & PMAP_ENTER_WIRED) != 0) 1171 pvo_flags |= PVO_WIRED; 1172 1173 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1174 pte_lo, pvo_flags); 1175 1176 /* 1177 * Flush the real page from the instruction cache. This has be done 1178 * for all user mappings to prevent information leakage via the 1179 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1180 * mapping for a page. 1181 */ 1182 if (pmap != kernel_pmap && error == ENOENT && 1183 (pte_lo & (PTE_I | PTE_G)) == 0) 1184 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1185 1186 return (error); 1187 } 1188 1189 /* 1190 * Maps a sequence of resident pages belonging to the same object. 1191 * The sequence begins with the given page m_start. This page is 1192 * mapped at the given virtual address start. Each subsequent page is 1193 * mapped at a virtual address that is offset from start by the same 1194 * amount as the page is offset from m_start within the object. The 1195 * last page in the sequence is the page with the largest offset from 1196 * m_start that can be mapped at a virtual address less than the given 1197 * virtual address end. Not every virtual page between start and end 1198 * is mapped; only those for which a resident page exists with the 1199 * corresponding offset from m_start are mapped. 1200 */ 1201 void 1202 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1203 vm_page_t m_start, vm_prot_t prot) 1204 { 1205 vm_page_t m; 1206 vm_pindex_t diff, psize; 1207 1208 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1209 1210 psize = atop(end - start); 1211 m = m_start; 1212 rw_wlock(&pvh_global_lock); 1213 PMAP_LOCK(pm); 1214 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1215 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1216 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1217 m = TAILQ_NEXT(m, listq); 1218 } 1219 rw_wunlock(&pvh_global_lock); 1220 PMAP_UNLOCK(pm); 1221 } 1222 1223 void 1224 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1225 vm_prot_t prot) 1226 { 1227 1228 rw_wlock(&pvh_global_lock); 1229 PMAP_LOCK(pm); 1230 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1231 0, 0); 1232 rw_wunlock(&pvh_global_lock); 1233 PMAP_UNLOCK(pm); 1234 } 1235 1236 vm_paddr_t 1237 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1238 { 1239 struct pvo_entry *pvo; 1240 vm_paddr_t pa; 1241 1242 PMAP_LOCK(pm); 1243 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1244 if (pvo == NULL) 1245 pa = 0; 1246 else 1247 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1248 PMAP_UNLOCK(pm); 1249 return (pa); 1250 } 1251 1252 /* 1253 * Atomically extract and hold the physical page with the given 1254 * pmap and virtual address pair if that mapping permits the given 1255 * protection. 1256 */ 1257 vm_page_t 1258 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1259 { 1260 struct pvo_entry *pvo; 1261 vm_page_t m; 1262 vm_paddr_t pa; 1263 1264 m = NULL; 1265 pa = 0; 1266 PMAP_LOCK(pmap); 1267 retry: 1268 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1269 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1270 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1271 (prot & VM_PROT_WRITE) == 0)) { 1272 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1273 goto retry; 1274 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1275 vm_page_hold(m); 1276 } 1277 PA_UNLOCK_COND(pa); 1278 PMAP_UNLOCK(pmap); 1279 return (m); 1280 } 1281 1282 void 1283 moea_init(mmu_t mmu) 1284 { 1285 1286 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1287 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1288 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1289 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1290 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1291 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1292 moea_initialized = TRUE; 1293 } 1294 1295 boolean_t 1296 moea_is_referenced(mmu_t mmu, vm_page_t m) 1297 { 1298 boolean_t rv; 1299 1300 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1301 ("moea_is_referenced: page %p is not managed", m)); 1302 rw_wlock(&pvh_global_lock); 1303 rv = moea_query_bit(m, PTE_REF); 1304 rw_wunlock(&pvh_global_lock); 1305 return (rv); 1306 } 1307 1308 boolean_t 1309 moea_is_modified(mmu_t mmu, vm_page_t m) 1310 { 1311 boolean_t rv; 1312 1313 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1314 ("moea_is_modified: page %p is not managed", m)); 1315 1316 /* 1317 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1318 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1319 * is clear, no PTEs can have PTE_CHG set. 1320 */ 1321 VM_OBJECT_ASSERT_WLOCKED(m->object); 1322 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1323 return (FALSE); 1324 rw_wlock(&pvh_global_lock); 1325 rv = moea_query_bit(m, PTE_CHG); 1326 rw_wunlock(&pvh_global_lock); 1327 return (rv); 1328 } 1329 1330 boolean_t 1331 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1332 { 1333 struct pvo_entry *pvo; 1334 boolean_t rv; 1335 1336 PMAP_LOCK(pmap); 1337 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1338 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1339 PMAP_UNLOCK(pmap); 1340 return (rv); 1341 } 1342 1343 void 1344 moea_clear_modify(mmu_t mmu, vm_page_t m) 1345 { 1346 1347 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1348 ("moea_clear_modify: page %p is not managed", m)); 1349 VM_OBJECT_ASSERT_WLOCKED(m->object); 1350 KASSERT(!vm_page_xbusied(m), 1351 ("moea_clear_modify: page %p is exclusive busy", m)); 1352 1353 /* 1354 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1355 * set. If the object containing the page is locked and the page is 1356 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1357 */ 1358 if ((m->aflags & PGA_WRITEABLE) == 0) 1359 return; 1360 rw_wlock(&pvh_global_lock); 1361 moea_clear_bit(m, PTE_CHG); 1362 rw_wunlock(&pvh_global_lock); 1363 } 1364 1365 /* 1366 * Clear the write and modified bits in each of the given page's mappings. 1367 */ 1368 void 1369 moea_remove_write(mmu_t mmu, vm_page_t m) 1370 { 1371 struct pvo_entry *pvo; 1372 struct pte *pt; 1373 pmap_t pmap; 1374 u_int lo; 1375 1376 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1377 ("moea_remove_write: page %p is not managed", m)); 1378 1379 /* 1380 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1381 * set by another thread while the object is locked. Thus, 1382 * if PGA_WRITEABLE is clear, no page table entries need updating. 1383 */ 1384 VM_OBJECT_ASSERT_WLOCKED(m->object); 1385 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1386 return; 1387 rw_wlock(&pvh_global_lock); 1388 lo = moea_attr_fetch(m); 1389 powerpc_sync(); 1390 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1391 pmap = pvo->pvo_pmap; 1392 PMAP_LOCK(pmap); 1393 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1394 pt = moea_pvo_to_pte(pvo, -1); 1395 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1396 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1397 if (pt != NULL) { 1398 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1399 lo |= pvo->pvo_pte.pte.pte_lo; 1400 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1401 moea_pte_change(pt, &pvo->pvo_pte.pte, 1402 pvo->pvo_vaddr); 1403 mtx_unlock(&moea_table_mutex); 1404 } 1405 } 1406 PMAP_UNLOCK(pmap); 1407 } 1408 if ((lo & PTE_CHG) != 0) { 1409 moea_attr_clear(m, PTE_CHG); 1410 vm_page_dirty(m); 1411 } 1412 vm_page_aflag_clear(m, PGA_WRITEABLE); 1413 rw_wunlock(&pvh_global_lock); 1414 } 1415 1416 /* 1417 * moea_ts_referenced: 1418 * 1419 * Return a count of reference bits for a page, clearing those bits. 1420 * It is not necessary for every reference bit to be cleared, but it 1421 * is necessary that 0 only be returned when there are truly no 1422 * reference bits set. 1423 * 1424 * XXX: The exact number of bits to check and clear is a matter that 1425 * should be tested and standardized at some point in the future for 1426 * optimal aging of shared pages. 1427 */ 1428 int 1429 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1430 { 1431 int count; 1432 1433 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1434 ("moea_ts_referenced: page %p is not managed", m)); 1435 rw_wlock(&pvh_global_lock); 1436 count = moea_clear_bit(m, PTE_REF); 1437 rw_wunlock(&pvh_global_lock); 1438 return (count); 1439 } 1440 1441 /* 1442 * Modify the WIMG settings of all mappings for a page. 1443 */ 1444 void 1445 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1446 { 1447 struct pvo_entry *pvo; 1448 struct pvo_head *pvo_head; 1449 struct pte *pt; 1450 pmap_t pmap; 1451 u_int lo; 1452 1453 if ((m->oflags & VPO_UNMANAGED) != 0) { 1454 m->md.mdpg_cache_attrs = ma; 1455 return; 1456 } 1457 1458 rw_wlock(&pvh_global_lock); 1459 pvo_head = vm_page_to_pvoh(m); 1460 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1461 1462 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1463 pmap = pvo->pvo_pmap; 1464 PMAP_LOCK(pmap); 1465 pt = moea_pvo_to_pte(pvo, -1); 1466 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1467 pvo->pvo_pte.pte.pte_lo |= lo; 1468 if (pt != NULL) { 1469 moea_pte_change(pt, &pvo->pvo_pte.pte, 1470 pvo->pvo_vaddr); 1471 if (pvo->pvo_pmap == kernel_pmap) 1472 isync(); 1473 } 1474 mtx_unlock(&moea_table_mutex); 1475 PMAP_UNLOCK(pmap); 1476 } 1477 m->md.mdpg_cache_attrs = ma; 1478 rw_wunlock(&pvh_global_lock); 1479 } 1480 1481 /* 1482 * Map a wired page into kernel virtual address space. 1483 */ 1484 void 1485 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1486 { 1487 1488 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1489 } 1490 1491 void 1492 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1493 { 1494 u_int pte_lo; 1495 int error; 1496 1497 #if 0 1498 if (va < VM_MIN_KERNEL_ADDRESS) 1499 panic("moea_kenter: attempt to enter non-kernel address %#x", 1500 va); 1501 #endif 1502 1503 pte_lo = moea_calc_wimg(pa, ma); 1504 1505 PMAP_LOCK(kernel_pmap); 1506 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1507 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1508 1509 if (error != 0 && error != ENOENT) 1510 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1511 pa, error); 1512 1513 PMAP_UNLOCK(kernel_pmap); 1514 } 1515 1516 /* 1517 * Extract the physical page address associated with the given kernel virtual 1518 * address. 1519 */ 1520 vm_paddr_t 1521 moea_kextract(mmu_t mmu, vm_offset_t va) 1522 { 1523 struct pvo_entry *pvo; 1524 vm_paddr_t pa; 1525 1526 /* 1527 * Allow direct mappings on 32-bit OEA 1528 */ 1529 if (va < VM_MIN_KERNEL_ADDRESS) { 1530 return (va); 1531 } 1532 1533 PMAP_LOCK(kernel_pmap); 1534 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1535 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1536 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1537 PMAP_UNLOCK(kernel_pmap); 1538 return (pa); 1539 } 1540 1541 /* 1542 * Remove a wired page from kernel virtual address space. 1543 */ 1544 void 1545 moea_kremove(mmu_t mmu, vm_offset_t va) 1546 { 1547 1548 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1549 } 1550 1551 /* 1552 * Provide a kernel pointer corresponding to a given userland pointer. 1553 * The returned pointer is valid until the next time this function is 1554 * called in this thread. This is used internally in copyin/copyout. 1555 */ 1556 int 1557 moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1558 void **kaddr, size_t ulen, size_t *klen) 1559 { 1560 size_t l; 1561 register_t vsid; 1562 1563 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1564 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1565 if (l > ulen) 1566 l = ulen; 1567 if (klen) 1568 *klen = l; 1569 else if (l != ulen) 1570 return (EFAULT); 1571 1572 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1573 1574 /* Mark segment no-execute */ 1575 vsid |= SR_N; 1576 1577 /* If we have already set this VSID, we can just return */ 1578 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1579 return (0); 1580 1581 __asm __volatile("isync"); 1582 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1583 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1584 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1585 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1586 1587 return (0); 1588 } 1589 1590 /* 1591 * Map a range of physical addresses into kernel virtual address space. 1592 * 1593 * The value passed in *virt is a suggested virtual address for the mapping. 1594 * Architectures which can support a direct-mapped physical to virtual region 1595 * can return the appropriate address within that region, leaving '*virt' 1596 * unchanged. We cannot and therefore do not; *virt is updated with the 1597 * first usable address after the mapped region. 1598 */ 1599 vm_offset_t 1600 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1601 vm_paddr_t pa_end, int prot) 1602 { 1603 vm_offset_t sva, va; 1604 1605 sva = *virt; 1606 va = sva; 1607 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1608 moea_kenter(mmu, va, pa_start); 1609 *virt = va; 1610 return (sva); 1611 } 1612 1613 /* 1614 * Returns true if the pmap's pv is one of the first 1615 * 16 pvs linked to from this page. This count may 1616 * be changed upwards or downwards in the future; it 1617 * is only necessary that true be returned for a small 1618 * subset of pmaps for proper page aging. 1619 */ 1620 boolean_t 1621 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1622 { 1623 int loops; 1624 struct pvo_entry *pvo; 1625 boolean_t rv; 1626 1627 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1628 ("moea_page_exists_quick: page %p is not managed", m)); 1629 loops = 0; 1630 rv = FALSE; 1631 rw_wlock(&pvh_global_lock); 1632 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1633 if (pvo->pvo_pmap == pmap) { 1634 rv = TRUE; 1635 break; 1636 } 1637 if (++loops >= 16) 1638 break; 1639 } 1640 rw_wunlock(&pvh_global_lock); 1641 return (rv); 1642 } 1643 1644 void 1645 moea_page_init(mmu_t mmu __unused, vm_page_t m) 1646 { 1647 1648 m->md.mdpg_attrs = 0; 1649 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1650 LIST_INIT(&m->md.mdpg_pvoh); 1651 } 1652 1653 /* 1654 * Return the number of managed mappings to the given physical page 1655 * that are wired. 1656 */ 1657 int 1658 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1659 { 1660 struct pvo_entry *pvo; 1661 int count; 1662 1663 count = 0; 1664 if ((m->oflags & VPO_UNMANAGED) != 0) 1665 return (count); 1666 rw_wlock(&pvh_global_lock); 1667 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1668 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1669 count++; 1670 rw_wunlock(&pvh_global_lock); 1671 return (count); 1672 } 1673 1674 static u_int moea_vsidcontext; 1675 1676 void 1677 moea_pinit(mmu_t mmu, pmap_t pmap) 1678 { 1679 int i, mask; 1680 u_int entropy; 1681 1682 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1683 RB_INIT(&pmap->pmap_pvo); 1684 1685 entropy = 0; 1686 __asm __volatile("mftb %0" : "=r"(entropy)); 1687 1688 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1689 == NULL) { 1690 pmap->pmap_phys = pmap; 1691 } 1692 1693 1694 mtx_lock(&moea_vsid_mutex); 1695 /* 1696 * Allocate some segment registers for this pmap. 1697 */ 1698 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1699 u_int hash, n; 1700 1701 /* 1702 * Create a new value by mutiplying by a prime and adding in 1703 * entropy from the timebase register. This is to make the 1704 * VSID more random so that the PT hash function collides 1705 * less often. (Note that the prime casues gcc to do shifts 1706 * instead of a multiply.) 1707 */ 1708 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1709 hash = moea_vsidcontext & (NPMAPS - 1); 1710 if (hash == 0) /* 0 is special, avoid it */ 1711 continue; 1712 n = hash >> 5; 1713 mask = 1 << (hash & (VSID_NBPW - 1)); 1714 hash = (moea_vsidcontext & 0xfffff); 1715 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1716 /* anything free in this bucket? */ 1717 if (moea_vsid_bitmap[n] == 0xffffffff) { 1718 entropy = (moea_vsidcontext >> 20); 1719 continue; 1720 } 1721 i = ffs(~moea_vsid_bitmap[n]) - 1; 1722 mask = 1 << i; 1723 hash &= rounddown2(0xfffff, VSID_NBPW); 1724 hash |= i; 1725 } 1726 KASSERT(!(moea_vsid_bitmap[n] & mask), 1727 ("Allocating in-use VSID group %#x\n", hash)); 1728 moea_vsid_bitmap[n] |= mask; 1729 for (i = 0; i < 16; i++) 1730 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1731 mtx_unlock(&moea_vsid_mutex); 1732 return; 1733 } 1734 1735 mtx_unlock(&moea_vsid_mutex); 1736 panic("moea_pinit: out of segments"); 1737 } 1738 1739 /* 1740 * Initialize the pmap associated with process 0. 1741 */ 1742 void 1743 moea_pinit0(mmu_t mmu, pmap_t pm) 1744 { 1745 1746 PMAP_LOCK_INIT(pm); 1747 moea_pinit(mmu, pm); 1748 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1749 } 1750 1751 /* 1752 * Set the physical protection on the specified range of this map as requested. 1753 */ 1754 void 1755 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1756 vm_prot_t prot) 1757 { 1758 struct pvo_entry *pvo, *tpvo, key; 1759 struct pte *pt; 1760 1761 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1762 ("moea_protect: non current pmap")); 1763 1764 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1765 moea_remove(mmu, pm, sva, eva); 1766 return; 1767 } 1768 1769 rw_wlock(&pvh_global_lock); 1770 PMAP_LOCK(pm); 1771 key.pvo_vaddr = sva; 1772 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1773 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1774 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1775 1776 /* 1777 * Grab the PTE pointer before we diddle with the cached PTE 1778 * copy. 1779 */ 1780 pt = moea_pvo_to_pte(pvo, -1); 1781 /* 1782 * Change the protection of the page. 1783 */ 1784 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1785 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1786 1787 /* 1788 * If the PVO is in the page table, update that pte as well. 1789 */ 1790 if (pt != NULL) { 1791 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1792 mtx_unlock(&moea_table_mutex); 1793 } 1794 } 1795 rw_wunlock(&pvh_global_lock); 1796 PMAP_UNLOCK(pm); 1797 } 1798 1799 /* 1800 * Map a list of wired pages into kernel virtual address space. This is 1801 * intended for temporary mappings which do not need page modification or 1802 * references recorded. Existing mappings in the region are overwritten. 1803 */ 1804 void 1805 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1806 { 1807 vm_offset_t va; 1808 1809 va = sva; 1810 while (count-- > 0) { 1811 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1812 va += PAGE_SIZE; 1813 m++; 1814 } 1815 } 1816 1817 /* 1818 * Remove page mappings from kernel virtual address space. Intended for 1819 * temporary mappings entered by moea_qenter. 1820 */ 1821 void 1822 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1823 { 1824 vm_offset_t va; 1825 1826 va = sva; 1827 while (count-- > 0) { 1828 moea_kremove(mmu, va); 1829 va += PAGE_SIZE; 1830 } 1831 } 1832 1833 void 1834 moea_release(mmu_t mmu, pmap_t pmap) 1835 { 1836 int idx, mask; 1837 1838 /* 1839 * Free segment register's VSID 1840 */ 1841 if (pmap->pm_sr[0] == 0) 1842 panic("moea_release"); 1843 1844 mtx_lock(&moea_vsid_mutex); 1845 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1846 mask = 1 << (idx % VSID_NBPW); 1847 idx /= VSID_NBPW; 1848 moea_vsid_bitmap[idx] &= ~mask; 1849 mtx_unlock(&moea_vsid_mutex); 1850 } 1851 1852 /* 1853 * Remove the given range of addresses from the specified map. 1854 */ 1855 void 1856 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1857 { 1858 struct pvo_entry *pvo, *tpvo, key; 1859 1860 rw_wlock(&pvh_global_lock); 1861 PMAP_LOCK(pm); 1862 key.pvo_vaddr = sva; 1863 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1864 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1865 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1866 moea_pvo_remove(pvo, -1); 1867 } 1868 PMAP_UNLOCK(pm); 1869 rw_wunlock(&pvh_global_lock); 1870 } 1871 1872 /* 1873 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1874 * will reflect changes in pte's back to the vm_page. 1875 */ 1876 void 1877 moea_remove_all(mmu_t mmu, vm_page_t m) 1878 { 1879 struct pvo_head *pvo_head; 1880 struct pvo_entry *pvo, *next_pvo; 1881 pmap_t pmap; 1882 1883 rw_wlock(&pvh_global_lock); 1884 pvo_head = vm_page_to_pvoh(m); 1885 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1886 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1887 1888 pmap = pvo->pvo_pmap; 1889 PMAP_LOCK(pmap); 1890 moea_pvo_remove(pvo, -1); 1891 PMAP_UNLOCK(pmap); 1892 } 1893 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1894 moea_attr_clear(m, PTE_CHG); 1895 vm_page_dirty(m); 1896 } 1897 vm_page_aflag_clear(m, PGA_WRITEABLE); 1898 rw_wunlock(&pvh_global_lock); 1899 } 1900 1901 /* 1902 * Allocate a physical page of memory directly from the phys_avail map. 1903 * Can only be called from moea_bootstrap before avail start and end are 1904 * calculated. 1905 */ 1906 static vm_offset_t 1907 moea_bootstrap_alloc(vm_size_t size, u_int align) 1908 { 1909 vm_offset_t s, e; 1910 int i, j; 1911 1912 size = round_page(size); 1913 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1914 if (align != 0) 1915 s = roundup2(phys_avail[i], align); 1916 else 1917 s = phys_avail[i]; 1918 e = s + size; 1919 1920 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1921 continue; 1922 1923 if (s == phys_avail[i]) { 1924 phys_avail[i] += size; 1925 } else if (e == phys_avail[i + 1]) { 1926 phys_avail[i + 1] -= size; 1927 } else { 1928 for (j = phys_avail_count * 2; j > i; j -= 2) { 1929 phys_avail[j] = phys_avail[j - 2]; 1930 phys_avail[j + 1] = phys_avail[j - 1]; 1931 } 1932 1933 phys_avail[i + 3] = phys_avail[i + 1]; 1934 phys_avail[i + 1] = s; 1935 phys_avail[i + 2] = e; 1936 phys_avail_count++; 1937 } 1938 1939 return (s); 1940 } 1941 panic("moea_bootstrap_alloc: could not allocate memory"); 1942 } 1943 1944 static void 1945 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1946 { 1947 __syncicache((void *)pa, len); 1948 } 1949 1950 static int 1951 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1952 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1953 { 1954 struct pvo_entry *pvo; 1955 u_int sr; 1956 int first; 1957 u_int ptegidx; 1958 int i; 1959 int bootstrap; 1960 1961 moea_pvo_enter_calls++; 1962 first = 0; 1963 bootstrap = 0; 1964 1965 /* 1966 * Compute the PTE Group index. 1967 */ 1968 va &= ~ADDR_POFF; 1969 sr = va_to_sr(pm->pm_sr, va); 1970 ptegidx = va_to_pteg(sr, va); 1971 1972 /* 1973 * Remove any existing mapping for this page. Reuse the pvo entry if 1974 * there is a mapping. 1975 */ 1976 mtx_lock(&moea_table_mutex); 1977 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1978 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1979 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1980 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1981 (pte_lo & PTE_PP)) { 1982 /* 1983 * The PTE is not changing. Instead, this may 1984 * be a request to change the mapping's wired 1985 * attribute. 1986 */ 1987 mtx_unlock(&moea_table_mutex); 1988 if ((flags & PVO_WIRED) != 0 && 1989 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1990 pvo->pvo_vaddr |= PVO_WIRED; 1991 pm->pm_stats.wired_count++; 1992 } else if ((flags & PVO_WIRED) == 0 && 1993 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1994 pvo->pvo_vaddr &= ~PVO_WIRED; 1995 pm->pm_stats.wired_count--; 1996 } 1997 return (0); 1998 } 1999 moea_pvo_remove(pvo, -1); 2000 break; 2001 } 2002 } 2003 2004 /* 2005 * If we aren't overwriting a mapping, try to allocate. 2006 */ 2007 if (moea_initialized) { 2008 pvo = uma_zalloc(zone, M_NOWAIT); 2009 } else { 2010 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2011 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2012 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2013 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2014 } 2015 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2016 moea_bpvo_pool_index++; 2017 bootstrap = 1; 2018 } 2019 2020 if (pvo == NULL) { 2021 mtx_unlock(&moea_table_mutex); 2022 return (ENOMEM); 2023 } 2024 2025 moea_pvo_entries++; 2026 pvo->pvo_vaddr = va; 2027 pvo->pvo_pmap = pm; 2028 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2029 pvo->pvo_vaddr &= ~ADDR_POFF; 2030 if (flags & PVO_WIRED) 2031 pvo->pvo_vaddr |= PVO_WIRED; 2032 if (pvo_head != &moea_pvo_kunmanaged) 2033 pvo->pvo_vaddr |= PVO_MANAGED; 2034 if (bootstrap) 2035 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2036 2037 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2038 2039 /* 2040 * Add to pmap list 2041 */ 2042 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2043 2044 /* 2045 * Remember if the list was empty and therefore will be the first 2046 * item. 2047 */ 2048 if (LIST_FIRST(pvo_head) == NULL) 2049 first = 1; 2050 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2051 2052 if (pvo->pvo_vaddr & PVO_WIRED) 2053 pm->pm_stats.wired_count++; 2054 pm->pm_stats.resident_count++; 2055 2056 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2057 KASSERT(i < 8, ("Invalid PTE index")); 2058 if (i >= 0) { 2059 PVO_PTEGIDX_SET(pvo, i); 2060 } else { 2061 panic("moea_pvo_enter: overflow"); 2062 moea_pte_overflow++; 2063 } 2064 mtx_unlock(&moea_table_mutex); 2065 2066 return (first ? ENOENT : 0); 2067 } 2068 2069 static void 2070 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2071 { 2072 struct pte *pt; 2073 2074 /* 2075 * If there is an active pte entry, we need to deactivate it (and 2076 * save the ref & cfg bits). 2077 */ 2078 pt = moea_pvo_to_pte(pvo, pteidx); 2079 if (pt != NULL) { 2080 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2081 mtx_unlock(&moea_table_mutex); 2082 PVO_PTEGIDX_CLR(pvo); 2083 } else { 2084 moea_pte_overflow--; 2085 } 2086 2087 /* 2088 * Update our statistics. 2089 */ 2090 pvo->pvo_pmap->pm_stats.resident_count--; 2091 if (pvo->pvo_vaddr & PVO_WIRED) 2092 pvo->pvo_pmap->pm_stats.wired_count--; 2093 2094 /* 2095 * Save the REF/CHG bits into their cache if the page is managed. 2096 */ 2097 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2098 struct vm_page *pg; 2099 2100 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2101 if (pg != NULL) { 2102 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2103 (PTE_REF | PTE_CHG)); 2104 } 2105 } 2106 2107 /* 2108 * Remove this PVO from the PV and pmap lists. 2109 */ 2110 LIST_REMOVE(pvo, pvo_vlink); 2111 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2112 2113 /* 2114 * Remove this from the overflow list and return it to the pool 2115 * if we aren't going to reuse it. 2116 */ 2117 LIST_REMOVE(pvo, pvo_olink); 2118 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2119 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2120 moea_upvo_zone, pvo); 2121 moea_pvo_entries--; 2122 moea_pvo_remove_calls++; 2123 } 2124 2125 static __inline int 2126 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2127 { 2128 int pteidx; 2129 2130 /* 2131 * We can find the actual pte entry without searching by grabbing 2132 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2133 * noticing the HID bit. 2134 */ 2135 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2136 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2137 pteidx ^= moea_pteg_mask * 8; 2138 2139 return (pteidx); 2140 } 2141 2142 static struct pvo_entry * 2143 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2144 { 2145 struct pvo_entry *pvo; 2146 int ptegidx; 2147 u_int sr; 2148 2149 va &= ~ADDR_POFF; 2150 sr = va_to_sr(pm->pm_sr, va); 2151 ptegidx = va_to_pteg(sr, va); 2152 2153 mtx_lock(&moea_table_mutex); 2154 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2155 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2156 if (pteidx_p) 2157 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2158 break; 2159 } 2160 } 2161 mtx_unlock(&moea_table_mutex); 2162 2163 return (pvo); 2164 } 2165 2166 static struct pte * 2167 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2168 { 2169 struct pte *pt; 2170 2171 /* 2172 * If we haven't been supplied the ptegidx, calculate it. 2173 */ 2174 if (pteidx == -1) { 2175 int ptegidx; 2176 u_int sr; 2177 2178 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2179 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2180 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2181 } 2182 2183 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2184 mtx_lock(&moea_table_mutex); 2185 2186 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2187 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2188 "valid pte index", pvo); 2189 } 2190 2191 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2192 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2193 "pvo but no valid pte", pvo); 2194 } 2195 2196 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2197 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2198 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2199 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2200 } 2201 2202 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2203 != 0) { 2204 panic("moea_pvo_to_pte: pvo %p pte does not match " 2205 "pte %p in moea_pteg_table", pvo, pt); 2206 } 2207 2208 mtx_assert(&moea_table_mutex, MA_OWNED); 2209 return (pt); 2210 } 2211 2212 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2213 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2214 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2215 } 2216 2217 mtx_unlock(&moea_table_mutex); 2218 return (NULL); 2219 } 2220 2221 /* 2222 * XXX: THIS STUFF SHOULD BE IN pte.c? 2223 */ 2224 int 2225 moea_pte_spill(vm_offset_t addr) 2226 { 2227 struct pvo_entry *source_pvo, *victim_pvo; 2228 struct pvo_entry *pvo; 2229 int ptegidx, i, j; 2230 u_int sr; 2231 struct pteg *pteg; 2232 struct pte *pt; 2233 2234 moea_pte_spills++; 2235 2236 sr = mfsrin(addr); 2237 ptegidx = va_to_pteg(sr, addr); 2238 2239 /* 2240 * Have to substitute some entry. Use the primary hash for this. 2241 * Use low bits of timebase as random generator. 2242 */ 2243 pteg = &moea_pteg_table[ptegidx]; 2244 mtx_lock(&moea_table_mutex); 2245 __asm __volatile("mftb %0" : "=r"(i)); 2246 i &= 7; 2247 pt = &pteg->pt[i]; 2248 2249 source_pvo = NULL; 2250 victim_pvo = NULL; 2251 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2252 /* 2253 * We need to find a pvo entry for this address. 2254 */ 2255 if (source_pvo == NULL && 2256 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2257 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2258 /* 2259 * Now found an entry to be spilled into the pteg. 2260 * The PTE is now valid, so we know it's active. 2261 */ 2262 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2263 2264 if (j >= 0) { 2265 PVO_PTEGIDX_SET(pvo, j); 2266 moea_pte_overflow--; 2267 mtx_unlock(&moea_table_mutex); 2268 return (1); 2269 } 2270 2271 source_pvo = pvo; 2272 2273 if (victim_pvo != NULL) 2274 break; 2275 } 2276 2277 /* 2278 * We also need the pvo entry of the victim we are replacing 2279 * so save the R & C bits of the PTE. 2280 */ 2281 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2282 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2283 victim_pvo = pvo; 2284 if (source_pvo != NULL) 2285 break; 2286 } 2287 } 2288 2289 if (source_pvo == NULL) { 2290 mtx_unlock(&moea_table_mutex); 2291 return (0); 2292 } 2293 2294 if (victim_pvo == NULL) { 2295 if ((pt->pte_hi & PTE_HID) == 0) 2296 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2297 "entry", pt); 2298 2299 /* 2300 * If this is a secondary PTE, we need to search it's primary 2301 * pvo bucket for the matching PVO. 2302 */ 2303 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2304 pvo_olink) { 2305 /* 2306 * We also need the pvo entry of the victim we are 2307 * replacing so save the R & C bits of the PTE. 2308 */ 2309 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2310 victim_pvo = pvo; 2311 break; 2312 } 2313 } 2314 2315 if (victim_pvo == NULL) 2316 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2317 "entry", pt); 2318 } 2319 2320 /* 2321 * We are invalidating the TLB entry for the EA we are replacing even 2322 * though it's valid. If we don't, we lose any ref/chg bit changes 2323 * contained in the TLB entry. 2324 */ 2325 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2326 2327 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2328 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2329 2330 PVO_PTEGIDX_CLR(victim_pvo); 2331 PVO_PTEGIDX_SET(source_pvo, i); 2332 moea_pte_replacements++; 2333 2334 mtx_unlock(&moea_table_mutex); 2335 return (1); 2336 } 2337 2338 static __inline struct pvo_entry * 2339 moea_pte_spillable_ident(u_int ptegidx) 2340 { 2341 struct pte *pt; 2342 struct pvo_entry *pvo_walk, *pvo = NULL; 2343 2344 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2345 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2346 continue; 2347 2348 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2349 continue; 2350 2351 pt = moea_pvo_to_pte(pvo_walk, -1); 2352 2353 if (pt == NULL) 2354 continue; 2355 2356 pvo = pvo_walk; 2357 2358 mtx_unlock(&moea_table_mutex); 2359 if (!(pt->pte_lo & PTE_REF)) 2360 return (pvo_walk); 2361 } 2362 2363 return (pvo); 2364 } 2365 2366 static int 2367 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2368 { 2369 struct pte *pt; 2370 struct pvo_entry *victim_pvo; 2371 int i; 2372 int victim_idx; 2373 u_int pteg_bkpidx = ptegidx; 2374 2375 mtx_assert(&moea_table_mutex, MA_OWNED); 2376 2377 /* 2378 * First try primary hash. 2379 */ 2380 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2381 if ((pt->pte_hi & PTE_VALID) == 0) { 2382 pvo_pt->pte_hi &= ~PTE_HID; 2383 moea_pte_set(pt, pvo_pt); 2384 return (i); 2385 } 2386 } 2387 2388 /* 2389 * Now try secondary hash. 2390 */ 2391 ptegidx ^= moea_pteg_mask; 2392 2393 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2394 if ((pt->pte_hi & PTE_VALID) == 0) { 2395 pvo_pt->pte_hi |= PTE_HID; 2396 moea_pte_set(pt, pvo_pt); 2397 return (i); 2398 } 2399 } 2400 2401 /* Try again, but this time try to force a PTE out. */ 2402 ptegidx = pteg_bkpidx; 2403 2404 victim_pvo = moea_pte_spillable_ident(ptegidx); 2405 if (victim_pvo == NULL) { 2406 ptegidx ^= moea_pteg_mask; 2407 victim_pvo = moea_pte_spillable_ident(ptegidx); 2408 } 2409 2410 if (victim_pvo == NULL) { 2411 panic("moea_pte_insert: overflow"); 2412 return (-1); 2413 } 2414 2415 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2416 2417 if (pteg_bkpidx == ptegidx) 2418 pvo_pt->pte_hi &= ~PTE_HID; 2419 else 2420 pvo_pt->pte_hi |= PTE_HID; 2421 2422 /* 2423 * Synchronize the sacrifice PTE with its PVO, then mark both 2424 * invalid. The PVO will be reused when/if the VM system comes 2425 * here after a fault. 2426 */ 2427 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2428 2429 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2430 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2431 2432 /* 2433 * Set the new PTE. 2434 */ 2435 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2436 PVO_PTEGIDX_CLR(victim_pvo); 2437 moea_pte_overflow++; 2438 moea_pte_set(pt, pvo_pt); 2439 2440 return (victim_idx & 7); 2441 } 2442 2443 static boolean_t 2444 moea_query_bit(vm_page_t m, int ptebit) 2445 { 2446 struct pvo_entry *pvo; 2447 struct pte *pt; 2448 2449 rw_assert(&pvh_global_lock, RA_WLOCKED); 2450 if (moea_attr_fetch(m) & ptebit) 2451 return (TRUE); 2452 2453 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2454 2455 /* 2456 * See if we saved the bit off. If so, cache it and return 2457 * success. 2458 */ 2459 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2460 moea_attr_save(m, ptebit); 2461 return (TRUE); 2462 } 2463 } 2464 2465 /* 2466 * No luck, now go through the hard part of looking at the PTEs 2467 * themselves. Sync so that any pending REF/CHG bits are flushed to 2468 * the PTEs. 2469 */ 2470 powerpc_sync(); 2471 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2472 2473 /* 2474 * See if this pvo has a valid PTE. if so, fetch the 2475 * REF/CHG bits from the valid PTE. If the appropriate 2476 * ptebit is set, cache it and return success. 2477 */ 2478 pt = moea_pvo_to_pte(pvo, -1); 2479 if (pt != NULL) { 2480 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2481 mtx_unlock(&moea_table_mutex); 2482 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2483 moea_attr_save(m, ptebit); 2484 return (TRUE); 2485 } 2486 } 2487 } 2488 2489 return (FALSE); 2490 } 2491 2492 static u_int 2493 moea_clear_bit(vm_page_t m, int ptebit) 2494 { 2495 u_int count; 2496 struct pvo_entry *pvo; 2497 struct pte *pt; 2498 2499 rw_assert(&pvh_global_lock, RA_WLOCKED); 2500 2501 /* 2502 * Clear the cached value. 2503 */ 2504 moea_attr_clear(m, ptebit); 2505 2506 /* 2507 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2508 * we can reset the right ones). note that since the pvo entries and 2509 * list heads are accessed via BAT0 and are never placed in the page 2510 * table, we don't have to worry about further accesses setting the 2511 * REF/CHG bits. 2512 */ 2513 powerpc_sync(); 2514 2515 /* 2516 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2517 * valid pte clear the ptebit from the valid pte. 2518 */ 2519 count = 0; 2520 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2521 pt = moea_pvo_to_pte(pvo, -1); 2522 if (pt != NULL) { 2523 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2524 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2525 count++; 2526 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2527 } 2528 mtx_unlock(&moea_table_mutex); 2529 } 2530 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2531 } 2532 2533 return (count); 2534 } 2535 2536 /* 2537 * Return true if the physical range is encompassed by the battable[idx] 2538 */ 2539 static int 2540 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2541 { 2542 u_int prot; 2543 u_int32_t start; 2544 u_int32_t end; 2545 u_int32_t bat_ble; 2546 2547 /* 2548 * Return immediately if not a valid mapping 2549 */ 2550 if (!(battable[idx].batu & BAT_Vs)) 2551 return (EINVAL); 2552 2553 /* 2554 * The BAT entry must be cache-inhibited, guarded, and r/w 2555 * so it can function as an i/o page 2556 */ 2557 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2558 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2559 return (EPERM); 2560 2561 /* 2562 * The address should be within the BAT range. Assume that the 2563 * start address in the BAT has the correct alignment (thus 2564 * not requiring masking) 2565 */ 2566 start = battable[idx].batl & BAT_PBS; 2567 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2568 end = start | (bat_ble << 15) | 0x7fff; 2569 2570 if ((pa < start) || ((pa + size) > end)) 2571 return (ERANGE); 2572 2573 return (0); 2574 } 2575 2576 boolean_t 2577 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2578 { 2579 int i; 2580 2581 /* 2582 * This currently does not work for entries that 2583 * overlap 256M BAT segments. 2584 */ 2585 2586 for(i = 0; i < 16; i++) 2587 if (moea_bat_mapped(i, pa, size) == 0) 2588 return (0); 2589 2590 return (EFAULT); 2591 } 2592 2593 /* 2594 * Map a set of physical memory pages into the kernel virtual 2595 * address space. Return a pointer to where it is mapped. This 2596 * routine is intended to be used for mapping device memory, 2597 * NOT real memory. 2598 */ 2599 void * 2600 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2601 { 2602 2603 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2604 } 2605 2606 void * 2607 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2608 { 2609 vm_offset_t va, tmpva, ppa, offset; 2610 int i; 2611 2612 ppa = trunc_page(pa); 2613 offset = pa & PAGE_MASK; 2614 size = roundup(offset + size, PAGE_SIZE); 2615 2616 /* 2617 * If the physical address lies within a valid BAT table entry, 2618 * return the 1:1 mapping. This currently doesn't work 2619 * for regions that overlap 256M BAT segments. 2620 */ 2621 for (i = 0; i < 16; i++) { 2622 if (moea_bat_mapped(i, pa, size) == 0) 2623 return ((void *) pa); 2624 } 2625 2626 va = kva_alloc(size); 2627 if (!va) 2628 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2629 2630 for (tmpva = va; size > 0;) { 2631 moea_kenter_attr(mmu, tmpva, ppa, ma); 2632 tlbie(tmpva); 2633 size -= PAGE_SIZE; 2634 tmpva += PAGE_SIZE; 2635 ppa += PAGE_SIZE; 2636 } 2637 2638 return ((void *)(va + offset)); 2639 } 2640 2641 void 2642 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2643 { 2644 vm_offset_t base, offset; 2645 2646 /* 2647 * If this is outside kernel virtual space, then it's a 2648 * battable entry and doesn't require unmapping 2649 */ 2650 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2651 base = trunc_page(va); 2652 offset = va & PAGE_MASK; 2653 size = roundup(offset + size, PAGE_SIZE); 2654 kva_free(base, size); 2655 } 2656 } 2657 2658 static void 2659 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2660 { 2661 struct pvo_entry *pvo; 2662 vm_offset_t lim; 2663 vm_paddr_t pa; 2664 vm_size_t len; 2665 2666 PMAP_LOCK(pm); 2667 while (sz > 0) { 2668 lim = round_page(va); 2669 len = MIN(lim - va, sz); 2670 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2671 if (pvo != NULL) { 2672 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2673 (va & ADDR_POFF); 2674 moea_syncicache(pa, len); 2675 } 2676 va += len; 2677 sz -= len; 2678 } 2679 PMAP_UNLOCK(pm); 2680 } 2681 2682 void 2683 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2684 { 2685 2686 *va = (void *)pa; 2687 } 2688 2689 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2690 2691 void 2692 moea_scan_init(mmu_t mmu) 2693 { 2694 struct pvo_entry *pvo; 2695 vm_offset_t va; 2696 int i; 2697 2698 if (!do_minidump) { 2699 /* Initialize phys. segments for dumpsys(). */ 2700 memset(&dump_map, 0, sizeof(dump_map)); 2701 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2702 for (i = 0; i < pregions_sz; i++) { 2703 dump_map[i].pa_start = pregions[i].mr_start; 2704 dump_map[i].pa_size = pregions[i].mr_size; 2705 } 2706 return; 2707 } 2708 2709 /* Virtual segments for minidumps: */ 2710 memset(&dump_map, 0, sizeof(dump_map)); 2711 2712 /* 1st: kernel .data and .bss. */ 2713 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2714 dump_map[0].pa_size = 2715 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2716 2717 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2718 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2719 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2720 2721 /* 3rd: kernel VM. */ 2722 va = dump_map[1].pa_start + dump_map[1].pa_size; 2723 /* Find start of next chunk (from va). */ 2724 while (va < virtual_end) { 2725 /* Don't dump the buffer cache. */ 2726 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2727 va = kmi.buffer_eva; 2728 continue; 2729 } 2730 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2731 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2732 break; 2733 va += PAGE_SIZE; 2734 } 2735 if (va < virtual_end) { 2736 dump_map[2].pa_start = va; 2737 va += PAGE_SIZE; 2738 /* Find last page in chunk. */ 2739 while (va < virtual_end) { 2740 /* Don't run into the buffer cache. */ 2741 if (va == kmi.buffer_sva) 2742 break; 2743 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2744 NULL); 2745 if (pvo == NULL || 2746 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2747 break; 2748 va += PAGE_SIZE; 2749 } 2750 dump_map[2].pa_size = va - dump_map[2].pa_start; 2751 } 2752 } 2753