1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/powerpc.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/sr.h> 151 #include <machine/mmuvar.h> 152 153 #include "mmu_if.h" 154 155 #define MOEA_DEBUG 156 157 #define TODO panic("%s: not implemented", __func__); 158 159 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 160 #define TLBSYNC() __asm __volatile("tlbsync"); 161 #define SYNC() __asm __volatile("sync"); 162 #define EIEIO() __asm __volatile("eieio"); 163 164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 165 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 167 168 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 169 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 170 #define PVO_WIRED 0x010 /* PVO entry is wired */ 171 #define PVO_MANAGED 0x020 /* PVO entry is managed */ 172 #define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 173 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 174 bootstrap */ 175 #define PVO_FAKE 0x100 /* fictitious phys page */ 176 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 177 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 178 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 179 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 180 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 181 #define PVO_PTEGIDX_CLR(pvo) \ 182 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 183 #define PVO_PTEGIDX_SET(pvo, i) \ 184 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 185 186 #define MOEA_PVO_CHECK(pvo) 187 188 struct ofw_map { 189 vm_offset_t om_va; 190 vm_size_t om_len; 191 vm_offset_t om_pa; 192 u_int om_mode; 193 }; 194 195 /* 196 * Map of physical memory regions. 197 */ 198 static struct mem_region *regions; 199 static struct mem_region *pregions; 200 u_int phys_avail_count; 201 int regions_sz, pregions_sz; 202 static struct ofw_map *translations; 203 204 extern struct pmap ofw_pmap; 205 206 207 208 /* 209 * Lock for the pteg and pvo tables. 210 */ 211 struct mtx moea_table_mutex; 212 213 /* 214 * PTEG data. 215 */ 216 static struct pteg *moea_pteg_table; 217 u_int moea_pteg_count; 218 u_int moea_pteg_mask; 219 220 /* 221 * PVO data. 222 */ 223 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 224 struct pvo_head moea_pvo_kunmanaged = 225 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 226 struct pvo_head moea_pvo_unmanaged = 227 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 228 229 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 230 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 231 232 #define BPVO_POOL_SIZE 32768 233 static struct pvo_entry *moea_bpvo_pool; 234 static int moea_bpvo_pool_index = 0; 235 236 #define VSID_NBPW (sizeof(u_int32_t) * 8) 237 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 238 239 static boolean_t moea_initialized = FALSE; 240 241 /* 242 * Statistics. 243 */ 244 u_int moea_pte_valid = 0; 245 u_int moea_pte_overflow = 0; 246 u_int moea_pte_replacements = 0; 247 u_int moea_pvo_entries = 0; 248 u_int moea_pvo_enter_calls = 0; 249 u_int moea_pvo_remove_calls = 0; 250 u_int moea_pte_spills = 0; 251 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 252 0, ""); 253 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 254 &moea_pte_overflow, 0, ""); 255 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 256 &moea_pte_replacements, 0, ""); 257 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 258 0, ""); 259 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 260 &moea_pvo_enter_calls, 0, ""); 261 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 262 &moea_pvo_remove_calls, 0, ""); 263 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 264 &moea_pte_spills, 0, ""); 265 266 struct pvo_entry *moea_pvo_zeropage; 267 struct mtx moea_pvo_zeropage_mtx; 268 269 vm_offset_t moea_rkva_start = VM_MIN_KERNEL_ADDRESS; 270 u_int moea_rkva_count = 4; 271 272 /* 273 * Allocate physical memory for use in moea_bootstrap. 274 */ 275 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 276 277 /* 278 * PTE calls. 279 */ 280 static int moea_pte_insert(u_int, struct pte *); 281 282 /* 283 * PVO calls. 284 */ 285 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 286 vm_offset_t, vm_offset_t, u_int, int); 287 static void moea_pvo_remove(struct pvo_entry *, int); 288 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 289 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 290 291 /* 292 * Utility routines. 293 */ 294 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 295 vm_prot_t, boolean_t); 296 static struct pvo_entry *moea_rkva_alloc(mmu_t); 297 static void moea_pa_map(struct pvo_entry *, vm_offset_t, 298 struct pte *, int *); 299 static void moea_pa_unmap(struct pvo_entry *, struct pte *, int *); 300 static void moea_syncicache(vm_offset_t, vm_size_t); 301 static boolean_t moea_query_bit(vm_page_t, int); 302 static u_int moea_clear_bit(vm_page_t, int, int *); 303 static void moea_kremove(mmu_t, vm_offset_t); 304 static void tlbia(void); 305 int moea_pte_spill(vm_offset_t); 306 307 /* 308 * Kernel MMU interface 309 */ 310 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 311 void moea_clear_modify(mmu_t, vm_page_t); 312 void moea_clear_reference(mmu_t, vm_page_t); 313 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 314 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 315 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 316 vm_prot_t); 317 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 318 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 319 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 320 void moea_init(mmu_t); 321 boolean_t moea_is_modified(mmu_t, vm_page_t); 322 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 323 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 324 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 325 void moea_pinit(mmu_t, pmap_t); 326 void moea_pinit0(mmu_t, pmap_t); 327 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 328 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 329 void moea_qremove(mmu_t, vm_offset_t, int); 330 void moea_release(mmu_t, pmap_t); 331 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 332 void moea_remove_all(mmu_t, vm_page_t); 333 void moea_remove_write(mmu_t, vm_page_t); 334 void moea_zero_page(mmu_t, vm_page_t); 335 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 336 void moea_zero_page_idle(mmu_t, vm_page_t); 337 void moea_activate(mmu_t, struct thread *); 338 void moea_deactivate(mmu_t, struct thread *); 339 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 340 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 341 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 342 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 343 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 344 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 345 346 static mmu_method_t moea_methods[] = { 347 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 348 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 349 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 350 MMUMETHOD(mmu_copy_page, moea_copy_page), 351 MMUMETHOD(mmu_enter, moea_enter), 352 MMUMETHOD(mmu_enter_object, moea_enter_object), 353 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 354 MMUMETHOD(mmu_extract, moea_extract), 355 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 356 MMUMETHOD(mmu_init, moea_init), 357 MMUMETHOD(mmu_is_modified, moea_is_modified), 358 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 359 MMUMETHOD(mmu_map, moea_map), 360 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 361 MMUMETHOD(mmu_pinit, moea_pinit), 362 MMUMETHOD(mmu_pinit0, moea_pinit0), 363 MMUMETHOD(mmu_protect, moea_protect), 364 MMUMETHOD(mmu_qenter, moea_qenter), 365 MMUMETHOD(mmu_qremove, moea_qremove), 366 MMUMETHOD(mmu_release, moea_release), 367 MMUMETHOD(mmu_remove, moea_remove), 368 MMUMETHOD(mmu_remove_all, moea_remove_all), 369 MMUMETHOD(mmu_remove_write, moea_remove_write), 370 MMUMETHOD(mmu_zero_page, moea_zero_page), 371 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 372 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 373 MMUMETHOD(mmu_activate, moea_activate), 374 MMUMETHOD(mmu_deactivate, moea_deactivate), 375 376 /* Internal interfaces */ 377 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 378 MMUMETHOD(mmu_mapdev, moea_mapdev), 379 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 380 MMUMETHOD(mmu_kextract, moea_kextract), 381 MMUMETHOD(mmu_kenter, moea_kenter), 382 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 383 384 { 0, 0 } 385 }; 386 387 static mmu_def_t oea_mmu = { 388 MMU_TYPE_OEA, 389 moea_methods, 390 0 391 }; 392 MMU_DEF(oea_mmu); 393 394 395 static __inline int 396 va_to_sr(u_int *sr, vm_offset_t va) 397 { 398 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 399 } 400 401 static __inline u_int 402 va_to_pteg(u_int sr, vm_offset_t addr) 403 { 404 u_int hash; 405 406 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 407 ADDR_PIDX_SHFT); 408 return (hash & moea_pteg_mask); 409 } 410 411 static __inline struct pvo_head * 412 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 413 { 414 struct vm_page *pg; 415 416 pg = PHYS_TO_VM_PAGE(pa); 417 418 if (pg_p != NULL) 419 *pg_p = pg; 420 421 if (pg == NULL) 422 return (&moea_pvo_unmanaged); 423 424 return (&pg->md.mdpg_pvoh); 425 } 426 427 static __inline struct pvo_head * 428 vm_page_to_pvoh(vm_page_t m) 429 { 430 431 return (&m->md.mdpg_pvoh); 432 } 433 434 static __inline void 435 moea_attr_clear(vm_page_t m, int ptebit) 436 { 437 438 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 439 m->md.mdpg_attrs &= ~ptebit; 440 } 441 442 static __inline int 443 moea_attr_fetch(vm_page_t m) 444 { 445 446 return (m->md.mdpg_attrs); 447 } 448 449 static __inline void 450 moea_attr_save(vm_page_t m, int ptebit) 451 { 452 453 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 454 m->md.mdpg_attrs |= ptebit; 455 } 456 457 static __inline int 458 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 459 { 460 if (pt->pte_hi == pvo_pt->pte_hi) 461 return (1); 462 463 return (0); 464 } 465 466 static __inline int 467 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 468 { 469 return (pt->pte_hi & ~PTE_VALID) == 470 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 471 ((va >> ADDR_API_SHFT) & PTE_API) | which); 472 } 473 474 static __inline void 475 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 476 { 477 478 mtx_assert(&moea_table_mutex, MA_OWNED); 479 480 /* 481 * Construct a PTE. Default to IMB initially. Valid bit only gets 482 * set when the real pte is set in memory. 483 * 484 * Note: Don't set the valid bit for correct operation of tlb update. 485 */ 486 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 487 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 488 pt->pte_lo = pte_lo; 489 } 490 491 static __inline void 492 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 493 { 494 495 mtx_assert(&moea_table_mutex, MA_OWNED); 496 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 497 } 498 499 static __inline void 500 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 501 { 502 503 mtx_assert(&moea_table_mutex, MA_OWNED); 504 505 /* 506 * As shown in Section 7.6.3.2.3 507 */ 508 pt->pte_lo &= ~ptebit; 509 TLBIE(va); 510 EIEIO(); 511 TLBSYNC(); 512 SYNC(); 513 } 514 515 static __inline void 516 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 517 { 518 519 mtx_assert(&moea_table_mutex, MA_OWNED); 520 pvo_pt->pte_hi |= PTE_VALID; 521 522 /* 523 * Update the PTE as defined in section 7.6.3.1. 524 * Note that the REF/CHG bits are from pvo_pt and thus should havce 525 * been saved so this routine can restore them (if desired). 526 */ 527 pt->pte_lo = pvo_pt->pte_lo; 528 EIEIO(); 529 pt->pte_hi = pvo_pt->pte_hi; 530 SYNC(); 531 moea_pte_valid++; 532 } 533 534 static __inline void 535 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 536 { 537 538 mtx_assert(&moea_table_mutex, MA_OWNED); 539 pvo_pt->pte_hi &= ~PTE_VALID; 540 541 /* 542 * Force the reg & chg bits back into the PTEs. 543 */ 544 SYNC(); 545 546 /* 547 * Invalidate the pte. 548 */ 549 pt->pte_hi &= ~PTE_VALID; 550 551 SYNC(); 552 TLBIE(va); 553 EIEIO(); 554 TLBSYNC(); 555 SYNC(); 556 557 /* 558 * Save the reg & chg bits. 559 */ 560 moea_pte_synch(pt, pvo_pt); 561 moea_pte_valid--; 562 } 563 564 static __inline void 565 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 566 { 567 568 /* 569 * Invalidate the PTE 570 */ 571 moea_pte_unset(pt, pvo_pt, va); 572 moea_pte_set(pt, pvo_pt); 573 } 574 575 /* 576 * Quick sort callout for comparing memory regions. 577 */ 578 static int mr_cmp(const void *a, const void *b); 579 static int om_cmp(const void *a, const void *b); 580 581 static int 582 mr_cmp(const void *a, const void *b) 583 { 584 const struct mem_region *regiona; 585 const struct mem_region *regionb; 586 587 regiona = a; 588 regionb = b; 589 if (regiona->mr_start < regionb->mr_start) 590 return (-1); 591 else if (regiona->mr_start > regionb->mr_start) 592 return (1); 593 else 594 return (0); 595 } 596 597 static int 598 om_cmp(const void *a, const void *b) 599 { 600 const struct ofw_map *mapa; 601 const struct ofw_map *mapb; 602 603 mapa = a; 604 mapb = b; 605 if (mapa->om_pa < mapb->om_pa) 606 return (-1); 607 else if (mapa->om_pa > mapb->om_pa) 608 return (1); 609 else 610 return (0); 611 } 612 613 void 614 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 615 { 616 ihandle_t mmui; 617 phandle_t chosen, mmu; 618 int sz; 619 int i, j; 620 int ofw_mappings; 621 vm_size_t size, physsz, hwphyssz; 622 vm_offset_t pa, va, off; 623 u_int batl, batu; 624 625 /* 626 * Set up BAT0 to map the lowest 256 MB area 627 */ 628 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 629 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 630 631 /* 632 * Map PCI memory space. 633 */ 634 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 635 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 636 637 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 638 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 639 640 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 641 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 642 643 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 644 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 645 646 /* 647 * Map obio devices. 648 */ 649 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 650 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 651 652 /* 653 * Use an IBAT and a DBAT to map the bottom segment of memory 654 * where we are. 655 */ 656 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 657 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 658 __asm (".balign 32; \n" 659 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 660 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 661 :: "r"(batu), "r"(batl)); 662 663 #if 0 664 /* map frame buffer */ 665 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 666 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 667 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 668 :: "r"(batu), "r"(batl)); 669 #endif 670 671 #if 1 672 /* map pci space */ 673 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 674 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 675 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 676 :: "r"(batu), "r"(batl)); 677 #endif 678 679 /* 680 * Set the start and end of kva. 681 */ 682 virtual_avail = VM_MIN_KERNEL_ADDRESS; 683 virtual_end = VM_MAX_KERNEL_ADDRESS; 684 685 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 686 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 687 688 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 689 for (i = 0; i < pregions_sz; i++) { 690 vm_offset_t pa; 691 vm_offset_t end; 692 693 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 694 pregions[i].mr_start, 695 pregions[i].mr_start + pregions[i].mr_size, 696 pregions[i].mr_size); 697 /* 698 * Install entries into the BAT table to allow all 699 * of physmem to be convered by on-demand BAT entries. 700 * The loop will sometimes set the same battable element 701 * twice, but that's fine since they won't be used for 702 * a while yet. 703 */ 704 pa = pregions[i].mr_start & 0xf0000000; 705 end = pregions[i].mr_start + pregions[i].mr_size; 706 do { 707 u_int n = pa >> ADDR_SR_SHFT; 708 709 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 710 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 711 pa += SEGMENT_LENGTH; 712 } while (pa < end); 713 } 714 715 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 716 panic("moea_bootstrap: phys_avail too small"); 717 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 718 phys_avail_count = 0; 719 physsz = 0; 720 hwphyssz = 0; 721 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 722 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 723 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 724 regions[i].mr_start + regions[i].mr_size, 725 regions[i].mr_size); 726 if (hwphyssz != 0 && 727 (physsz + regions[i].mr_size) >= hwphyssz) { 728 if (physsz < hwphyssz) { 729 phys_avail[j] = regions[i].mr_start; 730 phys_avail[j + 1] = regions[i].mr_start + 731 hwphyssz - physsz; 732 physsz = hwphyssz; 733 phys_avail_count++; 734 } 735 break; 736 } 737 phys_avail[j] = regions[i].mr_start; 738 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 739 phys_avail_count++; 740 physsz += regions[i].mr_size; 741 } 742 physmem = btoc(physsz); 743 744 /* 745 * Allocate PTEG table. 746 */ 747 #ifdef PTEGCOUNT 748 moea_pteg_count = PTEGCOUNT; 749 #else 750 moea_pteg_count = 0x1000; 751 752 while (moea_pteg_count < physmem) 753 moea_pteg_count <<= 1; 754 755 moea_pteg_count >>= 1; 756 #endif /* PTEGCOUNT */ 757 758 size = moea_pteg_count * sizeof(struct pteg); 759 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 760 size); 761 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 762 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 763 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 764 moea_pteg_mask = moea_pteg_count - 1; 765 766 /* 767 * Allocate pv/overflow lists. 768 */ 769 size = sizeof(struct pvo_head) * moea_pteg_count; 770 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 771 PAGE_SIZE); 772 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 773 for (i = 0; i < moea_pteg_count; i++) 774 LIST_INIT(&moea_pvo_table[i]); 775 776 /* 777 * Initialize the lock that synchronizes access to the pteg and pvo 778 * tables. 779 */ 780 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 781 MTX_RECURSE); 782 783 /* 784 * Allocate the message buffer. 785 */ 786 msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, 0); 787 788 /* 789 * Initialise the unmanaged pvo pool. 790 */ 791 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 792 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 793 moea_bpvo_pool_index = 0; 794 795 /* 796 * Make sure kernel vsid is allocated as well as VSID 0. 797 */ 798 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 799 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 800 moea_vsid_bitmap[0] |= 1; 801 802 /* 803 * Set up the Open Firmware pmap and add it's mappings. 804 */ 805 moea_pinit(mmup, &ofw_pmap); 806 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 807 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 808 if ((chosen = OF_finddevice("/chosen")) == -1) 809 panic("moea_bootstrap: can't find /chosen"); 810 OF_getprop(chosen, "mmu", &mmui, 4); 811 if ((mmu = OF_instance_to_package(mmui)) == -1) 812 panic("moea_bootstrap: can't get mmu package"); 813 if ((sz = OF_getproplen(mmu, "translations")) == -1) 814 panic("moea_bootstrap: can't get ofw translation count"); 815 translations = NULL; 816 for (i = 0; phys_avail[i] != 0; i += 2) { 817 if (phys_avail[i + 1] >= sz) { 818 translations = (struct ofw_map *)phys_avail[i]; 819 break; 820 } 821 } 822 if (translations == NULL) 823 panic("moea_bootstrap: no space to copy translations"); 824 bzero(translations, sz); 825 if (OF_getprop(mmu, "translations", translations, sz) == -1) 826 panic("moea_bootstrap: can't get ofw translations"); 827 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 828 sz /= sizeof(*translations); 829 qsort(translations, sz, sizeof (*translations), om_cmp); 830 for (i = 0, ofw_mappings = 0; i < sz; i++) { 831 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 832 translations[i].om_pa, translations[i].om_va, 833 translations[i].om_len); 834 835 /* 836 * If the mapping is 1:1, let the RAM and device on-demand 837 * BAT tables take care of the translation. 838 */ 839 if (translations[i].om_va == translations[i].om_pa) 840 continue; 841 842 /* Enter the pages */ 843 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 844 struct vm_page m; 845 846 m.phys_addr = translations[i].om_pa + off; 847 PMAP_LOCK(&ofw_pmap); 848 moea_enter_locked(&ofw_pmap, 849 translations[i].om_va + off, &m, 850 VM_PROT_ALL, 1); 851 PMAP_UNLOCK(&ofw_pmap); 852 ofw_mappings++; 853 } 854 } 855 #ifdef SMP 856 TLBSYNC(); 857 #endif 858 859 /* 860 * Initialize the kernel pmap (which is statically allocated). 861 */ 862 PMAP_LOCK_INIT(kernel_pmap); 863 for (i = 0; i < 16; i++) { 864 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 865 } 866 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 867 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 868 kernel_pmap->pm_active = ~0; 869 870 /* 871 * Allocate a kernel stack with a guard page for thread0 and map it 872 * into the kernel page map. 873 */ 874 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 875 kstack0_phys = pa; 876 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 877 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 878 kstack0); 879 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 880 for (i = 0; i < KSTACK_PAGES; i++) { 881 pa = kstack0_phys + i * PAGE_SIZE; 882 va = kstack0 + i * PAGE_SIZE; 883 moea_kenter(mmup, va, pa); 884 TLBIE(va); 885 } 886 887 /* 888 * Calculate the last available physical address. 889 */ 890 for (i = 0; phys_avail[i + 2] != 0; i += 2) 891 ; 892 Maxmem = powerpc_btop(phys_avail[i + 1]); 893 894 /* 895 * Allocate virtual address space for the message buffer. 896 */ 897 msgbufp = (struct msgbuf *)virtual_avail; 898 virtual_avail += round_page(MSGBUF_SIZE); 899 900 /* 901 * Initialize hardware. 902 */ 903 for (i = 0; i < 16; i++) { 904 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 905 } 906 __asm __volatile ("mtsr %0,%1" 907 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 908 __asm __volatile ("mtsr %0,%1" 909 :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 910 __asm __volatile ("sync; mtsdr1 %0; isync" 911 :: "r"((u_int)moea_pteg_table | (moea_pteg_mask >> 10))); 912 tlbia(); 913 914 pmap_bootstrapped++; 915 } 916 917 /* 918 * Activate a user pmap. The pmap must be activated before it's address 919 * space can be accessed in any way. 920 */ 921 void 922 moea_activate(mmu_t mmu, struct thread *td) 923 { 924 pmap_t pm, pmr; 925 926 /* 927 * Load all the data we need up front to encourage the compiler to 928 * not issue any loads while we have interrupts disabled below. 929 */ 930 pm = &td->td_proc->p_vmspace->vm_pmap; 931 932 if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL) 933 pmr = pm; 934 935 pm->pm_active |= PCPU_GET(cpumask); 936 PCPU_SET(curpmap, pmr); 937 } 938 939 void 940 moea_deactivate(mmu_t mmu, struct thread *td) 941 { 942 pmap_t pm; 943 944 pm = &td->td_proc->p_vmspace->vm_pmap; 945 pm->pm_active &= ~(PCPU_GET(cpumask)); 946 PCPU_SET(curpmap, NULL); 947 } 948 949 void 950 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 951 { 952 struct pvo_entry *pvo; 953 954 PMAP_LOCK(pm); 955 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 956 957 if (pvo != NULL) { 958 if (wired) { 959 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 960 pm->pm_stats.wired_count++; 961 pvo->pvo_vaddr |= PVO_WIRED; 962 } else { 963 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 964 pm->pm_stats.wired_count--; 965 pvo->pvo_vaddr &= ~PVO_WIRED; 966 } 967 } 968 PMAP_UNLOCK(pm); 969 } 970 971 void 972 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 973 { 974 vm_offset_t dst; 975 vm_offset_t src; 976 977 dst = VM_PAGE_TO_PHYS(mdst); 978 src = VM_PAGE_TO_PHYS(msrc); 979 980 kcopy((void *)src, (void *)dst, PAGE_SIZE); 981 } 982 983 /* 984 * Zero a page of physical memory by temporarily mapping it into the tlb. 985 */ 986 void 987 moea_zero_page(mmu_t mmu, vm_page_t m) 988 { 989 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 990 caddr_t va; 991 992 if (pa < SEGMENT_LENGTH) { 993 va = (caddr_t) pa; 994 } else if (moea_initialized) { 995 if (moea_pvo_zeropage == NULL) { 996 moea_pvo_zeropage = moea_rkva_alloc(mmu); 997 mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page", 998 NULL, MTX_DEF); 999 } 1000 mtx_lock(&moea_pvo_zeropage_mtx); 1001 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL); 1002 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage); 1003 } else { 1004 panic("moea_zero_page: can't zero pa %#x", pa); 1005 } 1006 1007 bzero(va, PAGE_SIZE); 1008 1009 if (pa >= SEGMENT_LENGTH) { 1010 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL); 1011 mtx_unlock(&moea_pvo_zeropage_mtx); 1012 } 1013 } 1014 1015 void 1016 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1017 { 1018 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1019 caddr_t va; 1020 1021 if (pa < SEGMENT_LENGTH) { 1022 va = (caddr_t) pa; 1023 } else if (moea_initialized) { 1024 if (moea_pvo_zeropage == NULL) { 1025 moea_pvo_zeropage = moea_rkva_alloc(mmu); 1026 mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page", 1027 NULL, MTX_DEF); 1028 } 1029 mtx_lock(&moea_pvo_zeropage_mtx); 1030 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL); 1031 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage); 1032 } else { 1033 panic("moea_zero_page: can't zero pa %#x", pa); 1034 } 1035 1036 bzero(va + off, size); 1037 1038 if (pa >= SEGMENT_LENGTH) { 1039 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL); 1040 mtx_unlock(&moea_pvo_zeropage_mtx); 1041 } 1042 } 1043 1044 void 1045 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1046 { 1047 1048 moea_zero_page(mmu, m); 1049 } 1050 1051 /* 1052 * Map the given physical page at the specified virtual address in the 1053 * target pmap with the protection requested. If specified the page 1054 * will be wired down. 1055 */ 1056 void 1057 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1058 boolean_t wired) 1059 { 1060 1061 vm_page_lock_queues(); 1062 PMAP_LOCK(pmap); 1063 moea_enter_locked(pmap, va, m, prot, wired); 1064 vm_page_unlock_queues(); 1065 PMAP_UNLOCK(pmap); 1066 } 1067 1068 /* 1069 * Map the given physical page at the specified virtual address in the 1070 * target pmap with the protection requested. If specified the page 1071 * will be wired down. 1072 * 1073 * The page queues and pmap must be locked. 1074 */ 1075 static void 1076 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1077 boolean_t wired) 1078 { 1079 struct pvo_head *pvo_head; 1080 uma_zone_t zone; 1081 vm_page_t pg; 1082 u_int pte_lo, pvo_flags, was_exec, i; 1083 int error; 1084 1085 if (!moea_initialized) { 1086 pvo_head = &moea_pvo_kunmanaged; 1087 zone = moea_upvo_zone; 1088 pvo_flags = 0; 1089 pg = NULL; 1090 was_exec = PTE_EXEC; 1091 } else { 1092 pvo_head = vm_page_to_pvoh(m); 1093 pg = m; 1094 zone = moea_mpvo_zone; 1095 pvo_flags = PVO_MANAGED; 1096 was_exec = 0; 1097 } 1098 if (pmap_bootstrapped) 1099 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1100 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1101 1102 /* XXX change the pvo head for fake pages */ 1103 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) 1104 pvo_head = &moea_pvo_kunmanaged; 1105 1106 /* 1107 * If this is a managed page, and it's the first reference to the page, 1108 * clear the execness of the page. Otherwise fetch the execness. 1109 */ 1110 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1111 if (LIST_EMPTY(pvo_head)) { 1112 moea_attr_clear(pg, PTE_EXEC); 1113 } else { 1114 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1115 } 1116 } 1117 1118 /* 1119 * Assume the page is cache inhibited and access is guarded unless 1120 * it's in our available memory array. 1121 */ 1122 pte_lo = PTE_I | PTE_G; 1123 for (i = 0; i < pregions_sz; i++) { 1124 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1125 (VM_PAGE_TO_PHYS(m) < 1126 (pregions[i].mr_start + pregions[i].mr_size))) { 1127 pte_lo &= ~(PTE_I | PTE_G); 1128 break; 1129 } 1130 } 1131 1132 if (prot & VM_PROT_WRITE) 1133 pte_lo |= PTE_BW; 1134 else 1135 pte_lo |= PTE_BR; 1136 1137 if (prot & VM_PROT_EXECUTE) 1138 pvo_flags |= PVO_EXECUTABLE; 1139 1140 if (wired) 1141 pvo_flags |= PVO_WIRED; 1142 1143 if ((m->flags & PG_FICTITIOUS) != 0) 1144 pvo_flags |= PVO_FAKE; 1145 1146 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1147 pte_lo, pvo_flags); 1148 1149 /* 1150 * Flush the real page from the instruction cache if this page is 1151 * mapped executable and cacheable and was not previously mapped (or 1152 * was not mapped executable). 1153 */ 1154 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1155 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1156 /* 1157 * Flush the real memory from the cache. 1158 */ 1159 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1160 if (pg != NULL) 1161 moea_attr_save(pg, PTE_EXEC); 1162 } 1163 1164 /* XXX syncicache always until problems are sorted */ 1165 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1166 } 1167 1168 /* 1169 * Maps a sequence of resident pages belonging to the same object. 1170 * The sequence begins with the given page m_start. This page is 1171 * mapped at the given virtual address start. Each subsequent page is 1172 * mapped at a virtual address that is offset from start by the same 1173 * amount as the page is offset from m_start within the object. The 1174 * last page in the sequence is the page with the largest offset from 1175 * m_start that can be mapped at a virtual address less than the given 1176 * virtual address end. Not every virtual page between start and end 1177 * is mapped; only those for which a resident page exists with the 1178 * corresponding offset from m_start are mapped. 1179 */ 1180 void 1181 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1182 vm_page_t m_start, vm_prot_t prot) 1183 { 1184 vm_page_t m; 1185 vm_pindex_t diff, psize; 1186 1187 psize = atop(end - start); 1188 m = m_start; 1189 PMAP_LOCK(pm); 1190 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1191 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1192 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1193 m = TAILQ_NEXT(m, listq); 1194 } 1195 PMAP_UNLOCK(pm); 1196 } 1197 1198 void 1199 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1200 vm_prot_t prot) 1201 { 1202 1203 PMAP_LOCK(pm); 1204 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1205 FALSE); 1206 PMAP_UNLOCK(pm); 1207 1208 } 1209 1210 vm_paddr_t 1211 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1212 { 1213 struct pvo_entry *pvo; 1214 vm_paddr_t pa; 1215 1216 PMAP_LOCK(pm); 1217 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1218 if (pvo == NULL) 1219 pa = 0; 1220 else 1221 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1222 PMAP_UNLOCK(pm); 1223 return (pa); 1224 } 1225 1226 /* 1227 * Atomically extract and hold the physical page with the given 1228 * pmap and virtual address pair if that mapping permits the given 1229 * protection. 1230 */ 1231 vm_page_t 1232 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1233 { 1234 struct pvo_entry *pvo; 1235 vm_page_t m; 1236 1237 m = NULL; 1238 vm_page_lock_queues(); 1239 PMAP_LOCK(pmap); 1240 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1241 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) && 1242 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW || 1243 (prot & VM_PROT_WRITE) == 0)) { 1244 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1245 vm_page_hold(m); 1246 } 1247 vm_page_unlock_queues(); 1248 PMAP_UNLOCK(pmap); 1249 return (m); 1250 } 1251 1252 void 1253 moea_init(mmu_t mmu) 1254 { 1255 1256 CTR0(KTR_PMAP, "moea_init"); 1257 1258 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1259 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1260 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1261 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1262 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1263 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1264 moea_initialized = TRUE; 1265 } 1266 1267 boolean_t 1268 moea_is_modified(mmu_t mmu, vm_page_t m) 1269 { 1270 1271 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1272 return (FALSE); 1273 1274 return (moea_query_bit(m, PTE_CHG)); 1275 } 1276 1277 void 1278 moea_clear_reference(mmu_t mmu, vm_page_t m) 1279 { 1280 1281 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1282 return; 1283 moea_clear_bit(m, PTE_REF, NULL); 1284 } 1285 1286 void 1287 moea_clear_modify(mmu_t mmu, vm_page_t m) 1288 { 1289 1290 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1291 return; 1292 moea_clear_bit(m, PTE_CHG, NULL); 1293 } 1294 1295 /* 1296 * Clear the write and modified bits in each of the given page's mappings. 1297 */ 1298 void 1299 moea_remove_write(mmu_t mmu, vm_page_t m) 1300 { 1301 struct pvo_entry *pvo; 1302 struct pte *pt; 1303 pmap_t pmap; 1304 u_int lo; 1305 1306 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1307 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1308 (m->flags & PG_WRITEABLE) == 0) 1309 return; 1310 lo = moea_attr_fetch(m); 1311 SYNC(); 1312 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1313 pmap = pvo->pvo_pmap; 1314 PMAP_LOCK(pmap); 1315 if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) { 1316 pt = moea_pvo_to_pte(pvo, -1); 1317 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1318 pvo->pvo_pte.pte_lo |= PTE_BR; 1319 if (pt != NULL) { 1320 moea_pte_synch(pt, &pvo->pvo_pte); 1321 lo |= pvo->pvo_pte.pte_lo; 1322 pvo->pvo_pte.pte_lo &= ~PTE_CHG; 1323 moea_pte_change(pt, &pvo->pvo_pte, 1324 pvo->pvo_vaddr); 1325 mtx_unlock(&moea_table_mutex); 1326 } 1327 } 1328 PMAP_UNLOCK(pmap); 1329 } 1330 if ((lo & PTE_CHG) != 0) { 1331 moea_attr_clear(m, PTE_CHG); 1332 vm_page_dirty(m); 1333 } 1334 vm_page_flag_clear(m, PG_WRITEABLE); 1335 } 1336 1337 /* 1338 * moea_ts_referenced: 1339 * 1340 * Return a count of reference bits for a page, clearing those bits. 1341 * It is not necessary for every reference bit to be cleared, but it 1342 * is necessary that 0 only be returned when there are truly no 1343 * reference bits set. 1344 * 1345 * XXX: The exact number of bits to check and clear is a matter that 1346 * should be tested and standardized at some point in the future for 1347 * optimal aging of shared pages. 1348 */ 1349 boolean_t 1350 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1351 { 1352 int count; 1353 1354 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1355 return (0); 1356 1357 count = moea_clear_bit(m, PTE_REF, NULL); 1358 1359 return (count); 1360 } 1361 1362 /* 1363 * Map a wired page into kernel virtual address space. 1364 */ 1365 void 1366 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1367 { 1368 u_int pte_lo; 1369 int error; 1370 int i; 1371 1372 #if 0 1373 if (va < VM_MIN_KERNEL_ADDRESS) 1374 panic("moea_kenter: attempt to enter non-kernel address %#x", 1375 va); 1376 #endif 1377 1378 pte_lo = PTE_I | PTE_G; 1379 for (i = 0; i < pregions_sz; i++) { 1380 if ((pa >= pregions[i].mr_start) && 1381 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1382 pte_lo &= ~(PTE_I | PTE_G); 1383 break; 1384 } 1385 } 1386 1387 PMAP_LOCK(kernel_pmap); 1388 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1389 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1390 1391 if (error != 0 && error != ENOENT) 1392 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1393 pa, error); 1394 1395 /* 1396 * Flush the real memory from the instruction cache. 1397 */ 1398 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1399 moea_syncicache(pa, PAGE_SIZE); 1400 } 1401 PMAP_UNLOCK(kernel_pmap); 1402 } 1403 1404 /* 1405 * Extract the physical page address associated with the given kernel virtual 1406 * address. 1407 */ 1408 vm_offset_t 1409 moea_kextract(mmu_t mmu, vm_offset_t va) 1410 { 1411 struct pvo_entry *pvo; 1412 vm_paddr_t pa; 1413 1414 #ifdef UMA_MD_SMALL_ALLOC 1415 /* 1416 * Allow direct mappings 1417 */ 1418 if (va < VM_MIN_KERNEL_ADDRESS) { 1419 return (va); 1420 } 1421 #endif 1422 1423 PMAP_LOCK(kernel_pmap); 1424 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1425 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1426 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1427 PMAP_UNLOCK(kernel_pmap); 1428 return (pa); 1429 } 1430 1431 /* 1432 * Remove a wired page from kernel virtual address space. 1433 */ 1434 void 1435 moea_kremove(mmu_t mmu, vm_offset_t va) 1436 { 1437 1438 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1439 } 1440 1441 /* 1442 * Map a range of physical addresses into kernel virtual address space. 1443 * 1444 * The value passed in *virt is a suggested virtual address for the mapping. 1445 * Architectures which can support a direct-mapped physical to virtual region 1446 * can return the appropriate address within that region, leaving '*virt' 1447 * unchanged. We cannot and therefore do not; *virt is updated with the 1448 * first usable address after the mapped region. 1449 */ 1450 vm_offset_t 1451 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1452 vm_offset_t pa_end, int prot) 1453 { 1454 vm_offset_t sva, va; 1455 1456 sva = *virt; 1457 va = sva; 1458 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1459 moea_kenter(mmu, va, pa_start); 1460 *virt = va; 1461 return (sva); 1462 } 1463 1464 /* 1465 * Returns true if the pmap's pv is one of the first 1466 * 16 pvs linked to from this page. This count may 1467 * be changed upwards or downwards in the future; it 1468 * is only necessary that true be returned for a small 1469 * subset of pmaps for proper page aging. 1470 */ 1471 boolean_t 1472 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1473 { 1474 int loops; 1475 struct pvo_entry *pvo; 1476 1477 if (!moea_initialized || (m->flags & PG_FICTITIOUS)) 1478 return FALSE; 1479 1480 loops = 0; 1481 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1482 if (pvo->pvo_pmap == pmap) 1483 return (TRUE); 1484 if (++loops >= 16) 1485 break; 1486 } 1487 1488 return (FALSE); 1489 } 1490 1491 static u_int moea_vsidcontext; 1492 1493 void 1494 moea_pinit(mmu_t mmu, pmap_t pmap) 1495 { 1496 int i, mask; 1497 u_int entropy; 1498 1499 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1500 PMAP_LOCK_INIT(pmap); 1501 1502 entropy = 0; 1503 __asm __volatile("mftb %0" : "=r"(entropy)); 1504 1505 /* 1506 * Allocate some segment registers for this pmap. 1507 */ 1508 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1509 u_int hash, n; 1510 1511 /* 1512 * Create a new value by mutiplying by a prime and adding in 1513 * entropy from the timebase register. This is to make the 1514 * VSID more random so that the PT hash function collides 1515 * less often. (Note that the prime casues gcc to do shifts 1516 * instead of a multiply.) 1517 */ 1518 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1519 hash = moea_vsidcontext & (NPMAPS - 1); 1520 if (hash == 0) /* 0 is special, avoid it */ 1521 continue; 1522 n = hash >> 5; 1523 mask = 1 << (hash & (VSID_NBPW - 1)); 1524 hash = (moea_vsidcontext & 0xfffff); 1525 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1526 /* anything free in this bucket? */ 1527 if (moea_vsid_bitmap[n] == 0xffffffff) { 1528 entropy = (moea_vsidcontext >> 20); 1529 continue; 1530 } 1531 i = ffs(~moea_vsid_bitmap[i]) - 1; 1532 mask = 1 << i; 1533 hash &= 0xfffff & ~(VSID_NBPW - 1); 1534 hash |= i; 1535 } 1536 moea_vsid_bitmap[n] |= mask; 1537 for (i = 0; i < 16; i++) 1538 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1539 return; 1540 } 1541 1542 panic("moea_pinit: out of segments"); 1543 } 1544 1545 /* 1546 * Initialize the pmap associated with process 0. 1547 */ 1548 void 1549 moea_pinit0(mmu_t mmu, pmap_t pm) 1550 { 1551 1552 moea_pinit(mmu, pm); 1553 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1554 } 1555 1556 /* 1557 * Set the physical protection on the specified range of this map as requested. 1558 */ 1559 void 1560 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1561 vm_prot_t prot) 1562 { 1563 struct pvo_entry *pvo; 1564 struct pte *pt; 1565 int pteidx; 1566 1567 CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1568 eva, prot); 1569 1570 1571 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1572 ("moea_protect: non current pmap")); 1573 1574 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1575 moea_remove(mmu, pm, sva, eva); 1576 return; 1577 } 1578 1579 vm_page_lock_queues(); 1580 PMAP_LOCK(pm); 1581 for (; sva < eva; sva += PAGE_SIZE) { 1582 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1583 if (pvo == NULL) 1584 continue; 1585 1586 if ((prot & VM_PROT_EXECUTE) == 0) 1587 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1588 1589 /* 1590 * Grab the PTE pointer before we diddle with the cached PTE 1591 * copy. 1592 */ 1593 pt = moea_pvo_to_pte(pvo, pteidx); 1594 /* 1595 * Change the protection of the page. 1596 */ 1597 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1598 pvo->pvo_pte.pte_lo |= PTE_BR; 1599 1600 /* 1601 * If the PVO is in the page table, update that pte as well. 1602 */ 1603 if (pt != NULL) { 1604 moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1605 mtx_unlock(&moea_table_mutex); 1606 } 1607 } 1608 vm_page_unlock_queues(); 1609 PMAP_UNLOCK(pm); 1610 } 1611 1612 /* 1613 * Map a list of wired pages into kernel virtual address space. This is 1614 * intended for temporary mappings which do not need page modification or 1615 * references recorded. Existing mappings in the region are overwritten. 1616 */ 1617 void 1618 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1619 { 1620 vm_offset_t va; 1621 1622 va = sva; 1623 while (count-- > 0) { 1624 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1625 va += PAGE_SIZE; 1626 m++; 1627 } 1628 } 1629 1630 /* 1631 * Remove page mappings from kernel virtual address space. Intended for 1632 * temporary mappings entered by moea_qenter. 1633 */ 1634 void 1635 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1636 { 1637 vm_offset_t va; 1638 1639 va = sva; 1640 while (count-- > 0) { 1641 moea_kremove(mmu, va); 1642 va += PAGE_SIZE; 1643 } 1644 } 1645 1646 void 1647 moea_release(mmu_t mmu, pmap_t pmap) 1648 { 1649 int idx, mask; 1650 1651 /* 1652 * Free segment register's VSID 1653 */ 1654 if (pmap->pm_sr[0] == 0) 1655 panic("moea_release"); 1656 1657 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1658 mask = 1 << (idx % VSID_NBPW); 1659 idx /= VSID_NBPW; 1660 moea_vsid_bitmap[idx] &= ~mask; 1661 PMAP_LOCK_DESTROY(pmap); 1662 } 1663 1664 /* 1665 * Remove the given range of addresses from the specified map. 1666 */ 1667 void 1668 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1669 { 1670 struct pvo_entry *pvo; 1671 int pteidx; 1672 1673 vm_page_lock_queues(); 1674 PMAP_LOCK(pm); 1675 for (; sva < eva; sva += PAGE_SIZE) { 1676 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1677 if (pvo != NULL) { 1678 moea_pvo_remove(pvo, pteidx); 1679 } 1680 } 1681 PMAP_UNLOCK(pm); 1682 vm_page_unlock_queues(); 1683 } 1684 1685 /* 1686 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1687 * will reflect changes in pte's back to the vm_page. 1688 */ 1689 void 1690 moea_remove_all(mmu_t mmu, vm_page_t m) 1691 { 1692 struct pvo_head *pvo_head; 1693 struct pvo_entry *pvo, *next_pvo; 1694 pmap_t pmap; 1695 1696 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1697 1698 pvo_head = vm_page_to_pvoh(m); 1699 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1700 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1701 1702 MOEA_PVO_CHECK(pvo); /* sanity check */ 1703 pmap = pvo->pvo_pmap; 1704 PMAP_LOCK(pmap); 1705 moea_pvo_remove(pvo, -1); 1706 PMAP_UNLOCK(pmap); 1707 } 1708 vm_page_flag_clear(m, PG_WRITEABLE); 1709 } 1710 1711 /* 1712 * Allocate a physical page of memory directly from the phys_avail map. 1713 * Can only be called from moea_bootstrap before avail start and end are 1714 * calculated. 1715 */ 1716 static vm_offset_t 1717 moea_bootstrap_alloc(vm_size_t size, u_int align) 1718 { 1719 vm_offset_t s, e; 1720 int i, j; 1721 1722 size = round_page(size); 1723 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1724 if (align != 0) 1725 s = (phys_avail[i] + align - 1) & ~(align - 1); 1726 else 1727 s = phys_avail[i]; 1728 e = s + size; 1729 1730 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1731 continue; 1732 1733 if (s == phys_avail[i]) { 1734 phys_avail[i] += size; 1735 } else if (e == phys_avail[i + 1]) { 1736 phys_avail[i + 1] -= size; 1737 } else { 1738 for (j = phys_avail_count * 2; j > i; j -= 2) { 1739 phys_avail[j] = phys_avail[j - 2]; 1740 phys_avail[j + 1] = phys_avail[j - 1]; 1741 } 1742 1743 phys_avail[i + 3] = phys_avail[i + 1]; 1744 phys_avail[i + 1] = s; 1745 phys_avail[i + 2] = e; 1746 phys_avail_count++; 1747 } 1748 1749 return (s); 1750 } 1751 panic("moea_bootstrap_alloc: could not allocate memory"); 1752 } 1753 1754 /* 1755 * Return an unmapped pvo for a kernel virtual address. 1756 * Used by pmap functions that operate on physical pages. 1757 */ 1758 static struct pvo_entry * 1759 moea_rkva_alloc(mmu_t mmu) 1760 { 1761 struct pvo_entry *pvo; 1762 struct pte *pt; 1763 vm_offset_t kva; 1764 int pteidx; 1765 1766 if (moea_rkva_count == 0) 1767 panic("moea_rkva_alloc: no more reserved KVAs"); 1768 1769 kva = moea_rkva_start + (PAGE_SIZE * --moea_rkva_count); 1770 moea_kenter(mmu, kva, 0); 1771 1772 pvo = moea_pvo_find_va(kernel_pmap, kva, &pteidx); 1773 1774 if (pvo == NULL) 1775 panic("moea_kva_alloc: moea_pvo_find_va failed"); 1776 1777 pt = moea_pvo_to_pte(pvo, pteidx); 1778 1779 if (pt == NULL) 1780 panic("moea_kva_alloc: moea_pvo_to_pte failed"); 1781 1782 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1783 mtx_unlock(&moea_table_mutex); 1784 PVO_PTEGIDX_CLR(pvo); 1785 1786 moea_pte_overflow++; 1787 1788 return (pvo); 1789 } 1790 1791 static void 1792 moea_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1793 int *depth_p) 1794 { 1795 struct pte *pt; 1796 1797 /* 1798 * If this pvo already has a valid pte, we need to save it so it can 1799 * be restored later. We then just reload the new PTE over the old 1800 * slot. 1801 */ 1802 if (saved_pt != NULL) { 1803 pt = moea_pvo_to_pte(pvo, -1); 1804 1805 if (pt != NULL) { 1806 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1807 mtx_unlock(&moea_table_mutex); 1808 PVO_PTEGIDX_CLR(pvo); 1809 moea_pte_overflow++; 1810 } 1811 1812 *saved_pt = pvo->pvo_pte; 1813 1814 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1815 } 1816 1817 pvo->pvo_pte.pte_lo |= pa; 1818 1819 if (!moea_pte_spill(pvo->pvo_vaddr)) 1820 panic("moea_pa_map: could not spill pvo %p", pvo); 1821 1822 if (depth_p != NULL) 1823 (*depth_p)++; 1824 } 1825 1826 static void 1827 moea_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1828 { 1829 struct pte *pt; 1830 1831 pt = moea_pvo_to_pte(pvo, -1); 1832 1833 if (pt != NULL) { 1834 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1835 mtx_unlock(&moea_table_mutex); 1836 PVO_PTEGIDX_CLR(pvo); 1837 moea_pte_overflow++; 1838 } 1839 1840 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1841 1842 /* 1843 * If there is a saved PTE and it's valid, restore it and return. 1844 */ 1845 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1846 if (depth_p != NULL && --(*depth_p) == 0) 1847 panic("moea_pa_unmap: restoring but depth == 0"); 1848 1849 pvo->pvo_pte = *saved_pt; 1850 1851 if (!moea_pte_spill(pvo->pvo_vaddr)) 1852 panic("moea_pa_unmap: could not spill pvo %p", pvo); 1853 } 1854 } 1855 1856 static void 1857 moea_syncicache(vm_offset_t pa, vm_size_t len) 1858 { 1859 __syncicache((void *)pa, len); 1860 } 1861 1862 static void 1863 tlbia(void) 1864 { 1865 caddr_t i; 1866 1867 SYNC(); 1868 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1869 TLBIE(i); 1870 EIEIO(); 1871 } 1872 TLBSYNC(); 1873 SYNC(); 1874 } 1875 1876 static int 1877 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1878 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1879 { 1880 struct pvo_entry *pvo; 1881 u_int sr; 1882 int first; 1883 u_int ptegidx; 1884 int i; 1885 int bootstrap; 1886 1887 moea_pvo_enter_calls++; 1888 first = 0; 1889 bootstrap = 0; 1890 1891 /* 1892 * Compute the PTE Group index. 1893 */ 1894 va &= ~ADDR_POFF; 1895 sr = va_to_sr(pm->pm_sr, va); 1896 ptegidx = va_to_pteg(sr, va); 1897 1898 /* 1899 * Remove any existing mapping for this page. Reuse the pvo entry if 1900 * there is a mapping. 1901 */ 1902 mtx_lock(&moea_table_mutex); 1903 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1904 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1905 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1906 (pvo->pvo_pte.pte_lo & PTE_PP) == 1907 (pte_lo & PTE_PP)) { 1908 mtx_unlock(&moea_table_mutex); 1909 return (0); 1910 } 1911 moea_pvo_remove(pvo, -1); 1912 break; 1913 } 1914 } 1915 1916 /* 1917 * If we aren't overwriting a mapping, try to allocate. 1918 */ 1919 if (moea_initialized) { 1920 pvo = uma_zalloc(zone, M_NOWAIT); 1921 } else { 1922 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1923 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1924 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1925 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1926 } 1927 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1928 moea_bpvo_pool_index++; 1929 bootstrap = 1; 1930 } 1931 1932 if (pvo == NULL) { 1933 mtx_unlock(&moea_table_mutex); 1934 return (ENOMEM); 1935 } 1936 1937 moea_pvo_entries++; 1938 pvo->pvo_vaddr = va; 1939 pvo->pvo_pmap = pm; 1940 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1941 pvo->pvo_vaddr &= ~ADDR_POFF; 1942 if (flags & VM_PROT_EXECUTE) 1943 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1944 if (flags & PVO_WIRED) 1945 pvo->pvo_vaddr |= PVO_WIRED; 1946 if (pvo_head != &moea_pvo_kunmanaged) 1947 pvo->pvo_vaddr |= PVO_MANAGED; 1948 if (bootstrap) 1949 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1950 if (flags & PVO_FAKE) 1951 pvo->pvo_vaddr |= PVO_FAKE; 1952 1953 moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1954 1955 /* 1956 * Remember if the list was empty and therefore will be the first 1957 * item. 1958 */ 1959 if (LIST_FIRST(pvo_head) == NULL) 1960 first = 1; 1961 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1962 1963 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1964 pm->pm_stats.wired_count++; 1965 pm->pm_stats.resident_count++; 1966 1967 /* 1968 * We hope this succeeds but it isn't required. 1969 */ 1970 i = moea_pte_insert(ptegidx, &pvo->pvo_pte); 1971 if (i >= 0) { 1972 PVO_PTEGIDX_SET(pvo, i); 1973 } else { 1974 panic("moea_pvo_enter: overflow"); 1975 moea_pte_overflow++; 1976 } 1977 mtx_unlock(&moea_table_mutex); 1978 1979 return (first ? ENOENT : 0); 1980 } 1981 1982 static void 1983 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1984 { 1985 struct pte *pt; 1986 1987 /* 1988 * If there is an active pte entry, we need to deactivate it (and 1989 * save the ref & cfg bits). 1990 */ 1991 pt = moea_pvo_to_pte(pvo, pteidx); 1992 if (pt != NULL) { 1993 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1994 mtx_unlock(&moea_table_mutex); 1995 PVO_PTEGIDX_CLR(pvo); 1996 } else { 1997 moea_pte_overflow--; 1998 } 1999 2000 /* 2001 * Update our statistics. 2002 */ 2003 pvo->pvo_pmap->pm_stats.resident_count--; 2004 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 2005 pvo->pvo_pmap->pm_stats.wired_count--; 2006 2007 /* 2008 * Save the REF/CHG bits into their cache if the page is managed. 2009 */ 2010 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2011 struct vm_page *pg; 2012 2013 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 2014 if (pg != NULL) { 2015 moea_attr_save(pg, pvo->pvo_pte.pte_lo & 2016 (PTE_REF | PTE_CHG)); 2017 } 2018 } 2019 2020 /* 2021 * Remove this PVO from the PV list. 2022 */ 2023 LIST_REMOVE(pvo, pvo_vlink); 2024 2025 /* 2026 * Remove this from the overflow list and return it to the pool 2027 * if we aren't going to reuse it. 2028 */ 2029 LIST_REMOVE(pvo, pvo_olink); 2030 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2031 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2032 moea_upvo_zone, pvo); 2033 moea_pvo_entries--; 2034 moea_pvo_remove_calls++; 2035 } 2036 2037 static __inline int 2038 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2039 { 2040 int pteidx; 2041 2042 /* 2043 * We can find the actual pte entry without searching by grabbing 2044 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2045 * noticing the HID bit. 2046 */ 2047 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2048 if (pvo->pvo_pte.pte_hi & PTE_HID) 2049 pteidx ^= moea_pteg_mask * 8; 2050 2051 return (pteidx); 2052 } 2053 2054 static struct pvo_entry * 2055 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2056 { 2057 struct pvo_entry *pvo; 2058 int ptegidx; 2059 u_int sr; 2060 2061 va &= ~ADDR_POFF; 2062 sr = va_to_sr(pm->pm_sr, va); 2063 ptegidx = va_to_pteg(sr, va); 2064 2065 mtx_lock(&moea_table_mutex); 2066 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2067 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2068 if (pteidx_p) 2069 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2070 break; 2071 } 2072 } 2073 mtx_unlock(&moea_table_mutex); 2074 2075 return (pvo); 2076 } 2077 2078 static struct pte * 2079 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2080 { 2081 struct pte *pt; 2082 2083 /* 2084 * If we haven't been supplied the ptegidx, calculate it. 2085 */ 2086 if (pteidx == -1) { 2087 int ptegidx; 2088 u_int sr; 2089 2090 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2091 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2092 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2093 } 2094 2095 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2096 mtx_lock(&moea_table_mutex); 2097 2098 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2099 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2100 "valid pte index", pvo); 2101 } 2102 2103 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2104 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2105 "pvo but no valid pte", pvo); 2106 } 2107 2108 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2109 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 2110 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2111 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2112 } 2113 2114 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2115 != 0) { 2116 panic("moea_pvo_to_pte: pvo %p pte does not match " 2117 "pte %p in moea_pteg_table", pvo, pt); 2118 } 2119 2120 mtx_assert(&moea_table_mutex, MA_OWNED); 2121 return (pt); 2122 } 2123 2124 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2125 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2126 "moea_pteg_table but valid in pvo", pvo, pt); 2127 } 2128 2129 mtx_unlock(&moea_table_mutex); 2130 return (NULL); 2131 } 2132 2133 /* 2134 * XXX: THIS STUFF SHOULD BE IN pte.c? 2135 */ 2136 int 2137 moea_pte_spill(vm_offset_t addr) 2138 { 2139 struct pvo_entry *source_pvo, *victim_pvo; 2140 struct pvo_entry *pvo; 2141 int ptegidx, i, j; 2142 u_int sr; 2143 struct pteg *pteg; 2144 struct pte *pt; 2145 2146 moea_pte_spills++; 2147 2148 sr = mfsrin(addr); 2149 ptegidx = va_to_pteg(sr, addr); 2150 2151 /* 2152 * Have to substitute some entry. Use the primary hash for this. 2153 * Use low bits of timebase as random generator. 2154 */ 2155 pteg = &moea_pteg_table[ptegidx]; 2156 mtx_lock(&moea_table_mutex); 2157 __asm __volatile("mftb %0" : "=r"(i)); 2158 i &= 7; 2159 pt = &pteg->pt[i]; 2160 2161 source_pvo = NULL; 2162 victim_pvo = NULL; 2163 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2164 /* 2165 * We need to find a pvo entry for this address. 2166 */ 2167 MOEA_PVO_CHECK(pvo); 2168 if (source_pvo == NULL && 2169 moea_pte_match(&pvo->pvo_pte, sr, addr, 2170 pvo->pvo_pte.pte_hi & PTE_HID)) { 2171 /* 2172 * Now found an entry to be spilled into the pteg. 2173 * The PTE is now valid, so we know it's active. 2174 */ 2175 j = moea_pte_insert(ptegidx, &pvo->pvo_pte); 2176 2177 if (j >= 0) { 2178 PVO_PTEGIDX_SET(pvo, j); 2179 moea_pte_overflow--; 2180 MOEA_PVO_CHECK(pvo); 2181 mtx_unlock(&moea_table_mutex); 2182 return (1); 2183 } 2184 2185 source_pvo = pvo; 2186 2187 if (victim_pvo != NULL) 2188 break; 2189 } 2190 2191 /* 2192 * We also need the pvo entry of the victim we are replacing 2193 * so save the R & C bits of the PTE. 2194 */ 2195 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2196 moea_pte_compare(pt, &pvo->pvo_pte)) { 2197 victim_pvo = pvo; 2198 if (source_pvo != NULL) 2199 break; 2200 } 2201 } 2202 2203 if (source_pvo == NULL) { 2204 mtx_unlock(&moea_table_mutex); 2205 return (0); 2206 } 2207 2208 if (victim_pvo == NULL) { 2209 if ((pt->pte_hi & PTE_HID) == 0) 2210 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2211 "entry", pt); 2212 2213 /* 2214 * If this is a secondary PTE, we need to search it's primary 2215 * pvo bucket for the matching PVO. 2216 */ 2217 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2218 pvo_olink) { 2219 MOEA_PVO_CHECK(pvo); 2220 /* 2221 * We also need the pvo entry of the victim we are 2222 * replacing so save the R & C bits of the PTE. 2223 */ 2224 if (moea_pte_compare(pt, &pvo->pvo_pte)) { 2225 victim_pvo = pvo; 2226 break; 2227 } 2228 } 2229 2230 if (victim_pvo == NULL) 2231 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2232 "entry", pt); 2233 } 2234 2235 /* 2236 * We are invalidating the TLB entry for the EA we are replacing even 2237 * though it's valid. If we don't, we lose any ref/chg bit changes 2238 * contained in the TLB entry. 2239 */ 2240 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2241 2242 moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2243 moea_pte_set(pt, &source_pvo->pvo_pte); 2244 2245 PVO_PTEGIDX_CLR(victim_pvo); 2246 PVO_PTEGIDX_SET(source_pvo, i); 2247 moea_pte_replacements++; 2248 2249 MOEA_PVO_CHECK(victim_pvo); 2250 MOEA_PVO_CHECK(source_pvo); 2251 2252 mtx_unlock(&moea_table_mutex); 2253 return (1); 2254 } 2255 2256 static int 2257 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2258 { 2259 struct pte *pt; 2260 int i; 2261 2262 mtx_assert(&moea_table_mutex, MA_OWNED); 2263 2264 /* 2265 * First try primary hash. 2266 */ 2267 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2268 if ((pt->pte_hi & PTE_VALID) == 0) { 2269 pvo_pt->pte_hi &= ~PTE_HID; 2270 moea_pte_set(pt, pvo_pt); 2271 return (i); 2272 } 2273 } 2274 2275 /* 2276 * Now try secondary hash. 2277 */ 2278 ptegidx ^= moea_pteg_mask; 2279 ptegidx++; 2280 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2281 if ((pt->pte_hi & PTE_VALID) == 0) { 2282 pvo_pt->pte_hi |= PTE_HID; 2283 moea_pte_set(pt, pvo_pt); 2284 return (i); 2285 } 2286 } 2287 2288 panic("moea_pte_insert: overflow"); 2289 return (-1); 2290 } 2291 2292 static boolean_t 2293 moea_query_bit(vm_page_t m, int ptebit) 2294 { 2295 struct pvo_entry *pvo; 2296 struct pte *pt; 2297 2298 #if 0 2299 if (moea_attr_fetch(m) & ptebit) 2300 return (TRUE); 2301 #endif 2302 2303 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2304 MOEA_PVO_CHECK(pvo); /* sanity check */ 2305 2306 /* 2307 * See if we saved the bit off. If so, cache it and return 2308 * success. 2309 */ 2310 if (pvo->pvo_pte.pte_lo & ptebit) { 2311 moea_attr_save(m, ptebit); 2312 MOEA_PVO_CHECK(pvo); /* sanity check */ 2313 return (TRUE); 2314 } 2315 } 2316 2317 /* 2318 * No luck, now go through the hard part of looking at the PTEs 2319 * themselves. Sync so that any pending REF/CHG bits are flushed to 2320 * the PTEs. 2321 */ 2322 SYNC(); 2323 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2324 MOEA_PVO_CHECK(pvo); /* sanity check */ 2325 2326 /* 2327 * See if this pvo has a valid PTE. if so, fetch the 2328 * REF/CHG bits from the valid PTE. If the appropriate 2329 * ptebit is set, cache it and return success. 2330 */ 2331 pt = moea_pvo_to_pte(pvo, -1); 2332 if (pt != NULL) { 2333 moea_pte_synch(pt, &pvo->pvo_pte); 2334 mtx_unlock(&moea_table_mutex); 2335 if (pvo->pvo_pte.pte_lo & ptebit) { 2336 moea_attr_save(m, ptebit); 2337 MOEA_PVO_CHECK(pvo); /* sanity check */ 2338 return (TRUE); 2339 } 2340 } 2341 } 2342 2343 return (FALSE); 2344 } 2345 2346 static u_int 2347 moea_clear_bit(vm_page_t m, int ptebit, int *origbit) 2348 { 2349 u_int count; 2350 struct pvo_entry *pvo; 2351 struct pte *pt; 2352 int rv; 2353 2354 /* 2355 * Clear the cached value. 2356 */ 2357 rv = moea_attr_fetch(m); 2358 moea_attr_clear(m, ptebit); 2359 2360 /* 2361 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2362 * we can reset the right ones). note that since the pvo entries and 2363 * list heads are accessed via BAT0 and are never placed in the page 2364 * table, we don't have to worry about further accesses setting the 2365 * REF/CHG bits. 2366 */ 2367 SYNC(); 2368 2369 /* 2370 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2371 * valid pte clear the ptebit from the valid pte. 2372 */ 2373 count = 0; 2374 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2375 MOEA_PVO_CHECK(pvo); /* sanity check */ 2376 pt = moea_pvo_to_pte(pvo, -1); 2377 if (pt != NULL) { 2378 moea_pte_synch(pt, &pvo->pvo_pte); 2379 if (pvo->pvo_pte.pte_lo & ptebit) { 2380 count++; 2381 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2382 } 2383 mtx_unlock(&moea_table_mutex); 2384 } 2385 rv |= pvo->pvo_pte.pte_lo; 2386 pvo->pvo_pte.pte_lo &= ~ptebit; 2387 MOEA_PVO_CHECK(pvo); /* sanity check */ 2388 } 2389 2390 if (origbit != NULL) { 2391 *origbit = rv; 2392 } 2393 2394 return (count); 2395 } 2396 2397 /* 2398 * Return true if the physical range is encompassed by the battable[idx] 2399 */ 2400 static int 2401 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2402 { 2403 u_int prot; 2404 u_int32_t start; 2405 u_int32_t end; 2406 u_int32_t bat_ble; 2407 2408 /* 2409 * Return immediately if not a valid mapping 2410 */ 2411 if (!battable[idx].batu & BAT_Vs) 2412 return (EINVAL); 2413 2414 /* 2415 * The BAT entry must be cache-inhibited, guarded, and r/w 2416 * so it can function as an i/o page 2417 */ 2418 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2419 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2420 return (EPERM); 2421 2422 /* 2423 * The address should be within the BAT range. Assume that the 2424 * start address in the BAT has the correct alignment (thus 2425 * not requiring masking) 2426 */ 2427 start = battable[idx].batl & BAT_PBS; 2428 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2429 end = start | (bat_ble << 15) | 0x7fff; 2430 2431 if ((pa < start) || ((pa + size) > end)) 2432 return (ERANGE); 2433 2434 return (0); 2435 } 2436 2437 boolean_t 2438 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2439 { 2440 int i; 2441 2442 /* 2443 * This currently does not work for entries that 2444 * overlap 256M BAT segments. 2445 */ 2446 2447 for(i = 0; i < 16; i++) 2448 if (moea_bat_mapped(i, pa, size) == 0) 2449 return (0); 2450 2451 return (EFAULT); 2452 } 2453 2454 /* 2455 * Map a set of physical memory pages into the kernel virtual 2456 * address space. Return a pointer to where it is mapped. This 2457 * routine is intended to be used for mapping device memory, 2458 * NOT real memory. 2459 */ 2460 void * 2461 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2462 { 2463 vm_offset_t va, tmpva, ppa, offset; 2464 int i; 2465 2466 ppa = trunc_page(pa); 2467 offset = pa & PAGE_MASK; 2468 size = roundup(offset + size, PAGE_SIZE); 2469 2470 GIANT_REQUIRED; 2471 2472 /* 2473 * If the physical address lies within a valid BAT table entry, 2474 * return the 1:1 mapping. This currently doesn't work 2475 * for regions that overlap 256M BAT segments. 2476 */ 2477 for (i = 0; i < 16; i++) { 2478 if (moea_bat_mapped(i, pa, size) == 0) 2479 return ((void *) pa); 2480 } 2481 2482 va = kmem_alloc_nofault(kernel_map, size); 2483 if (!va) 2484 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2485 2486 for (tmpva = va; size > 0;) { 2487 moea_kenter(mmu, tmpva, ppa); 2488 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2489 size -= PAGE_SIZE; 2490 tmpva += PAGE_SIZE; 2491 ppa += PAGE_SIZE; 2492 } 2493 2494 return ((void *)(va + offset)); 2495 } 2496 2497 void 2498 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2499 { 2500 vm_offset_t base, offset; 2501 2502 /* 2503 * If this is outside kernel virtual space, then it's a 2504 * battable entry and doesn't require unmapping 2505 */ 2506 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2507 base = trunc_page(va); 2508 offset = va & PAGE_MASK; 2509 size = roundup(offset + size, PAGE_SIZE); 2510 kmem_free(kernel_map, base, size); 2511 } 2512 } 2513