xref: /freebsd/sys/powerpc/aim/mmu_oea.c (revision a98ff317388a00b992f1bf8404dee596f9383f5e)
1 /*-
2  * Copyright (c) 2001 The NetBSD Foundation, Inc.
3  * All rights reserved.
4  *
5  * This code is derived from software contributed to The NetBSD Foundation
6  * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *        This product includes software developed by the NetBSD
19  *        Foundation, Inc. and its contributors.
20  * 4. Neither the name of The NetBSD Foundation nor the names of its
21  *    contributors may be used to endorse or promote products derived
22  *    from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  * POSSIBILITY OF SUCH DAMAGE.
35  */
36 /*-
37  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38  * Copyright (C) 1995, 1996 TooLs GmbH.
39  * All rights reserved.
40  *
41  * Redistribution and use in source and binary forms, with or without
42  * modification, are permitted provided that the following conditions
43  * are met:
44  * 1. Redistributions of source code must retain the above copyright
45  *    notice, this list of conditions and the following disclaimer.
46  * 2. Redistributions in binary form must reproduce the above copyright
47  *    notice, this list of conditions and the following disclaimer in the
48  *    documentation and/or other materials provided with the distribution.
49  * 3. All advertising materials mentioning features or use of this software
50  *    must display the following acknowledgement:
51  *	This product includes software developed by TooLs GmbH.
52  * 4. The name of TooLs GmbH may not be used to endorse or promote products
53  *    derived from this software without specific prior written permission.
54  *
55  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65  *
66  * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
67  */
68 /*-
69  * Copyright (C) 2001 Benno Rice.
70  * All rights reserved.
71  *
72  * Redistribution and use in source and binary forms, with or without
73  * modification, are permitted provided that the following conditions
74  * are met:
75  * 1. Redistributions of source code must retain the above copyright
76  *    notice, this list of conditions and the following disclaimer.
77  * 2. Redistributions in binary form must reproduce the above copyright
78  *    notice, this list of conditions and the following disclaimer in the
79  *    documentation and/or other materials provided with the distribution.
80  *
81  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
91  */
92 
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
95 
96 /*
97  * Manages physical address maps.
98  *
99  * Since the information managed by this module is also stored by the
100  * logical address mapping module, this module may throw away valid virtual
101  * to physical mappings at almost any time.  However, invalidations of
102  * mappings must be done as requested.
103  *
104  * In order to cope with hardware architectures which make virtual to
105  * physical map invalidates expensive, this module may delay invalidate
106  * reduced protection operations until such time as they are actually
107  * necessary.  This module is given full information as to which processors
108  * are currently using which maps, and to when physical maps must be made
109  * correct.
110  */
111 
112 #include "opt_kstack_pages.h"
113 
114 #include <sys/param.h>
115 #include <sys/kernel.h>
116 #include <sys/queue.h>
117 #include <sys/cpuset.h>
118 #include <sys/ktr.h>
119 #include <sys/lock.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #include <sys/systm.h>
127 #include <sys/vmmeter.h>
128 
129 #include <dev/ofw/openfirm.h>
130 
131 #include <vm/vm.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/uma.h>
140 
141 #include <machine/cpu.h>
142 #include <machine/platform.h>
143 #include <machine/bat.h>
144 #include <machine/frame.h>
145 #include <machine/md_var.h>
146 #include <machine/psl.h>
147 #include <machine/pte.h>
148 #include <machine/smp.h>
149 #include <machine/sr.h>
150 #include <machine/mmuvar.h>
151 #include <machine/trap_aim.h>
152 
153 #include "mmu_if.h"
154 
155 #define	MOEA_DEBUG
156 
157 #define TODO	panic("%s: not implemented", __func__);
158 
159 #define	VSID_MAKE(sr, hash)	((sr) | (((hash) & 0xfffff) << 4))
160 #define	VSID_TO_SR(vsid)	((vsid) & 0xf)
161 #define	VSID_TO_HASH(vsid)	(((vsid) >> 4) & 0xfffff)
162 
163 struct ofw_map {
164 	vm_offset_t	om_va;
165 	vm_size_t	om_len;
166 	vm_offset_t	om_pa;
167 	u_int		om_mode;
168 };
169 
170 extern unsigned char _etext[];
171 extern unsigned char _end[];
172 
173 extern int dumpsys_minidump;
174 
175 /*
176  * Map of physical memory regions.
177  */
178 static struct	mem_region *regions;
179 static struct	mem_region *pregions;
180 static u_int    phys_avail_count;
181 static int	regions_sz, pregions_sz;
182 static struct	ofw_map *translations;
183 
184 /*
185  * Lock for the pteg and pvo tables.
186  */
187 struct mtx	moea_table_mutex;
188 struct mtx	moea_vsid_mutex;
189 
190 /* tlbie instruction synchronization */
191 static struct mtx tlbie_mtx;
192 
193 /*
194  * PTEG data.
195  */
196 static struct	pteg *moea_pteg_table;
197 u_int		moea_pteg_count;
198 u_int		moea_pteg_mask;
199 
200 /*
201  * PVO data.
202  */
203 struct	pvo_head *moea_pvo_table;		/* pvo entries by pteg index */
204 struct	pvo_head moea_pvo_kunmanaged =
205     LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged);	/* list of unmanaged pages */
206 
207 static struct rwlock_padalign pvh_global_lock;
208 
209 uma_zone_t	moea_upvo_zone;	/* zone for pvo entries for unmanaged pages */
210 uma_zone_t	moea_mpvo_zone;	/* zone for pvo entries for managed pages */
211 
212 #define	BPVO_POOL_SIZE	32768
213 static struct	pvo_entry *moea_bpvo_pool;
214 static int	moea_bpvo_pool_index = 0;
215 
216 #define	VSID_NBPW	(sizeof(u_int32_t) * 8)
217 static u_int	moea_vsid_bitmap[NPMAPS / VSID_NBPW];
218 
219 static boolean_t moea_initialized = FALSE;
220 
221 /*
222  * Statistics.
223  */
224 u_int	moea_pte_valid = 0;
225 u_int	moea_pte_overflow = 0;
226 u_int	moea_pte_replacements = 0;
227 u_int	moea_pvo_entries = 0;
228 u_int	moea_pvo_enter_calls = 0;
229 u_int	moea_pvo_remove_calls = 0;
230 u_int	moea_pte_spills = 0;
231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
232     0, "");
233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
234     &moea_pte_overflow, 0, "");
235 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
236     &moea_pte_replacements, 0, "");
237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
238     0, "");
239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
240     &moea_pvo_enter_calls, 0, "");
241 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
242     &moea_pvo_remove_calls, 0, "");
243 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
244     &moea_pte_spills, 0, "");
245 
246 /*
247  * Allocate physical memory for use in moea_bootstrap.
248  */
249 static vm_offset_t	moea_bootstrap_alloc(vm_size_t, u_int);
250 
251 /*
252  * PTE calls.
253  */
254 static int		moea_pte_insert(u_int, struct pte *);
255 
256 /*
257  * PVO calls.
258  */
259 static int	moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
260 		    vm_offset_t, vm_offset_t, u_int, int);
261 static void	moea_pvo_remove(struct pvo_entry *, int);
262 static struct	pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
263 static struct	pte *moea_pvo_to_pte(const struct pvo_entry *, int);
264 
265 /*
266  * Utility routines.
267  */
268 static void		moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
269 			    vm_prot_t, boolean_t);
270 static void		moea_syncicache(vm_offset_t, vm_size_t);
271 static boolean_t	moea_query_bit(vm_page_t, int);
272 static u_int		moea_clear_bit(vm_page_t, int);
273 static void		moea_kremove(mmu_t, vm_offset_t);
274 int		moea_pte_spill(vm_offset_t);
275 
276 /*
277  * Kernel MMU interface
278  */
279 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
280 void moea_clear_modify(mmu_t, vm_page_t);
281 void moea_clear_reference(mmu_t, vm_page_t);
282 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
283 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
284     vm_page_t *mb, vm_offset_t b_offset, int xfersize);
285 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
286 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
287     vm_prot_t);
288 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
289 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
290 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
291 void moea_init(mmu_t);
292 boolean_t moea_is_modified(mmu_t, vm_page_t);
293 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
294 boolean_t moea_is_referenced(mmu_t, vm_page_t);
295 int moea_ts_referenced(mmu_t, vm_page_t);
296 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
297 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
298 int moea_page_wired_mappings(mmu_t, vm_page_t);
299 void moea_pinit(mmu_t, pmap_t);
300 void moea_pinit0(mmu_t, pmap_t);
301 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
302 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
303 void moea_qremove(mmu_t, vm_offset_t, int);
304 void moea_release(mmu_t, pmap_t);
305 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
306 void moea_remove_all(mmu_t, vm_page_t);
307 void moea_remove_write(mmu_t, vm_page_t);
308 void moea_zero_page(mmu_t, vm_page_t);
309 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
310 void moea_zero_page_idle(mmu_t, vm_page_t);
311 void moea_activate(mmu_t, struct thread *);
312 void moea_deactivate(mmu_t, struct thread *);
313 void moea_cpu_bootstrap(mmu_t, int);
314 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
315 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
316 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
317 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
318 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
319 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
320 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
321 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
322 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
323 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
324 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
325     vm_size_t *sz);
326 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev);
327 
328 static mmu_method_t moea_methods[] = {
329 	MMUMETHOD(mmu_change_wiring,	moea_change_wiring),
330 	MMUMETHOD(mmu_clear_modify,	moea_clear_modify),
331 	MMUMETHOD(mmu_clear_reference,	moea_clear_reference),
332 	MMUMETHOD(mmu_copy_page,	moea_copy_page),
333 	MMUMETHOD(mmu_copy_pages,	moea_copy_pages),
334 	MMUMETHOD(mmu_enter,		moea_enter),
335 	MMUMETHOD(mmu_enter_object,	moea_enter_object),
336 	MMUMETHOD(mmu_enter_quick,	moea_enter_quick),
337 	MMUMETHOD(mmu_extract,		moea_extract),
338 	MMUMETHOD(mmu_extract_and_hold,	moea_extract_and_hold),
339 	MMUMETHOD(mmu_init,		moea_init),
340 	MMUMETHOD(mmu_is_modified,	moea_is_modified),
341 	MMUMETHOD(mmu_is_prefaultable,	moea_is_prefaultable),
342 	MMUMETHOD(mmu_is_referenced,	moea_is_referenced),
343 	MMUMETHOD(mmu_ts_referenced,	moea_ts_referenced),
344 	MMUMETHOD(mmu_map,     		moea_map),
345 	MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
346 	MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
347 	MMUMETHOD(mmu_pinit,		moea_pinit),
348 	MMUMETHOD(mmu_pinit0,		moea_pinit0),
349 	MMUMETHOD(mmu_protect,		moea_protect),
350 	MMUMETHOD(mmu_qenter,		moea_qenter),
351 	MMUMETHOD(mmu_qremove,		moea_qremove),
352 	MMUMETHOD(mmu_release,		moea_release),
353 	MMUMETHOD(mmu_remove,		moea_remove),
354 	MMUMETHOD(mmu_remove_all,      	moea_remove_all),
355 	MMUMETHOD(mmu_remove_write,	moea_remove_write),
356 	MMUMETHOD(mmu_sync_icache,	moea_sync_icache),
357 	MMUMETHOD(mmu_zero_page,       	moea_zero_page),
358 	MMUMETHOD(mmu_zero_page_area,	moea_zero_page_area),
359 	MMUMETHOD(mmu_zero_page_idle,	moea_zero_page_idle),
360 	MMUMETHOD(mmu_activate,		moea_activate),
361 	MMUMETHOD(mmu_deactivate,      	moea_deactivate),
362 	MMUMETHOD(mmu_page_set_memattr,	moea_page_set_memattr),
363 
364 	/* Internal interfaces */
365 	MMUMETHOD(mmu_bootstrap,       	moea_bootstrap),
366 	MMUMETHOD(mmu_cpu_bootstrap,   	moea_cpu_bootstrap),
367 	MMUMETHOD(mmu_mapdev_attr,	moea_mapdev_attr),
368 	MMUMETHOD(mmu_mapdev,		moea_mapdev),
369 	MMUMETHOD(mmu_unmapdev,		moea_unmapdev),
370 	MMUMETHOD(mmu_kextract,		moea_kextract),
371 	MMUMETHOD(mmu_kenter,		moea_kenter),
372 	MMUMETHOD(mmu_kenter_attr,	moea_kenter_attr),
373 	MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
374 	MMUMETHOD(mmu_scan_md,		moea_scan_md),
375 	MMUMETHOD(mmu_dumpsys_map,	moea_dumpsys_map),
376 
377 	{ 0, 0 }
378 };
379 
380 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
381 
382 static __inline uint32_t
383 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
384 {
385 	uint32_t pte_lo;
386 	int i;
387 
388 	if (ma != VM_MEMATTR_DEFAULT) {
389 		switch (ma) {
390 		case VM_MEMATTR_UNCACHEABLE:
391 			return (PTE_I | PTE_G);
392 		case VM_MEMATTR_WRITE_COMBINING:
393 		case VM_MEMATTR_WRITE_BACK:
394 		case VM_MEMATTR_PREFETCHABLE:
395 			return (PTE_I);
396 		case VM_MEMATTR_WRITE_THROUGH:
397 			return (PTE_W | PTE_M);
398 		}
399 	}
400 
401 	/*
402 	 * Assume the page is cache inhibited and access is guarded unless
403 	 * it's in our available memory array.
404 	 */
405 	pte_lo = PTE_I | PTE_G;
406 	for (i = 0; i < pregions_sz; i++) {
407 		if ((pa >= pregions[i].mr_start) &&
408 		    (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
409 			pte_lo = PTE_M;
410 			break;
411 		}
412 	}
413 
414 	return pte_lo;
415 }
416 
417 static void
418 tlbie(vm_offset_t va)
419 {
420 
421 	mtx_lock_spin(&tlbie_mtx);
422 	__asm __volatile("ptesync");
423 	__asm __volatile("tlbie %0" :: "r"(va));
424 	__asm __volatile("eieio; tlbsync; ptesync");
425 	mtx_unlock_spin(&tlbie_mtx);
426 }
427 
428 static void
429 tlbia(void)
430 {
431 	vm_offset_t va;
432 
433 	for (va = 0; va < 0x00040000; va += 0x00001000) {
434 		__asm __volatile("tlbie %0" :: "r"(va));
435 		powerpc_sync();
436 	}
437 	__asm __volatile("tlbsync");
438 	powerpc_sync();
439 }
440 
441 static __inline int
442 va_to_sr(u_int *sr, vm_offset_t va)
443 {
444 	return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
445 }
446 
447 static __inline u_int
448 va_to_pteg(u_int sr, vm_offset_t addr)
449 {
450 	u_int hash;
451 
452 	hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
453 	    ADDR_PIDX_SHFT);
454 	return (hash & moea_pteg_mask);
455 }
456 
457 static __inline struct pvo_head *
458 vm_page_to_pvoh(vm_page_t m)
459 {
460 
461 	return (&m->md.mdpg_pvoh);
462 }
463 
464 static __inline void
465 moea_attr_clear(vm_page_t m, int ptebit)
466 {
467 
468 	rw_assert(&pvh_global_lock, RA_WLOCKED);
469 	m->md.mdpg_attrs &= ~ptebit;
470 }
471 
472 static __inline int
473 moea_attr_fetch(vm_page_t m)
474 {
475 
476 	return (m->md.mdpg_attrs);
477 }
478 
479 static __inline void
480 moea_attr_save(vm_page_t m, int ptebit)
481 {
482 
483 	rw_assert(&pvh_global_lock, RA_WLOCKED);
484 	m->md.mdpg_attrs |= ptebit;
485 }
486 
487 static __inline int
488 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
489 {
490 	if (pt->pte_hi == pvo_pt->pte_hi)
491 		return (1);
492 
493 	return (0);
494 }
495 
496 static __inline int
497 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
498 {
499 	return (pt->pte_hi & ~PTE_VALID) ==
500 	    (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
501 	    ((va >> ADDR_API_SHFT) & PTE_API) | which);
502 }
503 
504 static __inline void
505 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
506 {
507 
508 	mtx_assert(&moea_table_mutex, MA_OWNED);
509 
510 	/*
511 	 * Construct a PTE.  Default to IMB initially.  Valid bit only gets
512 	 * set when the real pte is set in memory.
513 	 *
514 	 * Note: Don't set the valid bit for correct operation of tlb update.
515 	 */
516 	pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
517 	    (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
518 	pt->pte_lo = pte_lo;
519 }
520 
521 static __inline void
522 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
523 {
524 
525 	mtx_assert(&moea_table_mutex, MA_OWNED);
526 	pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
527 }
528 
529 static __inline void
530 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
531 {
532 
533 	mtx_assert(&moea_table_mutex, MA_OWNED);
534 
535 	/*
536 	 * As shown in Section 7.6.3.2.3
537 	 */
538 	pt->pte_lo &= ~ptebit;
539 	tlbie(va);
540 }
541 
542 static __inline void
543 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
544 {
545 
546 	mtx_assert(&moea_table_mutex, MA_OWNED);
547 	pvo_pt->pte_hi |= PTE_VALID;
548 
549 	/*
550 	 * Update the PTE as defined in section 7.6.3.1.
551 	 * Note that the REF/CHG bits are from pvo_pt and thus should havce
552 	 * been saved so this routine can restore them (if desired).
553 	 */
554 	pt->pte_lo = pvo_pt->pte_lo;
555 	powerpc_sync();
556 	pt->pte_hi = pvo_pt->pte_hi;
557 	powerpc_sync();
558 	moea_pte_valid++;
559 }
560 
561 static __inline void
562 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
563 {
564 
565 	mtx_assert(&moea_table_mutex, MA_OWNED);
566 	pvo_pt->pte_hi &= ~PTE_VALID;
567 
568 	/*
569 	 * Force the reg & chg bits back into the PTEs.
570 	 */
571 	powerpc_sync();
572 
573 	/*
574 	 * Invalidate the pte.
575 	 */
576 	pt->pte_hi &= ~PTE_VALID;
577 
578 	tlbie(va);
579 
580 	/*
581 	 * Save the reg & chg bits.
582 	 */
583 	moea_pte_synch(pt, pvo_pt);
584 	moea_pte_valid--;
585 }
586 
587 static __inline void
588 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
589 {
590 
591 	/*
592 	 * Invalidate the PTE
593 	 */
594 	moea_pte_unset(pt, pvo_pt, va);
595 	moea_pte_set(pt, pvo_pt);
596 }
597 
598 /*
599  * Quick sort callout for comparing memory regions.
600  */
601 static int	om_cmp(const void *a, const void *b);
602 
603 static int
604 om_cmp(const void *a, const void *b)
605 {
606 	const struct	ofw_map *mapa;
607 	const struct	ofw_map *mapb;
608 
609 	mapa = a;
610 	mapb = b;
611 	if (mapa->om_pa < mapb->om_pa)
612 		return (-1);
613 	else if (mapa->om_pa > mapb->om_pa)
614 		return (1);
615 	else
616 		return (0);
617 }
618 
619 void
620 moea_cpu_bootstrap(mmu_t mmup, int ap)
621 {
622 	u_int sdr;
623 	int i;
624 
625 	if (ap) {
626 		powerpc_sync();
627 		__asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
628 		__asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
629 		isync();
630 		__asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
631 		__asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
632 		isync();
633 	}
634 
635 #ifdef WII
636 	/*
637 	 * Special case for the Wii: don't install the PCI BAT.
638 	 */
639 	if (strcmp(installed_platform(), "wii") != 0) {
640 #endif
641 		__asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
642 		__asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
643 #ifdef WII
644 	}
645 #endif
646 	isync();
647 
648 	__asm __volatile("mtibatu 1,%0" :: "r"(0));
649 	__asm __volatile("mtdbatu 2,%0" :: "r"(0));
650 	__asm __volatile("mtibatu 2,%0" :: "r"(0));
651 	__asm __volatile("mtdbatu 3,%0" :: "r"(0));
652 	__asm __volatile("mtibatu 3,%0" :: "r"(0));
653 	isync();
654 
655 	for (i = 0; i < 16; i++)
656 		mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
657 	powerpc_sync();
658 
659 	sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
660 	__asm __volatile("mtsdr1 %0" :: "r"(sdr));
661 	isync();
662 
663 	tlbia();
664 }
665 
666 void
667 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
668 {
669 	ihandle_t	mmui;
670 	phandle_t	chosen, mmu;
671 	int		sz;
672 	int		i, j;
673 	vm_size_t	size, physsz, hwphyssz;
674 	vm_offset_t	pa, va, off;
675 	void		*dpcpu;
676 	register_t	msr;
677 
678         /*
679          * Set up BAT0 to map the lowest 256 MB area
680          */
681         battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
682         battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
683 
684 	/*
685 	 * Map PCI memory space.
686 	 */
687 	battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
688 	battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
689 
690 	battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
691 	battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
692 
693 	battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
694 	battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
695 
696 	battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
697 	battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
698 
699 	/*
700 	 * Map obio devices.
701 	 */
702 	battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
703 	battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
704 
705 	/*
706 	 * Use an IBAT and a DBAT to map the bottom segment of memory
707 	 * where we are. Turn off instruction relocation temporarily
708 	 * to prevent faults while reprogramming the IBAT.
709 	 */
710 	msr = mfmsr();
711 	mtmsr(msr & ~PSL_IR);
712 	__asm (".balign 32; \n"
713 	       "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
714 	       "mtdbatu 0,%0; mtdbatl 0,%1; isync"
715 	    :: "r"(battable[0].batu), "r"(battable[0].batl));
716 	mtmsr(msr);
717 
718 #ifdef WII
719         if (strcmp(installed_platform(), "wii") != 0) {
720 #endif
721 		/* map pci space */
722 		__asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
723 		__asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
724 #ifdef WII
725 	}
726 #endif
727 	isync();
728 
729 	/* set global direct map flag */
730 	hw_direct_map = 1;
731 
732 	mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
733 	CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
734 
735 	for (i = 0; i < pregions_sz; i++) {
736 		vm_offset_t pa;
737 		vm_offset_t end;
738 
739 		CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
740 			pregions[i].mr_start,
741 			pregions[i].mr_start + pregions[i].mr_size,
742 			pregions[i].mr_size);
743 		/*
744 		 * Install entries into the BAT table to allow all
745 		 * of physmem to be convered by on-demand BAT entries.
746 		 * The loop will sometimes set the same battable element
747 		 * twice, but that's fine since they won't be used for
748 		 * a while yet.
749 		 */
750 		pa = pregions[i].mr_start & 0xf0000000;
751 		end = pregions[i].mr_start + pregions[i].mr_size;
752 		do {
753                         u_int n = pa >> ADDR_SR_SHFT;
754 
755 			battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
756 			battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
757 			pa += SEGMENT_LENGTH;
758 		} while (pa < end);
759 	}
760 
761 	if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
762 		panic("moea_bootstrap: phys_avail too small");
763 
764 	phys_avail_count = 0;
765 	physsz = 0;
766 	hwphyssz = 0;
767 	TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
768 	for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
769 		CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
770 		    regions[i].mr_start + regions[i].mr_size,
771 		    regions[i].mr_size);
772 		if (hwphyssz != 0 &&
773 		    (physsz + regions[i].mr_size) >= hwphyssz) {
774 			if (physsz < hwphyssz) {
775 				phys_avail[j] = regions[i].mr_start;
776 				phys_avail[j + 1] = regions[i].mr_start +
777 				    hwphyssz - physsz;
778 				physsz = hwphyssz;
779 				phys_avail_count++;
780 			}
781 			break;
782 		}
783 		phys_avail[j] = regions[i].mr_start;
784 		phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
785 		phys_avail_count++;
786 		physsz += regions[i].mr_size;
787 	}
788 
789 	/* Check for overlap with the kernel and exception vectors */
790 	for (j = 0; j < 2*phys_avail_count; j+=2) {
791 		if (phys_avail[j] < EXC_LAST)
792 			phys_avail[j] += EXC_LAST;
793 
794 		if (kernelstart >= phys_avail[j] &&
795 		    kernelstart < phys_avail[j+1]) {
796 			if (kernelend < phys_avail[j+1]) {
797 				phys_avail[2*phys_avail_count] =
798 				    (kernelend & ~PAGE_MASK) + PAGE_SIZE;
799 				phys_avail[2*phys_avail_count + 1] =
800 				    phys_avail[j+1];
801 				phys_avail_count++;
802 			}
803 
804 			phys_avail[j+1] = kernelstart & ~PAGE_MASK;
805 		}
806 
807 		if (kernelend >= phys_avail[j] &&
808 		    kernelend < phys_avail[j+1]) {
809 			if (kernelstart > phys_avail[j]) {
810 				phys_avail[2*phys_avail_count] = phys_avail[j];
811 				phys_avail[2*phys_avail_count + 1] =
812 				    kernelstart & ~PAGE_MASK;
813 				phys_avail_count++;
814 			}
815 
816 			phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
817 		}
818 	}
819 
820 	physmem = btoc(physsz);
821 
822 	/*
823 	 * Allocate PTEG table.
824 	 */
825 #ifdef PTEGCOUNT
826 	moea_pteg_count = PTEGCOUNT;
827 #else
828 	moea_pteg_count = 0x1000;
829 
830 	while (moea_pteg_count < physmem)
831 		moea_pteg_count <<= 1;
832 
833 	moea_pteg_count >>= 1;
834 #endif /* PTEGCOUNT */
835 
836 	size = moea_pteg_count * sizeof(struct pteg);
837 	CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
838 	    size);
839 	moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
840 	CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
841 	bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
842 	moea_pteg_mask = moea_pteg_count - 1;
843 
844 	/*
845 	 * Allocate pv/overflow lists.
846 	 */
847 	size = sizeof(struct pvo_head) * moea_pteg_count;
848 	moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
849 	    PAGE_SIZE);
850 	CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
851 	for (i = 0; i < moea_pteg_count; i++)
852 		LIST_INIT(&moea_pvo_table[i]);
853 
854 	/*
855 	 * Initialize the lock that synchronizes access to the pteg and pvo
856 	 * tables.
857 	 */
858 	mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
859 	    MTX_RECURSE);
860 	mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
861 
862 	mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
863 
864 	/*
865 	 * Initialise the unmanaged pvo pool.
866 	 */
867 	moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
868 		BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
869 	moea_bpvo_pool_index = 0;
870 
871 	/*
872 	 * Make sure kernel vsid is allocated as well as VSID 0.
873 	 */
874 	moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
875 		|= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
876 	moea_vsid_bitmap[0] |= 1;
877 
878 	/*
879 	 * Initialize the kernel pmap (which is statically allocated).
880 	 */
881 	PMAP_LOCK_INIT(kernel_pmap);
882 	for (i = 0; i < 16; i++)
883 		kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
884 	CPU_FILL(&kernel_pmap->pm_active);
885 	RB_INIT(&kernel_pmap->pmap_pvo);
886 
887  	/*
888 	 * Initialize the global pv list lock.
889 	 */
890 	rw_init(&pvh_global_lock, "pmap pv global");
891 
892 	/*
893 	 * Set up the Open Firmware mappings
894 	 */
895 	chosen = OF_finddevice("/chosen");
896 	if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
897 	    (mmu = OF_instance_to_package(mmui)) != -1 &&
898 	    (sz = OF_getproplen(mmu, "translations")) != -1) {
899 		translations = NULL;
900 		for (i = 0; phys_avail[i] != 0; i += 2) {
901 			if (phys_avail[i + 1] >= sz) {
902 				translations = (struct ofw_map *)phys_avail[i];
903 				break;
904 			}
905 		}
906 		if (translations == NULL)
907 			panic("moea_bootstrap: no space to copy translations");
908 		bzero(translations, sz);
909 		if (OF_getprop(mmu, "translations", translations, sz) == -1)
910 			panic("moea_bootstrap: can't get ofw translations");
911 		CTR0(KTR_PMAP, "moea_bootstrap: translations");
912 		sz /= sizeof(*translations);
913 		qsort(translations, sz, sizeof (*translations), om_cmp);
914 		for (i = 0; i < sz; i++) {
915 			CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
916 			    translations[i].om_pa, translations[i].om_va,
917 			    translations[i].om_len);
918 
919 			/*
920 			 * If the mapping is 1:1, let the RAM and device
921 			 * on-demand BAT tables take care of the translation.
922 			 */
923 			if (translations[i].om_va == translations[i].om_pa)
924 				continue;
925 
926 			/* Enter the pages */
927 			for (off = 0; off < translations[i].om_len;
928 			    off += PAGE_SIZE)
929 				moea_kenter(mmup, translations[i].om_va + off,
930 					    translations[i].om_pa + off);
931 		}
932 	}
933 
934 	/*
935 	 * Calculate the last available physical address.
936 	 */
937 	for (i = 0; phys_avail[i + 2] != 0; i += 2)
938 		;
939 	Maxmem = powerpc_btop(phys_avail[i + 1]);
940 
941 	moea_cpu_bootstrap(mmup,0);
942 
943 	pmap_bootstrapped++;
944 
945 	/*
946 	 * Set the start and end of kva.
947 	 */
948 	virtual_avail = VM_MIN_KERNEL_ADDRESS;
949 	virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
950 
951 	/*
952 	 * Allocate a kernel stack with a guard page for thread0 and map it
953 	 * into the kernel page map.
954 	 */
955 	pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
956 	va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
957 	virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
958 	CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
959 	thread0.td_kstack = va;
960 	thread0.td_kstack_pages = KSTACK_PAGES;
961 	for (i = 0; i < KSTACK_PAGES; i++) {
962 		moea_kenter(mmup, va, pa);
963 		pa += PAGE_SIZE;
964 		va += PAGE_SIZE;
965 	}
966 
967 	/*
968 	 * Allocate virtual address space for the message buffer.
969 	 */
970 	pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
971 	msgbufp = (struct msgbuf *)virtual_avail;
972 	va = virtual_avail;
973 	virtual_avail += round_page(msgbufsize);
974 	while (va < virtual_avail) {
975 		moea_kenter(mmup, va, pa);
976 		pa += PAGE_SIZE;
977 		va += PAGE_SIZE;
978 	}
979 
980 	/*
981 	 * Allocate virtual address space for the dynamic percpu area.
982 	 */
983 	pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
984 	dpcpu = (void *)virtual_avail;
985 	va = virtual_avail;
986 	virtual_avail += DPCPU_SIZE;
987 	while (va < virtual_avail) {
988 		moea_kenter(mmup, va, pa);
989 		pa += PAGE_SIZE;
990 		va += PAGE_SIZE;
991 	}
992 	dpcpu_init(dpcpu, 0);
993 }
994 
995 /*
996  * Activate a user pmap.  The pmap must be activated before it's address
997  * space can be accessed in any way.
998  */
999 void
1000 moea_activate(mmu_t mmu, struct thread *td)
1001 {
1002 	pmap_t	pm, pmr;
1003 
1004 	/*
1005 	 * Load all the data we need up front to encourage the compiler to
1006 	 * not issue any loads while we have interrupts disabled below.
1007 	 */
1008 	pm = &td->td_proc->p_vmspace->vm_pmap;
1009 	pmr = pm->pmap_phys;
1010 
1011 	CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1012 	PCPU_SET(curpmap, pmr);
1013 }
1014 
1015 void
1016 moea_deactivate(mmu_t mmu, struct thread *td)
1017 {
1018 	pmap_t	pm;
1019 
1020 	pm = &td->td_proc->p_vmspace->vm_pmap;
1021 	CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1022 	PCPU_SET(curpmap, NULL);
1023 }
1024 
1025 void
1026 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1027 {
1028 	struct	pvo_entry *pvo;
1029 
1030 	PMAP_LOCK(pm);
1031 	pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1032 
1033 	if (pvo != NULL) {
1034 		if (wired) {
1035 			if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1036 				pm->pm_stats.wired_count++;
1037 			pvo->pvo_vaddr |= PVO_WIRED;
1038 		} else {
1039 			if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1040 				pm->pm_stats.wired_count--;
1041 			pvo->pvo_vaddr &= ~PVO_WIRED;
1042 		}
1043 	}
1044 	PMAP_UNLOCK(pm);
1045 }
1046 
1047 void
1048 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1049 {
1050 	vm_offset_t	dst;
1051 	vm_offset_t	src;
1052 
1053 	dst = VM_PAGE_TO_PHYS(mdst);
1054 	src = VM_PAGE_TO_PHYS(msrc);
1055 
1056 	bcopy((void *)src, (void *)dst, PAGE_SIZE);
1057 }
1058 
1059 void
1060 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1061     vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1062 {
1063 	void *a_cp, *b_cp;
1064 	vm_offset_t a_pg_offset, b_pg_offset;
1065 	int cnt;
1066 
1067 	while (xfersize > 0) {
1068 		a_pg_offset = a_offset & PAGE_MASK;
1069 		cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1070 		a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1071 		    a_pg_offset;
1072 		b_pg_offset = b_offset & PAGE_MASK;
1073 		cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1074 		b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1075 		    b_pg_offset;
1076 		bcopy(a_cp, b_cp, cnt);
1077 		a_offset += cnt;
1078 		b_offset += cnt;
1079 		xfersize -= cnt;
1080 	}
1081 }
1082 
1083 /*
1084  * Zero a page of physical memory by temporarily mapping it into the tlb.
1085  */
1086 void
1087 moea_zero_page(mmu_t mmu, vm_page_t m)
1088 {
1089 	vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1090 	void *va = (void *)pa;
1091 
1092 	bzero(va, PAGE_SIZE);
1093 }
1094 
1095 void
1096 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1097 {
1098 	vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1099 	void *va = (void *)(pa + off);
1100 
1101 	bzero(va, size);
1102 }
1103 
1104 void
1105 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1106 {
1107 	vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1108 	void *va = (void *)pa;
1109 
1110 	bzero(va, PAGE_SIZE);
1111 }
1112 
1113 /*
1114  * Map the given physical page at the specified virtual address in the
1115  * target pmap with the protection requested.  If specified the page
1116  * will be wired down.
1117  */
1118 void
1119 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1120 	   boolean_t wired)
1121 {
1122 
1123 	rw_wlock(&pvh_global_lock);
1124 	PMAP_LOCK(pmap);
1125 	moea_enter_locked(pmap, va, m, prot, wired);
1126 	rw_wunlock(&pvh_global_lock);
1127 	PMAP_UNLOCK(pmap);
1128 }
1129 
1130 /*
1131  * Map the given physical page at the specified virtual address in the
1132  * target pmap with the protection requested.  If specified the page
1133  * will be wired down.
1134  *
1135  * The page queues and pmap must be locked.
1136  */
1137 static void
1138 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1139     boolean_t wired)
1140 {
1141 	struct		pvo_head *pvo_head;
1142 	uma_zone_t	zone;
1143 	vm_page_t	pg;
1144 	u_int		pte_lo, pvo_flags;
1145 	int		error;
1146 
1147 	if (!moea_initialized) {
1148 		pvo_head = &moea_pvo_kunmanaged;
1149 		zone = moea_upvo_zone;
1150 		pvo_flags = 0;
1151 		pg = NULL;
1152 	} else {
1153 		pvo_head = vm_page_to_pvoh(m);
1154 		pg = m;
1155 		zone = moea_mpvo_zone;
1156 		pvo_flags = PVO_MANAGED;
1157 	}
1158 	if (pmap_bootstrapped)
1159 		rw_assert(&pvh_global_lock, RA_WLOCKED);
1160 	PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1161 	if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0)
1162 		VM_OBJECT_ASSERT_LOCKED(m->object);
1163 
1164 	/* XXX change the pvo head for fake pages */
1165 	if ((m->oflags & VPO_UNMANAGED) != 0) {
1166 		pvo_flags &= ~PVO_MANAGED;
1167 		pvo_head = &moea_pvo_kunmanaged;
1168 		zone = moea_upvo_zone;
1169 	}
1170 
1171 	pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1172 
1173 	if (prot & VM_PROT_WRITE) {
1174 		pte_lo |= PTE_BW;
1175 		if (pmap_bootstrapped &&
1176 		    (m->oflags & VPO_UNMANAGED) == 0)
1177 			vm_page_aflag_set(m, PGA_WRITEABLE);
1178 	} else
1179 		pte_lo |= PTE_BR;
1180 
1181 	if (prot & VM_PROT_EXECUTE)
1182 		pvo_flags |= PVO_EXECUTABLE;
1183 
1184 	if (wired)
1185 		pvo_flags |= PVO_WIRED;
1186 
1187 	error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1188 	    pte_lo, pvo_flags);
1189 
1190 	/*
1191 	 * Flush the real page from the instruction cache. This has be done
1192 	 * for all user mappings to prevent information leakage via the
1193 	 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1194 	 * mapping for a page.
1195 	 */
1196 	if (pmap != kernel_pmap && error == ENOENT &&
1197 	    (pte_lo & (PTE_I | PTE_G)) == 0)
1198 		moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1199 }
1200 
1201 /*
1202  * Maps a sequence of resident pages belonging to the same object.
1203  * The sequence begins with the given page m_start.  This page is
1204  * mapped at the given virtual address start.  Each subsequent page is
1205  * mapped at a virtual address that is offset from start by the same
1206  * amount as the page is offset from m_start within the object.  The
1207  * last page in the sequence is the page with the largest offset from
1208  * m_start that can be mapped at a virtual address less than the given
1209  * virtual address end.  Not every virtual page between start and end
1210  * is mapped; only those for which a resident page exists with the
1211  * corresponding offset from m_start are mapped.
1212  */
1213 void
1214 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1215     vm_page_t m_start, vm_prot_t prot)
1216 {
1217 	vm_page_t m;
1218 	vm_pindex_t diff, psize;
1219 
1220 	VM_OBJECT_ASSERT_LOCKED(m_start->object);
1221 
1222 	psize = atop(end - start);
1223 	m = m_start;
1224 	rw_wlock(&pvh_global_lock);
1225 	PMAP_LOCK(pm);
1226 	while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1227 		moea_enter_locked(pm, start + ptoa(diff), m, prot &
1228 		    (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1229 		m = TAILQ_NEXT(m, listq);
1230 	}
1231 	rw_wunlock(&pvh_global_lock);
1232 	PMAP_UNLOCK(pm);
1233 }
1234 
1235 void
1236 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1237     vm_prot_t prot)
1238 {
1239 
1240 	rw_wlock(&pvh_global_lock);
1241 	PMAP_LOCK(pm);
1242 	moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1243 	    FALSE);
1244 	rw_wunlock(&pvh_global_lock);
1245 	PMAP_UNLOCK(pm);
1246 }
1247 
1248 vm_paddr_t
1249 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1250 {
1251 	struct	pvo_entry *pvo;
1252 	vm_paddr_t pa;
1253 
1254 	PMAP_LOCK(pm);
1255 	pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1256 	if (pvo == NULL)
1257 		pa = 0;
1258 	else
1259 		pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1260 	PMAP_UNLOCK(pm);
1261 	return (pa);
1262 }
1263 
1264 /*
1265  * Atomically extract and hold the physical page with the given
1266  * pmap and virtual address pair if that mapping permits the given
1267  * protection.
1268  */
1269 vm_page_t
1270 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1271 {
1272 	struct	pvo_entry *pvo;
1273 	vm_page_t m;
1274         vm_paddr_t pa;
1275 
1276 	m = NULL;
1277 	pa = 0;
1278 	PMAP_LOCK(pmap);
1279 retry:
1280 	pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1281 	if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1282 	    ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1283 	     (prot & VM_PROT_WRITE) == 0)) {
1284 		if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1285 			goto retry;
1286 		m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1287 		vm_page_hold(m);
1288 	}
1289 	PA_UNLOCK_COND(pa);
1290 	PMAP_UNLOCK(pmap);
1291 	return (m);
1292 }
1293 
1294 void
1295 moea_init(mmu_t mmu)
1296 {
1297 
1298 	moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1299 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1300 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1301 	moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1302 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1303 	    UMA_ZONE_VM | UMA_ZONE_NOFREE);
1304 	moea_initialized = TRUE;
1305 }
1306 
1307 boolean_t
1308 moea_is_referenced(mmu_t mmu, vm_page_t m)
1309 {
1310 	boolean_t rv;
1311 
1312 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1313 	    ("moea_is_referenced: page %p is not managed", m));
1314 	rw_wlock(&pvh_global_lock);
1315 	rv = moea_query_bit(m, PTE_REF);
1316 	rw_wunlock(&pvh_global_lock);
1317 	return (rv);
1318 }
1319 
1320 boolean_t
1321 moea_is_modified(mmu_t mmu, vm_page_t m)
1322 {
1323 	boolean_t rv;
1324 
1325 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1326 	    ("moea_is_modified: page %p is not managed", m));
1327 
1328 	/*
1329 	 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1330 	 * concurrently set while the object is locked.  Thus, if PGA_WRITEABLE
1331 	 * is clear, no PTEs can have PTE_CHG set.
1332 	 */
1333 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1334 	if ((m->oflags & VPO_BUSY) == 0 &&
1335 	    (m->aflags & PGA_WRITEABLE) == 0)
1336 		return (FALSE);
1337 	rw_wlock(&pvh_global_lock);
1338 	rv = moea_query_bit(m, PTE_CHG);
1339 	rw_wunlock(&pvh_global_lock);
1340 	return (rv);
1341 }
1342 
1343 boolean_t
1344 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1345 {
1346 	struct pvo_entry *pvo;
1347 	boolean_t rv;
1348 
1349 	PMAP_LOCK(pmap);
1350 	pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1351 	rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1352 	PMAP_UNLOCK(pmap);
1353 	return (rv);
1354 }
1355 
1356 void
1357 moea_clear_reference(mmu_t mmu, vm_page_t m)
1358 {
1359 
1360 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1361 	    ("moea_clear_reference: page %p is not managed", m));
1362 	rw_wlock(&pvh_global_lock);
1363 	moea_clear_bit(m, PTE_REF);
1364 	rw_wunlock(&pvh_global_lock);
1365 }
1366 
1367 void
1368 moea_clear_modify(mmu_t mmu, vm_page_t m)
1369 {
1370 
1371 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1372 	    ("moea_clear_modify: page %p is not managed", m));
1373 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1374 	KASSERT((m->oflags & VPO_BUSY) == 0,
1375 	    ("moea_clear_modify: page %p is busy", m));
1376 
1377 	/*
1378 	 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1379 	 * set.  If the object containing the page is locked and the page is
1380 	 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1381 	 */
1382 	if ((m->aflags & PGA_WRITEABLE) == 0)
1383 		return;
1384 	rw_wlock(&pvh_global_lock);
1385 	moea_clear_bit(m, PTE_CHG);
1386 	rw_wunlock(&pvh_global_lock);
1387 }
1388 
1389 /*
1390  * Clear the write and modified bits in each of the given page's mappings.
1391  */
1392 void
1393 moea_remove_write(mmu_t mmu, vm_page_t m)
1394 {
1395 	struct	pvo_entry *pvo;
1396 	struct	pte *pt;
1397 	pmap_t	pmap;
1398 	u_int	lo;
1399 
1400 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1401 	    ("moea_remove_write: page %p is not managed", m));
1402 
1403 	/*
1404 	 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1405 	 * another thread while the object is locked.  Thus, if PGA_WRITEABLE
1406 	 * is clear, no page table entries need updating.
1407 	 */
1408 	VM_OBJECT_ASSERT_WLOCKED(m->object);
1409 	if ((m->oflags & VPO_BUSY) == 0 &&
1410 	    (m->aflags & PGA_WRITEABLE) == 0)
1411 		return;
1412 	rw_wlock(&pvh_global_lock);
1413 	lo = moea_attr_fetch(m);
1414 	powerpc_sync();
1415 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1416 		pmap = pvo->pvo_pmap;
1417 		PMAP_LOCK(pmap);
1418 		if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1419 			pt = moea_pvo_to_pte(pvo, -1);
1420 			pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1421 			pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1422 			if (pt != NULL) {
1423 				moea_pte_synch(pt, &pvo->pvo_pte.pte);
1424 				lo |= pvo->pvo_pte.pte.pte_lo;
1425 				pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1426 				moea_pte_change(pt, &pvo->pvo_pte.pte,
1427 				    pvo->pvo_vaddr);
1428 				mtx_unlock(&moea_table_mutex);
1429 			}
1430 		}
1431 		PMAP_UNLOCK(pmap);
1432 	}
1433 	if ((lo & PTE_CHG) != 0) {
1434 		moea_attr_clear(m, PTE_CHG);
1435 		vm_page_dirty(m);
1436 	}
1437 	vm_page_aflag_clear(m, PGA_WRITEABLE);
1438 	rw_wunlock(&pvh_global_lock);
1439 }
1440 
1441 /*
1442  *	moea_ts_referenced:
1443  *
1444  *	Return a count of reference bits for a page, clearing those bits.
1445  *	It is not necessary for every reference bit to be cleared, but it
1446  *	is necessary that 0 only be returned when there are truly no
1447  *	reference bits set.
1448  *
1449  *	XXX: The exact number of bits to check and clear is a matter that
1450  *	should be tested and standardized at some point in the future for
1451  *	optimal aging of shared pages.
1452  */
1453 int
1454 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1455 {
1456 	int count;
1457 
1458 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1459 	    ("moea_ts_referenced: page %p is not managed", m));
1460 	rw_wlock(&pvh_global_lock);
1461 	count = moea_clear_bit(m, PTE_REF);
1462 	rw_wunlock(&pvh_global_lock);
1463 	return (count);
1464 }
1465 
1466 /*
1467  * Modify the WIMG settings of all mappings for a page.
1468  */
1469 void
1470 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1471 {
1472 	struct	pvo_entry *pvo;
1473 	struct	pvo_head *pvo_head;
1474 	struct	pte *pt;
1475 	pmap_t	pmap;
1476 	u_int	lo;
1477 
1478 	if ((m->oflags & VPO_UNMANAGED) != 0) {
1479 		m->md.mdpg_cache_attrs = ma;
1480 		return;
1481 	}
1482 
1483 	rw_wlock(&pvh_global_lock);
1484 	pvo_head = vm_page_to_pvoh(m);
1485 	lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1486 
1487 	LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1488 		pmap = pvo->pvo_pmap;
1489 		PMAP_LOCK(pmap);
1490 		pt = moea_pvo_to_pte(pvo, -1);
1491 		pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1492 		pvo->pvo_pte.pte.pte_lo |= lo;
1493 		if (pt != NULL) {
1494 			moea_pte_change(pt, &pvo->pvo_pte.pte,
1495 			    pvo->pvo_vaddr);
1496 			if (pvo->pvo_pmap == kernel_pmap)
1497 				isync();
1498 		}
1499 		mtx_unlock(&moea_table_mutex);
1500 		PMAP_UNLOCK(pmap);
1501 	}
1502 	m->md.mdpg_cache_attrs = ma;
1503 	rw_wunlock(&pvh_global_lock);
1504 }
1505 
1506 /*
1507  * Map a wired page into kernel virtual address space.
1508  */
1509 void
1510 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1511 {
1512 
1513 	moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1514 }
1515 
1516 void
1517 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1518 {
1519 	u_int		pte_lo;
1520 	int		error;
1521 
1522 #if 0
1523 	if (va < VM_MIN_KERNEL_ADDRESS)
1524 		panic("moea_kenter: attempt to enter non-kernel address %#x",
1525 		    va);
1526 #endif
1527 
1528 	pte_lo = moea_calc_wimg(pa, ma);
1529 
1530 	PMAP_LOCK(kernel_pmap);
1531 	error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1532 	    &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1533 
1534 	if (error != 0 && error != ENOENT)
1535 		panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1536 		    pa, error);
1537 
1538 	PMAP_UNLOCK(kernel_pmap);
1539 }
1540 
1541 /*
1542  * Extract the physical page address associated with the given kernel virtual
1543  * address.
1544  */
1545 vm_paddr_t
1546 moea_kextract(mmu_t mmu, vm_offset_t va)
1547 {
1548 	struct		pvo_entry *pvo;
1549 	vm_paddr_t pa;
1550 
1551 	/*
1552 	 * Allow direct mappings on 32-bit OEA
1553 	 */
1554 	if (va < VM_MIN_KERNEL_ADDRESS) {
1555 		return (va);
1556 	}
1557 
1558 	PMAP_LOCK(kernel_pmap);
1559 	pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1560 	KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1561 	pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1562 	PMAP_UNLOCK(kernel_pmap);
1563 	return (pa);
1564 }
1565 
1566 /*
1567  * Remove a wired page from kernel virtual address space.
1568  */
1569 void
1570 moea_kremove(mmu_t mmu, vm_offset_t va)
1571 {
1572 
1573 	moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1574 }
1575 
1576 /*
1577  * Map a range of physical addresses into kernel virtual address space.
1578  *
1579  * The value passed in *virt is a suggested virtual address for the mapping.
1580  * Architectures which can support a direct-mapped physical to virtual region
1581  * can return the appropriate address within that region, leaving '*virt'
1582  * unchanged.  We cannot and therefore do not; *virt is updated with the
1583  * first usable address after the mapped region.
1584  */
1585 vm_offset_t
1586 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1587     vm_paddr_t pa_end, int prot)
1588 {
1589 	vm_offset_t	sva, va;
1590 
1591 	sva = *virt;
1592 	va = sva;
1593 	for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1594 		moea_kenter(mmu, va, pa_start);
1595 	*virt = va;
1596 	return (sva);
1597 }
1598 
1599 /*
1600  * Returns true if the pmap's pv is one of the first
1601  * 16 pvs linked to from this page.  This count may
1602  * be changed upwards or downwards in the future; it
1603  * is only necessary that true be returned for a small
1604  * subset of pmaps for proper page aging.
1605  */
1606 boolean_t
1607 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1608 {
1609         int loops;
1610 	struct pvo_entry *pvo;
1611 	boolean_t rv;
1612 
1613 	KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1614 	    ("moea_page_exists_quick: page %p is not managed", m));
1615 	loops = 0;
1616 	rv = FALSE;
1617 	rw_wlock(&pvh_global_lock);
1618 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1619 		if (pvo->pvo_pmap == pmap) {
1620 			rv = TRUE;
1621 			break;
1622 		}
1623 		if (++loops >= 16)
1624 			break;
1625 	}
1626 	rw_wunlock(&pvh_global_lock);
1627 	return (rv);
1628 }
1629 
1630 /*
1631  * Return the number of managed mappings to the given physical page
1632  * that are wired.
1633  */
1634 int
1635 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1636 {
1637 	struct pvo_entry *pvo;
1638 	int count;
1639 
1640 	count = 0;
1641 	if ((m->oflags & VPO_UNMANAGED) != 0)
1642 		return (count);
1643 	rw_wlock(&pvh_global_lock);
1644 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1645 		if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1646 			count++;
1647 	rw_wunlock(&pvh_global_lock);
1648 	return (count);
1649 }
1650 
1651 static u_int	moea_vsidcontext;
1652 
1653 void
1654 moea_pinit(mmu_t mmu, pmap_t pmap)
1655 {
1656 	int	i, mask;
1657 	u_int	entropy;
1658 
1659 	KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1660 	PMAP_LOCK_INIT(pmap);
1661 	RB_INIT(&pmap->pmap_pvo);
1662 
1663 	entropy = 0;
1664 	__asm __volatile("mftb %0" : "=r"(entropy));
1665 
1666 	if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1667 	    == NULL) {
1668 		pmap->pmap_phys = pmap;
1669 	}
1670 
1671 
1672 	mtx_lock(&moea_vsid_mutex);
1673 	/*
1674 	 * Allocate some segment registers for this pmap.
1675 	 */
1676 	for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1677 		u_int	hash, n;
1678 
1679 		/*
1680 		 * Create a new value by mutiplying by a prime and adding in
1681 		 * entropy from the timebase register.  This is to make the
1682 		 * VSID more random so that the PT hash function collides
1683 		 * less often.  (Note that the prime casues gcc to do shifts
1684 		 * instead of a multiply.)
1685 		 */
1686 		moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1687 		hash = moea_vsidcontext & (NPMAPS - 1);
1688 		if (hash == 0)		/* 0 is special, avoid it */
1689 			continue;
1690 		n = hash >> 5;
1691 		mask = 1 << (hash & (VSID_NBPW - 1));
1692 		hash = (moea_vsidcontext & 0xfffff);
1693 		if (moea_vsid_bitmap[n] & mask) {	/* collision? */
1694 			/* anything free in this bucket? */
1695 			if (moea_vsid_bitmap[n] == 0xffffffff) {
1696 				entropy = (moea_vsidcontext >> 20);
1697 				continue;
1698 			}
1699 			i = ffs(~moea_vsid_bitmap[n]) - 1;
1700 			mask = 1 << i;
1701 			hash &= 0xfffff & ~(VSID_NBPW - 1);
1702 			hash |= i;
1703 		}
1704 		KASSERT(!(moea_vsid_bitmap[n] & mask),
1705 		    ("Allocating in-use VSID group %#x\n", hash));
1706 		moea_vsid_bitmap[n] |= mask;
1707 		for (i = 0; i < 16; i++)
1708 			pmap->pm_sr[i] = VSID_MAKE(i, hash);
1709 		mtx_unlock(&moea_vsid_mutex);
1710 		return;
1711 	}
1712 
1713 	mtx_unlock(&moea_vsid_mutex);
1714 	panic("moea_pinit: out of segments");
1715 }
1716 
1717 /*
1718  * Initialize the pmap associated with process 0.
1719  */
1720 void
1721 moea_pinit0(mmu_t mmu, pmap_t pm)
1722 {
1723 
1724 	moea_pinit(mmu, pm);
1725 	bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1726 }
1727 
1728 /*
1729  * Set the physical protection on the specified range of this map as requested.
1730  */
1731 void
1732 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1733     vm_prot_t prot)
1734 {
1735 	struct	pvo_entry *pvo, *tpvo, key;
1736 	struct	pte *pt;
1737 
1738 	KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1739 	    ("moea_protect: non current pmap"));
1740 
1741 	if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1742 		moea_remove(mmu, pm, sva, eva);
1743 		return;
1744 	}
1745 
1746 	rw_wlock(&pvh_global_lock);
1747 	PMAP_LOCK(pm);
1748 	key.pvo_vaddr = sva;
1749 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1750 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1751 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1752 		if ((prot & VM_PROT_EXECUTE) == 0)
1753 			pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1754 
1755 		/*
1756 		 * Grab the PTE pointer before we diddle with the cached PTE
1757 		 * copy.
1758 		 */
1759 		pt = moea_pvo_to_pte(pvo, -1);
1760 		/*
1761 		 * Change the protection of the page.
1762 		 */
1763 		pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1764 		pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1765 
1766 		/*
1767 		 * If the PVO is in the page table, update that pte as well.
1768 		 */
1769 		if (pt != NULL) {
1770 			moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1771 			mtx_unlock(&moea_table_mutex);
1772 		}
1773 	}
1774 	rw_wunlock(&pvh_global_lock);
1775 	PMAP_UNLOCK(pm);
1776 }
1777 
1778 /*
1779  * Map a list of wired pages into kernel virtual address space.  This is
1780  * intended for temporary mappings which do not need page modification or
1781  * references recorded.  Existing mappings in the region are overwritten.
1782  */
1783 void
1784 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1785 {
1786 	vm_offset_t va;
1787 
1788 	va = sva;
1789 	while (count-- > 0) {
1790 		moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1791 		va += PAGE_SIZE;
1792 		m++;
1793 	}
1794 }
1795 
1796 /*
1797  * Remove page mappings from kernel virtual address space.  Intended for
1798  * temporary mappings entered by moea_qenter.
1799  */
1800 void
1801 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1802 {
1803 	vm_offset_t va;
1804 
1805 	va = sva;
1806 	while (count-- > 0) {
1807 		moea_kremove(mmu, va);
1808 		va += PAGE_SIZE;
1809 	}
1810 }
1811 
1812 void
1813 moea_release(mmu_t mmu, pmap_t pmap)
1814 {
1815         int idx, mask;
1816 
1817 	/*
1818 	 * Free segment register's VSID
1819 	 */
1820         if (pmap->pm_sr[0] == 0)
1821                 panic("moea_release");
1822 
1823 	mtx_lock(&moea_vsid_mutex);
1824         idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1825         mask = 1 << (idx % VSID_NBPW);
1826         idx /= VSID_NBPW;
1827         moea_vsid_bitmap[idx] &= ~mask;
1828 	mtx_unlock(&moea_vsid_mutex);
1829 	PMAP_LOCK_DESTROY(pmap);
1830 }
1831 
1832 /*
1833  * Remove the given range of addresses from the specified map.
1834  */
1835 void
1836 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1837 {
1838 	struct	pvo_entry *pvo, *tpvo, key;
1839 
1840 	rw_wlock(&pvh_global_lock);
1841 	PMAP_LOCK(pm);
1842 	key.pvo_vaddr = sva;
1843 	for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1844 	    pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1845 		tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1846 		moea_pvo_remove(pvo, -1);
1847 	}
1848 	PMAP_UNLOCK(pm);
1849 	rw_wunlock(&pvh_global_lock);
1850 }
1851 
1852 /*
1853  * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1854  * will reflect changes in pte's back to the vm_page.
1855  */
1856 void
1857 moea_remove_all(mmu_t mmu, vm_page_t m)
1858 {
1859 	struct  pvo_head *pvo_head;
1860 	struct	pvo_entry *pvo, *next_pvo;
1861 	pmap_t	pmap;
1862 
1863 	rw_wlock(&pvh_global_lock);
1864 	pvo_head = vm_page_to_pvoh(m);
1865 	for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1866 		next_pvo = LIST_NEXT(pvo, pvo_vlink);
1867 
1868 		pmap = pvo->pvo_pmap;
1869 		PMAP_LOCK(pmap);
1870 		moea_pvo_remove(pvo, -1);
1871 		PMAP_UNLOCK(pmap);
1872 	}
1873 	if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1874 		moea_attr_clear(m, PTE_CHG);
1875 		vm_page_dirty(m);
1876 	}
1877 	vm_page_aflag_clear(m, PGA_WRITEABLE);
1878 	rw_wunlock(&pvh_global_lock);
1879 }
1880 
1881 /*
1882  * Allocate a physical page of memory directly from the phys_avail map.
1883  * Can only be called from moea_bootstrap before avail start and end are
1884  * calculated.
1885  */
1886 static vm_offset_t
1887 moea_bootstrap_alloc(vm_size_t size, u_int align)
1888 {
1889 	vm_offset_t	s, e;
1890 	int		i, j;
1891 
1892 	size = round_page(size);
1893 	for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1894 		if (align != 0)
1895 			s = (phys_avail[i] + align - 1) & ~(align - 1);
1896 		else
1897 			s = phys_avail[i];
1898 		e = s + size;
1899 
1900 		if (s < phys_avail[i] || e > phys_avail[i + 1])
1901 			continue;
1902 
1903 		if (s == phys_avail[i]) {
1904 			phys_avail[i] += size;
1905 		} else if (e == phys_avail[i + 1]) {
1906 			phys_avail[i + 1] -= size;
1907 		} else {
1908 			for (j = phys_avail_count * 2; j > i; j -= 2) {
1909 				phys_avail[j] = phys_avail[j - 2];
1910 				phys_avail[j + 1] = phys_avail[j - 1];
1911 			}
1912 
1913 			phys_avail[i + 3] = phys_avail[i + 1];
1914 			phys_avail[i + 1] = s;
1915 			phys_avail[i + 2] = e;
1916 			phys_avail_count++;
1917 		}
1918 
1919 		return (s);
1920 	}
1921 	panic("moea_bootstrap_alloc: could not allocate memory");
1922 }
1923 
1924 static void
1925 moea_syncicache(vm_offset_t pa, vm_size_t len)
1926 {
1927 	__syncicache((void *)pa, len);
1928 }
1929 
1930 static int
1931 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1932     vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1933 {
1934 	struct	pvo_entry *pvo;
1935 	u_int	sr;
1936 	int	first;
1937 	u_int	ptegidx;
1938 	int	i;
1939 	int     bootstrap;
1940 
1941 	moea_pvo_enter_calls++;
1942 	first = 0;
1943 	bootstrap = 0;
1944 
1945 	/*
1946 	 * Compute the PTE Group index.
1947 	 */
1948 	va &= ~ADDR_POFF;
1949 	sr = va_to_sr(pm->pm_sr, va);
1950 	ptegidx = va_to_pteg(sr, va);
1951 
1952 	/*
1953 	 * Remove any existing mapping for this page.  Reuse the pvo entry if
1954 	 * there is a mapping.
1955 	 */
1956 	mtx_lock(&moea_table_mutex);
1957 	LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1958 		if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1959 			if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1960 			    (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1961 			    (pte_lo & PTE_PP)) {
1962 				mtx_unlock(&moea_table_mutex);
1963 				return (0);
1964 			}
1965 			moea_pvo_remove(pvo, -1);
1966 			break;
1967 		}
1968 	}
1969 
1970 	/*
1971 	 * If we aren't overwriting a mapping, try to allocate.
1972 	 */
1973 	if (moea_initialized) {
1974 		pvo = uma_zalloc(zone, M_NOWAIT);
1975 	} else {
1976 		if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1977 			panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1978 			      moea_bpvo_pool_index, BPVO_POOL_SIZE,
1979 			      BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1980 		}
1981 		pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1982 		moea_bpvo_pool_index++;
1983 		bootstrap = 1;
1984 	}
1985 
1986 	if (pvo == NULL) {
1987 		mtx_unlock(&moea_table_mutex);
1988 		return (ENOMEM);
1989 	}
1990 
1991 	moea_pvo_entries++;
1992 	pvo->pvo_vaddr = va;
1993 	pvo->pvo_pmap = pm;
1994 	LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1995 	pvo->pvo_vaddr &= ~ADDR_POFF;
1996 	if (flags & VM_PROT_EXECUTE)
1997 		pvo->pvo_vaddr |= PVO_EXECUTABLE;
1998 	if (flags & PVO_WIRED)
1999 		pvo->pvo_vaddr |= PVO_WIRED;
2000 	if (pvo_head != &moea_pvo_kunmanaged)
2001 		pvo->pvo_vaddr |= PVO_MANAGED;
2002 	if (bootstrap)
2003 		pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2004 
2005 	moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
2006 
2007 	/*
2008 	 * Add to pmap list
2009 	 */
2010 	RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2011 
2012 	/*
2013 	 * Remember if the list was empty and therefore will be the first
2014 	 * item.
2015 	 */
2016 	if (LIST_FIRST(pvo_head) == NULL)
2017 		first = 1;
2018 	LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2019 
2020 	if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2021 		pm->pm_stats.wired_count++;
2022 	pm->pm_stats.resident_count++;
2023 
2024 	/*
2025 	 * We hope this succeeds but it isn't required.
2026 	 */
2027 	i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2028 	if (i >= 0) {
2029 		PVO_PTEGIDX_SET(pvo, i);
2030 	} else {
2031 		panic("moea_pvo_enter: overflow");
2032 		moea_pte_overflow++;
2033 	}
2034 	mtx_unlock(&moea_table_mutex);
2035 
2036 	return (first ? ENOENT : 0);
2037 }
2038 
2039 static void
2040 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2041 {
2042 	struct	pte *pt;
2043 
2044 	/*
2045 	 * If there is an active pte entry, we need to deactivate it (and
2046 	 * save the ref & cfg bits).
2047 	 */
2048 	pt = moea_pvo_to_pte(pvo, pteidx);
2049 	if (pt != NULL) {
2050 		moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2051 		mtx_unlock(&moea_table_mutex);
2052 		PVO_PTEGIDX_CLR(pvo);
2053 	} else {
2054 		moea_pte_overflow--;
2055 	}
2056 
2057 	/*
2058 	 * Update our statistics.
2059 	 */
2060 	pvo->pvo_pmap->pm_stats.resident_count--;
2061 	if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2062 		pvo->pvo_pmap->pm_stats.wired_count--;
2063 
2064 	/*
2065 	 * Save the REF/CHG bits into their cache if the page is managed.
2066 	 */
2067 	if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2068 		struct	vm_page *pg;
2069 
2070 		pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2071 		if (pg != NULL) {
2072 			moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2073 			    (PTE_REF | PTE_CHG));
2074 		}
2075 	}
2076 
2077 	/*
2078 	 * Remove this PVO from the PV and pmap lists.
2079 	 */
2080 	LIST_REMOVE(pvo, pvo_vlink);
2081 	RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2082 
2083 	/*
2084 	 * Remove this from the overflow list and return it to the pool
2085 	 * if we aren't going to reuse it.
2086 	 */
2087 	LIST_REMOVE(pvo, pvo_olink);
2088 	if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2089 		uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2090 		    moea_upvo_zone, pvo);
2091 	moea_pvo_entries--;
2092 	moea_pvo_remove_calls++;
2093 }
2094 
2095 static __inline int
2096 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2097 {
2098 	int	pteidx;
2099 
2100 	/*
2101 	 * We can find the actual pte entry without searching by grabbing
2102 	 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2103 	 * noticing the HID bit.
2104 	 */
2105 	pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2106 	if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2107 		pteidx ^= moea_pteg_mask * 8;
2108 
2109 	return (pteidx);
2110 }
2111 
2112 static struct pvo_entry *
2113 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2114 {
2115 	struct	pvo_entry *pvo;
2116 	int	ptegidx;
2117 	u_int	sr;
2118 
2119 	va &= ~ADDR_POFF;
2120 	sr = va_to_sr(pm->pm_sr, va);
2121 	ptegidx = va_to_pteg(sr, va);
2122 
2123 	mtx_lock(&moea_table_mutex);
2124 	LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2125 		if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2126 			if (pteidx_p)
2127 				*pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2128 			break;
2129 		}
2130 	}
2131 	mtx_unlock(&moea_table_mutex);
2132 
2133 	return (pvo);
2134 }
2135 
2136 static struct pte *
2137 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2138 {
2139 	struct	pte *pt;
2140 
2141 	/*
2142 	 * If we haven't been supplied the ptegidx, calculate it.
2143 	 */
2144 	if (pteidx == -1) {
2145 		int	ptegidx;
2146 		u_int	sr;
2147 
2148 		sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2149 		ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2150 		pteidx = moea_pvo_pte_index(pvo, ptegidx);
2151 	}
2152 
2153 	pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2154 	mtx_lock(&moea_table_mutex);
2155 
2156 	if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2157 		panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2158 		    "valid pte index", pvo);
2159 	}
2160 
2161 	if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2162 		panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2163 		    "pvo but no valid pte", pvo);
2164 	}
2165 
2166 	if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2167 		if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2168 			panic("moea_pvo_to_pte: pvo %p has valid pte in "
2169 			    "moea_pteg_table %p but invalid in pvo", pvo, pt);
2170 		}
2171 
2172 		if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2173 		    != 0) {
2174 			panic("moea_pvo_to_pte: pvo %p pte does not match "
2175 			    "pte %p in moea_pteg_table", pvo, pt);
2176 		}
2177 
2178 		mtx_assert(&moea_table_mutex, MA_OWNED);
2179 		return (pt);
2180 	}
2181 
2182 	if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2183 		panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2184 		    "moea_pteg_table but valid in pvo", pvo, pt);
2185 	}
2186 
2187 	mtx_unlock(&moea_table_mutex);
2188 	return (NULL);
2189 }
2190 
2191 /*
2192  * XXX: THIS STUFF SHOULD BE IN pte.c?
2193  */
2194 int
2195 moea_pte_spill(vm_offset_t addr)
2196 {
2197 	struct	pvo_entry *source_pvo, *victim_pvo;
2198 	struct	pvo_entry *pvo;
2199 	int	ptegidx, i, j;
2200 	u_int	sr;
2201 	struct	pteg *pteg;
2202 	struct	pte *pt;
2203 
2204 	moea_pte_spills++;
2205 
2206 	sr = mfsrin(addr);
2207 	ptegidx = va_to_pteg(sr, addr);
2208 
2209 	/*
2210 	 * Have to substitute some entry.  Use the primary hash for this.
2211 	 * Use low bits of timebase as random generator.
2212 	 */
2213 	pteg = &moea_pteg_table[ptegidx];
2214 	mtx_lock(&moea_table_mutex);
2215 	__asm __volatile("mftb %0" : "=r"(i));
2216 	i &= 7;
2217 	pt = &pteg->pt[i];
2218 
2219 	source_pvo = NULL;
2220 	victim_pvo = NULL;
2221 	LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2222 		/*
2223 		 * We need to find a pvo entry for this address.
2224 		 */
2225 		if (source_pvo == NULL &&
2226 		    moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2227 		    pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2228 			/*
2229 			 * Now found an entry to be spilled into the pteg.
2230 			 * The PTE is now valid, so we know it's active.
2231 			 */
2232 			j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2233 
2234 			if (j >= 0) {
2235 				PVO_PTEGIDX_SET(pvo, j);
2236 				moea_pte_overflow--;
2237 				mtx_unlock(&moea_table_mutex);
2238 				return (1);
2239 			}
2240 
2241 			source_pvo = pvo;
2242 
2243 			if (victim_pvo != NULL)
2244 				break;
2245 		}
2246 
2247 		/*
2248 		 * We also need the pvo entry of the victim we are replacing
2249 		 * so save the R & C bits of the PTE.
2250 		 */
2251 		if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2252 		    moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2253 			victim_pvo = pvo;
2254 			if (source_pvo != NULL)
2255 				break;
2256 		}
2257 	}
2258 
2259 	if (source_pvo == NULL) {
2260 		mtx_unlock(&moea_table_mutex);
2261 		return (0);
2262 	}
2263 
2264 	if (victim_pvo == NULL) {
2265 		if ((pt->pte_hi & PTE_HID) == 0)
2266 			panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2267 			    "entry", pt);
2268 
2269 		/*
2270 		 * If this is a secondary PTE, we need to search it's primary
2271 		 * pvo bucket for the matching PVO.
2272 		 */
2273 		LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2274 		    pvo_olink) {
2275 			/*
2276 			 * We also need the pvo entry of the victim we are
2277 			 * replacing so save the R & C bits of the PTE.
2278 			 */
2279 			if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2280 				victim_pvo = pvo;
2281 				break;
2282 			}
2283 		}
2284 
2285 		if (victim_pvo == NULL)
2286 			panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2287 			    "entry", pt);
2288 	}
2289 
2290 	/*
2291 	 * We are invalidating the TLB entry for the EA we are replacing even
2292 	 * though it's valid.  If we don't, we lose any ref/chg bit changes
2293 	 * contained in the TLB entry.
2294 	 */
2295 	source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2296 
2297 	moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2298 	moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2299 
2300 	PVO_PTEGIDX_CLR(victim_pvo);
2301 	PVO_PTEGIDX_SET(source_pvo, i);
2302 	moea_pte_replacements++;
2303 
2304 	mtx_unlock(&moea_table_mutex);
2305 	return (1);
2306 }
2307 
2308 static int
2309 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2310 {
2311 	struct	pte *pt;
2312 	int	i;
2313 
2314 	mtx_assert(&moea_table_mutex, MA_OWNED);
2315 
2316 	/*
2317 	 * First try primary hash.
2318 	 */
2319 	for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2320 		if ((pt->pte_hi & PTE_VALID) == 0) {
2321 			pvo_pt->pte_hi &= ~PTE_HID;
2322 			moea_pte_set(pt, pvo_pt);
2323 			return (i);
2324 		}
2325 	}
2326 
2327 	/*
2328 	 * Now try secondary hash.
2329 	 */
2330 	ptegidx ^= moea_pteg_mask;
2331 
2332 	for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2333 		if ((pt->pte_hi & PTE_VALID) == 0) {
2334 			pvo_pt->pte_hi |= PTE_HID;
2335 			moea_pte_set(pt, pvo_pt);
2336 			return (i);
2337 		}
2338 	}
2339 
2340 	panic("moea_pte_insert: overflow");
2341 	return (-1);
2342 }
2343 
2344 static boolean_t
2345 moea_query_bit(vm_page_t m, int ptebit)
2346 {
2347 	struct	pvo_entry *pvo;
2348 	struct	pte *pt;
2349 
2350 	rw_assert(&pvh_global_lock, RA_WLOCKED);
2351 	if (moea_attr_fetch(m) & ptebit)
2352 		return (TRUE);
2353 
2354 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2355 
2356 		/*
2357 		 * See if we saved the bit off.  If so, cache it and return
2358 		 * success.
2359 		 */
2360 		if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2361 			moea_attr_save(m, ptebit);
2362 			return (TRUE);
2363 		}
2364 	}
2365 
2366 	/*
2367 	 * No luck, now go through the hard part of looking at the PTEs
2368 	 * themselves.  Sync so that any pending REF/CHG bits are flushed to
2369 	 * the PTEs.
2370 	 */
2371 	powerpc_sync();
2372 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2373 
2374 		/*
2375 		 * See if this pvo has a valid PTE.  if so, fetch the
2376 		 * REF/CHG bits from the valid PTE.  If the appropriate
2377 		 * ptebit is set, cache it and return success.
2378 		 */
2379 		pt = moea_pvo_to_pte(pvo, -1);
2380 		if (pt != NULL) {
2381 			moea_pte_synch(pt, &pvo->pvo_pte.pte);
2382 			mtx_unlock(&moea_table_mutex);
2383 			if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2384 				moea_attr_save(m, ptebit);
2385 				return (TRUE);
2386 			}
2387 		}
2388 	}
2389 
2390 	return (FALSE);
2391 }
2392 
2393 static u_int
2394 moea_clear_bit(vm_page_t m, int ptebit)
2395 {
2396 	u_int	count;
2397 	struct	pvo_entry *pvo;
2398 	struct	pte *pt;
2399 
2400 	rw_assert(&pvh_global_lock, RA_WLOCKED);
2401 
2402 	/*
2403 	 * Clear the cached value.
2404 	 */
2405 	moea_attr_clear(m, ptebit);
2406 
2407 	/*
2408 	 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2409 	 * we can reset the right ones).  note that since the pvo entries and
2410 	 * list heads are accessed via BAT0 and are never placed in the page
2411 	 * table, we don't have to worry about further accesses setting the
2412 	 * REF/CHG bits.
2413 	 */
2414 	powerpc_sync();
2415 
2416 	/*
2417 	 * For each pvo entry, clear the pvo's ptebit.  If this pvo has a
2418 	 * valid pte clear the ptebit from the valid pte.
2419 	 */
2420 	count = 0;
2421 	LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2422 		pt = moea_pvo_to_pte(pvo, -1);
2423 		if (pt != NULL) {
2424 			moea_pte_synch(pt, &pvo->pvo_pte.pte);
2425 			if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2426 				count++;
2427 				moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2428 			}
2429 			mtx_unlock(&moea_table_mutex);
2430 		}
2431 		pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2432 	}
2433 
2434 	return (count);
2435 }
2436 
2437 /*
2438  * Return true if the physical range is encompassed by the battable[idx]
2439  */
2440 static int
2441 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2442 {
2443 	u_int prot;
2444 	u_int32_t start;
2445 	u_int32_t end;
2446 	u_int32_t bat_ble;
2447 
2448 	/*
2449 	 * Return immediately if not a valid mapping
2450 	 */
2451 	if (!(battable[idx].batu & BAT_Vs))
2452 		return (EINVAL);
2453 
2454 	/*
2455 	 * The BAT entry must be cache-inhibited, guarded, and r/w
2456 	 * so it can function as an i/o page
2457 	 */
2458 	prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2459 	if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2460 		return (EPERM);
2461 
2462 	/*
2463 	 * The address should be within the BAT range. Assume that the
2464 	 * start address in the BAT has the correct alignment (thus
2465 	 * not requiring masking)
2466 	 */
2467 	start = battable[idx].batl & BAT_PBS;
2468 	bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2469 	end = start | (bat_ble << 15) | 0x7fff;
2470 
2471 	if ((pa < start) || ((pa + size) > end))
2472 		return (ERANGE);
2473 
2474 	return (0);
2475 }
2476 
2477 boolean_t
2478 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2479 {
2480 	int i;
2481 
2482 	/*
2483 	 * This currently does not work for entries that
2484 	 * overlap 256M BAT segments.
2485 	 */
2486 
2487 	for(i = 0; i < 16; i++)
2488 		if (moea_bat_mapped(i, pa, size) == 0)
2489 			return (0);
2490 
2491 	return (EFAULT);
2492 }
2493 
2494 /*
2495  * Map a set of physical memory pages into the kernel virtual
2496  * address space. Return a pointer to where it is mapped. This
2497  * routine is intended to be used for mapping device memory,
2498  * NOT real memory.
2499  */
2500 void *
2501 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2502 {
2503 
2504 	return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2505 }
2506 
2507 void *
2508 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2509 {
2510 	vm_offset_t va, tmpva, ppa, offset;
2511 	int i;
2512 
2513 	ppa = trunc_page(pa);
2514 	offset = pa & PAGE_MASK;
2515 	size = roundup(offset + size, PAGE_SIZE);
2516 
2517 	/*
2518 	 * If the physical address lies within a valid BAT table entry,
2519 	 * return the 1:1 mapping. This currently doesn't work
2520 	 * for regions that overlap 256M BAT segments.
2521 	 */
2522 	for (i = 0; i < 16; i++) {
2523 		if (moea_bat_mapped(i, pa, size) == 0)
2524 			return ((void *) pa);
2525 	}
2526 
2527 	va = kmem_alloc_nofault(kernel_map, size);
2528 	if (!va)
2529 		panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2530 
2531 	for (tmpva = va; size > 0;) {
2532 		moea_kenter_attr(mmu, tmpva, ppa, ma);
2533 		tlbie(tmpva);
2534 		size -= PAGE_SIZE;
2535 		tmpva += PAGE_SIZE;
2536 		ppa += PAGE_SIZE;
2537 	}
2538 
2539 	return ((void *)(va + offset));
2540 }
2541 
2542 void
2543 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2544 {
2545 	vm_offset_t base, offset;
2546 
2547 	/*
2548 	 * If this is outside kernel virtual space, then it's a
2549 	 * battable entry and doesn't require unmapping
2550 	 */
2551 	if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2552 		base = trunc_page(va);
2553 		offset = va & PAGE_MASK;
2554 		size = roundup(offset + size, PAGE_SIZE);
2555 		kmem_free(kernel_map, base, size);
2556 	}
2557 }
2558 
2559 static void
2560 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2561 {
2562 	struct pvo_entry *pvo;
2563 	vm_offset_t lim;
2564 	vm_paddr_t pa;
2565 	vm_size_t len;
2566 
2567 	PMAP_LOCK(pm);
2568 	while (sz > 0) {
2569 		lim = round_page(va);
2570 		len = MIN(lim - va, sz);
2571 		pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2572 		if (pvo != NULL) {
2573 			pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2574 			    (va & ADDR_POFF);
2575 			moea_syncicache(pa, len);
2576 		}
2577 		va += len;
2578 		sz -= len;
2579 	}
2580 	PMAP_UNLOCK(pm);
2581 }
2582 
2583 vm_offset_t
2584 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2585     vm_size_t *sz)
2586 {
2587 	if (md->md_vaddr == ~0UL)
2588 	    return (md->md_paddr + ofs);
2589 	else
2590 	    return (md->md_vaddr + ofs);
2591 }
2592 
2593 struct pmap_md *
2594 moea_scan_md(mmu_t mmu, struct pmap_md *prev)
2595 {
2596 	static struct pmap_md md;
2597 	struct pvo_entry *pvo;
2598 	vm_offset_t va;
2599 
2600 	if (dumpsys_minidump) {
2601 		md.md_paddr = ~0UL;	/* Minidumps use virtual addresses. */
2602 		if (prev == NULL) {
2603 			/* 1st: kernel .data and .bss. */
2604 			md.md_index = 1;
2605 			md.md_vaddr = trunc_page((uintptr_t)_etext);
2606 			md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2607 			return (&md);
2608 		}
2609 		switch (prev->md_index) {
2610 		case 1:
2611 			/* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2612 			md.md_index = 2;
2613 			md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2614 			md.md_size = round_page(msgbufp->msg_size);
2615 			break;
2616 		case 2:
2617 			/* 3rd: kernel VM. */
2618 			va = prev->md_vaddr + prev->md_size;
2619 			/* Find start of next chunk (from va). */
2620 			while (va < virtual_end) {
2621 				/* Don't dump the buffer cache. */
2622 				if (va >= kmi.buffer_sva &&
2623 				    va < kmi.buffer_eva) {
2624 					va = kmi.buffer_eva;
2625 					continue;
2626 				}
2627 				pvo = moea_pvo_find_va(kernel_pmap,
2628 				    va & ~ADDR_POFF, NULL);
2629 				if (pvo != NULL &&
2630 				    (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2631 					break;
2632 				va += PAGE_SIZE;
2633 			}
2634 			if (va < virtual_end) {
2635 				md.md_vaddr = va;
2636 				va += PAGE_SIZE;
2637 				/* Find last page in chunk. */
2638 				while (va < virtual_end) {
2639 					/* Don't run into the buffer cache. */
2640 					if (va == kmi.buffer_sva)
2641 						break;
2642 					pvo = moea_pvo_find_va(kernel_pmap,
2643 					    va & ~ADDR_POFF, NULL);
2644 					if (pvo == NULL ||
2645 					    !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2646 						break;
2647 					va += PAGE_SIZE;
2648 				}
2649 				md.md_size = va - md.md_vaddr;
2650 				break;
2651 			}
2652 			md.md_index = 3;
2653 			/* FALLTHROUGH */
2654 		default:
2655 			return (NULL);
2656 		}
2657 	} else { /* minidumps */
2658 		mem_regions(&pregions, &pregions_sz,
2659 		    &regions, &regions_sz);
2660 
2661 		if (prev == NULL) {
2662 			/* first physical chunk. */
2663 			md.md_paddr = pregions[0].mr_start;
2664 			md.md_size = pregions[0].mr_size;
2665 			md.md_vaddr = ~0UL;
2666 			md.md_index = 1;
2667 		} else if (md.md_index < pregions_sz) {
2668 			md.md_paddr = pregions[md.md_index].mr_start;
2669 			md.md_size = pregions[md.md_index].mr_size;
2670 			md.md_vaddr = ~0UL;
2671 			md.md_index++;
2672 		} else {
2673 			/* There's no next physical chunk. */
2674 			return (NULL);
2675 		}
2676 	}
2677 
2678 	return (&md);
2679 }
2680