1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/queue.h> 110 #include <sys/cpuset.h> 111 #include <sys/ktr.h> 112 #include <sys/lock.h> 113 #include <sys/msgbuf.h> 114 #include <sys/mutex.h> 115 #include <sys/proc.h> 116 #include <sys/rwlock.h> 117 #include <sys/sched.h> 118 #include <sys/sysctl.h> 119 #include <sys/systm.h> 120 #include <sys/vmmeter.h> 121 122 #include <dev/ofw/openfirm.h> 123 124 #include <vm/vm.h> 125 #include <vm/vm_param.h> 126 #include <vm/vm_kern.h> 127 #include <vm/vm_page.h> 128 #include <vm/vm_map.h> 129 #include <vm/vm_object.h> 130 #include <vm/vm_extern.h> 131 #include <vm/vm_pageout.h> 132 #include <vm/uma.h> 133 134 #include <machine/cpu.h> 135 #include <machine/platform.h> 136 #include <machine/bat.h> 137 #include <machine/frame.h> 138 #include <machine/md_var.h> 139 #include <machine/psl.h> 140 #include <machine/pte.h> 141 #include <machine/smp.h> 142 #include <machine/sr.h> 143 #include <machine/mmuvar.h> 144 #include <machine/trap.h> 145 146 #include "mmu_if.h" 147 148 #define MOEA_DEBUG 149 150 #define TODO panic("%s: not implemented", __func__); 151 152 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 153 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 154 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 155 156 struct ofw_map { 157 vm_offset_t om_va; 158 vm_size_t om_len; 159 vm_offset_t om_pa; 160 u_int om_mode; 161 }; 162 163 extern unsigned char _etext[]; 164 extern unsigned char _end[]; 165 166 extern int dumpsys_minidump; 167 168 /* 169 * Map of physical memory regions. 170 */ 171 static struct mem_region *regions; 172 static struct mem_region *pregions; 173 static u_int phys_avail_count; 174 static int regions_sz, pregions_sz; 175 static struct ofw_map *translations; 176 177 /* 178 * Lock for the pteg and pvo tables. 179 */ 180 struct mtx moea_table_mutex; 181 struct mtx moea_vsid_mutex; 182 183 /* tlbie instruction synchronization */ 184 static struct mtx tlbie_mtx; 185 186 /* 187 * PTEG data. 188 */ 189 static struct pteg *moea_pteg_table; 190 u_int moea_pteg_count; 191 u_int moea_pteg_mask; 192 193 /* 194 * PVO data. 195 */ 196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197 struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200 static struct rwlock_padalign pvh_global_lock; 201 202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205 #define BPVO_POOL_SIZE 32768 206 static struct pvo_entry *moea_bpvo_pool; 207 static int moea_bpvo_pool_index = 0; 208 209 #define VSID_NBPW (sizeof(u_int32_t) * 8) 210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212 static boolean_t moea_initialized = FALSE; 213 214 /* 215 * Statistics. 216 */ 217 u_int moea_pte_valid = 0; 218 u_int moea_pte_overflow = 0; 219 u_int moea_pte_replacements = 0; 220 u_int moea_pvo_entries = 0; 221 u_int moea_pvo_enter_calls = 0; 222 u_int moea_pvo_remove_calls = 0; 223 u_int moea_pte_spills = 0; 224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239 /* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244 /* 245 * PTE calls. 246 */ 247 static int moea_pte_insert(u_int, struct pte *); 248 249 /* 250 * PVO calls. 251 */ 252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_offset_t, u_int, int); 254 static void moea_pvo_remove(struct pvo_entry *, int); 255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258 /* 259 * Utility routines. 260 */ 261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, u_int, int8_t); 263 static void moea_syncicache(vm_offset_t, vm_size_t); 264 static boolean_t moea_query_bit(vm_page_t, int); 265 static u_int moea_clear_bit(vm_page_t, int); 266 static void moea_kremove(mmu_t, vm_offset_t); 267 int moea_pte_spill(vm_offset_t); 268 269 /* 270 * Kernel MMU interface 271 */ 272 void moea_clear_modify(mmu_t, vm_page_t); 273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 275 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 277 int8_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 int moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_zero_page(mmu_t, vm_page_t); 302 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 303 void moea_zero_page_idle(mmu_t, vm_page_t); 304 void moea_activate(mmu_t, struct thread *); 305 void moea_deactivate(mmu_t, struct thread *); 306 void moea_cpu_bootstrap(mmu_t, int); 307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 317 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 318 vm_size_t *sz); 319 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev); 320 321 static mmu_method_t moea_methods[] = { 322 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 323 MMUMETHOD(mmu_copy_page, moea_copy_page), 324 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 325 MMUMETHOD(mmu_enter, moea_enter), 326 MMUMETHOD(mmu_enter_object, moea_enter_object), 327 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 328 MMUMETHOD(mmu_extract, moea_extract), 329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 330 MMUMETHOD(mmu_init, moea_init), 331 MMUMETHOD(mmu_is_modified, moea_is_modified), 332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 333 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 335 MMUMETHOD(mmu_map, moea_map), 336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 338 MMUMETHOD(mmu_pinit, moea_pinit), 339 MMUMETHOD(mmu_pinit0, moea_pinit0), 340 MMUMETHOD(mmu_protect, moea_protect), 341 MMUMETHOD(mmu_qenter, moea_qenter), 342 MMUMETHOD(mmu_qremove, moea_qremove), 343 MMUMETHOD(mmu_release, moea_release), 344 MMUMETHOD(mmu_remove, moea_remove), 345 MMUMETHOD(mmu_remove_all, moea_remove_all), 346 MMUMETHOD(mmu_remove_write, moea_remove_write), 347 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 348 MMUMETHOD(mmu_unwire, moea_unwire), 349 MMUMETHOD(mmu_zero_page, moea_zero_page), 350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 351 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 352 MMUMETHOD(mmu_activate, moea_activate), 353 MMUMETHOD(mmu_deactivate, moea_deactivate), 354 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 355 356 /* Internal interfaces */ 357 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 358 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 359 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 360 MMUMETHOD(mmu_mapdev, moea_mapdev), 361 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 362 MMUMETHOD(mmu_kextract, moea_kextract), 363 MMUMETHOD(mmu_kenter, moea_kenter), 364 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 365 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 366 MMUMETHOD(mmu_scan_md, moea_scan_md), 367 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 368 369 { 0, 0 } 370 }; 371 372 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 373 374 static __inline uint32_t 375 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 376 { 377 uint32_t pte_lo; 378 int i; 379 380 if (ma != VM_MEMATTR_DEFAULT) { 381 switch (ma) { 382 case VM_MEMATTR_UNCACHEABLE: 383 return (PTE_I | PTE_G); 384 case VM_MEMATTR_WRITE_COMBINING: 385 case VM_MEMATTR_WRITE_BACK: 386 case VM_MEMATTR_PREFETCHABLE: 387 return (PTE_I); 388 case VM_MEMATTR_WRITE_THROUGH: 389 return (PTE_W | PTE_M); 390 } 391 } 392 393 /* 394 * Assume the page is cache inhibited and access is guarded unless 395 * it's in our available memory array. 396 */ 397 pte_lo = PTE_I | PTE_G; 398 for (i = 0; i < pregions_sz; i++) { 399 if ((pa >= pregions[i].mr_start) && 400 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 401 pte_lo = PTE_M; 402 break; 403 } 404 } 405 406 return pte_lo; 407 } 408 409 static void 410 tlbie(vm_offset_t va) 411 { 412 413 mtx_lock_spin(&tlbie_mtx); 414 __asm __volatile("ptesync"); 415 __asm __volatile("tlbie %0" :: "r"(va)); 416 __asm __volatile("eieio; tlbsync; ptesync"); 417 mtx_unlock_spin(&tlbie_mtx); 418 } 419 420 static void 421 tlbia(void) 422 { 423 vm_offset_t va; 424 425 for (va = 0; va < 0x00040000; va += 0x00001000) { 426 __asm __volatile("tlbie %0" :: "r"(va)); 427 powerpc_sync(); 428 } 429 __asm __volatile("tlbsync"); 430 powerpc_sync(); 431 } 432 433 static __inline int 434 va_to_sr(u_int *sr, vm_offset_t va) 435 { 436 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 437 } 438 439 static __inline u_int 440 va_to_pteg(u_int sr, vm_offset_t addr) 441 { 442 u_int hash; 443 444 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 445 ADDR_PIDX_SHFT); 446 return (hash & moea_pteg_mask); 447 } 448 449 static __inline struct pvo_head * 450 vm_page_to_pvoh(vm_page_t m) 451 { 452 453 return (&m->md.mdpg_pvoh); 454 } 455 456 static __inline void 457 moea_attr_clear(vm_page_t m, int ptebit) 458 { 459 460 rw_assert(&pvh_global_lock, RA_WLOCKED); 461 m->md.mdpg_attrs &= ~ptebit; 462 } 463 464 static __inline int 465 moea_attr_fetch(vm_page_t m) 466 { 467 468 return (m->md.mdpg_attrs); 469 } 470 471 static __inline void 472 moea_attr_save(vm_page_t m, int ptebit) 473 { 474 475 rw_assert(&pvh_global_lock, RA_WLOCKED); 476 m->md.mdpg_attrs |= ptebit; 477 } 478 479 static __inline int 480 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 481 { 482 if (pt->pte_hi == pvo_pt->pte_hi) 483 return (1); 484 485 return (0); 486 } 487 488 static __inline int 489 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 490 { 491 return (pt->pte_hi & ~PTE_VALID) == 492 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 493 ((va >> ADDR_API_SHFT) & PTE_API) | which); 494 } 495 496 static __inline void 497 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 498 { 499 500 mtx_assert(&moea_table_mutex, MA_OWNED); 501 502 /* 503 * Construct a PTE. Default to IMB initially. Valid bit only gets 504 * set when the real pte is set in memory. 505 * 506 * Note: Don't set the valid bit for correct operation of tlb update. 507 */ 508 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 509 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 510 pt->pte_lo = pte_lo; 511 } 512 513 static __inline void 514 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 515 { 516 517 mtx_assert(&moea_table_mutex, MA_OWNED); 518 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 519 } 520 521 static __inline void 522 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 523 { 524 525 mtx_assert(&moea_table_mutex, MA_OWNED); 526 527 /* 528 * As shown in Section 7.6.3.2.3 529 */ 530 pt->pte_lo &= ~ptebit; 531 tlbie(va); 532 } 533 534 static __inline void 535 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 536 { 537 538 mtx_assert(&moea_table_mutex, MA_OWNED); 539 pvo_pt->pte_hi |= PTE_VALID; 540 541 /* 542 * Update the PTE as defined in section 7.6.3.1. 543 * Note that the REF/CHG bits are from pvo_pt and thus should have 544 * been saved so this routine can restore them (if desired). 545 */ 546 pt->pte_lo = pvo_pt->pte_lo; 547 powerpc_sync(); 548 pt->pte_hi = pvo_pt->pte_hi; 549 powerpc_sync(); 550 moea_pte_valid++; 551 } 552 553 static __inline void 554 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 555 { 556 557 mtx_assert(&moea_table_mutex, MA_OWNED); 558 pvo_pt->pte_hi &= ~PTE_VALID; 559 560 /* 561 * Force the reg & chg bits back into the PTEs. 562 */ 563 powerpc_sync(); 564 565 /* 566 * Invalidate the pte. 567 */ 568 pt->pte_hi &= ~PTE_VALID; 569 570 tlbie(va); 571 572 /* 573 * Save the reg & chg bits. 574 */ 575 moea_pte_synch(pt, pvo_pt); 576 moea_pte_valid--; 577 } 578 579 static __inline void 580 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 581 { 582 583 /* 584 * Invalidate the PTE 585 */ 586 moea_pte_unset(pt, pvo_pt, va); 587 moea_pte_set(pt, pvo_pt); 588 } 589 590 /* 591 * Quick sort callout for comparing memory regions. 592 */ 593 static int om_cmp(const void *a, const void *b); 594 595 static int 596 om_cmp(const void *a, const void *b) 597 { 598 const struct ofw_map *mapa; 599 const struct ofw_map *mapb; 600 601 mapa = a; 602 mapb = b; 603 if (mapa->om_pa < mapb->om_pa) 604 return (-1); 605 else if (mapa->om_pa > mapb->om_pa) 606 return (1); 607 else 608 return (0); 609 } 610 611 void 612 moea_cpu_bootstrap(mmu_t mmup, int ap) 613 { 614 u_int sdr; 615 int i; 616 617 if (ap) { 618 powerpc_sync(); 619 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 620 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 621 isync(); 622 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 623 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 624 isync(); 625 } 626 627 #ifdef WII 628 /* 629 * Special case for the Wii: don't install the PCI BAT. 630 */ 631 if (strcmp(installed_platform(), "wii") != 0) { 632 #endif 633 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 634 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 635 #ifdef WII 636 } 637 #endif 638 isync(); 639 640 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 641 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 642 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 643 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 644 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 645 isync(); 646 647 for (i = 0; i < 16; i++) 648 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 649 powerpc_sync(); 650 651 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 652 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 653 isync(); 654 655 tlbia(); 656 } 657 658 void 659 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 660 { 661 ihandle_t mmui; 662 phandle_t chosen, mmu; 663 int sz; 664 int i, j; 665 vm_size_t size, physsz, hwphyssz; 666 vm_offset_t pa, va, off; 667 void *dpcpu; 668 register_t msr; 669 670 /* 671 * Set up BAT0 to map the lowest 256 MB area 672 */ 673 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 674 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 675 676 /* 677 * Map PCI memory space. 678 */ 679 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 680 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 681 682 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 683 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 684 685 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 686 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 687 688 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 689 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 690 691 /* 692 * Map obio devices. 693 */ 694 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 695 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 696 697 /* 698 * Use an IBAT and a DBAT to map the bottom segment of memory 699 * where we are. Turn off instruction relocation temporarily 700 * to prevent faults while reprogramming the IBAT. 701 */ 702 msr = mfmsr(); 703 mtmsr(msr & ~PSL_IR); 704 __asm (".balign 32; \n" 705 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 706 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 707 :: "r"(battable[0].batu), "r"(battable[0].batl)); 708 mtmsr(msr); 709 710 #ifdef WII 711 if (strcmp(installed_platform(), "wii") != 0) { 712 #endif 713 /* map pci space */ 714 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 715 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 716 #ifdef WII 717 } 718 #endif 719 isync(); 720 721 /* set global direct map flag */ 722 hw_direct_map = 1; 723 724 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 725 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 726 727 for (i = 0; i < pregions_sz; i++) { 728 vm_offset_t pa; 729 vm_offset_t end; 730 731 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 732 pregions[i].mr_start, 733 pregions[i].mr_start + pregions[i].mr_size, 734 pregions[i].mr_size); 735 /* 736 * Install entries into the BAT table to allow all 737 * of physmem to be convered by on-demand BAT entries. 738 * The loop will sometimes set the same battable element 739 * twice, but that's fine since they won't be used for 740 * a while yet. 741 */ 742 pa = pregions[i].mr_start & 0xf0000000; 743 end = pregions[i].mr_start + pregions[i].mr_size; 744 do { 745 u_int n = pa >> ADDR_SR_SHFT; 746 747 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 748 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 749 pa += SEGMENT_LENGTH; 750 } while (pa < end); 751 } 752 753 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 754 panic("moea_bootstrap: phys_avail too small"); 755 756 phys_avail_count = 0; 757 physsz = 0; 758 hwphyssz = 0; 759 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 760 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 761 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 762 regions[i].mr_start + regions[i].mr_size, 763 regions[i].mr_size); 764 if (hwphyssz != 0 && 765 (physsz + regions[i].mr_size) >= hwphyssz) { 766 if (physsz < hwphyssz) { 767 phys_avail[j] = regions[i].mr_start; 768 phys_avail[j + 1] = regions[i].mr_start + 769 hwphyssz - physsz; 770 physsz = hwphyssz; 771 phys_avail_count++; 772 } 773 break; 774 } 775 phys_avail[j] = regions[i].mr_start; 776 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 777 phys_avail_count++; 778 physsz += regions[i].mr_size; 779 } 780 781 /* Check for overlap with the kernel and exception vectors */ 782 for (j = 0; j < 2*phys_avail_count; j+=2) { 783 if (phys_avail[j] < EXC_LAST) 784 phys_avail[j] += EXC_LAST; 785 786 if (kernelstart >= phys_avail[j] && 787 kernelstart < phys_avail[j+1]) { 788 if (kernelend < phys_avail[j+1]) { 789 phys_avail[2*phys_avail_count] = 790 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 791 phys_avail[2*phys_avail_count + 1] = 792 phys_avail[j+1]; 793 phys_avail_count++; 794 } 795 796 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 797 } 798 799 if (kernelend >= phys_avail[j] && 800 kernelend < phys_avail[j+1]) { 801 if (kernelstart > phys_avail[j]) { 802 phys_avail[2*phys_avail_count] = phys_avail[j]; 803 phys_avail[2*phys_avail_count + 1] = 804 kernelstart & ~PAGE_MASK; 805 phys_avail_count++; 806 } 807 808 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 809 } 810 } 811 812 physmem = btoc(physsz); 813 814 /* 815 * Allocate PTEG table. 816 */ 817 #ifdef PTEGCOUNT 818 moea_pteg_count = PTEGCOUNT; 819 #else 820 moea_pteg_count = 0x1000; 821 822 while (moea_pteg_count < physmem) 823 moea_pteg_count <<= 1; 824 825 moea_pteg_count >>= 1; 826 #endif /* PTEGCOUNT */ 827 828 size = moea_pteg_count * sizeof(struct pteg); 829 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 830 size); 831 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 832 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 833 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 834 moea_pteg_mask = moea_pteg_count - 1; 835 836 /* 837 * Allocate pv/overflow lists. 838 */ 839 size = sizeof(struct pvo_head) * moea_pteg_count; 840 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 841 PAGE_SIZE); 842 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 843 for (i = 0; i < moea_pteg_count; i++) 844 LIST_INIT(&moea_pvo_table[i]); 845 846 /* 847 * Initialize the lock that synchronizes access to the pteg and pvo 848 * tables. 849 */ 850 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 851 MTX_RECURSE); 852 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 853 854 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 855 856 /* 857 * Initialise the unmanaged pvo pool. 858 */ 859 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 860 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 861 moea_bpvo_pool_index = 0; 862 863 /* 864 * Make sure kernel vsid is allocated as well as VSID 0. 865 */ 866 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 867 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 868 moea_vsid_bitmap[0] |= 1; 869 870 /* 871 * Initialize the kernel pmap (which is statically allocated). 872 */ 873 PMAP_LOCK_INIT(kernel_pmap); 874 for (i = 0; i < 16; i++) 875 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 876 CPU_FILL(&kernel_pmap->pm_active); 877 RB_INIT(&kernel_pmap->pmap_pvo); 878 879 /* 880 * Initialize the global pv list lock. 881 */ 882 rw_init(&pvh_global_lock, "pmap pv global"); 883 884 /* 885 * Set up the Open Firmware mappings 886 */ 887 chosen = OF_finddevice("/chosen"); 888 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 889 (mmu = OF_instance_to_package(mmui)) != -1 && 890 (sz = OF_getproplen(mmu, "translations")) != -1) { 891 translations = NULL; 892 for (i = 0; phys_avail[i] != 0; i += 2) { 893 if (phys_avail[i + 1] >= sz) { 894 translations = (struct ofw_map *)phys_avail[i]; 895 break; 896 } 897 } 898 if (translations == NULL) 899 panic("moea_bootstrap: no space to copy translations"); 900 bzero(translations, sz); 901 if (OF_getprop(mmu, "translations", translations, sz) == -1) 902 panic("moea_bootstrap: can't get ofw translations"); 903 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 904 sz /= sizeof(*translations); 905 qsort(translations, sz, sizeof (*translations), om_cmp); 906 for (i = 0; i < sz; i++) { 907 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 908 translations[i].om_pa, translations[i].om_va, 909 translations[i].om_len); 910 911 /* 912 * If the mapping is 1:1, let the RAM and device 913 * on-demand BAT tables take care of the translation. 914 */ 915 if (translations[i].om_va == translations[i].om_pa) 916 continue; 917 918 /* Enter the pages */ 919 for (off = 0; off < translations[i].om_len; 920 off += PAGE_SIZE) 921 moea_kenter(mmup, translations[i].om_va + off, 922 translations[i].om_pa + off); 923 } 924 } 925 926 /* 927 * Calculate the last available physical address. 928 */ 929 for (i = 0; phys_avail[i + 2] != 0; i += 2) 930 ; 931 Maxmem = powerpc_btop(phys_avail[i + 1]); 932 933 moea_cpu_bootstrap(mmup,0); 934 935 pmap_bootstrapped++; 936 937 /* 938 * Set the start and end of kva. 939 */ 940 virtual_avail = VM_MIN_KERNEL_ADDRESS; 941 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 942 943 /* 944 * Allocate a kernel stack with a guard page for thread0 and map it 945 * into the kernel page map. 946 */ 947 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 948 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 949 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 950 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 951 thread0.td_kstack = va; 952 thread0.td_kstack_pages = KSTACK_PAGES; 953 for (i = 0; i < KSTACK_PAGES; i++) { 954 moea_kenter(mmup, va, pa); 955 pa += PAGE_SIZE; 956 va += PAGE_SIZE; 957 } 958 959 /* 960 * Allocate virtual address space for the message buffer. 961 */ 962 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 963 msgbufp = (struct msgbuf *)virtual_avail; 964 va = virtual_avail; 965 virtual_avail += round_page(msgbufsize); 966 while (va < virtual_avail) { 967 moea_kenter(mmup, va, pa); 968 pa += PAGE_SIZE; 969 va += PAGE_SIZE; 970 } 971 972 /* 973 * Allocate virtual address space for the dynamic percpu area. 974 */ 975 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 976 dpcpu = (void *)virtual_avail; 977 va = virtual_avail; 978 virtual_avail += DPCPU_SIZE; 979 while (va < virtual_avail) { 980 moea_kenter(mmup, va, pa); 981 pa += PAGE_SIZE; 982 va += PAGE_SIZE; 983 } 984 dpcpu_init(dpcpu, 0); 985 } 986 987 /* 988 * Activate a user pmap. The pmap must be activated before it's address 989 * space can be accessed in any way. 990 */ 991 void 992 moea_activate(mmu_t mmu, struct thread *td) 993 { 994 pmap_t pm, pmr; 995 996 /* 997 * Load all the data we need up front to encourage the compiler to 998 * not issue any loads while we have interrupts disabled below. 999 */ 1000 pm = &td->td_proc->p_vmspace->vm_pmap; 1001 pmr = pm->pmap_phys; 1002 1003 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1004 PCPU_SET(curpmap, pmr); 1005 } 1006 1007 void 1008 moea_deactivate(mmu_t mmu, struct thread *td) 1009 { 1010 pmap_t pm; 1011 1012 pm = &td->td_proc->p_vmspace->vm_pmap; 1013 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1014 PCPU_SET(curpmap, NULL); 1015 } 1016 1017 void 1018 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1019 { 1020 struct pvo_entry key, *pvo; 1021 1022 PMAP_LOCK(pm); 1023 key.pvo_vaddr = sva; 1024 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1025 pvo != NULL && PVO_VADDR(pvo) < eva; 1026 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1027 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1028 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1029 pvo->pvo_vaddr &= ~PVO_WIRED; 1030 pm->pm_stats.wired_count--; 1031 } 1032 PMAP_UNLOCK(pm); 1033 } 1034 1035 void 1036 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1037 { 1038 vm_offset_t dst; 1039 vm_offset_t src; 1040 1041 dst = VM_PAGE_TO_PHYS(mdst); 1042 src = VM_PAGE_TO_PHYS(msrc); 1043 1044 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1045 } 1046 1047 void 1048 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1049 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1050 { 1051 void *a_cp, *b_cp; 1052 vm_offset_t a_pg_offset, b_pg_offset; 1053 int cnt; 1054 1055 while (xfersize > 0) { 1056 a_pg_offset = a_offset & PAGE_MASK; 1057 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1058 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1059 a_pg_offset; 1060 b_pg_offset = b_offset & PAGE_MASK; 1061 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1062 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1063 b_pg_offset; 1064 bcopy(a_cp, b_cp, cnt); 1065 a_offset += cnt; 1066 b_offset += cnt; 1067 xfersize -= cnt; 1068 } 1069 } 1070 1071 /* 1072 * Zero a page of physical memory by temporarily mapping it into the tlb. 1073 */ 1074 void 1075 moea_zero_page(mmu_t mmu, vm_page_t m) 1076 { 1077 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1078 1079 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1080 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1081 } 1082 1083 void 1084 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1085 { 1086 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1087 void *va = (void *)(pa + off); 1088 1089 bzero(va, size); 1090 } 1091 1092 void 1093 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1094 { 1095 1096 moea_zero_page(mmu, m); 1097 } 1098 1099 /* 1100 * Map the given physical page at the specified virtual address in the 1101 * target pmap with the protection requested. If specified the page 1102 * will be wired down. 1103 */ 1104 int 1105 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1106 u_int flags, int8_t psind) 1107 { 1108 int error; 1109 1110 for (;;) { 1111 rw_wlock(&pvh_global_lock); 1112 PMAP_LOCK(pmap); 1113 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1114 rw_wunlock(&pvh_global_lock); 1115 PMAP_UNLOCK(pmap); 1116 if (error != ENOMEM) 1117 return (KERN_SUCCESS); 1118 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1119 return (KERN_RESOURCE_SHORTAGE); 1120 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1121 VM_WAIT; 1122 } 1123 } 1124 1125 /* 1126 * Map the given physical page at the specified virtual address in the 1127 * target pmap with the protection requested. If specified the page 1128 * will be wired down. 1129 * 1130 * The global pvh and pmap must be locked. 1131 */ 1132 static int 1133 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1134 u_int flags, int8_t psind __unused) 1135 { 1136 struct pvo_head *pvo_head; 1137 uma_zone_t zone; 1138 u_int pte_lo, pvo_flags; 1139 int error; 1140 1141 if (pmap_bootstrapped) 1142 rw_assert(&pvh_global_lock, RA_WLOCKED); 1143 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1144 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1145 VM_OBJECT_ASSERT_LOCKED(m->object); 1146 1147 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1148 pvo_head = &moea_pvo_kunmanaged; 1149 zone = moea_upvo_zone; 1150 pvo_flags = 0; 1151 } else { 1152 pvo_head = vm_page_to_pvoh(m); 1153 zone = moea_mpvo_zone; 1154 pvo_flags = PVO_MANAGED; 1155 } 1156 1157 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1158 1159 if (prot & VM_PROT_WRITE) { 1160 pte_lo |= PTE_BW; 1161 if (pmap_bootstrapped && 1162 (m->oflags & VPO_UNMANAGED) == 0) 1163 vm_page_aflag_set(m, PGA_WRITEABLE); 1164 } else 1165 pte_lo |= PTE_BR; 1166 1167 if ((flags & PMAP_ENTER_WIRED) != 0) 1168 pvo_flags |= PVO_WIRED; 1169 1170 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1171 pte_lo, pvo_flags); 1172 1173 /* 1174 * Flush the real page from the instruction cache. This has be done 1175 * for all user mappings to prevent information leakage via the 1176 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1177 * mapping for a page. 1178 */ 1179 if (pmap != kernel_pmap && error == ENOENT && 1180 (pte_lo & (PTE_I | PTE_G)) == 0) 1181 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1182 1183 return (error); 1184 } 1185 1186 /* 1187 * Maps a sequence of resident pages belonging to the same object. 1188 * The sequence begins with the given page m_start. This page is 1189 * mapped at the given virtual address start. Each subsequent page is 1190 * mapped at a virtual address that is offset from start by the same 1191 * amount as the page is offset from m_start within the object. The 1192 * last page in the sequence is the page with the largest offset from 1193 * m_start that can be mapped at a virtual address less than the given 1194 * virtual address end. Not every virtual page between start and end 1195 * is mapped; only those for which a resident page exists with the 1196 * corresponding offset from m_start are mapped. 1197 */ 1198 void 1199 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1200 vm_page_t m_start, vm_prot_t prot) 1201 { 1202 vm_page_t m; 1203 vm_pindex_t diff, psize; 1204 1205 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1206 1207 psize = atop(end - start); 1208 m = m_start; 1209 rw_wlock(&pvh_global_lock); 1210 PMAP_LOCK(pm); 1211 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1212 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1213 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1214 m = TAILQ_NEXT(m, listq); 1215 } 1216 rw_wunlock(&pvh_global_lock); 1217 PMAP_UNLOCK(pm); 1218 } 1219 1220 void 1221 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1222 vm_prot_t prot) 1223 { 1224 1225 rw_wlock(&pvh_global_lock); 1226 PMAP_LOCK(pm); 1227 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1228 0, 0); 1229 rw_wunlock(&pvh_global_lock); 1230 PMAP_UNLOCK(pm); 1231 } 1232 1233 vm_paddr_t 1234 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1235 { 1236 struct pvo_entry *pvo; 1237 vm_paddr_t pa; 1238 1239 PMAP_LOCK(pm); 1240 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1241 if (pvo == NULL) 1242 pa = 0; 1243 else 1244 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1245 PMAP_UNLOCK(pm); 1246 return (pa); 1247 } 1248 1249 /* 1250 * Atomically extract and hold the physical page with the given 1251 * pmap and virtual address pair if that mapping permits the given 1252 * protection. 1253 */ 1254 vm_page_t 1255 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1256 { 1257 struct pvo_entry *pvo; 1258 vm_page_t m; 1259 vm_paddr_t pa; 1260 1261 m = NULL; 1262 pa = 0; 1263 PMAP_LOCK(pmap); 1264 retry: 1265 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1266 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1267 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1268 (prot & VM_PROT_WRITE) == 0)) { 1269 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1270 goto retry; 1271 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1272 vm_page_hold(m); 1273 } 1274 PA_UNLOCK_COND(pa); 1275 PMAP_UNLOCK(pmap); 1276 return (m); 1277 } 1278 1279 void 1280 moea_init(mmu_t mmu) 1281 { 1282 1283 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1284 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1285 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1286 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1287 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1288 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1289 moea_initialized = TRUE; 1290 } 1291 1292 boolean_t 1293 moea_is_referenced(mmu_t mmu, vm_page_t m) 1294 { 1295 boolean_t rv; 1296 1297 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1298 ("moea_is_referenced: page %p is not managed", m)); 1299 rw_wlock(&pvh_global_lock); 1300 rv = moea_query_bit(m, PTE_REF); 1301 rw_wunlock(&pvh_global_lock); 1302 return (rv); 1303 } 1304 1305 boolean_t 1306 moea_is_modified(mmu_t mmu, vm_page_t m) 1307 { 1308 boolean_t rv; 1309 1310 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1311 ("moea_is_modified: page %p is not managed", m)); 1312 1313 /* 1314 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1315 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1316 * is clear, no PTEs can have PTE_CHG set. 1317 */ 1318 VM_OBJECT_ASSERT_WLOCKED(m->object); 1319 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1320 return (FALSE); 1321 rw_wlock(&pvh_global_lock); 1322 rv = moea_query_bit(m, PTE_CHG); 1323 rw_wunlock(&pvh_global_lock); 1324 return (rv); 1325 } 1326 1327 boolean_t 1328 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1329 { 1330 struct pvo_entry *pvo; 1331 boolean_t rv; 1332 1333 PMAP_LOCK(pmap); 1334 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1335 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1336 PMAP_UNLOCK(pmap); 1337 return (rv); 1338 } 1339 1340 void 1341 moea_clear_modify(mmu_t mmu, vm_page_t m) 1342 { 1343 1344 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1345 ("moea_clear_modify: page %p is not managed", m)); 1346 VM_OBJECT_ASSERT_WLOCKED(m->object); 1347 KASSERT(!vm_page_xbusied(m), 1348 ("moea_clear_modify: page %p is exclusive busy", m)); 1349 1350 /* 1351 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1352 * set. If the object containing the page is locked and the page is 1353 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1354 */ 1355 if ((m->aflags & PGA_WRITEABLE) == 0) 1356 return; 1357 rw_wlock(&pvh_global_lock); 1358 moea_clear_bit(m, PTE_CHG); 1359 rw_wunlock(&pvh_global_lock); 1360 } 1361 1362 /* 1363 * Clear the write and modified bits in each of the given page's mappings. 1364 */ 1365 void 1366 moea_remove_write(mmu_t mmu, vm_page_t m) 1367 { 1368 struct pvo_entry *pvo; 1369 struct pte *pt; 1370 pmap_t pmap; 1371 u_int lo; 1372 1373 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1374 ("moea_remove_write: page %p is not managed", m)); 1375 1376 /* 1377 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1378 * set by another thread while the object is locked. Thus, 1379 * if PGA_WRITEABLE is clear, no page table entries need updating. 1380 */ 1381 VM_OBJECT_ASSERT_WLOCKED(m->object); 1382 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1383 return; 1384 rw_wlock(&pvh_global_lock); 1385 lo = moea_attr_fetch(m); 1386 powerpc_sync(); 1387 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1388 pmap = pvo->pvo_pmap; 1389 PMAP_LOCK(pmap); 1390 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1391 pt = moea_pvo_to_pte(pvo, -1); 1392 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1393 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1394 if (pt != NULL) { 1395 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1396 lo |= pvo->pvo_pte.pte.pte_lo; 1397 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1398 moea_pte_change(pt, &pvo->pvo_pte.pte, 1399 pvo->pvo_vaddr); 1400 mtx_unlock(&moea_table_mutex); 1401 } 1402 } 1403 PMAP_UNLOCK(pmap); 1404 } 1405 if ((lo & PTE_CHG) != 0) { 1406 moea_attr_clear(m, PTE_CHG); 1407 vm_page_dirty(m); 1408 } 1409 vm_page_aflag_clear(m, PGA_WRITEABLE); 1410 rw_wunlock(&pvh_global_lock); 1411 } 1412 1413 /* 1414 * moea_ts_referenced: 1415 * 1416 * Return a count of reference bits for a page, clearing those bits. 1417 * It is not necessary for every reference bit to be cleared, but it 1418 * is necessary that 0 only be returned when there are truly no 1419 * reference bits set. 1420 * 1421 * XXX: The exact number of bits to check and clear is a matter that 1422 * should be tested and standardized at some point in the future for 1423 * optimal aging of shared pages. 1424 */ 1425 int 1426 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1427 { 1428 int count; 1429 1430 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1431 ("moea_ts_referenced: page %p is not managed", m)); 1432 rw_wlock(&pvh_global_lock); 1433 count = moea_clear_bit(m, PTE_REF); 1434 rw_wunlock(&pvh_global_lock); 1435 return (count); 1436 } 1437 1438 /* 1439 * Modify the WIMG settings of all mappings for a page. 1440 */ 1441 void 1442 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1443 { 1444 struct pvo_entry *pvo; 1445 struct pvo_head *pvo_head; 1446 struct pte *pt; 1447 pmap_t pmap; 1448 u_int lo; 1449 1450 if ((m->oflags & VPO_UNMANAGED) != 0) { 1451 m->md.mdpg_cache_attrs = ma; 1452 return; 1453 } 1454 1455 rw_wlock(&pvh_global_lock); 1456 pvo_head = vm_page_to_pvoh(m); 1457 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1458 1459 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1460 pmap = pvo->pvo_pmap; 1461 PMAP_LOCK(pmap); 1462 pt = moea_pvo_to_pte(pvo, -1); 1463 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1464 pvo->pvo_pte.pte.pte_lo |= lo; 1465 if (pt != NULL) { 1466 moea_pte_change(pt, &pvo->pvo_pte.pte, 1467 pvo->pvo_vaddr); 1468 if (pvo->pvo_pmap == kernel_pmap) 1469 isync(); 1470 } 1471 mtx_unlock(&moea_table_mutex); 1472 PMAP_UNLOCK(pmap); 1473 } 1474 m->md.mdpg_cache_attrs = ma; 1475 rw_wunlock(&pvh_global_lock); 1476 } 1477 1478 /* 1479 * Map a wired page into kernel virtual address space. 1480 */ 1481 void 1482 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1483 { 1484 1485 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1486 } 1487 1488 void 1489 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1490 { 1491 u_int pte_lo; 1492 int error; 1493 1494 #if 0 1495 if (va < VM_MIN_KERNEL_ADDRESS) 1496 panic("moea_kenter: attempt to enter non-kernel address %#x", 1497 va); 1498 #endif 1499 1500 pte_lo = moea_calc_wimg(pa, ma); 1501 1502 PMAP_LOCK(kernel_pmap); 1503 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1504 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1505 1506 if (error != 0 && error != ENOENT) 1507 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1508 pa, error); 1509 1510 PMAP_UNLOCK(kernel_pmap); 1511 } 1512 1513 /* 1514 * Extract the physical page address associated with the given kernel virtual 1515 * address. 1516 */ 1517 vm_paddr_t 1518 moea_kextract(mmu_t mmu, vm_offset_t va) 1519 { 1520 struct pvo_entry *pvo; 1521 vm_paddr_t pa; 1522 1523 /* 1524 * Allow direct mappings on 32-bit OEA 1525 */ 1526 if (va < VM_MIN_KERNEL_ADDRESS) { 1527 return (va); 1528 } 1529 1530 PMAP_LOCK(kernel_pmap); 1531 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1532 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1533 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1534 PMAP_UNLOCK(kernel_pmap); 1535 return (pa); 1536 } 1537 1538 /* 1539 * Remove a wired page from kernel virtual address space. 1540 */ 1541 void 1542 moea_kremove(mmu_t mmu, vm_offset_t va) 1543 { 1544 1545 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1546 } 1547 1548 /* 1549 * Map a range of physical addresses into kernel virtual address space. 1550 * 1551 * The value passed in *virt is a suggested virtual address for the mapping. 1552 * Architectures which can support a direct-mapped physical to virtual region 1553 * can return the appropriate address within that region, leaving '*virt' 1554 * unchanged. We cannot and therefore do not; *virt is updated with the 1555 * first usable address after the mapped region. 1556 */ 1557 vm_offset_t 1558 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1559 vm_paddr_t pa_end, int prot) 1560 { 1561 vm_offset_t sva, va; 1562 1563 sva = *virt; 1564 va = sva; 1565 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1566 moea_kenter(mmu, va, pa_start); 1567 *virt = va; 1568 return (sva); 1569 } 1570 1571 /* 1572 * Returns true if the pmap's pv is one of the first 1573 * 16 pvs linked to from this page. This count may 1574 * be changed upwards or downwards in the future; it 1575 * is only necessary that true be returned for a small 1576 * subset of pmaps for proper page aging. 1577 */ 1578 boolean_t 1579 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1580 { 1581 int loops; 1582 struct pvo_entry *pvo; 1583 boolean_t rv; 1584 1585 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1586 ("moea_page_exists_quick: page %p is not managed", m)); 1587 loops = 0; 1588 rv = FALSE; 1589 rw_wlock(&pvh_global_lock); 1590 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1591 if (pvo->pvo_pmap == pmap) { 1592 rv = TRUE; 1593 break; 1594 } 1595 if (++loops >= 16) 1596 break; 1597 } 1598 rw_wunlock(&pvh_global_lock); 1599 return (rv); 1600 } 1601 1602 /* 1603 * Return the number of managed mappings to the given physical page 1604 * that are wired. 1605 */ 1606 int 1607 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1608 { 1609 struct pvo_entry *pvo; 1610 int count; 1611 1612 count = 0; 1613 if ((m->oflags & VPO_UNMANAGED) != 0) 1614 return (count); 1615 rw_wlock(&pvh_global_lock); 1616 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1617 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1618 count++; 1619 rw_wunlock(&pvh_global_lock); 1620 return (count); 1621 } 1622 1623 static u_int moea_vsidcontext; 1624 1625 void 1626 moea_pinit(mmu_t mmu, pmap_t pmap) 1627 { 1628 int i, mask; 1629 u_int entropy; 1630 1631 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1632 RB_INIT(&pmap->pmap_pvo); 1633 1634 entropy = 0; 1635 __asm __volatile("mftb %0" : "=r"(entropy)); 1636 1637 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1638 == NULL) { 1639 pmap->pmap_phys = pmap; 1640 } 1641 1642 1643 mtx_lock(&moea_vsid_mutex); 1644 /* 1645 * Allocate some segment registers for this pmap. 1646 */ 1647 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1648 u_int hash, n; 1649 1650 /* 1651 * Create a new value by mutiplying by a prime and adding in 1652 * entropy from the timebase register. This is to make the 1653 * VSID more random so that the PT hash function collides 1654 * less often. (Note that the prime casues gcc to do shifts 1655 * instead of a multiply.) 1656 */ 1657 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1658 hash = moea_vsidcontext & (NPMAPS - 1); 1659 if (hash == 0) /* 0 is special, avoid it */ 1660 continue; 1661 n = hash >> 5; 1662 mask = 1 << (hash & (VSID_NBPW - 1)); 1663 hash = (moea_vsidcontext & 0xfffff); 1664 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1665 /* anything free in this bucket? */ 1666 if (moea_vsid_bitmap[n] == 0xffffffff) { 1667 entropy = (moea_vsidcontext >> 20); 1668 continue; 1669 } 1670 i = ffs(~moea_vsid_bitmap[n]) - 1; 1671 mask = 1 << i; 1672 hash &= 0xfffff & ~(VSID_NBPW - 1); 1673 hash |= i; 1674 } 1675 KASSERT(!(moea_vsid_bitmap[n] & mask), 1676 ("Allocating in-use VSID group %#x\n", hash)); 1677 moea_vsid_bitmap[n] |= mask; 1678 for (i = 0; i < 16; i++) 1679 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1680 mtx_unlock(&moea_vsid_mutex); 1681 return; 1682 } 1683 1684 mtx_unlock(&moea_vsid_mutex); 1685 panic("moea_pinit: out of segments"); 1686 } 1687 1688 /* 1689 * Initialize the pmap associated with process 0. 1690 */ 1691 void 1692 moea_pinit0(mmu_t mmu, pmap_t pm) 1693 { 1694 1695 PMAP_LOCK_INIT(pm); 1696 moea_pinit(mmu, pm); 1697 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1698 } 1699 1700 /* 1701 * Set the physical protection on the specified range of this map as requested. 1702 */ 1703 void 1704 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1705 vm_prot_t prot) 1706 { 1707 struct pvo_entry *pvo, *tpvo, key; 1708 struct pte *pt; 1709 1710 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1711 ("moea_protect: non current pmap")); 1712 1713 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1714 moea_remove(mmu, pm, sva, eva); 1715 return; 1716 } 1717 1718 rw_wlock(&pvh_global_lock); 1719 PMAP_LOCK(pm); 1720 key.pvo_vaddr = sva; 1721 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1722 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1723 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1724 1725 /* 1726 * Grab the PTE pointer before we diddle with the cached PTE 1727 * copy. 1728 */ 1729 pt = moea_pvo_to_pte(pvo, -1); 1730 /* 1731 * Change the protection of the page. 1732 */ 1733 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1734 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1735 1736 /* 1737 * If the PVO is in the page table, update that pte as well. 1738 */ 1739 if (pt != NULL) { 1740 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1741 mtx_unlock(&moea_table_mutex); 1742 } 1743 } 1744 rw_wunlock(&pvh_global_lock); 1745 PMAP_UNLOCK(pm); 1746 } 1747 1748 /* 1749 * Map a list of wired pages into kernel virtual address space. This is 1750 * intended for temporary mappings which do not need page modification or 1751 * references recorded. Existing mappings in the region are overwritten. 1752 */ 1753 void 1754 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1755 { 1756 vm_offset_t va; 1757 1758 va = sva; 1759 while (count-- > 0) { 1760 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1761 va += PAGE_SIZE; 1762 m++; 1763 } 1764 } 1765 1766 /* 1767 * Remove page mappings from kernel virtual address space. Intended for 1768 * temporary mappings entered by moea_qenter. 1769 */ 1770 void 1771 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1772 { 1773 vm_offset_t va; 1774 1775 va = sva; 1776 while (count-- > 0) { 1777 moea_kremove(mmu, va); 1778 va += PAGE_SIZE; 1779 } 1780 } 1781 1782 void 1783 moea_release(mmu_t mmu, pmap_t pmap) 1784 { 1785 int idx, mask; 1786 1787 /* 1788 * Free segment register's VSID 1789 */ 1790 if (pmap->pm_sr[0] == 0) 1791 panic("moea_release"); 1792 1793 mtx_lock(&moea_vsid_mutex); 1794 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1795 mask = 1 << (idx % VSID_NBPW); 1796 idx /= VSID_NBPW; 1797 moea_vsid_bitmap[idx] &= ~mask; 1798 mtx_unlock(&moea_vsid_mutex); 1799 } 1800 1801 /* 1802 * Remove the given range of addresses from the specified map. 1803 */ 1804 void 1805 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1806 { 1807 struct pvo_entry *pvo, *tpvo, key; 1808 1809 rw_wlock(&pvh_global_lock); 1810 PMAP_LOCK(pm); 1811 key.pvo_vaddr = sva; 1812 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1813 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1814 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1815 moea_pvo_remove(pvo, -1); 1816 } 1817 PMAP_UNLOCK(pm); 1818 rw_wunlock(&pvh_global_lock); 1819 } 1820 1821 /* 1822 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1823 * will reflect changes in pte's back to the vm_page. 1824 */ 1825 void 1826 moea_remove_all(mmu_t mmu, vm_page_t m) 1827 { 1828 struct pvo_head *pvo_head; 1829 struct pvo_entry *pvo, *next_pvo; 1830 pmap_t pmap; 1831 1832 rw_wlock(&pvh_global_lock); 1833 pvo_head = vm_page_to_pvoh(m); 1834 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1835 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1836 1837 pmap = pvo->pvo_pmap; 1838 PMAP_LOCK(pmap); 1839 moea_pvo_remove(pvo, -1); 1840 PMAP_UNLOCK(pmap); 1841 } 1842 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1843 moea_attr_clear(m, PTE_CHG); 1844 vm_page_dirty(m); 1845 } 1846 vm_page_aflag_clear(m, PGA_WRITEABLE); 1847 rw_wunlock(&pvh_global_lock); 1848 } 1849 1850 /* 1851 * Allocate a physical page of memory directly from the phys_avail map. 1852 * Can only be called from moea_bootstrap before avail start and end are 1853 * calculated. 1854 */ 1855 static vm_offset_t 1856 moea_bootstrap_alloc(vm_size_t size, u_int align) 1857 { 1858 vm_offset_t s, e; 1859 int i, j; 1860 1861 size = round_page(size); 1862 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1863 if (align != 0) 1864 s = (phys_avail[i] + align - 1) & ~(align - 1); 1865 else 1866 s = phys_avail[i]; 1867 e = s + size; 1868 1869 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1870 continue; 1871 1872 if (s == phys_avail[i]) { 1873 phys_avail[i] += size; 1874 } else if (e == phys_avail[i + 1]) { 1875 phys_avail[i + 1] -= size; 1876 } else { 1877 for (j = phys_avail_count * 2; j > i; j -= 2) { 1878 phys_avail[j] = phys_avail[j - 2]; 1879 phys_avail[j + 1] = phys_avail[j - 1]; 1880 } 1881 1882 phys_avail[i + 3] = phys_avail[i + 1]; 1883 phys_avail[i + 1] = s; 1884 phys_avail[i + 2] = e; 1885 phys_avail_count++; 1886 } 1887 1888 return (s); 1889 } 1890 panic("moea_bootstrap_alloc: could not allocate memory"); 1891 } 1892 1893 static void 1894 moea_syncicache(vm_offset_t pa, vm_size_t len) 1895 { 1896 __syncicache((void *)pa, len); 1897 } 1898 1899 static int 1900 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1901 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1902 { 1903 struct pvo_entry *pvo; 1904 u_int sr; 1905 int first; 1906 u_int ptegidx; 1907 int i; 1908 int bootstrap; 1909 1910 moea_pvo_enter_calls++; 1911 first = 0; 1912 bootstrap = 0; 1913 1914 /* 1915 * Compute the PTE Group index. 1916 */ 1917 va &= ~ADDR_POFF; 1918 sr = va_to_sr(pm->pm_sr, va); 1919 ptegidx = va_to_pteg(sr, va); 1920 1921 /* 1922 * Remove any existing mapping for this page. Reuse the pvo entry if 1923 * there is a mapping. 1924 */ 1925 mtx_lock(&moea_table_mutex); 1926 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1927 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1928 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1929 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1930 (pte_lo & PTE_PP)) { 1931 /* 1932 * The PTE is not changing. Instead, this may 1933 * be a request to change the mapping's wired 1934 * attribute. 1935 */ 1936 mtx_unlock(&moea_table_mutex); 1937 if ((flags & PVO_WIRED) != 0 && 1938 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1939 pvo->pvo_vaddr |= PVO_WIRED; 1940 pm->pm_stats.wired_count++; 1941 } else if ((flags & PVO_WIRED) == 0 && 1942 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1943 pvo->pvo_vaddr &= ~PVO_WIRED; 1944 pm->pm_stats.wired_count--; 1945 } 1946 return (0); 1947 } 1948 moea_pvo_remove(pvo, -1); 1949 break; 1950 } 1951 } 1952 1953 /* 1954 * If we aren't overwriting a mapping, try to allocate. 1955 */ 1956 if (moea_initialized) { 1957 pvo = uma_zalloc(zone, M_NOWAIT); 1958 } else { 1959 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1960 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1961 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1962 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1963 } 1964 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1965 moea_bpvo_pool_index++; 1966 bootstrap = 1; 1967 } 1968 1969 if (pvo == NULL) { 1970 mtx_unlock(&moea_table_mutex); 1971 return (ENOMEM); 1972 } 1973 1974 moea_pvo_entries++; 1975 pvo->pvo_vaddr = va; 1976 pvo->pvo_pmap = pm; 1977 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1978 pvo->pvo_vaddr &= ~ADDR_POFF; 1979 if (flags & PVO_WIRED) 1980 pvo->pvo_vaddr |= PVO_WIRED; 1981 if (pvo_head != &moea_pvo_kunmanaged) 1982 pvo->pvo_vaddr |= PVO_MANAGED; 1983 if (bootstrap) 1984 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1985 1986 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1987 1988 /* 1989 * Add to pmap list 1990 */ 1991 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1992 1993 /* 1994 * Remember if the list was empty and therefore will be the first 1995 * item. 1996 */ 1997 if (LIST_FIRST(pvo_head) == NULL) 1998 first = 1; 1999 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2000 2001 if (pvo->pvo_vaddr & PVO_WIRED) 2002 pm->pm_stats.wired_count++; 2003 pm->pm_stats.resident_count++; 2004 2005 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2006 KASSERT(i < 8, ("Invalid PTE index")); 2007 if (i >= 0) { 2008 PVO_PTEGIDX_SET(pvo, i); 2009 } else { 2010 panic("moea_pvo_enter: overflow"); 2011 moea_pte_overflow++; 2012 } 2013 mtx_unlock(&moea_table_mutex); 2014 2015 return (first ? ENOENT : 0); 2016 } 2017 2018 static void 2019 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2020 { 2021 struct pte *pt; 2022 2023 /* 2024 * If there is an active pte entry, we need to deactivate it (and 2025 * save the ref & cfg bits). 2026 */ 2027 pt = moea_pvo_to_pte(pvo, pteidx); 2028 if (pt != NULL) { 2029 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2030 mtx_unlock(&moea_table_mutex); 2031 PVO_PTEGIDX_CLR(pvo); 2032 } else { 2033 moea_pte_overflow--; 2034 } 2035 2036 /* 2037 * Update our statistics. 2038 */ 2039 pvo->pvo_pmap->pm_stats.resident_count--; 2040 if (pvo->pvo_vaddr & PVO_WIRED) 2041 pvo->pvo_pmap->pm_stats.wired_count--; 2042 2043 /* 2044 * Save the REF/CHG bits into their cache if the page is managed. 2045 */ 2046 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2047 struct vm_page *pg; 2048 2049 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2050 if (pg != NULL) { 2051 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2052 (PTE_REF | PTE_CHG)); 2053 } 2054 } 2055 2056 /* 2057 * Remove this PVO from the PV and pmap lists. 2058 */ 2059 LIST_REMOVE(pvo, pvo_vlink); 2060 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2061 2062 /* 2063 * Remove this from the overflow list and return it to the pool 2064 * if we aren't going to reuse it. 2065 */ 2066 LIST_REMOVE(pvo, pvo_olink); 2067 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2068 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2069 moea_upvo_zone, pvo); 2070 moea_pvo_entries--; 2071 moea_pvo_remove_calls++; 2072 } 2073 2074 static __inline int 2075 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2076 { 2077 int pteidx; 2078 2079 /* 2080 * We can find the actual pte entry without searching by grabbing 2081 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2082 * noticing the HID bit. 2083 */ 2084 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2085 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2086 pteidx ^= moea_pteg_mask * 8; 2087 2088 return (pteidx); 2089 } 2090 2091 static struct pvo_entry * 2092 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2093 { 2094 struct pvo_entry *pvo; 2095 int ptegidx; 2096 u_int sr; 2097 2098 va &= ~ADDR_POFF; 2099 sr = va_to_sr(pm->pm_sr, va); 2100 ptegidx = va_to_pteg(sr, va); 2101 2102 mtx_lock(&moea_table_mutex); 2103 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2104 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2105 if (pteidx_p) 2106 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2107 break; 2108 } 2109 } 2110 mtx_unlock(&moea_table_mutex); 2111 2112 return (pvo); 2113 } 2114 2115 static struct pte * 2116 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2117 { 2118 struct pte *pt; 2119 2120 /* 2121 * If we haven't been supplied the ptegidx, calculate it. 2122 */ 2123 if (pteidx == -1) { 2124 int ptegidx; 2125 u_int sr; 2126 2127 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2128 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2129 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2130 } 2131 2132 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2133 mtx_lock(&moea_table_mutex); 2134 2135 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2136 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2137 "valid pte index", pvo); 2138 } 2139 2140 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2141 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2142 "pvo but no valid pte", pvo); 2143 } 2144 2145 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2146 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2147 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2148 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2149 } 2150 2151 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2152 != 0) { 2153 panic("moea_pvo_to_pte: pvo %p pte does not match " 2154 "pte %p in moea_pteg_table", pvo, pt); 2155 } 2156 2157 mtx_assert(&moea_table_mutex, MA_OWNED); 2158 return (pt); 2159 } 2160 2161 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2162 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2163 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2164 } 2165 2166 mtx_unlock(&moea_table_mutex); 2167 return (NULL); 2168 } 2169 2170 /* 2171 * XXX: THIS STUFF SHOULD BE IN pte.c? 2172 */ 2173 int 2174 moea_pte_spill(vm_offset_t addr) 2175 { 2176 struct pvo_entry *source_pvo, *victim_pvo; 2177 struct pvo_entry *pvo; 2178 int ptegidx, i, j; 2179 u_int sr; 2180 struct pteg *pteg; 2181 struct pte *pt; 2182 2183 moea_pte_spills++; 2184 2185 sr = mfsrin(addr); 2186 ptegidx = va_to_pteg(sr, addr); 2187 2188 /* 2189 * Have to substitute some entry. Use the primary hash for this. 2190 * Use low bits of timebase as random generator. 2191 */ 2192 pteg = &moea_pteg_table[ptegidx]; 2193 mtx_lock(&moea_table_mutex); 2194 __asm __volatile("mftb %0" : "=r"(i)); 2195 i &= 7; 2196 pt = &pteg->pt[i]; 2197 2198 source_pvo = NULL; 2199 victim_pvo = NULL; 2200 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2201 /* 2202 * We need to find a pvo entry for this address. 2203 */ 2204 if (source_pvo == NULL && 2205 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2206 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2207 /* 2208 * Now found an entry to be spilled into the pteg. 2209 * The PTE is now valid, so we know it's active. 2210 */ 2211 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2212 2213 if (j >= 0) { 2214 PVO_PTEGIDX_SET(pvo, j); 2215 moea_pte_overflow--; 2216 mtx_unlock(&moea_table_mutex); 2217 return (1); 2218 } 2219 2220 source_pvo = pvo; 2221 2222 if (victim_pvo != NULL) 2223 break; 2224 } 2225 2226 /* 2227 * We also need the pvo entry of the victim we are replacing 2228 * so save the R & C bits of the PTE. 2229 */ 2230 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2231 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2232 victim_pvo = pvo; 2233 if (source_pvo != NULL) 2234 break; 2235 } 2236 } 2237 2238 if (source_pvo == NULL) { 2239 mtx_unlock(&moea_table_mutex); 2240 return (0); 2241 } 2242 2243 if (victim_pvo == NULL) { 2244 if ((pt->pte_hi & PTE_HID) == 0) 2245 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2246 "entry", pt); 2247 2248 /* 2249 * If this is a secondary PTE, we need to search it's primary 2250 * pvo bucket for the matching PVO. 2251 */ 2252 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2253 pvo_olink) { 2254 /* 2255 * We also need the pvo entry of the victim we are 2256 * replacing so save the R & C bits of the PTE. 2257 */ 2258 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2259 victim_pvo = pvo; 2260 break; 2261 } 2262 } 2263 2264 if (victim_pvo == NULL) 2265 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2266 "entry", pt); 2267 } 2268 2269 /* 2270 * We are invalidating the TLB entry for the EA we are replacing even 2271 * though it's valid. If we don't, we lose any ref/chg bit changes 2272 * contained in the TLB entry. 2273 */ 2274 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2275 2276 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2277 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2278 2279 PVO_PTEGIDX_CLR(victim_pvo); 2280 PVO_PTEGIDX_SET(source_pvo, i); 2281 moea_pte_replacements++; 2282 2283 mtx_unlock(&moea_table_mutex); 2284 return (1); 2285 } 2286 2287 static __inline struct pvo_entry * 2288 moea_pte_spillable_ident(u_int ptegidx) 2289 { 2290 struct pte *pt; 2291 struct pvo_entry *pvo_walk, *pvo = NULL; 2292 2293 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2294 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2295 continue; 2296 2297 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2298 continue; 2299 2300 pt = moea_pvo_to_pte(pvo_walk, -1); 2301 2302 if (pt == NULL) 2303 continue; 2304 2305 pvo = pvo_walk; 2306 2307 mtx_unlock(&moea_table_mutex); 2308 if (!(pt->pte_lo & PTE_REF)) 2309 return (pvo_walk); 2310 } 2311 2312 return (pvo); 2313 } 2314 2315 static int 2316 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2317 { 2318 struct pte *pt; 2319 struct pvo_entry *victim_pvo; 2320 int i; 2321 int victim_idx; 2322 u_int pteg_bkpidx = ptegidx; 2323 2324 mtx_assert(&moea_table_mutex, MA_OWNED); 2325 2326 /* 2327 * First try primary hash. 2328 */ 2329 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2330 if ((pt->pte_hi & PTE_VALID) == 0) { 2331 pvo_pt->pte_hi &= ~PTE_HID; 2332 moea_pte_set(pt, pvo_pt); 2333 return (i); 2334 } 2335 } 2336 2337 /* 2338 * Now try secondary hash. 2339 */ 2340 ptegidx ^= moea_pteg_mask; 2341 2342 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2343 if ((pt->pte_hi & PTE_VALID) == 0) { 2344 pvo_pt->pte_hi |= PTE_HID; 2345 moea_pte_set(pt, pvo_pt); 2346 return (i); 2347 } 2348 } 2349 2350 /* Try again, but this time try to force a PTE out. */ 2351 ptegidx = pteg_bkpidx; 2352 2353 victim_pvo = moea_pte_spillable_ident(ptegidx); 2354 if (victim_pvo == NULL) { 2355 ptegidx ^= moea_pteg_mask; 2356 victim_pvo = moea_pte_spillable_ident(ptegidx); 2357 } 2358 2359 if (victim_pvo == NULL) { 2360 panic("moea_pte_insert: overflow"); 2361 return (-1); 2362 } 2363 2364 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2365 2366 if (pteg_bkpidx == ptegidx) 2367 pvo_pt->pte_hi &= ~PTE_HID; 2368 else 2369 pvo_pt->pte_hi |= PTE_HID; 2370 2371 /* 2372 * Synchronize the sacrifice PTE with its PVO, then mark both 2373 * invalid. The PVO will be reused when/if the VM system comes 2374 * here after a fault. 2375 */ 2376 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2377 2378 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2379 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2380 2381 /* 2382 * Set the new PTE. 2383 */ 2384 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2385 PVO_PTEGIDX_CLR(victim_pvo); 2386 moea_pte_overflow++; 2387 moea_pte_set(pt, pvo_pt); 2388 2389 return (victim_idx & 7); 2390 } 2391 2392 static boolean_t 2393 moea_query_bit(vm_page_t m, int ptebit) 2394 { 2395 struct pvo_entry *pvo; 2396 struct pte *pt; 2397 2398 rw_assert(&pvh_global_lock, RA_WLOCKED); 2399 if (moea_attr_fetch(m) & ptebit) 2400 return (TRUE); 2401 2402 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2403 2404 /* 2405 * See if we saved the bit off. If so, cache it and return 2406 * success. 2407 */ 2408 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2409 moea_attr_save(m, ptebit); 2410 return (TRUE); 2411 } 2412 } 2413 2414 /* 2415 * No luck, now go through the hard part of looking at the PTEs 2416 * themselves. Sync so that any pending REF/CHG bits are flushed to 2417 * the PTEs. 2418 */ 2419 powerpc_sync(); 2420 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2421 2422 /* 2423 * See if this pvo has a valid PTE. if so, fetch the 2424 * REF/CHG bits from the valid PTE. If the appropriate 2425 * ptebit is set, cache it and return success. 2426 */ 2427 pt = moea_pvo_to_pte(pvo, -1); 2428 if (pt != NULL) { 2429 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2430 mtx_unlock(&moea_table_mutex); 2431 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2432 moea_attr_save(m, ptebit); 2433 return (TRUE); 2434 } 2435 } 2436 } 2437 2438 return (FALSE); 2439 } 2440 2441 static u_int 2442 moea_clear_bit(vm_page_t m, int ptebit) 2443 { 2444 u_int count; 2445 struct pvo_entry *pvo; 2446 struct pte *pt; 2447 2448 rw_assert(&pvh_global_lock, RA_WLOCKED); 2449 2450 /* 2451 * Clear the cached value. 2452 */ 2453 moea_attr_clear(m, ptebit); 2454 2455 /* 2456 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2457 * we can reset the right ones). note that since the pvo entries and 2458 * list heads are accessed via BAT0 and are never placed in the page 2459 * table, we don't have to worry about further accesses setting the 2460 * REF/CHG bits. 2461 */ 2462 powerpc_sync(); 2463 2464 /* 2465 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2466 * valid pte clear the ptebit from the valid pte. 2467 */ 2468 count = 0; 2469 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2470 pt = moea_pvo_to_pte(pvo, -1); 2471 if (pt != NULL) { 2472 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2473 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2474 count++; 2475 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2476 } 2477 mtx_unlock(&moea_table_mutex); 2478 } 2479 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2480 } 2481 2482 return (count); 2483 } 2484 2485 /* 2486 * Return true if the physical range is encompassed by the battable[idx] 2487 */ 2488 static int 2489 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2490 { 2491 u_int prot; 2492 u_int32_t start; 2493 u_int32_t end; 2494 u_int32_t bat_ble; 2495 2496 /* 2497 * Return immediately if not a valid mapping 2498 */ 2499 if (!(battable[idx].batu & BAT_Vs)) 2500 return (EINVAL); 2501 2502 /* 2503 * The BAT entry must be cache-inhibited, guarded, and r/w 2504 * so it can function as an i/o page 2505 */ 2506 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2507 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2508 return (EPERM); 2509 2510 /* 2511 * The address should be within the BAT range. Assume that the 2512 * start address in the BAT has the correct alignment (thus 2513 * not requiring masking) 2514 */ 2515 start = battable[idx].batl & BAT_PBS; 2516 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2517 end = start | (bat_ble << 15) | 0x7fff; 2518 2519 if ((pa < start) || ((pa + size) > end)) 2520 return (ERANGE); 2521 2522 return (0); 2523 } 2524 2525 boolean_t 2526 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2527 { 2528 int i; 2529 2530 /* 2531 * This currently does not work for entries that 2532 * overlap 256M BAT segments. 2533 */ 2534 2535 for(i = 0; i < 16; i++) 2536 if (moea_bat_mapped(i, pa, size) == 0) 2537 return (0); 2538 2539 return (EFAULT); 2540 } 2541 2542 /* 2543 * Map a set of physical memory pages into the kernel virtual 2544 * address space. Return a pointer to where it is mapped. This 2545 * routine is intended to be used for mapping device memory, 2546 * NOT real memory. 2547 */ 2548 void * 2549 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2550 { 2551 2552 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2553 } 2554 2555 void * 2556 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2557 { 2558 vm_offset_t va, tmpva, ppa, offset; 2559 int i; 2560 2561 ppa = trunc_page(pa); 2562 offset = pa & PAGE_MASK; 2563 size = roundup(offset + size, PAGE_SIZE); 2564 2565 /* 2566 * If the physical address lies within a valid BAT table entry, 2567 * return the 1:1 mapping. This currently doesn't work 2568 * for regions that overlap 256M BAT segments. 2569 */ 2570 for (i = 0; i < 16; i++) { 2571 if (moea_bat_mapped(i, pa, size) == 0) 2572 return ((void *) pa); 2573 } 2574 2575 va = kva_alloc(size); 2576 if (!va) 2577 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2578 2579 for (tmpva = va; size > 0;) { 2580 moea_kenter_attr(mmu, tmpva, ppa, ma); 2581 tlbie(tmpva); 2582 size -= PAGE_SIZE; 2583 tmpva += PAGE_SIZE; 2584 ppa += PAGE_SIZE; 2585 } 2586 2587 return ((void *)(va + offset)); 2588 } 2589 2590 void 2591 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2592 { 2593 vm_offset_t base, offset; 2594 2595 /* 2596 * If this is outside kernel virtual space, then it's a 2597 * battable entry and doesn't require unmapping 2598 */ 2599 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2600 base = trunc_page(va); 2601 offset = va & PAGE_MASK; 2602 size = roundup(offset + size, PAGE_SIZE); 2603 kva_free(base, size); 2604 } 2605 } 2606 2607 static void 2608 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2609 { 2610 struct pvo_entry *pvo; 2611 vm_offset_t lim; 2612 vm_paddr_t pa; 2613 vm_size_t len; 2614 2615 PMAP_LOCK(pm); 2616 while (sz > 0) { 2617 lim = round_page(va); 2618 len = MIN(lim - va, sz); 2619 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2620 if (pvo != NULL) { 2621 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2622 (va & ADDR_POFF); 2623 moea_syncicache(pa, len); 2624 } 2625 va += len; 2626 sz -= len; 2627 } 2628 PMAP_UNLOCK(pm); 2629 } 2630 2631 vm_offset_t 2632 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2633 vm_size_t *sz) 2634 { 2635 if (md->md_vaddr == ~0UL) 2636 return (md->md_paddr + ofs); 2637 else 2638 return (md->md_vaddr + ofs); 2639 } 2640 2641 struct pmap_md * 2642 moea_scan_md(mmu_t mmu, struct pmap_md *prev) 2643 { 2644 static struct pmap_md md; 2645 struct pvo_entry *pvo; 2646 vm_offset_t va; 2647 2648 if (dumpsys_minidump) { 2649 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2650 if (prev == NULL) { 2651 /* 1st: kernel .data and .bss. */ 2652 md.md_index = 1; 2653 md.md_vaddr = trunc_page((uintptr_t)_etext); 2654 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2655 return (&md); 2656 } 2657 switch (prev->md_index) { 2658 case 1: 2659 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2660 md.md_index = 2; 2661 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2662 md.md_size = round_page(msgbufp->msg_size); 2663 break; 2664 case 2: 2665 /* 3rd: kernel VM. */ 2666 va = prev->md_vaddr + prev->md_size; 2667 /* Find start of next chunk (from va). */ 2668 while (va < virtual_end) { 2669 /* Don't dump the buffer cache. */ 2670 if (va >= kmi.buffer_sva && 2671 va < kmi.buffer_eva) { 2672 va = kmi.buffer_eva; 2673 continue; 2674 } 2675 pvo = moea_pvo_find_va(kernel_pmap, 2676 va & ~ADDR_POFF, NULL); 2677 if (pvo != NULL && 2678 (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2679 break; 2680 va += PAGE_SIZE; 2681 } 2682 if (va < virtual_end) { 2683 md.md_vaddr = va; 2684 va += PAGE_SIZE; 2685 /* Find last page in chunk. */ 2686 while (va < virtual_end) { 2687 /* Don't run into the buffer cache. */ 2688 if (va == kmi.buffer_sva) 2689 break; 2690 pvo = moea_pvo_find_va(kernel_pmap, 2691 va & ~ADDR_POFF, NULL); 2692 if (pvo == NULL || 2693 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2694 break; 2695 va += PAGE_SIZE; 2696 } 2697 md.md_size = va - md.md_vaddr; 2698 break; 2699 } 2700 md.md_index = 3; 2701 /* FALLTHROUGH */ 2702 default: 2703 return (NULL); 2704 } 2705 } else { /* minidumps */ 2706 mem_regions(&pregions, &pregions_sz, 2707 ®ions, ®ions_sz); 2708 2709 if (prev == NULL) { 2710 /* first physical chunk. */ 2711 md.md_paddr = pregions[0].mr_start; 2712 md.md_size = pregions[0].mr_size; 2713 md.md_vaddr = ~0UL; 2714 md.md_index = 1; 2715 } else if (md.md_index < pregions_sz) { 2716 md.md_paddr = pregions[md.md_index].mr_start; 2717 md.md_size = pregions[md.md_index].mr_size; 2718 md.md_vaddr = ~0UL; 2719 md.md_index++; 2720 } else { 2721 /* There's no next physical chunk. */ 2722 return (NULL); 2723 } 2724 } 2725 2726 return (&md); 2727 } 2728