1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/queue.h> 110 #include <sys/cpuset.h> 111 #include <sys/ktr.h> 112 #include <sys/lock.h> 113 #include <sys/msgbuf.h> 114 #include <sys/mutex.h> 115 #include <sys/proc.h> 116 #include <sys/rwlock.h> 117 #include <sys/sched.h> 118 #include <sys/sysctl.h> 119 #include <sys/systm.h> 120 #include <sys/vmmeter.h> 121 122 #include <dev/ofw/openfirm.h> 123 124 #include <vm/vm.h> 125 #include <vm/vm_param.h> 126 #include <vm/vm_kern.h> 127 #include <vm/vm_page.h> 128 #include <vm/vm_map.h> 129 #include <vm/vm_object.h> 130 #include <vm/vm_extern.h> 131 #include <vm/vm_pageout.h> 132 #include <vm/uma.h> 133 134 #include <machine/cpu.h> 135 #include <machine/platform.h> 136 #include <machine/bat.h> 137 #include <machine/frame.h> 138 #include <machine/md_var.h> 139 #include <machine/psl.h> 140 #include <machine/pte.h> 141 #include <machine/smp.h> 142 #include <machine/sr.h> 143 #include <machine/mmuvar.h> 144 #include <machine/trap.h> 145 146 #include "mmu_if.h" 147 148 #define MOEA_DEBUG 149 150 #define TODO panic("%s: not implemented", __func__); 151 152 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 153 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 154 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 155 156 struct ofw_map { 157 vm_offset_t om_va; 158 vm_size_t om_len; 159 vm_offset_t om_pa; 160 u_int om_mode; 161 }; 162 163 extern unsigned char _etext[]; 164 extern unsigned char _end[]; 165 166 extern int dumpsys_minidump; 167 168 /* 169 * Map of physical memory regions. 170 */ 171 static struct mem_region *regions; 172 static struct mem_region *pregions; 173 static u_int phys_avail_count; 174 static int regions_sz, pregions_sz; 175 static struct ofw_map *translations; 176 177 /* 178 * Lock for the pteg and pvo tables. 179 */ 180 struct mtx moea_table_mutex; 181 struct mtx moea_vsid_mutex; 182 183 /* tlbie instruction synchronization */ 184 static struct mtx tlbie_mtx; 185 186 /* 187 * PTEG data. 188 */ 189 static struct pteg *moea_pteg_table; 190 u_int moea_pteg_count; 191 u_int moea_pteg_mask; 192 193 /* 194 * PVO data. 195 */ 196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197 struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200 static struct rwlock_padalign pvh_global_lock; 201 202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205 #define BPVO_POOL_SIZE 32768 206 static struct pvo_entry *moea_bpvo_pool; 207 static int moea_bpvo_pool_index = 0; 208 209 #define VSID_NBPW (sizeof(u_int32_t) * 8) 210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212 static boolean_t moea_initialized = FALSE; 213 214 /* 215 * Statistics. 216 */ 217 u_int moea_pte_valid = 0; 218 u_int moea_pte_overflow = 0; 219 u_int moea_pte_replacements = 0; 220 u_int moea_pvo_entries = 0; 221 u_int moea_pvo_enter_calls = 0; 222 u_int moea_pvo_remove_calls = 0; 223 u_int moea_pte_spills = 0; 224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239 /* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244 /* 245 * PTE calls. 246 */ 247 static int moea_pte_insert(u_int, struct pte *); 248 249 /* 250 * PVO calls. 251 */ 252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_offset_t, u_int, int); 254 static void moea_pvo_remove(struct pvo_entry *, int); 255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258 /* 259 * Utility routines. 260 */ 261 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, boolean_t); 263 static void moea_syncicache(vm_offset_t, vm_size_t); 264 static boolean_t moea_query_bit(vm_page_t, int); 265 static u_int moea_clear_bit(vm_page_t, int); 266 static void moea_kremove(mmu_t, vm_offset_t); 267 int moea_pte_spill(vm_offset_t); 268 269 /* 270 * Kernel MMU interface 271 */ 272 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 273 void moea_clear_modify(mmu_t, vm_page_t); 274 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 275 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 276 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 277 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 int moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_zero_page(mmu_t, vm_page_t); 302 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 303 void moea_zero_page_idle(mmu_t, vm_page_t); 304 void moea_activate(mmu_t, struct thread *); 305 void moea_deactivate(mmu_t, struct thread *); 306 void moea_cpu_bootstrap(mmu_t, int); 307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 317 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 318 vm_size_t *sz); 319 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev); 320 321 static mmu_method_t moea_methods[] = { 322 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 323 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 324 MMUMETHOD(mmu_copy_page, moea_copy_page), 325 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 326 MMUMETHOD(mmu_enter, moea_enter), 327 MMUMETHOD(mmu_enter_object, moea_enter_object), 328 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 329 MMUMETHOD(mmu_extract, moea_extract), 330 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 331 MMUMETHOD(mmu_init, moea_init), 332 MMUMETHOD(mmu_is_modified, moea_is_modified), 333 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 334 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 335 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 336 MMUMETHOD(mmu_map, moea_map), 337 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 338 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 339 MMUMETHOD(mmu_pinit, moea_pinit), 340 MMUMETHOD(mmu_pinit0, moea_pinit0), 341 MMUMETHOD(mmu_protect, moea_protect), 342 MMUMETHOD(mmu_qenter, moea_qenter), 343 MMUMETHOD(mmu_qremove, moea_qremove), 344 MMUMETHOD(mmu_release, moea_release), 345 MMUMETHOD(mmu_remove, moea_remove), 346 MMUMETHOD(mmu_remove_all, moea_remove_all), 347 MMUMETHOD(mmu_remove_write, moea_remove_write), 348 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 349 MMUMETHOD(mmu_unwire, moea_unwire), 350 MMUMETHOD(mmu_zero_page, moea_zero_page), 351 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 352 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 353 MMUMETHOD(mmu_activate, moea_activate), 354 MMUMETHOD(mmu_deactivate, moea_deactivate), 355 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 356 357 /* Internal interfaces */ 358 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 359 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 360 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 361 MMUMETHOD(mmu_mapdev, moea_mapdev), 362 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 363 MMUMETHOD(mmu_kextract, moea_kextract), 364 MMUMETHOD(mmu_kenter, moea_kenter), 365 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 366 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 367 MMUMETHOD(mmu_scan_md, moea_scan_md), 368 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 369 370 { 0, 0 } 371 }; 372 373 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 374 375 static __inline uint32_t 376 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 377 { 378 uint32_t pte_lo; 379 int i; 380 381 if (ma != VM_MEMATTR_DEFAULT) { 382 switch (ma) { 383 case VM_MEMATTR_UNCACHEABLE: 384 return (PTE_I | PTE_G); 385 case VM_MEMATTR_WRITE_COMBINING: 386 case VM_MEMATTR_WRITE_BACK: 387 case VM_MEMATTR_PREFETCHABLE: 388 return (PTE_I); 389 case VM_MEMATTR_WRITE_THROUGH: 390 return (PTE_W | PTE_M); 391 } 392 } 393 394 /* 395 * Assume the page is cache inhibited and access is guarded unless 396 * it's in our available memory array. 397 */ 398 pte_lo = PTE_I | PTE_G; 399 for (i = 0; i < pregions_sz; i++) { 400 if ((pa >= pregions[i].mr_start) && 401 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 402 pte_lo = PTE_M; 403 break; 404 } 405 } 406 407 return pte_lo; 408 } 409 410 static void 411 tlbie(vm_offset_t va) 412 { 413 414 mtx_lock_spin(&tlbie_mtx); 415 __asm __volatile("ptesync"); 416 __asm __volatile("tlbie %0" :: "r"(va)); 417 __asm __volatile("eieio; tlbsync; ptesync"); 418 mtx_unlock_spin(&tlbie_mtx); 419 } 420 421 static void 422 tlbia(void) 423 { 424 vm_offset_t va; 425 426 for (va = 0; va < 0x00040000; va += 0x00001000) { 427 __asm __volatile("tlbie %0" :: "r"(va)); 428 powerpc_sync(); 429 } 430 __asm __volatile("tlbsync"); 431 powerpc_sync(); 432 } 433 434 static __inline int 435 va_to_sr(u_int *sr, vm_offset_t va) 436 { 437 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 438 } 439 440 static __inline u_int 441 va_to_pteg(u_int sr, vm_offset_t addr) 442 { 443 u_int hash; 444 445 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 446 ADDR_PIDX_SHFT); 447 return (hash & moea_pteg_mask); 448 } 449 450 static __inline struct pvo_head * 451 vm_page_to_pvoh(vm_page_t m) 452 { 453 454 return (&m->md.mdpg_pvoh); 455 } 456 457 static __inline void 458 moea_attr_clear(vm_page_t m, int ptebit) 459 { 460 461 rw_assert(&pvh_global_lock, RA_WLOCKED); 462 m->md.mdpg_attrs &= ~ptebit; 463 } 464 465 static __inline int 466 moea_attr_fetch(vm_page_t m) 467 { 468 469 return (m->md.mdpg_attrs); 470 } 471 472 static __inline void 473 moea_attr_save(vm_page_t m, int ptebit) 474 { 475 476 rw_assert(&pvh_global_lock, RA_WLOCKED); 477 m->md.mdpg_attrs |= ptebit; 478 } 479 480 static __inline int 481 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 482 { 483 if (pt->pte_hi == pvo_pt->pte_hi) 484 return (1); 485 486 return (0); 487 } 488 489 static __inline int 490 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 491 { 492 return (pt->pte_hi & ~PTE_VALID) == 493 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 494 ((va >> ADDR_API_SHFT) & PTE_API) | which); 495 } 496 497 static __inline void 498 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 499 { 500 501 mtx_assert(&moea_table_mutex, MA_OWNED); 502 503 /* 504 * Construct a PTE. Default to IMB initially. Valid bit only gets 505 * set when the real pte is set in memory. 506 * 507 * Note: Don't set the valid bit for correct operation of tlb update. 508 */ 509 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 510 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 511 pt->pte_lo = pte_lo; 512 } 513 514 static __inline void 515 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 516 { 517 518 mtx_assert(&moea_table_mutex, MA_OWNED); 519 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 520 } 521 522 static __inline void 523 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 524 { 525 526 mtx_assert(&moea_table_mutex, MA_OWNED); 527 528 /* 529 * As shown in Section 7.6.3.2.3 530 */ 531 pt->pte_lo &= ~ptebit; 532 tlbie(va); 533 } 534 535 static __inline void 536 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 537 { 538 539 mtx_assert(&moea_table_mutex, MA_OWNED); 540 pvo_pt->pte_hi |= PTE_VALID; 541 542 /* 543 * Update the PTE as defined in section 7.6.3.1. 544 * Note that the REF/CHG bits are from pvo_pt and thus should have 545 * been saved so this routine can restore them (if desired). 546 */ 547 pt->pte_lo = pvo_pt->pte_lo; 548 powerpc_sync(); 549 pt->pte_hi = pvo_pt->pte_hi; 550 powerpc_sync(); 551 moea_pte_valid++; 552 } 553 554 static __inline void 555 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 556 { 557 558 mtx_assert(&moea_table_mutex, MA_OWNED); 559 pvo_pt->pte_hi &= ~PTE_VALID; 560 561 /* 562 * Force the reg & chg bits back into the PTEs. 563 */ 564 powerpc_sync(); 565 566 /* 567 * Invalidate the pte. 568 */ 569 pt->pte_hi &= ~PTE_VALID; 570 571 tlbie(va); 572 573 /* 574 * Save the reg & chg bits. 575 */ 576 moea_pte_synch(pt, pvo_pt); 577 moea_pte_valid--; 578 } 579 580 static __inline void 581 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 582 { 583 584 /* 585 * Invalidate the PTE 586 */ 587 moea_pte_unset(pt, pvo_pt, va); 588 moea_pte_set(pt, pvo_pt); 589 } 590 591 /* 592 * Quick sort callout for comparing memory regions. 593 */ 594 static int om_cmp(const void *a, const void *b); 595 596 static int 597 om_cmp(const void *a, const void *b) 598 { 599 const struct ofw_map *mapa; 600 const struct ofw_map *mapb; 601 602 mapa = a; 603 mapb = b; 604 if (mapa->om_pa < mapb->om_pa) 605 return (-1); 606 else if (mapa->om_pa > mapb->om_pa) 607 return (1); 608 else 609 return (0); 610 } 611 612 void 613 moea_cpu_bootstrap(mmu_t mmup, int ap) 614 { 615 u_int sdr; 616 int i; 617 618 if (ap) { 619 powerpc_sync(); 620 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 621 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 622 isync(); 623 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 624 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 625 isync(); 626 } 627 628 #ifdef WII 629 /* 630 * Special case for the Wii: don't install the PCI BAT. 631 */ 632 if (strcmp(installed_platform(), "wii") != 0) { 633 #endif 634 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 635 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 636 #ifdef WII 637 } 638 #endif 639 isync(); 640 641 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 642 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 643 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 644 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 645 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 646 isync(); 647 648 for (i = 0; i < 16; i++) 649 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 650 powerpc_sync(); 651 652 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 653 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 654 isync(); 655 656 tlbia(); 657 } 658 659 void 660 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 661 { 662 ihandle_t mmui; 663 phandle_t chosen, mmu; 664 int sz; 665 int i, j; 666 vm_size_t size, physsz, hwphyssz; 667 vm_offset_t pa, va, off; 668 void *dpcpu; 669 register_t msr; 670 671 /* 672 * Set up BAT0 to map the lowest 256 MB area 673 */ 674 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 675 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 676 677 /* 678 * Map PCI memory space. 679 */ 680 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 681 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 682 683 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 684 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 685 686 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 687 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 688 689 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 690 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 691 692 /* 693 * Map obio devices. 694 */ 695 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 696 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 697 698 /* 699 * Use an IBAT and a DBAT to map the bottom segment of memory 700 * where we are. Turn off instruction relocation temporarily 701 * to prevent faults while reprogramming the IBAT. 702 */ 703 msr = mfmsr(); 704 mtmsr(msr & ~PSL_IR); 705 __asm (".balign 32; \n" 706 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 707 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 708 :: "r"(battable[0].batu), "r"(battable[0].batl)); 709 mtmsr(msr); 710 711 #ifdef WII 712 if (strcmp(installed_platform(), "wii") != 0) { 713 #endif 714 /* map pci space */ 715 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 716 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 717 #ifdef WII 718 } 719 #endif 720 isync(); 721 722 /* set global direct map flag */ 723 hw_direct_map = 1; 724 725 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 726 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 727 728 for (i = 0; i < pregions_sz; i++) { 729 vm_offset_t pa; 730 vm_offset_t end; 731 732 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 733 pregions[i].mr_start, 734 pregions[i].mr_start + pregions[i].mr_size, 735 pregions[i].mr_size); 736 /* 737 * Install entries into the BAT table to allow all 738 * of physmem to be convered by on-demand BAT entries. 739 * The loop will sometimes set the same battable element 740 * twice, but that's fine since they won't be used for 741 * a while yet. 742 */ 743 pa = pregions[i].mr_start & 0xf0000000; 744 end = pregions[i].mr_start + pregions[i].mr_size; 745 do { 746 u_int n = pa >> ADDR_SR_SHFT; 747 748 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 749 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 750 pa += SEGMENT_LENGTH; 751 } while (pa < end); 752 } 753 754 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 755 panic("moea_bootstrap: phys_avail too small"); 756 757 phys_avail_count = 0; 758 physsz = 0; 759 hwphyssz = 0; 760 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 761 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 762 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 763 regions[i].mr_start + regions[i].mr_size, 764 regions[i].mr_size); 765 if (hwphyssz != 0 && 766 (physsz + regions[i].mr_size) >= hwphyssz) { 767 if (physsz < hwphyssz) { 768 phys_avail[j] = regions[i].mr_start; 769 phys_avail[j + 1] = regions[i].mr_start + 770 hwphyssz - physsz; 771 physsz = hwphyssz; 772 phys_avail_count++; 773 } 774 break; 775 } 776 phys_avail[j] = regions[i].mr_start; 777 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 778 phys_avail_count++; 779 physsz += regions[i].mr_size; 780 } 781 782 /* Check for overlap with the kernel and exception vectors */ 783 for (j = 0; j < 2*phys_avail_count; j+=2) { 784 if (phys_avail[j] < EXC_LAST) 785 phys_avail[j] += EXC_LAST; 786 787 if (kernelstart >= phys_avail[j] && 788 kernelstart < phys_avail[j+1]) { 789 if (kernelend < phys_avail[j+1]) { 790 phys_avail[2*phys_avail_count] = 791 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 phys_avail[2*phys_avail_count + 1] = 793 phys_avail[j+1]; 794 phys_avail_count++; 795 } 796 797 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 798 } 799 800 if (kernelend >= phys_avail[j] && 801 kernelend < phys_avail[j+1]) { 802 if (kernelstart > phys_avail[j]) { 803 phys_avail[2*phys_avail_count] = phys_avail[j]; 804 phys_avail[2*phys_avail_count + 1] = 805 kernelstart & ~PAGE_MASK; 806 phys_avail_count++; 807 } 808 809 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 810 } 811 } 812 813 physmem = btoc(physsz); 814 815 /* 816 * Allocate PTEG table. 817 */ 818 #ifdef PTEGCOUNT 819 moea_pteg_count = PTEGCOUNT; 820 #else 821 moea_pteg_count = 0x1000; 822 823 while (moea_pteg_count < physmem) 824 moea_pteg_count <<= 1; 825 826 moea_pteg_count >>= 1; 827 #endif /* PTEGCOUNT */ 828 829 size = moea_pteg_count * sizeof(struct pteg); 830 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 831 size); 832 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 833 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 834 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 835 moea_pteg_mask = moea_pteg_count - 1; 836 837 /* 838 * Allocate pv/overflow lists. 839 */ 840 size = sizeof(struct pvo_head) * moea_pteg_count; 841 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 842 PAGE_SIZE); 843 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 844 for (i = 0; i < moea_pteg_count; i++) 845 LIST_INIT(&moea_pvo_table[i]); 846 847 /* 848 * Initialize the lock that synchronizes access to the pteg and pvo 849 * tables. 850 */ 851 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 852 MTX_RECURSE); 853 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 854 855 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 856 857 /* 858 * Initialise the unmanaged pvo pool. 859 */ 860 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 861 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 862 moea_bpvo_pool_index = 0; 863 864 /* 865 * Make sure kernel vsid is allocated as well as VSID 0. 866 */ 867 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 868 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 869 moea_vsid_bitmap[0] |= 1; 870 871 /* 872 * Initialize the kernel pmap (which is statically allocated). 873 */ 874 PMAP_LOCK_INIT(kernel_pmap); 875 for (i = 0; i < 16; i++) 876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 877 CPU_FILL(&kernel_pmap->pm_active); 878 RB_INIT(&kernel_pmap->pmap_pvo); 879 880 /* 881 * Initialize the global pv list lock. 882 */ 883 rw_init(&pvh_global_lock, "pmap pv global"); 884 885 /* 886 * Set up the Open Firmware mappings 887 */ 888 chosen = OF_finddevice("/chosen"); 889 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 890 (mmu = OF_instance_to_package(mmui)) != -1 && 891 (sz = OF_getproplen(mmu, "translations")) != -1) { 892 translations = NULL; 893 for (i = 0; phys_avail[i] != 0; i += 2) { 894 if (phys_avail[i + 1] >= sz) { 895 translations = (struct ofw_map *)phys_avail[i]; 896 break; 897 } 898 } 899 if (translations == NULL) 900 panic("moea_bootstrap: no space to copy translations"); 901 bzero(translations, sz); 902 if (OF_getprop(mmu, "translations", translations, sz) == -1) 903 panic("moea_bootstrap: can't get ofw translations"); 904 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 905 sz /= sizeof(*translations); 906 qsort(translations, sz, sizeof (*translations), om_cmp); 907 for (i = 0; i < sz; i++) { 908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 909 translations[i].om_pa, translations[i].om_va, 910 translations[i].om_len); 911 912 /* 913 * If the mapping is 1:1, let the RAM and device 914 * on-demand BAT tables take care of the translation. 915 */ 916 if (translations[i].om_va == translations[i].om_pa) 917 continue; 918 919 /* Enter the pages */ 920 for (off = 0; off < translations[i].om_len; 921 off += PAGE_SIZE) 922 moea_kenter(mmup, translations[i].om_va + off, 923 translations[i].om_pa + off); 924 } 925 } 926 927 /* 928 * Calculate the last available physical address. 929 */ 930 for (i = 0; phys_avail[i + 2] != 0; i += 2) 931 ; 932 Maxmem = powerpc_btop(phys_avail[i + 1]); 933 934 moea_cpu_bootstrap(mmup,0); 935 936 pmap_bootstrapped++; 937 938 /* 939 * Set the start and end of kva. 940 */ 941 virtual_avail = VM_MIN_KERNEL_ADDRESS; 942 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 943 944 /* 945 * Allocate a kernel stack with a guard page for thread0 and map it 946 * into the kernel page map. 947 */ 948 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 949 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 950 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 951 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 952 thread0.td_kstack = va; 953 thread0.td_kstack_pages = KSTACK_PAGES; 954 for (i = 0; i < KSTACK_PAGES; i++) { 955 moea_kenter(mmup, va, pa); 956 pa += PAGE_SIZE; 957 va += PAGE_SIZE; 958 } 959 960 /* 961 * Allocate virtual address space for the message buffer. 962 */ 963 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 964 msgbufp = (struct msgbuf *)virtual_avail; 965 va = virtual_avail; 966 virtual_avail += round_page(msgbufsize); 967 while (va < virtual_avail) { 968 moea_kenter(mmup, va, pa); 969 pa += PAGE_SIZE; 970 va += PAGE_SIZE; 971 } 972 973 /* 974 * Allocate virtual address space for the dynamic percpu area. 975 */ 976 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 977 dpcpu = (void *)virtual_avail; 978 va = virtual_avail; 979 virtual_avail += DPCPU_SIZE; 980 while (va < virtual_avail) { 981 moea_kenter(mmup, va, pa); 982 pa += PAGE_SIZE; 983 va += PAGE_SIZE; 984 } 985 dpcpu_init(dpcpu, 0); 986 } 987 988 /* 989 * Activate a user pmap. The pmap must be activated before it's address 990 * space can be accessed in any way. 991 */ 992 void 993 moea_activate(mmu_t mmu, struct thread *td) 994 { 995 pmap_t pm, pmr; 996 997 /* 998 * Load all the data we need up front to encourage the compiler to 999 * not issue any loads while we have interrupts disabled below. 1000 */ 1001 pm = &td->td_proc->p_vmspace->vm_pmap; 1002 pmr = pm->pmap_phys; 1003 1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1005 PCPU_SET(curpmap, pmr); 1006 } 1007 1008 void 1009 moea_deactivate(mmu_t mmu, struct thread *td) 1010 { 1011 pmap_t pm; 1012 1013 pm = &td->td_proc->p_vmspace->vm_pmap; 1014 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1015 PCPU_SET(curpmap, NULL); 1016 } 1017 1018 void 1019 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1020 { 1021 struct pvo_entry *pvo; 1022 1023 PMAP_LOCK(pm); 1024 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1025 1026 if (pvo != NULL) { 1027 if (wired) { 1028 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1029 pm->pm_stats.wired_count++; 1030 pvo->pvo_vaddr |= PVO_WIRED; 1031 } else { 1032 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1033 pm->pm_stats.wired_count--; 1034 pvo->pvo_vaddr &= ~PVO_WIRED; 1035 } 1036 } 1037 PMAP_UNLOCK(pm); 1038 } 1039 1040 void 1041 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1042 { 1043 struct pvo_entry key, *pvo; 1044 1045 PMAP_LOCK(pm); 1046 key.pvo_vaddr = sva; 1047 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1048 pvo != NULL && PVO_VADDR(pvo) < eva; 1049 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1050 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1051 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1052 pvo->pvo_vaddr &= ~PVO_WIRED; 1053 pm->pm_stats.wired_count--; 1054 } 1055 PMAP_UNLOCK(pm); 1056 } 1057 1058 void 1059 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1060 { 1061 vm_offset_t dst; 1062 vm_offset_t src; 1063 1064 dst = VM_PAGE_TO_PHYS(mdst); 1065 src = VM_PAGE_TO_PHYS(msrc); 1066 1067 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1068 } 1069 1070 void 1071 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1072 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1073 { 1074 void *a_cp, *b_cp; 1075 vm_offset_t a_pg_offset, b_pg_offset; 1076 int cnt; 1077 1078 while (xfersize > 0) { 1079 a_pg_offset = a_offset & PAGE_MASK; 1080 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1081 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1082 a_pg_offset; 1083 b_pg_offset = b_offset & PAGE_MASK; 1084 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1085 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1086 b_pg_offset; 1087 bcopy(a_cp, b_cp, cnt); 1088 a_offset += cnt; 1089 b_offset += cnt; 1090 xfersize -= cnt; 1091 } 1092 } 1093 1094 /* 1095 * Zero a page of physical memory by temporarily mapping it into the tlb. 1096 */ 1097 void 1098 moea_zero_page(mmu_t mmu, vm_page_t m) 1099 { 1100 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1101 1102 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1103 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1104 } 1105 1106 void 1107 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1108 { 1109 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1110 void *va = (void *)(pa + off); 1111 1112 bzero(va, size); 1113 } 1114 1115 void 1116 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1117 { 1118 1119 moea_zero_page(mmu, m); 1120 } 1121 1122 /* 1123 * Map the given physical page at the specified virtual address in the 1124 * target pmap with the protection requested. If specified the page 1125 * will be wired down. 1126 */ 1127 void 1128 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1129 boolean_t wired) 1130 { 1131 1132 rw_wlock(&pvh_global_lock); 1133 PMAP_LOCK(pmap); 1134 moea_enter_locked(pmap, va, m, prot, wired); 1135 rw_wunlock(&pvh_global_lock); 1136 PMAP_UNLOCK(pmap); 1137 } 1138 1139 /* 1140 * Map the given physical page at the specified virtual address in the 1141 * target pmap with the protection requested. If specified the page 1142 * will be wired down. 1143 * 1144 * The global pvh and pmap must be locked. 1145 */ 1146 static void 1147 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1148 boolean_t wired) 1149 { 1150 struct pvo_head *pvo_head; 1151 uma_zone_t zone; 1152 u_int pte_lo, pvo_flags; 1153 int error; 1154 1155 if (!moea_initialized) { 1156 pvo_head = &moea_pvo_kunmanaged; 1157 zone = moea_upvo_zone; 1158 pvo_flags = 0; 1159 } else { 1160 pvo_head = vm_page_to_pvoh(m); 1161 zone = moea_mpvo_zone; 1162 pvo_flags = PVO_MANAGED; 1163 } 1164 if (pmap_bootstrapped) 1165 rw_assert(&pvh_global_lock, RA_WLOCKED); 1166 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1167 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1168 VM_OBJECT_ASSERT_LOCKED(m->object); 1169 1170 /* XXX change the pvo head for unmanaged pages */ 1171 if ((m->oflags & VPO_UNMANAGED) != 0) { 1172 pvo_flags &= ~PVO_MANAGED; 1173 pvo_head = &moea_pvo_kunmanaged; 1174 zone = moea_upvo_zone; 1175 } 1176 1177 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1178 1179 if (prot & VM_PROT_WRITE) { 1180 pte_lo |= PTE_BW; 1181 if (pmap_bootstrapped && 1182 (m->oflags & VPO_UNMANAGED) == 0) 1183 vm_page_aflag_set(m, PGA_WRITEABLE); 1184 } else 1185 pte_lo |= PTE_BR; 1186 1187 if (prot & VM_PROT_EXECUTE) 1188 pvo_flags |= PVO_EXECUTABLE; 1189 1190 if (wired) 1191 pvo_flags |= PVO_WIRED; 1192 1193 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1194 pte_lo, pvo_flags); 1195 1196 /* 1197 * Flush the real page from the instruction cache. This has be done 1198 * for all user mappings to prevent information leakage via the 1199 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1200 * mapping for a page. 1201 */ 1202 if (pmap != kernel_pmap && error == ENOENT && 1203 (pte_lo & (PTE_I | PTE_G)) == 0) 1204 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1205 } 1206 1207 /* 1208 * Maps a sequence of resident pages belonging to the same object. 1209 * The sequence begins with the given page m_start. This page is 1210 * mapped at the given virtual address start. Each subsequent page is 1211 * mapped at a virtual address that is offset from start by the same 1212 * amount as the page is offset from m_start within the object. The 1213 * last page in the sequence is the page with the largest offset from 1214 * m_start that can be mapped at a virtual address less than the given 1215 * virtual address end. Not every virtual page between start and end 1216 * is mapped; only those for which a resident page exists with the 1217 * corresponding offset from m_start are mapped. 1218 */ 1219 void 1220 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1221 vm_page_t m_start, vm_prot_t prot) 1222 { 1223 vm_page_t m; 1224 vm_pindex_t diff, psize; 1225 1226 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1227 1228 psize = atop(end - start); 1229 m = m_start; 1230 rw_wlock(&pvh_global_lock); 1231 PMAP_LOCK(pm); 1232 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1233 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1234 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1235 m = TAILQ_NEXT(m, listq); 1236 } 1237 rw_wunlock(&pvh_global_lock); 1238 PMAP_UNLOCK(pm); 1239 } 1240 1241 void 1242 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1243 vm_prot_t prot) 1244 { 1245 1246 rw_wlock(&pvh_global_lock); 1247 PMAP_LOCK(pm); 1248 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1249 FALSE); 1250 rw_wunlock(&pvh_global_lock); 1251 PMAP_UNLOCK(pm); 1252 } 1253 1254 vm_paddr_t 1255 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1256 { 1257 struct pvo_entry *pvo; 1258 vm_paddr_t pa; 1259 1260 PMAP_LOCK(pm); 1261 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1262 if (pvo == NULL) 1263 pa = 0; 1264 else 1265 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1266 PMAP_UNLOCK(pm); 1267 return (pa); 1268 } 1269 1270 /* 1271 * Atomically extract and hold the physical page with the given 1272 * pmap and virtual address pair if that mapping permits the given 1273 * protection. 1274 */ 1275 vm_page_t 1276 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1277 { 1278 struct pvo_entry *pvo; 1279 vm_page_t m; 1280 vm_paddr_t pa; 1281 1282 m = NULL; 1283 pa = 0; 1284 PMAP_LOCK(pmap); 1285 retry: 1286 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1287 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1288 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1289 (prot & VM_PROT_WRITE) == 0)) { 1290 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1291 goto retry; 1292 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1293 vm_page_hold(m); 1294 } 1295 PA_UNLOCK_COND(pa); 1296 PMAP_UNLOCK(pmap); 1297 return (m); 1298 } 1299 1300 void 1301 moea_init(mmu_t mmu) 1302 { 1303 1304 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1305 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1306 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1307 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1308 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1309 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1310 moea_initialized = TRUE; 1311 } 1312 1313 boolean_t 1314 moea_is_referenced(mmu_t mmu, vm_page_t m) 1315 { 1316 boolean_t rv; 1317 1318 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1319 ("moea_is_referenced: page %p is not managed", m)); 1320 rw_wlock(&pvh_global_lock); 1321 rv = moea_query_bit(m, PTE_REF); 1322 rw_wunlock(&pvh_global_lock); 1323 return (rv); 1324 } 1325 1326 boolean_t 1327 moea_is_modified(mmu_t mmu, vm_page_t m) 1328 { 1329 boolean_t rv; 1330 1331 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1332 ("moea_is_modified: page %p is not managed", m)); 1333 1334 /* 1335 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1336 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1337 * is clear, no PTEs can have PTE_CHG set. 1338 */ 1339 VM_OBJECT_ASSERT_WLOCKED(m->object); 1340 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1341 return (FALSE); 1342 rw_wlock(&pvh_global_lock); 1343 rv = moea_query_bit(m, PTE_CHG); 1344 rw_wunlock(&pvh_global_lock); 1345 return (rv); 1346 } 1347 1348 boolean_t 1349 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1350 { 1351 struct pvo_entry *pvo; 1352 boolean_t rv; 1353 1354 PMAP_LOCK(pmap); 1355 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1356 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1357 PMAP_UNLOCK(pmap); 1358 return (rv); 1359 } 1360 1361 void 1362 moea_clear_modify(mmu_t mmu, vm_page_t m) 1363 { 1364 1365 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1366 ("moea_clear_modify: page %p is not managed", m)); 1367 VM_OBJECT_ASSERT_WLOCKED(m->object); 1368 KASSERT(!vm_page_xbusied(m), 1369 ("moea_clear_modify: page %p is exclusive busy", m)); 1370 1371 /* 1372 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1373 * set. If the object containing the page is locked and the page is 1374 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1375 */ 1376 if ((m->aflags & PGA_WRITEABLE) == 0) 1377 return; 1378 rw_wlock(&pvh_global_lock); 1379 moea_clear_bit(m, PTE_CHG); 1380 rw_wunlock(&pvh_global_lock); 1381 } 1382 1383 /* 1384 * Clear the write and modified bits in each of the given page's mappings. 1385 */ 1386 void 1387 moea_remove_write(mmu_t mmu, vm_page_t m) 1388 { 1389 struct pvo_entry *pvo; 1390 struct pte *pt; 1391 pmap_t pmap; 1392 u_int lo; 1393 1394 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1395 ("moea_remove_write: page %p is not managed", m)); 1396 1397 /* 1398 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1399 * set by another thread while the object is locked. Thus, 1400 * if PGA_WRITEABLE is clear, no page table entries need updating. 1401 */ 1402 VM_OBJECT_ASSERT_WLOCKED(m->object); 1403 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1404 return; 1405 rw_wlock(&pvh_global_lock); 1406 lo = moea_attr_fetch(m); 1407 powerpc_sync(); 1408 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1409 pmap = pvo->pvo_pmap; 1410 PMAP_LOCK(pmap); 1411 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1412 pt = moea_pvo_to_pte(pvo, -1); 1413 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1414 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1415 if (pt != NULL) { 1416 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1417 lo |= pvo->pvo_pte.pte.pte_lo; 1418 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1419 moea_pte_change(pt, &pvo->pvo_pte.pte, 1420 pvo->pvo_vaddr); 1421 mtx_unlock(&moea_table_mutex); 1422 } 1423 } 1424 PMAP_UNLOCK(pmap); 1425 } 1426 if ((lo & PTE_CHG) != 0) { 1427 moea_attr_clear(m, PTE_CHG); 1428 vm_page_dirty(m); 1429 } 1430 vm_page_aflag_clear(m, PGA_WRITEABLE); 1431 rw_wunlock(&pvh_global_lock); 1432 } 1433 1434 /* 1435 * moea_ts_referenced: 1436 * 1437 * Return a count of reference bits for a page, clearing those bits. 1438 * It is not necessary for every reference bit to be cleared, but it 1439 * is necessary that 0 only be returned when there are truly no 1440 * reference bits set. 1441 * 1442 * XXX: The exact number of bits to check and clear is a matter that 1443 * should be tested and standardized at some point in the future for 1444 * optimal aging of shared pages. 1445 */ 1446 int 1447 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1448 { 1449 int count; 1450 1451 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1452 ("moea_ts_referenced: page %p is not managed", m)); 1453 rw_wlock(&pvh_global_lock); 1454 count = moea_clear_bit(m, PTE_REF); 1455 rw_wunlock(&pvh_global_lock); 1456 return (count); 1457 } 1458 1459 /* 1460 * Modify the WIMG settings of all mappings for a page. 1461 */ 1462 void 1463 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1464 { 1465 struct pvo_entry *pvo; 1466 struct pvo_head *pvo_head; 1467 struct pte *pt; 1468 pmap_t pmap; 1469 u_int lo; 1470 1471 if ((m->oflags & VPO_UNMANAGED) != 0) { 1472 m->md.mdpg_cache_attrs = ma; 1473 return; 1474 } 1475 1476 rw_wlock(&pvh_global_lock); 1477 pvo_head = vm_page_to_pvoh(m); 1478 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1479 1480 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1481 pmap = pvo->pvo_pmap; 1482 PMAP_LOCK(pmap); 1483 pt = moea_pvo_to_pte(pvo, -1); 1484 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1485 pvo->pvo_pte.pte.pte_lo |= lo; 1486 if (pt != NULL) { 1487 moea_pte_change(pt, &pvo->pvo_pte.pte, 1488 pvo->pvo_vaddr); 1489 if (pvo->pvo_pmap == kernel_pmap) 1490 isync(); 1491 } 1492 mtx_unlock(&moea_table_mutex); 1493 PMAP_UNLOCK(pmap); 1494 } 1495 m->md.mdpg_cache_attrs = ma; 1496 rw_wunlock(&pvh_global_lock); 1497 } 1498 1499 /* 1500 * Map a wired page into kernel virtual address space. 1501 */ 1502 void 1503 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1504 { 1505 1506 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1507 } 1508 1509 void 1510 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1511 { 1512 u_int pte_lo; 1513 int error; 1514 1515 #if 0 1516 if (va < VM_MIN_KERNEL_ADDRESS) 1517 panic("moea_kenter: attempt to enter non-kernel address %#x", 1518 va); 1519 #endif 1520 1521 pte_lo = moea_calc_wimg(pa, ma); 1522 1523 PMAP_LOCK(kernel_pmap); 1524 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1525 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1526 1527 if (error != 0 && error != ENOENT) 1528 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1529 pa, error); 1530 1531 PMAP_UNLOCK(kernel_pmap); 1532 } 1533 1534 /* 1535 * Extract the physical page address associated with the given kernel virtual 1536 * address. 1537 */ 1538 vm_paddr_t 1539 moea_kextract(mmu_t mmu, vm_offset_t va) 1540 { 1541 struct pvo_entry *pvo; 1542 vm_paddr_t pa; 1543 1544 /* 1545 * Allow direct mappings on 32-bit OEA 1546 */ 1547 if (va < VM_MIN_KERNEL_ADDRESS) { 1548 return (va); 1549 } 1550 1551 PMAP_LOCK(kernel_pmap); 1552 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1553 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1554 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1555 PMAP_UNLOCK(kernel_pmap); 1556 return (pa); 1557 } 1558 1559 /* 1560 * Remove a wired page from kernel virtual address space. 1561 */ 1562 void 1563 moea_kremove(mmu_t mmu, vm_offset_t va) 1564 { 1565 1566 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1567 } 1568 1569 /* 1570 * Map a range of physical addresses into kernel virtual address space. 1571 * 1572 * The value passed in *virt is a suggested virtual address for the mapping. 1573 * Architectures which can support a direct-mapped physical to virtual region 1574 * can return the appropriate address within that region, leaving '*virt' 1575 * unchanged. We cannot and therefore do not; *virt is updated with the 1576 * first usable address after the mapped region. 1577 */ 1578 vm_offset_t 1579 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1580 vm_paddr_t pa_end, int prot) 1581 { 1582 vm_offset_t sva, va; 1583 1584 sva = *virt; 1585 va = sva; 1586 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1587 moea_kenter(mmu, va, pa_start); 1588 *virt = va; 1589 return (sva); 1590 } 1591 1592 /* 1593 * Returns true if the pmap's pv is one of the first 1594 * 16 pvs linked to from this page. This count may 1595 * be changed upwards or downwards in the future; it 1596 * is only necessary that true be returned for a small 1597 * subset of pmaps for proper page aging. 1598 */ 1599 boolean_t 1600 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1601 { 1602 int loops; 1603 struct pvo_entry *pvo; 1604 boolean_t rv; 1605 1606 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1607 ("moea_page_exists_quick: page %p is not managed", m)); 1608 loops = 0; 1609 rv = FALSE; 1610 rw_wlock(&pvh_global_lock); 1611 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1612 if (pvo->pvo_pmap == pmap) { 1613 rv = TRUE; 1614 break; 1615 } 1616 if (++loops >= 16) 1617 break; 1618 } 1619 rw_wunlock(&pvh_global_lock); 1620 return (rv); 1621 } 1622 1623 /* 1624 * Return the number of managed mappings to the given physical page 1625 * that are wired. 1626 */ 1627 int 1628 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1629 { 1630 struct pvo_entry *pvo; 1631 int count; 1632 1633 count = 0; 1634 if ((m->oflags & VPO_UNMANAGED) != 0) 1635 return (count); 1636 rw_wlock(&pvh_global_lock); 1637 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1638 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1639 count++; 1640 rw_wunlock(&pvh_global_lock); 1641 return (count); 1642 } 1643 1644 static u_int moea_vsidcontext; 1645 1646 void 1647 moea_pinit(mmu_t mmu, pmap_t pmap) 1648 { 1649 int i, mask; 1650 u_int entropy; 1651 1652 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1653 RB_INIT(&pmap->pmap_pvo); 1654 1655 entropy = 0; 1656 __asm __volatile("mftb %0" : "=r"(entropy)); 1657 1658 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1659 == NULL) { 1660 pmap->pmap_phys = pmap; 1661 } 1662 1663 1664 mtx_lock(&moea_vsid_mutex); 1665 /* 1666 * Allocate some segment registers for this pmap. 1667 */ 1668 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1669 u_int hash, n; 1670 1671 /* 1672 * Create a new value by mutiplying by a prime and adding in 1673 * entropy from the timebase register. This is to make the 1674 * VSID more random so that the PT hash function collides 1675 * less often. (Note that the prime casues gcc to do shifts 1676 * instead of a multiply.) 1677 */ 1678 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1679 hash = moea_vsidcontext & (NPMAPS - 1); 1680 if (hash == 0) /* 0 is special, avoid it */ 1681 continue; 1682 n = hash >> 5; 1683 mask = 1 << (hash & (VSID_NBPW - 1)); 1684 hash = (moea_vsidcontext & 0xfffff); 1685 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1686 /* anything free in this bucket? */ 1687 if (moea_vsid_bitmap[n] == 0xffffffff) { 1688 entropy = (moea_vsidcontext >> 20); 1689 continue; 1690 } 1691 i = ffs(~moea_vsid_bitmap[n]) - 1; 1692 mask = 1 << i; 1693 hash &= 0xfffff & ~(VSID_NBPW - 1); 1694 hash |= i; 1695 } 1696 KASSERT(!(moea_vsid_bitmap[n] & mask), 1697 ("Allocating in-use VSID group %#x\n", hash)); 1698 moea_vsid_bitmap[n] |= mask; 1699 for (i = 0; i < 16; i++) 1700 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1701 mtx_unlock(&moea_vsid_mutex); 1702 return; 1703 } 1704 1705 mtx_unlock(&moea_vsid_mutex); 1706 panic("moea_pinit: out of segments"); 1707 } 1708 1709 /* 1710 * Initialize the pmap associated with process 0. 1711 */ 1712 void 1713 moea_pinit0(mmu_t mmu, pmap_t pm) 1714 { 1715 1716 PMAP_LOCK_INIT(pm); 1717 moea_pinit(mmu, pm); 1718 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1719 } 1720 1721 /* 1722 * Set the physical protection on the specified range of this map as requested. 1723 */ 1724 void 1725 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1726 vm_prot_t prot) 1727 { 1728 struct pvo_entry *pvo, *tpvo, key; 1729 struct pte *pt; 1730 1731 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1732 ("moea_protect: non current pmap")); 1733 1734 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1735 moea_remove(mmu, pm, sva, eva); 1736 return; 1737 } 1738 1739 rw_wlock(&pvh_global_lock); 1740 PMAP_LOCK(pm); 1741 key.pvo_vaddr = sva; 1742 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1743 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1744 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1745 if ((prot & VM_PROT_EXECUTE) == 0) 1746 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1747 1748 /* 1749 * Grab the PTE pointer before we diddle with the cached PTE 1750 * copy. 1751 */ 1752 pt = moea_pvo_to_pte(pvo, -1); 1753 /* 1754 * Change the protection of the page. 1755 */ 1756 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1757 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1758 1759 /* 1760 * If the PVO is in the page table, update that pte as well. 1761 */ 1762 if (pt != NULL) { 1763 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1764 mtx_unlock(&moea_table_mutex); 1765 } 1766 } 1767 rw_wunlock(&pvh_global_lock); 1768 PMAP_UNLOCK(pm); 1769 } 1770 1771 /* 1772 * Map a list of wired pages into kernel virtual address space. This is 1773 * intended for temporary mappings which do not need page modification or 1774 * references recorded. Existing mappings in the region are overwritten. 1775 */ 1776 void 1777 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1778 { 1779 vm_offset_t va; 1780 1781 va = sva; 1782 while (count-- > 0) { 1783 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1784 va += PAGE_SIZE; 1785 m++; 1786 } 1787 } 1788 1789 /* 1790 * Remove page mappings from kernel virtual address space. Intended for 1791 * temporary mappings entered by moea_qenter. 1792 */ 1793 void 1794 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1795 { 1796 vm_offset_t va; 1797 1798 va = sva; 1799 while (count-- > 0) { 1800 moea_kremove(mmu, va); 1801 va += PAGE_SIZE; 1802 } 1803 } 1804 1805 void 1806 moea_release(mmu_t mmu, pmap_t pmap) 1807 { 1808 int idx, mask; 1809 1810 /* 1811 * Free segment register's VSID 1812 */ 1813 if (pmap->pm_sr[0] == 0) 1814 panic("moea_release"); 1815 1816 mtx_lock(&moea_vsid_mutex); 1817 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1818 mask = 1 << (idx % VSID_NBPW); 1819 idx /= VSID_NBPW; 1820 moea_vsid_bitmap[idx] &= ~mask; 1821 mtx_unlock(&moea_vsid_mutex); 1822 } 1823 1824 /* 1825 * Remove the given range of addresses from the specified map. 1826 */ 1827 void 1828 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1829 { 1830 struct pvo_entry *pvo, *tpvo, key; 1831 1832 rw_wlock(&pvh_global_lock); 1833 PMAP_LOCK(pm); 1834 key.pvo_vaddr = sva; 1835 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1836 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1837 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1838 moea_pvo_remove(pvo, -1); 1839 } 1840 PMAP_UNLOCK(pm); 1841 rw_wunlock(&pvh_global_lock); 1842 } 1843 1844 /* 1845 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1846 * will reflect changes in pte's back to the vm_page. 1847 */ 1848 void 1849 moea_remove_all(mmu_t mmu, vm_page_t m) 1850 { 1851 struct pvo_head *pvo_head; 1852 struct pvo_entry *pvo, *next_pvo; 1853 pmap_t pmap; 1854 1855 rw_wlock(&pvh_global_lock); 1856 pvo_head = vm_page_to_pvoh(m); 1857 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1858 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1859 1860 pmap = pvo->pvo_pmap; 1861 PMAP_LOCK(pmap); 1862 moea_pvo_remove(pvo, -1); 1863 PMAP_UNLOCK(pmap); 1864 } 1865 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1866 moea_attr_clear(m, PTE_CHG); 1867 vm_page_dirty(m); 1868 } 1869 vm_page_aflag_clear(m, PGA_WRITEABLE); 1870 rw_wunlock(&pvh_global_lock); 1871 } 1872 1873 /* 1874 * Allocate a physical page of memory directly from the phys_avail map. 1875 * Can only be called from moea_bootstrap before avail start and end are 1876 * calculated. 1877 */ 1878 static vm_offset_t 1879 moea_bootstrap_alloc(vm_size_t size, u_int align) 1880 { 1881 vm_offset_t s, e; 1882 int i, j; 1883 1884 size = round_page(size); 1885 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1886 if (align != 0) 1887 s = (phys_avail[i] + align - 1) & ~(align - 1); 1888 else 1889 s = phys_avail[i]; 1890 e = s + size; 1891 1892 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1893 continue; 1894 1895 if (s == phys_avail[i]) { 1896 phys_avail[i] += size; 1897 } else if (e == phys_avail[i + 1]) { 1898 phys_avail[i + 1] -= size; 1899 } else { 1900 for (j = phys_avail_count * 2; j > i; j -= 2) { 1901 phys_avail[j] = phys_avail[j - 2]; 1902 phys_avail[j + 1] = phys_avail[j - 1]; 1903 } 1904 1905 phys_avail[i + 3] = phys_avail[i + 1]; 1906 phys_avail[i + 1] = s; 1907 phys_avail[i + 2] = e; 1908 phys_avail_count++; 1909 } 1910 1911 return (s); 1912 } 1913 panic("moea_bootstrap_alloc: could not allocate memory"); 1914 } 1915 1916 static void 1917 moea_syncicache(vm_offset_t pa, vm_size_t len) 1918 { 1919 __syncicache((void *)pa, len); 1920 } 1921 1922 static int 1923 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1924 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1925 { 1926 struct pvo_entry *pvo; 1927 u_int sr; 1928 int first; 1929 u_int ptegidx; 1930 int i; 1931 int bootstrap; 1932 1933 moea_pvo_enter_calls++; 1934 first = 0; 1935 bootstrap = 0; 1936 1937 /* 1938 * Compute the PTE Group index. 1939 */ 1940 va &= ~ADDR_POFF; 1941 sr = va_to_sr(pm->pm_sr, va); 1942 ptegidx = va_to_pteg(sr, va); 1943 1944 /* 1945 * Remove any existing mapping for this page. Reuse the pvo entry if 1946 * there is a mapping. 1947 */ 1948 mtx_lock(&moea_table_mutex); 1949 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1950 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1951 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1952 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1953 (pte_lo & PTE_PP)) { 1954 mtx_unlock(&moea_table_mutex); 1955 return (0); 1956 } 1957 moea_pvo_remove(pvo, -1); 1958 break; 1959 } 1960 } 1961 1962 /* 1963 * If we aren't overwriting a mapping, try to allocate. 1964 */ 1965 if (moea_initialized) { 1966 pvo = uma_zalloc(zone, M_NOWAIT); 1967 } else { 1968 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1969 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1970 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1971 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1972 } 1973 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1974 moea_bpvo_pool_index++; 1975 bootstrap = 1; 1976 } 1977 1978 if (pvo == NULL) { 1979 mtx_unlock(&moea_table_mutex); 1980 return (ENOMEM); 1981 } 1982 1983 moea_pvo_entries++; 1984 pvo->pvo_vaddr = va; 1985 pvo->pvo_pmap = pm; 1986 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1987 pvo->pvo_vaddr &= ~ADDR_POFF; 1988 if (flags & VM_PROT_EXECUTE) 1989 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1990 if (flags & PVO_WIRED) 1991 pvo->pvo_vaddr |= PVO_WIRED; 1992 if (pvo_head != &moea_pvo_kunmanaged) 1993 pvo->pvo_vaddr |= PVO_MANAGED; 1994 if (bootstrap) 1995 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1996 1997 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1998 1999 /* 2000 * Add to pmap list 2001 */ 2002 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2003 2004 /* 2005 * Remember if the list was empty and therefore will be the first 2006 * item. 2007 */ 2008 if (LIST_FIRST(pvo_head) == NULL) 2009 first = 1; 2010 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2011 2012 if (pvo->pvo_vaddr & PVO_WIRED) 2013 pm->pm_stats.wired_count++; 2014 pm->pm_stats.resident_count++; 2015 2016 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2017 KASSERT(i < 8, ("Invalid PTE index")); 2018 if (i >= 0) { 2019 PVO_PTEGIDX_SET(pvo, i); 2020 } else { 2021 panic("moea_pvo_enter: overflow"); 2022 moea_pte_overflow++; 2023 } 2024 mtx_unlock(&moea_table_mutex); 2025 2026 return (first ? ENOENT : 0); 2027 } 2028 2029 static void 2030 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2031 { 2032 struct pte *pt; 2033 2034 /* 2035 * If there is an active pte entry, we need to deactivate it (and 2036 * save the ref & cfg bits). 2037 */ 2038 pt = moea_pvo_to_pte(pvo, pteidx); 2039 if (pt != NULL) { 2040 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2041 mtx_unlock(&moea_table_mutex); 2042 PVO_PTEGIDX_CLR(pvo); 2043 } else { 2044 moea_pte_overflow--; 2045 } 2046 2047 /* 2048 * Update our statistics. 2049 */ 2050 pvo->pvo_pmap->pm_stats.resident_count--; 2051 if (pvo->pvo_vaddr & PVO_WIRED) 2052 pvo->pvo_pmap->pm_stats.wired_count--; 2053 2054 /* 2055 * Save the REF/CHG bits into their cache if the page is managed. 2056 */ 2057 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2058 struct vm_page *pg; 2059 2060 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2061 if (pg != NULL) { 2062 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2063 (PTE_REF | PTE_CHG)); 2064 } 2065 } 2066 2067 /* 2068 * Remove this PVO from the PV and pmap lists. 2069 */ 2070 LIST_REMOVE(pvo, pvo_vlink); 2071 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2072 2073 /* 2074 * Remove this from the overflow list and return it to the pool 2075 * if we aren't going to reuse it. 2076 */ 2077 LIST_REMOVE(pvo, pvo_olink); 2078 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2079 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2080 moea_upvo_zone, pvo); 2081 moea_pvo_entries--; 2082 moea_pvo_remove_calls++; 2083 } 2084 2085 static __inline int 2086 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2087 { 2088 int pteidx; 2089 2090 /* 2091 * We can find the actual pte entry without searching by grabbing 2092 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2093 * noticing the HID bit. 2094 */ 2095 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2096 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2097 pteidx ^= moea_pteg_mask * 8; 2098 2099 return (pteidx); 2100 } 2101 2102 static struct pvo_entry * 2103 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2104 { 2105 struct pvo_entry *pvo; 2106 int ptegidx; 2107 u_int sr; 2108 2109 va &= ~ADDR_POFF; 2110 sr = va_to_sr(pm->pm_sr, va); 2111 ptegidx = va_to_pteg(sr, va); 2112 2113 mtx_lock(&moea_table_mutex); 2114 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2115 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2116 if (pteidx_p) 2117 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2118 break; 2119 } 2120 } 2121 mtx_unlock(&moea_table_mutex); 2122 2123 return (pvo); 2124 } 2125 2126 static struct pte * 2127 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2128 { 2129 struct pte *pt; 2130 2131 /* 2132 * If we haven't been supplied the ptegidx, calculate it. 2133 */ 2134 if (pteidx == -1) { 2135 int ptegidx; 2136 u_int sr; 2137 2138 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2139 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2140 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2141 } 2142 2143 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2144 mtx_lock(&moea_table_mutex); 2145 2146 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2147 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2148 "valid pte index", pvo); 2149 } 2150 2151 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2152 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2153 "pvo but no valid pte", pvo); 2154 } 2155 2156 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2157 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2158 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2159 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2160 } 2161 2162 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2163 != 0) { 2164 panic("moea_pvo_to_pte: pvo %p pte does not match " 2165 "pte %p in moea_pteg_table", pvo, pt); 2166 } 2167 2168 mtx_assert(&moea_table_mutex, MA_OWNED); 2169 return (pt); 2170 } 2171 2172 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2173 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2174 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2175 } 2176 2177 mtx_unlock(&moea_table_mutex); 2178 return (NULL); 2179 } 2180 2181 /* 2182 * XXX: THIS STUFF SHOULD BE IN pte.c? 2183 */ 2184 int 2185 moea_pte_spill(vm_offset_t addr) 2186 { 2187 struct pvo_entry *source_pvo, *victim_pvo; 2188 struct pvo_entry *pvo; 2189 int ptegidx, i, j; 2190 u_int sr; 2191 struct pteg *pteg; 2192 struct pte *pt; 2193 2194 moea_pte_spills++; 2195 2196 sr = mfsrin(addr); 2197 ptegidx = va_to_pteg(sr, addr); 2198 2199 /* 2200 * Have to substitute some entry. Use the primary hash for this. 2201 * Use low bits of timebase as random generator. 2202 */ 2203 pteg = &moea_pteg_table[ptegidx]; 2204 mtx_lock(&moea_table_mutex); 2205 __asm __volatile("mftb %0" : "=r"(i)); 2206 i &= 7; 2207 pt = &pteg->pt[i]; 2208 2209 source_pvo = NULL; 2210 victim_pvo = NULL; 2211 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2212 /* 2213 * We need to find a pvo entry for this address. 2214 */ 2215 if (source_pvo == NULL && 2216 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2217 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2218 /* 2219 * Now found an entry to be spilled into the pteg. 2220 * The PTE is now valid, so we know it's active. 2221 */ 2222 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2223 2224 if (j >= 0) { 2225 PVO_PTEGIDX_SET(pvo, j); 2226 moea_pte_overflow--; 2227 mtx_unlock(&moea_table_mutex); 2228 return (1); 2229 } 2230 2231 source_pvo = pvo; 2232 2233 if (victim_pvo != NULL) 2234 break; 2235 } 2236 2237 /* 2238 * We also need the pvo entry of the victim we are replacing 2239 * so save the R & C bits of the PTE. 2240 */ 2241 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2242 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2243 victim_pvo = pvo; 2244 if (source_pvo != NULL) 2245 break; 2246 } 2247 } 2248 2249 if (source_pvo == NULL) { 2250 mtx_unlock(&moea_table_mutex); 2251 return (0); 2252 } 2253 2254 if (victim_pvo == NULL) { 2255 if ((pt->pte_hi & PTE_HID) == 0) 2256 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2257 "entry", pt); 2258 2259 /* 2260 * If this is a secondary PTE, we need to search it's primary 2261 * pvo bucket for the matching PVO. 2262 */ 2263 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2264 pvo_olink) { 2265 /* 2266 * We also need the pvo entry of the victim we are 2267 * replacing so save the R & C bits of the PTE. 2268 */ 2269 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2270 victim_pvo = pvo; 2271 break; 2272 } 2273 } 2274 2275 if (victim_pvo == NULL) 2276 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2277 "entry", pt); 2278 } 2279 2280 /* 2281 * We are invalidating the TLB entry for the EA we are replacing even 2282 * though it's valid. If we don't, we lose any ref/chg bit changes 2283 * contained in the TLB entry. 2284 */ 2285 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2286 2287 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2288 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2289 2290 PVO_PTEGIDX_CLR(victim_pvo); 2291 PVO_PTEGIDX_SET(source_pvo, i); 2292 moea_pte_replacements++; 2293 2294 mtx_unlock(&moea_table_mutex); 2295 return (1); 2296 } 2297 2298 static __inline struct pvo_entry * 2299 moea_pte_spillable_ident(u_int ptegidx) 2300 { 2301 struct pte *pt; 2302 struct pvo_entry *pvo_walk, *pvo = NULL; 2303 2304 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2305 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2306 continue; 2307 2308 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2309 continue; 2310 2311 pt = moea_pvo_to_pte(pvo_walk, -1); 2312 2313 if (pt == NULL) 2314 continue; 2315 2316 pvo = pvo_walk; 2317 2318 mtx_unlock(&moea_table_mutex); 2319 if (!(pt->pte_lo & PTE_REF)) 2320 return (pvo_walk); 2321 } 2322 2323 return (pvo); 2324 } 2325 2326 static int 2327 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2328 { 2329 struct pte *pt; 2330 struct pvo_entry *victim_pvo; 2331 int i; 2332 int victim_idx; 2333 u_int pteg_bkpidx = ptegidx; 2334 2335 mtx_assert(&moea_table_mutex, MA_OWNED); 2336 2337 /* 2338 * First try primary hash. 2339 */ 2340 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2341 if ((pt->pte_hi & PTE_VALID) == 0) { 2342 pvo_pt->pte_hi &= ~PTE_HID; 2343 moea_pte_set(pt, pvo_pt); 2344 return (i); 2345 } 2346 } 2347 2348 /* 2349 * Now try secondary hash. 2350 */ 2351 ptegidx ^= moea_pteg_mask; 2352 2353 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2354 if ((pt->pte_hi & PTE_VALID) == 0) { 2355 pvo_pt->pte_hi |= PTE_HID; 2356 moea_pte_set(pt, pvo_pt); 2357 return (i); 2358 } 2359 } 2360 2361 /* Try again, but this time try to force a PTE out. */ 2362 ptegidx = pteg_bkpidx; 2363 2364 victim_pvo = moea_pte_spillable_ident(ptegidx); 2365 if (victim_pvo == NULL) { 2366 ptegidx ^= moea_pteg_mask; 2367 victim_pvo = moea_pte_spillable_ident(ptegidx); 2368 } 2369 2370 if (victim_pvo == NULL) { 2371 panic("moea_pte_insert: overflow"); 2372 return (-1); 2373 } 2374 2375 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2376 2377 if (pteg_bkpidx == ptegidx) 2378 pvo_pt->pte_hi &= ~PTE_HID; 2379 else 2380 pvo_pt->pte_hi |= PTE_HID; 2381 2382 /* 2383 * Synchronize the sacrifice PTE with its PVO, then mark both 2384 * invalid. The PVO will be reused when/if the VM system comes 2385 * here after a fault. 2386 */ 2387 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2388 2389 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2390 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2391 2392 /* 2393 * Set the new PTE. 2394 */ 2395 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2396 PVO_PTEGIDX_CLR(victim_pvo); 2397 moea_pte_overflow++; 2398 moea_pte_set(pt, pvo_pt); 2399 2400 return (victim_idx & 7); 2401 } 2402 2403 static boolean_t 2404 moea_query_bit(vm_page_t m, int ptebit) 2405 { 2406 struct pvo_entry *pvo; 2407 struct pte *pt; 2408 2409 rw_assert(&pvh_global_lock, RA_WLOCKED); 2410 if (moea_attr_fetch(m) & ptebit) 2411 return (TRUE); 2412 2413 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2414 2415 /* 2416 * See if we saved the bit off. If so, cache it and return 2417 * success. 2418 */ 2419 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2420 moea_attr_save(m, ptebit); 2421 return (TRUE); 2422 } 2423 } 2424 2425 /* 2426 * No luck, now go through the hard part of looking at the PTEs 2427 * themselves. Sync so that any pending REF/CHG bits are flushed to 2428 * the PTEs. 2429 */ 2430 powerpc_sync(); 2431 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2432 2433 /* 2434 * See if this pvo has a valid PTE. if so, fetch the 2435 * REF/CHG bits from the valid PTE. If the appropriate 2436 * ptebit is set, cache it and return success. 2437 */ 2438 pt = moea_pvo_to_pte(pvo, -1); 2439 if (pt != NULL) { 2440 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2441 mtx_unlock(&moea_table_mutex); 2442 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2443 moea_attr_save(m, ptebit); 2444 return (TRUE); 2445 } 2446 } 2447 } 2448 2449 return (FALSE); 2450 } 2451 2452 static u_int 2453 moea_clear_bit(vm_page_t m, int ptebit) 2454 { 2455 u_int count; 2456 struct pvo_entry *pvo; 2457 struct pte *pt; 2458 2459 rw_assert(&pvh_global_lock, RA_WLOCKED); 2460 2461 /* 2462 * Clear the cached value. 2463 */ 2464 moea_attr_clear(m, ptebit); 2465 2466 /* 2467 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2468 * we can reset the right ones). note that since the pvo entries and 2469 * list heads are accessed via BAT0 and are never placed in the page 2470 * table, we don't have to worry about further accesses setting the 2471 * REF/CHG bits. 2472 */ 2473 powerpc_sync(); 2474 2475 /* 2476 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2477 * valid pte clear the ptebit from the valid pte. 2478 */ 2479 count = 0; 2480 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2481 pt = moea_pvo_to_pte(pvo, -1); 2482 if (pt != NULL) { 2483 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2484 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2485 count++; 2486 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2487 } 2488 mtx_unlock(&moea_table_mutex); 2489 } 2490 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2491 } 2492 2493 return (count); 2494 } 2495 2496 /* 2497 * Return true if the physical range is encompassed by the battable[idx] 2498 */ 2499 static int 2500 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2501 { 2502 u_int prot; 2503 u_int32_t start; 2504 u_int32_t end; 2505 u_int32_t bat_ble; 2506 2507 /* 2508 * Return immediately if not a valid mapping 2509 */ 2510 if (!(battable[idx].batu & BAT_Vs)) 2511 return (EINVAL); 2512 2513 /* 2514 * The BAT entry must be cache-inhibited, guarded, and r/w 2515 * so it can function as an i/o page 2516 */ 2517 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2518 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2519 return (EPERM); 2520 2521 /* 2522 * The address should be within the BAT range. Assume that the 2523 * start address in the BAT has the correct alignment (thus 2524 * not requiring masking) 2525 */ 2526 start = battable[idx].batl & BAT_PBS; 2527 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2528 end = start | (bat_ble << 15) | 0x7fff; 2529 2530 if ((pa < start) || ((pa + size) > end)) 2531 return (ERANGE); 2532 2533 return (0); 2534 } 2535 2536 boolean_t 2537 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2538 { 2539 int i; 2540 2541 /* 2542 * This currently does not work for entries that 2543 * overlap 256M BAT segments. 2544 */ 2545 2546 for(i = 0; i < 16; i++) 2547 if (moea_bat_mapped(i, pa, size) == 0) 2548 return (0); 2549 2550 return (EFAULT); 2551 } 2552 2553 /* 2554 * Map a set of physical memory pages into the kernel virtual 2555 * address space. Return a pointer to where it is mapped. This 2556 * routine is intended to be used for mapping device memory, 2557 * NOT real memory. 2558 */ 2559 void * 2560 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2561 { 2562 2563 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2564 } 2565 2566 void * 2567 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2568 { 2569 vm_offset_t va, tmpva, ppa, offset; 2570 int i; 2571 2572 ppa = trunc_page(pa); 2573 offset = pa & PAGE_MASK; 2574 size = roundup(offset + size, PAGE_SIZE); 2575 2576 /* 2577 * If the physical address lies within a valid BAT table entry, 2578 * return the 1:1 mapping. This currently doesn't work 2579 * for regions that overlap 256M BAT segments. 2580 */ 2581 for (i = 0; i < 16; i++) { 2582 if (moea_bat_mapped(i, pa, size) == 0) 2583 return ((void *) pa); 2584 } 2585 2586 va = kva_alloc(size); 2587 if (!va) 2588 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2589 2590 for (tmpva = va; size > 0;) { 2591 moea_kenter_attr(mmu, tmpva, ppa, ma); 2592 tlbie(tmpva); 2593 size -= PAGE_SIZE; 2594 tmpva += PAGE_SIZE; 2595 ppa += PAGE_SIZE; 2596 } 2597 2598 return ((void *)(va + offset)); 2599 } 2600 2601 void 2602 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2603 { 2604 vm_offset_t base, offset; 2605 2606 /* 2607 * If this is outside kernel virtual space, then it's a 2608 * battable entry and doesn't require unmapping 2609 */ 2610 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2611 base = trunc_page(va); 2612 offset = va & PAGE_MASK; 2613 size = roundup(offset + size, PAGE_SIZE); 2614 kva_free(base, size); 2615 } 2616 } 2617 2618 static void 2619 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2620 { 2621 struct pvo_entry *pvo; 2622 vm_offset_t lim; 2623 vm_paddr_t pa; 2624 vm_size_t len; 2625 2626 PMAP_LOCK(pm); 2627 while (sz > 0) { 2628 lim = round_page(va); 2629 len = MIN(lim - va, sz); 2630 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2631 if (pvo != NULL) { 2632 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2633 (va & ADDR_POFF); 2634 moea_syncicache(pa, len); 2635 } 2636 va += len; 2637 sz -= len; 2638 } 2639 PMAP_UNLOCK(pm); 2640 } 2641 2642 vm_offset_t 2643 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2644 vm_size_t *sz) 2645 { 2646 if (md->md_vaddr == ~0UL) 2647 return (md->md_paddr + ofs); 2648 else 2649 return (md->md_vaddr + ofs); 2650 } 2651 2652 struct pmap_md * 2653 moea_scan_md(mmu_t mmu, struct pmap_md *prev) 2654 { 2655 static struct pmap_md md; 2656 struct pvo_entry *pvo; 2657 vm_offset_t va; 2658 2659 if (dumpsys_minidump) { 2660 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2661 if (prev == NULL) { 2662 /* 1st: kernel .data and .bss. */ 2663 md.md_index = 1; 2664 md.md_vaddr = trunc_page((uintptr_t)_etext); 2665 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2666 return (&md); 2667 } 2668 switch (prev->md_index) { 2669 case 1: 2670 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2671 md.md_index = 2; 2672 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr; 2673 md.md_size = round_page(msgbufp->msg_size); 2674 break; 2675 case 2: 2676 /* 3rd: kernel VM. */ 2677 va = prev->md_vaddr + prev->md_size; 2678 /* Find start of next chunk (from va). */ 2679 while (va < virtual_end) { 2680 /* Don't dump the buffer cache. */ 2681 if (va >= kmi.buffer_sva && 2682 va < kmi.buffer_eva) { 2683 va = kmi.buffer_eva; 2684 continue; 2685 } 2686 pvo = moea_pvo_find_va(kernel_pmap, 2687 va & ~ADDR_POFF, NULL); 2688 if (pvo != NULL && 2689 (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2690 break; 2691 va += PAGE_SIZE; 2692 } 2693 if (va < virtual_end) { 2694 md.md_vaddr = va; 2695 va += PAGE_SIZE; 2696 /* Find last page in chunk. */ 2697 while (va < virtual_end) { 2698 /* Don't run into the buffer cache. */ 2699 if (va == kmi.buffer_sva) 2700 break; 2701 pvo = moea_pvo_find_va(kernel_pmap, 2702 va & ~ADDR_POFF, NULL); 2703 if (pvo == NULL || 2704 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2705 break; 2706 va += PAGE_SIZE; 2707 } 2708 md.md_size = va - md.md_vaddr; 2709 break; 2710 } 2711 md.md_index = 3; 2712 /* FALLTHROUGH */ 2713 default: 2714 return (NULL); 2715 } 2716 } else { /* minidumps */ 2717 mem_regions(&pregions, &pregions_sz, 2718 ®ions, ®ions_sz); 2719 2720 if (prev == NULL) { 2721 /* first physical chunk. */ 2722 md.md_paddr = pregions[0].mr_start; 2723 md.md_size = pregions[0].mr_size; 2724 md.md_vaddr = ~0UL; 2725 md.md_index = 1; 2726 } else if (md.md_index < pregions_sz) { 2727 md.md_paddr = pregions[md.md_index].mr_start; 2728 md.md_size = pregions[md.md_index].mr_size; 2729 md.md_vaddr = ~0UL; 2730 md.md_index++; 2731 } else { 2732 /* There's no next physical chunk. */ 2733 return (NULL); 2734 } 2735 } 2736 2737 return (&md); 2738 } 2739