1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/platform.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/smp.h> 151 #include <machine/sr.h> 152 #include <machine/mmuvar.h> 153 154 #include "mmu_if.h" 155 156 #define MOEA_DEBUG 157 158 #define TODO panic("%s: not implemented", __func__); 159 160 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 161 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 162 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163 164 struct ofw_map { 165 vm_offset_t om_va; 166 vm_size_t om_len; 167 vm_offset_t om_pa; 168 u_int om_mode; 169 }; 170 171 /* 172 * Map of physical memory regions. 173 */ 174 static struct mem_region *regions; 175 static struct mem_region *pregions; 176 static u_int phys_avail_count; 177 static int regions_sz, pregions_sz; 178 static struct ofw_map *translations; 179 180 /* 181 * Lock for the pteg and pvo tables. 182 */ 183 struct mtx moea_table_mutex; 184 struct mtx moea_vsid_mutex; 185 186 /* tlbie instruction synchronization */ 187 static struct mtx tlbie_mtx; 188 189 /* 190 * PTEG data. 191 */ 192 static struct pteg *moea_pteg_table; 193 u_int moea_pteg_count; 194 u_int moea_pteg_mask; 195 196 /* 197 * PVO data. 198 */ 199 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 200 struct pvo_head moea_pvo_kunmanaged = 201 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 202 203 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 204 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 205 206 #define BPVO_POOL_SIZE 32768 207 static struct pvo_entry *moea_bpvo_pool; 208 static int moea_bpvo_pool_index = 0; 209 210 #define VSID_NBPW (sizeof(u_int32_t) * 8) 211 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 212 213 static boolean_t moea_initialized = FALSE; 214 215 /* 216 * Statistics. 217 */ 218 u_int moea_pte_valid = 0; 219 u_int moea_pte_overflow = 0; 220 u_int moea_pte_replacements = 0; 221 u_int moea_pvo_entries = 0; 222 u_int moea_pvo_enter_calls = 0; 223 u_int moea_pvo_remove_calls = 0; 224 u_int moea_pte_spills = 0; 225 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 226 0, ""); 227 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 228 &moea_pte_overflow, 0, ""); 229 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 230 &moea_pte_replacements, 0, ""); 231 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 232 0, ""); 233 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 234 &moea_pvo_enter_calls, 0, ""); 235 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 236 &moea_pvo_remove_calls, 0, ""); 237 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 238 &moea_pte_spills, 0, ""); 239 240 /* 241 * Allocate physical memory for use in moea_bootstrap. 242 */ 243 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 244 245 /* 246 * PTE calls. 247 */ 248 static int moea_pte_insert(u_int, struct pte *); 249 250 /* 251 * PVO calls. 252 */ 253 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 254 vm_offset_t, vm_offset_t, u_int, int); 255 static void moea_pvo_remove(struct pvo_entry *, int); 256 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 257 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 258 259 /* 260 * Utility routines. 261 */ 262 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 263 vm_prot_t, boolean_t); 264 static void moea_syncicache(vm_offset_t, vm_size_t); 265 static boolean_t moea_query_bit(vm_page_t, int); 266 static u_int moea_clear_bit(vm_page_t, int); 267 static void moea_kremove(mmu_t, vm_offset_t); 268 int moea_pte_spill(vm_offset_t); 269 270 /* 271 * Kernel MMU interface 272 */ 273 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 274 void moea_clear_modify(mmu_t, vm_page_t); 275 void moea_clear_reference(mmu_t, vm_page_t); 276 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 277 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_zero_page(mmu_t, vm_page_t); 301 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 302 void moea_zero_page_idle(mmu_t, vm_page_t); 303 void moea_activate(mmu_t, struct thread *); 304 void moea_deactivate(mmu_t, struct thread *); 305 void moea_cpu_bootstrap(mmu_t, int); 306 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 307 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 308 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 309 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 310 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 311 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 312 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 313 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 314 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 315 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 316 317 static mmu_method_t moea_methods[] = { 318 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 319 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 320 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 321 MMUMETHOD(mmu_copy_page, moea_copy_page), 322 MMUMETHOD(mmu_enter, moea_enter), 323 MMUMETHOD(mmu_enter_object, moea_enter_object), 324 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 325 MMUMETHOD(mmu_extract, moea_extract), 326 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 327 MMUMETHOD(mmu_init, moea_init), 328 MMUMETHOD(mmu_is_modified, moea_is_modified), 329 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 330 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 331 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 332 MMUMETHOD(mmu_map, moea_map), 333 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 334 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 335 MMUMETHOD(mmu_pinit, moea_pinit), 336 MMUMETHOD(mmu_pinit0, moea_pinit0), 337 MMUMETHOD(mmu_protect, moea_protect), 338 MMUMETHOD(mmu_qenter, moea_qenter), 339 MMUMETHOD(mmu_qremove, moea_qremove), 340 MMUMETHOD(mmu_release, moea_release), 341 MMUMETHOD(mmu_remove, moea_remove), 342 MMUMETHOD(mmu_remove_all, moea_remove_all), 343 MMUMETHOD(mmu_remove_write, moea_remove_write), 344 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 345 MMUMETHOD(mmu_zero_page, moea_zero_page), 346 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 347 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 348 MMUMETHOD(mmu_activate, moea_activate), 349 MMUMETHOD(mmu_deactivate, moea_deactivate), 350 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 351 352 /* Internal interfaces */ 353 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 354 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 355 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 356 MMUMETHOD(mmu_mapdev, moea_mapdev), 357 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 358 MMUMETHOD(mmu_kextract, moea_kextract), 359 MMUMETHOD(mmu_kenter, moea_kenter), 360 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 361 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 362 363 { 0, 0 } 364 }; 365 366 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 367 368 static __inline uint32_t 369 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 370 { 371 uint32_t pte_lo; 372 int i; 373 374 if (ma != VM_MEMATTR_DEFAULT) { 375 switch (ma) { 376 case VM_MEMATTR_UNCACHEABLE: 377 return (PTE_I | PTE_G); 378 case VM_MEMATTR_WRITE_COMBINING: 379 case VM_MEMATTR_WRITE_BACK: 380 case VM_MEMATTR_PREFETCHABLE: 381 return (PTE_I); 382 case VM_MEMATTR_WRITE_THROUGH: 383 return (PTE_W | PTE_M); 384 } 385 } 386 387 /* 388 * Assume the page is cache inhibited and access is guarded unless 389 * it's in our available memory array. 390 */ 391 pte_lo = PTE_I | PTE_G; 392 for (i = 0; i < pregions_sz; i++) { 393 if ((pa >= pregions[i].mr_start) && 394 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 395 pte_lo = PTE_M; 396 break; 397 } 398 } 399 400 return pte_lo; 401 } 402 403 static void 404 tlbie(vm_offset_t va) 405 { 406 407 mtx_lock_spin(&tlbie_mtx); 408 __asm __volatile("ptesync"); 409 __asm __volatile("tlbie %0" :: "r"(va)); 410 __asm __volatile("eieio; tlbsync; ptesync"); 411 mtx_unlock_spin(&tlbie_mtx); 412 } 413 414 static void 415 tlbia(void) 416 { 417 vm_offset_t va; 418 419 for (va = 0; va < 0x00040000; va += 0x00001000) { 420 __asm __volatile("tlbie %0" :: "r"(va)); 421 powerpc_sync(); 422 } 423 __asm __volatile("tlbsync"); 424 powerpc_sync(); 425 } 426 427 static __inline int 428 va_to_sr(u_int *sr, vm_offset_t va) 429 { 430 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 431 } 432 433 static __inline u_int 434 va_to_pteg(u_int sr, vm_offset_t addr) 435 { 436 u_int hash; 437 438 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 439 ADDR_PIDX_SHFT); 440 return (hash & moea_pteg_mask); 441 } 442 443 static __inline struct pvo_head * 444 vm_page_to_pvoh(vm_page_t m) 445 { 446 447 return (&m->md.mdpg_pvoh); 448 } 449 450 static __inline void 451 moea_attr_clear(vm_page_t m, int ptebit) 452 { 453 454 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 455 m->md.mdpg_attrs &= ~ptebit; 456 } 457 458 static __inline int 459 moea_attr_fetch(vm_page_t m) 460 { 461 462 return (m->md.mdpg_attrs); 463 } 464 465 static __inline void 466 moea_attr_save(vm_page_t m, int ptebit) 467 { 468 469 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 470 m->md.mdpg_attrs |= ptebit; 471 } 472 473 static __inline int 474 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 475 { 476 if (pt->pte_hi == pvo_pt->pte_hi) 477 return (1); 478 479 return (0); 480 } 481 482 static __inline int 483 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 484 { 485 return (pt->pte_hi & ~PTE_VALID) == 486 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 487 ((va >> ADDR_API_SHFT) & PTE_API) | which); 488 } 489 490 static __inline void 491 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 492 { 493 494 mtx_assert(&moea_table_mutex, MA_OWNED); 495 496 /* 497 * Construct a PTE. Default to IMB initially. Valid bit only gets 498 * set when the real pte is set in memory. 499 * 500 * Note: Don't set the valid bit for correct operation of tlb update. 501 */ 502 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 503 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 504 pt->pte_lo = pte_lo; 505 } 506 507 static __inline void 508 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 509 { 510 511 mtx_assert(&moea_table_mutex, MA_OWNED); 512 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 513 } 514 515 static __inline void 516 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 517 { 518 519 mtx_assert(&moea_table_mutex, MA_OWNED); 520 521 /* 522 * As shown in Section 7.6.3.2.3 523 */ 524 pt->pte_lo &= ~ptebit; 525 tlbie(va); 526 } 527 528 static __inline void 529 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 530 { 531 532 mtx_assert(&moea_table_mutex, MA_OWNED); 533 pvo_pt->pte_hi |= PTE_VALID; 534 535 /* 536 * Update the PTE as defined in section 7.6.3.1. 537 * Note that the REF/CHG bits are from pvo_pt and thus should havce 538 * been saved so this routine can restore them (if desired). 539 */ 540 pt->pte_lo = pvo_pt->pte_lo; 541 powerpc_sync(); 542 pt->pte_hi = pvo_pt->pte_hi; 543 powerpc_sync(); 544 moea_pte_valid++; 545 } 546 547 static __inline void 548 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 549 { 550 551 mtx_assert(&moea_table_mutex, MA_OWNED); 552 pvo_pt->pte_hi &= ~PTE_VALID; 553 554 /* 555 * Force the reg & chg bits back into the PTEs. 556 */ 557 powerpc_sync(); 558 559 /* 560 * Invalidate the pte. 561 */ 562 pt->pte_hi &= ~PTE_VALID; 563 564 tlbie(va); 565 566 /* 567 * Save the reg & chg bits. 568 */ 569 moea_pte_synch(pt, pvo_pt); 570 moea_pte_valid--; 571 } 572 573 static __inline void 574 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 575 { 576 577 /* 578 * Invalidate the PTE 579 */ 580 moea_pte_unset(pt, pvo_pt, va); 581 moea_pte_set(pt, pvo_pt); 582 } 583 584 /* 585 * Quick sort callout for comparing memory regions. 586 */ 587 static int om_cmp(const void *a, const void *b); 588 589 static int 590 om_cmp(const void *a, const void *b) 591 { 592 const struct ofw_map *mapa; 593 const struct ofw_map *mapb; 594 595 mapa = a; 596 mapb = b; 597 if (mapa->om_pa < mapb->om_pa) 598 return (-1); 599 else if (mapa->om_pa > mapb->om_pa) 600 return (1); 601 else 602 return (0); 603 } 604 605 void 606 moea_cpu_bootstrap(mmu_t mmup, int ap) 607 { 608 u_int sdr; 609 int i; 610 611 if (ap) { 612 powerpc_sync(); 613 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 614 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 615 isync(); 616 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 617 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 618 isync(); 619 } 620 621 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 622 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 623 isync(); 624 625 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 626 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 627 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 628 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 629 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 630 isync(); 631 632 for (i = 0; i < 16; i++) 633 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 634 powerpc_sync(); 635 636 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 637 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 638 isync(); 639 640 tlbia(); 641 } 642 643 void 644 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 645 { 646 ihandle_t mmui; 647 phandle_t chosen, mmu; 648 int sz; 649 int i, j; 650 vm_size_t size, physsz, hwphyssz; 651 vm_offset_t pa, va, off; 652 void *dpcpu; 653 register_t msr; 654 655 /* 656 * Set up BAT0 to map the lowest 256 MB area 657 */ 658 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 659 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 660 661 /* 662 * Map PCI memory space. 663 */ 664 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 665 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 666 667 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 668 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 669 670 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 671 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 672 673 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 674 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 675 676 /* 677 * Map obio devices. 678 */ 679 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 680 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 681 682 /* 683 * Use an IBAT and a DBAT to map the bottom segment of memory 684 * where we are. Turn off instruction relocation temporarily 685 * to prevent faults while reprogramming the IBAT. 686 */ 687 msr = mfmsr(); 688 mtmsr(msr & ~PSL_IR); 689 __asm (".balign 32; \n" 690 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 691 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 692 :: "r"(battable[0].batu), "r"(battable[0].batl)); 693 mtmsr(msr); 694 695 /* map pci space */ 696 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 697 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 698 isync(); 699 700 /* set global direct map flag */ 701 hw_direct_map = 1; 702 703 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 704 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 705 706 for (i = 0; i < pregions_sz; i++) { 707 vm_offset_t pa; 708 vm_offset_t end; 709 710 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 711 pregions[i].mr_start, 712 pregions[i].mr_start + pregions[i].mr_size, 713 pregions[i].mr_size); 714 /* 715 * Install entries into the BAT table to allow all 716 * of physmem to be convered by on-demand BAT entries. 717 * The loop will sometimes set the same battable element 718 * twice, but that's fine since they won't be used for 719 * a while yet. 720 */ 721 pa = pregions[i].mr_start & 0xf0000000; 722 end = pregions[i].mr_start + pregions[i].mr_size; 723 do { 724 u_int n = pa >> ADDR_SR_SHFT; 725 726 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 727 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 728 pa += SEGMENT_LENGTH; 729 } while (pa < end); 730 } 731 732 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 733 panic("moea_bootstrap: phys_avail too small"); 734 735 phys_avail_count = 0; 736 physsz = 0; 737 hwphyssz = 0; 738 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 739 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 740 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 741 regions[i].mr_start + regions[i].mr_size, 742 regions[i].mr_size); 743 if (hwphyssz != 0 && 744 (physsz + regions[i].mr_size) >= hwphyssz) { 745 if (physsz < hwphyssz) { 746 phys_avail[j] = regions[i].mr_start; 747 phys_avail[j + 1] = regions[i].mr_start + 748 hwphyssz - physsz; 749 physsz = hwphyssz; 750 phys_avail_count++; 751 } 752 break; 753 } 754 phys_avail[j] = regions[i].mr_start; 755 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 756 phys_avail_count++; 757 physsz += regions[i].mr_size; 758 } 759 physmem = btoc(physsz); 760 761 /* 762 * Allocate PTEG table. 763 */ 764 #ifdef PTEGCOUNT 765 moea_pteg_count = PTEGCOUNT; 766 #else 767 moea_pteg_count = 0x1000; 768 769 while (moea_pteg_count < physmem) 770 moea_pteg_count <<= 1; 771 772 moea_pteg_count >>= 1; 773 #endif /* PTEGCOUNT */ 774 775 size = moea_pteg_count * sizeof(struct pteg); 776 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 777 size); 778 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 779 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 780 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 781 moea_pteg_mask = moea_pteg_count - 1; 782 783 /* 784 * Allocate pv/overflow lists. 785 */ 786 size = sizeof(struct pvo_head) * moea_pteg_count; 787 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 788 PAGE_SIZE); 789 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 790 for (i = 0; i < moea_pteg_count; i++) 791 LIST_INIT(&moea_pvo_table[i]); 792 793 /* 794 * Initialize the lock that synchronizes access to the pteg and pvo 795 * tables. 796 */ 797 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 798 MTX_RECURSE); 799 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 800 801 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 802 803 /* 804 * Initialise the unmanaged pvo pool. 805 */ 806 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 807 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 808 moea_bpvo_pool_index = 0; 809 810 /* 811 * Make sure kernel vsid is allocated as well as VSID 0. 812 */ 813 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 814 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 815 moea_vsid_bitmap[0] |= 1; 816 817 /* 818 * Initialize the kernel pmap (which is statically allocated). 819 */ 820 PMAP_LOCK_INIT(kernel_pmap); 821 for (i = 0; i < 16; i++) 822 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 823 kernel_pmap->pm_active = ~0; 824 825 /* 826 * Set up the Open Firmware mappings 827 */ 828 if ((chosen = OF_finddevice("/chosen")) == -1) 829 panic("moea_bootstrap: can't find /chosen"); 830 OF_getprop(chosen, "mmu", &mmui, 4); 831 if ((mmu = OF_instance_to_package(mmui)) == -1) 832 panic("moea_bootstrap: can't get mmu package"); 833 if ((sz = OF_getproplen(mmu, "translations")) == -1) 834 panic("moea_bootstrap: can't get ofw translation count"); 835 translations = NULL; 836 for (i = 0; phys_avail[i] != 0; i += 2) { 837 if (phys_avail[i + 1] >= sz) { 838 translations = (struct ofw_map *)phys_avail[i]; 839 break; 840 } 841 } 842 if (translations == NULL) 843 panic("moea_bootstrap: no space to copy translations"); 844 bzero(translations, sz); 845 if (OF_getprop(mmu, "translations", translations, sz) == -1) 846 panic("moea_bootstrap: can't get ofw translations"); 847 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 848 sz /= sizeof(*translations); 849 qsort(translations, sz, sizeof (*translations), om_cmp); 850 for (i = 0; i < sz; i++) { 851 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 852 translations[i].om_pa, translations[i].om_va, 853 translations[i].om_len); 854 855 /* 856 * If the mapping is 1:1, let the RAM and device on-demand 857 * BAT tables take care of the translation. 858 */ 859 if (translations[i].om_va == translations[i].om_pa) 860 continue; 861 862 /* Enter the pages */ 863 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) 864 moea_kenter(mmup, translations[i].om_va + off, 865 translations[i].om_pa + off); 866 } 867 868 /* 869 * Calculate the last available physical address. 870 */ 871 for (i = 0; phys_avail[i + 2] != 0; i += 2) 872 ; 873 Maxmem = powerpc_btop(phys_avail[i + 1]); 874 875 moea_cpu_bootstrap(mmup,0); 876 877 pmap_bootstrapped++; 878 879 /* 880 * Set the start and end of kva. 881 */ 882 virtual_avail = VM_MIN_KERNEL_ADDRESS; 883 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 884 885 /* 886 * Allocate a kernel stack with a guard page for thread0 and map it 887 * into the kernel page map. 888 */ 889 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 890 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 891 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 892 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 893 thread0.td_kstack = va; 894 thread0.td_kstack_pages = KSTACK_PAGES; 895 for (i = 0; i < KSTACK_PAGES; i++) { 896 moea_kenter(mmup, va, pa); 897 pa += PAGE_SIZE; 898 va += PAGE_SIZE; 899 } 900 901 /* 902 * Allocate virtual address space for the message buffer. 903 */ 904 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 905 msgbufp = (struct msgbuf *)virtual_avail; 906 va = virtual_avail; 907 virtual_avail += round_page(msgbufsize); 908 while (va < virtual_avail) { 909 moea_kenter(mmup, va, pa); 910 pa += PAGE_SIZE; 911 va += PAGE_SIZE; 912 } 913 914 /* 915 * Allocate virtual address space for the dynamic percpu area. 916 */ 917 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 918 dpcpu = (void *)virtual_avail; 919 va = virtual_avail; 920 virtual_avail += DPCPU_SIZE; 921 while (va < virtual_avail) { 922 moea_kenter(mmup, va, pa); 923 pa += PAGE_SIZE; 924 va += PAGE_SIZE; 925 } 926 dpcpu_init(dpcpu, 0); 927 } 928 929 /* 930 * Activate a user pmap. The pmap must be activated before it's address 931 * space can be accessed in any way. 932 */ 933 void 934 moea_activate(mmu_t mmu, struct thread *td) 935 { 936 pmap_t pm, pmr; 937 938 /* 939 * Load all the data we need up front to encourage the compiler to 940 * not issue any loads while we have interrupts disabled below. 941 */ 942 pm = &td->td_proc->p_vmspace->vm_pmap; 943 pmr = pm->pmap_phys; 944 945 pm->pm_active |= PCPU_GET(cpumask); 946 PCPU_SET(curpmap, pmr); 947 } 948 949 void 950 moea_deactivate(mmu_t mmu, struct thread *td) 951 { 952 pmap_t pm; 953 954 pm = &td->td_proc->p_vmspace->vm_pmap; 955 pm->pm_active &= ~PCPU_GET(cpumask); 956 PCPU_SET(curpmap, NULL); 957 } 958 959 void 960 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 961 { 962 struct pvo_entry *pvo; 963 964 PMAP_LOCK(pm); 965 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 966 967 if (pvo != NULL) { 968 if (wired) { 969 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 970 pm->pm_stats.wired_count++; 971 pvo->pvo_vaddr |= PVO_WIRED; 972 } else { 973 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 974 pm->pm_stats.wired_count--; 975 pvo->pvo_vaddr &= ~PVO_WIRED; 976 } 977 } 978 PMAP_UNLOCK(pm); 979 } 980 981 void 982 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 983 { 984 vm_offset_t dst; 985 vm_offset_t src; 986 987 dst = VM_PAGE_TO_PHYS(mdst); 988 src = VM_PAGE_TO_PHYS(msrc); 989 990 kcopy((void *)src, (void *)dst, PAGE_SIZE); 991 } 992 993 /* 994 * Zero a page of physical memory by temporarily mapping it into the tlb. 995 */ 996 void 997 moea_zero_page(mmu_t mmu, vm_page_t m) 998 { 999 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1000 void *va = (void *)pa; 1001 1002 bzero(va, PAGE_SIZE); 1003 } 1004 1005 void 1006 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1007 { 1008 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1009 void *va = (void *)(pa + off); 1010 1011 bzero(va, size); 1012 } 1013 1014 void 1015 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1016 { 1017 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1018 void *va = (void *)pa; 1019 1020 bzero(va, PAGE_SIZE); 1021 } 1022 1023 /* 1024 * Map the given physical page at the specified virtual address in the 1025 * target pmap with the protection requested. If specified the page 1026 * will be wired down. 1027 */ 1028 void 1029 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1030 boolean_t wired) 1031 { 1032 1033 vm_page_lock_queues(); 1034 PMAP_LOCK(pmap); 1035 moea_enter_locked(pmap, va, m, prot, wired); 1036 vm_page_unlock_queues(); 1037 PMAP_UNLOCK(pmap); 1038 } 1039 1040 /* 1041 * Map the given physical page at the specified virtual address in the 1042 * target pmap with the protection requested. If specified the page 1043 * will be wired down. 1044 * 1045 * The page queues and pmap must be locked. 1046 */ 1047 static void 1048 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1049 boolean_t wired) 1050 { 1051 struct pvo_head *pvo_head; 1052 uma_zone_t zone; 1053 vm_page_t pg; 1054 u_int pte_lo, pvo_flags, was_exec; 1055 int error; 1056 1057 if (!moea_initialized) { 1058 pvo_head = &moea_pvo_kunmanaged; 1059 zone = moea_upvo_zone; 1060 pvo_flags = 0; 1061 pg = NULL; 1062 was_exec = PTE_EXEC; 1063 } else { 1064 pvo_head = vm_page_to_pvoh(m); 1065 pg = m; 1066 zone = moea_mpvo_zone; 1067 pvo_flags = PVO_MANAGED; 1068 was_exec = 0; 1069 } 1070 if (pmap_bootstrapped) 1071 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1072 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1073 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1074 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1075 ("moea_enter_locked: page %p is not busy", m)); 1076 1077 /* XXX change the pvo head for fake pages */ 1078 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1079 pvo_flags &= ~PVO_MANAGED; 1080 pvo_head = &moea_pvo_kunmanaged; 1081 zone = moea_upvo_zone; 1082 } 1083 1084 /* 1085 * If this is a managed page, and it's the first reference to the page, 1086 * clear the execness of the page. Otherwise fetch the execness. 1087 */ 1088 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1089 if (LIST_EMPTY(pvo_head)) { 1090 moea_attr_clear(pg, PTE_EXEC); 1091 } else { 1092 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1093 } 1094 } 1095 1096 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1097 1098 if (prot & VM_PROT_WRITE) { 1099 pte_lo |= PTE_BW; 1100 if (pmap_bootstrapped && 1101 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1102 vm_page_flag_set(m, PG_WRITEABLE); 1103 } else 1104 pte_lo |= PTE_BR; 1105 1106 if (prot & VM_PROT_EXECUTE) 1107 pvo_flags |= PVO_EXECUTABLE; 1108 1109 if (wired) 1110 pvo_flags |= PVO_WIRED; 1111 1112 if ((m->flags & PG_FICTITIOUS) != 0) 1113 pvo_flags |= PVO_FAKE; 1114 1115 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1116 pte_lo, pvo_flags); 1117 1118 /* 1119 * Flush the real page from the instruction cache if this page is 1120 * mapped executable and cacheable and was not previously mapped (or 1121 * was not mapped executable). 1122 */ 1123 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1124 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1125 /* 1126 * Flush the real memory from the cache. 1127 */ 1128 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1129 if (pg != NULL) 1130 moea_attr_save(pg, PTE_EXEC); 1131 } 1132 1133 /* XXX syncicache always until problems are sorted */ 1134 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1135 } 1136 1137 /* 1138 * Maps a sequence of resident pages belonging to the same object. 1139 * The sequence begins with the given page m_start. This page is 1140 * mapped at the given virtual address start. Each subsequent page is 1141 * mapped at a virtual address that is offset from start by the same 1142 * amount as the page is offset from m_start within the object. The 1143 * last page in the sequence is the page with the largest offset from 1144 * m_start that can be mapped at a virtual address less than the given 1145 * virtual address end. Not every virtual page between start and end 1146 * is mapped; only those for which a resident page exists with the 1147 * corresponding offset from m_start are mapped. 1148 */ 1149 void 1150 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1151 vm_page_t m_start, vm_prot_t prot) 1152 { 1153 vm_page_t m; 1154 vm_pindex_t diff, psize; 1155 1156 psize = atop(end - start); 1157 m = m_start; 1158 vm_page_lock_queues(); 1159 PMAP_LOCK(pm); 1160 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1161 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1162 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1163 m = TAILQ_NEXT(m, listq); 1164 } 1165 vm_page_unlock_queues(); 1166 PMAP_UNLOCK(pm); 1167 } 1168 1169 void 1170 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1171 vm_prot_t prot) 1172 { 1173 1174 vm_page_lock_queues(); 1175 PMAP_LOCK(pm); 1176 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1177 FALSE); 1178 vm_page_unlock_queues(); 1179 PMAP_UNLOCK(pm); 1180 } 1181 1182 vm_paddr_t 1183 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1184 { 1185 struct pvo_entry *pvo; 1186 vm_paddr_t pa; 1187 1188 PMAP_LOCK(pm); 1189 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1190 if (pvo == NULL) 1191 pa = 0; 1192 else 1193 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1194 PMAP_UNLOCK(pm); 1195 return (pa); 1196 } 1197 1198 /* 1199 * Atomically extract and hold the physical page with the given 1200 * pmap and virtual address pair if that mapping permits the given 1201 * protection. 1202 */ 1203 vm_page_t 1204 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1205 { 1206 struct pvo_entry *pvo; 1207 vm_page_t m; 1208 vm_paddr_t pa; 1209 1210 m = NULL; 1211 pa = 0; 1212 PMAP_LOCK(pmap); 1213 retry: 1214 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1215 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1216 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1217 (prot & VM_PROT_WRITE) == 0)) { 1218 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1219 goto retry; 1220 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1221 vm_page_hold(m); 1222 } 1223 PA_UNLOCK_COND(pa); 1224 PMAP_UNLOCK(pmap); 1225 return (m); 1226 } 1227 1228 void 1229 moea_init(mmu_t mmu) 1230 { 1231 1232 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1233 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1234 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1235 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1236 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1237 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1238 moea_initialized = TRUE; 1239 } 1240 1241 boolean_t 1242 moea_is_referenced(mmu_t mmu, vm_page_t m) 1243 { 1244 1245 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1246 ("moea_is_referenced: page %p is not managed", m)); 1247 return (moea_query_bit(m, PTE_REF)); 1248 } 1249 1250 boolean_t 1251 moea_is_modified(mmu_t mmu, vm_page_t m) 1252 { 1253 1254 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1255 ("moea_is_modified: page %p is not managed", m)); 1256 1257 /* 1258 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1259 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1260 * is clear, no PTEs can have PTE_CHG set. 1261 */ 1262 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1263 if ((m->oflags & VPO_BUSY) == 0 && 1264 (m->flags & PG_WRITEABLE) == 0) 1265 return (FALSE); 1266 return (moea_query_bit(m, PTE_CHG)); 1267 } 1268 1269 boolean_t 1270 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1271 { 1272 struct pvo_entry *pvo; 1273 boolean_t rv; 1274 1275 PMAP_LOCK(pmap); 1276 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1277 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1278 PMAP_UNLOCK(pmap); 1279 return (rv); 1280 } 1281 1282 void 1283 moea_clear_reference(mmu_t mmu, vm_page_t m) 1284 { 1285 1286 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1287 ("moea_clear_reference: page %p is not managed", m)); 1288 moea_clear_bit(m, PTE_REF); 1289 } 1290 1291 void 1292 moea_clear_modify(mmu_t mmu, vm_page_t m) 1293 { 1294 1295 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1296 ("moea_clear_modify: page %p is not managed", m)); 1297 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1298 KASSERT((m->oflags & VPO_BUSY) == 0, 1299 ("moea_clear_modify: page %p is busy", m)); 1300 1301 /* 1302 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1303 * set. If the object containing the page is locked and the page is 1304 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1305 */ 1306 if ((m->flags & PG_WRITEABLE) == 0) 1307 return; 1308 moea_clear_bit(m, PTE_CHG); 1309 } 1310 1311 /* 1312 * Clear the write and modified bits in each of the given page's mappings. 1313 */ 1314 void 1315 moea_remove_write(mmu_t mmu, vm_page_t m) 1316 { 1317 struct pvo_entry *pvo; 1318 struct pte *pt; 1319 pmap_t pmap; 1320 u_int lo; 1321 1322 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1323 ("moea_remove_write: page %p is not managed", m)); 1324 1325 /* 1326 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1327 * another thread while the object is locked. Thus, if PG_WRITEABLE 1328 * is clear, no page table entries need updating. 1329 */ 1330 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1331 if ((m->oflags & VPO_BUSY) == 0 && 1332 (m->flags & PG_WRITEABLE) == 0) 1333 return; 1334 vm_page_lock_queues(); 1335 lo = moea_attr_fetch(m); 1336 powerpc_sync(); 1337 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1338 pmap = pvo->pvo_pmap; 1339 PMAP_LOCK(pmap); 1340 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1341 pt = moea_pvo_to_pte(pvo, -1); 1342 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1343 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1344 if (pt != NULL) { 1345 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1346 lo |= pvo->pvo_pte.pte.pte_lo; 1347 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1348 moea_pte_change(pt, &pvo->pvo_pte.pte, 1349 pvo->pvo_vaddr); 1350 mtx_unlock(&moea_table_mutex); 1351 } 1352 } 1353 PMAP_UNLOCK(pmap); 1354 } 1355 if ((lo & PTE_CHG) != 0) { 1356 moea_attr_clear(m, PTE_CHG); 1357 vm_page_dirty(m); 1358 } 1359 vm_page_flag_clear(m, PG_WRITEABLE); 1360 vm_page_unlock_queues(); 1361 } 1362 1363 /* 1364 * moea_ts_referenced: 1365 * 1366 * Return a count of reference bits for a page, clearing those bits. 1367 * It is not necessary for every reference bit to be cleared, but it 1368 * is necessary that 0 only be returned when there are truly no 1369 * reference bits set. 1370 * 1371 * XXX: The exact number of bits to check and clear is a matter that 1372 * should be tested and standardized at some point in the future for 1373 * optimal aging of shared pages. 1374 */ 1375 boolean_t 1376 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1377 { 1378 1379 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1380 ("moea_ts_referenced: page %p is not managed", m)); 1381 return (moea_clear_bit(m, PTE_REF)); 1382 } 1383 1384 /* 1385 * Modify the WIMG settings of all mappings for a page. 1386 */ 1387 void 1388 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1389 { 1390 struct pvo_entry *pvo; 1391 struct pvo_head *pvo_head; 1392 struct pte *pt; 1393 pmap_t pmap; 1394 u_int lo; 1395 1396 if (m->flags & PG_FICTITIOUS) { 1397 m->md.mdpg_cache_attrs = ma; 1398 return; 1399 } 1400 1401 vm_page_lock_queues(); 1402 pvo_head = vm_page_to_pvoh(m); 1403 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1404 1405 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1406 pmap = pvo->pvo_pmap; 1407 PMAP_LOCK(pmap); 1408 pt = moea_pvo_to_pte(pvo, -1); 1409 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1410 pvo->pvo_pte.pte.pte_lo |= lo; 1411 if (pt != NULL) { 1412 moea_pte_change(pt, &pvo->pvo_pte.pte, 1413 pvo->pvo_vaddr); 1414 if (pvo->pvo_pmap == kernel_pmap) 1415 isync(); 1416 } 1417 mtx_unlock(&moea_table_mutex); 1418 PMAP_UNLOCK(pmap); 1419 } 1420 m->md.mdpg_cache_attrs = ma; 1421 vm_page_unlock_queues(); 1422 } 1423 1424 /* 1425 * Map a wired page into kernel virtual address space. 1426 */ 1427 void 1428 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1429 { 1430 1431 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1432 } 1433 1434 void 1435 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1436 { 1437 u_int pte_lo; 1438 int error; 1439 1440 #if 0 1441 if (va < VM_MIN_KERNEL_ADDRESS) 1442 panic("moea_kenter: attempt to enter non-kernel address %#x", 1443 va); 1444 #endif 1445 1446 pte_lo = moea_calc_wimg(pa, ma); 1447 1448 PMAP_LOCK(kernel_pmap); 1449 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1450 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1451 1452 if (error != 0 && error != ENOENT) 1453 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1454 pa, error); 1455 1456 /* 1457 * Flush the real memory from the instruction cache. 1458 */ 1459 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1460 moea_syncicache(pa, PAGE_SIZE); 1461 } 1462 PMAP_UNLOCK(kernel_pmap); 1463 } 1464 1465 /* 1466 * Extract the physical page address associated with the given kernel virtual 1467 * address. 1468 */ 1469 vm_offset_t 1470 moea_kextract(mmu_t mmu, vm_offset_t va) 1471 { 1472 struct pvo_entry *pvo; 1473 vm_paddr_t pa; 1474 1475 /* 1476 * Allow direct mappings on 32-bit OEA 1477 */ 1478 if (va < VM_MIN_KERNEL_ADDRESS) { 1479 return (va); 1480 } 1481 1482 PMAP_LOCK(kernel_pmap); 1483 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1484 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1485 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1486 PMAP_UNLOCK(kernel_pmap); 1487 return (pa); 1488 } 1489 1490 /* 1491 * Remove a wired page from kernel virtual address space. 1492 */ 1493 void 1494 moea_kremove(mmu_t mmu, vm_offset_t va) 1495 { 1496 1497 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1498 } 1499 1500 /* 1501 * Map a range of physical addresses into kernel virtual address space. 1502 * 1503 * The value passed in *virt is a suggested virtual address for the mapping. 1504 * Architectures which can support a direct-mapped physical to virtual region 1505 * can return the appropriate address within that region, leaving '*virt' 1506 * unchanged. We cannot and therefore do not; *virt is updated with the 1507 * first usable address after the mapped region. 1508 */ 1509 vm_offset_t 1510 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1511 vm_offset_t pa_end, int prot) 1512 { 1513 vm_offset_t sva, va; 1514 1515 sva = *virt; 1516 va = sva; 1517 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1518 moea_kenter(mmu, va, pa_start); 1519 *virt = va; 1520 return (sva); 1521 } 1522 1523 /* 1524 * Returns true if the pmap's pv is one of the first 1525 * 16 pvs linked to from this page. This count may 1526 * be changed upwards or downwards in the future; it 1527 * is only necessary that true be returned for a small 1528 * subset of pmaps for proper page aging. 1529 */ 1530 boolean_t 1531 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1532 { 1533 int loops; 1534 struct pvo_entry *pvo; 1535 boolean_t rv; 1536 1537 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1538 ("moea_page_exists_quick: page %p is not managed", m)); 1539 loops = 0; 1540 rv = FALSE; 1541 vm_page_lock_queues(); 1542 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1543 if (pvo->pvo_pmap == pmap) { 1544 rv = TRUE; 1545 break; 1546 } 1547 if (++loops >= 16) 1548 break; 1549 } 1550 vm_page_unlock_queues(); 1551 return (rv); 1552 } 1553 1554 /* 1555 * Return the number of managed mappings to the given physical page 1556 * that are wired. 1557 */ 1558 int 1559 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1560 { 1561 struct pvo_entry *pvo; 1562 int count; 1563 1564 count = 0; 1565 if ((m->flags & PG_FICTITIOUS) != 0) 1566 return (count); 1567 vm_page_lock_queues(); 1568 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1569 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1570 count++; 1571 vm_page_unlock_queues(); 1572 return (count); 1573 } 1574 1575 static u_int moea_vsidcontext; 1576 1577 void 1578 moea_pinit(mmu_t mmu, pmap_t pmap) 1579 { 1580 int i, mask; 1581 u_int entropy; 1582 1583 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1584 PMAP_LOCK_INIT(pmap); 1585 1586 entropy = 0; 1587 __asm __volatile("mftb %0" : "=r"(entropy)); 1588 1589 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1590 == NULL) { 1591 pmap->pmap_phys = pmap; 1592 } 1593 1594 1595 mtx_lock(&moea_vsid_mutex); 1596 /* 1597 * Allocate some segment registers for this pmap. 1598 */ 1599 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1600 u_int hash, n; 1601 1602 /* 1603 * Create a new value by mutiplying by a prime and adding in 1604 * entropy from the timebase register. This is to make the 1605 * VSID more random so that the PT hash function collides 1606 * less often. (Note that the prime casues gcc to do shifts 1607 * instead of a multiply.) 1608 */ 1609 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1610 hash = moea_vsidcontext & (NPMAPS - 1); 1611 if (hash == 0) /* 0 is special, avoid it */ 1612 continue; 1613 n = hash >> 5; 1614 mask = 1 << (hash & (VSID_NBPW - 1)); 1615 hash = (moea_vsidcontext & 0xfffff); 1616 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1617 /* anything free in this bucket? */ 1618 if (moea_vsid_bitmap[n] == 0xffffffff) { 1619 entropy = (moea_vsidcontext >> 20); 1620 continue; 1621 } 1622 i = ffs(~moea_vsid_bitmap[n]) - 1; 1623 mask = 1 << i; 1624 hash &= 0xfffff & ~(VSID_NBPW - 1); 1625 hash |= i; 1626 } 1627 moea_vsid_bitmap[n] |= mask; 1628 for (i = 0; i < 16; i++) 1629 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1630 mtx_unlock(&moea_vsid_mutex); 1631 return; 1632 } 1633 1634 mtx_unlock(&moea_vsid_mutex); 1635 panic("moea_pinit: out of segments"); 1636 } 1637 1638 /* 1639 * Initialize the pmap associated with process 0. 1640 */ 1641 void 1642 moea_pinit0(mmu_t mmu, pmap_t pm) 1643 { 1644 1645 moea_pinit(mmu, pm); 1646 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1647 } 1648 1649 /* 1650 * Set the physical protection on the specified range of this map as requested. 1651 */ 1652 void 1653 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1654 vm_prot_t prot) 1655 { 1656 struct pvo_entry *pvo; 1657 struct pte *pt; 1658 int pteidx; 1659 1660 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1661 ("moea_protect: non current pmap")); 1662 1663 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1664 moea_remove(mmu, pm, sva, eva); 1665 return; 1666 } 1667 1668 vm_page_lock_queues(); 1669 PMAP_LOCK(pm); 1670 for (; sva < eva; sva += PAGE_SIZE) { 1671 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1672 if (pvo == NULL) 1673 continue; 1674 1675 if ((prot & VM_PROT_EXECUTE) == 0) 1676 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1677 1678 /* 1679 * Grab the PTE pointer before we diddle with the cached PTE 1680 * copy. 1681 */ 1682 pt = moea_pvo_to_pte(pvo, pteidx); 1683 /* 1684 * Change the protection of the page. 1685 */ 1686 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1687 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1688 1689 /* 1690 * If the PVO is in the page table, update that pte as well. 1691 */ 1692 if (pt != NULL) { 1693 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1694 mtx_unlock(&moea_table_mutex); 1695 } 1696 } 1697 vm_page_unlock_queues(); 1698 PMAP_UNLOCK(pm); 1699 } 1700 1701 /* 1702 * Map a list of wired pages into kernel virtual address space. This is 1703 * intended for temporary mappings which do not need page modification or 1704 * references recorded. Existing mappings in the region are overwritten. 1705 */ 1706 void 1707 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1708 { 1709 vm_offset_t va; 1710 1711 va = sva; 1712 while (count-- > 0) { 1713 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1714 va += PAGE_SIZE; 1715 m++; 1716 } 1717 } 1718 1719 /* 1720 * Remove page mappings from kernel virtual address space. Intended for 1721 * temporary mappings entered by moea_qenter. 1722 */ 1723 void 1724 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1725 { 1726 vm_offset_t va; 1727 1728 va = sva; 1729 while (count-- > 0) { 1730 moea_kremove(mmu, va); 1731 va += PAGE_SIZE; 1732 } 1733 } 1734 1735 void 1736 moea_release(mmu_t mmu, pmap_t pmap) 1737 { 1738 int idx, mask; 1739 1740 /* 1741 * Free segment register's VSID 1742 */ 1743 if (pmap->pm_sr[0] == 0) 1744 panic("moea_release"); 1745 1746 mtx_lock(&moea_vsid_mutex); 1747 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1748 mask = 1 << (idx % VSID_NBPW); 1749 idx /= VSID_NBPW; 1750 moea_vsid_bitmap[idx] &= ~mask; 1751 mtx_unlock(&moea_vsid_mutex); 1752 PMAP_LOCK_DESTROY(pmap); 1753 } 1754 1755 /* 1756 * Remove the given range of addresses from the specified map. 1757 */ 1758 void 1759 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1760 { 1761 struct pvo_entry *pvo; 1762 int pteidx; 1763 1764 vm_page_lock_queues(); 1765 PMAP_LOCK(pm); 1766 for (; sva < eva; sva += PAGE_SIZE) { 1767 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1768 if (pvo != NULL) { 1769 moea_pvo_remove(pvo, pteidx); 1770 } 1771 } 1772 PMAP_UNLOCK(pm); 1773 vm_page_unlock_queues(); 1774 } 1775 1776 /* 1777 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1778 * will reflect changes in pte's back to the vm_page. 1779 */ 1780 void 1781 moea_remove_all(mmu_t mmu, vm_page_t m) 1782 { 1783 struct pvo_head *pvo_head; 1784 struct pvo_entry *pvo, *next_pvo; 1785 pmap_t pmap; 1786 1787 vm_page_lock_queues(); 1788 pvo_head = vm_page_to_pvoh(m); 1789 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1790 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1791 1792 pmap = pvo->pvo_pmap; 1793 PMAP_LOCK(pmap); 1794 moea_pvo_remove(pvo, -1); 1795 PMAP_UNLOCK(pmap); 1796 } 1797 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1798 moea_attr_clear(m, PTE_CHG); 1799 vm_page_dirty(m); 1800 } 1801 vm_page_flag_clear(m, PG_WRITEABLE); 1802 vm_page_unlock_queues(); 1803 } 1804 1805 /* 1806 * Allocate a physical page of memory directly from the phys_avail map. 1807 * Can only be called from moea_bootstrap before avail start and end are 1808 * calculated. 1809 */ 1810 static vm_offset_t 1811 moea_bootstrap_alloc(vm_size_t size, u_int align) 1812 { 1813 vm_offset_t s, e; 1814 int i, j; 1815 1816 size = round_page(size); 1817 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1818 if (align != 0) 1819 s = (phys_avail[i] + align - 1) & ~(align - 1); 1820 else 1821 s = phys_avail[i]; 1822 e = s + size; 1823 1824 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1825 continue; 1826 1827 if (s == phys_avail[i]) { 1828 phys_avail[i] += size; 1829 } else if (e == phys_avail[i + 1]) { 1830 phys_avail[i + 1] -= size; 1831 } else { 1832 for (j = phys_avail_count * 2; j > i; j -= 2) { 1833 phys_avail[j] = phys_avail[j - 2]; 1834 phys_avail[j + 1] = phys_avail[j - 1]; 1835 } 1836 1837 phys_avail[i + 3] = phys_avail[i + 1]; 1838 phys_avail[i + 1] = s; 1839 phys_avail[i + 2] = e; 1840 phys_avail_count++; 1841 } 1842 1843 return (s); 1844 } 1845 panic("moea_bootstrap_alloc: could not allocate memory"); 1846 } 1847 1848 static void 1849 moea_syncicache(vm_offset_t pa, vm_size_t len) 1850 { 1851 __syncicache((void *)pa, len); 1852 } 1853 1854 static int 1855 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1856 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1857 { 1858 struct pvo_entry *pvo; 1859 u_int sr; 1860 int first; 1861 u_int ptegidx; 1862 int i; 1863 int bootstrap; 1864 1865 moea_pvo_enter_calls++; 1866 first = 0; 1867 bootstrap = 0; 1868 1869 /* 1870 * Compute the PTE Group index. 1871 */ 1872 va &= ~ADDR_POFF; 1873 sr = va_to_sr(pm->pm_sr, va); 1874 ptegidx = va_to_pteg(sr, va); 1875 1876 /* 1877 * Remove any existing mapping for this page. Reuse the pvo entry if 1878 * there is a mapping. 1879 */ 1880 mtx_lock(&moea_table_mutex); 1881 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1882 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1883 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1884 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1885 (pte_lo & PTE_PP)) { 1886 mtx_unlock(&moea_table_mutex); 1887 return (0); 1888 } 1889 moea_pvo_remove(pvo, -1); 1890 break; 1891 } 1892 } 1893 1894 /* 1895 * If we aren't overwriting a mapping, try to allocate. 1896 */ 1897 if (moea_initialized) { 1898 pvo = uma_zalloc(zone, M_NOWAIT); 1899 } else { 1900 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1901 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1902 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1903 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1904 } 1905 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1906 moea_bpvo_pool_index++; 1907 bootstrap = 1; 1908 } 1909 1910 if (pvo == NULL) { 1911 mtx_unlock(&moea_table_mutex); 1912 return (ENOMEM); 1913 } 1914 1915 moea_pvo_entries++; 1916 pvo->pvo_vaddr = va; 1917 pvo->pvo_pmap = pm; 1918 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1919 pvo->pvo_vaddr &= ~ADDR_POFF; 1920 if (flags & VM_PROT_EXECUTE) 1921 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1922 if (flags & PVO_WIRED) 1923 pvo->pvo_vaddr |= PVO_WIRED; 1924 if (pvo_head != &moea_pvo_kunmanaged) 1925 pvo->pvo_vaddr |= PVO_MANAGED; 1926 if (bootstrap) 1927 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1928 if (flags & PVO_FAKE) 1929 pvo->pvo_vaddr |= PVO_FAKE; 1930 1931 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1932 1933 /* 1934 * Remember if the list was empty and therefore will be the first 1935 * item. 1936 */ 1937 if (LIST_FIRST(pvo_head) == NULL) 1938 first = 1; 1939 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1940 1941 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1942 pm->pm_stats.wired_count++; 1943 pm->pm_stats.resident_count++; 1944 1945 /* 1946 * We hope this succeeds but it isn't required. 1947 */ 1948 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1949 if (i >= 0) { 1950 PVO_PTEGIDX_SET(pvo, i); 1951 } else { 1952 panic("moea_pvo_enter: overflow"); 1953 moea_pte_overflow++; 1954 } 1955 mtx_unlock(&moea_table_mutex); 1956 1957 return (first ? ENOENT : 0); 1958 } 1959 1960 static void 1961 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1962 { 1963 struct pte *pt; 1964 1965 /* 1966 * If there is an active pte entry, we need to deactivate it (and 1967 * save the ref & cfg bits). 1968 */ 1969 pt = moea_pvo_to_pte(pvo, pteidx); 1970 if (pt != NULL) { 1971 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1972 mtx_unlock(&moea_table_mutex); 1973 PVO_PTEGIDX_CLR(pvo); 1974 } else { 1975 moea_pte_overflow--; 1976 } 1977 1978 /* 1979 * Update our statistics. 1980 */ 1981 pvo->pvo_pmap->pm_stats.resident_count--; 1982 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1983 pvo->pvo_pmap->pm_stats.wired_count--; 1984 1985 /* 1986 * Save the REF/CHG bits into their cache if the page is managed. 1987 */ 1988 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 1989 struct vm_page *pg; 1990 1991 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1992 if (pg != NULL) { 1993 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 1994 (PTE_REF | PTE_CHG)); 1995 } 1996 } 1997 1998 /* 1999 * Remove this PVO from the PV list. 2000 */ 2001 LIST_REMOVE(pvo, pvo_vlink); 2002 2003 /* 2004 * Remove this from the overflow list and return it to the pool 2005 * if we aren't going to reuse it. 2006 */ 2007 LIST_REMOVE(pvo, pvo_olink); 2008 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2009 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2010 moea_upvo_zone, pvo); 2011 moea_pvo_entries--; 2012 moea_pvo_remove_calls++; 2013 } 2014 2015 static __inline int 2016 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2017 { 2018 int pteidx; 2019 2020 /* 2021 * We can find the actual pte entry without searching by grabbing 2022 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2023 * noticing the HID bit. 2024 */ 2025 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2026 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2027 pteidx ^= moea_pteg_mask * 8; 2028 2029 return (pteidx); 2030 } 2031 2032 static struct pvo_entry * 2033 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2034 { 2035 struct pvo_entry *pvo; 2036 int ptegidx; 2037 u_int sr; 2038 2039 va &= ~ADDR_POFF; 2040 sr = va_to_sr(pm->pm_sr, va); 2041 ptegidx = va_to_pteg(sr, va); 2042 2043 mtx_lock(&moea_table_mutex); 2044 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2045 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2046 if (pteidx_p) 2047 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2048 break; 2049 } 2050 } 2051 mtx_unlock(&moea_table_mutex); 2052 2053 return (pvo); 2054 } 2055 2056 static struct pte * 2057 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2058 { 2059 struct pte *pt; 2060 2061 /* 2062 * If we haven't been supplied the ptegidx, calculate it. 2063 */ 2064 if (pteidx == -1) { 2065 int ptegidx; 2066 u_int sr; 2067 2068 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2069 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2070 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2071 } 2072 2073 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2074 mtx_lock(&moea_table_mutex); 2075 2076 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2077 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2078 "valid pte index", pvo); 2079 } 2080 2081 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2082 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2083 "pvo but no valid pte", pvo); 2084 } 2085 2086 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2087 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2088 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2089 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2090 } 2091 2092 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2093 != 0) { 2094 panic("moea_pvo_to_pte: pvo %p pte does not match " 2095 "pte %p in moea_pteg_table", pvo, pt); 2096 } 2097 2098 mtx_assert(&moea_table_mutex, MA_OWNED); 2099 return (pt); 2100 } 2101 2102 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2103 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2104 "moea_pteg_table but valid in pvo", pvo, pt); 2105 } 2106 2107 mtx_unlock(&moea_table_mutex); 2108 return (NULL); 2109 } 2110 2111 /* 2112 * XXX: THIS STUFF SHOULD BE IN pte.c? 2113 */ 2114 int 2115 moea_pte_spill(vm_offset_t addr) 2116 { 2117 struct pvo_entry *source_pvo, *victim_pvo; 2118 struct pvo_entry *pvo; 2119 int ptegidx, i, j; 2120 u_int sr; 2121 struct pteg *pteg; 2122 struct pte *pt; 2123 2124 moea_pte_spills++; 2125 2126 sr = mfsrin(addr); 2127 ptegidx = va_to_pteg(sr, addr); 2128 2129 /* 2130 * Have to substitute some entry. Use the primary hash for this. 2131 * Use low bits of timebase as random generator. 2132 */ 2133 pteg = &moea_pteg_table[ptegidx]; 2134 mtx_lock(&moea_table_mutex); 2135 __asm __volatile("mftb %0" : "=r"(i)); 2136 i &= 7; 2137 pt = &pteg->pt[i]; 2138 2139 source_pvo = NULL; 2140 victim_pvo = NULL; 2141 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2142 /* 2143 * We need to find a pvo entry for this address. 2144 */ 2145 if (source_pvo == NULL && 2146 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2147 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2148 /* 2149 * Now found an entry to be spilled into the pteg. 2150 * The PTE is now valid, so we know it's active. 2151 */ 2152 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2153 2154 if (j >= 0) { 2155 PVO_PTEGIDX_SET(pvo, j); 2156 moea_pte_overflow--; 2157 mtx_unlock(&moea_table_mutex); 2158 return (1); 2159 } 2160 2161 source_pvo = pvo; 2162 2163 if (victim_pvo != NULL) 2164 break; 2165 } 2166 2167 /* 2168 * We also need the pvo entry of the victim we are replacing 2169 * so save the R & C bits of the PTE. 2170 */ 2171 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2172 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2173 victim_pvo = pvo; 2174 if (source_pvo != NULL) 2175 break; 2176 } 2177 } 2178 2179 if (source_pvo == NULL) { 2180 mtx_unlock(&moea_table_mutex); 2181 return (0); 2182 } 2183 2184 if (victim_pvo == NULL) { 2185 if ((pt->pte_hi & PTE_HID) == 0) 2186 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2187 "entry", pt); 2188 2189 /* 2190 * If this is a secondary PTE, we need to search it's primary 2191 * pvo bucket for the matching PVO. 2192 */ 2193 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2194 pvo_olink) { 2195 /* 2196 * We also need the pvo entry of the victim we are 2197 * replacing so save the R & C bits of the PTE. 2198 */ 2199 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2200 victim_pvo = pvo; 2201 break; 2202 } 2203 } 2204 2205 if (victim_pvo == NULL) 2206 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2207 "entry", pt); 2208 } 2209 2210 /* 2211 * We are invalidating the TLB entry for the EA we are replacing even 2212 * though it's valid. If we don't, we lose any ref/chg bit changes 2213 * contained in the TLB entry. 2214 */ 2215 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2216 2217 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2218 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2219 2220 PVO_PTEGIDX_CLR(victim_pvo); 2221 PVO_PTEGIDX_SET(source_pvo, i); 2222 moea_pte_replacements++; 2223 2224 mtx_unlock(&moea_table_mutex); 2225 return (1); 2226 } 2227 2228 static int 2229 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2230 { 2231 struct pte *pt; 2232 int i; 2233 2234 mtx_assert(&moea_table_mutex, MA_OWNED); 2235 2236 /* 2237 * First try primary hash. 2238 */ 2239 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2240 if ((pt->pte_hi & PTE_VALID) == 0) { 2241 pvo_pt->pte_hi &= ~PTE_HID; 2242 moea_pte_set(pt, pvo_pt); 2243 return (i); 2244 } 2245 } 2246 2247 /* 2248 * Now try secondary hash. 2249 */ 2250 ptegidx ^= moea_pteg_mask; 2251 2252 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2253 if ((pt->pte_hi & PTE_VALID) == 0) { 2254 pvo_pt->pte_hi |= PTE_HID; 2255 moea_pte_set(pt, pvo_pt); 2256 return (i); 2257 } 2258 } 2259 2260 panic("moea_pte_insert: overflow"); 2261 return (-1); 2262 } 2263 2264 static boolean_t 2265 moea_query_bit(vm_page_t m, int ptebit) 2266 { 2267 struct pvo_entry *pvo; 2268 struct pte *pt; 2269 2270 if (moea_attr_fetch(m) & ptebit) 2271 return (TRUE); 2272 2273 vm_page_lock_queues(); 2274 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2275 2276 /* 2277 * See if we saved the bit off. If so, cache it and return 2278 * success. 2279 */ 2280 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2281 moea_attr_save(m, ptebit); 2282 vm_page_unlock_queues(); 2283 return (TRUE); 2284 } 2285 } 2286 2287 /* 2288 * No luck, now go through the hard part of looking at the PTEs 2289 * themselves. Sync so that any pending REF/CHG bits are flushed to 2290 * the PTEs. 2291 */ 2292 powerpc_sync(); 2293 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2294 2295 /* 2296 * See if this pvo has a valid PTE. if so, fetch the 2297 * REF/CHG bits from the valid PTE. If the appropriate 2298 * ptebit is set, cache it and return success. 2299 */ 2300 pt = moea_pvo_to_pte(pvo, -1); 2301 if (pt != NULL) { 2302 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2303 mtx_unlock(&moea_table_mutex); 2304 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2305 moea_attr_save(m, ptebit); 2306 vm_page_unlock_queues(); 2307 return (TRUE); 2308 } 2309 } 2310 } 2311 2312 vm_page_unlock_queues(); 2313 return (FALSE); 2314 } 2315 2316 static u_int 2317 moea_clear_bit(vm_page_t m, int ptebit) 2318 { 2319 u_int count; 2320 struct pvo_entry *pvo; 2321 struct pte *pt; 2322 2323 vm_page_lock_queues(); 2324 2325 /* 2326 * Clear the cached value. 2327 */ 2328 moea_attr_clear(m, ptebit); 2329 2330 /* 2331 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2332 * we can reset the right ones). note that since the pvo entries and 2333 * list heads are accessed via BAT0 and are never placed in the page 2334 * table, we don't have to worry about further accesses setting the 2335 * REF/CHG bits. 2336 */ 2337 powerpc_sync(); 2338 2339 /* 2340 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2341 * valid pte clear the ptebit from the valid pte. 2342 */ 2343 count = 0; 2344 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2345 pt = moea_pvo_to_pte(pvo, -1); 2346 if (pt != NULL) { 2347 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2348 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2349 count++; 2350 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2351 } 2352 mtx_unlock(&moea_table_mutex); 2353 } 2354 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2355 } 2356 2357 vm_page_unlock_queues(); 2358 return (count); 2359 } 2360 2361 /* 2362 * Return true if the physical range is encompassed by the battable[idx] 2363 */ 2364 static int 2365 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2366 { 2367 u_int prot; 2368 u_int32_t start; 2369 u_int32_t end; 2370 u_int32_t bat_ble; 2371 2372 /* 2373 * Return immediately if not a valid mapping 2374 */ 2375 if (!(battable[idx].batu & BAT_Vs)) 2376 return (EINVAL); 2377 2378 /* 2379 * The BAT entry must be cache-inhibited, guarded, and r/w 2380 * so it can function as an i/o page 2381 */ 2382 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2383 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2384 return (EPERM); 2385 2386 /* 2387 * The address should be within the BAT range. Assume that the 2388 * start address in the BAT has the correct alignment (thus 2389 * not requiring masking) 2390 */ 2391 start = battable[idx].batl & BAT_PBS; 2392 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2393 end = start | (bat_ble << 15) | 0x7fff; 2394 2395 if ((pa < start) || ((pa + size) > end)) 2396 return (ERANGE); 2397 2398 return (0); 2399 } 2400 2401 boolean_t 2402 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2403 { 2404 int i; 2405 2406 /* 2407 * This currently does not work for entries that 2408 * overlap 256M BAT segments. 2409 */ 2410 2411 for(i = 0; i < 16; i++) 2412 if (moea_bat_mapped(i, pa, size) == 0) 2413 return (0); 2414 2415 return (EFAULT); 2416 } 2417 2418 /* 2419 * Map a set of physical memory pages into the kernel virtual 2420 * address space. Return a pointer to where it is mapped. This 2421 * routine is intended to be used for mapping device memory, 2422 * NOT real memory. 2423 */ 2424 void * 2425 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2426 { 2427 2428 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2429 } 2430 2431 void * 2432 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2433 { 2434 vm_offset_t va, tmpva, ppa, offset; 2435 int i; 2436 2437 ppa = trunc_page(pa); 2438 offset = pa & PAGE_MASK; 2439 size = roundup(offset + size, PAGE_SIZE); 2440 2441 /* 2442 * If the physical address lies within a valid BAT table entry, 2443 * return the 1:1 mapping. This currently doesn't work 2444 * for regions that overlap 256M BAT segments. 2445 */ 2446 for (i = 0; i < 16; i++) { 2447 if (moea_bat_mapped(i, pa, size) == 0) 2448 return ((void *) pa); 2449 } 2450 2451 va = kmem_alloc_nofault(kernel_map, size); 2452 if (!va) 2453 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2454 2455 for (tmpva = va; size > 0;) { 2456 moea_kenter_attr(mmu, tmpva, ppa, ma); 2457 tlbie(tmpva); 2458 size -= PAGE_SIZE; 2459 tmpva += PAGE_SIZE; 2460 ppa += PAGE_SIZE; 2461 } 2462 2463 return ((void *)(va + offset)); 2464 } 2465 2466 void 2467 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2468 { 2469 vm_offset_t base, offset; 2470 2471 /* 2472 * If this is outside kernel virtual space, then it's a 2473 * battable entry and doesn't require unmapping 2474 */ 2475 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2476 base = trunc_page(va); 2477 offset = va & PAGE_MASK; 2478 size = roundup(offset + size, PAGE_SIZE); 2479 kmem_free(kernel_map, base, size); 2480 } 2481 } 2482 2483 static void 2484 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2485 { 2486 struct pvo_entry *pvo; 2487 vm_offset_t lim; 2488 vm_paddr_t pa; 2489 vm_size_t len; 2490 2491 PMAP_LOCK(pm); 2492 while (sz > 0) { 2493 lim = round_page(va); 2494 len = MIN(lim - va, sz); 2495 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2496 if (pvo != NULL) { 2497 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2498 (va & ADDR_POFF); 2499 moea_syncicache(pa, len); 2500 } 2501 va += len; 2502 sz -= len; 2503 } 2504 PMAP_UNLOCK(pm); 2505 } 2506