1 /* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /* 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /* 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/powerpc.h> 144 #include <machine/bat.h> 145 #include <machine/frame.h> 146 #include <machine/md_var.h> 147 #include <machine/psl.h> 148 #include <machine/pte.h> 149 #include <machine/sr.h> 150 151 #define PMAP_DEBUG 152 153 #define TODO panic("%s: not implemented", __func__); 154 155 #define PMAP_LOCK(pm) 156 #define PMAP_UNLOCK(pm) 157 158 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 159 #define TLBSYNC() __asm __volatile("tlbsync"); 160 #define SYNC() __asm __volatile("sync"); 161 #define EIEIO() __asm __volatile("eieio"); 162 163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 165 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 166 167 #define PVO_PTEGIDX_MASK 0x0007 /* which PTEG slot */ 168 #define PVO_PTEGIDX_VALID 0x0008 /* slot is valid */ 169 #define PVO_WIRED 0x0010 /* PVO entry is wired */ 170 #define PVO_MANAGED 0x0020 /* PVO entry is managed */ 171 #define PVO_EXECUTABLE 0x0040 /* PVO entry is executable */ 172 #define PVO_BOOTSTRAP 0x0080 /* PVO entry allocated during 173 bootstrap */ 174 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 175 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 176 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 177 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 178 #define PVO_PTEGIDX_CLR(pvo) \ 179 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 180 #define PVO_PTEGIDX_SET(pvo, i) \ 181 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 182 183 #define PMAP_PVO_CHECK(pvo) 184 185 struct ofw_map { 186 vm_offset_t om_va; 187 vm_size_t om_len; 188 vm_offset_t om_pa; 189 u_int om_mode; 190 }; 191 192 int pmap_bootstrapped = 0; 193 194 /* 195 * Virtual and physical address of message buffer. 196 */ 197 struct msgbuf *msgbufp; 198 vm_offset_t msgbuf_phys; 199 200 /* 201 * Physical addresses of first and last available physical page. 202 */ 203 vm_offset_t avail_start; 204 vm_offset_t avail_end; 205 206 int pmap_pagedaemon_waken; 207 208 /* 209 * Map of physical memory regions. 210 */ 211 vm_offset_t phys_avail[128]; 212 u_int phys_avail_count; 213 static struct mem_region *regions; 214 static struct mem_region *pregions; 215 int regions_sz, pregions_sz; 216 static struct ofw_map *translations; 217 218 /* 219 * First and last available kernel virtual addresses. 220 */ 221 vm_offset_t virtual_avail; 222 vm_offset_t virtual_end; 223 vm_offset_t kernel_vm_end; 224 225 /* 226 * Kernel pmap. 227 */ 228 struct pmap kernel_pmap_store; 229 extern struct pmap ofw_pmap; 230 231 /* 232 * PTEG data. 233 */ 234 static struct pteg *pmap_pteg_table; 235 u_int pmap_pteg_count; 236 u_int pmap_pteg_mask; 237 238 /* 239 * PVO data. 240 */ 241 struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 242 struct pvo_head pmap_pvo_kunmanaged = 243 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 244 struct pvo_head pmap_pvo_unmanaged = 245 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 246 247 uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 248 uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 249 struct vm_object pmap_upvo_zone_obj; 250 struct vm_object pmap_mpvo_zone_obj; 251 252 #define BPVO_POOL_SIZE 32768 253 static struct pvo_entry *pmap_bpvo_pool; 254 static int pmap_bpvo_pool_index = 0; 255 256 #define VSID_NBPW (sizeof(u_int32_t) * 8) 257 static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 258 259 static boolean_t pmap_initialized = FALSE; 260 261 /* 262 * Statistics. 263 */ 264 u_int pmap_pte_valid = 0; 265 u_int pmap_pte_overflow = 0; 266 u_int pmap_pte_replacements = 0; 267 u_int pmap_pvo_entries = 0; 268 u_int pmap_pvo_enter_calls = 0; 269 u_int pmap_pvo_remove_calls = 0; 270 u_int pmap_pte_spills = 0; 271 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 272 0, ""); 273 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 274 &pmap_pte_overflow, 0, ""); 275 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 276 &pmap_pte_replacements, 0, ""); 277 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 278 0, ""); 279 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 280 &pmap_pvo_enter_calls, 0, ""); 281 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 282 &pmap_pvo_remove_calls, 0, ""); 283 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 284 &pmap_pte_spills, 0, ""); 285 286 struct pvo_entry *pmap_pvo_zeropage; 287 288 vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 289 u_int pmap_rkva_count = 4; 290 291 /* 292 * Allocate physical memory for use in pmap_bootstrap. 293 */ 294 static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 295 296 /* 297 * PTE calls. 298 */ 299 static int pmap_pte_insert(u_int, struct pte *); 300 301 /* 302 * PVO calls. 303 */ 304 static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 305 vm_offset_t, vm_offset_t, u_int, int); 306 static void pmap_pvo_remove(struct pvo_entry *, int); 307 static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 308 static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 309 310 /* 311 * Utility routines. 312 */ 313 static void * pmap_pvo_allocf(uma_zone_t, int, u_int8_t *, int); 314 static struct pvo_entry *pmap_rkva_alloc(void); 315 static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 316 struct pte *, int *); 317 static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 318 static void pmap_syncicache(vm_offset_t, vm_size_t); 319 static boolean_t pmap_query_bit(vm_page_t, int); 320 static u_int pmap_clear_bit(vm_page_t, int, int *); 321 static void tlbia(void); 322 323 static __inline int 324 va_to_sr(u_int *sr, vm_offset_t va) 325 { 326 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 327 } 328 329 static __inline u_int 330 va_to_pteg(u_int sr, vm_offset_t addr) 331 { 332 u_int hash; 333 334 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 335 ADDR_PIDX_SHFT); 336 return (hash & pmap_pteg_mask); 337 } 338 339 static __inline struct pvo_head * 340 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 341 { 342 struct vm_page *pg; 343 344 pg = PHYS_TO_VM_PAGE(pa); 345 346 if (pg_p != NULL) 347 *pg_p = pg; 348 349 if (pg == NULL) 350 return (&pmap_pvo_unmanaged); 351 352 return (&pg->md.mdpg_pvoh); 353 } 354 355 static __inline struct pvo_head * 356 vm_page_to_pvoh(vm_page_t m) 357 { 358 359 return (&m->md.mdpg_pvoh); 360 } 361 362 static __inline void 363 pmap_attr_clear(vm_page_t m, int ptebit) 364 { 365 366 m->md.mdpg_attrs &= ~ptebit; 367 } 368 369 static __inline int 370 pmap_attr_fetch(vm_page_t m) 371 { 372 373 return (m->md.mdpg_attrs); 374 } 375 376 static __inline void 377 pmap_attr_save(vm_page_t m, int ptebit) 378 { 379 380 m->md.mdpg_attrs |= ptebit; 381 } 382 383 static __inline int 384 pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 385 { 386 if (pt->pte_hi == pvo_pt->pte_hi) 387 return (1); 388 389 return (0); 390 } 391 392 static __inline int 393 pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 394 { 395 return (pt->pte_hi & ~PTE_VALID) == 396 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 397 ((va >> ADDR_API_SHFT) & PTE_API) | which); 398 } 399 400 static __inline void 401 pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 402 { 403 /* 404 * Construct a PTE. Default to IMB initially. Valid bit only gets 405 * set when the real pte is set in memory. 406 * 407 * Note: Don't set the valid bit for correct operation of tlb update. 408 */ 409 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 410 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 411 pt->pte_lo = pte_lo; 412 } 413 414 static __inline void 415 pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 416 { 417 418 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 419 } 420 421 static __inline void 422 pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 423 { 424 425 /* 426 * As shown in Section 7.6.3.2.3 427 */ 428 pt->pte_lo &= ~ptebit; 429 TLBIE(va); 430 EIEIO(); 431 TLBSYNC(); 432 SYNC(); 433 } 434 435 static __inline void 436 pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 437 { 438 439 pvo_pt->pte_hi |= PTE_VALID; 440 441 /* 442 * Update the PTE as defined in section 7.6.3.1. 443 * Note that the REF/CHG bits are from pvo_pt and thus should havce 444 * been saved so this routine can restore them (if desired). 445 */ 446 pt->pte_lo = pvo_pt->pte_lo; 447 EIEIO(); 448 pt->pte_hi = pvo_pt->pte_hi; 449 SYNC(); 450 pmap_pte_valid++; 451 } 452 453 static __inline void 454 pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 455 { 456 457 pvo_pt->pte_hi &= ~PTE_VALID; 458 459 /* 460 * Force the reg & chg bits back into the PTEs. 461 */ 462 SYNC(); 463 464 /* 465 * Invalidate the pte. 466 */ 467 pt->pte_hi &= ~PTE_VALID; 468 469 SYNC(); 470 TLBIE(va); 471 EIEIO(); 472 TLBSYNC(); 473 SYNC(); 474 475 /* 476 * Save the reg & chg bits. 477 */ 478 pmap_pte_synch(pt, pvo_pt); 479 pmap_pte_valid--; 480 } 481 482 static __inline void 483 pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 484 { 485 486 /* 487 * Invalidate the PTE 488 */ 489 pmap_pte_unset(pt, pvo_pt, va); 490 pmap_pte_set(pt, pvo_pt); 491 } 492 493 /* 494 * Quick sort callout for comparing memory regions. 495 */ 496 static int mr_cmp(const void *a, const void *b); 497 static int om_cmp(const void *a, const void *b); 498 499 static int 500 mr_cmp(const void *a, const void *b) 501 { 502 const struct mem_region *regiona; 503 const struct mem_region *regionb; 504 505 regiona = a; 506 regionb = b; 507 if (regiona->mr_start < regionb->mr_start) 508 return (-1); 509 else if (regiona->mr_start > regionb->mr_start) 510 return (1); 511 else 512 return (0); 513 } 514 515 static int 516 om_cmp(const void *a, const void *b) 517 { 518 const struct ofw_map *mapa; 519 const struct ofw_map *mapb; 520 521 mapa = a; 522 mapb = b; 523 if (mapa->om_pa < mapb->om_pa) 524 return (-1); 525 else if (mapa->om_pa > mapb->om_pa) 526 return (1); 527 else 528 return (0); 529 } 530 531 void 532 pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 533 { 534 ihandle_t mmui; 535 phandle_t chosen, mmu; 536 int sz; 537 int i, j; 538 int ofw_mappings; 539 vm_size_t size, physsz; 540 vm_offset_t pa, va, off; 541 u_int batl, batu; 542 543 /* 544 * Set up BAT0 to map the lowest 256 MB area 545 */ 546 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 547 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 548 549 /* 550 * Map PCI memory space. 551 */ 552 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 553 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 554 555 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 556 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 557 558 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 559 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 560 561 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 562 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 563 564 /* 565 * Map obio devices. 566 */ 567 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 568 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 569 570 /* 571 * Use an IBAT and a DBAT to map the bottom segment of memory 572 * where we are. 573 */ 574 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 575 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 576 __asm ("mtibatu 0,%0; mtibatl 0,%1; mtdbatu 0,%0; mtdbatl 0,%1" 577 :: "r"(batu), "r"(batl)); 578 579 #if 0 580 /* map frame buffer */ 581 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 582 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 583 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 584 :: "r"(batu), "r"(batl)); 585 #endif 586 587 #if 1 588 /* map pci space */ 589 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 590 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 591 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 592 :: "r"(batu), "r"(batl)); 593 #endif 594 595 /* 596 * Set the start and end of kva. 597 */ 598 virtual_avail = VM_MIN_KERNEL_ADDRESS; 599 virtual_end = VM_MAX_KERNEL_ADDRESS; 600 601 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 602 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 603 604 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 605 for (i = 0; i < pregions_sz; i++) { 606 vm_offset_t pa; 607 vm_offset_t end; 608 609 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 610 pregions[i].mr_start, 611 pregions[i].mr_start + pregions[i].mr_size, 612 pregions[i].mr_size); 613 /* 614 * Install entries into the BAT table to allow all 615 * of physmem to be convered by on-demand BAT entries. 616 * The loop will sometimes set the same battable element 617 * twice, but that's fine since they won't be used for 618 * a while yet. 619 */ 620 pa = pregions[i].mr_start & 0xf0000000; 621 end = pregions[i].mr_start + pregions[i].mr_size; 622 do { 623 u_int n = pa >> ADDR_SR_SHFT; 624 625 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 626 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 627 pa += SEGMENT_LENGTH; 628 } while (pa < end); 629 } 630 631 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 632 panic("pmap_bootstrap: phys_avail too small"); 633 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 634 phys_avail_count = 0; 635 physsz = 0; 636 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 637 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 638 regions[i].mr_start + regions[i].mr_size, 639 regions[i].mr_size); 640 phys_avail[j] = regions[i].mr_start; 641 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 642 phys_avail_count++; 643 physsz += regions[i].mr_size; 644 } 645 physmem = btoc(physsz); 646 647 /* 648 * Allocate PTEG table. 649 */ 650 #ifdef PTEGCOUNT 651 pmap_pteg_count = PTEGCOUNT; 652 #else 653 pmap_pteg_count = 0x1000; 654 655 while (pmap_pteg_count < physmem) 656 pmap_pteg_count <<= 1; 657 658 pmap_pteg_count >>= 1; 659 #endif /* PTEGCOUNT */ 660 661 size = pmap_pteg_count * sizeof(struct pteg); 662 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 663 size); 664 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 665 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 666 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 667 pmap_pteg_mask = pmap_pteg_count - 1; 668 669 /* 670 * Allocate pv/overflow lists. 671 */ 672 size = sizeof(struct pvo_head) * pmap_pteg_count; 673 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 674 PAGE_SIZE); 675 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 676 for (i = 0; i < pmap_pteg_count; i++) 677 LIST_INIT(&pmap_pvo_table[i]); 678 679 /* 680 * Allocate the message buffer. 681 */ 682 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 683 684 /* 685 * Initialise the unmanaged pvo pool. 686 */ 687 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 688 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 689 pmap_bpvo_pool_index = 0; 690 691 /* 692 * Make sure kernel vsid is allocated as well as VSID 0. 693 */ 694 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 695 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 696 pmap_vsid_bitmap[0] |= 1; 697 698 /* 699 * Set up the OpenFirmware pmap and add it's mappings. 700 */ 701 pmap_pinit(&ofw_pmap); 702 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 703 if ((chosen = OF_finddevice("/chosen")) == -1) 704 panic("pmap_bootstrap: can't find /chosen"); 705 OF_getprop(chosen, "mmu", &mmui, 4); 706 if ((mmu = OF_instance_to_package(mmui)) == -1) 707 panic("pmap_bootstrap: can't get mmu package"); 708 if ((sz = OF_getproplen(mmu, "translations")) == -1) 709 panic("pmap_bootstrap: can't get ofw translation count"); 710 translations = NULL; 711 for (i = 0; phys_avail[i + 2] != 0; i += 2) { 712 if (phys_avail[i + 1] >= sz) 713 translations = (struct ofw_map *)phys_avail[i]; 714 } 715 if (translations == NULL) 716 panic("pmap_bootstrap: no space to copy translations"); 717 bzero(translations, sz); 718 if (OF_getprop(mmu, "translations", translations, sz) == -1) 719 panic("pmap_bootstrap: can't get ofw translations"); 720 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 721 sz /= sizeof(*translations); 722 qsort(translations, sz, sizeof (*translations), om_cmp); 723 for (i = 0, ofw_mappings = 0; i < sz; i++) { 724 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 725 translations[i].om_pa, translations[i].om_va, 726 translations[i].om_len); 727 728 /* 729 * If the mapping is 1:1, let the RAM and device on-demand 730 * BAT tables take care of the translation. 731 */ 732 if (translations[i].om_va == translations[i].om_pa) 733 continue; 734 735 /* Enter the pages */ 736 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 737 struct vm_page m; 738 739 m.phys_addr = translations[i].om_pa + off; 740 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 741 VM_PROT_ALL, 1); 742 ofw_mappings++; 743 } 744 } 745 #ifdef SMP 746 TLBSYNC(); 747 #endif 748 749 /* 750 * Initialize the kernel pmap (which is statically allocated). 751 */ 752 for (i = 0; i < 16; i++) { 753 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 754 } 755 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 756 kernel_pmap->pm_active = ~0; 757 758 /* 759 * Allocate a kernel stack with a guard page for thread0 and map it 760 * into the kernel page map. 761 */ 762 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 763 kstack0_phys = pa; 764 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 765 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 766 kstack0); 767 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 768 for (i = 0; i < KSTACK_PAGES; i++) { 769 pa = kstack0_phys + i * PAGE_SIZE; 770 va = kstack0 + i * PAGE_SIZE; 771 pmap_kenter(va, pa); 772 TLBIE(va); 773 } 774 775 /* 776 * Calculate the first and last available physical addresses. 777 */ 778 avail_start = phys_avail[0]; 779 for (i = 0; phys_avail[i + 2] != 0; i += 2) 780 ; 781 avail_end = phys_avail[i + 1]; 782 Maxmem = powerpc_btop(avail_end); 783 784 /* 785 * Allocate virtual address space for the message buffer. 786 */ 787 msgbufp = (struct msgbuf *)virtual_avail; 788 virtual_avail += round_page(MSGBUF_SIZE); 789 790 /* 791 * Initialize hardware. 792 */ 793 for (i = 0; i < 16; i++) { 794 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 795 } 796 __asm __volatile ("mtsr %0,%1" 797 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 798 __asm __volatile ("sync; mtsdr1 %0; isync" 799 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 800 tlbia(); 801 802 pmap_bootstrapped++; 803 } 804 805 /* 806 * Activate a user pmap. The pmap must be activated before it's address 807 * space can be accessed in any way. 808 */ 809 void 810 pmap_activate(struct thread *td) 811 { 812 pmap_t pm, pmr; 813 814 /* 815 * Load all the data we need up front to encourage the compiler to 816 * not issue any loads while we have interrupts disabled below. 817 */ 818 pm = &td->td_proc->p_vmspace->vm_pmap; 819 820 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 821 pmr = pm; 822 823 pm->pm_active |= PCPU_GET(cpumask); 824 PCPU_SET(curpmap, pmr); 825 } 826 827 void 828 pmap_deactivate(struct thread *td) 829 { 830 pmap_t pm; 831 832 pm = &td->td_proc->p_vmspace->vm_pmap; 833 pm->pm_active &= ~(PCPU_GET(cpumask)); 834 PCPU_SET(curpmap, NULL); 835 } 836 837 vm_offset_t 838 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 839 { 840 841 return (va); 842 } 843 844 void 845 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 846 { 847 struct pvo_entry *pvo; 848 849 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 850 851 if (pvo != NULL) { 852 if (wired) { 853 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 854 pm->pm_stats.wired_count++; 855 pvo->pvo_vaddr |= PVO_WIRED; 856 } else { 857 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 858 pm->pm_stats.wired_count--; 859 pvo->pvo_vaddr &= ~PVO_WIRED; 860 } 861 } 862 } 863 864 void 865 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 866 vm_size_t len, vm_offset_t src_addr) 867 { 868 869 /* 870 * This is not needed as it's mainly an optimisation. 871 * It may want to be implemented later though. 872 */ 873 } 874 875 void 876 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 877 { 878 vm_offset_t dst; 879 vm_offset_t src; 880 881 dst = VM_PAGE_TO_PHYS(mdst); 882 src = VM_PAGE_TO_PHYS(msrc); 883 884 kcopy((void *)src, (void *)dst, PAGE_SIZE); 885 } 886 887 /* 888 * Zero a page of physical memory by temporarily mapping it into the tlb. 889 */ 890 void 891 pmap_zero_page(vm_page_t m) 892 { 893 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 894 caddr_t va; 895 896 if (pa < SEGMENT_LENGTH) { 897 va = (caddr_t) pa; 898 } else if (pmap_initialized) { 899 if (pmap_pvo_zeropage == NULL) 900 pmap_pvo_zeropage = pmap_rkva_alloc(); 901 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 902 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 903 } else { 904 panic("pmap_zero_page: can't zero pa %#x", pa); 905 } 906 907 bzero(va, PAGE_SIZE); 908 909 if (pa >= SEGMENT_LENGTH) 910 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 911 } 912 913 void 914 pmap_zero_page_area(vm_page_t m, int off, int size) 915 { 916 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 917 caddr_t va; 918 919 if (pa < SEGMENT_LENGTH) { 920 va = (caddr_t) pa; 921 } else if (pmap_initialized) { 922 if (pmap_pvo_zeropage == NULL) 923 pmap_pvo_zeropage = pmap_rkva_alloc(); 924 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 925 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 926 } else { 927 panic("pmap_zero_page: can't zero pa %#x", pa); 928 } 929 930 bzero(va + off, size); 931 932 if (pa >= SEGMENT_LENGTH) 933 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 934 } 935 936 void 937 pmap_zero_page_idle(vm_page_t m) 938 { 939 940 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 941 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 942 mtx_lock(&Giant); 943 pmap_zero_page(m); 944 mtx_unlock(&Giant); 945 } 946 947 /* 948 * Map the given physical page at the specified virtual address in the 949 * target pmap with the protection requested. If specified the page 950 * will be wired down. 951 */ 952 void 953 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 954 boolean_t wired) 955 { 956 struct pvo_head *pvo_head; 957 uma_zone_t zone; 958 vm_page_t pg; 959 u_int pte_lo, pvo_flags, was_exec, i; 960 int error; 961 962 if (!pmap_initialized) { 963 pvo_head = &pmap_pvo_kunmanaged; 964 zone = pmap_upvo_zone; 965 pvo_flags = 0; 966 pg = NULL; 967 was_exec = PTE_EXEC; 968 } else { 969 pvo_head = vm_page_to_pvoh(m); 970 pg = m; 971 zone = pmap_mpvo_zone; 972 pvo_flags = PVO_MANAGED; 973 was_exec = 0; 974 } 975 976 /* 977 * If this is a managed page, and it's the first reference to the page, 978 * clear the execness of the page. Otherwise fetch the execness. 979 */ 980 if (pg != NULL) { 981 if (LIST_EMPTY(pvo_head)) { 982 pmap_attr_clear(pg, PTE_EXEC); 983 } else { 984 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 985 } 986 } 987 988 989 /* 990 * Assume the page is cache inhibited and access is guarded unless 991 * it's in our available memory array. 992 */ 993 pte_lo = PTE_I | PTE_G; 994 for (i = 0; i < pregions_sz; i++) { 995 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 996 (VM_PAGE_TO_PHYS(m) < 997 (pregions[i].mr_start + pregions[i].mr_size))) { 998 pte_lo &= ~(PTE_I | PTE_G); 999 break; 1000 } 1001 } 1002 1003 if (prot & VM_PROT_WRITE) 1004 pte_lo |= PTE_BW; 1005 else 1006 pte_lo |= PTE_BR; 1007 1008 pvo_flags |= (prot & VM_PROT_EXECUTE); 1009 1010 if (wired) 1011 pvo_flags |= PVO_WIRED; 1012 1013 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1014 pte_lo, pvo_flags); 1015 1016 /* 1017 * Flush the real page from the instruction cache if this page is 1018 * mapped executable and cacheable and was not previously mapped (or 1019 * was not mapped executable). 1020 */ 1021 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1022 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1023 /* 1024 * Flush the real memory from the cache. 1025 */ 1026 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1027 if (pg != NULL) 1028 pmap_attr_save(pg, PTE_EXEC); 1029 } 1030 1031 /* XXX syncicache always until problems are sorted */ 1032 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1033 } 1034 1035 vm_page_t 1036 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_page_t mpte) 1037 { 1038 1039 pmap_enter(pm, va, m, VM_PROT_READ | VM_PROT_EXECUTE, FALSE); 1040 return (NULL); 1041 } 1042 1043 vm_offset_t 1044 pmap_extract(pmap_t pm, vm_offset_t va) 1045 { 1046 struct pvo_entry *pvo; 1047 1048 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1049 1050 if (pvo != NULL) { 1051 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1052 } 1053 1054 return (0); 1055 } 1056 1057 /* 1058 * Grow the number of kernel page table entries. Unneeded. 1059 */ 1060 void 1061 pmap_growkernel(vm_offset_t addr) 1062 { 1063 } 1064 1065 void 1066 pmap_init(vm_offset_t phys_start, vm_offset_t phys_end) 1067 { 1068 1069 CTR0(KTR_PMAP, "pmap_init"); 1070 1071 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1072 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1073 uma_zone_set_allocf(pmap_upvo_zone, pmap_pvo_allocf); 1074 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1075 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1076 uma_zone_set_allocf(pmap_mpvo_zone, pmap_pvo_allocf); 1077 pmap_initialized = TRUE; 1078 } 1079 1080 void 1081 pmap_init2(void) 1082 { 1083 1084 CTR0(KTR_PMAP, "pmap_init2"); 1085 } 1086 1087 boolean_t 1088 pmap_is_modified(vm_page_t m) 1089 { 1090 1091 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1092 return (FALSE); 1093 1094 return (pmap_query_bit(m, PTE_CHG)); 1095 } 1096 1097 void 1098 pmap_clear_reference(vm_page_t m) 1099 { 1100 1101 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1102 return; 1103 pmap_clear_bit(m, PTE_REF, NULL); 1104 } 1105 1106 void 1107 pmap_clear_modify(vm_page_t m) 1108 { 1109 1110 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1111 return; 1112 pmap_clear_bit(m, PTE_CHG, NULL); 1113 } 1114 1115 /* 1116 * pmap_ts_referenced: 1117 * 1118 * Return a count of reference bits for a page, clearing those bits. 1119 * It is not necessary for every reference bit to be cleared, but it 1120 * is necessary that 0 only be returned when there are truly no 1121 * reference bits set. 1122 * 1123 * XXX: The exact number of bits to check and clear is a matter that 1124 * should be tested and standardized at some point in the future for 1125 * optimal aging of shared pages. 1126 */ 1127 int 1128 pmap_ts_referenced(vm_page_t m) 1129 { 1130 int count; 1131 1132 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1133 return (0); 1134 1135 count = pmap_clear_bit(m, PTE_REF, NULL); 1136 1137 return (count); 1138 } 1139 1140 /* 1141 * Map a wired page into kernel virtual address space. 1142 */ 1143 void 1144 pmap_kenter(vm_offset_t va, vm_offset_t pa) 1145 { 1146 u_int pte_lo; 1147 int error; 1148 int i; 1149 1150 #if 0 1151 if (va < VM_MIN_KERNEL_ADDRESS) 1152 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1153 va); 1154 #endif 1155 1156 pte_lo = PTE_I | PTE_G; 1157 for (i = 0; i < pregions_sz; i++) { 1158 if ((pa >= pregions[i].mr_start) && 1159 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1160 pte_lo &= ~(PTE_I | PTE_G); 1161 break; 1162 } 1163 } 1164 1165 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1166 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1167 1168 if (error != 0 && error != ENOENT) 1169 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1170 pa, error); 1171 1172 /* 1173 * Flush the real memory from the instruction cache. 1174 */ 1175 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1176 pmap_syncicache(pa, PAGE_SIZE); 1177 } 1178 } 1179 1180 /* 1181 * Extract the physical page address associated with the given kernel virtual 1182 * address. 1183 */ 1184 vm_offset_t 1185 pmap_kextract(vm_offset_t va) 1186 { 1187 struct pvo_entry *pvo; 1188 1189 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1190 if (pvo == NULL) { 1191 return (0); 1192 } 1193 1194 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1195 } 1196 1197 /* 1198 * Remove a wired page from kernel virtual address space. 1199 */ 1200 void 1201 pmap_kremove(vm_offset_t va) 1202 { 1203 1204 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1205 } 1206 1207 /* 1208 * Map a range of physical addresses into kernel virtual address space. 1209 * 1210 * The value passed in *virt is a suggested virtual address for the mapping. 1211 * Architectures which can support a direct-mapped physical to virtual region 1212 * can return the appropriate address within that region, leaving '*virt' 1213 * unchanged. We cannot and therefore do not; *virt is updated with the 1214 * first usable address after the mapped region. 1215 */ 1216 vm_offset_t 1217 pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1218 { 1219 vm_offset_t sva, va; 1220 1221 sva = *virt; 1222 va = sva; 1223 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1224 pmap_kenter(va, pa_start); 1225 *virt = va; 1226 return (sva); 1227 } 1228 1229 int 1230 pmap_mincore(pmap_t pmap, vm_offset_t addr) 1231 { 1232 TODO; 1233 return (0); 1234 } 1235 1236 void 1237 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1238 vm_pindex_t pindex, vm_size_t size) 1239 { 1240 1241 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 1242 KASSERT(object->type == OBJT_DEVICE, 1243 ("pmap_object_init_pt: non-device object")); 1244 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1245 ("pmap_object_init_pt: non current pmap")); 1246 } 1247 1248 /* 1249 * Lower the permission for all mappings to a given page. 1250 */ 1251 void 1252 pmap_page_protect(vm_page_t m, vm_prot_t prot) 1253 { 1254 struct pvo_head *pvo_head; 1255 struct pvo_entry *pvo, *next_pvo; 1256 struct pte *pt; 1257 1258 /* 1259 * Since the routine only downgrades protection, if the 1260 * maximal protection is desired, there isn't any change 1261 * to be made. 1262 */ 1263 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1264 (VM_PROT_READ|VM_PROT_WRITE)) 1265 return; 1266 1267 pvo_head = vm_page_to_pvoh(m); 1268 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1269 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1270 PMAP_PVO_CHECK(pvo); /* sanity check */ 1271 1272 /* 1273 * Downgrading to no mapping at all, we just remove the entry. 1274 */ 1275 if ((prot & VM_PROT_READ) == 0) { 1276 pmap_pvo_remove(pvo, -1); 1277 continue; 1278 } 1279 1280 /* 1281 * If EXEC permission is being revoked, just clear the flag 1282 * in the PVO. 1283 */ 1284 if ((prot & VM_PROT_EXECUTE) == 0) 1285 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1286 1287 /* 1288 * If this entry is already RO, don't diddle with the page 1289 * table. 1290 */ 1291 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1292 PMAP_PVO_CHECK(pvo); 1293 continue; 1294 } 1295 1296 /* 1297 * Grab the PTE before we diddle the bits so pvo_to_pte can 1298 * verify the pte contents are as expected. 1299 */ 1300 pt = pmap_pvo_to_pte(pvo, -1); 1301 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1302 pvo->pvo_pte.pte_lo |= PTE_BR; 1303 if (pt != NULL) 1304 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1305 PMAP_PVO_CHECK(pvo); /* sanity check */ 1306 } 1307 } 1308 1309 /* 1310 * Returns true if the pmap's pv is one of the first 1311 * 16 pvs linked to from this page. This count may 1312 * be changed upwards or downwards in the future; it 1313 * is only necessary that true be returned for a small 1314 * subset of pmaps for proper page aging. 1315 */ 1316 boolean_t 1317 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1318 { 1319 int loops; 1320 struct pvo_entry *pvo; 1321 1322 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 1323 return FALSE; 1324 1325 loops = 0; 1326 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1327 if (pvo->pvo_pmap == pmap) 1328 return (TRUE); 1329 if (++loops >= 16) 1330 break; 1331 } 1332 1333 return (FALSE); 1334 } 1335 1336 static u_int pmap_vsidcontext; 1337 1338 void 1339 pmap_pinit(pmap_t pmap) 1340 { 1341 int i, mask; 1342 u_int entropy; 1343 1344 entropy = 0; 1345 __asm __volatile("mftb %0" : "=r"(entropy)); 1346 1347 /* 1348 * Allocate some segment registers for this pmap. 1349 */ 1350 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1351 u_int hash, n; 1352 1353 /* 1354 * Create a new value by mutiplying by a prime and adding in 1355 * entropy from the timebase register. This is to make the 1356 * VSID more random so that the PT hash function collides 1357 * less often. (Note that the prime casues gcc to do shifts 1358 * instead of a multiply.) 1359 */ 1360 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1361 hash = pmap_vsidcontext & (NPMAPS - 1); 1362 if (hash == 0) /* 0 is special, avoid it */ 1363 continue; 1364 n = hash >> 5; 1365 mask = 1 << (hash & (VSID_NBPW - 1)); 1366 hash = (pmap_vsidcontext & 0xfffff); 1367 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1368 /* anything free in this bucket? */ 1369 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1370 entropy = (pmap_vsidcontext >> 20); 1371 continue; 1372 } 1373 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1374 mask = 1 << i; 1375 hash &= 0xfffff & ~(VSID_NBPW - 1); 1376 hash |= i; 1377 } 1378 pmap_vsid_bitmap[n] |= mask; 1379 for (i = 0; i < 16; i++) 1380 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1381 return; 1382 } 1383 1384 panic("pmap_pinit: out of segments"); 1385 } 1386 1387 /* 1388 * Initialize the pmap associated with process 0. 1389 */ 1390 void 1391 pmap_pinit0(pmap_t pm) 1392 { 1393 1394 pmap_pinit(pm); 1395 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1396 } 1397 1398 void 1399 pmap_pinit2(pmap_t pmap) 1400 { 1401 /* XXX: Remove this stub when no longer called */ 1402 } 1403 1404 void 1405 pmap_prefault(pmap_t pm, vm_offset_t va, vm_map_entry_t entry) 1406 { 1407 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1408 ("pmap_prefault: non current pmap")); 1409 /* XXX */ 1410 } 1411 1412 /* 1413 * Set the physical protection on the specified range of this map as requested. 1414 */ 1415 void 1416 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1417 { 1418 struct pvo_entry *pvo; 1419 struct pte *pt; 1420 int pteidx; 1421 1422 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1423 eva, prot); 1424 1425 1426 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1427 ("pmap_protect: non current pmap")); 1428 1429 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1430 pmap_remove(pm, sva, eva); 1431 return; 1432 } 1433 1434 for (; sva < eva; sva += PAGE_SIZE) { 1435 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1436 if (pvo == NULL) 1437 continue; 1438 1439 if ((prot & VM_PROT_EXECUTE) == 0) 1440 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1441 1442 /* 1443 * Grab the PTE pointer before we diddle with the cached PTE 1444 * copy. 1445 */ 1446 pt = pmap_pvo_to_pte(pvo, pteidx); 1447 /* 1448 * Change the protection of the page. 1449 */ 1450 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1451 pvo->pvo_pte.pte_lo |= PTE_BR; 1452 1453 /* 1454 * If the PVO is in the page table, update that pte as well. 1455 */ 1456 if (pt != NULL) 1457 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1458 } 1459 } 1460 1461 /* 1462 * Map a list of wired pages into kernel virtual address space. This is 1463 * intended for temporary mappings which do not need page modification or 1464 * references recorded. Existing mappings in the region are overwritten. 1465 */ 1466 void 1467 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1468 { 1469 vm_offset_t va; 1470 1471 va = sva; 1472 while (count-- > 0) { 1473 pmap_kenter(va, VM_PAGE_TO_PHYS(*m)); 1474 va += PAGE_SIZE; 1475 m++; 1476 } 1477 } 1478 1479 /* 1480 * Remove page mappings from kernel virtual address space. Intended for 1481 * temporary mappings entered by pmap_qenter. 1482 */ 1483 void 1484 pmap_qremove(vm_offset_t sva, int count) 1485 { 1486 vm_offset_t va; 1487 1488 va = sva; 1489 while (count-- > 0) { 1490 pmap_kremove(va); 1491 va += PAGE_SIZE; 1492 } 1493 } 1494 1495 void 1496 pmap_release(pmap_t pmap) 1497 { 1498 int idx, mask; 1499 1500 /* 1501 * Free segment register's VSID 1502 */ 1503 if (pmap->pm_sr[0] == 0) 1504 panic("pmap_release"); 1505 1506 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1507 mask = 1 << (idx % VSID_NBPW); 1508 idx /= VSID_NBPW; 1509 pmap_vsid_bitmap[idx] &= ~mask; 1510 } 1511 1512 /* 1513 * Remove the given range of addresses from the specified map. 1514 */ 1515 void 1516 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1517 { 1518 struct pvo_entry *pvo; 1519 int pteidx; 1520 1521 for (; sva < eva; sva += PAGE_SIZE) { 1522 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1523 if (pvo != NULL) { 1524 pmap_pvo_remove(pvo, pteidx); 1525 } 1526 } 1527 } 1528 1529 /* 1530 * Remove physical page from all pmaps in which it resides. pmap_pvo_remove() 1531 * will reflect changes in pte's back to the vm_page. 1532 */ 1533 void 1534 pmap_remove_all(vm_page_t m) 1535 { 1536 struct pvo_head *pvo_head; 1537 struct pvo_entry *pvo, *next_pvo; 1538 1539 KASSERT((m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) == 0, 1540 ("pv_remove_all: illegal for unmanaged page %#x", 1541 VM_PAGE_TO_PHYS(m))); 1542 1543 pvo_head = vm_page_to_pvoh(m); 1544 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1545 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1546 1547 PMAP_PVO_CHECK(pvo); /* sanity check */ 1548 pmap_pvo_remove(pvo, -1); 1549 } 1550 vm_page_flag_clear(m, PG_WRITEABLE); 1551 } 1552 1553 /* 1554 * Remove all pages from specified address space, this aids process exit 1555 * speeds. This is much faster than pmap_remove in the case of running down 1556 * an entire address space. Only works for the current pmap. 1557 */ 1558 void 1559 pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1560 { 1561 1562 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1563 ("pmap_remove_pages: non current pmap")); 1564 pmap_remove(pm, sva, eva); 1565 } 1566 1567 /* 1568 * Allocate a physical page of memory directly from the phys_avail map. 1569 * Can only be called from pmap_bootstrap before avail start and end are 1570 * calculated. 1571 */ 1572 static vm_offset_t 1573 pmap_bootstrap_alloc(vm_size_t size, u_int align) 1574 { 1575 vm_offset_t s, e; 1576 int i, j; 1577 1578 size = round_page(size); 1579 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1580 if (align != 0) 1581 s = (phys_avail[i] + align - 1) & ~(align - 1); 1582 else 1583 s = phys_avail[i]; 1584 e = s + size; 1585 1586 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1587 continue; 1588 1589 if (s == phys_avail[i]) { 1590 phys_avail[i] += size; 1591 } else if (e == phys_avail[i + 1]) { 1592 phys_avail[i + 1] -= size; 1593 } else { 1594 for (j = phys_avail_count * 2; j > i; j -= 2) { 1595 phys_avail[j] = phys_avail[j - 2]; 1596 phys_avail[j + 1] = phys_avail[j - 1]; 1597 } 1598 1599 phys_avail[i + 3] = phys_avail[i + 1]; 1600 phys_avail[i + 1] = s; 1601 phys_avail[i + 2] = e; 1602 phys_avail_count++; 1603 } 1604 1605 return (s); 1606 } 1607 panic("pmap_bootstrap_alloc: could not allocate memory"); 1608 } 1609 1610 /* 1611 * Return an unmapped pvo for a kernel virtual address. 1612 * Used by pmap functions that operate on physical pages. 1613 */ 1614 static struct pvo_entry * 1615 pmap_rkva_alloc(void) 1616 { 1617 struct pvo_entry *pvo; 1618 struct pte *pt; 1619 vm_offset_t kva; 1620 int pteidx; 1621 1622 if (pmap_rkva_count == 0) 1623 panic("pmap_rkva_alloc: no more reserved KVAs"); 1624 1625 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1626 pmap_kenter(kva, 0); 1627 1628 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1629 1630 if (pvo == NULL) 1631 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1632 1633 pt = pmap_pvo_to_pte(pvo, pteidx); 1634 1635 if (pt == NULL) 1636 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1637 1638 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1639 PVO_PTEGIDX_CLR(pvo); 1640 1641 pmap_pte_overflow++; 1642 1643 return (pvo); 1644 } 1645 1646 static void 1647 pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1648 int *depth_p) 1649 { 1650 struct pte *pt; 1651 1652 /* 1653 * If this pvo already has a valid pte, we need to save it so it can 1654 * be restored later. We then just reload the new PTE over the old 1655 * slot. 1656 */ 1657 if (saved_pt != NULL) { 1658 pt = pmap_pvo_to_pte(pvo, -1); 1659 1660 if (pt != NULL) { 1661 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1662 PVO_PTEGIDX_CLR(pvo); 1663 pmap_pte_overflow++; 1664 } 1665 1666 *saved_pt = pvo->pvo_pte; 1667 1668 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1669 } 1670 1671 pvo->pvo_pte.pte_lo |= pa; 1672 1673 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1674 panic("pmap_pa_map: could not spill pvo %p", pvo); 1675 1676 if (depth_p != NULL) 1677 (*depth_p)++; 1678 } 1679 1680 static void 1681 pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1682 { 1683 struct pte *pt; 1684 1685 pt = pmap_pvo_to_pte(pvo, -1); 1686 1687 if (pt != NULL) { 1688 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1689 PVO_PTEGIDX_CLR(pvo); 1690 pmap_pte_overflow++; 1691 } 1692 1693 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1694 1695 /* 1696 * If there is a saved PTE and it's valid, restore it and return. 1697 */ 1698 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1699 if (depth_p != NULL && --(*depth_p) == 0) 1700 panic("pmap_pa_unmap: restoring but depth == 0"); 1701 1702 pvo->pvo_pte = *saved_pt; 1703 1704 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1705 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1706 } 1707 } 1708 1709 static void 1710 pmap_syncicache(vm_offset_t pa, vm_size_t len) 1711 { 1712 __syncicache((void *)pa, len); 1713 } 1714 1715 static void 1716 tlbia(void) 1717 { 1718 caddr_t i; 1719 1720 SYNC(); 1721 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1722 TLBIE(i); 1723 EIEIO(); 1724 } 1725 TLBSYNC(); 1726 SYNC(); 1727 } 1728 1729 static int 1730 pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1731 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1732 { 1733 struct pvo_entry *pvo; 1734 u_int sr; 1735 int first; 1736 u_int ptegidx; 1737 int i; 1738 int bootstrap; 1739 1740 pmap_pvo_enter_calls++; 1741 first = 0; 1742 1743 bootstrap = 0; 1744 1745 /* 1746 * Compute the PTE Group index. 1747 */ 1748 va &= ~ADDR_POFF; 1749 sr = va_to_sr(pm->pm_sr, va); 1750 ptegidx = va_to_pteg(sr, va); 1751 1752 /* 1753 * Remove any existing mapping for this page. Reuse the pvo entry if 1754 * there is a mapping. 1755 */ 1756 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1757 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1758 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1759 (pvo->pvo_pte.pte_lo & PTE_PP) == 1760 (pte_lo & PTE_PP)) { 1761 return (0); 1762 } 1763 pmap_pvo_remove(pvo, -1); 1764 break; 1765 } 1766 } 1767 1768 /* 1769 * If we aren't overwriting a mapping, try to allocate. 1770 */ 1771 if (pmap_initialized) { 1772 pvo = uma_zalloc(zone, M_NOWAIT); 1773 } else { 1774 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1775 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1776 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1777 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1778 } 1779 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1780 pmap_bpvo_pool_index++; 1781 bootstrap = 1; 1782 } 1783 1784 if (pvo == NULL) { 1785 return (ENOMEM); 1786 } 1787 1788 pmap_pvo_entries++; 1789 pvo->pvo_vaddr = va; 1790 pvo->pvo_pmap = pm; 1791 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1792 pvo->pvo_vaddr &= ~ADDR_POFF; 1793 if (flags & VM_PROT_EXECUTE) 1794 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1795 if (flags & PVO_WIRED) 1796 pvo->pvo_vaddr |= PVO_WIRED; 1797 if (pvo_head != &pmap_pvo_kunmanaged) 1798 pvo->pvo_vaddr |= PVO_MANAGED; 1799 if (bootstrap) 1800 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1801 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1802 1803 /* 1804 * Remember if the list was empty and therefore will be the first 1805 * item. 1806 */ 1807 if (LIST_FIRST(pvo_head) == NULL) 1808 first = 1; 1809 1810 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1811 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1812 pvo->pvo_pmap->pm_stats.wired_count++; 1813 pvo->pvo_pmap->pm_stats.resident_count++; 1814 1815 /* 1816 * We hope this succeeds but it isn't required. 1817 */ 1818 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1819 if (i >= 0) { 1820 PVO_PTEGIDX_SET(pvo, i); 1821 } else { 1822 panic("pmap_pvo_enter: overflow"); 1823 pmap_pte_overflow++; 1824 } 1825 1826 return (first ? ENOENT : 0); 1827 } 1828 1829 static void 1830 pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1831 { 1832 struct pte *pt; 1833 1834 /* 1835 * If there is an active pte entry, we need to deactivate it (and 1836 * save the ref & cfg bits). 1837 */ 1838 pt = pmap_pvo_to_pte(pvo, pteidx); 1839 if (pt != NULL) { 1840 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1841 PVO_PTEGIDX_CLR(pvo); 1842 } else { 1843 pmap_pte_overflow--; 1844 } 1845 1846 /* 1847 * Update our statistics. 1848 */ 1849 pvo->pvo_pmap->pm_stats.resident_count--; 1850 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1851 pvo->pvo_pmap->pm_stats.wired_count--; 1852 1853 /* 1854 * Save the REF/CHG bits into their cache if the page is managed. 1855 */ 1856 if (pvo->pvo_vaddr & PVO_MANAGED) { 1857 struct vm_page *pg; 1858 1859 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1860 if (pg != NULL) { 1861 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 1862 (PTE_REF | PTE_CHG)); 1863 } 1864 } 1865 1866 /* 1867 * Remove this PVO from the PV list. 1868 */ 1869 LIST_REMOVE(pvo, pvo_vlink); 1870 1871 /* 1872 * Remove this from the overflow list and return it to the pool 1873 * if we aren't going to reuse it. 1874 */ 1875 LIST_REMOVE(pvo, pvo_olink); 1876 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1877 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 1878 pmap_upvo_zone, pvo); 1879 pmap_pvo_entries--; 1880 pmap_pvo_remove_calls++; 1881 } 1882 1883 static __inline int 1884 pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1885 { 1886 int pteidx; 1887 1888 /* 1889 * We can find the actual pte entry without searching by grabbing 1890 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1891 * noticing the HID bit. 1892 */ 1893 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1894 if (pvo->pvo_pte.pte_hi & PTE_HID) 1895 pteidx ^= pmap_pteg_mask * 8; 1896 1897 return (pteidx); 1898 } 1899 1900 static struct pvo_entry * 1901 pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1902 { 1903 struct pvo_entry *pvo; 1904 int ptegidx; 1905 u_int sr; 1906 1907 va &= ~ADDR_POFF; 1908 sr = va_to_sr(pm->pm_sr, va); 1909 ptegidx = va_to_pteg(sr, va); 1910 1911 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1912 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1913 if (pteidx_p) 1914 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 1915 return (pvo); 1916 } 1917 } 1918 1919 return (NULL); 1920 } 1921 1922 static struct pte * 1923 pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 1924 { 1925 struct pte *pt; 1926 1927 /* 1928 * If we haven't been supplied the ptegidx, calculate it. 1929 */ 1930 if (pteidx == -1) { 1931 int ptegidx; 1932 u_int sr; 1933 1934 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 1935 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1936 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 1937 } 1938 1939 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 1940 1941 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 1942 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 1943 "valid pte index", pvo); 1944 } 1945 1946 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 1947 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 1948 "pvo but no valid pte", pvo); 1949 } 1950 1951 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 1952 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 1953 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 1954 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 1955 } 1956 1957 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 1958 != 0) { 1959 panic("pmap_pvo_to_pte: pvo %p pte does not match " 1960 "pte %p in pmap_pteg_table", pvo, pt); 1961 } 1962 1963 return (pt); 1964 } 1965 1966 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 1967 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 1968 "pmap_pteg_table but valid in pvo", pvo, pt); 1969 } 1970 1971 return (NULL); 1972 } 1973 1974 static void * 1975 pmap_pvo_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 1976 { 1977 static vm_pindex_t color; 1978 vm_page_t m; 1979 1980 if (bytes != PAGE_SIZE) 1981 panic("pmap_pvo_allocf: benno was shortsighted. hit him."); 1982 1983 *flags = UMA_SLAB_PRIV; 1984 /* 1985 * The color is only a hint. Thus, a data race in the read- 1986 * modify-write operation below isn't a catastrophe. 1987 */ 1988 m = vm_page_alloc(NULL, color++, VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM); 1989 if (m == NULL) 1990 return (NULL); 1991 return ((void *)VM_PAGE_TO_PHYS(m)); 1992 } 1993 1994 /* 1995 * XXX: THIS STUFF SHOULD BE IN pte.c? 1996 */ 1997 int 1998 pmap_pte_spill(vm_offset_t addr) 1999 { 2000 struct pvo_entry *source_pvo, *victim_pvo; 2001 struct pvo_entry *pvo; 2002 int ptegidx, i, j; 2003 u_int sr; 2004 struct pteg *pteg; 2005 struct pte *pt; 2006 2007 pmap_pte_spills++; 2008 2009 sr = mfsrin(addr); 2010 ptegidx = va_to_pteg(sr, addr); 2011 2012 /* 2013 * Have to substitute some entry. Use the primary hash for this. 2014 * Use low bits of timebase as random generator. 2015 */ 2016 pteg = &pmap_pteg_table[ptegidx]; 2017 __asm __volatile("mftb %0" : "=r"(i)); 2018 i &= 7; 2019 pt = &pteg->pt[i]; 2020 2021 source_pvo = NULL; 2022 victim_pvo = NULL; 2023 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2024 /* 2025 * We need to find a pvo entry for this address. 2026 */ 2027 PMAP_PVO_CHECK(pvo); 2028 if (source_pvo == NULL && 2029 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2030 pvo->pvo_pte.pte_hi & PTE_HID)) { 2031 /* 2032 * Now found an entry to be spilled into the pteg. 2033 * The PTE is now valid, so we know it's active. 2034 */ 2035 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2036 2037 if (j >= 0) { 2038 PVO_PTEGIDX_SET(pvo, j); 2039 pmap_pte_overflow--; 2040 PMAP_PVO_CHECK(pvo); 2041 return (1); 2042 } 2043 2044 source_pvo = pvo; 2045 2046 if (victim_pvo != NULL) 2047 break; 2048 } 2049 2050 /* 2051 * We also need the pvo entry of the victim we are replacing 2052 * so save the R & C bits of the PTE. 2053 */ 2054 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2055 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2056 victim_pvo = pvo; 2057 if (source_pvo != NULL) 2058 break; 2059 } 2060 } 2061 2062 if (source_pvo == NULL) 2063 return (0); 2064 2065 if (victim_pvo == NULL) { 2066 if ((pt->pte_hi & PTE_HID) == 0) 2067 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2068 "entry", pt); 2069 2070 /* 2071 * If this is a secondary PTE, we need to search it's primary 2072 * pvo bucket for the matching PVO. 2073 */ 2074 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2075 pvo_olink) { 2076 PMAP_PVO_CHECK(pvo); 2077 /* 2078 * We also need the pvo entry of the victim we are 2079 * replacing so save the R & C bits of the PTE. 2080 */ 2081 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2082 victim_pvo = pvo; 2083 break; 2084 } 2085 } 2086 2087 if (victim_pvo == NULL) 2088 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2089 "entry", pt); 2090 } 2091 2092 /* 2093 * We are invalidating the TLB entry for the EA we are replacing even 2094 * though it's valid. If we don't, we lose any ref/chg bit changes 2095 * contained in the TLB entry. 2096 */ 2097 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2098 2099 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2100 pmap_pte_set(pt, &source_pvo->pvo_pte); 2101 2102 PVO_PTEGIDX_CLR(victim_pvo); 2103 PVO_PTEGIDX_SET(source_pvo, i); 2104 pmap_pte_replacements++; 2105 2106 PMAP_PVO_CHECK(victim_pvo); 2107 PMAP_PVO_CHECK(source_pvo); 2108 2109 return (1); 2110 } 2111 2112 static int 2113 pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2114 { 2115 struct pte *pt; 2116 int i; 2117 2118 /* 2119 * First try primary hash. 2120 */ 2121 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2122 if ((pt->pte_hi & PTE_VALID) == 0) { 2123 pvo_pt->pte_hi &= ~PTE_HID; 2124 pmap_pte_set(pt, pvo_pt); 2125 return (i); 2126 } 2127 } 2128 2129 /* 2130 * Now try secondary hash. 2131 */ 2132 ptegidx ^= pmap_pteg_mask; 2133 ptegidx++; 2134 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2135 if ((pt->pte_hi & PTE_VALID) == 0) { 2136 pvo_pt->pte_hi |= PTE_HID; 2137 pmap_pte_set(pt, pvo_pt); 2138 return (i); 2139 } 2140 } 2141 2142 panic("pmap_pte_insert: overflow"); 2143 return (-1); 2144 } 2145 2146 static boolean_t 2147 pmap_query_bit(vm_page_t m, int ptebit) 2148 { 2149 struct pvo_entry *pvo; 2150 struct pte *pt; 2151 2152 if (pmap_attr_fetch(m) & ptebit) 2153 return (TRUE); 2154 2155 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2156 PMAP_PVO_CHECK(pvo); /* sanity check */ 2157 2158 /* 2159 * See if we saved the bit off. If so, cache it and return 2160 * success. 2161 */ 2162 if (pvo->pvo_pte.pte_lo & ptebit) { 2163 pmap_attr_save(m, ptebit); 2164 PMAP_PVO_CHECK(pvo); /* sanity check */ 2165 return (TRUE); 2166 } 2167 } 2168 2169 /* 2170 * No luck, now go through the hard part of looking at the PTEs 2171 * themselves. Sync so that any pending REF/CHG bits are flushed to 2172 * the PTEs. 2173 */ 2174 SYNC(); 2175 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2176 PMAP_PVO_CHECK(pvo); /* sanity check */ 2177 2178 /* 2179 * See if this pvo has a valid PTE. if so, fetch the 2180 * REF/CHG bits from the valid PTE. If the appropriate 2181 * ptebit is set, cache it and return success. 2182 */ 2183 pt = pmap_pvo_to_pte(pvo, -1); 2184 if (pt != NULL) { 2185 pmap_pte_synch(pt, &pvo->pvo_pte); 2186 if (pvo->pvo_pte.pte_lo & ptebit) { 2187 pmap_attr_save(m, ptebit); 2188 PMAP_PVO_CHECK(pvo); /* sanity check */ 2189 return (TRUE); 2190 } 2191 } 2192 } 2193 2194 return (TRUE); 2195 } 2196 2197 static u_int 2198 pmap_clear_bit(vm_page_t m, int ptebit, int *origbit) 2199 { 2200 u_int count; 2201 struct pvo_entry *pvo; 2202 struct pte *pt; 2203 int rv; 2204 2205 /* 2206 * Clear the cached value. 2207 */ 2208 rv = pmap_attr_fetch(m); 2209 pmap_attr_clear(m, ptebit); 2210 2211 /* 2212 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2213 * we can reset the right ones). note that since the pvo entries and 2214 * list heads are accessed via BAT0 and are never placed in the page 2215 * table, we don't have to worry about further accesses setting the 2216 * REF/CHG bits. 2217 */ 2218 SYNC(); 2219 2220 /* 2221 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2222 * valid pte clear the ptebit from the valid pte. 2223 */ 2224 count = 0; 2225 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2226 PMAP_PVO_CHECK(pvo); /* sanity check */ 2227 pt = pmap_pvo_to_pte(pvo, -1); 2228 if (pt != NULL) { 2229 pmap_pte_synch(pt, &pvo->pvo_pte); 2230 if (pvo->pvo_pte.pte_lo & ptebit) { 2231 count++; 2232 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2233 } 2234 } 2235 rv |= pvo->pvo_pte.pte_lo; 2236 pvo->pvo_pte.pte_lo &= ~ptebit; 2237 PMAP_PVO_CHECK(pvo); /* sanity check */ 2238 } 2239 2240 if (origbit != NULL) { 2241 *origbit = rv; 2242 } 2243 2244 return (count); 2245 } 2246 2247 /* 2248 * Return true if the physical range is encompassed by the battable[idx] 2249 */ 2250 static int 2251 pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2252 { 2253 u_int prot; 2254 u_int32_t start; 2255 u_int32_t end; 2256 u_int32_t bat_ble; 2257 2258 /* 2259 * Return immediately if not a valid mapping 2260 */ 2261 if (!battable[idx].batu & BAT_Vs) 2262 return (EINVAL); 2263 2264 /* 2265 * The BAT entry must be cache-inhibited, guarded, and r/w 2266 * so it can function as an i/o page 2267 */ 2268 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2269 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2270 return (EPERM); 2271 2272 /* 2273 * The address should be within the BAT range. Assume that the 2274 * start address in the BAT has the correct alignment (thus 2275 * not requiring masking) 2276 */ 2277 start = battable[idx].batl & BAT_PBS; 2278 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2279 end = start | (bat_ble << 15) | 0x7fff; 2280 2281 if ((pa < start) || ((pa + size) > end)) 2282 return (ERANGE); 2283 2284 return (0); 2285 } 2286 2287 2288 /* 2289 * Map a set of physical memory pages into the kernel virtual 2290 * address space. Return a pointer to where it is mapped. This 2291 * routine is intended to be used for mapping device memory, 2292 * NOT real memory. 2293 */ 2294 void * 2295 pmap_mapdev(vm_offset_t pa, vm_size_t size) 2296 { 2297 vm_offset_t va, tmpva, ppa, offset; 2298 int i; 2299 2300 ppa = trunc_page(pa); 2301 offset = pa & PAGE_MASK; 2302 size = roundup(offset + size, PAGE_SIZE); 2303 2304 GIANT_REQUIRED; 2305 2306 /* 2307 * If the physical address lies within a valid BAT table entry, 2308 * return the 1:1 mapping. This currently doesn't work 2309 * for regions that overlap 256M BAT segments. 2310 */ 2311 for (i = 0; i < 16; i++) { 2312 if (pmap_bat_mapped(i, pa, size) == 0) 2313 return ((void *) pa); 2314 } 2315 2316 va = kmem_alloc_nofault(kernel_map, size); 2317 if (!va) 2318 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2319 2320 for (tmpva = va; size > 0;) { 2321 pmap_kenter(tmpva, ppa); 2322 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2323 size -= PAGE_SIZE; 2324 tmpva += PAGE_SIZE; 2325 ppa += PAGE_SIZE; 2326 } 2327 2328 return ((void *)(va + offset)); 2329 } 2330 2331 void 2332 pmap_unmapdev(vm_offset_t va, vm_size_t size) 2333 { 2334 vm_offset_t base, offset; 2335 2336 /* 2337 * If this is outside kernel virtual space, then it's a 2338 * battable entry and doesn't require unmapping 2339 */ 2340 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2341 base = trunc_page(va); 2342 offset = va & PAGE_MASK; 2343 size = roundup(offset + size, PAGE_SIZE); 2344 kmem_free(kernel_map, base, size); 2345 } 2346 } 2347