1 /* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /* 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /* 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/powerpc.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/sr.h> 151 152 #define PMAP_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define PMAP_LOCK(pm) 157 #define PMAP_UNLOCK(pm) 158 159 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 160 #define TLBSYNC() __asm __volatile("tlbsync"); 161 #define SYNC() __asm __volatile("sync"); 162 #define EIEIO() __asm __volatile("eieio"); 163 164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 165 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 167 168 #define PVO_PTEGIDX_MASK 0x0007 /* which PTEG slot */ 169 #define PVO_PTEGIDX_VALID 0x0008 /* slot is valid */ 170 #define PVO_WIRED 0x0010 /* PVO entry is wired */ 171 #define PVO_MANAGED 0x0020 /* PVO entry is managed */ 172 #define PVO_EXECUTABLE 0x0040 /* PVO entry is executable */ 173 #define PVO_BOOTSTRAP 0x0080 /* PVO entry allocated during 174 bootstrap */ 175 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 176 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 177 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 178 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 179 #define PVO_PTEGIDX_CLR(pvo) \ 180 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 181 #define PVO_PTEGIDX_SET(pvo, i) \ 182 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 183 184 #define PMAP_PVO_CHECK(pvo) 185 186 struct ofw_map { 187 vm_offset_t om_va; 188 vm_size_t om_len; 189 vm_offset_t om_pa; 190 u_int om_mode; 191 }; 192 193 int pmap_bootstrapped = 0; 194 195 /* 196 * Virtual and physical address of message buffer. 197 */ 198 struct msgbuf *msgbufp; 199 vm_offset_t msgbuf_phys; 200 201 int pmap_pagedaemon_waken; 202 203 /* 204 * Map of physical memory regions. 205 */ 206 vm_offset_t phys_avail[128]; 207 u_int phys_avail_count; 208 static struct mem_region *regions; 209 static struct mem_region *pregions; 210 int regions_sz, pregions_sz; 211 static struct ofw_map *translations; 212 213 /* 214 * First and last available kernel virtual addresses. 215 */ 216 vm_offset_t virtual_avail; 217 vm_offset_t virtual_end; 218 vm_offset_t kernel_vm_end; 219 220 /* 221 * Kernel pmap. 222 */ 223 struct pmap kernel_pmap_store; 224 extern struct pmap ofw_pmap; 225 226 /* 227 * PTEG data. 228 */ 229 static struct pteg *pmap_pteg_table; 230 u_int pmap_pteg_count; 231 u_int pmap_pteg_mask; 232 233 /* 234 * PVO data. 235 */ 236 struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 237 struct pvo_head pmap_pvo_kunmanaged = 238 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 239 struct pvo_head pmap_pvo_unmanaged = 240 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 241 242 uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 243 uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 244 245 #define BPVO_POOL_SIZE 32768 246 static struct pvo_entry *pmap_bpvo_pool; 247 static int pmap_bpvo_pool_index = 0; 248 249 #define VSID_NBPW (sizeof(u_int32_t) * 8) 250 static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 251 252 static boolean_t pmap_initialized = FALSE; 253 254 /* 255 * Statistics. 256 */ 257 u_int pmap_pte_valid = 0; 258 u_int pmap_pte_overflow = 0; 259 u_int pmap_pte_replacements = 0; 260 u_int pmap_pvo_entries = 0; 261 u_int pmap_pvo_enter_calls = 0; 262 u_int pmap_pvo_remove_calls = 0; 263 u_int pmap_pte_spills = 0; 264 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 265 0, ""); 266 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 267 &pmap_pte_overflow, 0, ""); 268 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 269 &pmap_pte_replacements, 0, ""); 270 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 271 0, ""); 272 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 273 &pmap_pvo_enter_calls, 0, ""); 274 SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 275 &pmap_pvo_remove_calls, 0, ""); 276 SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 277 &pmap_pte_spills, 0, ""); 278 279 struct pvo_entry *pmap_pvo_zeropage; 280 281 vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 282 u_int pmap_rkva_count = 4; 283 284 /* 285 * Allocate physical memory for use in pmap_bootstrap. 286 */ 287 static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 288 289 /* 290 * PTE calls. 291 */ 292 static int pmap_pte_insert(u_int, struct pte *); 293 294 /* 295 * PVO calls. 296 */ 297 static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 298 vm_offset_t, vm_offset_t, u_int, int); 299 static void pmap_pvo_remove(struct pvo_entry *, int); 300 static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 301 static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 302 303 /* 304 * Utility routines. 305 */ 306 static struct pvo_entry *pmap_rkva_alloc(void); 307 static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 308 struct pte *, int *); 309 static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 310 static void pmap_syncicache(vm_offset_t, vm_size_t); 311 static boolean_t pmap_query_bit(vm_page_t, int); 312 static u_int pmap_clear_bit(vm_page_t, int, int *); 313 static void tlbia(void); 314 315 static __inline int 316 va_to_sr(u_int *sr, vm_offset_t va) 317 { 318 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 319 } 320 321 static __inline u_int 322 va_to_pteg(u_int sr, vm_offset_t addr) 323 { 324 u_int hash; 325 326 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 327 ADDR_PIDX_SHFT); 328 return (hash & pmap_pteg_mask); 329 } 330 331 static __inline struct pvo_head * 332 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 333 { 334 struct vm_page *pg; 335 336 pg = PHYS_TO_VM_PAGE(pa); 337 338 if (pg_p != NULL) 339 *pg_p = pg; 340 341 if (pg == NULL) 342 return (&pmap_pvo_unmanaged); 343 344 return (&pg->md.mdpg_pvoh); 345 } 346 347 static __inline struct pvo_head * 348 vm_page_to_pvoh(vm_page_t m) 349 { 350 351 return (&m->md.mdpg_pvoh); 352 } 353 354 static __inline void 355 pmap_attr_clear(vm_page_t m, int ptebit) 356 { 357 358 m->md.mdpg_attrs &= ~ptebit; 359 } 360 361 static __inline int 362 pmap_attr_fetch(vm_page_t m) 363 { 364 365 return (m->md.mdpg_attrs); 366 } 367 368 static __inline void 369 pmap_attr_save(vm_page_t m, int ptebit) 370 { 371 372 m->md.mdpg_attrs |= ptebit; 373 } 374 375 static __inline int 376 pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 377 { 378 if (pt->pte_hi == pvo_pt->pte_hi) 379 return (1); 380 381 return (0); 382 } 383 384 static __inline int 385 pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 386 { 387 return (pt->pte_hi & ~PTE_VALID) == 388 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 389 ((va >> ADDR_API_SHFT) & PTE_API) | which); 390 } 391 392 static __inline void 393 pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 394 { 395 /* 396 * Construct a PTE. Default to IMB initially. Valid bit only gets 397 * set when the real pte is set in memory. 398 * 399 * Note: Don't set the valid bit for correct operation of tlb update. 400 */ 401 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 402 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 403 pt->pte_lo = pte_lo; 404 } 405 406 static __inline void 407 pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 408 { 409 410 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 411 } 412 413 static __inline void 414 pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 415 { 416 417 /* 418 * As shown in Section 7.6.3.2.3 419 */ 420 pt->pte_lo &= ~ptebit; 421 TLBIE(va); 422 EIEIO(); 423 TLBSYNC(); 424 SYNC(); 425 } 426 427 static __inline void 428 pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 429 { 430 431 pvo_pt->pte_hi |= PTE_VALID; 432 433 /* 434 * Update the PTE as defined in section 7.6.3.1. 435 * Note that the REF/CHG bits are from pvo_pt and thus should havce 436 * been saved so this routine can restore them (if desired). 437 */ 438 pt->pte_lo = pvo_pt->pte_lo; 439 EIEIO(); 440 pt->pte_hi = pvo_pt->pte_hi; 441 SYNC(); 442 pmap_pte_valid++; 443 } 444 445 static __inline void 446 pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 447 { 448 449 pvo_pt->pte_hi &= ~PTE_VALID; 450 451 /* 452 * Force the reg & chg bits back into the PTEs. 453 */ 454 SYNC(); 455 456 /* 457 * Invalidate the pte. 458 */ 459 pt->pte_hi &= ~PTE_VALID; 460 461 SYNC(); 462 TLBIE(va); 463 EIEIO(); 464 TLBSYNC(); 465 SYNC(); 466 467 /* 468 * Save the reg & chg bits. 469 */ 470 pmap_pte_synch(pt, pvo_pt); 471 pmap_pte_valid--; 472 } 473 474 static __inline void 475 pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 476 { 477 478 /* 479 * Invalidate the PTE 480 */ 481 pmap_pte_unset(pt, pvo_pt, va); 482 pmap_pte_set(pt, pvo_pt); 483 } 484 485 /* 486 * Quick sort callout for comparing memory regions. 487 */ 488 static int mr_cmp(const void *a, const void *b); 489 static int om_cmp(const void *a, const void *b); 490 491 static int 492 mr_cmp(const void *a, const void *b) 493 { 494 const struct mem_region *regiona; 495 const struct mem_region *regionb; 496 497 regiona = a; 498 regionb = b; 499 if (regiona->mr_start < regionb->mr_start) 500 return (-1); 501 else if (regiona->mr_start > regionb->mr_start) 502 return (1); 503 else 504 return (0); 505 } 506 507 static int 508 om_cmp(const void *a, const void *b) 509 { 510 const struct ofw_map *mapa; 511 const struct ofw_map *mapb; 512 513 mapa = a; 514 mapb = b; 515 if (mapa->om_pa < mapb->om_pa) 516 return (-1); 517 else if (mapa->om_pa > mapb->om_pa) 518 return (1); 519 else 520 return (0); 521 } 522 523 void 524 pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 525 { 526 ihandle_t mmui; 527 phandle_t chosen, mmu; 528 int sz; 529 int i, j; 530 int ofw_mappings; 531 vm_size_t size, physsz; 532 vm_offset_t pa, va, off; 533 u_int batl, batu; 534 535 /* 536 * Set up BAT0 to map the lowest 256 MB area 537 */ 538 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 539 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 540 541 /* 542 * Map PCI memory space. 543 */ 544 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 545 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 546 547 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 548 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 549 550 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 551 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 552 553 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 554 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 555 556 /* 557 * Map obio devices. 558 */ 559 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 560 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 561 562 /* 563 * Use an IBAT and a DBAT to map the bottom segment of memory 564 * where we are. 565 */ 566 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 567 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 568 __asm ("mtibatu 0,%0; mtibatl 0,%1; isync; \n" 569 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 570 :: "r"(batu), "r"(batl)); 571 572 #if 0 573 /* map frame buffer */ 574 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 575 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 576 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 577 :: "r"(batu), "r"(batl)); 578 #endif 579 580 #if 1 581 /* map pci space */ 582 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 583 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 584 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 585 :: "r"(batu), "r"(batl)); 586 #endif 587 588 /* 589 * Set the start and end of kva. 590 */ 591 virtual_avail = VM_MIN_KERNEL_ADDRESS; 592 virtual_end = VM_MAX_KERNEL_ADDRESS; 593 594 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 595 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 596 597 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 598 for (i = 0; i < pregions_sz; i++) { 599 vm_offset_t pa; 600 vm_offset_t end; 601 602 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 603 pregions[i].mr_start, 604 pregions[i].mr_start + pregions[i].mr_size, 605 pregions[i].mr_size); 606 /* 607 * Install entries into the BAT table to allow all 608 * of physmem to be convered by on-demand BAT entries. 609 * The loop will sometimes set the same battable element 610 * twice, but that's fine since they won't be used for 611 * a while yet. 612 */ 613 pa = pregions[i].mr_start & 0xf0000000; 614 end = pregions[i].mr_start + pregions[i].mr_size; 615 do { 616 u_int n = pa >> ADDR_SR_SHFT; 617 618 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 619 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 620 pa += SEGMENT_LENGTH; 621 } while (pa < end); 622 } 623 624 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 625 panic("pmap_bootstrap: phys_avail too small"); 626 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 627 phys_avail_count = 0; 628 physsz = 0; 629 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 630 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 631 regions[i].mr_start + regions[i].mr_size, 632 regions[i].mr_size); 633 phys_avail[j] = regions[i].mr_start; 634 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 635 phys_avail_count++; 636 physsz += regions[i].mr_size; 637 } 638 physmem = btoc(physsz); 639 640 /* 641 * Allocate PTEG table. 642 */ 643 #ifdef PTEGCOUNT 644 pmap_pteg_count = PTEGCOUNT; 645 #else 646 pmap_pteg_count = 0x1000; 647 648 while (pmap_pteg_count < physmem) 649 pmap_pteg_count <<= 1; 650 651 pmap_pteg_count >>= 1; 652 #endif /* PTEGCOUNT */ 653 654 size = pmap_pteg_count * sizeof(struct pteg); 655 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 656 size); 657 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 658 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 659 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 660 pmap_pteg_mask = pmap_pteg_count - 1; 661 662 /* 663 * Allocate pv/overflow lists. 664 */ 665 size = sizeof(struct pvo_head) * pmap_pteg_count; 666 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 667 PAGE_SIZE); 668 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 669 for (i = 0; i < pmap_pteg_count; i++) 670 LIST_INIT(&pmap_pvo_table[i]); 671 672 /* 673 * Allocate the message buffer. 674 */ 675 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 676 677 /* 678 * Initialise the unmanaged pvo pool. 679 */ 680 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 681 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 682 pmap_bpvo_pool_index = 0; 683 684 /* 685 * Make sure kernel vsid is allocated as well as VSID 0. 686 */ 687 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 688 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 689 pmap_vsid_bitmap[0] |= 1; 690 691 /* 692 * Set up the OpenFirmware pmap and add it's mappings. 693 */ 694 pmap_pinit(&ofw_pmap); 695 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 696 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 697 if ((chosen = OF_finddevice("/chosen")) == -1) 698 panic("pmap_bootstrap: can't find /chosen"); 699 OF_getprop(chosen, "mmu", &mmui, 4); 700 if ((mmu = OF_instance_to_package(mmui)) == -1) 701 panic("pmap_bootstrap: can't get mmu package"); 702 if ((sz = OF_getproplen(mmu, "translations")) == -1) 703 panic("pmap_bootstrap: can't get ofw translation count"); 704 translations = NULL; 705 for (i = 0; phys_avail[i] != 0; i += 2) { 706 if (phys_avail[i + 1] >= sz) { 707 translations = (struct ofw_map *)phys_avail[i]; 708 break; 709 } 710 } 711 if (translations == NULL) 712 panic("pmap_bootstrap: no space to copy translations"); 713 bzero(translations, sz); 714 if (OF_getprop(mmu, "translations", translations, sz) == -1) 715 panic("pmap_bootstrap: can't get ofw translations"); 716 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 717 sz /= sizeof(*translations); 718 qsort(translations, sz, sizeof (*translations), om_cmp); 719 for (i = 0, ofw_mappings = 0; i < sz; i++) { 720 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 721 translations[i].om_pa, translations[i].om_va, 722 translations[i].om_len); 723 724 /* 725 * If the mapping is 1:1, let the RAM and device on-demand 726 * BAT tables take care of the translation. 727 */ 728 if (translations[i].om_va == translations[i].om_pa) 729 continue; 730 731 /* Enter the pages */ 732 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 733 struct vm_page m; 734 735 m.phys_addr = translations[i].om_pa + off; 736 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 737 VM_PROT_ALL, 1); 738 ofw_mappings++; 739 } 740 } 741 #ifdef SMP 742 TLBSYNC(); 743 #endif 744 745 /* 746 * Initialize the kernel pmap (which is statically allocated). 747 */ 748 for (i = 0; i < 16; i++) { 749 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 750 } 751 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 752 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL_SEGMENT; 753 kernel_pmap->pm_active = ~0; 754 755 /* 756 * Allocate a kernel stack with a guard page for thread0 and map it 757 * into the kernel page map. 758 */ 759 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 760 kstack0_phys = pa; 761 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 762 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 763 kstack0); 764 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 765 for (i = 0; i < KSTACK_PAGES; i++) { 766 pa = kstack0_phys + i * PAGE_SIZE; 767 va = kstack0 + i * PAGE_SIZE; 768 pmap_kenter(va, pa); 769 TLBIE(va); 770 } 771 772 /* 773 * Calculate the last available physical address. 774 */ 775 for (i = 0; phys_avail[i + 2] != 0; i += 2) 776 ; 777 Maxmem = powerpc_btop(phys_avail[i + 1]); 778 779 /* 780 * Allocate virtual address space for the message buffer. 781 */ 782 msgbufp = (struct msgbuf *)virtual_avail; 783 virtual_avail += round_page(MSGBUF_SIZE); 784 785 /* 786 * Initialize hardware. 787 */ 788 for (i = 0; i < 16; i++) { 789 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 790 } 791 __asm __volatile ("mtsr %0,%1" 792 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 793 __asm __volatile ("sync; mtsdr1 %0; isync" 794 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 795 tlbia(); 796 797 pmap_bootstrapped++; 798 } 799 800 /* 801 * Activate a user pmap. The pmap must be activated before it's address 802 * space can be accessed in any way. 803 */ 804 void 805 pmap_activate(struct thread *td) 806 { 807 pmap_t pm, pmr; 808 809 /* 810 * Load all the data we need up front to encourage the compiler to 811 * not issue any loads while we have interrupts disabled below. 812 */ 813 pm = &td->td_proc->p_vmspace->vm_pmap; 814 815 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 816 pmr = pm; 817 818 pm->pm_active |= PCPU_GET(cpumask); 819 PCPU_SET(curpmap, pmr); 820 } 821 822 void 823 pmap_deactivate(struct thread *td) 824 { 825 pmap_t pm; 826 827 pm = &td->td_proc->p_vmspace->vm_pmap; 828 pm->pm_active &= ~(PCPU_GET(cpumask)); 829 PCPU_SET(curpmap, NULL); 830 } 831 832 vm_offset_t 833 pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 834 { 835 836 return (va); 837 } 838 839 void 840 pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 841 { 842 struct pvo_entry *pvo; 843 844 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 845 846 if (pvo != NULL) { 847 if (wired) { 848 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 849 pm->pm_stats.wired_count++; 850 pvo->pvo_vaddr |= PVO_WIRED; 851 } else { 852 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 853 pm->pm_stats.wired_count--; 854 pvo->pvo_vaddr &= ~PVO_WIRED; 855 } 856 } 857 } 858 859 void 860 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 861 vm_size_t len, vm_offset_t src_addr) 862 { 863 864 /* 865 * This is not needed as it's mainly an optimisation. 866 * It may want to be implemented later though. 867 */ 868 } 869 870 void 871 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 872 { 873 vm_offset_t dst; 874 vm_offset_t src; 875 876 dst = VM_PAGE_TO_PHYS(mdst); 877 src = VM_PAGE_TO_PHYS(msrc); 878 879 kcopy((void *)src, (void *)dst, PAGE_SIZE); 880 } 881 882 /* 883 * Zero a page of physical memory by temporarily mapping it into the tlb. 884 */ 885 void 886 pmap_zero_page(vm_page_t m) 887 { 888 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 889 caddr_t va; 890 891 if (pa < SEGMENT_LENGTH) { 892 va = (caddr_t) pa; 893 } else if (pmap_initialized) { 894 if (pmap_pvo_zeropage == NULL) 895 pmap_pvo_zeropage = pmap_rkva_alloc(); 896 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 897 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 898 } else { 899 panic("pmap_zero_page: can't zero pa %#x", pa); 900 } 901 902 bzero(va, PAGE_SIZE); 903 904 if (pa >= SEGMENT_LENGTH) 905 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 906 } 907 908 void 909 pmap_zero_page_area(vm_page_t m, int off, int size) 910 { 911 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 912 caddr_t va; 913 914 if (pa < SEGMENT_LENGTH) { 915 va = (caddr_t) pa; 916 } else if (pmap_initialized) { 917 if (pmap_pvo_zeropage == NULL) 918 pmap_pvo_zeropage = pmap_rkva_alloc(); 919 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 920 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 921 } else { 922 panic("pmap_zero_page: can't zero pa %#x", pa); 923 } 924 925 bzero(va + off, size); 926 927 if (pa >= SEGMENT_LENGTH) 928 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 929 } 930 931 void 932 pmap_zero_page_idle(vm_page_t m) 933 { 934 935 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 936 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 937 mtx_lock(&Giant); 938 pmap_zero_page(m); 939 mtx_unlock(&Giant); 940 } 941 942 /* 943 * Map the given physical page at the specified virtual address in the 944 * target pmap with the protection requested. If specified the page 945 * will be wired down. 946 */ 947 void 948 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 949 boolean_t wired) 950 { 951 struct pvo_head *pvo_head; 952 uma_zone_t zone; 953 vm_page_t pg; 954 u_int pte_lo, pvo_flags, was_exec, i; 955 int error; 956 957 if (!pmap_initialized) { 958 pvo_head = &pmap_pvo_kunmanaged; 959 zone = pmap_upvo_zone; 960 pvo_flags = 0; 961 pg = NULL; 962 was_exec = PTE_EXEC; 963 } else { 964 pvo_head = vm_page_to_pvoh(m); 965 pg = m; 966 zone = pmap_mpvo_zone; 967 pvo_flags = PVO_MANAGED; 968 was_exec = 0; 969 } 970 971 /* 972 * If this is a managed page, and it's the first reference to the page, 973 * clear the execness of the page. Otherwise fetch the execness. 974 */ 975 if (pg != NULL) { 976 if (LIST_EMPTY(pvo_head)) { 977 pmap_attr_clear(pg, PTE_EXEC); 978 } else { 979 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 980 } 981 } 982 983 984 /* 985 * Assume the page is cache inhibited and access is guarded unless 986 * it's in our available memory array. 987 */ 988 pte_lo = PTE_I | PTE_G; 989 for (i = 0; i < pregions_sz; i++) { 990 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 991 (VM_PAGE_TO_PHYS(m) < 992 (pregions[i].mr_start + pregions[i].mr_size))) { 993 pte_lo &= ~(PTE_I | PTE_G); 994 break; 995 } 996 } 997 998 if (prot & VM_PROT_WRITE) 999 pte_lo |= PTE_BW; 1000 else 1001 pte_lo |= PTE_BR; 1002 1003 pvo_flags |= (prot & VM_PROT_EXECUTE); 1004 1005 if (wired) 1006 pvo_flags |= PVO_WIRED; 1007 1008 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1009 pte_lo, pvo_flags); 1010 1011 /* 1012 * Flush the real page from the instruction cache if this page is 1013 * mapped executable and cacheable and was not previously mapped (or 1014 * was not mapped executable). 1015 */ 1016 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1017 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1018 /* 1019 * Flush the real memory from the cache. 1020 */ 1021 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1022 if (pg != NULL) 1023 pmap_attr_save(pg, PTE_EXEC); 1024 } 1025 1026 /* XXX syncicache always until problems are sorted */ 1027 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1028 } 1029 1030 vm_page_t 1031 pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_page_t mpte) 1032 { 1033 1034 pmap_enter(pm, va, m, VM_PROT_READ | VM_PROT_EXECUTE, FALSE); 1035 return (NULL); 1036 } 1037 1038 vm_paddr_t 1039 pmap_extract(pmap_t pm, vm_offset_t va) 1040 { 1041 struct pvo_entry *pvo; 1042 1043 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1044 1045 if (pvo != NULL) { 1046 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1047 } 1048 1049 return (0); 1050 } 1051 1052 /* 1053 * Atomically extract and hold the physical page with the given 1054 * pmap and virtual address pair if that mapping permits the given 1055 * protection. 1056 */ 1057 vm_page_t 1058 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1059 { 1060 vm_paddr_t pa; 1061 vm_page_t m; 1062 1063 m = NULL; 1064 mtx_lock(&Giant); 1065 if ((pa = pmap_extract(pmap, va)) != 0) { 1066 m = PHYS_TO_VM_PAGE(pa); 1067 vm_page_lock_queues(); 1068 vm_page_hold(m); 1069 vm_page_unlock_queues(); 1070 } 1071 mtx_unlock(&Giant); 1072 return (m); 1073 } 1074 1075 /* 1076 * Grow the number of kernel page table entries. Unneeded. 1077 */ 1078 void 1079 pmap_growkernel(vm_offset_t addr) 1080 { 1081 } 1082 1083 void 1084 pmap_init(void) 1085 { 1086 1087 CTR0(KTR_PMAP, "pmap_init"); 1088 1089 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1090 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1091 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1092 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1093 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1094 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1095 pmap_initialized = TRUE; 1096 } 1097 1098 void 1099 pmap_init2(void) 1100 { 1101 1102 CTR0(KTR_PMAP, "pmap_init2"); 1103 } 1104 1105 boolean_t 1106 pmap_is_modified(vm_page_t m) 1107 { 1108 1109 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1110 return (FALSE); 1111 1112 return (pmap_query_bit(m, PTE_CHG)); 1113 } 1114 1115 /* 1116 * pmap_is_prefaultable: 1117 * 1118 * Return whether or not the specified virtual address is elgible 1119 * for prefault. 1120 */ 1121 boolean_t 1122 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 1123 { 1124 1125 return (FALSE); 1126 } 1127 1128 void 1129 pmap_clear_reference(vm_page_t m) 1130 { 1131 1132 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1133 return; 1134 pmap_clear_bit(m, PTE_REF, NULL); 1135 } 1136 1137 void 1138 pmap_clear_modify(vm_page_t m) 1139 { 1140 1141 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1142 return; 1143 pmap_clear_bit(m, PTE_CHG, NULL); 1144 } 1145 1146 /* 1147 * pmap_ts_referenced: 1148 * 1149 * Return a count of reference bits for a page, clearing those bits. 1150 * It is not necessary for every reference bit to be cleared, but it 1151 * is necessary that 0 only be returned when there are truly no 1152 * reference bits set. 1153 * 1154 * XXX: The exact number of bits to check and clear is a matter that 1155 * should be tested and standardized at some point in the future for 1156 * optimal aging of shared pages. 1157 */ 1158 int 1159 pmap_ts_referenced(vm_page_t m) 1160 { 1161 int count; 1162 1163 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1164 return (0); 1165 1166 count = pmap_clear_bit(m, PTE_REF, NULL); 1167 1168 return (count); 1169 } 1170 1171 /* 1172 * Map a wired page into kernel virtual address space. 1173 */ 1174 void 1175 pmap_kenter(vm_offset_t va, vm_offset_t pa) 1176 { 1177 u_int pte_lo; 1178 int error; 1179 int i; 1180 1181 #if 0 1182 if (va < VM_MIN_KERNEL_ADDRESS) 1183 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1184 va); 1185 #endif 1186 1187 pte_lo = PTE_I | PTE_G; 1188 for (i = 0; i < pregions_sz; i++) { 1189 if ((pa >= pregions[i].mr_start) && 1190 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1191 pte_lo &= ~(PTE_I | PTE_G); 1192 break; 1193 } 1194 } 1195 1196 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1197 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1198 1199 if (error != 0 && error != ENOENT) 1200 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1201 pa, error); 1202 1203 /* 1204 * Flush the real memory from the instruction cache. 1205 */ 1206 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1207 pmap_syncicache(pa, PAGE_SIZE); 1208 } 1209 } 1210 1211 /* 1212 * Extract the physical page address associated with the given kernel virtual 1213 * address. 1214 */ 1215 vm_offset_t 1216 pmap_kextract(vm_offset_t va) 1217 { 1218 struct pvo_entry *pvo; 1219 1220 #ifdef UMA_MD_SMALL_ALLOC 1221 /* 1222 * Allow direct mappings 1223 */ 1224 if (va < VM_MIN_KERNEL_ADDRESS) { 1225 return (va); 1226 } 1227 #endif 1228 1229 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1230 KASSERT(pvo != NULL, ("pmap_kextract: no addr found")); 1231 if (pvo == NULL) { 1232 return (0); 1233 } 1234 1235 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1236 } 1237 1238 /* 1239 * Remove a wired page from kernel virtual address space. 1240 */ 1241 void 1242 pmap_kremove(vm_offset_t va) 1243 { 1244 1245 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1246 } 1247 1248 /* 1249 * Map a range of physical addresses into kernel virtual address space. 1250 * 1251 * The value passed in *virt is a suggested virtual address for the mapping. 1252 * Architectures which can support a direct-mapped physical to virtual region 1253 * can return the appropriate address within that region, leaving '*virt' 1254 * unchanged. We cannot and therefore do not; *virt is updated with the 1255 * first usable address after the mapped region. 1256 */ 1257 vm_offset_t 1258 pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1259 { 1260 vm_offset_t sva, va; 1261 1262 sva = *virt; 1263 va = sva; 1264 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1265 pmap_kenter(va, pa_start); 1266 *virt = va; 1267 return (sva); 1268 } 1269 1270 int 1271 pmap_mincore(pmap_t pmap, vm_offset_t addr) 1272 { 1273 TODO; 1274 return (0); 1275 } 1276 1277 void 1278 pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1279 vm_pindex_t pindex, vm_size_t size) 1280 { 1281 1282 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 1283 KASSERT(object->type == OBJT_DEVICE, 1284 ("pmap_object_init_pt: non-device object")); 1285 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1286 ("pmap_object_init_pt: non current pmap")); 1287 } 1288 1289 /* 1290 * Lower the permission for all mappings to a given page. 1291 */ 1292 void 1293 pmap_page_protect(vm_page_t m, vm_prot_t prot) 1294 { 1295 struct pvo_head *pvo_head; 1296 struct pvo_entry *pvo, *next_pvo; 1297 struct pte *pt; 1298 1299 /* 1300 * Since the routine only downgrades protection, if the 1301 * maximal protection is desired, there isn't any change 1302 * to be made. 1303 */ 1304 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1305 (VM_PROT_READ|VM_PROT_WRITE)) 1306 return; 1307 1308 pvo_head = vm_page_to_pvoh(m); 1309 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1310 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1311 PMAP_PVO_CHECK(pvo); /* sanity check */ 1312 1313 /* 1314 * Downgrading to no mapping at all, we just remove the entry. 1315 */ 1316 if ((prot & VM_PROT_READ) == 0) { 1317 pmap_pvo_remove(pvo, -1); 1318 continue; 1319 } 1320 1321 /* 1322 * If EXEC permission is being revoked, just clear the flag 1323 * in the PVO. 1324 */ 1325 if ((prot & VM_PROT_EXECUTE) == 0) 1326 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1327 1328 /* 1329 * If this entry is already RO, don't diddle with the page 1330 * table. 1331 */ 1332 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1333 PMAP_PVO_CHECK(pvo); 1334 continue; 1335 } 1336 1337 /* 1338 * Grab the PTE before we diddle the bits so pvo_to_pte can 1339 * verify the pte contents are as expected. 1340 */ 1341 pt = pmap_pvo_to_pte(pvo, -1); 1342 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1343 pvo->pvo_pte.pte_lo |= PTE_BR; 1344 if (pt != NULL) 1345 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1346 PMAP_PVO_CHECK(pvo); /* sanity check */ 1347 } 1348 } 1349 1350 /* 1351 * Returns true if the pmap's pv is one of the first 1352 * 16 pvs linked to from this page. This count may 1353 * be changed upwards or downwards in the future; it 1354 * is only necessary that true be returned for a small 1355 * subset of pmaps for proper page aging. 1356 */ 1357 boolean_t 1358 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1359 { 1360 int loops; 1361 struct pvo_entry *pvo; 1362 1363 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 1364 return FALSE; 1365 1366 loops = 0; 1367 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1368 if (pvo->pvo_pmap == pmap) 1369 return (TRUE); 1370 if (++loops >= 16) 1371 break; 1372 } 1373 1374 return (FALSE); 1375 } 1376 1377 static u_int pmap_vsidcontext; 1378 1379 void 1380 pmap_pinit(pmap_t pmap) 1381 { 1382 int i, mask; 1383 u_int entropy; 1384 1385 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("pmap_pinit: virt pmap")); 1386 1387 entropy = 0; 1388 __asm __volatile("mftb %0" : "=r"(entropy)); 1389 1390 /* 1391 * Allocate some segment registers for this pmap. 1392 */ 1393 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1394 u_int hash, n; 1395 1396 /* 1397 * Create a new value by mutiplying by a prime and adding in 1398 * entropy from the timebase register. This is to make the 1399 * VSID more random so that the PT hash function collides 1400 * less often. (Note that the prime casues gcc to do shifts 1401 * instead of a multiply.) 1402 */ 1403 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1404 hash = pmap_vsidcontext & (NPMAPS - 1); 1405 if (hash == 0) /* 0 is special, avoid it */ 1406 continue; 1407 n = hash >> 5; 1408 mask = 1 << (hash & (VSID_NBPW - 1)); 1409 hash = (pmap_vsidcontext & 0xfffff); 1410 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1411 /* anything free in this bucket? */ 1412 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1413 entropy = (pmap_vsidcontext >> 20); 1414 continue; 1415 } 1416 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1417 mask = 1 << i; 1418 hash &= 0xfffff & ~(VSID_NBPW - 1); 1419 hash |= i; 1420 } 1421 pmap_vsid_bitmap[n] |= mask; 1422 for (i = 0; i < 16; i++) 1423 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1424 return; 1425 } 1426 1427 panic("pmap_pinit: out of segments"); 1428 } 1429 1430 /* 1431 * Initialize the pmap associated with process 0. 1432 */ 1433 void 1434 pmap_pinit0(pmap_t pm) 1435 { 1436 1437 pmap_pinit(pm); 1438 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1439 } 1440 1441 /* 1442 * Set the physical protection on the specified range of this map as requested. 1443 */ 1444 void 1445 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1446 { 1447 struct pvo_entry *pvo; 1448 struct pte *pt; 1449 int pteidx; 1450 1451 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1452 eva, prot); 1453 1454 1455 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1456 ("pmap_protect: non current pmap")); 1457 1458 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1459 pmap_remove(pm, sva, eva); 1460 return; 1461 } 1462 1463 vm_page_lock_queues(); 1464 for (; sva < eva; sva += PAGE_SIZE) { 1465 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1466 if (pvo == NULL) 1467 continue; 1468 1469 if ((prot & VM_PROT_EXECUTE) == 0) 1470 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1471 1472 /* 1473 * Grab the PTE pointer before we diddle with the cached PTE 1474 * copy. 1475 */ 1476 pt = pmap_pvo_to_pte(pvo, pteidx); 1477 /* 1478 * Change the protection of the page. 1479 */ 1480 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1481 pvo->pvo_pte.pte_lo |= PTE_BR; 1482 1483 /* 1484 * If the PVO is in the page table, update that pte as well. 1485 */ 1486 if (pt != NULL) 1487 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1488 } 1489 vm_page_unlock_queues(); 1490 } 1491 1492 /* 1493 * Map a list of wired pages into kernel virtual address space. This is 1494 * intended for temporary mappings which do not need page modification or 1495 * references recorded. Existing mappings in the region are overwritten. 1496 */ 1497 void 1498 pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1499 { 1500 vm_offset_t va; 1501 1502 va = sva; 1503 while (count-- > 0) { 1504 pmap_kenter(va, VM_PAGE_TO_PHYS(*m)); 1505 va += PAGE_SIZE; 1506 m++; 1507 } 1508 } 1509 1510 /* 1511 * Remove page mappings from kernel virtual address space. Intended for 1512 * temporary mappings entered by pmap_qenter. 1513 */ 1514 void 1515 pmap_qremove(vm_offset_t sva, int count) 1516 { 1517 vm_offset_t va; 1518 1519 va = sva; 1520 while (count-- > 0) { 1521 pmap_kremove(va); 1522 va += PAGE_SIZE; 1523 } 1524 } 1525 1526 void 1527 pmap_release(pmap_t pmap) 1528 { 1529 int idx, mask; 1530 1531 /* 1532 * Free segment register's VSID 1533 */ 1534 if (pmap->pm_sr[0] == 0) 1535 panic("pmap_release"); 1536 1537 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1538 mask = 1 << (idx % VSID_NBPW); 1539 idx /= VSID_NBPW; 1540 pmap_vsid_bitmap[idx] &= ~mask; 1541 } 1542 1543 /* 1544 * Remove the given range of addresses from the specified map. 1545 */ 1546 void 1547 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1548 { 1549 struct pvo_entry *pvo; 1550 int pteidx; 1551 1552 vm_page_lock_queues(); 1553 for (; sva < eva; sva += PAGE_SIZE) { 1554 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1555 if (pvo != NULL) { 1556 pmap_pvo_remove(pvo, pteidx); 1557 } 1558 } 1559 vm_page_unlock_queues(); 1560 } 1561 1562 /* 1563 * Remove physical page from all pmaps in which it resides. pmap_pvo_remove() 1564 * will reflect changes in pte's back to the vm_page. 1565 */ 1566 void 1567 pmap_remove_all(vm_page_t m) 1568 { 1569 struct pvo_head *pvo_head; 1570 struct pvo_entry *pvo, *next_pvo; 1571 1572 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1573 1574 pvo_head = vm_page_to_pvoh(m); 1575 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1576 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1577 1578 PMAP_PVO_CHECK(pvo); /* sanity check */ 1579 pmap_pvo_remove(pvo, -1); 1580 } 1581 vm_page_flag_clear(m, PG_WRITEABLE); 1582 } 1583 1584 /* 1585 * Remove all pages from specified address space, this aids process exit 1586 * speeds. This is much faster than pmap_remove in the case of running down 1587 * an entire address space. Only works for the current pmap. 1588 */ 1589 void 1590 pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1591 { 1592 } 1593 1594 /* 1595 * Allocate a physical page of memory directly from the phys_avail map. 1596 * Can only be called from pmap_bootstrap before avail start and end are 1597 * calculated. 1598 */ 1599 static vm_offset_t 1600 pmap_bootstrap_alloc(vm_size_t size, u_int align) 1601 { 1602 vm_offset_t s, e; 1603 int i, j; 1604 1605 size = round_page(size); 1606 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1607 if (align != 0) 1608 s = (phys_avail[i] + align - 1) & ~(align - 1); 1609 else 1610 s = phys_avail[i]; 1611 e = s + size; 1612 1613 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1614 continue; 1615 1616 if (s == phys_avail[i]) { 1617 phys_avail[i] += size; 1618 } else if (e == phys_avail[i + 1]) { 1619 phys_avail[i + 1] -= size; 1620 } else { 1621 for (j = phys_avail_count * 2; j > i; j -= 2) { 1622 phys_avail[j] = phys_avail[j - 2]; 1623 phys_avail[j + 1] = phys_avail[j - 1]; 1624 } 1625 1626 phys_avail[i + 3] = phys_avail[i + 1]; 1627 phys_avail[i + 1] = s; 1628 phys_avail[i + 2] = e; 1629 phys_avail_count++; 1630 } 1631 1632 return (s); 1633 } 1634 panic("pmap_bootstrap_alloc: could not allocate memory"); 1635 } 1636 1637 /* 1638 * Return an unmapped pvo for a kernel virtual address. 1639 * Used by pmap functions that operate on physical pages. 1640 */ 1641 static struct pvo_entry * 1642 pmap_rkva_alloc(void) 1643 { 1644 struct pvo_entry *pvo; 1645 struct pte *pt; 1646 vm_offset_t kva; 1647 int pteidx; 1648 1649 if (pmap_rkva_count == 0) 1650 panic("pmap_rkva_alloc: no more reserved KVAs"); 1651 1652 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1653 pmap_kenter(kva, 0); 1654 1655 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1656 1657 if (pvo == NULL) 1658 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1659 1660 pt = pmap_pvo_to_pte(pvo, pteidx); 1661 1662 if (pt == NULL) 1663 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1664 1665 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1666 PVO_PTEGIDX_CLR(pvo); 1667 1668 pmap_pte_overflow++; 1669 1670 return (pvo); 1671 } 1672 1673 static void 1674 pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1675 int *depth_p) 1676 { 1677 struct pte *pt; 1678 1679 /* 1680 * If this pvo already has a valid pte, we need to save it so it can 1681 * be restored later. We then just reload the new PTE over the old 1682 * slot. 1683 */ 1684 if (saved_pt != NULL) { 1685 pt = pmap_pvo_to_pte(pvo, -1); 1686 1687 if (pt != NULL) { 1688 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1689 PVO_PTEGIDX_CLR(pvo); 1690 pmap_pte_overflow++; 1691 } 1692 1693 *saved_pt = pvo->pvo_pte; 1694 1695 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1696 } 1697 1698 pvo->pvo_pte.pte_lo |= pa; 1699 1700 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1701 panic("pmap_pa_map: could not spill pvo %p", pvo); 1702 1703 if (depth_p != NULL) 1704 (*depth_p)++; 1705 } 1706 1707 static void 1708 pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1709 { 1710 struct pte *pt; 1711 1712 pt = pmap_pvo_to_pte(pvo, -1); 1713 1714 if (pt != NULL) { 1715 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1716 PVO_PTEGIDX_CLR(pvo); 1717 pmap_pte_overflow++; 1718 } 1719 1720 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1721 1722 /* 1723 * If there is a saved PTE and it's valid, restore it and return. 1724 */ 1725 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1726 if (depth_p != NULL && --(*depth_p) == 0) 1727 panic("pmap_pa_unmap: restoring but depth == 0"); 1728 1729 pvo->pvo_pte = *saved_pt; 1730 1731 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1732 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1733 } 1734 } 1735 1736 static void 1737 pmap_syncicache(vm_offset_t pa, vm_size_t len) 1738 { 1739 __syncicache((void *)pa, len); 1740 } 1741 1742 static void 1743 tlbia(void) 1744 { 1745 caddr_t i; 1746 1747 SYNC(); 1748 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1749 TLBIE(i); 1750 EIEIO(); 1751 } 1752 TLBSYNC(); 1753 SYNC(); 1754 } 1755 1756 static int 1757 pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1758 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1759 { 1760 struct pvo_entry *pvo; 1761 u_int sr; 1762 int first; 1763 u_int ptegidx; 1764 int i; 1765 int bootstrap; 1766 1767 pmap_pvo_enter_calls++; 1768 first = 0; 1769 1770 bootstrap = 0; 1771 1772 /* 1773 * Compute the PTE Group index. 1774 */ 1775 va &= ~ADDR_POFF; 1776 sr = va_to_sr(pm->pm_sr, va); 1777 ptegidx = va_to_pteg(sr, va); 1778 1779 /* 1780 * Remove any existing mapping for this page. Reuse the pvo entry if 1781 * there is a mapping. 1782 */ 1783 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1784 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1785 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1786 (pvo->pvo_pte.pte_lo & PTE_PP) == 1787 (pte_lo & PTE_PP)) { 1788 return (0); 1789 } 1790 pmap_pvo_remove(pvo, -1); 1791 break; 1792 } 1793 } 1794 1795 /* 1796 * If we aren't overwriting a mapping, try to allocate. 1797 */ 1798 if (pmap_initialized) { 1799 pvo = uma_zalloc(zone, M_NOWAIT); 1800 } else { 1801 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1802 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1803 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1804 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1805 } 1806 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1807 pmap_bpvo_pool_index++; 1808 bootstrap = 1; 1809 } 1810 1811 if (pvo == NULL) { 1812 return (ENOMEM); 1813 } 1814 1815 pmap_pvo_entries++; 1816 pvo->pvo_vaddr = va; 1817 pvo->pvo_pmap = pm; 1818 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1819 pvo->pvo_vaddr &= ~ADDR_POFF; 1820 if (flags & VM_PROT_EXECUTE) 1821 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1822 if (flags & PVO_WIRED) 1823 pvo->pvo_vaddr |= PVO_WIRED; 1824 if (pvo_head != &pmap_pvo_kunmanaged) 1825 pvo->pvo_vaddr |= PVO_MANAGED; 1826 if (bootstrap) 1827 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1828 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1829 1830 /* 1831 * Remember if the list was empty and therefore will be the first 1832 * item. 1833 */ 1834 if (LIST_FIRST(pvo_head) == NULL) 1835 first = 1; 1836 1837 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1838 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1839 pvo->pvo_pmap->pm_stats.wired_count++; 1840 pvo->pvo_pmap->pm_stats.resident_count++; 1841 1842 /* 1843 * We hope this succeeds but it isn't required. 1844 */ 1845 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1846 if (i >= 0) { 1847 PVO_PTEGIDX_SET(pvo, i); 1848 } else { 1849 panic("pmap_pvo_enter: overflow"); 1850 pmap_pte_overflow++; 1851 } 1852 1853 return (first ? ENOENT : 0); 1854 } 1855 1856 static void 1857 pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1858 { 1859 struct pte *pt; 1860 1861 /* 1862 * If there is an active pte entry, we need to deactivate it (and 1863 * save the ref & cfg bits). 1864 */ 1865 pt = pmap_pvo_to_pte(pvo, pteidx); 1866 if (pt != NULL) { 1867 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1868 PVO_PTEGIDX_CLR(pvo); 1869 } else { 1870 pmap_pte_overflow--; 1871 } 1872 1873 /* 1874 * Update our statistics. 1875 */ 1876 pvo->pvo_pmap->pm_stats.resident_count--; 1877 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1878 pvo->pvo_pmap->pm_stats.wired_count--; 1879 1880 /* 1881 * Save the REF/CHG bits into their cache if the page is managed. 1882 */ 1883 if (pvo->pvo_vaddr & PVO_MANAGED) { 1884 struct vm_page *pg; 1885 1886 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1887 if (pg != NULL) { 1888 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 1889 (PTE_REF | PTE_CHG)); 1890 } 1891 } 1892 1893 /* 1894 * Remove this PVO from the PV list. 1895 */ 1896 LIST_REMOVE(pvo, pvo_vlink); 1897 1898 /* 1899 * Remove this from the overflow list and return it to the pool 1900 * if we aren't going to reuse it. 1901 */ 1902 LIST_REMOVE(pvo, pvo_olink); 1903 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1904 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 1905 pmap_upvo_zone, pvo); 1906 pmap_pvo_entries--; 1907 pmap_pvo_remove_calls++; 1908 } 1909 1910 static __inline int 1911 pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1912 { 1913 int pteidx; 1914 1915 /* 1916 * We can find the actual pte entry without searching by grabbing 1917 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1918 * noticing the HID bit. 1919 */ 1920 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1921 if (pvo->pvo_pte.pte_hi & PTE_HID) 1922 pteidx ^= pmap_pteg_mask * 8; 1923 1924 return (pteidx); 1925 } 1926 1927 static struct pvo_entry * 1928 pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1929 { 1930 struct pvo_entry *pvo; 1931 int ptegidx; 1932 u_int sr; 1933 1934 va &= ~ADDR_POFF; 1935 sr = va_to_sr(pm->pm_sr, va); 1936 ptegidx = va_to_pteg(sr, va); 1937 1938 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1939 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1940 if (pteidx_p) 1941 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 1942 return (pvo); 1943 } 1944 } 1945 1946 return (NULL); 1947 } 1948 1949 static struct pte * 1950 pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 1951 { 1952 struct pte *pt; 1953 1954 /* 1955 * If we haven't been supplied the ptegidx, calculate it. 1956 */ 1957 if (pteidx == -1) { 1958 int ptegidx; 1959 u_int sr; 1960 1961 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 1962 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1963 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 1964 } 1965 1966 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 1967 1968 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 1969 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 1970 "valid pte index", pvo); 1971 } 1972 1973 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 1974 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 1975 "pvo but no valid pte", pvo); 1976 } 1977 1978 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 1979 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 1980 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 1981 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 1982 } 1983 1984 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 1985 != 0) { 1986 panic("pmap_pvo_to_pte: pvo %p pte does not match " 1987 "pte %p in pmap_pteg_table", pvo, pt); 1988 } 1989 1990 return (pt); 1991 } 1992 1993 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 1994 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 1995 "pmap_pteg_table but valid in pvo", pvo, pt); 1996 } 1997 1998 return (NULL); 1999 } 2000 2001 /* 2002 * XXX: THIS STUFF SHOULD BE IN pte.c? 2003 */ 2004 int 2005 pmap_pte_spill(vm_offset_t addr) 2006 { 2007 struct pvo_entry *source_pvo, *victim_pvo; 2008 struct pvo_entry *pvo; 2009 int ptegidx, i, j; 2010 u_int sr; 2011 struct pteg *pteg; 2012 struct pte *pt; 2013 2014 pmap_pte_spills++; 2015 2016 sr = mfsrin(addr); 2017 ptegidx = va_to_pteg(sr, addr); 2018 2019 /* 2020 * Have to substitute some entry. Use the primary hash for this. 2021 * Use low bits of timebase as random generator. 2022 */ 2023 pteg = &pmap_pteg_table[ptegidx]; 2024 __asm __volatile("mftb %0" : "=r"(i)); 2025 i &= 7; 2026 pt = &pteg->pt[i]; 2027 2028 source_pvo = NULL; 2029 victim_pvo = NULL; 2030 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2031 /* 2032 * We need to find a pvo entry for this address. 2033 */ 2034 PMAP_PVO_CHECK(pvo); 2035 if (source_pvo == NULL && 2036 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2037 pvo->pvo_pte.pte_hi & PTE_HID)) { 2038 /* 2039 * Now found an entry to be spilled into the pteg. 2040 * The PTE is now valid, so we know it's active. 2041 */ 2042 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2043 2044 if (j >= 0) { 2045 PVO_PTEGIDX_SET(pvo, j); 2046 pmap_pte_overflow--; 2047 PMAP_PVO_CHECK(pvo); 2048 return (1); 2049 } 2050 2051 source_pvo = pvo; 2052 2053 if (victim_pvo != NULL) 2054 break; 2055 } 2056 2057 /* 2058 * We also need the pvo entry of the victim we are replacing 2059 * so save the R & C bits of the PTE. 2060 */ 2061 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2062 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2063 victim_pvo = pvo; 2064 if (source_pvo != NULL) 2065 break; 2066 } 2067 } 2068 2069 if (source_pvo == NULL) 2070 return (0); 2071 2072 if (victim_pvo == NULL) { 2073 if ((pt->pte_hi & PTE_HID) == 0) 2074 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2075 "entry", pt); 2076 2077 /* 2078 * If this is a secondary PTE, we need to search it's primary 2079 * pvo bucket for the matching PVO. 2080 */ 2081 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2082 pvo_olink) { 2083 PMAP_PVO_CHECK(pvo); 2084 /* 2085 * We also need the pvo entry of the victim we are 2086 * replacing so save the R & C bits of the PTE. 2087 */ 2088 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2089 victim_pvo = pvo; 2090 break; 2091 } 2092 } 2093 2094 if (victim_pvo == NULL) 2095 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2096 "entry", pt); 2097 } 2098 2099 /* 2100 * We are invalidating the TLB entry for the EA we are replacing even 2101 * though it's valid. If we don't, we lose any ref/chg bit changes 2102 * contained in the TLB entry. 2103 */ 2104 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2105 2106 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2107 pmap_pte_set(pt, &source_pvo->pvo_pte); 2108 2109 PVO_PTEGIDX_CLR(victim_pvo); 2110 PVO_PTEGIDX_SET(source_pvo, i); 2111 pmap_pte_replacements++; 2112 2113 PMAP_PVO_CHECK(victim_pvo); 2114 PMAP_PVO_CHECK(source_pvo); 2115 2116 return (1); 2117 } 2118 2119 static int 2120 pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2121 { 2122 struct pte *pt; 2123 int i; 2124 2125 /* 2126 * First try primary hash. 2127 */ 2128 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2129 if ((pt->pte_hi & PTE_VALID) == 0) { 2130 pvo_pt->pte_hi &= ~PTE_HID; 2131 pmap_pte_set(pt, pvo_pt); 2132 return (i); 2133 } 2134 } 2135 2136 /* 2137 * Now try secondary hash. 2138 */ 2139 ptegidx ^= pmap_pteg_mask; 2140 ptegidx++; 2141 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2142 if ((pt->pte_hi & PTE_VALID) == 0) { 2143 pvo_pt->pte_hi |= PTE_HID; 2144 pmap_pte_set(pt, pvo_pt); 2145 return (i); 2146 } 2147 } 2148 2149 panic("pmap_pte_insert: overflow"); 2150 return (-1); 2151 } 2152 2153 static boolean_t 2154 pmap_query_bit(vm_page_t m, int ptebit) 2155 { 2156 struct pvo_entry *pvo; 2157 struct pte *pt; 2158 2159 #if 0 2160 if (pmap_attr_fetch(m) & ptebit) 2161 return (TRUE); 2162 #endif 2163 2164 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2165 PMAP_PVO_CHECK(pvo); /* sanity check */ 2166 2167 /* 2168 * See if we saved the bit off. If so, cache it and return 2169 * success. 2170 */ 2171 if (pvo->pvo_pte.pte_lo & ptebit) { 2172 pmap_attr_save(m, ptebit); 2173 PMAP_PVO_CHECK(pvo); /* sanity check */ 2174 return (TRUE); 2175 } 2176 } 2177 2178 /* 2179 * No luck, now go through the hard part of looking at the PTEs 2180 * themselves. Sync so that any pending REF/CHG bits are flushed to 2181 * the PTEs. 2182 */ 2183 SYNC(); 2184 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2185 PMAP_PVO_CHECK(pvo); /* sanity check */ 2186 2187 /* 2188 * See if this pvo has a valid PTE. if so, fetch the 2189 * REF/CHG bits from the valid PTE. If the appropriate 2190 * ptebit is set, cache it and return success. 2191 */ 2192 pt = pmap_pvo_to_pte(pvo, -1); 2193 if (pt != NULL) { 2194 pmap_pte_synch(pt, &pvo->pvo_pte); 2195 if (pvo->pvo_pte.pte_lo & ptebit) { 2196 pmap_attr_save(m, ptebit); 2197 PMAP_PVO_CHECK(pvo); /* sanity check */ 2198 return (TRUE); 2199 } 2200 } 2201 } 2202 2203 return (FALSE); 2204 } 2205 2206 static u_int 2207 pmap_clear_bit(vm_page_t m, int ptebit, int *origbit) 2208 { 2209 u_int count; 2210 struct pvo_entry *pvo; 2211 struct pte *pt; 2212 int rv; 2213 2214 /* 2215 * Clear the cached value. 2216 */ 2217 rv = pmap_attr_fetch(m); 2218 pmap_attr_clear(m, ptebit); 2219 2220 /* 2221 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2222 * we can reset the right ones). note that since the pvo entries and 2223 * list heads are accessed via BAT0 and are never placed in the page 2224 * table, we don't have to worry about further accesses setting the 2225 * REF/CHG bits. 2226 */ 2227 SYNC(); 2228 2229 /* 2230 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2231 * valid pte clear the ptebit from the valid pte. 2232 */ 2233 count = 0; 2234 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2235 PMAP_PVO_CHECK(pvo); /* sanity check */ 2236 pt = pmap_pvo_to_pte(pvo, -1); 2237 if (pt != NULL) { 2238 pmap_pte_synch(pt, &pvo->pvo_pte); 2239 if (pvo->pvo_pte.pte_lo & ptebit) { 2240 count++; 2241 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2242 } 2243 } 2244 rv |= pvo->pvo_pte.pte_lo; 2245 pvo->pvo_pte.pte_lo &= ~ptebit; 2246 PMAP_PVO_CHECK(pvo); /* sanity check */ 2247 } 2248 2249 if (origbit != NULL) { 2250 *origbit = rv; 2251 } 2252 2253 return (count); 2254 } 2255 2256 /* 2257 * Return true if the physical range is encompassed by the battable[idx] 2258 */ 2259 static int 2260 pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2261 { 2262 u_int prot; 2263 u_int32_t start; 2264 u_int32_t end; 2265 u_int32_t bat_ble; 2266 2267 /* 2268 * Return immediately if not a valid mapping 2269 */ 2270 if (!battable[idx].batu & BAT_Vs) 2271 return (EINVAL); 2272 2273 /* 2274 * The BAT entry must be cache-inhibited, guarded, and r/w 2275 * so it can function as an i/o page 2276 */ 2277 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2278 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2279 return (EPERM); 2280 2281 /* 2282 * The address should be within the BAT range. Assume that the 2283 * start address in the BAT has the correct alignment (thus 2284 * not requiring masking) 2285 */ 2286 start = battable[idx].batl & BAT_PBS; 2287 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2288 end = start | (bat_ble << 15) | 0x7fff; 2289 2290 if ((pa < start) || ((pa + size) > end)) 2291 return (ERANGE); 2292 2293 return (0); 2294 } 2295 2296 2297 /* 2298 * Map a set of physical memory pages into the kernel virtual 2299 * address space. Return a pointer to where it is mapped. This 2300 * routine is intended to be used for mapping device memory, 2301 * NOT real memory. 2302 */ 2303 void * 2304 pmap_mapdev(vm_offset_t pa, vm_size_t size) 2305 { 2306 vm_offset_t va, tmpva, ppa, offset; 2307 int i; 2308 2309 ppa = trunc_page(pa); 2310 offset = pa & PAGE_MASK; 2311 size = roundup(offset + size, PAGE_SIZE); 2312 2313 GIANT_REQUIRED; 2314 2315 /* 2316 * If the physical address lies within a valid BAT table entry, 2317 * return the 1:1 mapping. This currently doesn't work 2318 * for regions that overlap 256M BAT segments. 2319 */ 2320 for (i = 0; i < 16; i++) { 2321 if (pmap_bat_mapped(i, pa, size) == 0) 2322 return ((void *) pa); 2323 } 2324 2325 va = kmem_alloc_nofault(kernel_map, size); 2326 if (!va) 2327 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2328 2329 for (tmpva = va; size > 0;) { 2330 pmap_kenter(tmpva, ppa); 2331 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2332 size -= PAGE_SIZE; 2333 tmpva += PAGE_SIZE; 2334 ppa += PAGE_SIZE; 2335 } 2336 2337 return ((void *)(va + offset)); 2338 } 2339 2340 void 2341 pmap_unmapdev(vm_offset_t va, vm_size_t size) 2342 { 2343 vm_offset_t base, offset; 2344 2345 /* 2346 * If this is outside kernel virtual space, then it's a 2347 * battable entry and doesn't require unmapping 2348 */ 2349 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2350 base = trunc_page(va); 2351 offset = va & PAGE_MASK; 2352 size = roundup(offset + size, PAGE_SIZE); 2353 kmem_free(kernel_map, base, size); 2354 } 2355 } 2356