1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/queue.h> 122 #include <sys/cpuset.h> 123 #include <sys/ktr.h> 124 #include <sys/lock.h> 125 #include <sys/msgbuf.h> 126 #include <sys/mutex.h> 127 #include <sys/proc.h> 128 #include <sys/sched.h> 129 #include <sys/sysctl.h> 130 #include <sys/systm.h> 131 #include <sys/vmmeter.h> 132 133 #include <dev/ofw/openfirm.h> 134 135 #include <vm/vm.h> 136 #include <vm/vm_param.h> 137 #include <vm/vm_kern.h> 138 #include <vm/vm_page.h> 139 #include <vm/vm_map.h> 140 #include <vm/vm_object.h> 141 #include <vm/vm_extern.h> 142 #include <vm/vm_pageout.h> 143 #include <vm/vm_pager.h> 144 #include <vm/uma.h> 145 146 #include <machine/cpu.h> 147 #include <machine/platform.h> 148 #include <machine/bat.h> 149 #include <machine/frame.h> 150 #include <machine/md_var.h> 151 #include <machine/psl.h> 152 #include <machine/pte.h> 153 #include <machine/smp.h> 154 #include <machine/sr.h> 155 #include <machine/mmuvar.h> 156 #include <machine/trap_aim.h> 157 158 #include "mmu_if.h" 159 160 #define MOEA_DEBUG 161 162 #define TODO panic("%s: not implemented", __func__); 163 164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 165 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 167 168 struct ofw_map { 169 vm_offset_t om_va; 170 vm_size_t om_len; 171 vm_offset_t om_pa; 172 u_int om_mode; 173 }; 174 175 /* 176 * Map of physical memory regions. 177 */ 178 static struct mem_region *regions; 179 static struct mem_region *pregions; 180 static u_int phys_avail_count; 181 static int regions_sz, pregions_sz; 182 static struct ofw_map *translations; 183 184 /* 185 * Lock for the pteg and pvo tables. 186 */ 187 struct mtx moea_table_mutex; 188 struct mtx moea_vsid_mutex; 189 190 /* tlbie instruction synchronization */ 191 static struct mtx tlbie_mtx; 192 193 /* 194 * PTEG data. 195 */ 196 static struct pteg *moea_pteg_table; 197 u_int moea_pteg_count; 198 u_int moea_pteg_mask; 199 200 /* 201 * PVO data. 202 */ 203 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 204 struct pvo_head moea_pvo_kunmanaged = 205 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 206 207 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 208 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 209 210 #define BPVO_POOL_SIZE 32768 211 static struct pvo_entry *moea_bpvo_pool; 212 static int moea_bpvo_pool_index = 0; 213 214 #define VSID_NBPW (sizeof(u_int32_t) * 8) 215 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 216 217 static boolean_t moea_initialized = FALSE; 218 219 /* 220 * Statistics. 221 */ 222 u_int moea_pte_valid = 0; 223 u_int moea_pte_overflow = 0; 224 u_int moea_pte_replacements = 0; 225 u_int moea_pvo_entries = 0; 226 u_int moea_pvo_enter_calls = 0; 227 u_int moea_pvo_remove_calls = 0; 228 u_int moea_pte_spills = 0; 229 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 230 0, ""); 231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 232 &moea_pte_overflow, 0, ""); 233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 234 &moea_pte_replacements, 0, ""); 235 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 236 0, ""); 237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 238 &moea_pvo_enter_calls, 0, ""); 239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 240 &moea_pvo_remove_calls, 0, ""); 241 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 242 &moea_pte_spills, 0, ""); 243 244 /* 245 * Allocate physical memory for use in moea_bootstrap. 246 */ 247 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 248 249 /* 250 * PTE calls. 251 */ 252 static int moea_pte_insert(u_int, struct pte *); 253 254 /* 255 * PVO calls. 256 */ 257 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 258 vm_offset_t, vm_offset_t, u_int, int); 259 static void moea_pvo_remove(struct pvo_entry *, int); 260 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 261 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 262 263 /* 264 * Utility routines. 265 */ 266 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 267 vm_prot_t, boolean_t); 268 static void moea_syncicache(vm_offset_t, vm_size_t); 269 static boolean_t moea_query_bit(vm_page_t, int); 270 static u_int moea_clear_bit(vm_page_t, int); 271 static void moea_kremove(mmu_t, vm_offset_t); 272 int moea_pte_spill(vm_offset_t); 273 274 /* 275 * Kernel MMU interface 276 */ 277 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 278 void moea_clear_modify(mmu_t, vm_page_t); 279 void moea_clear_reference(mmu_t, vm_page_t); 280 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 281 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 287 void moea_init(mmu_t); 288 boolean_t moea_is_modified(mmu_t, vm_page_t); 289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 boolean_t moea_is_referenced(mmu_t, vm_page_t); 291 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 int moea_page_wired_mappings(mmu_t, vm_page_t); 295 void moea_pinit(mmu_t, pmap_t); 296 void moea_pinit0(mmu_t, pmap_t); 297 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 298 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 299 void moea_qremove(mmu_t, vm_offset_t, int); 300 void moea_release(mmu_t, pmap_t); 301 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 302 void moea_remove_all(mmu_t, vm_page_t); 303 void moea_remove_write(mmu_t, vm_page_t); 304 void moea_zero_page(mmu_t, vm_page_t); 305 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 306 void moea_zero_page_idle(mmu_t, vm_page_t); 307 void moea_activate(mmu_t, struct thread *); 308 void moea_deactivate(mmu_t, struct thread *); 309 void moea_cpu_bootstrap(mmu_t, int); 310 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 311 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 312 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 313 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 314 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 315 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 316 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 317 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 318 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 319 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 320 321 static mmu_method_t moea_methods[] = { 322 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 323 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 324 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 325 MMUMETHOD(mmu_copy_page, moea_copy_page), 326 MMUMETHOD(mmu_enter, moea_enter), 327 MMUMETHOD(mmu_enter_object, moea_enter_object), 328 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 329 MMUMETHOD(mmu_extract, moea_extract), 330 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 331 MMUMETHOD(mmu_init, moea_init), 332 MMUMETHOD(mmu_is_modified, moea_is_modified), 333 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 334 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 335 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 336 MMUMETHOD(mmu_map, moea_map), 337 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 338 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 339 MMUMETHOD(mmu_pinit, moea_pinit), 340 MMUMETHOD(mmu_pinit0, moea_pinit0), 341 MMUMETHOD(mmu_protect, moea_protect), 342 MMUMETHOD(mmu_qenter, moea_qenter), 343 MMUMETHOD(mmu_qremove, moea_qremove), 344 MMUMETHOD(mmu_release, moea_release), 345 MMUMETHOD(mmu_remove, moea_remove), 346 MMUMETHOD(mmu_remove_all, moea_remove_all), 347 MMUMETHOD(mmu_remove_write, moea_remove_write), 348 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 349 MMUMETHOD(mmu_zero_page, moea_zero_page), 350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 351 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 352 MMUMETHOD(mmu_activate, moea_activate), 353 MMUMETHOD(mmu_deactivate, moea_deactivate), 354 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 355 356 /* Internal interfaces */ 357 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 358 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 359 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 360 MMUMETHOD(mmu_mapdev, moea_mapdev), 361 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 362 MMUMETHOD(mmu_kextract, moea_kextract), 363 MMUMETHOD(mmu_kenter, moea_kenter), 364 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 365 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 366 367 { 0, 0 } 368 }; 369 370 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 371 372 static __inline uint32_t 373 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 374 { 375 uint32_t pte_lo; 376 int i; 377 378 if (ma != VM_MEMATTR_DEFAULT) { 379 switch (ma) { 380 case VM_MEMATTR_UNCACHEABLE: 381 return (PTE_I | PTE_G); 382 case VM_MEMATTR_WRITE_COMBINING: 383 case VM_MEMATTR_WRITE_BACK: 384 case VM_MEMATTR_PREFETCHABLE: 385 return (PTE_I); 386 case VM_MEMATTR_WRITE_THROUGH: 387 return (PTE_W | PTE_M); 388 } 389 } 390 391 /* 392 * Assume the page is cache inhibited and access is guarded unless 393 * it's in our available memory array. 394 */ 395 pte_lo = PTE_I | PTE_G; 396 for (i = 0; i < pregions_sz; i++) { 397 if ((pa >= pregions[i].mr_start) && 398 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 399 pte_lo = PTE_M; 400 break; 401 } 402 } 403 404 return pte_lo; 405 } 406 407 static void 408 tlbie(vm_offset_t va) 409 { 410 411 mtx_lock_spin(&tlbie_mtx); 412 __asm __volatile("ptesync"); 413 __asm __volatile("tlbie %0" :: "r"(va)); 414 __asm __volatile("eieio; tlbsync; ptesync"); 415 mtx_unlock_spin(&tlbie_mtx); 416 } 417 418 static void 419 tlbia(void) 420 { 421 vm_offset_t va; 422 423 for (va = 0; va < 0x00040000; va += 0x00001000) { 424 __asm __volatile("tlbie %0" :: "r"(va)); 425 powerpc_sync(); 426 } 427 __asm __volatile("tlbsync"); 428 powerpc_sync(); 429 } 430 431 static __inline int 432 va_to_sr(u_int *sr, vm_offset_t va) 433 { 434 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 435 } 436 437 static __inline u_int 438 va_to_pteg(u_int sr, vm_offset_t addr) 439 { 440 u_int hash; 441 442 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 443 ADDR_PIDX_SHFT); 444 return (hash & moea_pteg_mask); 445 } 446 447 static __inline struct pvo_head * 448 vm_page_to_pvoh(vm_page_t m) 449 { 450 451 return (&m->md.mdpg_pvoh); 452 } 453 454 static __inline void 455 moea_attr_clear(vm_page_t m, int ptebit) 456 { 457 458 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 459 m->md.mdpg_attrs &= ~ptebit; 460 } 461 462 static __inline int 463 moea_attr_fetch(vm_page_t m) 464 { 465 466 return (m->md.mdpg_attrs); 467 } 468 469 static __inline void 470 moea_attr_save(vm_page_t m, int ptebit) 471 { 472 473 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 474 m->md.mdpg_attrs |= ptebit; 475 } 476 477 static __inline int 478 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 479 { 480 if (pt->pte_hi == pvo_pt->pte_hi) 481 return (1); 482 483 return (0); 484 } 485 486 static __inline int 487 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 488 { 489 return (pt->pte_hi & ~PTE_VALID) == 490 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 491 ((va >> ADDR_API_SHFT) & PTE_API) | which); 492 } 493 494 static __inline void 495 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 496 { 497 498 mtx_assert(&moea_table_mutex, MA_OWNED); 499 500 /* 501 * Construct a PTE. Default to IMB initially. Valid bit only gets 502 * set when the real pte is set in memory. 503 * 504 * Note: Don't set the valid bit for correct operation of tlb update. 505 */ 506 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 507 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 508 pt->pte_lo = pte_lo; 509 } 510 511 static __inline void 512 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 513 { 514 515 mtx_assert(&moea_table_mutex, MA_OWNED); 516 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 517 } 518 519 static __inline void 520 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 521 { 522 523 mtx_assert(&moea_table_mutex, MA_OWNED); 524 525 /* 526 * As shown in Section 7.6.3.2.3 527 */ 528 pt->pte_lo &= ~ptebit; 529 tlbie(va); 530 } 531 532 static __inline void 533 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 534 { 535 536 mtx_assert(&moea_table_mutex, MA_OWNED); 537 pvo_pt->pte_hi |= PTE_VALID; 538 539 /* 540 * Update the PTE as defined in section 7.6.3.1. 541 * Note that the REF/CHG bits are from pvo_pt and thus should havce 542 * been saved so this routine can restore them (if desired). 543 */ 544 pt->pte_lo = pvo_pt->pte_lo; 545 powerpc_sync(); 546 pt->pte_hi = pvo_pt->pte_hi; 547 powerpc_sync(); 548 moea_pte_valid++; 549 } 550 551 static __inline void 552 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 553 { 554 555 mtx_assert(&moea_table_mutex, MA_OWNED); 556 pvo_pt->pte_hi &= ~PTE_VALID; 557 558 /* 559 * Force the reg & chg bits back into the PTEs. 560 */ 561 powerpc_sync(); 562 563 /* 564 * Invalidate the pte. 565 */ 566 pt->pte_hi &= ~PTE_VALID; 567 568 tlbie(va); 569 570 /* 571 * Save the reg & chg bits. 572 */ 573 moea_pte_synch(pt, pvo_pt); 574 moea_pte_valid--; 575 } 576 577 static __inline void 578 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 579 { 580 581 /* 582 * Invalidate the PTE 583 */ 584 moea_pte_unset(pt, pvo_pt, va); 585 moea_pte_set(pt, pvo_pt); 586 } 587 588 /* 589 * Quick sort callout for comparing memory regions. 590 */ 591 static int om_cmp(const void *a, const void *b); 592 593 static int 594 om_cmp(const void *a, const void *b) 595 { 596 const struct ofw_map *mapa; 597 const struct ofw_map *mapb; 598 599 mapa = a; 600 mapb = b; 601 if (mapa->om_pa < mapb->om_pa) 602 return (-1); 603 else if (mapa->om_pa > mapb->om_pa) 604 return (1); 605 else 606 return (0); 607 } 608 609 void 610 moea_cpu_bootstrap(mmu_t mmup, int ap) 611 { 612 u_int sdr; 613 int i; 614 615 if (ap) { 616 powerpc_sync(); 617 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 618 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 619 isync(); 620 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 621 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 622 isync(); 623 } 624 625 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 626 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 627 isync(); 628 629 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 630 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 631 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 632 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 633 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 634 isync(); 635 636 for (i = 0; i < 16; i++) 637 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 638 powerpc_sync(); 639 640 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 641 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 642 isync(); 643 644 tlbia(); 645 } 646 647 void 648 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 649 { 650 ihandle_t mmui; 651 phandle_t chosen, mmu; 652 int sz; 653 int i, j; 654 vm_size_t size, physsz, hwphyssz; 655 vm_offset_t pa, va, off; 656 void *dpcpu; 657 register_t msr; 658 659 /* 660 * Set up BAT0 to map the lowest 256 MB area 661 */ 662 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 663 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 664 665 /* 666 * Map PCI memory space. 667 */ 668 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 669 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 670 671 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 672 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 673 674 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 675 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 676 677 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 678 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 679 680 /* 681 * Map obio devices. 682 */ 683 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 684 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 685 686 /* 687 * Use an IBAT and a DBAT to map the bottom segment of memory 688 * where we are. Turn off instruction relocation temporarily 689 * to prevent faults while reprogramming the IBAT. 690 */ 691 msr = mfmsr(); 692 mtmsr(msr & ~PSL_IR); 693 __asm (".balign 32; \n" 694 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 695 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 696 :: "r"(battable[0].batu), "r"(battable[0].batl)); 697 mtmsr(msr); 698 699 /* map pci space */ 700 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 701 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 702 isync(); 703 704 /* set global direct map flag */ 705 hw_direct_map = 1; 706 707 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 708 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 709 710 for (i = 0; i < pregions_sz; i++) { 711 vm_offset_t pa; 712 vm_offset_t end; 713 714 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 715 pregions[i].mr_start, 716 pregions[i].mr_start + pregions[i].mr_size, 717 pregions[i].mr_size); 718 /* 719 * Install entries into the BAT table to allow all 720 * of physmem to be convered by on-demand BAT entries. 721 * The loop will sometimes set the same battable element 722 * twice, but that's fine since they won't be used for 723 * a while yet. 724 */ 725 pa = pregions[i].mr_start & 0xf0000000; 726 end = pregions[i].mr_start + pregions[i].mr_size; 727 do { 728 u_int n = pa >> ADDR_SR_SHFT; 729 730 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 731 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 732 pa += SEGMENT_LENGTH; 733 } while (pa < end); 734 } 735 736 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 737 panic("moea_bootstrap: phys_avail too small"); 738 739 phys_avail_count = 0; 740 physsz = 0; 741 hwphyssz = 0; 742 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 743 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 744 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 745 regions[i].mr_start + regions[i].mr_size, 746 regions[i].mr_size); 747 if (hwphyssz != 0 && 748 (physsz + regions[i].mr_size) >= hwphyssz) { 749 if (physsz < hwphyssz) { 750 phys_avail[j] = regions[i].mr_start; 751 phys_avail[j + 1] = regions[i].mr_start + 752 hwphyssz - physsz; 753 physsz = hwphyssz; 754 phys_avail_count++; 755 } 756 break; 757 } 758 phys_avail[j] = regions[i].mr_start; 759 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 760 phys_avail_count++; 761 physsz += regions[i].mr_size; 762 } 763 764 /* Check for overlap with the kernel and exception vectors */ 765 for (j = 0; j < 2*phys_avail_count; j+=2) { 766 if (phys_avail[j] < EXC_LAST) 767 phys_avail[j] += EXC_LAST; 768 769 if (kernelstart >= phys_avail[j] && 770 kernelstart < phys_avail[j+1]) { 771 if (kernelend < phys_avail[j+1]) { 772 phys_avail[2*phys_avail_count] = 773 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 774 phys_avail[2*phys_avail_count + 1] = 775 phys_avail[j+1]; 776 phys_avail_count++; 777 } 778 779 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 780 } 781 782 if (kernelend >= phys_avail[j] && 783 kernelend < phys_avail[j+1]) { 784 if (kernelstart > phys_avail[j]) { 785 phys_avail[2*phys_avail_count] = phys_avail[j]; 786 phys_avail[2*phys_avail_count + 1] = 787 kernelstart & ~PAGE_MASK; 788 phys_avail_count++; 789 } 790 791 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 } 793 } 794 795 physmem = btoc(physsz); 796 797 /* 798 * Allocate PTEG table. 799 */ 800 #ifdef PTEGCOUNT 801 moea_pteg_count = PTEGCOUNT; 802 #else 803 moea_pteg_count = 0x1000; 804 805 while (moea_pteg_count < physmem) 806 moea_pteg_count <<= 1; 807 808 moea_pteg_count >>= 1; 809 #endif /* PTEGCOUNT */ 810 811 size = moea_pteg_count * sizeof(struct pteg); 812 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 813 size); 814 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 815 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 816 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 817 moea_pteg_mask = moea_pteg_count - 1; 818 819 /* 820 * Allocate pv/overflow lists. 821 */ 822 size = sizeof(struct pvo_head) * moea_pteg_count; 823 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 824 PAGE_SIZE); 825 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 826 for (i = 0; i < moea_pteg_count; i++) 827 LIST_INIT(&moea_pvo_table[i]); 828 829 /* 830 * Initialize the lock that synchronizes access to the pteg and pvo 831 * tables. 832 */ 833 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 834 MTX_RECURSE); 835 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 836 837 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 838 839 /* 840 * Initialise the unmanaged pvo pool. 841 */ 842 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 843 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 844 moea_bpvo_pool_index = 0; 845 846 /* 847 * Make sure kernel vsid is allocated as well as VSID 0. 848 */ 849 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 850 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 851 moea_vsid_bitmap[0] |= 1; 852 853 /* 854 * Initialize the kernel pmap (which is statically allocated). 855 */ 856 PMAP_LOCK_INIT(kernel_pmap); 857 for (i = 0; i < 16; i++) 858 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 859 CPU_FILL(&kernel_pmap->pm_active); 860 LIST_INIT(&kernel_pmap->pmap_pvo); 861 862 /* 863 * Set up the Open Firmware mappings 864 */ 865 chosen = OF_finddevice("/chosen"); 866 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 867 (mmu = OF_instance_to_package(mmui)) != -1 && 868 (sz = OF_getproplen(mmu, "translations")) != -1) { 869 translations = NULL; 870 for (i = 0; phys_avail[i] != 0; i += 2) { 871 if (phys_avail[i + 1] >= sz) { 872 translations = (struct ofw_map *)phys_avail[i]; 873 break; 874 } 875 } 876 if (translations == NULL) 877 panic("moea_bootstrap: no space to copy translations"); 878 bzero(translations, sz); 879 if (OF_getprop(mmu, "translations", translations, sz) == -1) 880 panic("moea_bootstrap: can't get ofw translations"); 881 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 882 sz /= sizeof(*translations); 883 qsort(translations, sz, sizeof (*translations), om_cmp); 884 for (i = 0; i < sz; i++) { 885 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 886 translations[i].om_pa, translations[i].om_va, 887 translations[i].om_len); 888 889 /* 890 * If the mapping is 1:1, let the RAM and device 891 * on-demand BAT tables take care of the translation. 892 */ 893 if (translations[i].om_va == translations[i].om_pa) 894 continue; 895 896 /* Enter the pages */ 897 for (off = 0; off < translations[i].om_len; 898 off += PAGE_SIZE) 899 moea_kenter(mmup, translations[i].om_va + off, 900 translations[i].om_pa + off); 901 } 902 } 903 904 /* 905 * Calculate the last available physical address. 906 */ 907 for (i = 0; phys_avail[i + 2] != 0; i += 2) 908 ; 909 Maxmem = powerpc_btop(phys_avail[i + 1]); 910 911 moea_cpu_bootstrap(mmup,0); 912 913 pmap_bootstrapped++; 914 915 /* 916 * Set the start and end of kva. 917 */ 918 virtual_avail = VM_MIN_KERNEL_ADDRESS; 919 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 920 921 /* 922 * Allocate a kernel stack with a guard page for thread0 and map it 923 * into the kernel page map. 924 */ 925 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 926 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 927 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 928 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 929 thread0.td_kstack = va; 930 thread0.td_kstack_pages = KSTACK_PAGES; 931 for (i = 0; i < KSTACK_PAGES; i++) { 932 moea_kenter(mmup, va, pa); 933 pa += PAGE_SIZE; 934 va += PAGE_SIZE; 935 } 936 937 /* 938 * Allocate virtual address space for the message buffer. 939 */ 940 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 941 msgbufp = (struct msgbuf *)virtual_avail; 942 va = virtual_avail; 943 virtual_avail += round_page(msgbufsize); 944 while (va < virtual_avail) { 945 moea_kenter(mmup, va, pa); 946 pa += PAGE_SIZE; 947 va += PAGE_SIZE; 948 } 949 950 /* 951 * Allocate virtual address space for the dynamic percpu area. 952 */ 953 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 954 dpcpu = (void *)virtual_avail; 955 va = virtual_avail; 956 virtual_avail += DPCPU_SIZE; 957 while (va < virtual_avail) { 958 moea_kenter(mmup, va, pa); 959 pa += PAGE_SIZE; 960 va += PAGE_SIZE; 961 } 962 dpcpu_init(dpcpu, 0); 963 } 964 965 /* 966 * Activate a user pmap. The pmap must be activated before it's address 967 * space can be accessed in any way. 968 */ 969 void 970 moea_activate(mmu_t mmu, struct thread *td) 971 { 972 pmap_t pm, pmr; 973 974 /* 975 * Load all the data we need up front to encourage the compiler to 976 * not issue any loads while we have interrupts disabled below. 977 */ 978 pm = &td->td_proc->p_vmspace->vm_pmap; 979 pmr = pm->pmap_phys; 980 981 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 982 PCPU_SET(curpmap, pmr); 983 } 984 985 void 986 moea_deactivate(mmu_t mmu, struct thread *td) 987 { 988 pmap_t pm; 989 990 pm = &td->td_proc->p_vmspace->vm_pmap; 991 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 992 PCPU_SET(curpmap, NULL); 993 } 994 995 void 996 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 997 { 998 struct pvo_entry *pvo; 999 1000 PMAP_LOCK(pm); 1001 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1002 1003 if (pvo != NULL) { 1004 if (wired) { 1005 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1006 pm->pm_stats.wired_count++; 1007 pvo->pvo_vaddr |= PVO_WIRED; 1008 } else { 1009 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1010 pm->pm_stats.wired_count--; 1011 pvo->pvo_vaddr &= ~PVO_WIRED; 1012 } 1013 } 1014 PMAP_UNLOCK(pm); 1015 } 1016 1017 void 1018 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1019 { 1020 vm_offset_t dst; 1021 vm_offset_t src; 1022 1023 dst = VM_PAGE_TO_PHYS(mdst); 1024 src = VM_PAGE_TO_PHYS(msrc); 1025 1026 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1027 } 1028 1029 /* 1030 * Zero a page of physical memory by temporarily mapping it into the tlb. 1031 */ 1032 void 1033 moea_zero_page(mmu_t mmu, vm_page_t m) 1034 { 1035 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1036 void *va = (void *)pa; 1037 1038 bzero(va, PAGE_SIZE); 1039 } 1040 1041 void 1042 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1043 { 1044 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1045 void *va = (void *)(pa + off); 1046 1047 bzero(va, size); 1048 } 1049 1050 void 1051 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1052 { 1053 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1054 void *va = (void *)pa; 1055 1056 bzero(va, PAGE_SIZE); 1057 } 1058 1059 /* 1060 * Map the given physical page at the specified virtual address in the 1061 * target pmap with the protection requested. If specified the page 1062 * will be wired down. 1063 */ 1064 void 1065 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1066 boolean_t wired) 1067 { 1068 1069 vm_page_lock_queues(); 1070 PMAP_LOCK(pmap); 1071 moea_enter_locked(pmap, va, m, prot, wired); 1072 vm_page_unlock_queues(); 1073 PMAP_UNLOCK(pmap); 1074 } 1075 1076 /* 1077 * Map the given physical page at the specified virtual address in the 1078 * target pmap with the protection requested. If specified the page 1079 * will be wired down. 1080 * 1081 * The page queues and pmap must be locked. 1082 */ 1083 static void 1084 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1085 boolean_t wired) 1086 { 1087 struct pvo_head *pvo_head; 1088 uma_zone_t zone; 1089 vm_page_t pg; 1090 u_int pte_lo, pvo_flags; 1091 int error; 1092 1093 if (!moea_initialized) { 1094 pvo_head = &moea_pvo_kunmanaged; 1095 zone = moea_upvo_zone; 1096 pvo_flags = 0; 1097 pg = NULL; 1098 } else { 1099 pvo_head = vm_page_to_pvoh(m); 1100 pg = m; 1101 zone = moea_mpvo_zone; 1102 pvo_flags = PVO_MANAGED; 1103 } 1104 if (pmap_bootstrapped) 1105 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1106 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1107 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1108 VM_OBJECT_LOCKED(m->object), 1109 ("moea_enter_locked: page %p is not busy", m)); 1110 1111 /* XXX change the pvo head for fake pages */ 1112 if ((m->oflags & VPO_UNMANAGED) != 0) { 1113 pvo_flags &= ~PVO_MANAGED; 1114 pvo_head = &moea_pvo_kunmanaged; 1115 zone = moea_upvo_zone; 1116 } 1117 1118 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1119 1120 if (prot & VM_PROT_WRITE) { 1121 pte_lo |= PTE_BW; 1122 if (pmap_bootstrapped && 1123 (m->oflags & VPO_UNMANAGED) == 0) 1124 vm_page_aflag_set(m, PGA_WRITEABLE); 1125 } else 1126 pte_lo |= PTE_BR; 1127 1128 if (prot & VM_PROT_EXECUTE) 1129 pvo_flags |= PVO_EXECUTABLE; 1130 1131 if (wired) 1132 pvo_flags |= PVO_WIRED; 1133 1134 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1135 pte_lo, pvo_flags); 1136 1137 /* 1138 * Flush the real page from the instruction cache. This has be done 1139 * for all user mappings to prevent information leakage via the 1140 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1141 * mapping for a page. 1142 */ 1143 if (pmap != kernel_pmap && error == ENOENT && 1144 (pte_lo & (PTE_I | PTE_G)) == 0) 1145 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1146 } 1147 1148 /* 1149 * Maps a sequence of resident pages belonging to the same object. 1150 * The sequence begins with the given page m_start. This page is 1151 * mapped at the given virtual address start. Each subsequent page is 1152 * mapped at a virtual address that is offset from start by the same 1153 * amount as the page is offset from m_start within the object. The 1154 * last page in the sequence is the page with the largest offset from 1155 * m_start that can be mapped at a virtual address less than the given 1156 * virtual address end. Not every virtual page between start and end 1157 * is mapped; only those for which a resident page exists with the 1158 * corresponding offset from m_start are mapped. 1159 */ 1160 void 1161 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1162 vm_page_t m_start, vm_prot_t prot) 1163 { 1164 vm_page_t m; 1165 vm_pindex_t diff, psize; 1166 1167 psize = atop(end - start); 1168 m = m_start; 1169 vm_page_lock_queues(); 1170 PMAP_LOCK(pm); 1171 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1172 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1173 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1174 m = TAILQ_NEXT(m, listq); 1175 } 1176 vm_page_unlock_queues(); 1177 PMAP_UNLOCK(pm); 1178 } 1179 1180 void 1181 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1182 vm_prot_t prot) 1183 { 1184 1185 vm_page_lock_queues(); 1186 PMAP_LOCK(pm); 1187 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1188 FALSE); 1189 vm_page_unlock_queues(); 1190 PMAP_UNLOCK(pm); 1191 } 1192 1193 vm_paddr_t 1194 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1195 { 1196 struct pvo_entry *pvo; 1197 vm_paddr_t pa; 1198 1199 PMAP_LOCK(pm); 1200 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1201 if (pvo == NULL) 1202 pa = 0; 1203 else 1204 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1205 PMAP_UNLOCK(pm); 1206 return (pa); 1207 } 1208 1209 /* 1210 * Atomically extract and hold the physical page with the given 1211 * pmap and virtual address pair if that mapping permits the given 1212 * protection. 1213 */ 1214 vm_page_t 1215 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1216 { 1217 struct pvo_entry *pvo; 1218 vm_page_t m; 1219 vm_paddr_t pa; 1220 1221 m = NULL; 1222 pa = 0; 1223 PMAP_LOCK(pmap); 1224 retry: 1225 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1226 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1227 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1228 (prot & VM_PROT_WRITE) == 0)) { 1229 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1230 goto retry; 1231 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1232 vm_page_hold(m); 1233 } 1234 PA_UNLOCK_COND(pa); 1235 PMAP_UNLOCK(pmap); 1236 return (m); 1237 } 1238 1239 void 1240 moea_init(mmu_t mmu) 1241 { 1242 1243 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1244 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1245 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1246 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1247 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1248 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1249 moea_initialized = TRUE; 1250 } 1251 1252 boolean_t 1253 moea_is_referenced(mmu_t mmu, vm_page_t m) 1254 { 1255 1256 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1257 ("moea_is_referenced: page %p is not managed", m)); 1258 return (moea_query_bit(m, PTE_REF)); 1259 } 1260 1261 boolean_t 1262 moea_is_modified(mmu_t mmu, vm_page_t m) 1263 { 1264 1265 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1266 ("moea_is_modified: page %p is not managed", m)); 1267 1268 /* 1269 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1270 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1271 * is clear, no PTEs can have PTE_CHG set. 1272 */ 1273 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1274 if ((m->oflags & VPO_BUSY) == 0 && 1275 (m->aflags & PGA_WRITEABLE) == 0) 1276 return (FALSE); 1277 return (moea_query_bit(m, PTE_CHG)); 1278 } 1279 1280 boolean_t 1281 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1282 { 1283 struct pvo_entry *pvo; 1284 boolean_t rv; 1285 1286 PMAP_LOCK(pmap); 1287 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1288 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1289 PMAP_UNLOCK(pmap); 1290 return (rv); 1291 } 1292 1293 void 1294 moea_clear_reference(mmu_t mmu, vm_page_t m) 1295 { 1296 1297 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1298 ("moea_clear_reference: page %p is not managed", m)); 1299 moea_clear_bit(m, PTE_REF); 1300 } 1301 1302 void 1303 moea_clear_modify(mmu_t mmu, vm_page_t m) 1304 { 1305 1306 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1307 ("moea_clear_modify: page %p is not managed", m)); 1308 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1309 KASSERT((m->oflags & VPO_BUSY) == 0, 1310 ("moea_clear_modify: page %p is busy", m)); 1311 1312 /* 1313 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1314 * set. If the object containing the page is locked and the page is 1315 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1316 */ 1317 if ((m->aflags & PGA_WRITEABLE) == 0) 1318 return; 1319 moea_clear_bit(m, PTE_CHG); 1320 } 1321 1322 /* 1323 * Clear the write and modified bits in each of the given page's mappings. 1324 */ 1325 void 1326 moea_remove_write(mmu_t mmu, vm_page_t m) 1327 { 1328 struct pvo_entry *pvo; 1329 struct pte *pt; 1330 pmap_t pmap; 1331 u_int lo; 1332 1333 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1334 ("moea_remove_write: page %p is not managed", m)); 1335 1336 /* 1337 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1338 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1339 * is clear, no page table entries need updating. 1340 */ 1341 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1342 if ((m->oflags & VPO_BUSY) == 0 && 1343 (m->aflags & PGA_WRITEABLE) == 0) 1344 return; 1345 vm_page_lock_queues(); 1346 lo = moea_attr_fetch(m); 1347 powerpc_sync(); 1348 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1349 pmap = pvo->pvo_pmap; 1350 PMAP_LOCK(pmap); 1351 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1352 pt = moea_pvo_to_pte(pvo, -1); 1353 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1354 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1355 if (pt != NULL) { 1356 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1357 lo |= pvo->pvo_pte.pte.pte_lo; 1358 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1359 moea_pte_change(pt, &pvo->pvo_pte.pte, 1360 pvo->pvo_vaddr); 1361 mtx_unlock(&moea_table_mutex); 1362 } 1363 } 1364 PMAP_UNLOCK(pmap); 1365 } 1366 if ((lo & PTE_CHG) != 0) { 1367 moea_attr_clear(m, PTE_CHG); 1368 vm_page_dirty(m); 1369 } 1370 vm_page_aflag_clear(m, PGA_WRITEABLE); 1371 vm_page_unlock_queues(); 1372 } 1373 1374 /* 1375 * moea_ts_referenced: 1376 * 1377 * Return a count of reference bits for a page, clearing those bits. 1378 * It is not necessary for every reference bit to be cleared, but it 1379 * is necessary that 0 only be returned when there are truly no 1380 * reference bits set. 1381 * 1382 * XXX: The exact number of bits to check and clear is a matter that 1383 * should be tested and standardized at some point in the future for 1384 * optimal aging of shared pages. 1385 */ 1386 boolean_t 1387 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1388 { 1389 1390 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1391 ("moea_ts_referenced: page %p is not managed", m)); 1392 return (moea_clear_bit(m, PTE_REF)); 1393 } 1394 1395 /* 1396 * Modify the WIMG settings of all mappings for a page. 1397 */ 1398 void 1399 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1400 { 1401 struct pvo_entry *pvo; 1402 struct pvo_head *pvo_head; 1403 struct pte *pt; 1404 pmap_t pmap; 1405 u_int lo; 1406 1407 if ((m->oflags & VPO_UNMANAGED) != 0) { 1408 m->md.mdpg_cache_attrs = ma; 1409 return; 1410 } 1411 1412 vm_page_lock_queues(); 1413 pvo_head = vm_page_to_pvoh(m); 1414 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1415 1416 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1417 pmap = pvo->pvo_pmap; 1418 PMAP_LOCK(pmap); 1419 pt = moea_pvo_to_pte(pvo, -1); 1420 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1421 pvo->pvo_pte.pte.pte_lo |= lo; 1422 if (pt != NULL) { 1423 moea_pte_change(pt, &pvo->pvo_pte.pte, 1424 pvo->pvo_vaddr); 1425 if (pvo->pvo_pmap == kernel_pmap) 1426 isync(); 1427 } 1428 mtx_unlock(&moea_table_mutex); 1429 PMAP_UNLOCK(pmap); 1430 } 1431 m->md.mdpg_cache_attrs = ma; 1432 vm_page_unlock_queues(); 1433 } 1434 1435 /* 1436 * Map a wired page into kernel virtual address space. 1437 */ 1438 void 1439 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1440 { 1441 1442 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1443 } 1444 1445 void 1446 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1447 { 1448 u_int pte_lo; 1449 int error; 1450 1451 #if 0 1452 if (va < VM_MIN_KERNEL_ADDRESS) 1453 panic("moea_kenter: attempt to enter non-kernel address %#x", 1454 va); 1455 #endif 1456 1457 pte_lo = moea_calc_wimg(pa, ma); 1458 1459 PMAP_LOCK(kernel_pmap); 1460 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1461 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1462 1463 if (error != 0 && error != ENOENT) 1464 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1465 pa, error); 1466 1467 PMAP_UNLOCK(kernel_pmap); 1468 } 1469 1470 /* 1471 * Extract the physical page address associated with the given kernel virtual 1472 * address. 1473 */ 1474 vm_offset_t 1475 moea_kextract(mmu_t mmu, vm_offset_t va) 1476 { 1477 struct pvo_entry *pvo; 1478 vm_paddr_t pa; 1479 1480 /* 1481 * Allow direct mappings on 32-bit OEA 1482 */ 1483 if (va < VM_MIN_KERNEL_ADDRESS) { 1484 return (va); 1485 } 1486 1487 PMAP_LOCK(kernel_pmap); 1488 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1489 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1490 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1491 PMAP_UNLOCK(kernel_pmap); 1492 return (pa); 1493 } 1494 1495 /* 1496 * Remove a wired page from kernel virtual address space. 1497 */ 1498 void 1499 moea_kremove(mmu_t mmu, vm_offset_t va) 1500 { 1501 1502 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1503 } 1504 1505 /* 1506 * Map a range of physical addresses into kernel virtual address space. 1507 * 1508 * The value passed in *virt is a suggested virtual address for the mapping. 1509 * Architectures which can support a direct-mapped physical to virtual region 1510 * can return the appropriate address within that region, leaving '*virt' 1511 * unchanged. We cannot and therefore do not; *virt is updated with the 1512 * first usable address after the mapped region. 1513 */ 1514 vm_offset_t 1515 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1516 vm_offset_t pa_end, int prot) 1517 { 1518 vm_offset_t sva, va; 1519 1520 sva = *virt; 1521 va = sva; 1522 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1523 moea_kenter(mmu, va, pa_start); 1524 *virt = va; 1525 return (sva); 1526 } 1527 1528 /* 1529 * Returns true if the pmap's pv is one of the first 1530 * 16 pvs linked to from this page. This count may 1531 * be changed upwards or downwards in the future; it 1532 * is only necessary that true be returned for a small 1533 * subset of pmaps for proper page aging. 1534 */ 1535 boolean_t 1536 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1537 { 1538 int loops; 1539 struct pvo_entry *pvo; 1540 boolean_t rv; 1541 1542 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1543 ("moea_page_exists_quick: page %p is not managed", m)); 1544 loops = 0; 1545 rv = FALSE; 1546 vm_page_lock_queues(); 1547 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1548 if (pvo->pvo_pmap == pmap) { 1549 rv = TRUE; 1550 break; 1551 } 1552 if (++loops >= 16) 1553 break; 1554 } 1555 vm_page_unlock_queues(); 1556 return (rv); 1557 } 1558 1559 /* 1560 * Return the number of managed mappings to the given physical page 1561 * that are wired. 1562 */ 1563 int 1564 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1565 { 1566 struct pvo_entry *pvo; 1567 int count; 1568 1569 count = 0; 1570 if ((m->oflags & VPO_UNMANAGED) != 0) 1571 return (count); 1572 vm_page_lock_queues(); 1573 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1574 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1575 count++; 1576 vm_page_unlock_queues(); 1577 return (count); 1578 } 1579 1580 static u_int moea_vsidcontext; 1581 1582 void 1583 moea_pinit(mmu_t mmu, pmap_t pmap) 1584 { 1585 int i, mask; 1586 u_int entropy; 1587 1588 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1589 PMAP_LOCK_INIT(pmap); 1590 LIST_INIT(&pmap->pmap_pvo); 1591 1592 entropy = 0; 1593 __asm __volatile("mftb %0" : "=r"(entropy)); 1594 1595 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1596 == NULL) { 1597 pmap->pmap_phys = pmap; 1598 } 1599 1600 1601 mtx_lock(&moea_vsid_mutex); 1602 /* 1603 * Allocate some segment registers for this pmap. 1604 */ 1605 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1606 u_int hash, n; 1607 1608 /* 1609 * Create a new value by mutiplying by a prime and adding in 1610 * entropy from the timebase register. This is to make the 1611 * VSID more random so that the PT hash function collides 1612 * less often. (Note that the prime casues gcc to do shifts 1613 * instead of a multiply.) 1614 */ 1615 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1616 hash = moea_vsidcontext & (NPMAPS - 1); 1617 if (hash == 0) /* 0 is special, avoid it */ 1618 continue; 1619 n = hash >> 5; 1620 mask = 1 << (hash & (VSID_NBPW - 1)); 1621 hash = (moea_vsidcontext & 0xfffff); 1622 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1623 /* anything free in this bucket? */ 1624 if (moea_vsid_bitmap[n] == 0xffffffff) { 1625 entropy = (moea_vsidcontext >> 20); 1626 continue; 1627 } 1628 i = ffs(~moea_vsid_bitmap[n]) - 1; 1629 mask = 1 << i; 1630 hash &= 0xfffff & ~(VSID_NBPW - 1); 1631 hash |= i; 1632 } 1633 KASSERT(!(moea_vsid_bitmap[n] & mask), 1634 ("Allocating in-use VSID group %#x\n", hash)); 1635 moea_vsid_bitmap[n] |= mask; 1636 for (i = 0; i < 16; i++) 1637 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1638 mtx_unlock(&moea_vsid_mutex); 1639 return; 1640 } 1641 1642 mtx_unlock(&moea_vsid_mutex); 1643 panic("moea_pinit: out of segments"); 1644 } 1645 1646 /* 1647 * Initialize the pmap associated with process 0. 1648 */ 1649 void 1650 moea_pinit0(mmu_t mmu, pmap_t pm) 1651 { 1652 1653 moea_pinit(mmu, pm); 1654 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1655 } 1656 1657 /* 1658 * Set the physical protection on the specified range of this map as requested. 1659 */ 1660 void 1661 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1662 vm_prot_t prot) 1663 { 1664 struct pvo_entry *pvo; 1665 struct pte *pt; 1666 int pteidx; 1667 1668 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1669 ("moea_protect: non current pmap")); 1670 1671 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1672 moea_remove(mmu, pm, sva, eva); 1673 return; 1674 } 1675 1676 vm_page_lock_queues(); 1677 PMAP_LOCK(pm); 1678 for (; sva < eva; sva += PAGE_SIZE) { 1679 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1680 if (pvo == NULL) 1681 continue; 1682 1683 if ((prot & VM_PROT_EXECUTE) == 0) 1684 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1685 1686 /* 1687 * Grab the PTE pointer before we diddle with the cached PTE 1688 * copy. 1689 */ 1690 pt = moea_pvo_to_pte(pvo, pteidx); 1691 /* 1692 * Change the protection of the page. 1693 */ 1694 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1695 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1696 1697 /* 1698 * If the PVO is in the page table, update that pte as well. 1699 */ 1700 if (pt != NULL) { 1701 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1702 mtx_unlock(&moea_table_mutex); 1703 } 1704 } 1705 vm_page_unlock_queues(); 1706 PMAP_UNLOCK(pm); 1707 } 1708 1709 /* 1710 * Map a list of wired pages into kernel virtual address space. This is 1711 * intended for temporary mappings which do not need page modification or 1712 * references recorded. Existing mappings in the region are overwritten. 1713 */ 1714 void 1715 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1716 { 1717 vm_offset_t va; 1718 1719 va = sva; 1720 while (count-- > 0) { 1721 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1722 va += PAGE_SIZE; 1723 m++; 1724 } 1725 } 1726 1727 /* 1728 * Remove page mappings from kernel virtual address space. Intended for 1729 * temporary mappings entered by moea_qenter. 1730 */ 1731 void 1732 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1733 { 1734 vm_offset_t va; 1735 1736 va = sva; 1737 while (count-- > 0) { 1738 moea_kremove(mmu, va); 1739 va += PAGE_SIZE; 1740 } 1741 } 1742 1743 void 1744 moea_release(mmu_t mmu, pmap_t pmap) 1745 { 1746 int idx, mask; 1747 1748 /* 1749 * Free segment register's VSID 1750 */ 1751 if (pmap->pm_sr[0] == 0) 1752 panic("moea_release"); 1753 1754 mtx_lock(&moea_vsid_mutex); 1755 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1756 mask = 1 << (idx % VSID_NBPW); 1757 idx /= VSID_NBPW; 1758 moea_vsid_bitmap[idx] &= ~mask; 1759 mtx_unlock(&moea_vsid_mutex); 1760 PMAP_LOCK_DESTROY(pmap); 1761 } 1762 1763 /* 1764 * Remove the given range of addresses from the specified map. 1765 */ 1766 void 1767 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1768 { 1769 struct pvo_entry *pvo, *tpvo; 1770 int pteidx; 1771 1772 vm_page_lock_queues(); 1773 PMAP_LOCK(pm); 1774 if ((eva - sva)/PAGE_SIZE < 10) { 1775 for (; sva < eva; sva += PAGE_SIZE) { 1776 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1777 if (pvo != NULL) 1778 moea_pvo_remove(pvo, pteidx); 1779 } 1780 } else { 1781 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) { 1782 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 1783 continue; 1784 moea_pvo_remove(pvo, -1); 1785 } 1786 } 1787 PMAP_UNLOCK(pm); 1788 vm_page_unlock_queues(); 1789 } 1790 1791 /* 1792 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1793 * will reflect changes in pte's back to the vm_page. 1794 */ 1795 void 1796 moea_remove_all(mmu_t mmu, vm_page_t m) 1797 { 1798 struct pvo_head *pvo_head; 1799 struct pvo_entry *pvo, *next_pvo; 1800 pmap_t pmap; 1801 1802 vm_page_lock_queues(); 1803 pvo_head = vm_page_to_pvoh(m); 1804 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1805 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1806 1807 pmap = pvo->pvo_pmap; 1808 PMAP_LOCK(pmap); 1809 moea_pvo_remove(pvo, -1); 1810 PMAP_UNLOCK(pmap); 1811 } 1812 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) { 1813 moea_attr_clear(m, PTE_CHG); 1814 vm_page_dirty(m); 1815 } 1816 vm_page_aflag_clear(m, PGA_WRITEABLE); 1817 vm_page_unlock_queues(); 1818 } 1819 1820 /* 1821 * Allocate a physical page of memory directly from the phys_avail map. 1822 * Can only be called from moea_bootstrap before avail start and end are 1823 * calculated. 1824 */ 1825 static vm_offset_t 1826 moea_bootstrap_alloc(vm_size_t size, u_int align) 1827 { 1828 vm_offset_t s, e; 1829 int i, j; 1830 1831 size = round_page(size); 1832 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1833 if (align != 0) 1834 s = (phys_avail[i] + align - 1) & ~(align - 1); 1835 else 1836 s = phys_avail[i]; 1837 e = s + size; 1838 1839 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1840 continue; 1841 1842 if (s == phys_avail[i]) { 1843 phys_avail[i] += size; 1844 } else if (e == phys_avail[i + 1]) { 1845 phys_avail[i + 1] -= size; 1846 } else { 1847 for (j = phys_avail_count * 2; j > i; j -= 2) { 1848 phys_avail[j] = phys_avail[j - 2]; 1849 phys_avail[j + 1] = phys_avail[j - 1]; 1850 } 1851 1852 phys_avail[i + 3] = phys_avail[i + 1]; 1853 phys_avail[i + 1] = s; 1854 phys_avail[i + 2] = e; 1855 phys_avail_count++; 1856 } 1857 1858 return (s); 1859 } 1860 panic("moea_bootstrap_alloc: could not allocate memory"); 1861 } 1862 1863 static void 1864 moea_syncicache(vm_offset_t pa, vm_size_t len) 1865 { 1866 __syncicache((void *)pa, len); 1867 } 1868 1869 static int 1870 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1871 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1872 { 1873 struct pvo_entry *pvo; 1874 u_int sr; 1875 int first; 1876 u_int ptegidx; 1877 int i; 1878 int bootstrap; 1879 1880 moea_pvo_enter_calls++; 1881 first = 0; 1882 bootstrap = 0; 1883 1884 /* 1885 * Compute the PTE Group index. 1886 */ 1887 va &= ~ADDR_POFF; 1888 sr = va_to_sr(pm->pm_sr, va); 1889 ptegidx = va_to_pteg(sr, va); 1890 1891 /* 1892 * Remove any existing mapping for this page. Reuse the pvo entry if 1893 * there is a mapping. 1894 */ 1895 mtx_lock(&moea_table_mutex); 1896 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1897 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1898 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1899 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1900 (pte_lo & PTE_PP)) { 1901 mtx_unlock(&moea_table_mutex); 1902 return (0); 1903 } 1904 moea_pvo_remove(pvo, -1); 1905 break; 1906 } 1907 } 1908 1909 /* 1910 * If we aren't overwriting a mapping, try to allocate. 1911 */ 1912 if (moea_initialized) { 1913 pvo = uma_zalloc(zone, M_NOWAIT); 1914 } else { 1915 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1916 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1917 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1918 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1919 } 1920 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1921 moea_bpvo_pool_index++; 1922 bootstrap = 1; 1923 } 1924 1925 if (pvo == NULL) { 1926 mtx_unlock(&moea_table_mutex); 1927 return (ENOMEM); 1928 } 1929 1930 moea_pvo_entries++; 1931 pvo->pvo_vaddr = va; 1932 pvo->pvo_pmap = pm; 1933 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1934 pvo->pvo_vaddr &= ~ADDR_POFF; 1935 if (flags & VM_PROT_EXECUTE) 1936 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1937 if (flags & PVO_WIRED) 1938 pvo->pvo_vaddr |= PVO_WIRED; 1939 if (pvo_head != &moea_pvo_kunmanaged) 1940 pvo->pvo_vaddr |= PVO_MANAGED; 1941 if (bootstrap) 1942 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1943 1944 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1945 1946 /* 1947 * Add to pmap list 1948 */ 1949 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink); 1950 1951 /* 1952 * Remember if the list was empty and therefore will be the first 1953 * item. 1954 */ 1955 if (LIST_FIRST(pvo_head) == NULL) 1956 first = 1; 1957 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1958 1959 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1960 pm->pm_stats.wired_count++; 1961 pm->pm_stats.resident_count++; 1962 1963 /* 1964 * We hope this succeeds but it isn't required. 1965 */ 1966 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1967 if (i >= 0) { 1968 PVO_PTEGIDX_SET(pvo, i); 1969 } else { 1970 panic("moea_pvo_enter: overflow"); 1971 moea_pte_overflow++; 1972 } 1973 mtx_unlock(&moea_table_mutex); 1974 1975 return (first ? ENOENT : 0); 1976 } 1977 1978 static void 1979 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1980 { 1981 struct pte *pt; 1982 1983 /* 1984 * If there is an active pte entry, we need to deactivate it (and 1985 * save the ref & cfg bits). 1986 */ 1987 pt = moea_pvo_to_pte(pvo, pteidx); 1988 if (pt != NULL) { 1989 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1990 mtx_unlock(&moea_table_mutex); 1991 PVO_PTEGIDX_CLR(pvo); 1992 } else { 1993 moea_pte_overflow--; 1994 } 1995 1996 /* 1997 * Update our statistics. 1998 */ 1999 pvo->pvo_pmap->pm_stats.resident_count--; 2000 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2001 pvo->pvo_pmap->pm_stats.wired_count--; 2002 2003 /* 2004 * Save the REF/CHG bits into their cache if the page is managed. 2005 */ 2006 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2007 struct vm_page *pg; 2008 2009 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2010 if (pg != NULL) { 2011 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2012 (PTE_REF | PTE_CHG)); 2013 } 2014 } 2015 2016 /* 2017 * Remove this PVO from the PV and pmap lists. 2018 */ 2019 LIST_REMOVE(pvo, pvo_vlink); 2020 LIST_REMOVE(pvo, pvo_plink); 2021 2022 /* 2023 * Remove this from the overflow list and return it to the pool 2024 * if we aren't going to reuse it. 2025 */ 2026 LIST_REMOVE(pvo, pvo_olink); 2027 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2028 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2029 moea_upvo_zone, pvo); 2030 moea_pvo_entries--; 2031 moea_pvo_remove_calls++; 2032 } 2033 2034 static __inline int 2035 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2036 { 2037 int pteidx; 2038 2039 /* 2040 * We can find the actual pte entry without searching by grabbing 2041 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2042 * noticing the HID bit. 2043 */ 2044 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2045 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2046 pteidx ^= moea_pteg_mask * 8; 2047 2048 return (pteidx); 2049 } 2050 2051 static struct pvo_entry * 2052 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2053 { 2054 struct pvo_entry *pvo; 2055 int ptegidx; 2056 u_int sr; 2057 2058 va &= ~ADDR_POFF; 2059 sr = va_to_sr(pm->pm_sr, va); 2060 ptegidx = va_to_pteg(sr, va); 2061 2062 mtx_lock(&moea_table_mutex); 2063 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2064 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2065 if (pteidx_p) 2066 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2067 break; 2068 } 2069 } 2070 mtx_unlock(&moea_table_mutex); 2071 2072 return (pvo); 2073 } 2074 2075 static struct pte * 2076 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2077 { 2078 struct pte *pt; 2079 2080 /* 2081 * If we haven't been supplied the ptegidx, calculate it. 2082 */ 2083 if (pteidx == -1) { 2084 int ptegidx; 2085 u_int sr; 2086 2087 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2088 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2089 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2090 } 2091 2092 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2093 mtx_lock(&moea_table_mutex); 2094 2095 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2096 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2097 "valid pte index", pvo); 2098 } 2099 2100 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2101 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2102 "pvo but no valid pte", pvo); 2103 } 2104 2105 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2106 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2107 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2108 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2109 } 2110 2111 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2112 != 0) { 2113 panic("moea_pvo_to_pte: pvo %p pte does not match " 2114 "pte %p in moea_pteg_table", pvo, pt); 2115 } 2116 2117 mtx_assert(&moea_table_mutex, MA_OWNED); 2118 return (pt); 2119 } 2120 2121 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2122 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2123 "moea_pteg_table but valid in pvo", pvo, pt); 2124 } 2125 2126 mtx_unlock(&moea_table_mutex); 2127 return (NULL); 2128 } 2129 2130 /* 2131 * XXX: THIS STUFF SHOULD BE IN pte.c? 2132 */ 2133 int 2134 moea_pte_spill(vm_offset_t addr) 2135 { 2136 struct pvo_entry *source_pvo, *victim_pvo; 2137 struct pvo_entry *pvo; 2138 int ptegidx, i, j; 2139 u_int sr; 2140 struct pteg *pteg; 2141 struct pte *pt; 2142 2143 moea_pte_spills++; 2144 2145 sr = mfsrin(addr); 2146 ptegidx = va_to_pteg(sr, addr); 2147 2148 /* 2149 * Have to substitute some entry. Use the primary hash for this. 2150 * Use low bits of timebase as random generator. 2151 */ 2152 pteg = &moea_pteg_table[ptegidx]; 2153 mtx_lock(&moea_table_mutex); 2154 __asm __volatile("mftb %0" : "=r"(i)); 2155 i &= 7; 2156 pt = &pteg->pt[i]; 2157 2158 source_pvo = NULL; 2159 victim_pvo = NULL; 2160 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2161 /* 2162 * We need to find a pvo entry for this address. 2163 */ 2164 if (source_pvo == NULL && 2165 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2166 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2167 /* 2168 * Now found an entry to be spilled into the pteg. 2169 * The PTE is now valid, so we know it's active. 2170 */ 2171 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2172 2173 if (j >= 0) { 2174 PVO_PTEGIDX_SET(pvo, j); 2175 moea_pte_overflow--; 2176 mtx_unlock(&moea_table_mutex); 2177 return (1); 2178 } 2179 2180 source_pvo = pvo; 2181 2182 if (victim_pvo != NULL) 2183 break; 2184 } 2185 2186 /* 2187 * We also need the pvo entry of the victim we are replacing 2188 * so save the R & C bits of the PTE. 2189 */ 2190 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2191 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2192 victim_pvo = pvo; 2193 if (source_pvo != NULL) 2194 break; 2195 } 2196 } 2197 2198 if (source_pvo == NULL) { 2199 mtx_unlock(&moea_table_mutex); 2200 return (0); 2201 } 2202 2203 if (victim_pvo == NULL) { 2204 if ((pt->pte_hi & PTE_HID) == 0) 2205 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2206 "entry", pt); 2207 2208 /* 2209 * If this is a secondary PTE, we need to search it's primary 2210 * pvo bucket for the matching PVO. 2211 */ 2212 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2213 pvo_olink) { 2214 /* 2215 * We also need the pvo entry of the victim we are 2216 * replacing so save the R & C bits of the PTE. 2217 */ 2218 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2219 victim_pvo = pvo; 2220 break; 2221 } 2222 } 2223 2224 if (victim_pvo == NULL) 2225 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2226 "entry", pt); 2227 } 2228 2229 /* 2230 * We are invalidating the TLB entry for the EA we are replacing even 2231 * though it's valid. If we don't, we lose any ref/chg bit changes 2232 * contained in the TLB entry. 2233 */ 2234 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2235 2236 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2237 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2238 2239 PVO_PTEGIDX_CLR(victim_pvo); 2240 PVO_PTEGIDX_SET(source_pvo, i); 2241 moea_pte_replacements++; 2242 2243 mtx_unlock(&moea_table_mutex); 2244 return (1); 2245 } 2246 2247 static int 2248 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2249 { 2250 struct pte *pt; 2251 int i; 2252 2253 mtx_assert(&moea_table_mutex, MA_OWNED); 2254 2255 /* 2256 * First try primary hash. 2257 */ 2258 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2259 if ((pt->pte_hi & PTE_VALID) == 0) { 2260 pvo_pt->pte_hi &= ~PTE_HID; 2261 moea_pte_set(pt, pvo_pt); 2262 return (i); 2263 } 2264 } 2265 2266 /* 2267 * Now try secondary hash. 2268 */ 2269 ptegidx ^= moea_pteg_mask; 2270 2271 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2272 if ((pt->pte_hi & PTE_VALID) == 0) { 2273 pvo_pt->pte_hi |= PTE_HID; 2274 moea_pte_set(pt, pvo_pt); 2275 return (i); 2276 } 2277 } 2278 2279 panic("moea_pte_insert: overflow"); 2280 return (-1); 2281 } 2282 2283 static boolean_t 2284 moea_query_bit(vm_page_t m, int ptebit) 2285 { 2286 struct pvo_entry *pvo; 2287 struct pte *pt; 2288 2289 if (moea_attr_fetch(m) & ptebit) 2290 return (TRUE); 2291 2292 vm_page_lock_queues(); 2293 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2294 2295 /* 2296 * See if we saved the bit off. If so, cache it and return 2297 * success. 2298 */ 2299 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2300 moea_attr_save(m, ptebit); 2301 vm_page_unlock_queues(); 2302 return (TRUE); 2303 } 2304 } 2305 2306 /* 2307 * No luck, now go through the hard part of looking at the PTEs 2308 * themselves. Sync so that any pending REF/CHG bits are flushed to 2309 * the PTEs. 2310 */ 2311 powerpc_sync(); 2312 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2313 2314 /* 2315 * See if this pvo has a valid PTE. if so, fetch the 2316 * REF/CHG bits from the valid PTE. If the appropriate 2317 * ptebit is set, cache it and return success. 2318 */ 2319 pt = moea_pvo_to_pte(pvo, -1); 2320 if (pt != NULL) { 2321 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2322 mtx_unlock(&moea_table_mutex); 2323 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2324 moea_attr_save(m, ptebit); 2325 vm_page_unlock_queues(); 2326 return (TRUE); 2327 } 2328 } 2329 } 2330 2331 vm_page_unlock_queues(); 2332 return (FALSE); 2333 } 2334 2335 static u_int 2336 moea_clear_bit(vm_page_t m, int ptebit) 2337 { 2338 u_int count; 2339 struct pvo_entry *pvo; 2340 struct pte *pt; 2341 2342 vm_page_lock_queues(); 2343 2344 /* 2345 * Clear the cached value. 2346 */ 2347 moea_attr_clear(m, ptebit); 2348 2349 /* 2350 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2351 * we can reset the right ones). note that since the pvo entries and 2352 * list heads are accessed via BAT0 and are never placed in the page 2353 * table, we don't have to worry about further accesses setting the 2354 * REF/CHG bits. 2355 */ 2356 powerpc_sync(); 2357 2358 /* 2359 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2360 * valid pte clear the ptebit from the valid pte. 2361 */ 2362 count = 0; 2363 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2364 pt = moea_pvo_to_pte(pvo, -1); 2365 if (pt != NULL) { 2366 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2367 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2368 count++; 2369 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2370 } 2371 mtx_unlock(&moea_table_mutex); 2372 } 2373 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2374 } 2375 2376 vm_page_unlock_queues(); 2377 return (count); 2378 } 2379 2380 /* 2381 * Return true if the physical range is encompassed by the battable[idx] 2382 */ 2383 static int 2384 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2385 { 2386 u_int prot; 2387 u_int32_t start; 2388 u_int32_t end; 2389 u_int32_t bat_ble; 2390 2391 /* 2392 * Return immediately if not a valid mapping 2393 */ 2394 if (!(battable[idx].batu & BAT_Vs)) 2395 return (EINVAL); 2396 2397 /* 2398 * The BAT entry must be cache-inhibited, guarded, and r/w 2399 * so it can function as an i/o page 2400 */ 2401 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2402 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2403 return (EPERM); 2404 2405 /* 2406 * The address should be within the BAT range. Assume that the 2407 * start address in the BAT has the correct alignment (thus 2408 * not requiring masking) 2409 */ 2410 start = battable[idx].batl & BAT_PBS; 2411 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2412 end = start | (bat_ble << 15) | 0x7fff; 2413 2414 if ((pa < start) || ((pa + size) > end)) 2415 return (ERANGE); 2416 2417 return (0); 2418 } 2419 2420 boolean_t 2421 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2422 { 2423 int i; 2424 2425 /* 2426 * This currently does not work for entries that 2427 * overlap 256M BAT segments. 2428 */ 2429 2430 for(i = 0; i < 16; i++) 2431 if (moea_bat_mapped(i, pa, size) == 0) 2432 return (0); 2433 2434 return (EFAULT); 2435 } 2436 2437 /* 2438 * Map a set of physical memory pages into the kernel virtual 2439 * address space. Return a pointer to where it is mapped. This 2440 * routine is intended to be used for mapping device memory, 2441 * NOT real memory. 2442 */ 2443 void * 2444 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2445 { 2446 2447 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2448 } 2449 2450 void * 2451 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2452 { 2453 vm_offset_t va, tmpva, ppa, offset; 2454 int i; 2455 2456 ppa = trunc_page(pa); 2457 offset = pa & PAGE_MASK; 2458 size = roundup(offset + size, PAGE_SIZE); 2459 2460 /* 2461 * If the physical address lies within a valid BAT table entry, 2462 * return the 1:1 mapping. This currently doesn't work 2463 * for regions that overlap 256M BAT segments. 2464 */ 2465 for (i = 0; i < 16; i++) { 2466 if (moea_bat_mapped(i, pa, size) == 0) 2467 return ((void *) pa); 2468 } 2469 2470 va = kmem_alloc_nofault(kernel_map, size); 2471 if (!va) 2472 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2473 2474 for (tmpva = va; size > 0;) { 2475 moea_kenter_attr(mmu, tmpva, ppa, ma); 2476 tlbie(tmpva); 2477 size -= PAGE_SIZE; 2478 tmpva += PAGE_SIZE; 2479 ppa += PAGE_SIZE; 2480 } 2481 2482 return ((void *)(va + offset)); 2483 } 2484 2485 void 2486 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2487 { 2488 vm_offset_t base, offset; 2489 2490 /* 2491 * If this is outside kernel virtual space, then it's a 2492 * battable entry and doesn't require unmapping 2493 */ 2494 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2495 base = trunc_page(va); 2496 offset = va & PAGE_MASK; 2497 size = roundup(offset + size, PAGE_SIZE); 2498 kmem_free(kernel_map, base, size); 2499 } 2500 } 2501 2502 static void 2503 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2504 { 2505 struct pvo_entry *pvo; 2506 vm_offset_t lim; 2507 vm_paddr_t pa; 2508 vm_size_t len; 2509 2510 PMAP_LOCK(pm); 2511 while (sz > 0) { 2512 lim = round_page(va); 2513 len = MIN(lim - va, sz); 2514 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2515 if (pvo != NULL) { 2516 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2517 (va & ADDR_POFF); 2518 moea_syncicache(pa, len); 2519 } 2520 va += len; 2521 sz -= len; 2522 } 2523 PMAP_UNLOCK(pm); 2524 } 2525