1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/conf.h> 110 #include <sys/queue.h> 111 #include <sys/cpuset.h> 112 #include <sys/kerneldump.h> 113 #include <sys/ktr.h> 114 #include <sys/lock.h> 115 #include <sys/msgbuf.h> 116 #include <sys/mutex.h> 117 #include <sys/proc.h> 118 #include <sys/rwlock.h> 119 #include <sys/sched.h> 120 #include <sys/sysctl.h> 121 #include <sys/systm.h> 122 #include <sys/vmmeter.h> 123 124 #include <dev/ofw/openfirm.h> 125 126 #include <vm/vm.h> 127 #include <vm/vm_param.h> 128 #include <vm/vm_kern.h> 129 #include <vm/vm_page.h> 130 #include <vm/vm_map.h> 131 #include <vm/vm_object.h> 132 #include <vm/vm_extern.h> 133 #include <vm/vm_pageout.h> 134 #include <vm/uma.h> 135 136 #include <machine/cpu.h> 137 #include <machine/platform.h> 138 #include <machine/bat.h> 139 #include <machine/frame.h> 140 #include <machine/md_var.h> 141 #include <machine/psl.h> 142 #include <machine/pte.h> 143 #include <machine/smp.h> 144 #include <machine/sr.h> 145 #include <machine/mmuvar.h> 146 #include <machine/trap.h> 147 148 #include "mmu_if.h" 149 150 #define MOEA_DEBUG 151 152 #define TODO panic("%s: not implemented", __func__); 153 154 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 155 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 156 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 157 158 struct ofw_map { 159 vm_offset_t om_va; 160 vm_size_t om_len; 161 vm_offset_t om_pa; 162 u_int om_mode; 163 }; 164 165 extern unsigned char _etext[]; 166 extern unsigned char _end[]; 167 168 /* 169 * Map of physical memory regions. 170 */ 171 static struct mem_region *regions; 172 static struct mem_region *pregions; 173 static u_int phys_avail_count; 174 static int regions_sz, pregions_sz; 175 static struct ofw_map *translations; 176 177 /* 178 * Lock for the pteg and pvo tables. 179 */ 180 struct mtx moea_table_mutex; 181 struct mtx moea_vsid_mutex; 182 183 /* tlbie instruction synchronization */ 184 static struct mtx tlbie_mtx; 185 186 /* 187 * PTEG data. 188 */ 189 static struct pteg *moea_pteg_table; 190 u_int moea_pteg_count; 191 u_int moea_pteg_mask; 192 193 /* 194 * PVO data. 195 */ 196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197 struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200 static struct rwlock_padalign pvh_global_lock; 201 202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205 #define BPVO_POOL_SIZE 32768 206 static struct pvo_entry *moea_bpvo_pool; 207 static int moea_bpvo_pool_index = 0; 208 209 #define VSID_NBPW (sizeof(u_int32_t) * 8) 210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212 static boolean_t moea_initialized = FALSE; 213 214 /* 215 * Statistics. 216 */ 217 u_int moea_pte_valid = 0; 218 u_int moea_pte_overflow = 0; 219 u_int moea_pte_replacements = 0; 220 u_int moea_pvo_entries = 0; 221 u_int moea_pvo_enter_calls = 0; 222 u_int moea_pvo_remove_calls = 0; 223 u_int moea_pte_spills = 0; 224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239 /* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244 /* 245 * PTE calls. 246 */ 247 static int moea_pte_insert(u_int, struct pte *); 248 249 /* 250 * PVO calls. 251 */ 252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_paddr_t, u_int, int); 254 static void moea_pvo_remove(struct pvo_entry *, int); 255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258 /* 259 * Utility routines. 260 */ 261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, u_int, int8_t); 263 static void moea_syncicache(vm_paddr_t, vm_size_t); 264 static boolean_t moea_query_bit(vm_page_t, int); 265 static u_int moea_clear_bit(vm_page_t, int); 266 static void moea_kremove(mmu_t, vm_offset_t); 267 int moea_pte_spill(vm_offset_t); 268 269 /* 270 * Kernel MMU interface 271 */ 272 void moea_clear_modify(mmu_t, vm_page_t); 273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 275 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 277 int8_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 int moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_zero_page(mmu_t, vm_page_t); 302 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 303 void moea_zero_page_idle(mmu_t, vm_page_t); 304 void moea_activate(mmu_t, struct thread *); 305 void moea_deactivate(mmu_t, struct thread *); 306 void moea_cpu_bootstrap(mmu_t, int); 307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 309 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 317 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 318 void moea_scan_init(mmu_t mmu); 319 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 320 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 321 322 static mmu_method_t moea_methods[] = { 323 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 324 MMUMETHOD(mmu_copy_page, moea_copy_page), 325 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 326 MMUMETHOD(mmu_enter, moea_enter), 327 MMUMETHOD(mmu_enter_object, moea_enter_object), 328 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 329 MMUMETHOD(mmu_extract, moea_extract), 330 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 331 MMUMETHOD(mmu_init, moea_init), 332 MMUMETHOD(mmu_is_modified, moea_is_modified), 333 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 334 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 335 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 336 MMUMETHOD(mmu_map, moea_map), 337 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 338 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 339 MMUMETHOD(mmu_pinit, moea_pinit), 340 MMUMETHOD(mmu_pinit0, moea_pinit0), 341 MMUMETHOD(mmu_protect, moea_protect), 342 MMUMETHOD(mmu_qenter, moea_qenter), 343 MMUMETHOD(mmu_qremove, moea_qremove), 344 MMUMETHOD(mmu_release, moea_release), 345 MMUMETHOD(mmu_remove, moea_remove), 346 MMUMETHOD(mmu_remove_all, moea_remove_all), 347 MMUMETHOD(mmu_remove_write, moea_remove_write), 348 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 349 MMUMETHOD(mmu_unwire, moea_unwire), 350 MMUMETHOD(mmu_zero_page, moea_zero_page), 351 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 352 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 353 MMUMETHOD(mmu_activate, moea_activate), 354 MMUMETHOD(mmu_deactivate, moea_deactivate), 355 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 356 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 357 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 358 359 /* Internal interfaces */ 360 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 361 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 362 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 363 MMUMETHOD(mmu_mapdev, moea_mapdev), 364 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 365 MMUMETHOD(mmu_kextract, moea_kextract), 366 MMUMETHOD(mmu_kenter, moea_kenter), 367 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 368 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 369 MMUMETHOD(mmu_scan_init, moea_scan_init), 370 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 371 372 { 0, 0 } 373 }; 374 375 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 376 377 static __inline uint32_t 378 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 379 { 380 uint32_t pte_lo; 381 int i; 382 383 if (ma != VM_MEMATTR_DEFAULT) { 384 switch (ma) { 385 case VM_MEMATTR_UNCACHEABLE: 386 return (PTE_I | PTE_G); 387 case VM_MEMATTR_CACHEABLE: 388 return (PTE_M); 389 case VM_MEMATTR_WRITE_COMBINING: 390 case VM_MEMATTR_WRITE_BACK: 391 case VM_MEMATTR_PREFETCHABLE: 392 return (PTE_I); 393 case VM_MEMATTR_WRITE_THROUGH: 394 return (PTE_W | PTE_M); 395 } 396 } 397 398 /* 399 * Assume the page is cache inhibited and access is guarded unless 400 * it's in our available memory array. 401 */ 402 pte_lo = PTE_I | PTE_G; 403 for (i = 0; i < pregions_sz; i++) { 404 if ((pa >= pregions[i].mr_start) && 405 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 406 pte_lo = PTE_M; 407 break; 408 } 409 } 410 411 return pte_lo; 412 } 413 414 static void 415 tlbie(vm_offset_t va) 416 { 417 418 mtx_lock_spin(&tlbie_mtx); 419 __asm __volatile("ptesync"); 420 __asm __volatile("tlbie %0" :: "r"(va)); 421 __asm __volatile("eieio; tlbsync; ptesync"); 422 mtx_unlock_spin(&tlbie_mtx); 423 } 424 425 static void 426 tlbia(void) 427 { 428 vm_offset_t va; 429 430 for (va = 0; va < 0x00040000; va += 0x00001000) { 431 __asm __volatile("tlbie %0" :: "r"(va)); 432 powerpc_sync(); 433 } 434 __asm __volatile("tlbsync"); 435 powerpc_sync(); 436 } 437 438 static __inline int 439 va_to_sr(u_int *sr, vm_offset_t va) 440 { 441 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 442 } 443 444 static __inline u_int 445 va_to_pteg(u_int sr, vm_offset_t addr) 446 { 447 u_int hash; 448 449 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 450 ADDR_PIDX_SHFT); 451 return (hash & moea_pteg_mask); 452 } 453 454 static __inline struct pvo_head * 455 vm_page_to_pvoh(vm_page_t m) 456 { 457 458 return (&m->md.mdpg_pvoh); 459 } 460 461 static __inline void 462 moea_attr_clear(vm_page_t m, int ptebit) 463 { 464 465 rw_assert(&pvh_global_lock, RA_WLOCKED); 466 m->md.mdpg_attrs &= ~ptebit; 467 } 468 469 static __inline int 470 moea_attr_fetch(vm_page_t m) 471 { 472 473 return (m->md.mdpg_attrs); 474 } 475 476 static __inline void 477 moea_attr_save(vm_page_t m, int ptebit) 478 { 479 480 rw_assert(&pvh_global_lock, RA_WLOCKED); 481 m->md.mdpg_attrs |= ptebit; 482 } 483 484 static __inline int 485 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 486 { 487 if (pt->pte_hi == pvo_pt->pte_hi) 488 return (1); 489 490 return (0); 491 } 492 493 static __inline int 494 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 495 { 496 return (pt->pte_hi & ~PTE_VALID) == 497 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 498 ((va >> ADDR_API_SHFT) & PTE_API) | which); 499 } 500 501 static __inline void 502 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 503 { 504 505 mtx_assert(&moea_table_mutex, MA_OWNED); 506 507 /* 508 * Construct a PTE. Default to IMB initially. Valid bit only gets 509 * set when the real pte is set in memory. 510 * 511 * Note: Don't set the valid bit for correct operation of tlb update. 512 */ 513 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 514 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 515 pt->pte_lo = pte_lo; 516 } 517 518 static __inline void 519 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 520 { 521 522 mtx_assert(&moea_table_mutex, MA_OWNED); 523 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 524 } 525 526 static __inline void 527 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 528 { 529 530 mtx_assert(&moea_table_mutex, MA_OWNED); 531 532 /* 533 * As shown in Section 7.6.3.2.3 534 */ 535 pt->pte_lo &= ~ptebit; 536 tlbie(va); 537 } 538 539 static __inline void 540 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 541 { 542 543 mtx_assert(&moea_table_mutex, MA_OWNED); 544 pvo_pt->pte_hi |= PTE_VALID; 545 546 /* 547 * Update the PTE as defined in section 7.6.3.1. 548 * Note that the REF/CHG bits are from pvo_pt and thus should have 549 * been saved so this routine can restore them (if desired). 550 */ 551 pt->pte_lo = pvo_pt->pte_lo; 552 powerpc_sync(); 553 pt->pte_hi = pvo_pt->pte_hi; 554 powerpc_sync(); 555 moea_pte_valid++; 556 } 557 558 static __inline void 559 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 560 { 561 562 mtx_assert(&moea_table_mutex, MA_OWNED); 563 pvo_pt->pte_hi &= ~PTE_VALID; 564 565 /* 566 * Force the reg & chg bits back into the PTEs. 567 */ 568 powerpc_sync(); 569 570 /* 571 * Invalidate the pte. 572 */ 573 pt->pte_hi &= ~PTE_VALID; 574 575 tlbie(va); 576 577 /* 578 * Save the reg & chg bits. 579 */ 580 moea_pte_synch(pt, pvo_pt); 581 moea_pte_valid--; 582 } 583 584 static __inline void 585 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 586 { 587 588 /* 589 * Invalidate the PTE 590 */ 591 moea_pte_unset(pt, pvo_pt, va); 592 moea_pte_set(pt, pvo_pt); 593 } 594 595 /* 596 * Quick sort callout for comparing memory regions. 597 */ 598 static int om_cmp(const void *a, const void *b); 599 600 static int 601 om_cmp(const void *a, const void *b) 602 { 603 const struct ofw_map *mapa; 604 const struct ofw_map *mapb; 605 606 mapa = a; 607 mapb = b; 608 if (mapa->om_pa < mapb->om_pa) 609 return (-1); 610 else if (mapa->om_pa > mapb->om_pa) 611 return (1); 612 else 613 return (0); 614 } 615 616 void 617 moea_cpu_bootstrap(mmu_t mmup, int ap) 618 { 619 u_int sdr; 620 int i; 621 622 if (ap) { 623 powerpc_sync(); 624 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 625 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 626 isync(); 627 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 628 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 629 isync(); 630 } 631 632 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 633 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 634 isync(); 635 636 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 637 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 638 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 639 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 640 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 641 isync(); 642 643 for (i = 0; i < 16; i++) 644 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 645 powerpc_sync(); 646 647 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 648 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 649 isync(); 650 651 tlbia(); 652 } 653 654 void 655 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 656 { 657 ihandle_t mmui; 658 phandle_t chosen, mmu; 659 int sz; 660 int i, j; 661 vm_size_t size, physsz, hwphyssz; 662 vm_offset_t pa, va, off; 663 void *dpcpu; 664 register_t msr; 665 666 /* 667 * Set up BAT0 to map the lowest 256 MB area 668 */ 669 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 670 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 671 672 /* 673 * Map PCI memory space. 674 */ 675 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 676 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 677 678 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 679 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 680 681 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 682 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 683 684 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 686 687 /* 688 * Map obio devices. 689 */ 690 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 692 693 /* 694 * Use an IBAT and a DBAT to map the bottom segment of memory 695 * where we are. Turn off instruction relocation temporarily 696 * to prevent faults while reprogramming the IBAT. 697 */ 698 msr = mfmsr(); 699 mtmsr(msr & ~PSL_IR); 700 __asm (".balign 32; \n" 701 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 702 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 703 :: "r"(battable[0].batu), "r"(battable[0].batl)); 704 mtmsr(msr); 705 706 /* map pci space */ 707 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 708 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 709 isync(); 710 711 /* set global direct map flag */ 712 hw_direct_map = 1; 713 714 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 715 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 716 717 for (i = 0; i < pregions_sz; i++) { 718 vm_offset_t pa; 719 vm_offset_t end; 720 721 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 722 pregions[i].mr_start, 723 pregions[i].mr_start + pregions[i].mr_size, 724 pregions[i].mr_size); 725 /* 726 * Install entries into the BAT table to allow all 727 * of physmem to be convered by on-demand BAT entries. 728 * The loop will sometimes set the same battable element 729 * twice, but that's fine since they won't be used for 730 * a while yet. 731 */ 732 pa = pregions[i].mr_start & 0xf0000000; 733 end = pregions[i].mr_start + pregions[i].mr_size; 734 do { 735 u_int n = pa >> ADDR_SR_SHFT; 736 737 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 738 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 739 pa += SEGMENT_LENGTH; 740 } while (pa < end); 741 } 742 743 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 744 panic("moea_bootstrap: phys_avail too small"); 745 746 phys_avail_count = 0; 747 physsz = 0; 748 hwphyssz = 0; 749 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 750 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 751 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 752 regions[i].mr_start + regions[i].mr_size, 753 regions[i].mr_size); 754 if (hwphyssz != 0 && 755 (physsz + regions[i].mr_size) >= hwphyssz) { 756 if (physsz < hwphyssz) { 757 phys_avail[j] = regions[i].mr_start; 758 phys_avail[j + 1] = regions[i].mr_start + 759 hwphyssz - physsz; 760 physsz = hwphyssz; 761 phys_avail_count++; 762 } 763 break; 764 } 765 phys_avail[j] = regions[i].mr_start; 766 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 767 phys_avail_count++; 768 physsz += regions[i].mr_size; 769 } 770 771 /* Check for overlap with the kernel and exception vectors */ 772 for (j = 0; j < 2*phys_avail_count; j+=2) { 773 if (phys_avail[j] < EXC_LAST) 774 phys_avail[j] += EXC_LAST; 775 776 if (kernelstart >= phys_avail[j] && 777 kernelstart < phys_avail[j+1]) { 778 if (kernelend < phys_avail[j+1]) { 779 phys_avail[2*phys_avail_count] = 780 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 781 phys_avail[2*phys_avail_count + 1] = 782 phys_avail[j+1]; 783 phys_avail_count++; 784 } 785 786 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 787 } 788 789 if (kernelend >= phys_avail[j] && 790 kernelend < phys_avail[j+1]) { 791 if (kernelstart > phys_avail[j]) { 792 phys_avail[2*phys_avail_count] = phys_avail[j]; 793 phys_avail[2*phys_avail_count + 1] = 794 kernelstart & ~PAGE_MASK; 795 phys_avail_count++; 796 } 797 798 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 799 } 800 } 801 802 physmem = btoc(physsz); 803 804 /* 805 * Allocate PTEG table. 806 */ 807 #ifdef PTEGCOUNT 808 moea_pteg_count = PTEGCOUNT; 809 #else 810 moea_pteg_count = 0x1000; 811 812 while (moea_pteg_count < physmem) 813 moea_pteg_count <<= 1; 814 815 moea_pteg_count >>= 1; 816 #endif /* PTEGCOUNT */ 817 818 size = moea_pteg_count * sizeof(struct pteg); 819 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 820 size); 821 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 822 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 823 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 824 moea_pteg_mask = moea_pteg_count - 1; 825 826 /* 827 * Allocate pv/overflow lists. 828 */ 829 size = sizeof(struct pvo_head) * moea_pteg_count; 830 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 831 PAGE_SIZE); 832 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 833 for (i = 0; i < moea_pteg_count; i++) 834 LIST_INIT(&moea_pvo_table[i]); 835 836 /* 837 * Initialize the lock that synchronizes access to the pteg and pvo 838 * tables. 839 */ 840 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 841 MTX_RECURSE); 842 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 843 844 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 845 846 /* 847 * Initialise the unmanaged pvo pool. 848 */ 849 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 850 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 851 moea_bpvo_pool_index = 0; 852 853 /* 854 * Make sure kernel vsid is allocated as well as VSID 0. 855 */ 856 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 857 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 858 moea_vsid_bitmap[0] |= 1; 859 860 /* 861 * Initialize the kernel pmap (which is statically allocated). 862 */ 863 PMAP_LOCK_INIT(kernel_pmap); 864 for (i = 0; i < 16; i++) 865 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 866 CPU_FILL(&kernel_pmap->pm_active); 867 RB_INIT(&kernel_pmap->pmap_pvo); 868 869 /* 870 * Initialize the global pv list lock. 871 */ 872 rw_init(&pvh_global_lock, "pmap pv global"); 873 874 /* 875 * Set up the Open Firmware mappings 876 */ 877 chosen = OF_finddevice("/chosen"); 878 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 879 (mmu = OF_instance_to_package(mmui)) != -1 && 880 (sz = OF_getproplen(mmu, "translations")) != -1) { 881 translations = NULL; 882 for (i = 0; phys_avail[i] != 0; i += 2) { 883 if (phys_avail[i + 1] >= sz) { 884 translations = (struct ofw_map *)phys_avail[i]; 885 break; 886 } 887 } 888 if (translations == NULL) 889 panic("moea_bootstrap: no space to copy translations"); 890 bzero(translations, sz); 891 if (OF_getprop(mmu, "translations", translations, sz) == -1) 892 panic("moea_bootstrap: can't get ofw translations"); 893 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 894 sz /= sizeof(*translations); 895 qsort(translations, sz, sizeof (*translations), om_cmp); 896 for (i = 0; i < sz; i++) { 897 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 898 translations[i].om_pa, translations[i].om_va, 899 translations[i].om_len); 900 901 /* 902 * If the mapping is 1:1, let the RAM and device 903 * on-demand BAT tables take care of the translation. 904 */ 905 if (translations[i].om_va == translations[i].om_pa) 906 continue; 907 908 /* Enter the pages */ 909 for (off = 0; off < translations[i].om_len; 910 off += PAGE_SIZE) 911 moea_kenter(mmup, translations[i].om_va + off, 912 translations[i].om_pa + off); 913 } 914 } 915 916 /* 917 * Calculate the last available physical address. 918 */ 919 for (i = 0; phys_avail[i + 2] != 0; i += 2) 920 ; 921 Maxmem = powerpc_btop(phys_avail[i + 1]); 922 923 moea_cpu_bootstrap(mmup,0); 924 mtmsr(mfmsr() | PSL_DR | PSL_IR); 925 pmap_bootstrapped++; 926 927 /* 928 * Set the start and end of kva. 929 */ 930 virtual_avail = VM_MIN_KERNEL_ADDRESS; 931 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 932 933 /* 934 * Allocate a kernel stack with a guard page for thread0 and map it 935 * into the kernel page map. 936 */ 937 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 938 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 939 virtual_avail = va + kstack_pages * PAGE_SIZE; 940 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 941 thread0.td_kstack = va; 942 thread0.td_kstack_pages = kstack_pages; 943 for (i = 0; i < kstack_pages; i++) { 944 moea_kenter(mmup, va, pa); 945 pa += PAGE_SIZE; 946 va += PAGE_SIZE; 947 } 948 949 /* 950 * Allocate virtual address space for the message buffer. 951 */ 952 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 953 msgbufp = (struct msgbuf *)virtual_avail; 954 va = virtual_avail; 955 virtual_avail += round_page(msgbufsize); 956 while (va < virtual_avail) { 957 moea_kenter(mmup, va, pa); 958 pa += PAGE_SIZE; 959 va += PAGE_SIZE; 960 } 961 962 /* 963 * Allocate virtual address space for the dynamic percpu area. 964 */ 965 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 966 dpcpu = (void *)virtual_avail; 967 va = virtual_avail; 968 virtual_avail += DPCPU_SIZE; 969 while (va < virtual_avail) { 970 moea_kenter(mmup, va, pa); 971 pa += PAGE_SIZE; 972 va += PAGE_SIZE; 973 } 974 dpcpu_init(dpcpu, 0); 975 } 976 977 /* 978 * Activate a user pmap. The pmap must be activated before it's address 979 * space can be accessed in any way. 980 */ 981 void 982 moea_activate(mmu_t mmu, struct thread *td) 983 { 984 pmap_t pm, pmr; 985 986 /* 987 * Load all the data we need up front to encourage the compiler to 988 * not issue any loads while we have interrupts disabled below. 989 */ 990 pm = &td->td_proc->p_vmspace->vm_pmap; 991 pmr = pm->pmap_phys; 992 993 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 994 PCPU_SET(curpmap, pmr); 995 996 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 997 } 998 999 void 1000 moea_deactivate(mmu_t mmu, struct thread *td) 1001 { 1002 pmap_t pm; 1003 1004 pm = &td->td_proc->p_vmspace->vm_pmap; 1005 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1006 PCPU_SET(curpmap, NULL); 1007 } 1008 1009 void 1010 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1011 { 1012 struct pvo_entry key, *pvo; 1013 1014 PMAP_LOCK(pm); 1015 key.pvo_vaddr = sva; 1016 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1017 pvo != NULL && PVO_VADDR(pvo) < eva; 1018 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1019 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1020 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1021 pvo->pvo_vaddr &= ~PVO_WIRED; 1022 pm->pm_stats.wired_count--; 1023 } 1024 PMAP_UNLOCK(pm); 1025 } 1026 1027 void 1028 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1029 { 1030 vm_offset_t dst; 1031 vm_offset_t src; 1032 1033 dst = VM_PAGE_TO_PHYS(mdst); 1034 src = VM_PAGE_TO_PHYS(msrc); 1035 1036 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1037 } 1038 1039 void 1040 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1041 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1042 { 1043 void *a_cp, *b_cp; 1044 vm_offset_t a_pg_offset, b_pg_offset; 1045 int cnt; 1046 1047 while (xfersize > 0) { 1048 a_pg_offset = a_offset & PAGE_MASK; 1049 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1050 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1051 a_pg_offset; 1052 b_pg_offset = b_offset & PAGE_MASK; 1053 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1054 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1055 b_pg_offset; 1056 bcopy(a_cp, b_cp, cnt); 1057 a_offset += cnt; 1058 b_offset += cnt; 1059 xfersize -= cnt; 1060 } 1061 } 1062 1063 /* 1064 * Zero a page of physical memory by temporarily mapping it into the tlb. 1065 */ 1066 void 1067 moea_zero_page(mmu_t mmu, vm_page_t m) 1068 { 1069 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1070 1071 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1072 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1073 } 1074 1075 void 1076 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1077 { 1078 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1079 void *va = (void *)(pa + off); 1080 1081 bzero(va, size); 1082 } 1083 1084 void 1085 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1086 { 1087 1088 moea_zero_page(mmu, m); 1089 } 1090 1091 vm_offset_t 1092 moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1093 { 1094 1095 return (VM_PAGE_TO_PHYS(m)); 1096 } 1097 1098 void 1099 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1100 { 1101 } 1102 1103 /* 1104 * Map the given physical page at the specified virtual address in the 1105 * target pmap with the protection requested. If specified the page 1106 * will be wired down. 1107 */ 1108 int 1109 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1110 u_int flags, int8_t psind) 1111 { 1112 int error; 1113 1114 for (;;) { 1115 rw_wlock(&pvh_global_lock); 1116 PMAP_LOCK(pmap); 1117 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1118 rw_wunlock(&pvh_global_lock); 1119 PMAP_UNLOCK(pmap); 1120 if (error != ENOMEM) 1121 return (KERN_SUCCESS); 1122 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1123 return (KERN_RESOURCE_SHORTAGE); 1124 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1125 VM_WAIT; 1126 } 1127 } 1128 1129 /* 1130 * Map the given physical page at the specified virtual address in the 1131 * target pmap with the protection requested. If specified the page 1132 * will be wired down. 1133 * 1134 * The global pvh and pmap must be locked. 1135 */ 1136 static int 1137 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1138 u_int flags, int8_t psind __unused) 1139 { 1140 struct pvo_head *pvo_head; 1141 uma_zone_t zone; 1142 u_int pte_lo, pvo_flags; 1143 int error; 1144 1145 if (pmap_bootstrapped) 1146 rw_assert(&pvh_global_lock, RA_WLOCKED); 1147 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1148 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1149 VM_OBJECT_ASSERT_LOCKED(m->object); 1150 1151 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1152 pvo_head = &moea_pvo_kunmanaged; 1153 zone = moea_upvo_zone; 1154 pvo_flags = 0; 1155 } else { 1156 pvo_head = vm_page_to_pvoh(m); 1157 zone = moea_mpvo_zone; 1158 pvo_flags = PVO_MANAGED; 1159 } 1160 1161 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1162 1163 if (prot & VM_PROT_WRITE) { 1164 pte_lo |= PTE_BW; 1165 if (pmap_bootstrapped && 1166 (m->oflags & VPO_UNMANAGED) == 0) 1167 vm_page_aflag_set(m, PGA_WRITEABLE); 1168 } else 1169 pte_lo |= PTE_BR; 1170 1171 if ((flags & PMAP_ENTER_WIRED) != 0) 1172 pvo_flags |= PVO_WIRED; 1173 1174 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1175 pte_lo, pvo_flags); 1176 1177 /* 1178 * Flush the real page from the instruction cache. This has be done 1179 * for all user mappings to prevent information leakage via the 1180 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1181 * mapping for a page. 1182 */ 1183 if (pmap != kernel_pmap && error == ENOENT && 1184 (pte_lo & (PTE_I | PTE_G)) == 0) 1185 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1186 1187 return (error); 1188 } 1189 1190 /* 1191 * Maps a sequence of resident pages belonging to the same object. 1192 * The sequence begins with the given page m_start. This page is 1193 * mapped at the given virtual address start. Each subsequent page is 1194 * mapped at a virtual address that is offset from start by the same 1195 * amount as the page is offset from m_start within the object. The 1196 * last page in the sequence is the page with the largest offset from 1197 * m_start that can be mapped at a virtual address less than the given 1198 * virtual address end. Not every virtual page between start and end 1199 * is mapped; only those for which a resident page exists with the 1200 * corresponding offset from m_start are mapped. 1201 */ 1202 void 1203 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1204 vm_page_t m_start, vm_prot_t prot) 1205 { 1206 vm_page_t m; 1207 vm_pindex_t diff, psize; 1208 1209 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1210 1211 psize = atop(end - start); 1212 m = m_start; 1213 rw_wlock(&pvh_global_lock); 1214 PMAP_LOCK(pm); 1215 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1216 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1217 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1218 m = TAILQ_NEXT(m, listq); 1219 } 1220 rw_wunlock(&pvh_global_lock); 1221 PMAP_UNLOCK(pm); 1222 } 1223 1224 void 1225 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1226 vm_prot_t prot) 1227 { 1228 1229 rw_wlock(&pvh_global_lock); 1230 PMAP_LOCK(pm); 1231 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1232 0, 0); 1233 rw_wunlock(&pvh_global_lock); 1234 PMAP_UNLOCK(pm); 1235 } 1236 1237 vm_paddr_t 1238 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1239 { 1240 struct pvo_entry *pvo; 1241 vm_paddr_t pa; 1242 1243 PMAP_LOCK(pm); 1244 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1245 if (pvo == NULL) 1246 pa = 0; 1247 else 1248 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1249 PMAP_UNLOCK(pm); 1250 return (pa); 1251 } 1252 1253 /* 1254 * Atomically extract and hold the physical page with the given 1255 * pmap and virtual address pair if that mapping permits the given 1256 * protection. 1257 */ 1258 vm_page_t 1259 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1260 { 1261 struct pvo_entry *pvo; 1262 vm_page_t m; 1263 vm_paddr_t pa; 1264 1265 m = NULL; 1266 pa = 0; 1267 PMAP_LOCK(pmap); 1268 retry: 1269 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1270 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1271 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1272 (prot & VM_PROT_WRITE) == 0)) { 1273 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1274 goto retry; 1275 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1276 vm_page_hold(m); 1277 } 1278 PA_UNLOCK_COND(pa); 1279 PMAP_UNLOCK(pmap); 1280 return (m); 1281 } 1282 1283 void 1284 moea_init(mmu_t mmu) 1285 { 1286 1287 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1288 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1289 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1290 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1291 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1292 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1293 moea_initialized = TRUE; 1294 } 1295 1296 boolean_t 1297 moea_is_referenced(mmu_t mmu, vm_page_t m) 1298 { 1299 boolean_t rv; 1300 1301 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1302 ("moea_is_referenced: page %p is not managed", m)); 1303 rw_wlock(&pvh_global_lock); 1304 rv = moea_query_bit(m, PTE_REF); 1305 rw_wunlock(&pvh_global_lock); 1306 return (rv); 1307 } 1308 1309 boolean_t 1310 moea_is_modified(mmu_t mmu, vm_page_t m) 1311 { 1312 boolean_t rv; 1313 1314 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1315 ("moea_is_modified: page %p is not managed", m)); 1316 1317 /* 1318 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1319 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1320 * is clear, no PTEs can have PTE_CHG set. 1321 */ 1322 VM_OBJECT_ASSERT_WLOCKED(m->object); 1323 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1324 return (FALSE); 1325 rw_wlock(&pvh_global_lock); 1326 rv = moea_query_bit(m, PTE_CHG); 1327 rw_wunlock(&pvh_global_lock); 1328 return (rv); 1329 } 1330 1331 boolean_t 1332 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1333 { 1334 struct pvo_entry *pvo; 1335 boolean_t rv; 1336 1337 PMAP_LOCK(pmap); 1338 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1339 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1340 PMAP_UNLOCK(pmap); 1341 return (rv); 1342 } 1343 1344 void 1345 moea_clear_modify(mmu_t mmu, vm_page_t m) 1346 { 1347 1348 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1349 ("moea_clear_modify: page %p is not managed", m)); 1350 VM_OBJECT_ASSERT_WLOCKED(m->object); 1351 KASSERT(!vm_page_xbusied(m), 1352 ("moea_clear_modify: page %p is exclusive busy", m)); 1353 1354 /* 1355 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1356 * set. If the object containing the page is locked and the page is 1357 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1358 */ 1359 if ((m->aflags & PGA_WRITEABLE) == 0) 1360 return; 1361 rw_wlock(&pvh_global_lock); 1362 moea_clear_bit(m, PTE_CHG); 1363 rw_wunlock(&pvh_global_lock); 1364 } 1365 1366 /* 1367 * Clear the write and modified bits in each of the given page's mappings. 1368 */ 1369 void 1370 moea_remove_write(mmu_t mmu, vm_page_t m) 1371 { 1372 struct pvo_entry *pvo; 1373 struct pte *pt; 1374 pmap_t pmap; 1375 u_int lo; 1376 1377 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1378 ("moea_remove_write: page %p is not managed", m)); 1379 1380 /* 1381 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1382 * set by another thread while the object is locked. Thus, 1383 * if PGA_WRITEABLE is clear, no page table entries need updating. 1384 */ 1385 VM_OBJECT_ASSERT_WLOCKED(m->object); 1386 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1387 return; 1388 rw_wlock(&pvh_global_lock); 1389 lo = moea_attr_fetch(m); 1390 powerpc_sync(); 1391 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1392 pmap = pvo->pvo_pmap; 1393 PMAP_LOCK(pmap); 1394 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1395 pt = moea_pvo_to_pte(pvo, -1); 1396 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1397 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1398 if (pt != NULL) { 1399 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1400 lo |= pvo->pvo_pte.pte.pte_lo; 1401 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1402 moea_pte_change(pt, &pvo->pvo_pte.pte, 1403 pvo->pvo_vaddr); 1404 mtx_unlock(&moea_table_mutex); 1405 } 1406 } 1407 PMAP_UNLOCK(pmap); 1408 } 1409 if ((lo & PTE_CHG) != 0) { 1410 moea_attr_clear(m, PTE_CHG); 1411 vm_page_dirty(m); 1412 } 1413 vm_page_aflag_clear(m, PGA_WRITEABLE); 1414 rw_wunlock(&pvh_global_lock); 1415 } 1416 1417 /* 1418 * moea_ts_referenced: 1419 * 1420 * Return a count of reference bits for a page, clearing those bits. 1421 * It is not necessary for every reference bit to be cleared, but it 1422 * is necessary that 0 only be returned when there are truly no 1423 * reference bits set. 1424 * 1425 * XXX: The exact number of bits to check and clear is a matter that 1426 * should be tested and standardized at some point in the future for 1427 * optimal aging of shared pages. 1428 */ 1429 int 1430 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1431 { 1432 int count; 1433 1434 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1435 ("moea_ts_referenced: page %p is not managed", m)); 1436 rw_wlock(&pvh_global_lock); 1437 count = moea_clear_bit(m, PTE_REF); 1438 rw_wunlock(&pvh_global_lock); 1439 return (count); 1440 } 1441 1442 /* 1443 * Modify the WIMG settings of all mappings for a page. 1444 */ 1445 void 1446 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1447 { 1448 struct pvo_entry *pvo; 1449 struct pvo_head *pvo_head; 1450 struct pte *pt; 1451 pmap_t pmap; 1452 u_int lo; 1453 1454 if ((m->oflags & VPO_UNMANAGED) != 0) { 1455 m->md.mdpg_cache_attrs = ma; 1456 return; 1457 } 1458 1459 rw_wlock(&pvh_global_lock); 1460 pvo_head = vm_page_to_pvoh(m); 1461 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1462 1463 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1464 pmap = pvo->pvo_pmap; 1465 PMAP_LOCK(pmap); 1466 pt = moea_pvo_to_pte(pvo, -1); 1467 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1468 pvo->pvo_pte.pte.pte_lo |= lo; 1469 if (pt != NULL) { 1470 moea_pte_change(pt, &pvo->pvo_pte.pte, 1471 pvo->pvo_vaddr); 1472 if (pvo->pvo_pmap == kernel_pmap) 1473 isync(); 1474 } 1475 mtx_unlock(&moea_table_mutex); 1476 PMAP_UNLOCK(pmap); 1477 } 1478 m->md.mdpg_cache_attrs = ma; 1479 rw_wunlock(&pvh_global_lock); 1480 } 1481 1482 /* 1483 * Map a wired page into kernel virtual address space. 1484 */ 1485 void 1486 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1487 { 1488 1489 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1490 } 1491 1492 void 1493 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1494 { 1495 u_int pte_lo; 1496 int error; 1497 1498 #if 0 1499 if (va < VM_MIN_KERNEL_ADDRESS) 1500 panic("moea_kenter: attempt to enter non-kernel address %#x", 1501 va); 1502 #endif 1503 1504 pte_lo = moea_calc_wimg(pa, ma); 1505 1506 PMAP_LOCK(kernel_pmap); 1507 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1508 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1509 1510 if (error != 0 && error != ENOENT) 1511 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1512 pa, error); 1513 1514 PMAP_UNLOCK(kernel_pmap); 1515 } 1516 1517 /* 1518 * Extract the physical page address associated with the given kernel virtual 1519 * address. 1520 */ 1521 vm_paddr_t 1522 moea_kextract(mmu_t mmu, vm_offset_t va) 1523 { 1524 struct pvo_entry *pvo; 1525 vm_paddr_t pa; 1526 1527 /* 1528 * Allow direct mappings on 32-bit OEA 1529 */ 1530 if (va < VM_MIN_KERNEL_ADDRESS) { 1531 return (va); 1532 } 1533 1534 PMAP_LOCK(kernel_pmap); 1535 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1536 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1537 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1538 PMAP_UNLOCK(kernel_pmap); 1539 return (pa); 1540 } 1541 1542 /* 1543 * Remove a wired page from kernel virtual address space. 1544 */ 1545 void 1546 moea_kremove(mmu_t mmu, vm_offset_t va) 1547 { 1548 1549 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1550 } 1551 1552 /* 1553 * Map a range of physical addresses into kernel virtual address space. 1554 * 1555 * The value passed in *virt is a suggested virtual address for the mapping. 1556 * Architectures which can support a direct-mapped physical to virtual region 1557 * can return the appropriate address within that region, leaving '*virt' 1558 * unchanged. We cannot and therefore do not; *virt is updated with the 1559 * first usable address after the mapped region. 1560 */ 1561 vm_offset_t 1562 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1563 vm_paddr_t pa_end, int prot) 1564 { 1565 vm_offset_t sva, va; 1566 1567 sva = *virt; 1568 va = sva; 1569 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1570 moea_kenter(mmu, va, pa_start); 1571 *virt = va; 1572 return (sva); 1573 } 1574 1575 /* 1576 * Returns true if the pmap's pv is one of the first 1577 * 16 pvs linked to from this page. This count may 1578 * be changed upwards or downwards in the future; it 1579 * is only necessary that true be returned for a small 1580 * subset of pmaps for proper page aging. 1581 */ 1582 boolean_t 1583 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1584 { 1585 int loops; 1586 struct pvo_entry *pvo; 1587 boolean_t rv; 1588 1589 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1590 ("moea_page_exists_quick: page %p is not managed", m)); 1591 loops = 0; 1592 rv = FALSE; 1593 rw_wlock(&pvh_global_lock); 1594 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1595 if (pvo->pvo_pmap == pmap) { 1596 rv = TRUE; 1597 break; 1598 } 1599 if (++loops >= 16) 1600 break; 1601 } 1602 rw_wunlock(&pvh_global_lock); 1603 return (rv); 1604 } 1605 1606 /* 1607 * Return the number of managed mappings to the given physical page 1608 * that are wired. 1609 */ 1610 int 1611 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1612 { 1613 struct pvo_entry *pvo; 1614 int count; 1615 1616 count = 0; 1617 if ((m->oflags & VPO_UNMANAGED) != 0) 1618 return (count); 1619 rw_wlock(&pvh_global_lock); 1620 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1621 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1622 count++; 1623 rw_wunlock(&pvh_global_lock); 1624 return (count); 1625 } 1626 1627 static u_int moea_vsidcontext; 1628 1629 void 1630 moea_pinit(mmu_t mmu, pmap_t pmap) 1631 { 1632 int i, mask; 1633 u_int entropy; 1634 1635 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1636 RB_INIT(&pmap->pmap_pvo); 1637 1638 entropy = 0; 1639 __asm __volatile("mftb %0" : "=r"(entropy)); 1640 1641 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1642 == NULL) { 1643 pmap->pmap_phys = pmap; 1644 } 1645 1646 1647 mtx_lock(&moea_vsid_mutex); 1648 /* 1649 * Allocate some segment registers for this pmap. 1650 */ 1651 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1652 u_int hash, n; 1653 1654 /* 1655 * Create a new value by mutiplying by a prime and adding in 1656 * entropy from the timebase register. This is to make the 1657 * VSID more random so that the PT hash function collides 1658 * less often. (Note that the prime casues gcc to do shifts 1659 * instead of a multiply.) 1660 */ 1661 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1662 hash = moea_vsidcontext & (NPMAPS - 1); 1663 if (hash == 0) /* 0 is special, avoid it */ 1664 continue; 1665 n = hash >> 5; 1666 mask = 1 << (hash & (VSID_NBPW - 1)); 1667 hash = (moea_vsidcontext & 0xfffff); 1668 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1669 /* anything free in this bucket? */ 1670 if (moea_vsid_bitmap[n] == 0xffffffff) { 1671 entropy = (moea_vsidcontext >> 20); 1672 continue; 1673 } 1674 i = ffs(~moea_vsid_bitmap[n]) - 1; 1675 mask = 1 << i; 1676 hash &= rounddown2(0xfffff, VSID_NBPW); 1677 hash |= i; 1678 } 1679 KASSERT(!(moea_vsid_bitmap[n] & mask), 1680 ("Allocating in-use VSID group %#x\n", hash)); 1681 moea_vsid_bitmap[n] |= mask; 1682 for (i = 0; i < 16; i++) 1683 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1684 mtx_unlock(&moea_vsid_mutex); 1685 return; 1686 } 1687 1688 mtx_unlock(&moea_vsid_mutex); 1689 panic("moea_pinit: out of segments"); 1690 } 1691 1692 /* 1693 * Initialize the pmap associated with process 0. 1694 */ 1695 void 1696 moea_pinit0(mmu_t mmu, pmap_t pm) 1697 { 1698 1699 PMAP_LOCK_INIT(pm); 1700 moea_pinit(mmu, pm); 1701 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1702 } 1703 1704 /* 1705 * Set the physical protection on the specified range of this map as requested. 1706 */ 1707 void 1708 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1709 vm_prot_t prot) 1710 { 1711 struct pvo_entry *pvo, *tpvo, key; 1712 struct pte *pt; 1713 1714 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1715 ("moea_protect: non current pmap")); 1716 1717 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1718 moea_remove(mmu, pm, sva, eva); 1719 return; 1720 } 1721 1722 rw_wlock(&pvh_global_lock); 1723 PMAP_LOCK(pm); 1724 key.pvo_vaddr = sva; 1725 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1726 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1727 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1728 1729 /* 1730 * Grab the PTE pointer before we diddle with the cached PTE 1731 * copy. 1732 */ 1733 pt = moea_pvo_to_pte(pvo, -1); 1734 /* 1735 * Change the protection of the page. 1736 */ 1737 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1738 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1739 1740 /* 1741 * If the PVO is in the page table, update that pte as well. 1742 */ 1743 if (pt != NULL) { 1744 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1745 mtx_unlock(&moea_table_mutex); 1746 } 1747 } 1748 rw_wunlock(&pvh_global_lock); 1749 PMAP_UNLOCK(pm); 1750 } 1751 1752 /* 1753 * Map a list of wired pages into kernel virtual address space. This is 1754 * intended for temporary mappings which do not need page modification or 1755 * references recorded. Existing mappings in the region are overwritten. 1756 */ 1757 void 1758 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1759 { 1760 vm_offset_t va; 1761 1762 va = sva; 1763 while (count-- > 0) { 1764 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1765 va += PAGE_SIZE; 1766 m++; 1767 } 1768 } 1769 1770 /* 1771 * Remove page mappings from kernel virtual address space. Intended for 1772 * temporary mappings entered by moea_qenter. 1773 */ 1774 void 1775 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1776 { 1777 vm_offset_t va; 1778 1779 va = sva; 1780 while (count-- > 0) { 1781 moea_kremove(mmu, va); 1782 va += PAGE_SIZE; 1783 } 1784 } 1785 1786 void 1787 moea_release(mmu_t mmu, pmap_t pmap) 1788 { 1789 int idx, mask; 1790 1791 /* 1792 * Free segment register's VSID 1793 */ 1794 if (pmap->pm_sr[0] == 0) 1795 panic("moea_release"); 1796 1797 mtx_lock(&moea_vsid_mutex); 1798 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1799 mask = 1 << (idx % VSID_NBPW); 1800 idx /= VSID_NBPW; 1801 moea_vsid_bitmap[idx] &= ~mask; 1802 mtx_unlock(&moea_vsid_mutex); 1803 } 1804 1805 /* 1806 * Remove the given range of addresses from the specified map. 1807 */ 1808 void 1809 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1810 { 1811 struct pvo_entry *pvo, *tpvo, key; 1812 1813 rw_wlock(&pvh_global_lock); 1814 PMAP_LOCK(pm); 1815 key.pvo_vaddr = sva; 1816 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1817 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1818 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1819 moea_pvo_remove(pvo, -1); 1820 } 1821 PMAP_UNLOCK(pm); 1822 rw_wunlock(&pvh_global_lock); 1823 } 1824 1825 /* 1826 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1827 * will reflect changes in pte's back to the vm_page. 1828 */ 1829 void 1830 moea_remove_all(mmu_t mmu, vm_page_t m) 1831 { 1832 struct pvo_head *pvo_head; 1833 struct pvo_entry *pvo, *next_pvo; 1834 pmap_t pmap; 1835 1836 rw_wlock(&pvh_global_lock); 1837 pvo_head = vm_page_to_pvoh(m); 1838 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1839 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1840 1841 pmap = pvo->pvo_pmap; 1842 PMAP_LOCK(pmap); 1843 moea_pvo_remove(pvo, -1); 1844 PMAP_UNLOCK(pmap); 1845 } 1846 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1847 moea_attr_clear(m, PTE_CHG); 1848 vm_page_dirty(m); 1849 } 1850 vm_page_aflag_clear(m, PGA_WRITEABLE); 1851 rw_wunlock(&pvh_global_lock); 1852 } 1853 1854 /* 1855 * Allocate a physical page of memory directly from the phys_avail map. 1856 * Can only be called from moea_bootstrap before avail start and end are 1857 * calculated. 1858 */ 1859 static vm_offset_t 1860 moea_bootstrap_alloc(vm_size_t size, u_int align) 1861 { 1862 vm_offset_t s, e; 1863 int i, j; 1864 1865 size = round_page(size); 1866 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1867 if (align != 0) 1868 s = roundup2(phys_avail[i], align); 1869 else 1870 s = phys_avail[i]; 1871 e = s + size; 1872 1873 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1874 continue; 1875 1876 if (s == phys_avail[i]) { 1877 phys_avail[i] += size; 1878 } else if (e == phys_avail[i + 1]) { 1879 phys_avail[i + 1] -= size; 1880 } else { 1881 for (j = phys_avail_count * 2; j > i; j -= 2) { 1882 phys_avail[j] = phys_avail[j - 2]; 1883 phys_avail[j + 1] = phys_avail[j - 1]; 1884 } 1885 1886 phys_avail[i + 3] = phys_avail[i + 1]; 1887 phys_avail[i + 1] = s; 1888 phys_avail[i + 2] = e; 1889 phys_avail_count++; 1890 } 1891 1892 return (s); 1893 } 1894 panic("moea_bootstrap_alloc: could not allocate memory"); 1895 } 1896 1897 static void 1898 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1899 { 1900 __syncicache((void *)pa, len); 1901 } 1902 1903 static int 1904 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1905 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1906 { 1907 struct pvo_entry *pvo; 1908 u_int sr; 1909 int first; 1910 u_int ptegidx; 1911 int i; 1912 int bootstrap; 1913 1914 moea_pvo_enter_calls++; 1915 first = 0; 1916 bootstrap = 0; 1917 1918 /* 1919 * Compute the PTE Group index. 1920 */ 1921 va &= ~ADDR_POFF; 1922 sr = va_to_sr(pm->pm_sr, va); 1923 ptegidx = va_to_pteg(sr, va); 1924 1925 /* 1926 * Remove any existing mapping for this page. Reuse the pvo entry if 1927 * there is a mapping. 1928 */ 1929 mtx_lock(&moea_table_mutex); 1930 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1931 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1932 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1933 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1934 (pte_lo & PTE_PP)) { 1935 /* 1936 * The PTE is not changing. Instead, this may 1937 * be a request to change the mapping's wired 1938 * attribute. 1939 */ 1940 mtx_unlock(&moea_table_mutex); 1941 if ((flags & PVO_WIRED) != 0 && 1942 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1943 pvo->pvo_vaddr |= PVO_WIRED; 1944 pm->pm_stats.wired_count++; 1945 } else if ((flags & PVO_WIRED) == 0 && 1946 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1947 pvo->pvo_vaddr &= ~PVO_WIRED; 1948 pm->pm_stats.wired_count--; 1949 } 1950 return (0); 1951 } 1952 moea_pvo_remove(pvo, -1); 1953 break; 1954 } 1955 } 1956 1957 /* 1958 * If we aren't overwriting a mapping, try to allocate. 1959 */ 1960 if (moea_initialized) { 1961 pvo = uma_zalloc(zone, M_NOWAIT); 1962 } else { 1963 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1964 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1965 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1966 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1967 } 1968 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1969 moea_bpvo_pool_index++; 1970 bootstrap = 1; 1971 } 1972 1973 if (pvo == NULL) { 1974 mtx_unlock(&moea_table_mutex); 1975 return (ENOMEM); 1976 } 1977 1978 moea_pvo_entries++; 1979 pvo->pvo_vaddr = va; 1980 pvo->pvo_pmap = pm; 1981 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1982 pvo->pvo_vaddr &= ~ADDR_POFF; 1983 if (flags & PVO_WIRED) 1984 pvo->pvo_vaddr |= PVO_WIRED; 1985 if (pvo_head != &moea_pvo_kunmanaged) 1986 pvo->pvo_vaddr |= PVO_MANAGED; 1987 if (bootstrap) 1988 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1989 1990 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1991 1992 /* 1993 * Add to pmap list 1994 */ 1995 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1996 1997 /* 1998 * Remember if the list was empty and therefore will be the first 1999 * item. 2000 */ 2001 if (LIST_FIRST(pvo_head) == NULL) 2002 first = 1; 2003 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2004 2005 if (pvo->pvo_vaddr & PVO_WIRED) 2006 pm->pm_stats.wired_count++; 2007 pm->pm_stats.resident_count++; 2008 2009 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2010 KASSERT(i < 8, ("Invalid PTE index")); 2011 if (i >= 0) { 2012 PVO_PTEGIDX_SET(pvo, i); 2013 } else { 2014 panic("moea_pvo_enter: overflow"); 2015 moea_pte_overflow++; 2016 } 2017 mtx_unlock(&moea_table_mutex); 2018 2019 return (first ? ENOENT : 0); 2020 } 2021 2022 static void 2023 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2024 { 2025 struct pte *pt; 2026 2027 /* 2028 * If there is an active pte entry, we need to deactivate it (and 2029 * save the ref & cfg bits). 2030 */ 2031 pt = moea_pvo_to_pte(pvo, pteidx); 2032 if (pt != NULL) { 2033 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2034 mtx_unlock(&moea_table_mutex); 2035 PVO_PTEGIDX_CLR(pvo); 2036 } else { 2037 moea_pte_overflow--; 2038 } 2039 2040 /* 2041 * Update our statistics. 2042 */ 2043 pvo->pvo_pmap->pm_stats.resident_count--; 2044 if (pvo->pvo_vaddr & PVO_WIRED) 2045 pvo->pvo_pmap->pm_stats.wired_count--; 2046 2047 /* 2048 * Save the REF/CHG bits into their cache if the page is managed. 2049 */ 2050 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2051 struct vm_page *pg; 2052 2053 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2054 if (pg != NULL) { 2055 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2056 (PTE_REF | PTE_CHG)); 2057 } 2058 } 2059 2060 /* 2061 * Remove this PVO from the PV and pmap lists. 2062 */ 2063 LIST_REMOVE(pvo, pvo_vlink); 2064 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2065 2066 /* 2067 * Remove this from the overflow list and return it to the pool 2068 * if we aren't going to reuse it. 2069 */ 2070 LIST_REMOVE(pvo, pvo_olink); 2071 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2072 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2073 moea_upvo_zone, pvo); 2074 moea_pvo_entries--; 2075 moea_pvo_remove_calls++; 2076 } 2077 2078 static __inline int 2079 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2080 { 2081 int pteidx; 2082 2083 /* 2084 * We can find the actual pte entry without searching by grabbing 2085 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2086 * noticing the HID bit. 2087 */ 2088 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2089 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2090 pteidx ^= moea_pteg_mask * 8; 2091 2092 return (pteidx); 2093 } 2094 2095 static struct pvo_entry * 2096 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2097 { 2098 struct pvo_entry *pvo; 2099 int ptegidx; 2100 u_int sr; 2101 2102 va &= ~ADDR_POFF; 2103 sr = va_to_sr(pm->pm_sr, va); 2104 ptegidx = va_to_pteg(sr, va); 2105 2106 mtx_lock(&moea_table_mutex); 2107 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2108 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2109 if (pteidx_p) 2110 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2111 break; 2112 } 2113 } 2114 mtx_unlock(&moea_table_mutex); 2115 2116 return (pvo); 2117 } 2118 2119 static struct pte * 2120 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2121 { 2122 struct pte *pt; 2123 2124 /* 2125 * If we haven't been supplied the ptegidx, calculate it. 2126 */ 2127 if (pteidx == -1) { 2128 int ptegidx; 2129 u_int sr; 2130 2131 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2132 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2133 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2134 } 2135 2136 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2137 mtx_lock(&moea_table_mutex); 2138 2139 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2140 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2141 "valid pte index", pvo); 2142 } 2143 2144 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2145 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2146 "pvo but no valid pte", pvo); 2147 } 2148 2149 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2150 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2151 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2152 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2153 } 2154 2155 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2156 != 0) { 2157 panic("moea_pvo_to_pte: pvo %p pte does not match " 2158 "pte %p in moea_pteg_table", pvo, pt); 2159 } 2160 2161 mtx_assert(&moea_table_mutex, MA_OWNED); 2162 return (pt); 2163 } 2164 2165 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2166 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2167 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2168 } 2169 2170 mtx_unlock(&moea_table_mutex); 2171 return (NULL); 2172 } 2173 2174 /* 2175 * XXX: THIS STUFF SHOULD BE IN pte.c? 2176 */ 2177 int 2178 moea_pte_spill(vm_offset_t addr) 2179 { 2180 struct pvo_entry *source_pvo, *victim_pvo; 2181 struct pvo_entry *pvo; 2182 int ptegidx, i, j; 2183 u_int sr; 2184 struct pteg *pteg; 2185 struct pte *pt; 2186 2187 moea_pte_spills++; 2188 2189 sr = mfsrin(addr); 2190 ptegidx = va_to_pteg(sr, addr); 2191 2192 /* 2193 * Have to substitute some entry. Use the primary hash for this. 2194 * Use low bits of timebase as random generator. 2195 */ 2196 pteg = &moea_pteg_table[ptegidx]; 2197 mtx_lock(&moea_table_mutex); 2198 __asm __volatile("mftb %0" : "=r"(i)); 2199 i &= 7; 2200 pt = &pteg->pt[i]; 2201 2202 source_pvo = NULL; 2203 victim_pvo = NULL; 2204 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2205 /* 2206 * We need to find a pvo entry for this address. 2207 */ 2208 if (source_pvo == NULL && 2209 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2210 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2211 /* 2212 * Now found an entry to be spilled into the pteg. 2213 * The PTE is now valid, so we know it's active. 2214 */ 2215 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2216 2217 if (j >= 0) { 2218 PVO_PTEGIDX_SET(pvo, j); 2219 moea_pte_overflow--; 2220 mtx_unlock(&moea_table_mutex); 2221 return (1); 2222 } 2223 2224 source_pvo = pvo; 2225 2226 if (victim_pvo != NULL) 2227 break; 2228 } 2229 2230 /* 2231 * We also need the pvo entry of the victim we are replacing 2232 * so save the R & C bits of the PTE. 2233 */ 2234 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2235 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2236 victim_pvo = pvo; 2237 if (source_pvo != NULL) 2238 break; 2239 } 2240 } 2241 2242 if (source_pvo == NULL) { 2243 mtx_unlock(&moea_table_mutex); 2244 return (0); 2245 } 2246 2247 if (victim_pvo == NULL) { 2248 if ((pt->pte_hi & PTE_HID) == 0) 2249 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2250 "entry", pt); 2251 2252 /* 2253 * If this is a secondary PTE, we need to search it's primary 2254 * pvo bucket for the matching PVO. 2255 */ 2256 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2257 pvo_olink) { 2258 /* 2259 * We also need the pvo entry of the victim we are 2260 * replacing so save the R & C bits of the PTE. 2261 */ 2262 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2263 victim_pvo = pvo; 2264 break; 2265 } 2266 } 2267 2268 if (victim_pvo == NULL) 2269 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2270 "entry", pt); 2271 } 2272 2273 /* 2274 * We are invalidating the TLB entry for the EA we are replacing even 2275 * though it's valid. If we don't, we lose any ref/chg bit changes 2276 * contained in the TLB entry. 2277 */ 2278 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2279 2280 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2281 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2282 2283 PVO_PTEGIDX_CLR(victim_pvo); 2284 PVO_PTEGIDX_SET(source_pvo, i); 2285 moea_pte_replacements++; 2286 2287 mtx_unlock(&moea_table_mutex); 2288 return (1); 2289 } 2290 2291 static __inline struct pvo_entry * 2292 moea_pte_spillable_ident(u_int ptegidx) 2293 { 2294 struct pte *pt; 2295 struct pvo_entry *pvo_walk, *pvo = NULL; 2296 2297 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2298 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2299 continue; 2300 2301 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2302 continue; 2303 2304 pt = moea_pvo_to_pte(pvo_walk, -1); 2305 2306 if (pt == NULL) 2307 continue; 2308 2309 pvo = pvo_walk; 2310 2311 mtx_unlock(&moea_table_mutex); 2312 if (!(pt->pte_lo & PTE_REF)) 2313 return (pvo_walk); 2314 } 2315 2316 return (pvo); 2317 } 2318 2319 static int 2320 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2321 { 2322 struct pte *pt; 2323 struct pvo_entry *victim_pvo; 2324 int i; 2325 int victim_idx; 2326 u_int pteg_bkpidx = ptegidx; 2327 2328 mtx_assert(&moea_table_mutex, MA_OWNED); 2329 2330 /* 2331 * First try primary hash. 2332 */ 2333 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2334 if ((pt->pte_hi & PTE_VALID) == 0) { 2335 pvo_pt->pte_hi &= ~PTE_HID; 2336 moea_pte_set(pt, pvo_pt); 2337 return (i); 2338 } 2339 } 2340 2341 /* 2342 * Now try secondary hash. 2343 */ 2344 ptegidx ^= moea_pteg_mask; 2345 2346 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2347 if ((pt->pte_hi & PTE_VALID) == 0) { 2348 pvo_pt->pte_hi |= PTE_HID; 2349 moea_pte_set(pt, pvo_pt); 2350 return (i); 2351 } 2352 } 2353 2354 /* Try again, but this time try to force a PTE out. */ 2355 ptegidx = pteg_bkpidx; 2356 2357 victim_pvo = moea_pte_spillable_ident(ptegidx); 2358 if (victim_pvo == NULL) { 2359 ptegidx ^= moea_pteg_mask; 2360 victim_pvo = moea_pte_spillable_ident(ptegidx); 2361 } 2362 2363 if (victim_pvo == NULL) { 2364 panic("moea_pte_insert: overflow"); 2365 return (-1); 2366 } 2367 2368 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2369 2370 if (pteg_bkpidx == ptegidx) 2371 pvo_pt->pte_hi &= ~PTE_HID; 2372 else 2373 pvo_pt->pte_hi |= PTE_HID; 2374 2375 /* 2376 * Synchronize the sacrifice PTE with its PVO, then mark both 2377 * invalid. The PVO will be reused when/if the VM system comes 2378 * here after a fault. 2379 */ 2380 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2381 2382 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2383 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2384 2385 /* 2386 * Set the new PTE. 2387 */ 2388 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2389 PVO_PTEGIDX_CLR(victim_pvo); 2390 moea_pte_overflow++; 2391 moea_pte_set(pt, pvo_pt); 2392 2393 return (victim_idx & 7); 2394 } 2395 2396 static boolean_t 2397 moea_query_bit(vm_page_t m, int ptebit) 2398 { 2399 struct pvo_entry *pvo; 2400 struct pte *pt; 2401 2402 rw_assert(&pvh_global_lock, RA_WLOCKED); 2403 if (moea_attr_fetch(m) & ptebit) 2404 return (TRUE); 2405 2406 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2407 2408 /* 2409 * See if we saved the bit off. If so, cache it and return 2410 * success. 2411 */ 2412 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2413 moea_attr_save(m, ptebit); 2414 return (TRUE); 2415 } 2416 } 2417 2418 /* 2419 * No luck, now go through the hard part of looking at the PTEs 2420 * themselves. Sync so that any pending REF/CHG bits are flushed to 2421 * the PTEs. 2422 */ 2423 powerpc_sync(); 2424 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2425 2426 /* 2427 * See if this pvo has a valid PTE. if so, fetch the 2428 * REF/CHG bits from the valid PTE. If the appropriate 2429 * ptebit is set, cache it and return success. 2430 */ 2431 pt = moea_pvo_to_pte(pvo, -1); 2432 if (pt != NULL) { 2433 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2434 mtx_unlock(&moea_table_mutex); 2435 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2436 moea_attr_save(m, ptebit); 2437 return (TRUE); 2438 } 2439 } 2440 } 2441 2442 return (FALSE); 2443 } 2444 2445 static u_int 2446 moea_clear_bit(vm_page_t m, int ptebit) 2447 { 2448 u_int count; 2449 struct pvo_entry *pvo; 2450 struct pte *pt; 2451 2452 rw_assert(&pvh_global_lock, RA_WLOCKED); 2453 2454 /* 2455 * Clear the cached value. 2456 */ 2457 moea_attr_clear(m, ptebit); 2458 2459 /* 2460 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2461 * we can reset the right ones). note that since the pvo entries and 2462 * list heads are accessed via BAT0 and are never placed in the page 2463 * table, we don't have to worry about further accesses setting the 2464 * REF/CHG bits. 2465 */ 2466 powerpc_sync(); 2467 2468 /* 2469 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2470 * valid pte clear the ptebit from the valid pte. 2471 */ 2472 count = 0; 2473 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2474 pt = moea_pvo_to_pte(pvo, -1); 2475 if (pt != NULL) { 2476 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2477 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2478 count++; 2479 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2480 } 2481 mtx_unlock(&moea_table_mutex); 2482 } 2483 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2484 } 2485 2486 return (count); 2487 } 2488 2489 /* 2490 * Return true if the physical range is encompassed by the battable[idx] 2491 */ 2492 static int 2493 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2494 { 2495 u_int prot; 2496 u_int32_t start; 2497 u_int32_t end; 2498 u_int32_t bat_ble; 2499 2500 /* 2501 * Return immediately if not a valid mapping 2502 */ 2503 if (!(battable[idx].batu & BAT_Vs)) 2504 return (EINVAL); 2505 2506 /* 2507 * The BAT entry must be cache-inhibited, guarded, and r/w 2508 * so it can function as an i/o page 2509 */ 2510 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2511 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2512 return (EPERM); 2513 2514 /* 2515 * The address should be within the BAT range. Assume that the 2516 * start address in the BAT has the correct alignment (thus 2517 * not requiring masking) 2518 */ 2519 start = battable[idx].batl & BAT_PBS; 2520 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2521 end = start | (bat_ble << 15) | 0x7fff; 2522 2523 if ((pa < start) || ((pa + size) > end)) 2524 return (ERANGE); 2525 2526 return (0); 2527 } 2528 2529 boolean_t 2530 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2531 { 2532 int i; 2533 2534 /* 2535 * This currently does not work for entries that 2536 * overlap 256M BAT segments. 2537 */ 2538 2539 for(i = 0; i < 16; i++) 2540 if (moea_bat_mapped(i, pa, size) == 0) 2541 return (0); 2542 2543 return (EFAULT); 2544 } 2545 2546 /* 2547 * Map a set of physical memory pages into the kernel virtual 2548 * address space. Return a pointer to where it is mapped. This 2549 * routine is intended to be used for mapping device memory, 2550 * NOT real memory. 2551 */ 2552 void * 2553 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2554 { 2555 2556 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2557 } 2558 2559 void * 2560 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2561 { 2562 vm_offset_t va, tmpva, ppa, offset; 2563 int i; 2564 2565 ppa = trunc_page(pa); 2566 offset = pa & PAGE_MASK; 2567 size = roundup(offset + size, PAGE_SIZE); 2568 2569 /* 2570 * If the physical address lies within a valid BAT table entry, 2571 * return the 1:1 mapping. This currently doesn't work 2572 * for regions that overlap 256M BAT segments. 2573 */ 2574 for (i = 0; i < 16; i++) { 2575 if (moea_bat_mapped(i, pa, size) == 0) 2576 return ((void *) pa); 2577 } 2578 2579 va = kva_alloc(size); 2580 if (!va) 2581 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2582 2583 for (tmpva = va; size > 0;) { 2584 moea_kenter_attr(mmu, tmpva, ppa, ma); 2585 tlbie(tmpva); 2586 size -= PAGE_SIZE; 2587 tmpva += PAGE_SIZE; 2588 ppa += PAGE_SIZE; 2589 } 2590 2591 return ((void *)(va + offset)); 2592 } 2593 2594 void 2595 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2596 { 2597 vm_offset_t base, offset; 2598 2599 /* 2600 * If this is outside kernel virtual space, then it's a 2601 * battable entry and doesn't require unmapping 2602 */ 2603 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2604 base = trunc_page(va); 2605 offset = va & PAGE_MASK; 2606 size = roundup(offset + size, PAGE_SIZE); 2607 kva_free(base, size); 2608 } 2609 } 2610 2611 static void 2612 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2613 { 2614 struct pvo_entry *pvo; 2615 vm_offset_t lim; 2616 vm_paddr_t pa; 2617 vm_size_t len; 2618 2619 PMAP_LOCK(pm); 2620 while (sz > 0) { 2621 lim = round_page(va); 2622 len = MIN(lim - va, sz); 2623 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2624 if (pvo != NULL) { 2625 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2626 (va & ADDR_POFF); 2627 moea_syncicache(pa, len); 2628 } 2629 va += len; 2630 sz -= len; 2631 } 2632 PMAP_UNLOCK(pm); 2633 } 2634 2635 void 2636 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2637 { 2638 2639 *va = (void *)pa; 2640 } 2641 2642 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2643 2644 void 2645 moea_scan_init(mmu_t mmu) 2646 { 2647 struct pvo_entry *pvo; 2648 vm_offset_t va; 2649 int i; 2650 2651 if (!do_minidump) { 2652 /* Initialize phys. segments for dumpsys(). */ 2653 memset(&dump_map, 0, sizeof(dump_map)); 2654 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2655 for (i = 0; i < pregions_sz; i++) { 2656 dump_map[i].pa_start = pregions[i].mr_start; 2657 dump_map[i].pa_size = pregions[i].mr_size; 2658 } 2659 return; 2660 } 2661 2662 /* Virtual segments for minidumps: */ 2663 memset(&dump_map, 0, sizeof(dump_map)); 2664 2665 /* 1st: kernel .data and .bss. */ 2666 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2667 dump_map[0].pa_size = 2668 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2669 2670 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2671 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2672 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2673 2674 /* 3rd: kernel VM. */ 2675 va = dump_map[1].pa_start + dump_map[1].pa_size; 2676 /* Find start of next chunk (from va). */ 2677 while (va < virtual_end) { 2678 /* Don't dump the buffer cache. */ 2679 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2680 va = kmi.buffer_eva; 2681 continue; 2682 } 2683 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2684 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2685 break; 2686 va += PAGE_SIZE; 2687 } 2688 if (va < virtual_end) { 2689 dump_map[2].pa_start = va; 2690 va += PAGE_SIZE; 2691 /* Find last page in chunk. */ 2692 while (va < virtual_end) { 2693 /* Don't run into the buffer cache. */ 2694 if (va == kmi.buffer_sva) 2695 break; 2696 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2697 NULL); 2698 if (pvo == NULL || 2699 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2700 break; 2701 va += PAGE_SIZE; 2702 } 2703 dump_map[2].pa_size = va - dump_map[2].pa_start; 2704 } 2705 } 2706