1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/queue.h> 122 #include <sys/cpuset.h> 123 #include <sys/ktr.h> 124 #include <sys/lock.h> 125 #include <sys/msgbuf.h> 126 #include <sys/mutex.h> 127 #include <sys/proc.h> 128 #include <sys/sched.h> 129 #include <sys/sysctl.h> 130 #include <sys/systm.h> 131 #include <sys/vmmeter.h> 132 133 #include <dev/ofw/openfirm.h> 134 135 #include <vm/vm.h> 136 #include <vm/vm_param.h> 137 #include <vm/vm_kern.h> 138 #include <vm/vm_page.h> 139 #include <vm/vm_map.h> 140 #include <vm/vm_object.h> 141 #include <vm/vm_extern.h> 142 #include <vm/vm_pageout.h> 143 #include <vm/vm_pager.h> 144 #include <vm/uma.h> 145 146 #include <machine/cpu.h> 147 #include <machine/platform.h> 148 #include <machine/bat.h> 149 #include <machine/frame.h> 150 #include <machine/md_var.h> 151 #include <machine/psl.h> 152 #include <machine/pte.h> 153 #include <machine/smp.h> 154 #include <machine/sr.h> 155 #include <machine/mmuvar.h> 156 #include <machine/trap_aim.h> 157 158 #include "mmu_if.h" 159 160 #define MOEA_DEBUG 161 162 #define TODO panic("%s: not implemented", __func__); 163 164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 165 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 167 168 struct ofw_map { 169 vm_offset_t om_va; 170 vm_size_t om_len; 171 vm_offset_t om_pa; 172 u_int om_mode; 173 }; 174 175 /* 176 * Map of physical memory regions. 177 */ 178 static struct mem_region *regions; 179 static struct mem_region *pregions; 180 static u_int phys_avail_count; 181 static int regions_sz, pregions_sz; 182 static struct ofw_map *translations; 183 184 /* 185 * Lock for the pteg and pvo tables. 186 */ 187 struct mtx moea_table_mutex; 188 struct mtx moea_vsid_mutex; 189 190 /* tlbie instruction synchronization */ 191 static struct mtx tlbie_mtx; 192 193 /* 194 * PTEG data. 195 */ 196 static struct pteg *moea_pteg_table; 197 u_int moea_pteg_count; 198 u_int moea_pteg_mask; 199 200 /* 201 * PVO data. 202 */ 203 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 204 struct pvo_head moea_pvo_kunmanaged = 205 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 206 207 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 208 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 209 210 #define BPVO_POOL_SIZE 32768 211 static struct pvo_entry *moea_bpvo_pool; 212 static int moea_bpvo_pool_index = 0; 213 214 #define VSID_NBPW (sizeof(u_int32_t) * 8) 215 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 216 217 static boolean_t moea_initialized = FALSE; 218 219 /* 220 * Statistics. 221 */ 222 u_int moea_pte_valid = 0; 223 u_int moea_pte_overflow = 0; 224 u_int moea_pte_replacements = 0; 225 u_int moea_pvo_entries = 0; 226 u_int moea_pvo_enter_calls = 0; 227 u_int moea_pvo_remove_calls = 0; 228 u_int moea_pte_spills = 0; 229 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 230 0, ""); 231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 232 &moea_pte_overflow, 0, ""); 233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 234 &moea_pte_replacements, 0, ""); 235 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 236 0, ""); 237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 238 &moea_pvo_enter_calls, 0, ""); 239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 240 &moea_pvo_remove_calls, 0, ""); 241 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 242 &moea_pte_spills, 0, ""); 243 244 /* 245 * Allocate physical memory for use in moea_bootstrap. 246 */ 247 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 248 249 /* 250 * PTE calls. 251 */ 252 static int moea_pte_insert(u_int, struct pte *); 253 254 /* 255 * PVO calls. 256 */ 257 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 258 vm_offset_t, vm_offset_t, u_int, int); 259 static void moea_pvo_remove(struct pvo_entry *, int); 260 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 261 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 262 263 /* 264 * Utility routines. 265 */ 266 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 267 vm_prot_t, boolean_t); 268 static void moea_syncicache(vm_offset_t, vm_size_t); 269 static boolean_t moea_query_bit(vm_page_t, int); 270 static u_int moea_clear_bit(vm_page_t, int); 271 static void moea_kremove(mmu_t, vm_offset_t); 272 int moea_pte_spill(vm_offset_t); 273 274 /* 275 * Kernel MMU interface 276 */ 277 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 278 void moea_clear_modify(mmu_t, vm_page_t); 279 void moea_clear_reference(mmu_t, vm_page_t); 280 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 281 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 287 void moea_init(mmu_t); 288 boolean_t moea_is_modified(mmu_t, vm_page_t); 289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 boolean_t moea_is_referenced(mmu_t, vm_page_t); 291 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 int moea_page_wired_mappings(mmu_t, vm_page_t); 295 void moea_pinit(mmu_t, pmap_t); 296 void moea_pinit0(mmu_t, pmap_t); 297 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 298 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 299 void moea_qremove(mmu_t, vm_offset_t, int); 300 void moea_release(mmu_t, pmap_t); 301 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 302 void moea_remove_all(mmu_t, vm_page_t); 303 void moea_remove_write(mmu_t, vm_page_t); 304 void moea_zero_page(mmu_t, vm_page_t); 305 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 306 void moea_zero_page_idle(mmu_t, vm_page_t); 307 void moea_activate(mmu_t, struct thread *); 308 void moea_deactivate(mmu_t, struct thread *); 309 void moea_cpu_bootstrap(mmu_t, int); 310 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 311 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 312 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 313 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 314 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 315 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 316 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 317 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 318 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 319 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 320 321 static mmu_method_t moea_methods[] = { 322 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 323 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 324 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 325 MMUMETHOD(mmu_copy_page, moea_copy_page), 326 MMUMETHOD(mmu_enter, moea_enter), 327 MMUMETHOD(mmu_enter_object, moea_enter_object), 328 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 329 MMUMETHOD(mmu_extract, moea_extract), 330 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 331 MMUMETHOD(mmu_init, moea_init), 332 MMUMETHOD(mmu_is_modified, moea_is_modified), 333 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 334 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 335 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 336 MMUMETHOD(mmu_map, moea_map), 337 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 338 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 339 MMUMETHOD(mmu_pinit, moea_pinit), 340 MMUMETHOD(mmu_pinit0, moea_pinit0), 341 MMUMETHOD(mmu_protect, moea_protect), 342 MMUMETHOD(mmu_qenter, moea_qenter), 343 MMUMETHOD(mmu_qremove, moea_qremove), 344 MMUMETHOD(mmu_release, moea_release), 345 MMUMETHOD(mmu_remove, moea_remove), 346 MMUMETHOD(mmu_remove_all, moea_remove_all), 347 MMUMETHOD(mmu_remove_write, moea_remove_write), 348 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 349 MMUMETHOD(mmu_zero_page, moea_zero_page), 350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 351 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 352 MMUMETHOD(mmu_activate, moea_activate), 353 MMUMETHOD(mmu_deactivate, moea_deactivate), 354 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 355 356 /* Internal interfaces */ 357 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 358 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 359 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 360 MMUMETHOD(mmu_mapdev, moea_mapdev), 361 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 362 MMUMETHOD(mmu_kextract, moea_kextract), 363 MMUMETHOD(mmu_kenter, moea_kenter), 364 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 365 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 366 367 { 0, 0 } 368 }; 369 370 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 371 372 static __inline uint32_t 373 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 374 { 375 uint32_t pte_lo; 376 int i; 377 378 if (ma != VM_MEMATTR_DEFAULT) { 379 switch (ma) { 380 case VM_MEMATTR_UNCACHEABLE: 381 return (PTE_I | PTE_G); 382 case VM_MEMATTR_WRITE_COMBINING: 383 case VM_MEMATTR_WRITE_BACK: 384 case VM_MEMATTR_PREFETCHABLE: 385 return (PTE_I); 386 case VM_MEMATTR_WRITE_THROUGH: 387 return (PTE_W | PTE_M); 388 } 389 } 390 391 /* 392 * Assume the page is cache inhibited and access is guarded unless 393 * it's in our available memory array. 394 */ 395 pte_lo = PTE_I | PTE_G; 396 for (i = 0; i < pregions_sz; i++) { 397 if ((pa >= pregions[i].mr_start) && 398 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 399 pte_lo = PTE_M; 400 break; 401 } 402 } 403 404 return pte_lo; 405 } 406 407 static void 408 tlbie(vm_offset_t va) 409 { 410 411 mtx_lock_spin(&tlbie_mtx); 412 __asm __volatile("ptesync"); 413 __asm __volatile("tlbie %0" :: "r"(va)); 414 __asm __volatile("eieio; tlbsync; ptesync"); 415 mtx_unlock_spin(&tlbie_mtx); 416 } 417 418 static void 419 tlbia(void) 420 { 421 vm_offset_t va; 422 423 for (va = 0; va < 0x00040000; va += 0x00001000) { 424 __asm __volatile("tlbie %0" :: "r"(va)); 425 powerpc_sync(); 426 } 427 __asm __volatile("tlbsync"); 428 powerpc_sync(); 429 } 430 431 static __inline int 432 va_to_sr(u_int *sr, vm_offset_t va) 433 { 434 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 435 } 436 437 static __inline u_int 438 va_to_pteg(u_int sr, vm_offset_t addr) 439 { 440 u_int hash; 441 442 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 443 ADDR_PIDX_SHFT); 444 return (hash & moea_pteg_mask); 445 } 446 447 static __inline struct pvo_head * 448 vm_page_to_pvoh(vm_page_t m) 449 { 450 451 return (&m->md.mdpg_pvoh); 452 } 453 454 static __inline void 455 moea_attr_clear(vm_page_t m, int ptebit) 456 { 457 458 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 459 m->md.mdpg_attrs &= ~ptebit; 460 } 461 462 static __inline int 463 moea_attr_fetch(vm_page_t m) 464 { 465 466 return (m->md.mdpg_attrs); 467 } 468 469 static __inline void 470 moea_attr_save(vm_page_t m, int ptebit) 471 { 472 473 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 474 m->md.mdpg_attrs |= ptebit; 475 } 476 477 static __inline int 478 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 479 { 480 if (pt->pte_hi == pvo_pt->pte_hi) 481 return (1); 482 483 return (0); 484 } 485 486 static __inline int 487 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 488 { 489 return (pt->pte_hi & ~PTE_VALID) == 490 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 491 ((va >> ADDR_API_SHFT) & PTE_API) | which); 492 } 493 494 static __inline void 495 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 496 { 497 498 mtx_assert(&moea_table_mutex, MA_OWNED); 499 500 /* 501 * Construct a PTE. Default to IMB initially. Valid bit only gets 502 * set when the real pte is set in memory. 503 * 504 * Note: Don't set the valid bit for correct operation of tlb update. 505 */ 506 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 507 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 508 pt->pte_lo = pte_lo; 509 } 510 511 static __inline void 512 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 513 { 514 515 mtx_assert(&moea_table_mutex, MA_OWNED); 516 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 517 } 518 519 static __inline void 520 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 521 { 522 523 mtx_assert(&moea_table_mutex, MA_OWNED); 524 525 /* 526 * As shown in Section 7.6.3.2.3 527 */ 528 pt->pte_lo &= ~ptebit; 529 tlbie(va); 530 } 531 532 static __inline void 533 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 534 { 535 536 mtx_assert(&moea_table_mutex, MA_OWNED); 537 pvo_pt->pte_hi |= PTE_VALID; 538 539 /* 540 * Update the PTE as defined in section 7.6.3.1. 541 * Note that the REF/CHG bits are from pvo_pt and thus should havce 542 * been saved so this routine can restore them (if desired). 543 */ 544 pt->pte_lo = pvo_pt->pte_lo; 545 powerpc_sync(); 546 pt->pte_hi = pvo_pt->pte_hi; 547 powerpc_sync(); 548 moea_pte_valid++; 549 } 550 551 static __inline void 552 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 553 { 554 555 mtx_assert(&moea_table_mutex, MA_OWNED); 556 pvo_pt->pte_hi &= ~PTE_VALID; 557 558 /* 559 * Force the reg & chg bits back into the PTEs. 560 */ 561 powerpc_sync(); 562 563 /* 564 * Invalidate the pte. 565 */ 566 pt->pte_hi &= ~PTE_VALID; 567 568 tlbie(va); 569 570 /* 571 * Save the reg & chg bits. 572 */ 573 moea_pte_synch(pt, pvo_pt); 574 moea_pte_valid--; 575 } 576 577 static __inline void 578 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 579 { 580 581 /* 582 * Invalidate the PTE 583 */ 584 moea_pte_unset(pt, pvo_pt, va); 585 moea_pte_set(pt, pvo_pt); 586 } 587 588 /* 589 * Quick sort callout for comparing memory regions. 590 */ 591 static int om_cmp(const void *a, const void *b); 592 593 static int 594 om_cmp(const void *a, const void *b) 595 { 596 const struct ofw_map *mapa; 597 const struct ofw_map *mapb; 598 599 mapa = a; 600 mapb = b; 601 if (mapa->om_pa < mapb->om_pa) 602 return (-1); 603 else if (mapa->om_pa > mapb->om_pa) 604 return (1); 605 else 606 return (0); 607 } 608 609 void 610 moea_cpu_bootstrap(mmu_t mmup, int ap) 611 { 612 u_int sdr; 613 int i; 614 615 if (ap) { 616 powerpc_sync(); 617 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 618 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 619 isync(); 620 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 621 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 622 isync(); 623 } 624 625 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 626 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 627 isync(); 628 629 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 630 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 631 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 632 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 633 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 634 isync(); 635 636 for (i = 0; i < 16; i++) 637 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 638 powerpc_sync(); 639 640 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 641 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 642 isync(); 643 644 tlbia(); 645 } 646 647 void 648 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 649 { 650 ihandle_t mmui; 651 phandle_t chosen, mmu; 652 int sz; 653 int i, j; 654 vm_size_t size, physsz, hwphyssz; 655 vm_offset_t pa, va, off; 656 void *dpcpu; 657 register_t msr; 658 659 /* 660 * Set up BAT0 to map the lowest 256 MB area 661 */ 662 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 663 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 664 665 /* 666 * Map PCI memory space. 667 */ 668 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 669 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 670 671 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 672 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 673 674 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 675 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 676 677 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 678 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 679 680 /* 681 * Map obio devices. 682 */ 683 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 684 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 685 686 /* 687 * Use an IBAT and a DBAT to map the bottom segment of memory 688 * where we are. Turn off instruction relocation temporarily 689 * to prevent faults while reprogramming the IBAT. 690 */ 691 msr = mfmsr(); 692 mtmsr(msr & ~PSL_IR); 693 __asm (".balign 32; \n" 694 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 695 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 696 :: "r"(battable[0].batu), "r"(battable[0].batl)); 697 mtmsr(msr); 698 699 /* map pci space */ 700 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 701 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 702 isync(); 703 704 /* set global direct map flag */ 705 hw_direct_map = 1; 706 707 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 708 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 709 710 for (i = 0; i < pregions_sz; i++) { 711 vm_offset_t pa; 712 vm_offset_t end; 713 714 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 715 pregions[i].mr_start, 716 pregions[i].mr_start + pregions[i].mr_size, 717 pregions[i].mr_size); 718 /* 719 * Install entries into the BAT table to allow all 720 * of physmem to be convered by on-demand BAT entries. 721 * The loop will sometimes set the same battable element 722 * twice, but that's fine since they won't be used for 723 * a while yet. 724 */ 725 pa = pregions[i].mr_start & 0xf0000000; 726 end = pregions[i].mr_start + pregions[i].mr_size; 727 do { 728 u_int n = pa >> ADDR_SR_SHFT; 729 730 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 731 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 732 pa += SEGMENT_LENGTH; 733 } while (pa < end); 734 } 735 736 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 737 panic("moea_bootstrap: phys_avail too small"); 738 739 phys_avail_count = 0; 740 physsz = 0; 741 hwphyssz = 0; 742 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 743 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 744 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 745 regions[i].mr_start + regions[i].mr_size, 746 regions[i].mr_size); 747 if (hwphyssz != 0 && 748 (physsz + regions[i].mr_size) >= hwphyssz) { 749 if (physsz < hwphyssz) { 750 phys_avail[j] = regions[i].mr_start; 751 phys_avail[j + 1] = regions[i].mr_start + 752 hwphyssz - physsz; 753 physsz = hwphyssz; 754 phys_avail_count++; 755 } 756 break; 757 } 758 phys_avail[j] = regions[i].mr_start; 759 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 760 phys_avail_count++; 761 physsz += regions[i].mr_size; 762 } 763 764 /* Check for overlap with the kernel and exception vectors */ 765 for (j = 0; j < 2*phys_avail_count; j+=2) { 766 if (phys_avail[j] < EXC_LAST) 767 phys_avail[j] += EXC_LAST; 768 769 if (kernelstart >= phys_avail[j] && 770 kernelstart < phys_avail[j+1]) { 771 if (kernelend < phys_avail[j+1]) { 772 phys_avail[2*phys_avail_count] = 773 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 774 phys_avail[2*phys_avail_count + 1] = 775 phys_avail[j+1]; 776 phys_avail_count++; 777 } 778 779 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 780 } 781 782 if (kernelend >= phys_avail[j] && 783 kernelend < phys_avail[j+1]) { 784 if (kernelstart > phys_avail[j]) { 785 phys_avail[2*phys_avail_count] = phys_avail[j]; 786 phys_avail[2*phys_avail_count + 1] = 787 kernelstart & ~PAGE_MASK; 788 phys_avail_count++; 789 } 790 791 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 } 793 } 794 795 physmem = btoc(physsz); 796 797 /* 798 * Allocate PTEG table. 799 */ 800 #ifdef PTEGCOUNT 801 moea_pteg_count = PTEGCOUNT; 802 #else 803 moea_pteg_count = 0x1000; 804 805 while (moea_pteg_count < physmem) 806 moea_pteg_count <<= 1; 807 808 moea_pteg_count >>= 1; 809 #endif /* PTEGCOUNT */ 810 811 size = moea_pteg_count * sizeof(struct pteg); 812 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 813 size); 814 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 815 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 816 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 817 moea_pteg_mask = moea_pteg_count - 1; 818 819 /* 820 * Allocate pv/overflow lists. 821 */ 822 size = sizeof(struct pvo_head) * moea_pteg_count; 823 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 824 PAGE_SIZE); 825 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 826 for (i = 0; i < moea_pteg_count; i++) 827 LIST_INIT(&moea_pvo_table[i]); 828 829 /* 830 * Initialize the lock that synchronizes access to the pteg and pvo 831 * tables. 832 */ 833 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 834 MTX_RECURSE); 835 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 836 837 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 838 839 /* 840 * Initialise the unmanaged pvo pool. 841 */ 842 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 843 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 844 moea_bpvo_pool_index = 0; 845 846 /* 847 * Make sure kernel vsid is allocated as well as VSID 0. 848 */ 849 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 850 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 851 moea_vsid_bitmap[0] |= 1; 852 853 /* 854 * Initialize the kernel pmap (which is statically allocated). 855 */ 856 PMAP_LOCK_INIT(kernel_pmap); 857 for (i = 0; i < 16; i++) 858 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 859 CPU_FILL(&kernel_pmap->pm_active); 860 LIST_INIT(&kernel_pmap->pmap_pvo); 861 862 /* 863 * Set up the Open Firmware mappings 864 */ 865 chosen = OF_finddevice("/chosen"); 866 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 867 (mmu = OF_instance_to_package(mmui)) != -1 && 868 (sz = OF_getproplen(mmu, "translations")) != -1) { 869 translations = NULL; 870 for (i = 0; phys_avail[i] != 0; i += 2) { 871 if (phys_avail[i + 1] >= sz) { 872 translations = (struct ofw_map *)phys_avail[i]; 873 break; 874 } 875 } 876 if (translations == NULL) 877 panic("moea_bootstrap: no space to copy translations"); 878 bzero(translations, sz); 879 if (OF_getprop(mmu, "translations", translations, sz) == -1) 880 panic("moea_bootstrap: can't get ofw translations"); 881 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 882 sz /= sizeof(*translations); 883 qsort(translations, sz, sizeof (*translations), om_cmp); 884 for (i = 0; i < sz; i++) { 885 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 886 translations[i].om_pa, translations[i].om_va, 887 translations[i].om_len); 888 889 /* 890 * If the mapping is 1:1, let the RAM and device 891 * on-demand BAT tables take care of the translation. 892 */ 893 if (translations[i].om_va == translations[i].om_pa) 894 continue; 895 896 /* Enter the pages */ 897 for (off = 0; off < translations[i].om_len; 898 off += PAGE_SIZE) 899 moea_kenter(mmup, translations[i].om_va + off, 900 translations[i].om_pa + off); 901 } 902 } 903 904 /* 905 * Calculate the last available physical address. 906 */ 907 for (i = 0; phys_avail[i + 2] != 0; i += 2) 908 ; 909 Maxmem = powerpc_btop(phys_avail[i + 1]); 910 911 moea_cpu_bootstrap(mmup,0); 912 913 pmap_bootstrapped++; 914 915 /* 916 * Set the start and end of kva. 917 */ 918 virtual_avail = VM_MIN_KERNEL_ADDRESS; 919 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 920 921 /* 922 * Allocate a kernel stack with a guard page for thread0 and map it 923 * into the kernel page map. 924 */ 925 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 926 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 927 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 928 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 929 thread0.td_kstack = va; 930 thread0.td_kstack_pages = KSTACK_PAGES; 931 for (i = 0; i < KSTACK_PAGES; i++) { 932 moea_kenter(mmup, va, pa); 933 pa += PAGE_SIZE; 934 va += PAGE_SIZE; 935 } 936 937 /* 938 * Allocate virtual address space for the message buffer. 939 */ 940 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 941 msgbufp = (struct msgbuf *)virtual_avail; 942 va = virtual_avail; 943 virtual_avail += round_page(msgbufsize); 944 while (va < virtual_avail) { 945 moea_kenter(mmup, va, pa); 946 pa += PAGE_SIZE; 947 va += PAGE_SIZE; 948 } 949 950 /* 951 * Allocate virtual address space for the dynamic percpu area. 952 */ 953 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 954 dpcpu = (void *)virtual_avail; 955 va = virtual_avail; 956 virtual_avail += DPCPU_SIZE; 957 while (va < virtual_avail) { 958 moea_kenter(mmup, va, pa); 959 pa += PAGE_SIZE; 960 va += PAGE_SIZE; 961 } 962 dpcpu_init(dpcpu, 0); 963 } 964 965 /* 966 * Activate a user pmap. The pmap must be activated before it's address 967 * space can be accessed in any way. 968 */ 969 void 970 moea_activate(mmu_t mmu, struct thread *td) 971 { 972 pmap_t pm, pmr; 973 974 /* 975 * Load all the data we need up front to encourage the compiler to 976 * not issue any loads while we have interrupts disabled below. 977 */ 978 pm = &td->td_proc->p_vmspace->vm_pmap; 979 pmr = pm->pmap_phys; 980 981 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 982 PCPU_SET(curpmap, pmr); 983 } 984 985 void 986 moea_deactivate(mmu_t mmu, struct thread *td) 987 { 988 pmap_t pm; 989 990 pm = &td->td_proc->p_vmspace->vm_pmap; 991 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 992 PCPU_SET(curpmap, NULL); 993 } 994 995 void 996 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 997 { 998 struct pvo_entry *pvo; 999 1000 PMAP_LOCK(pm); 1001 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1002 1003 if (pvo != NULL) { 1004 if (wired) { 1005 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1006 pm->pm_stats.wired_count++; 1007 pvo->pvo_vaddr |= PVO_WIRED; 1008 } else { 1009 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1010 pm->pm_stats.wired_count--; 1011 pvo->pvo_vaddr &= ~PVO_WIRED; 1012 } 1013 } 1014 PMAP_UNLOCK(pm); 1015 } 1016 1017 void 1018 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1019 { 1020 vm_offset_t dst; 1021 vm_offset_t src; 1022 1023 dst = VM_PAGE_TO_PHYS(mdst); 1024 src = VM_PAGE_TO_PHYS(msrc); 1025 1026 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1027 } 1028 1029 /* 1030 * Zero a page of physical memory by temporarily mapping it into the tlb. 1031 */ 1032 void 1033 moea_zero_page(mmu_t mmu, vm_page_t m) 1034 { 1035 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1036 void *va = (void *)pa; 1037 1038 bzero(va, PAGE_SIZE); 1039 } 1040 1041 void 1042 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1043 { 1044 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1045 void *va = (void *)(pa + off); 1046 1047 bzero(va, size); 1048 } 1049 1050 void 1051 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1052 { 1053 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1054 void *va = (void *)pa; 1055 1056 bzero(va, PAGE_SIZE); 1057 } 1058 1059 /* 1060 * Map the given physical page at the specified virtual address in the 1061 * target pmap with the protection requested. If specified the page 1062 * will be wired down. 1063 */ 1064 void 1065 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1066 boolean_t wired) 1067 { 1068 1069 vm_page_lock_queues(); 1070 PMAP_LOCK(pmap); 1071 moea_enter_locked(pmap, va, m, prot, wired); 1072 vm_page_unlock_queues(); 1073 PMAP_UNLOCK(pmap); 1074 } 1075 1076 /* 1077 * Map the given physical page at the specified virtual address in the 1078 * target pmap with the protection requested. If specified the page 1079 * will be wired down. 1080 * 1081 * The page queues and pmap must be locked. 1082 */ 1083 static void 1084 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1085 boolean_t wired) 1086 { 1087 struct pvo_head *pvo_head; 1088 uma_zone_t zone; 1089 vm_page_t pg; 1090 u_int pte_lo, pvo_flags, was_exec; 1091 int error; 1092 1093 if (!moea_initialized) { 1094 pvo_head = &moea_pvo_kunmanaged; 1095 zone = moea_upvo_zone; 1096 pvo_flags = 0; 1097 pg = NULL; 1098 was_exec = PTE_EXEC; 1099 } else { 1100 pvo_head = vm_page_to_pvoh(m); 1101 pg = m; 1102 zone = moea_mpvo_zone; 1103 pvo_flags = PVO_MANAGED; 1104 was_exec = 0; 1105 } 1106 if (pmap_bootstrapped) 1107 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1108 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1109 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1110 VM_OBJECT_LOCKED(m->object), 1111 ("moea_enter_locked: page %p is not busy", m)); 1112 1113 /* XXX change the pvo head for fake pages */ 1114 if ((m->oflags & VPO_UNMANAGED) != 0) { 1115 pvo_flags &= ~PVO_MANAGED; 1116 pvo_head = &moea_pvo_kunmanaged; 1117 zone = moea_upvo_zone; 1118 } 1119 1120 /* 1121 * If this is a managed page, and it's the first reference to the page, 1122 * clear the execness of the page. Otherwise fetch the execness. 1123 */ 1124 if ((pg != NULL) && ((m->oflags & VPO_UNMANAGED) == 0)) { 1125 if (LIST_EMPTY(pvo_head)) { 1126 moea_attr_clear(pg, PTE_EXEC); 1127 } else { 1128 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1129 } 1130 } 1131 1132 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1133 1134 if (prot & VM_PROT_WRITE) { 1135 pte_lo |= PTE_BW; 1136 if (pmap_bootstrapped && 1137 (m->oflags & VPO_UNMANAGED) == 0) 1138 vm_page_aflag_set(m, PGA_WRITEABLE); 1139 } else 1140 pte_lo |= PTE_BR; 1141 1142 if (prot & VM_PROT_EXECUTE) 1143 pvo_flags |= PVO_EXECUTABLE; 1144 1145 if (wired) 1146 pvo_flags |= PVO_WIRED; 1147 1148 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1149 pte_lo, pvo_flags); 1150 1151 /* 1152 * Flush the real page from the instruction cache if this page is 1153 * mapped executable and cacheable and was not previously mapped (or 1154 * was not mapped executable). 1155 */ 1156 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1157 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1158 /* 1159 * Flush the real memory from the cache. 1160 */ 1161 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1162 if (pg != NULL) 1163 moea_attr_save(pg, PTE_EXEC); 1164 } 1165 1166 /* XXX syncicache always until problems are sorted */ 1167 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1168 } 1169 1170 /* 1171 * Maps a sequence of resident pages belonging to the same object. 1172 * The sequence begins with the given page m_start. This page is 1173 * mapped at the given virtual address start. Each subsequent page is 1174 * mapped at a virtual address that is offset from start by the same 1175 * amount as the page is offset from m_start within the object. The 1176 * last page in the sequence is the page with the largest offset from 1177 * m_start that can be mapped at a virtual address less than the given 1178 * virtual address end. Not every virtual page between start and end 1179 * is mapped; only those for which a resident page exists with the 1180 * corresponding offset from m_start are mapped. 1181 */ 1182 void 1183 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1184 vm_page_t m_start, vm_prot_t prot) 1185 { 1186 vm_page_t m; 1187 vm_pindex_t diff, psize; 1188 1189 psize = atop(end - start); 1190 m = m_start; 1191 vm_page_lock_queues(); 1192 PMAP_LOCK(pm); 1193 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1194 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1195 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1196 m = TAILQ_NEXT(m, listq); 1197 } 1198 vm_page_unlock_queues(); 1199 PMAP_UNLOCK(pm); 1200 } 1201 1202 void 1203 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1204 vm_prot_t prot) 1205 { 1206 1207 vm_page_lock_queues(); 1208 PMAP_LOCK(pm); 1209 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1210 FALSE); 1211 vm_page_unlock_queues(); 1212 PMAP_UNLOCK(pm); 1213 } 1214 1215 vm_paddr_t 1216 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1217 { 1218 struct pvo_entry *pvo; 1219 vm_paddr_t pa; 1220 1221 PMAP_LOCK(pm); 1222 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1223 if (pvo == NULL) 1224 pa = 0; 1225 else 1226 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1227 PMAP_UNLOCK(pm); 1228 return (pa); 1229 } 1230 1231 /* 1232 * Atomically extract and hold the physical page with the given 1233 * pmap and virtual address pair if that mapping permits the given 1234 * protection. 1235 */ 1236 vm_page_t 1237 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1238 { 1239 struct pvo_entry *pvo; 1240 vm_page_t m; 1241 vm_paddr_t pa; 1242 1243 m = NULL; 1244 pa = 0; 1245 PMAP_LOCK(pmap); 1246 retry: 1247 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1248 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1249 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1250 (prot & VM_PROT_WRITE) == 0)) { 1251 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1252 goto retry; 1253 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1254 vm_page_hold(m); 1255 } 1256 PA_UNLOCK_COND(pa); 1257 PMAP_UNLOCK(pmap); 1258 return (m); 1259 } 1260 1261 void 1262 moea_init(mmu_t mmu) 1263 { 1264 1265 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1266 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1267 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1268 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1269 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1270 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1271 moea_initialized = TRUE; 1272 } 1273 1274 boolean_t 1275 moea_is_referenced(mmu_t mmu, vm_page_t m) 1276 { 1277 1278 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1279 ("moea_is_referenced: page %p is not managed", m)); 1280 return (moea_query_bit(m, PTE_REF)); 1281 } 1282 1283 boolean_t 1284 moea_is_modified(mmu_t mmu, vm_page_t m) 1285 { 1286 1287 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1288 ("moea_is_modified: page %p is not managed", m)); 1289 1290 /* 1291 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1292 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1293 * is clear, no PTEs can have PTE_CHG set. 1294 */ 1295 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1296 if ((m->oflags & VPO_BUSY) == 0 && 1297 (m->aflags & PGA_WRITEABLE) == 0) 1298 return (FALSE); 1299 return (moea_query_bit(m, PTE_CHG)); 1300 } 1301 1302 boolean_t 1303 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1304 { 1305 struct pvo_entry *pvo; 1306 boolean_t rv; 1307 1308 PMAP_LOCK(pmap); 1309 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1310 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1311 PMAP_UNLOCK(pmap); 1312 return (rv); 1313 } 1314 1315 void 1316 moea_clear_reference(mmu_t mmu, vm_page_t m) 1317 { 1318 1319 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1320 ("moea_clear_reference: page %p is not managed", m)); 1321 moea_clear_bit(m, PTE_REF); 1322 } 1323 1324 void 1325 moea_clear_modify(mmu_t mmu, vm_page_t m) 1326 { 1327 1328 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1329 ("moea_clear_modify: page %p is not managed", m)); 1330 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1331 KASSERT((m->oflags & VPO_BUSY) == 0, 1332 ("moea_clear_modify: page %p is busy", m)); 1333 1334 /* 1335 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1336 * set. If the object containing the page is locked and the page is 1337 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1338 */ 1339 if ((m->aflags & PGA_WRITEABLE) == 0) 1340 return; 1341 moea_clear_bit(m, PTE_CHG); 1342 } 1343 1344 /* 1345 * Clear the write and modified bits in each of the given page's mappings. 1346 */ 1347 void 1348 moea_remove_write(mmu_t mmu, vm_page_t m) 1349 { 1350 struct pvo_entry *pvo; 1351 struct pte *pt; 1352 pmap_t pmap; 1353 u_int lo; 1354 1355 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1356 ("moea_remove_write: page %p is not managed", m)); 1357 1358 /* 1359 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1360 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1361 * is clear, no page table entries need updating. 1362 */ 1363 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1364 if ((m->oflags & VPO_BUSY) == 0 && 1365 (m->aflags & PGA_WRITEABLE) == 0) 1366 return; 1367 vm_page_lock_queues(); 1368 lo = moea_attr_fetch(m); 1369 powerpc_sync(); 1370 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1371 pmap = pvo->pvo_pmap; 1372 PMAP_LOCK(pmap); 1373 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1374 pt = moea_pvo_to_pte(pvo, -1); 1375 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1376 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1377 if (pt != NULL) { 1378 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1379 lo |= pvo->pvo_pte.pte.pte_lo; 1380 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1381 moea_pte_change(pt, &pvo->pvo_pte.pte, 1382 pvo->pvo_vaddr); 1383 mtx_unlock(&moea_table_mutex); 1384 } 1385 } 1386 PMAP_UNLOCK(pmap); 1387 } 1388 if ((lo & PTE_CHG) != 0) { 1389 moea_attr_clear(m, PTE_CHG); 1390 vm_page_dirty(m); 1391 } 1392 vm_page_aflag_clear(m, PGA_WRITEABLE); 1393 vm_page_unlock_queues(); 1394 } 1395 1396 /* 1397 * moea_ts_referenced: 1398 * 1399 * Return a count of reference bits for a page, clearing those bits. 1400 * It is not necessary for every reference bit to be cleared, but it 1401 * is necessary that 0 only be returned when there are truly no 1402 * reference bits set. 1403 * 1404 * XXX: The exact number of bits to check and clear is a matter that 1405 * should be tested and standardized at some point in the future for 1406 * optimal aging of shared pages. 1407 */ 1408 boolean_t 1409 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1410 { 1411 1412 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1413 ("moea_ts_referenced: page %p is not managed", m)); 1414 return (moea_clear_bit(m, PTE_REF)); 1415 } 1416 1417 /* 1418 * Modify the WIMG settings of all mappings for a page. 1419 */ 1420 void 1421 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1422 { 1423 struct pvo_entry *pvo; 1424 struct pvo_head *pvo_head; 1425 struct pte *pt; 1426 pmap_t pmap; 1427 u_int lo; 1428 1429 if ((m->oflags & VPO_UNMANAGED) != 0) { 1430 m->md.mdpg_cache_attrs = ma; 1431 return; 1432 } 1433 1434 vm_page_lock_queues(); 1435 pvo_head = vm_page_to_pvoh(m); 1436 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1437 1438 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1439 pmap = pvo->pvo_pmap; 1440 PMAP_LOCK(pmap); 1441 pt = moea_pvo_to_pte(pvo, -1); 1442 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1443 pvo->pvo_pte.pte.pte_lo |= lo; 1444 if (pt != NULL) { 1445 moea_pte_change(pt, &pvo->pvo_pte.pte, 1446 pvo->pvo_vaddr); 1447 if (pvo->pvo_pmap == kernel_pmap) 1448 isync(); 1449 } 1450 mtx_unlock(&moea_table_mutex); 1451 PMAP_UNLOCK(pmap); 1452 } 1453 m->md.mdpg_cache_attrs = ma; 1454 vm_page_unlock_queues(); 1455 } 1456 1457 /* 1458 * Map a wired page into kernel virtual address space. 1459 */ 1460 void 1461 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1462 { 1463 1464 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1465 } 1466 1467 void 1468 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1469 { 1470 u_int pte_lo; 1471 int error; 1472 1473 #if 0 1474 if (va < VM_MIN_KERNEL_ADDRESS) 1475 panic("moea_kenter: attempt to enter non-kernel address %#x", 1476 va); 1477 #endif 1478 1479 pte_lo = moea_calc_wimg(pa, ma); 1480 1481 PMAP_LOCK(kernel_pmap); 1482 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1483 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1484 1485 if (error != 0 && error != ENOENT) 1486 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1487 pa, error); 1488 1489 /* 1490 * Flush the real memory from the instruction cache. 1491 */ 1492 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1493 moea_syncicache(pa, PAGE_SIZE); 1494 } 1495 PMAP_UNLOCK(kernel_pmap); 1496 } 1497 1498 /* 1499 * Extract the physical page address associated with the given kernel virtual 1500 * address. 1501 */ 1502 vm_offset_t 1503 moea_kextract(mmu_t mmu, vm_offset_t va) 1504 { 1505 struct pvo_entry *pvo; 1506 vm_paddr_t pa; 1507 1508 /* 1509 * Allow direct mappings on 32-bit OEA 1510 */ 1511 if (va < VM_MIN_KERNEL_ADDRESS) { 1512 return (va); 1513 } 1514 1515 PMAP_LOCK(kernel_pmap); 1516 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1517 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1518 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1519 PMAP_UNLOCK(kernel_pmap); 1520 return (pa); 1521 } 1522 1523 /* 1524 * Remove a wired page from kernel virtual address space. 1525 */ 1526 void 1527 moea_kremove(mmu_t mmu, vm_offset_t va) 1528 { 1529 1530 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1531 } 1532 1533 /* 1534 * Map a range of physical addresses into kernel virtual address space. 1535 * 1536 * The value passed in *virt is a suggested virtual address for the mapping. 1537 * Architectures which can support a direct-mapped physical to virtual region 1538 * can return the appropriate address within that region, leaving '*virt' 1539 * unchanged. We cannot and therefore do not; *virt is updated with the 1540 * first usable address after the mapped region. 1541 */ 1542 vm_offset_t 1543 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1544 vm_offset_t pa_end, int prot) 1545 { 1546 vm_offset_t sva, va; 1547 1548 sva = *virt; 1549 va = sva; 1550 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1551 moea_kenter(mmu, va, pa_start); 1552 *virt = va; 1553 return (sva); 1554 } 1555 1556 /* 1557 * Returns true if the pmap's pv is one of the first 1558 * 16 pvs linked to from this page. This count may 1559 * be changed upwards or downwards in the future; it 1560 * is only necessary that true be returned for a small 1561 * subset of pmaps for proper page aging. 1562 */ 1563 boolean_t 1564 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1565 { 1566 int loops; 1567 struct pvo_entry *pvo; 1568 boolean_t rv; 1569 1570 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1571 ("moea_page_exists_quick: page %p is not managed", m)); 1572 loops = 0; 1573 rv = FALSE; 1574 vm_page_lock_queues(); 1575 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1576 if (pvo->pvo_pmap == pmap) { 1577 rv = TRUE; 1578 break; 1579 } 1580 if (++loops >= 16) 1581 break; 1582 } 1583 vm_page_unlock_queues(); 1584 return (rv); 1585 } 1586 1587 /* 1588 * Return the number of managed mappings to the given physical page 1589 * that are wired. 1590 */ 1591 int 1592 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1593 { 1594 struct pvo_entry *pvo; 1595 int count; 1596 1597 count = 0; 1598 if ((m->oflags & VPO_UNMANAGED) != 0) 1599 return (count); 1600 vm_page_lock_queues(); 1601 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1602 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1603 count++; 1604 vm_page_unlock_queues(); 1605 return (count); 1606 } 1607 1608 static u_int moea_vsidcontext; 1609 1610 void 1611 moea_pinit(mmu_t mmu, pmap_t pmap) 1612 { 1613 int i, mask; 1614 u_int entropy; 1615 1616 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1617 PMAP_LOCK_INIT(pmap); 1618 LIST_INIT(&pmap->pmap_pvo); 1619 1620 entropy = 0; 1621 __asm __volatile("mftb %0" : "=r"(entropy)); 1622 1623 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1624 == NULL) { 1625 pmap->pmap_phys = pmap; 1626 } 1627 1628 1629 mtx_lock(&moea_vsid_mutex); 1630 /* 1631 * Allocate some segment registers for this pmap. 1632 */ 1633 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1634 u_int hash, n; 1635 1636 /* 1637 * Create a new value by mutiplying by a prime and adding in 1638 * entropy from the timebase register. This is to make the 1639 * VSID more random so that the PT hash function collides 1640 * less often. (Note that the prime casues gcc to do shifts 1641 * instead of a multiply.) 1642 */ 1643 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1644 hash = moea_vsidcontext & (NPMAPS - 1); 1645 if (hash == 0) /* 0 is special, avoid it */ 1646 continue; 1647 n = hash >> 5; 1648 mask = 1 << (hash & (VSID_NBPW - 1)); 1649 hash = (moea_vsidcontext & 0xfffff); 1650 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1651 /* anything free in this bucket? */ 1652 if (moea_vsid_bitmap[n] == 0xffffffff) { 1653 entropy = (moea_vsidcontext >> 20); 1654 continue; 1655 } 1656 i = ffs(~moea_vsid_bitmap[n]) - 1; 1657 mask = 1 << i; 1658 hash &= 0xfffff & ~(VSID_NBPW - 1); 1659 hash |= i; 1660 } 1661 KASSERT(!(moea_vsid_bitmap[n] & mask), 1662 ("Allocating in-use VSID group %#x\n", hash)); 1663 moea_vsid_bitmap[n] |= mask; 1664 for (i = 0; i < 16; i++) 1665 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1666 mtx_unlock(&moea_vsid_mutex); 1667 return; 1668 } 1669 1670 mtx_unlock(&moea_vsid_mutex); 1671 panic("moea_pinit: out of segments"); 1672 } 1673 1674 /* 1675 * Initialize the pmap associated with process 0. 1676 */ 1677 void 1678 moea_pinit0(mmu_t mmu, pmap_t pm) 1679 { 1680 1681 moea_pinit(mmu, pm); 1682 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1683 } 1684 1685 /* 1686 * Set the physical protection on the specified range of this map as requested. 1687 */ 1688 void 1689 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1690 vm_prot_t prot) 1691 { 1692 struct pvo_entry *pvo; 1693 struct pte *pt; 1694 int pteidx; 1695 1696 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1697 ("moea_protect: non current pmap")); 1698 1699 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1700 moea_remove(mmu, pm, sva, eva); 1701 return; 1702 } 1703 1704 vm_page_lock_queues(); 1705 PMAP_LOCK(pm); 1706 for (; sva < eva; sva += PAGE_SIZE) { 1707 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1708 if (pvo == NULL) 1709 continue; 1710 1711 if ((prot & VM_PROT_EXECUTE) == 0) 1712 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1713 1714 /* 1715 * Grab the PTE pointer before we diddle with the cached PTE 1716 * copy. 1717 */ 1718 pt = moea_pvo_to_pte(pvo, pteidx); 1719 /* 1720 * Change the protection of the page. 1721 */ 1722 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1723 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1724 1725 /* 1726 * If the PVO is in the page table, update that pte as well. 1727 */ 1728 if (pt != NULL) { 1729 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1730 mtx_unlock(&moea_table_mutex); 1731 } 1732 } 1733 vm_page_unlock_queues(); 1734 PMAP_UNLOCK(pm); 1735 } 1736 1737 /* 1738 * Map a list of wired pages into kernel virtual address space. This is 1739 * intended for temporary mappings which do not need page modification or 1740 * references recorded. Existing mappings in the region are overwritten. 1741 */ 1742 void 1743 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1744 { 1745 vm_offset_t va; 1746 1747 va = sva; 1748 while (count-- > 0) { 1749 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1750 va += PAGE_SIZE; 1751 m++; 1752 } 1753 } 1754 1755 /* 1756 * Remove page mappings from kernel virtual address space. Intended for 1757 * temporary mappings entered by moea_qenter. 1758 */ 1759 void 1760 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1761 { 1762 vm_offset_t va; 1763 1764 va = sva; 1765 while (count-- > 0) { 1766 moea_kremove(mmu, va); 1767 va += PAGE_SIZE; 1768 } 1769 } 1770 1771 void 1772 moea_release(mmu_t mmu, pmap_t pmap) 1773 { 1774 int idx, mask; 1775 1776 /* 1777 * Free segment register's VSID 1778 */ 1779 if (pmap->pm_sr[0] == 0) 1780 panic("moea_release"); 1781 1782 mtx_lock(&moea_vsid_mutex); 1783 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1784 mask = 1 << (idx % VSID_NBPW); 1785 idx /= VSID_NBPW; 1786 moea_vsid_bitmap[idx] &= ~mask; 1787 mtx_unlock(&moea_vsid_mutex); 1788 PMAP_LOCK_DESTROY(pmap); 1789 } 1790 1791 /* 1792 * Remove the given range of addresses from the specified map. 1793 */ 1794 void 1795 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1796 { 1797 struct pvo_entry *pvo; 1798 int pteidx; 1799 1800 vm_page_lock_queues(); 1801 PMAP_LOCK(pm); 1802 if ((eva - sva)/PAGE_SIZE < 10) { 1803 for (; sva < eva; sva += PAGE_SIZE) { 1804 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1805 if (pvo != NULL) 1806 moea_pvo_remove(pvo, pteidx); 1807 } 1808 } else { 1809 LIST_FOREACH(pvo, &pm->pmap_pvo, pvo_plink) { 1810 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 1811 continue; 1812 moea_pvo_remove(pvo, -1); 1813 } 1814 } 1815 PMAP_UNLOCK(pm); 1816 vm_page_unlock_queues(); 1817 } 1818 1819 /* 1820 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1821 * will reflect changes in pte's back to the vm_page. 1822 */ 1823 void 1824 moea_remove_all(mmu_t mmu, vm_page_t m) 1825 { 1826 struct pvo_head *pvo_head; 1827 struct pvo_entry *pvo, *next_pvo; 1828 pmap_t pmap; 1829 1830 vm_page_lock_queues(); 1831 pvo_head = vm_page_to_pvoh(m); 1832 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1833 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1834 1835 pmap = pvo->pvo_pmap; 1836 PMAP_LOCK(pmap); 1837 moea_pvo_remove(pvo, -1); 1838 PMAP_UNLOCK(pmap); 1839 } 1840 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) { 1841 moea_attr_clear(m, PTE_CHG); 1842 vm_page_dirty(m); 1843 } 1844 vm_page_aflag_clear(m, PGA_WRITEABLE); 1845 vm_page_unlock_queues(); 1846 } 1847 1848 /* 1849 * Allocate a physical page of memory directly from the phys_avail map. 1850 * Can only be called from moea_bootstrap before avail start and end are 1851 * calculated. 1852 */ 1853 static vm_offset_t 1854 moea_bootstrap_alloc(vm_size_t size, u_int align) 1855 { 1856 vm_offset_t s, e; 1857 int i, j; 1858 1859 size = round_page(size); 1860 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1861 if (align != 0) 1862 s = (phys_avail[i] + align - 1) & ~(align - 1); 1863 else 1864 s = phys_avail[i]; 1865 e = s + size; 1866 1867 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1868 continue; 1869 1870 if (s == phys_avail[i]) { 1871 phys_avail[i] += size; 1872 } else if (e == phys_avail[i + 1]) { 1873 phys_avail[i + 1] -= size; 1874 } else { 1875 for (j = phys_avail_count * 2; j > i; j -= 2) { 1876 phys_avail[j] = phys_avail[j - 2]; 1877 phys_avail[j + 1] = phys_avail[j - 1]; 1878 } 1879 1880 phys_avail[i + 3] = phys_avail[i + 1]; 1881 phys_avail[i + 1] = s; 1882 phys_avail[i + 2] = e; 1883 phys_avail_count++; 1884 } 1885 1886 return (s); 1887 } 1888 panic("moea_bootstrap_alloc: could not allocate memory"); 1889 } 1890 1891 static void 1892 moea_syncicache(vm_offset_t pa, vm_size_t len) 1893 { 1894 __syncicache((void *)pa, len); 1895 } 1896 1897 static int 1898 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1899 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1900 { 1901 struct pvo_entry *pvo; 1902 u_int sr; 1903 int first; 1904 u_int ptegidx; 1905 int i; 1906 int bootstrap; 1907 1908 moea_pvo_enter_calls++; 1909 first = 0; 1910 bootstrap = 0; 1911 1912 /* 1913 * Compute the PTE Group index. 1914 */ 1915 va &= ~ADDR_POFF; 1916 sr = va_to_sr(pm->pm_sr, va); 1917 ptegidx = va_to_pteg(sr, va); 1918 1919 /* 1920 * Remove any existing mapping for this page. Reuse the pvo entry if 1921 * there is a mapping. 1922 */ 1923 mtx_lock(&moea_table_mutex); 1924 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1925 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1926 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1927 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1928 (pte_lo & PTE_PP)) { 1929 mtx_unlock(&moea_table_mutex); 1930 return (0); 1931 } 1932 moea_pvo_remove(pvo, -1); 1933 break; 1934 } 1935 } 1936 1937 /* 1938 * If we aren't overwriting a mapping, try to allocate. 1939 */ 1940 if (moea_initialized) { 1941 pvo = uma_zalloc(zone, M_NOWAIT); 1942 } else { 1943 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1944 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1945 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1946 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1947 } 1948 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1949 moea_bpvo_pool_index++; 1950 bootstrap = 1; 1951 } 1952 1953 if (pvo == NULL) { 1954 mtx_unlock(&moea_table_mutex); 1955 return (ENOMEM); 1956 } 1957 1958 moea_pvo_entries++; 1959 pvo->pvo_vaddr = va; 1960 pvo->pvo_pmap = pm; 1961 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1962 pvo->pvo_vaddr &= ~ADDR_POFF; 1963 if (flags & VM_PROT_EXECUTE) 1964 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1965 if (flags & PVO_WIRED) 1966 pvo->pvo_vaddr |= PVO_WIRED; 1967 if (pvo_head != &moea_pvo_kunmanaged) 1968 pvo->pvo_vaddr |= PVO_MANAGED; 1969 if (bootstrap) 1970 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1971 1972 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1973 1974 /* 1975 * Add to pmap list 1976 */ 1977 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink); 1978 1979 /* 1980 * Remember if the list was empty and therefore will be the first 1981 * item. 1982 */ 1983 if (LIST_FIRST(pvo_head) == NULL) 1984 first = 1; 1985 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1986 1987 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1988 pm->pm_stats.wired_count++; 1989 pm->pm_stats.resident_count++; 1990 1991 /* 1992 * We hope this succeeds but it isn't required. 1993 */ 1994 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1995 if (i >= 0) { 1996 PVO_PTEGIDX_SET(pvo, i); 1997 } else { 1998 panic("moea_pvo_enter: overflow"); 1999 moea_pte_overflow++; 2000 } 2001 mtx_unlock(&moea_table_mutex); 2002 2003 return (first ? ENOENT : 0); 2004 } 2005 2006 static void 2007 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2008 { 2009 struct pte *pt; 2010 2011 /* 2012 * If there is an active pte entry, we need to deactivate it (and 2013 * save the ref & cfg bits). 2014 */ 2015 pt = moea_pvo_to_pte(pvo, pteidx); 2016 if (pt != NULL) { 2017 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2018 mtx_unlock(&moea_table_mutex); 2019 PVO_PTEGIDX_CLR(pvo); 2020 } else { 2021 moea_pte_overflow--; 2022 } 2023 2024 /* 2025 * Update our statistics. 2026 */ 2027 pvo->pvo_pmap->pm_stats.resident_count--; 2028 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2029 pvo->pvo_pmap->pm_stats.wired_count--; 2030 2031 /* 2032 * Save the REF/CHG bits into their cache if the page is managed. 2033 */ 2034 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2035 struct vm_page *pg; 2036 2037 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2038 if (pg != NULL) { 2039 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2040 (PTE_REF | PTE_CHG)); 2041 } 2042 } 2043 2044 /* 2045 * Remove this PVO from the PV and pmap lists. 2046 */ 2047 LIST_REMOVE(pvo, pvo_vlink); 2048 LIST_REMOVE(pvo, pvo_plink); 2049 2050 /* 2051 * Remove this from the overflow list and return it to the pool 2052 * if we aren't going to reuse it. 2053 */ 2054 LIST_REMOVE(pvo, pvo_olink); 2055 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2056 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2057 moea_upvo_zone, pvo); 2058 moea_pvo_entries--; 2059 moea_pvo_remove_calls++; 2060 } 2061 2062 static __inline int 2063 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2064 { 2065 int pteidx; 2066 2067 /* 2068 * We can find the actual pte entry without searching by grabbing 2069 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2070 * noticing the HID bit. 2071 */ 2072 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2073 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2074 pteidx ^= moea_pteg_mask * 8; 2075 2076 return (pteidx); 2077 } 2078 2079 static struct pvo_entry * 2080 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2081 { 2082 struct pvo_entry *pvo; 2083 int ptegidx; 2084 u_int sr; 2085 2086 va &= ~ADDR_POFF; 2087 sr = va_to_sr(pm->pm_sr, va); 2088 ptegidx = va_to_pteg(sr, va); 2089 2090 mtx_lock(&moea_table_mutex); 2091 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2092 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2093 if (pteidx_p) 2094 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2095 break; 2096 } 2097 } 2098 mtx_unlock(&moea_table_mutex); 2099 2100 return (pvo); 2101 } 2102 2103 static struct pte * 2104 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2105 { 2106 struct pte *pt; 2107 2108 /* 2109 * If we haven't been supplied the ptegidx, calculate it. 2110 */ 2111 if (pteidx == -1) { 2112 int ptegidx; 2113 u_int sr; 2114 2115 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2116 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2117 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2118 } 2119 2120 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2121 mtx_lock(&moea_table_mutex); 2122 2123 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2124 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2125 "valid pte index", pvo); 2126 } 2127 2128 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2129 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2130 "pvo but no valid pte", pvo); 2131 } 2132 2133 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2134 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2135 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2136 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2137 } 2138 2139 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2140 != 0) { 2141 panic("moea_pvo_to_pte: pvo %p pte does not match " 2142 "pte %p in moea_pteg_table", pvo, pt); 2143 } 2144 2145 mtx_assert(&moea_table_mutex, MA_OWNED); 2146 return (pt); 2147 } 2148 2149 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2150 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2151 "moea_pteg_table but valid in pvo", pvo, pt); 2152 } 2153 2154 mtx_unlock(&moea_table_mutex); 2155 return (NULL); 2156 } 2157 2158 /* 2159 * XXX: THIS STUFF SHOULD BE IN pte.c? 2160 */ 2161 int 2162 moea_pte_spill(vm_offset_t addr) 2163 { 2164 struct pvo_entry *source_pvo, *victim_pvo; 2165 struct pvo_entry *pvo; 2166 int ptegidx, i, j; 2167 u_int sr; 2168 struct pteg *pteg; 2169 struct pte *pt; 2170 2171 moea_pte_spills++; 2172 2173 sr = mfsrin(addr); 2174 ptegidx = va_to_pteg(sr, addr); 2175 2176 /* 2177 * Have to substitute some entry. Use the primary hash for this. 2178 * Use low bits of timebase as random generator. 2179 */ 2180 pteg = &moea_pteg_table[ptegidx]; 2181 mtx_lock(&moea_table_mutex); 2182 __asm __volatile("mftb %0" : "=r"(i)); 2183 i &= 7; 2184 pt = &pteg->pt[i]; 2185 2186 source_pvo = NULL; 2187 victim_pvo = NULL; 2188 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2189 /* 2190 * We need to find a pvo entry for this address. 2191 */ 2192 if (source_pvo == NULL && 2193 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2194 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2195 /* 2196 * Now found an entry to be spilled into the pteg. 2197 * The PTE is now valid, so we know it's active. 2198 */ 2199 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2200 2201 if (j >= 0) { 2202 PVO_PTEGIDX_SET(pvo, j); 2203 moea_pte_overflow--; 2204 mtx_unlock(&moea_table_mutex); 2205 return (1); 2206 } 2207 2208 source_pvo = pvo; 2209 2210 if (victim_pvo != NULL) 2211 break; 2212 } 2213 2214 /* 2215 * We also need the pvo entry of the victim we are replacing 2216 * so save the R & C bits of the PTE. 2217 */ 2218 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2219 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2220 victim_pvo = pvo; 2221 if (source_pvo != NULL) 2222 break; 2223 } 2224 } 2225 2226 if (source_pvo == NULL) { 2227 mtx_unlock(&moea_table_mutex); 2228 return (0); 2229 } 2230 2231 if (victim_pvo == NULL) { 2232 if ((pt->pte_hi & PTE_HID) == 0) 2233 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2234 "entry", pt); 2235 2236 /* 2237 * If this is a secondary PTE, we need to search it's primary 2238 * pvo bucket for the matching PVO. 2239 */ 2240 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2241 pvo_olink) { 2242 /* 2243 * We also need the pvo entry of the victim we are 2244 * replacing so save the R & C bits of the PTE. 2245 */ 2246 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2247 victim_pvo = pvo; 2248 break; 2249 } 2250 } 2251 2252 if (victim_pvo == NULL) 2253 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2254 "entry", pt); 2255 } 2256 2257 /* 2258 * We are invalidating the TLB entry for the EA we are replacing even 2259 * though it's valid. If we don't, we lose any ref/chg bit changes 2260 * contained in the TLB entry. 2261 */ 2262 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2263 2264 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2265 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2266 2267 PVO_PTEGIDX_CLR(victim_pvo); 2268 PVO_PTEGIDX_SET(source_pvo, i); 2269 moea_pte_replacements++; 2270 2271 mtx_unlock(&moea_table_mutex); 2272 return (1); 2273 } 2274 2275 static int 2276 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2277 { 2278 struct pte *pt; 2279 int i; 2280 2281 mtx_assert(&moea_table_mutex, MA_OWNED); 2282 2283 /* 2284 * First try primary hash. 2285 */ 2286 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2287 if ((pt->pte_hi & PTE_VALID) == 0) { 2288 pvo_pt->pte_hi &= ~PTE_HID; 2289 moea_pte_set(pt, pvo_pt); 2290 return (i); 2291 } 2292 } 2293 2294 /* 2295 * Now try secondary hash. 2296 */ 2297 ptegidx ^= moea_pteg_mask; 2298 2299 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2300 if ((pt->pte_hi & PTE_VALID) == 0) { 2301 pvo_pt->pte_hi |= PTE_HID; 2302 moea_pte_set(pt, pvo_pt); 2303 return (i); 2304 } 2305 } 2306 2307 panic("moea_pte_insert: overflow"); 2308 return (-1); 2309 } 2310 2311 static boolean_t 2312 moea_query_bit(vm_page_t m, int ptebit) 2313 { 2314 struct pvo_entry *pvo; 2315 struct pte *pt; 2316 2317 if (moea_attr_fetch(m) & ptebit) 2318 return (TRUE); 2319 2320 vm_page_lock_queues(); 2321 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2322 2323 /* 2324 * See if we saved the bit off. If so, cache it and return 2325 * success. 2326 */ 2327 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2328 moea_attr_save(m, ptebit); 2329 vm_page_unlock_queues(); 2330 return (TRUE); 2331 } 2332 } 2333 2334 /* 2335 * No luck, now go through the hard part of looking at the PTEs 2336 * themselves. Sync so that any pending REF/CHG bits are flushed to 2337 * the PTEs. 2338 */ 2339 powerpc_sync(); 2340 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2341 2342 /* 2343 * See if this pvo has a valid PTE. if so, fetch the 2344 * REF/CHG bits from the valid PTE. If the appropriate 2345 * ptebit is set, cache it and return success. 2346 */ 2347 pt = moea_pvo_to_pte(pvo, -1); 2348 if (pt != NULL) { 2349 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2350 mtx_unlock(&moea_table_mutex); 2351 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2352 moea_attr_save(m, ptebit); 2353 vm_page_unlock_queues(); 2354 return (TRUE); 2355 } 2356 } 2357 } 2358 2359 vm_page_unlock_queues(); 2360 return (FALSE); 2361 } 2362 2363 static u_int 2364 moea_clear_bit(vm_page_t m, int ptebit) 2365 { 2366 u_int count; 2367 struct pvo_entry *pvo; 2368 struct pte *pt; 2369 2370 vm_page_lock_queues(); 2371 2372 /* 2373 * Clear the cached value. 2374 */ 2375 moea_attr_clear(m, ptebit); 2376 2377 /* 2378 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2379 * we can reset the right ones). note that since the pvo entries and 2380 * list heads are accessed via BAT0 and are never placed in the page 2381 * table, we don't have to worry about further accesses setting the 2382 * REF/CHG bits. 2383 */ 2384 powerpc_sync(); 2385 2386 /* 2387 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2388 * valid pte clear the ptebit from the valid pte. 2389 */ 2390 count = 0; 2391 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2392 pt = moea_pvo_to_pte(pvo, -1); 2393 if (pt != NULL) { 2394 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2395 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2396 count++; 2397 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2398 } 2399 mtx_unlock(&moea_table_mutex); 2400 } 2401 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2402 } 2403 2404 vm_page_unlock_queues(); 2405 return (count); 2406 } 2407 2408 /* 2409 * Return true if the physical range is encompassed by the battable[idx] 2410 */ 2411 static int 2412 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2413 { 2414 u_int prot; 2415 u_int32_t start; 2416 u_int32_t end; 2417 u_int32_t bat_ble; 2418 2419 /* 2420 * Return immediately if not a valid mapping 2421 */ 2422 if (!(battable[idx].batu & BAT_Vs)) 2423 return (EINVAL); 2424 2425 /* 2426 * The BAT entry must be cache-inhibited, guarded, and r/w 2427 * so it can function as an i/o page 2428 */ 2429 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2430 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2431 return (EPERM); 2432 2433 /* 2434 * The address should be within the BAT range. Assume that the 2435 * start address in the BAT has the correct alignment (thus 2436 * not requiring masking) 2437 */ 2438 start = battable[idx].batl & BAT_PBS; 2439 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2440 end = start | (bat_ble << 15) | 0x7fff; 2441 2442 if ((pa < start) || ((pa + size) > end)) 2443 return (ERANGE); 2444 2445 return (0); 2446 } 2447 2448 boolean_t 2449 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2450 { 2451 int i; 2452 2453 /* 2454 * This currently does not work for entries that 2455 * overlap 256M BAT segments. 2456 */ 2457 2458 for(i = 0; i < 16; i++) 2459 if (moea_bat_mapped(i, pa, size) == 0) 2460 return (0); 2461 2462 return (EFAULT); 2463 } 2464 2465 /* 2466 * Map a set of physical memory pages into the kernel virtual 2467 * address space. Return a pointer to where it is mapped. This 2468 * routine is intended to be used for mapping device memory, 2469 * NOT real memory. 2470 */ 2471 void * 2472 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2473 { 2474 2475 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2476 } 2477 2478 void * 2479 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2480 { 2481 vm_offset_t va, tmpva, ppa, offset; 2482 int i; 2483 2484 ppa = trunc_page(pa); 2485 offset = pa & PAGE_MASK; 2486 size = roundup(offset + size, PAGE_SIZE); 2487 2488 /* 2489 * If the physical address lies within a valid BAT table entry, 2490 * return the 1:1 mapping. This currently doesn't work 2491 * for regions that overlap 256M BAT segments. 2492 */ 2493 for (i = 0; i < 16; i++) { 2494 if (moea_bat_mapped(i, pa, size) == 0) 2495 return ((void *) pa); 2496 } 2497 2498 va = kmem_alloc_nofault(kernel_map, size); 2499 if (!va) 2500 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2501 2502 for (tmpva = va; size > 0;) { 2503 moea_kenter_attr(mmu, tmpva, ppa, ma); 2504 tlbie(tmpva); 2505 size -= PAGE_SIZE; 2506 tmpva += PAGE_SIZE; 2507 ppa += PAGE_SIZE; 2508 } 2509 2510 return ((void *)(va + offset)); 2511 } 2512 2513 void 2514 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2515 { 2516 vm_offset_t base, offset; 2517 2518 /* 2519 * If this is outside kernel virtual space, then it's a 2520 * battable entry and doesn't require unmapping 2521 */ 2522 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2523 base = trunc_page(va); 2524 offset = va & PAGE_MASK; 2525 size = roundup(offset + size, PAGE_SIZE); 2526 kmem_free(kernel_map, base, size); 2527 } 2528 } 2529 2530 static void 2531 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2532 { 2533 struct pvo_entry *pvo; 2534 vm_offset_t lim; 2535 vm_paddr_t pa; 2536 vm_size_t len; 2537 2538 PMAP_LOCK(pm); 2539 while (sz > 0) { 2540 lim = round_page(va); 2541 len = MIN(lim - va, sz); 2542 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2543 if (pvo != NULL) { 2544 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2545 (va & ADDR_POFF); 2546 moea_syncicache(pa, len); 2547 } 2548 va += len; 2549 sz -= len; 2550 } 2551 PMAP_UNLOCK(pm); 2552 } 2553