1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_pageout.h> 136 #include <vm/uma.h> 137 138 #include <machine/cpu.h> 139 #include <machine/platform.h> 140 #include <machine/bat.h> 141 #include <machine/frame.h> 142 #include <machine/md_var.h> 143 #include <machine/psl.h> 144 #include <machine/pte.h> 145 #include <machine/smp.h> 146 #include <machine/sr.h> 147 #include <machine/mmuvar.h> 148 #include <machine/trap.h> 149 150 #include "mmu_if.h" 151 152 #define MOEA_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 157 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 159 160 struct ofw_map { 161 vm_offset_t om_va; 162 vm_size_t om_len; 163 vm_offset_t om_pa; 164 u_int om_mode; 165 }; 166 167 extern unsigned char _etext[]; 168 extern unsigned char _end[]; 169 170 /* 171 * Map of physical memory regions. 172 */ 173 static struct mem_region *regions; 174 static struct mem_region *pregions; 175 static u_int phys_avail_count; 176 static int regions_sz, pregions_sz; 177 static struct ofw_map *translations; 178 179 /* 180 * Lock for the pteg and pvo tables. 181 */ 182 struct mtx moea_table_mutex; 183 struct mtx moea_vsid_mutex; 184 185 /* tlbie instruction synchronization */ 186 static struct mtx tlbie_mtx; 187 188 /* 189 * PTEG data. 190 */ 191 static struct pteg *moea_pteg_table; 192 u_int moea_pteg_count; 193 u_int moea_pteg_mask; 194 195 /* 196 * PVO data. 197 */ 198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 199 struct pvo_head moea_pvo_kunmanaged = 200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 201 202 static struct rwlock_padalign pvh_global_lock; 203 204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 206 207 #define BPVO_POOL_SIZE 32768 208 static struct pvo_entry *moea_bpvo_pool; 209 static int moea_bpvo_pool_index = 0; 210 211 #define VSID_NBPW (sizeof(u_int32_t) * 8) 212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 213 214 static boolean_t moea_initialized = FALSE; 215 216 /* 217 * Statistics. 218 */ 219 u_int moea_pte_valid = 0; 220 u_int moea_pte_overflow = 0; 221 u_int moea_pte_replacements = 0; 222 u_int moea_pvo_entries = 0; 223 u_int moea_pvo_enter_calls = 0; 224 u_int moea_pvo_remove_calls = 0; 225 u_int moea_pte_spills = 0; 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 227 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 229 &moea_pte_overflow, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 231 &moea_pte_replacements, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 233 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 235 &moea_pvo_enter_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 237 &moea_pvo_remove_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 239 &moea_pte_spills, 0, ""); 240 241 /* 242 * Allocate physical memory for use in moea_bootstrap. 243 */ 244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 245 246 /* 247 * PTE calls. 248 */ 249 static int moea_pte_insert(u_int, struct pte *); 250 251 /* 252 * PVO calls. 253 */ 254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 255 vm_offset_t, vm_paddr_t, u_int, int); 256 static void moea_pvo_remove(struct pvo_entry *, int); 257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 259 260 /* 261 * Utility routines. 262 */ 263 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 264 vm_prot_t, u_int, int8_t); 265 static void moea_syncicache(vm_paddr_t, vm_size_t); 266 static boolean_t moea_query_bit(vm_page_t, int); 267 static u_int moea_clear_bit(vm_page_t, int); 268 static void moea_kremove(mmu_t, vm_offset_t); 269 int moea_pte_spill(vm_offset_t); 270 271 /* 272 * Kernel MMU interface 273 */ 274 void moea_clear_modify(mmu_t, vm_page_t); 275 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 276 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 277 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 278 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 279 int8_t); 280 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 284 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 285 void moea_init(mmu_t); 286 boolean_t moea_is_modified(mmu_t, vm_page_t); 287 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288 boolean_t moea_is_referenced(mmu_t, vm_page_t); 289 int moea_ts_referenced(mmu_t, vm_page_t); 290 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 291 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 292 void moea_page_init(mmu_t, vm_page_t); 293 int moea_page_wired_mappings(mmu_t, vm_page_t); 294 void moea_pinit(mmu_t, pmap_t); 295 void moea_pinit0(mmu_t, pmap_t); 296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 298 void moea_qremove(mmu_t, vm_offset_t, int); 299 void moea_release(mmu_t, pmap_t); 300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(mmu_t, vm_page_t); 302 void moea_remove_write(mmu_t, vm_page_t); 303 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 304 void moea_zero_page(mmu_t, vm_page_t); 305 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 306 void moea_activate(mmu_t, struct thread *); 307 void moea_deactivate(mmu_t, struct thread *); 308 void moea_cpu_bootstrap(mmu_t, int); 309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 310 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 311 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 313 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 315 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 319 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 320 void moea_scan_init(mmu_t mmu); 321 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 322 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 323 static int moea_map_user_ptr(mmu_t mmu, pmap_t pm, 324 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 325 static int moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, 326 int *is_user, vm_offset_t *decoded_addr); 327 328 329 static mmu_method_t moea_methods[] = { 330 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 331 MMUMETHOD(mmu_copy_page, moea_copy_page), 332 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 333 MMUMETHOD(mmu_enter, moea_enter), 334 MMUMETHOD(mmu_enter_object, moea_enter_object), 335 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 336 MMUMETHOD(mmu_extract, moea_extract), 337 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 338 MMUMETHOD(mmu_init, moea_init), 339 MMUMETHOD(mmu_is_modified, moea_is_modified), 340 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 341 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 342 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 343 MMUMETHOD(mmu_map, moea_map), 344 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 345 MMUMETHOD(mmu_page_init, moea_page_init), 346 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 347 MMUMETHOD(mmu_pinit, moea_pinit), 348 MMUMETHOD(mmu_pinit0, moea_pinit0), 349 MMUMETHOD(mmu_protect, moea_protect), 350 MMUMETHOD(mmu_qenter, moea_qenter), 351 MMUMETHOD(mmu_qremove, moea_qremove), 352 MMUMETHOD(mmu_release, moea_release), 353 MMUMETHOD(mmu_remove, moea_remove), 354 MMUMETHOD(mmu_remove_all, moea_remove_all), 355 MMUMETHOD(mmu_remove_write, moea_remove_write), 356 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 357 MMUMETHOD(mmu_unwire, moea_unwire), 358 MMUMETHOD(mmu_zero_page, moea_zero_page), 359 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 360 MMUMETHOD(mmu_activate, moea_activate), 361 MMUMETHOD(mmu_deactivate, moea_deactivate), 362 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 363 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 364 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 365 366 /* Internal interfaces */ 367 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 368 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 369 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 370 MMUMETHOD(mmu_mapdev, moea_mapdev), 371 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 372 MMUMETHOD(mmu_kextract, moea_kextract), 373 MMUMETHOD(mmu_kenter, moea_kenter), 374 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 375 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 376 MMUMETHOD(mmu_scan_init, moea_scan_init), 377 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 378 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr), 379 MMUMETHOD(mmu_decode_kernel_ptr, moea_decode_kernel_ptr), 380 381 { 0, 0 } 382 }; 383 384 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 385 386 static __inline uint32_t 387 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 388 { 389 uint32_t pte_lo; 390 int i; 391 392 if (ma != VM_MEMATTR_DEFAULT) { 393 switch (ma) { 394 case VM_MEMATTR_UNCACHEABLE: 395 return (PTE_I | PTE_G); 396 case VM_MEMATTR_CACHEABLE: 397 return (PTE_M); 398 case VM_MEMATTR_WRITE_COMBINING: 399 case VM_MEMATTR_WRITE_BACK: 400 case VM_MEMATTR_PREFETCHABLE: 401 return (PTE_I); 402 case VM_MEMATTR_WRITE_THROUGH: 403 return (PTE_W | PTE_M); 404 } 405 } 406 407 /* 408 * Assume the page is cache inhibited and access is guarded unless 409 * it's in our available memory array. 410 */ 411 pte_lo = PTE_I | PTE_G; 412 for (i = 0; i < pregions_sz; i++) { 413 if ((pa >= pregions[i].mr_start) && 414 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 415 pte_lo = PTE_M; 416 break; 417 } 418 } 419 420 return pte_lo; 421 } 422 423 static void 424 tlbie(vm_offset_t va) 425 { 426 427 mtx_lock_spin(&tlbie_mtx); 428 __asm __volatile("ptesync"); 429 __asm __volatile("tlbie %0" :: "r"(va)); 430 __asm __volatile("eieio; tlbsync; ptesync"); 431 mtx_unlock_spin(&tlbie_mtx); 432 } 433 434 static void 435 tlbia(void) 436 { 437 vm_offset_t va; 438 439 for (va = 0; va < 0x00040000; va += 0x00001000) { 440 __asm __volatile("tlbie %0" :: "r"(va)); 441 powerpc_sync(); 442 } 443 __asm __volatile("tlbsync"); 444 powerpc_sync(); 445 } 446 447 static __inline int 448 va_to_sr(u_int *sr, vm_offset_t va) 449 { 450 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 451 } 452 453 static __inline u_int 454 va_to_pteg(u_int sr, vm_offset_t addr) 455 { 456 u_int hash; 457 458 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 459 ADDR_PIDX_SHFT); 460 return (hash & moea_pteg_mask); 461 } 462 463 static __inline struct pvo_head * 464 vm_page_to_pvoh(vm_page_t m) 465 { 466 467 return (&m->md.mdpg_pvoh); 468 } 469 470 static __inline void 471 moea_attr_clear(vm_page_t m, int ptebit) 472 { 473 474 rw_assert(&pvh_global_lock, RA_WLOCKED); 475 m->md.mdpg_attrs &= ~ptebit; 476 } 477 478 static __inline int 479 moea_attr_fetch(vm_page_t m) 480 { 481 482 return (m->md.mdpg_attrs); 483 } 484 485 static __inline void 486 moea_attr_save(vm_page_t m, int ptebit) 487 { 488 489 rw_assert(&pvh_global_lock, RA_WLOCKED); 490 m->md.mdpg_attrs |= ptebit; 491 } 492 493 static __inline int 494 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 495 { 496 if (pt->pte_hi == pvo_pt->pte_hi) 497 return (1); 498 499 return (0); 500 } 501 502 static __inline int 503 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 504 { 505 return (pt->pte_hi & ~PTE_VALID) == 506 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 507 ((va >> ADDR_API_SHFT) & PTE_API) | which); 508 } 509 510 static __inline void 511 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 512 { 513 514 mtx_assert(&moea_table_mutex, MA_OWNED); 515 516 /* 517 * Construct a PTE. Default to IMB initially. Valid bit only gets 518 * set when the real pte is set in memory. 519 * 520 * Note: Don't set the valid bit for correct operation of tlb update. 521 */ 522 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 523 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 524 pt->pte_lo = pte_lo; 525 } 526 527 static __inline void 528 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 529 { 530 531 mtx_assert(&moea_table_mutex, MA_OWNED); 532 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 533 } 534 535 static __inline void 536 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 537 { 538 539 mtx_assert(&moea_table_mutex, MA_OWNED); 540 541 /* 542 * As shown in Section 7.6.3.2.3 543 */ 544 pt->pte_lo &= ~ptebit; 545 tlbie(va); 546 } 547 548 static __inline void 549 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 550 { 551 552 mtx_assert(&moea_table_mutex, MA_OWNED); 553 pvo_pt->pte_hi |= PTE_VALID; 554 555 /* 556 * Update the PTE as defined in section 7.6.3.1. 557 * Note that the REF/CHG bits are from pvo_pt and thus should have 558 * been saved so this routine can restore them (if desired). 559 */ 560 pt->pte_lo = pvo_pt->pte_lo; 561 powerpc_sync(); 562 pt->pte_hi = pvo_pt->pte_hi; 563 powerpc_sync(); 564 moea_pte_valid++; 565 } 566 567 static __inline void 568 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 569 { 570 571 mtx_assert(&moea_table_mutex, MA_OWNED); 572 pvo_pt->pte_hi &= ~PTE_VALID; 573 574 /* 575 * Force the reg & chg bits back into the PTEs. 576 */ 577 powerpc_sync(); 578 579 /* 580 * Invalidate the pte. 581 */ 582 pt->pte_hi &= ~PTE_VALID; 583 584 tlbie(va); 585 586 /* 587 * Save the reg & chg bits. 588 */ 589 moea_pte_synch(pt, pvo_pt); 590 moea_pte_valid--; 591 } 592 593 static __inline void 594 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 595 { 596 597 /* 598 * Invalidate the PTE 599 */ 600 moea_pte_unset(pt, pvo_pt, va); 601 moea_pte_set(pt, pvo_pt); 602 } 603 604 /* 605 * Quick sort callout for comparing memory regions. 606 */ 607 static int om_cmp(const void *a, const void *b); 608 609 static int 610 om_cmp(const void *a, const void *b) 611 { 612 const struct ofw_map *mapa; 613 const struct ofw_map *mapb; 614 615 mapa = a; 616 mapb = b; 617 if (mapa->om_pa < mapb->om_pa) 618 return (-1); 619 else if (mapa->om_pa > mapb->om_pa) 620 return (1); 621 else 622 return (0); 623 } 624 625 void 626 moea_cpu_bootstrap(mmu_t mmup, int ap) 627 { 628 u_int sdr; 629 int i; 630 631 if (ap) { 632 powerpc_sync(); 633 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 634 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 635 isync(); 636 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 637 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 638 isync(); 639 } 640 641 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 642 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 643 isync(); 644 645 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 646 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 647 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 648 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 649 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 650 isync(); 651 652 for (i = 0; i < 16; i++) 653 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 654 powerpc_sync(); 655 656 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 657 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 658 isync(); 659 660 tlbia(); 661 } 662 663 void 664 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 665 { 666 ihandle_t mmui; 667 phandle_t chosen, mmu; 668 int sz; 669 int i, j; 670 vm_size_t size, physsz, hwphyssz; 671 vm_offset_t pa, va, off; 672 void *dpcpu; 673 register_t msr; 674 675 /* 676 * Set up BAT0 to map the lowest 256 MB area 677 */ 678 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 679 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 680 681 /* 682 * Map PCI memory space. 683 */ 684 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 686 687 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 689 690 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 692 693 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 694 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 695 696 /* 697 * Map obio devices. 698 */ 699 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 700 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 701 702 /* 703 * Use an IBAT and a DBAT to map the bottom segment of memory 704 * where we are. Turn off instruction relocation temporarily 705 * to prevent faults while reprogramming the IBAT. 706 */ 707 msr = mfmsr(); 708 mtmsr(msr & ~PSL_IR); 709 __asm (".balign 32; \n" 710 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 711 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 712 :: "r"(battable[0].batu), "r"(battable[0].batl)); 713 mtmsr(msr); 714 715 /* map pci space */ 716 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 717 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 718 isync(); 719 720 /* set global direct map flag */ 721 hw_direct_map = 1; 722 723 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 724 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 725 726 for (i = 0; i < pregions_sz; i++) { 727 vm_offset_t pa; 728 vm_offset_t end; 729 730 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 731 pregions[i].mr_start, 732 pregions[i].mr_start + pregions[i].mr_size, 733 pregions[i].mr_size); 734 /* 735 * Install entries into the BAT table to allow all 736 * of physmem to be convered by on-demand BAT entries. 737 * The loop will sometimes set the same battable element 738 * twice, but that's fine since they won't be used for 739 * a while yet. 740 */ 741 pa = pregions[i].mr_start & 0xf0000000; 742 end = pregions[i].mr_start + pregions[i].mr_size; 743 do { 744 u_int n = pa >> ADDR_SR_SHFT; 745 746 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 747 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 748 pa += SEGMENT_LENGTH; 749 } while (pa < end); 750 } 751 752 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 753 panic("moea_bootstrap: phys_avail too small"); 754 755 phys_avail_count = 0; 756 physsz = 0; 757 hwphyssz = 0; 758 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 759 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 760 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 761 regions[i].mr_start + regions[i].mr_size, 762 regions[i].mr_size); 763 if (hwphyssz != 0 && 764 (physsz + regions[i].mr_size) >= hwphyssz) { 765 if (physsz < hwphyssz) { 766 phys_avail[j] = regions[i].mr_start; 767 phys_avail[j + 1] = regions[i].mr_start + 768 hwphyssz - physsz; 769 physsz = hwphyssz; 770 phys_avail_count++; 771 } 772 break; 773 } 774 phys_avail[j] = regions[i].mr_start; 775 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 776 phys_avail_count++; 777 physsz += regions[i].mr_size; 778 } 779 780 /* Check for overlap with the kernel and exception vectors */ 781 for (j = 0; j < 2*phys_avail_count; j+=2) { 782 if (phys_avail[j] < EXC_LAST) 783 phys_avail[j] += EXC_LAST; 784 785 if (kernelstart >= phys_avail[j] && 786 kernelstart < phys_avail[j+1]) { 787 if (kernelend < phys_avail[j+1]) { 788 phys_avail[2*phys_avail_count] = 789 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 790 phys_avail[2*phys_avail_count + 1] = 791 phys_avail[j+1]; 792 phys_avail_count++; 793 } 794 795 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 796 } 797 798 if (kernelend >= phys_avail[j] && 799 kernelend < phys_avail[j+1]) { 800 if (kernelstart > phys_avail[j]) { 801 phys_avail[2*phys_avail_count] = phys_avail[j]; 802 phys_avail[2*phys_avail_count + 1] = 803 kernelstart & ~PAGE_MASK; 804 phys_avail_count++; 805 } 806 807 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 808 } 809 } 810 811 physmem = btoc(physsz); 812 813 /* 814 * Allocate PTEG table. 815 */ 816 #ifdef PTEGCOUNT 817 moea_pteg_count = PTEGCOUNT; 818 #else 819 moea_pteg_count = 0x1000; 820 821 while (moea_pteg_count < physmem) 822 moea_pteg_count <<= 1; 823 824 moea_pteg_count >>= 1; 825 #endif /* PTEGCOUNT */ 826 827 size = moea_pteg_count * sizeof(struct pteg); 828 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 829 size); 830 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 831 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 832 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 833 moea_pteg_mask = moea_pteg_count - 1; 834 835 /* 836 * Allocate pv/overflow lists. 837 */ 838 size = sizeof(struct pvo_head) * moea_pteg_count; 839 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 840 PAGE_SIZE); 841 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 842 for (i = 0; i < moea_pteg_count; i++) 843 LIST_INIT(&moea_pvo_table[i]); 844 845 /* 846 * Initialize the lock that synchronizes access to the pteg and pvo 847 * tables. 848 */ 849 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 850 MTX_RECURSE); 851 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 852 853 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 854 855 /* 856 * Initialise the unmanaged pvo pool. 857 */ 858 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 859 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 860 moea_bpvo_pool_index = 0; 861 862 /* 863 * Make sure kernel vsid is allocated as well as VSID 0. 864 */ 865 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 866 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 867 moea_vsid_bitmap[0] |= 1; 868 869 /* 870 * Initialize the kernel pmap (which is statically allocated). 871 */ 872 PMAP_LOCK_INIT(kernel_pmap); 873 for (i = 0; i < 16; i++) 874 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 875 CPU_FILL(&kernel_pmap->pm_active); 876 RB_INIT(&kernel_pmap->pmap_pvo); 877 878 /* 879 * Initialize the global pv list lock. 880 */ 881 rw_init(&pvh_global_lock, "pmap pv global"); 882 883 /* 884 * Set up the Open Firmware mappings 885 */ 886 chosen = OF_finddevice("/chosen"); 887 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 888 (mmu = OF_instance_to_package(mmui)) != -1 && 889 (sz = OF_getproplen(mmu, "translations")) != -1) { 890 translations = NULL; 891 for (i = 0; phys_avail[i] != 0; i += 2) { 892 if (phys_avail[i + 1] >= sz) { 893 translations = (struct ofw_map *)phys_avail[i]; 894 break; 895 } 896 } 897 if (translations == NULL) 898 panic("moea_bootstrap: no space to copy translations"); 899 bzero(translations, sz); 900 if (OF_getprop(mmu, "translations", translations, sz) == -1) 901 panic("moea_bootstrap: can't get ofw translations"); 902 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 903 sz /= sizeof(*translations); 904 qsort(translations, sz, sizeof (*translations), om_cmp); 905 for (i = 0; i < sz; i++) { 906 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 907 translations[i].om_pa, translations[i].om_va, 908 translations[i].om_len); 909 910 /* 911 * If the mapping is 1:1, let the RAM and device 912 * on-demand BAT tables take care of the translation. 913 */ 914 if (translations[i].om_va == translations[i].om_pa) 915 continue; 916 917 /* Enter the pages */ 918 for (off = 0; off < translations[i].om_len; 919 off += PAGE_SIZE) 920 moea_kenter(mmup, translations[i].om_va + off, 921 translations[i].om_pa + off); 922 } 923 } 924 925 /* 926 * Calculate the last available physical address. 927 */ 928 for (i = 0; phys_avail[i + 2] != 0; i += 2) 929 ; 930 Maxmem = powerpc_btop(phys_avail[i + 1]); 931 932 moea_cpu_bootstrap(mmup,0); 933 mtmsr(mfmsr() | PSL_DR | PSL_IR); 934 pmap_bootstrapped++; 935 936 /* 937 * Set the start and end of kva. 938 */ 939 virtual_avail = VM_MIN_KERNEL_ADDRESS; 940 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 941 942 /* 943 * Allocate a kernel stack with a guard page for thread0 and map it 944 * into the kernel page map. 945 */ 946 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 947 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 948 virtual_avail = va + kstack_pages * PAGE_SIZE; 949 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 950 thread0.td_kstack = va; 951 thread0.td_kstack_pages = kstack_pages; 952 for (i = 0; i < kstack_pages; i++) { 953 moea_kenter(mmup, va, pa); 954 pa += PAGE_SIZE; 955 va += PAGE_SIZE; 956 } 957 958 /* 959 * Allocate virtual address space for the message buffer. 960 */ 961 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 962 msgbufp = (struct msgbuf *)virtual_avail; 963 va = virtual_avail; 964 virtual_avail += round_page(msgbufsize); 965 while (va < virtual_avail) { 966 moea_kenter(mmup, va, pa); 967 pa += PAGE_SIZE; 968 va += PAGE_SIZE; 969 } 970 971 /* 972 * Allocate virtual address space for the dynamic percpu area. 973 */ 974 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 975 dpcpu = (void *)virtual_avail; 976 va = virtual_avail; 977 virtual_avail += DPCPU_SIZE; 978 while (va < virtual_avail) { 979 moea_kenter(mmup, va, pa); 980 pa += PAGE_SIZE; 981 va += PAGE_SIZE; 982 } 983 dpcpu_init(dpcpu, 0); 984 } 985 986 /* 987 * Activate a user pmap. The pmap must be activated before it's address 988 * space can be accessed in any way. 989 */ 990 void 991 moea_activate(mmu_t mmu, struct thread *td) 992 { 993 pmap_t pm, pmr; 994 995 /* 996 * Load all the data we need up front to encourage the compiler to 997 * not issue any loads while we have interrupts disabled below. 998 */ 999 pm = &td->td_proc->p_vmspace->vm_pmap; 1000 pmr = pm->pmap_phys; 1001 1002 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1003 PCPU_SET(curpmap, pmr); 1004 1005 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1006 } 1007 1008 void 1009 moea_deactivate(mmu_t mmu, struct thread *td) 1010 { 1011 pmap_t pm; 1012 1013 pm = &td->td_proc->p_vmspace->vm_pmap; 1014 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1015 PCPU_SET(curpmap, NULL); 1016 } 1017 1018 void 1019 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1020 { 1021 struct pvo_entry key, *pvo; 1022 1023 PMAP_LOCK(pm); 1024 key.pvo_vaddr = sva; 1025 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1026 pvo != NULL && PVO_VADDR(pvo) < eva; 1027 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1028 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1029 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1030 pvo->pvo_vaddr &= ~PVO_WIRED; 1031 pm->pm_stats.wired_count--; 1032 } 1033 PMAP_UNLOCK(pm); 1034 } 1035 1036 void 1037 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1038 { 1039 vm_offset_t dst; 1040 vm_offset_t src; 1041 1042 dst = VM_PAGE_TO_PHYS(mdst); 1043 src = VM_PAGE_TO_PHYS(msrc); 1044 1045 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1046 } 1047 1048 void 1049 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1050 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1051 { 1052 void *a_cp, *b_cp; 1053 vm_offset_t a_pg_offset, b_pg_offset; 1054 int cnt; 1055 1056 while (xfersize > 0) { 1057 a_pg_offset = a_offset & PAGE_MASK; 1058 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1059 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1060 a_pg_offset; 1061 b_pg_offset = b_offset & PAGE_MASK; 1062 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1063 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1064 b_pg_offset; 1065 bcopy(a_cp, b_cp, cnt); 1066 a_offset += cnt; 1067 b_offset += cnt; 1068 xfersize -= cnt; 1069 } 1070 } 1071 1072 /* 1073 * Zero a page of physical memory by temporarily mapping it into the tlb. 1074 */ 1075 void 1076 moea_zero_page(mmu_t mmu, vm_page_t m) 1077 { 1078 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1079 1080 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1081 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1082 } 1083 1084 void 1085 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1086 { 1087 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1088 void *va = (void *)(pa + off); 1089 1090 bzero(va, size); 1091 } 1092 1093 vm_offset_t 1094 moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1095 { 1096 1097 return (VM_PAGE_TO_PHYS(m)); 1098 } 1099 1100 void 1101 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1102 { 1103 } 1104 1105 /* 1106 * Map the given physical page at the specified virtual address in the 1107 * target pmap with the protection requested. If specified the page 1108 * will be wired down. 1109 */ 1110 int 1111 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1112 u_int flags, int8_t psind) 1113 { 1114 int error; 1115 1116 for (;;) { 1117 rw_wlock(&pvh_global_lock); 1118 PMAP_LOCK(pmap); 1119 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1120 rw_wunlock(&pvh_global_lock); 1121 PMAP_UNLOCK(pmap); 1122 if (error != ENOMEM) 1123 return (KERN_SUCCESS); 1124 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1125 return (KERN_RESOURCE_SHORTAGE); 1126 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1127 vm_wait(NULL); 1128 } 1129 } 1130 1131 /* 1132 * Map the given physical page at the specified virtual address in the 1133 * target pmap with the protection requested. If specified the page 1134 * will be wired down. 1135 * 1136 * The global pvh and pmap must be locked. 1137 */ 1138 static int 1139 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1140 u_int flags, int8_t psind __unused) 1141 { 1142 struct pvo_head *pvo_head; 1143 uma_zone_t zone; 1144 u_int pte_lo, pvo_flags; 1145 int error; 1146 1147 if (pmap_bootstrapped) 1148 rw_assert(&pvh_global_lock, RA_WLOCKED); 1149 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1150 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1151 VM_OBJECT_ASSERT_LOCKED(m->object); 1152 1153 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1154 pvo_head = &moea_pvo_kunmanaged; 1155 zone = moea_upvo_zone; 1156 pvo_flags = 0; 1157 } else { 1158 pvo_head = vm_page_to_pvoh(m); 1159 zone = moea_mpvo_zone; 1160 pvo_flags = PVO_MANAGED; 1161 } 1162 1163 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1164 1165 if (prot & VM_PROT_WRITE) { 1166 pte_lo |= PTE_BW; 1167 if (pmap_bootstrapped && 1168 (m->oflags & VPO_UNMANAGED) == 0) 1169 vm_page_aflag_set(m, PGA_WRITEABLE); 1170 } else 1171 pte_lo |= PTE_BR; 1172 1173 if ((flags & PMAP_ENTER_WIRED) != 0) 1174 pvo_flags |= PVO_WIRED; 1175 1176 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1177 pte_lo, pvo_flags); 1178 1179 /* 1180 * Flush the real page from the instruction cache. This has be done 1181 * for all user mappings to prevent information leakage via the 1182 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1183 * mapping for a page. 1184 */ 1185 if (pmap != kernel_pmap && error == ENOENT && 1186 (pte_lo & (PTE_I | PTE_G)) == 0) 1187 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1188 1189 return (error); 1190 } 1191 1192 /* 1193 * Maps a sequence of resident pages belonging to the same object. 1194 * The sequence begins with the given page m_start. This page is 1195 * mapped at the given virtual address start. Each subsequent page is 1196 * mapped at a virtual address that is offset from start by the same 1197 * amount as the page is offset from m_start within the object. The 1198 * last page in the sequence is the page with the largest offset from 1199 * m_start that can be mapped at a virtual address less than the given 1200 * virtual address end. Not every virtual page between start and end 1201 * is mapped; only those for which a resident page exists with the 1202 * corresponding offset from m_start are mapped. 1203 */ 1204 void 1205 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1206 vm_page_t m_start, vm_prot_t prot) 1207 { 1208 vm_page_t m; 1209 vm_pindex_t diff, psize; 1210 1211 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1212 1213 psize = atop(end - start); 1214 m = m_start; 1215 rw_wlock(&pvh_global_lock); 1216 PMAP_LOCK(pm); 1217 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1218 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1219 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1220 m = TAILQ_NEXT(m, listq); 1221 } 1222 rw_wunlock(&pvh_global_lock); 1223 PMAP_UNLOCK(pm); 1224 } 1225 1226 void 1227 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1228 vm_prot_t prot) 1229 { 1230 1231 rw_wlock(&pvh_global_lock); 1232 PMAP_LOCK(pm); 1233 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1234 0, 0); 1235 rw_wunlock(&pvh_global_lock); 1236 PMAP_UNLOCK(pm); 1237 } 1238 1239 vm_paddr_t 1240 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1241 { 1242 struct pvo_entry *pvo; 1243 vm_paddr_t pa; 1244 1245 PMAP_LOCK(pm); 1246 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1247 if (pvo == NULL) 1248 pa = 0; 1249 else 1250 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1251 PMAP_UNLOCK(pm); 1252 return (pa); 1253 } 1254 1255 /* 1256 * Atomically extract and hold the physical page with the given 1257 * pmap and virtual address pair if that mapping permits the given 1258 * protection. 1259 */ 1260 vm_page_t 1261 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1262 { 1263 struct pvo_entry *pvo; 1264 vm_page_t m; 1265 vm_paddr_t pa; 1266 1267 m = NULL; 1268 pa = 0; 1269 PMAP_LOCK(pmap); 1270 retry: 1271 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1272 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1273 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1274 (prot & VM_PROT_WRITE) == 0)) { 1275 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1276 goto retry; 1277 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1278 vm_page_hold(m); 1279 } 1280 PA_UNLOCK_COND(pa); 1281 PMAP_UNLOCK(pmap); 1282 return (m); 1283 } 1284 1285 void 1286 moea_init(mmu_t mmu) 1287 { 1288 1289 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1290 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1291 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1292 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1293 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1294 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1295 moea_initialized = TRUE; 1296 } 1297 1298 boolean_t 1299 moea_is_referenced(mmu_t mmu, vm_page_t m) 1300 { 1301 boolean_t rv; 1302 1303 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1304 ("moea_is_referenced: page %p is not managed", m)); 1305 rw_wlock(&pvh_global_lock); 1306 rv = moea_query_bit(m, PTE_REF); 1307 rw_wunlock(&pvh_global_lock); 1308 return (rv); 1309 } 1310 1311 boolean_t 1312 moea_is_modified(mmu_t mmu, vm_page_t m) 1313 { 1314 boolean_t rv; 1315 1316 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1317 ("moea_is_modified: page %p is not managed", m)); 1318 1319 /* 1320 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1321 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1322 * is clear, no PTEs can have PTE_CHG set. 1323 */ 1324 VM_OBJECT_ASSERT_WLOCKED(m->object); 1325 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1326 return (FALSE); 1327 rw_wlock(&pvh_global_lock); 1328 rv = moea_query_bit(m, PTE_CHG); 1329 rw_wunlock(&pvh_global_lock); 1330 return (rv); 1331 } 1332 1333 boolean_t 1334 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1335 { 1336 struct pvo_entry *pvo; 1337 boolean_t rv; 1338 1339 PMAP_LOCK(pmap); 1340 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1341 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1342 PMAP_UNLOCK(pmap); 1343 return (rv); 1344 } 1345 1346 void 1347 moea_clear_modify(mmu_t mmu, vm_page_t m) 1348 { 1349 1350 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1351 ("moea_clear_modify: page %p is not managed", m)); 1352 VM_OBJECT_ASSERT_WLOCKED(m->object); 1353 KASSERT(!vm_page_xbusied(m), 1354 ("moea_clear_modify: page %p is exclusive busy", m)); 1355 1356 /* 1357 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1358 * set. If the object containing the page is locked and the page is 1359 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1360 */ 1361 if ((m->aflags & PGA_WRITEABLE) == 0) 1362 return; 1363 rw_wlock(&pvh_global_lock); 1364 moea_clear_bit(m, PTE_CHG); 1365 rw_wunlock(&pvh_global_lock); 1366 } 1367 1368 /* 1369 * Clear the write and modified bits in each of the given page's mappings. 1370 */ 1371 void 1372 moea_remove_write(mmu_t mmu, vm_page_t m) 1373 { 1374 struct pvo_entry *pvo; 1375 struct pte *pt; 1376 pmap_t pmap; 1377 u_int lo; 1378 1379 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1380 ("moea_remove_write: page %p is not managed", m)); 1381 1382 /* 1383 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1384 * set by another thread while the object is locked. Thus, 1385 * if PGA_WRITEABLE is clear, no page table entries need updating. 1386 */ 1387 VM_OBJECT_ASSERT_WLOCKED(m->object); 1388 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1389 return; 1390 rw_wlock(&pvh_global_lock); 1391 lo = moea_attr_fetch(m); 1392 powerpc_sync(); 1393 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1394 pmap = pvo->pvo_pmap; 1395 PMAP_LOCK(pmap); 1396 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1397 pt = moea_pvo_to_pte(pvo, -1); 1398 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1399 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1400 if (pt != NULL) { 1401 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1402 lo |= pvo->pvo_pte.pte.pte_lo; 1403 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1404 moea_pte_change(pt, &pvo->pvo_pte.pte, 1405 pvo->pvo_vaddr); 1406 mtx_unlock(&moea_table_mutex); 1407 } 1408 } 1409 PMAP_UNLOCK(pmap); 1410 } 1411 if ((lo & PTE_CHG) != 0) { 1412 moea_attr_clear(m, PTE_CHG); 1413 vm_page_dirty(m); 1414 } 1415 vm_page_aflag_clear(m, PGA_WRITEABLE); 1416 rw_wunlock(&pvh_global_lock); 1417 } 1418 1419 /* 1420 * moea_ts_referenced: 1421 * 1422 * Return a count of reference bits for a page, clearing those bits. 1423 * It is not necessary for every reference bit to be cleared, but it 1424 * is necessary that 0 only be returned when there are truly no 1425 * reference bits set. 1426 * 1427 * XXX: The exact number of bits to check and clear is a matter that 1428 * should be tested and standardized at some point in the future for 1429 * optimal aging of shared pages. 1430 */ 1431 int 1432 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1433 { 1434 int count; 1435 1436 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1437 ("moea_ts_referenced: page %p is not managed", m)); 1438 rw_wlock(&pvh_global_lock); 1439 count = moea_clear_bit(m, PTE_REF); 1440 rw_wunlock(&pvh_global_lock); 1441 return (count); 1442 } 1443 1444 /* 1445 * Modify the WIMG settings of all mappings for a page. 1446 */ 1447 void 1448 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1449 { 1450 struct pvo_entry *pvo; 1451 struct pvo_head *pvo_head; 1452 struct pte *pt; 1453 pmap_t pmap; 1454 u_int lo; 1455 1456 if ((m->oflags & VPO_UNMANAGED) != 0) { 1457 m->md.mdpg_cache_attrs = ma; 1458 return; 1459 } 1460 1461 rw_wlock(&pvh_global_lock); 1462 pvo_head = vm_page_to_pvoh(m); 1463 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1464 1465 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1466 pmap = pvo->pvo_pmap; 1467 PMAP_LOCK(pmap); 1468 pt = moea_pvo_to_pte(pvo, -1); 1469 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1470 pvo->pvo_pte.pte.pte_lo |= lo; 1471 if (pt != NULL) { 1472 moea_pte_change(pt, &pvo->pvo_pte.pte, 1473 pvo->pvo_vaddr); 1474 if (pvo->pvo_pmap == kernel_pmap) 1475 isync(); 1476 } 1477 mtx_unlock(&moea_table_mutex); 1478 PMAP_UNLOCK(pmap); 1479 } 1480 m->md.mdpg_cache_attrs = ma; 1481 rw_wunlock(&pvh_global_lock); 1482 } 1483 1484 /* 1485 * Map a wired page into kernel virtual address space. 1486 */ 1487 void 1488 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1489 { 1490 1491 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1492 } 1493 1494 void 1495 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1496 { 1497 u_int pte_lo; 1498 int error; 1499 1500 #if 0 1501 if (va < VM_MIN_KERNEL_ADDRESS) 1502 panic("moea_kenter: attempt to enter non-kernel address %#x", 1503 va); 1504 #endif 1505 1506 pte_lo = moea_calc_wimg(pa, ma); 1507 1508 PMAP_LOCK(kernel_pmap); 1509 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1510 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1511 1512 if (error != 0 && error != ENOENT) 1513 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1514 pa, error); 1515 1516 PMAP_UNLOCK(kernel_pmap); 1517 } 1518 1519 /* 1520 * Extract the physical page address associated with the given kernel virtual 1521 * address. 1522 */ 1523 vm_paddr_t 1524 moea_kextract(mmu_t mmu, vm_offset_t va) 1525 { 1526 struct pvo_entry *pvo; 1527 vm_paddr_t pa; 1528 1529 /* 1530 * Allow direct mappings on 32-bit OEA 1531 */ 1532 if (va < VM_MIN_KERNEL_ADDRESS) { 1533 return (va); 1534 } 1535 1536 PMAP_LOCK(kernel_pmap); 1537 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1538 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1539 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1540 PMAP_UNLOCK(kernel_pmap); 1541 return (pa); 1542 } 1543 1544 /* 1545 * Remove a wired page from kernel virtual address space. 1546 */ 1547 void 1548 moea_kremove(mmu_t mmu, vm_offset_t va) 1549 { 1550 1551 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1552 } 1553 1554 /* 1555 * Provide a kernel pointer corresponding to a given userland pointer. 1556 * The returned pointer is valid until the next time this function is 1557 * called in this thread. This is used internally in copyin/copyout. 1558 */ 1559 int 1560 moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr, 1561 void **kaddr, size_t ulen, size_t *klen) 1562 { 1563 size_t l; 1564 register_t vsid; 1565 1566 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1567 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1568 if (l > ulen) 1569 l = ulen; 1570 if (klen) 1571 *klen = l; 1572 else if (l != ulen) 1573 return (EFAULT); 1574 1575 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1576 1577 /* Mark segment no-execute */ 1578 vsid |= SR_N; 1579 1580 /* If we have already set this VSID, we can just return */ 1581 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1582 return (0); 1583 1584 __asm __volatile("isync"); 1585 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1586 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1587 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1588 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1589 1590 return (0); 1591 } 1592 1593 /* 1594 * Figure out where a given kernel pointer (usually in a fault) points 1595 * to from the VM's perspective, potentially remapping into userland's 1596 * address space. 1597 */ 1598 static int 1599 moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user, 1600 vm_offset_t *decoded_addr) 1601 { 1602 vm_offset_t user_sr; 1603 1604 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1605 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1606 addr &= ADDR_PIDX | ADDR_POFF; 1607 addr |= user_sr << ADDR_SR_SHFT; 1608 *decoded_addr = addr; 1609 *is_user = 1; 1610 } else { 1611 *decoded_addr = addr; 1612 *is_user = 0; 1613 } 1614 1615 return (0); 1616 } 1617 1618 /* 1619 * Map a range of physical addresses into kernel virtual address space. 1620 * 1621 * The value passed in *virt is a suggested virtual address for the mapping. 1622 * Architectures which can support a direct-mapped physical to virtual region 1623 * can return the appropriate address within that region, leaving '*virt' 1624 * unchanged. We cannot and therefore do not; *virt is updated with the 1625 * first usable address after the mapped region. 1626 */ 1627 vm_offset_t 1628 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1629 vm_paddr_t pa_end, int prot) 1630 { 1631 vm_offset_t sva, va; 1632 1633 sva = *virt; 1634 va = sva; 1635 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1636 moea_kenter(mmu, va, pa_start); 1637 *virt = va; 1638 return (sva); 1639 } 1640 1641 /* 1642 * Returns true if the pmap's pv is one of the first 1643 * 16 pvs linked to from this page. This count may 1644 * be changed upwards or downwards in the future; it 1645 * is only necessary that true be returned for a small 1646 * subset of pmaps for proper page aging. 1647 */ 1648 boolean_t 1649 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1650 { 1651 int loops; 1652 struct pvo_entry *pvo; 1653 boolean_t rv; 1654 1655 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1656 ("moea_page_exists_quick: page %p is not managed", m)); 1657 loops = 0; 1658 rv = FALSE; 1659 rw_wlock(&pvh_global_lock); 1660 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1661 if (pvo->pvo_pmap == pmap) { 1662 rv = TRUE; 1663 break; 1664 } 1665 if (++loops >= 16) 1666 break; 1667 } 1668 rw_wunlock(&pvh_global_lock); 1669 return (rv); 1670 } 1671 1672 void 1673 moea_page_init(mmu_t mmu __unused, vm_page_t m) 1674 { 1675 1676 m->md.mdpg_attrs = 0; 1677 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1678 LIST_INIT(&m->md.mdpg_pvoh); 1679 } 1680 1681 /* 1682 * Return the number of managed mappings to the given physical page 1683 * that are wired. 1684 */ 1685 int 1686 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1687 { 1688 struct pvo_entry *pvo; 1689 int count; 1690 1691 count = 0; 1692 if ((m->oflags & VPO_UNMANAGED) != 0) 1693 return (count); 1694 rw_wlock(&pvh_global_lock); 1695 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1696 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1697 count++; 1698 rw_wunlock(&pvh_global_lock); 1699 return (count); 1700 } 1701 1702 static u_int moea_vsidcontext; 1703 1704 void 1705 moea_pinit(mmu_t mmu, pmap_t pmap) 1706 { 1707 int i, mask; 1708 u_int entropy; 1709 1710 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1711 RB_INIT(&pmap->pmap_pvo); 1712 1713 entropy = 0; 1714 __asm __volatile("mftb %0" : "=r"(entropy)); 1715 1716 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1717 == NULL) { 1718 pmap->pmap_phys = pmap; 1719 } 1720 1721 1722 mtx_lock(&moea_vsid_mutex); 1723 /* 1724 * Allocate some segment registers for this pmap. 1725 */ 1726 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1727 u_int hash, n; 1728 1729 /* 1730 * Create a new value by mutiplying by a prime and adding in 1731 * entropy from the timebase register. This is to make the 1732 * VSID more random so that the PT hash function collides 1733 * less often. (Note that the prime casues gcc to do shifts 1734 * instead of a multiply.) 1735 */ 1736 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1737 hash = moea_vsidcontext & (NPMAPS - 1); 1738 if (hash == 0) /* 0 is special, avoid it */ 1739 continue; 1740 n = hash >> 5; 1741 mask = 1 << (hash & (VSID_NBPW - 1)); 1742 hash = (moea_vsidcontext & 0xfffff); 1743 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1744 /* anything free in this bucket? */ 1745 if (moea_vsid_bitmap[n] == 0xffffffff) { 1746 entropy = (moea_vsidcontext >> 20); 1747 continue; 1748 } 1749 i = ffs(~moea_vsid_bitmap[n]) - 1; 1750 mask = 1 << i; 1751 hash &= rounddown2(0xfffff, VSID_NBPW); 1752 hash |= i; 1753 } 1754 KASSERT(!(moea_vsid_bitmap[n] & mask), 1755 ("Allocating in-use VSID group %#x\n", hash)); 1756 moea_vsid_bitmap[n] |= mask; 1757 for (i = 0; i < 16; i++) 1758 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1759 mtx_unlock(&moea_vsid_mutex); 1760 return; 1761 } 1762 1763 mtx_unlock(&moea_vsid_mutex); 1764 panic("moea_pinit: out of segments"); 1765 } 1766 1767 /* 1768 * Initialize the pmap associated with process 0. 1769 */ 1770 void 1771 moea_pinit0(mmu_t mmu, pmap_t pm) 1772 { 1773 1774 PMAP_LOCK_INIT(pm); 1775 moea_pinit(mmu, pm); 1776 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1777 } 1778 1779 /* 1780 * Set the physical protection on the specified range of this map as requested. 1781 */ 1782 void 1783 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1784 vm_prot_t prot) 1785 { 1786 struct pvo_entry *pvo, *tpvo, key; 1787 struct pte *pt; 1788 1789 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1790 ("moea_protect: non current pmap")); 1791 1792 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1793 moea_remove(mmu, pm, sva, eva); 1794 return; 1795 } 1796 1797 rw_wlock(&pvh_global_lock); 1798 PMAP_LOCK(pm); 1799 key.pvo_vaddr = sva; 1800 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1801 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1802 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1803 1804 /* 1805 * Grab the PTE pointer before we diddle with the cached PTE 1806 * copy. 1807 */ 1808 pt = moea_pvo_to_pte(pvo, -1); 1809 /* 1810 * Change the protection of the page. 1811 */ 1812 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1813 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1814 1815 /* 1816 * If the PVO is in the page table, update that pte as well. 1817 */ 1818 if (pt != NULL) { 1819 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1820 mtx_unlock(&moea_table_mutex); 1821 } 1822 } 1823 rw_wunlock(&pvh_global_lock); 1824 PMAP_UNLOCK(pm); 1825 } 1826 1827 /* 1828 * Map a list of wired pages into kernel virtual address space. This is 1829 * intended for temporary mappings which do not need page modification or 1830 * references recorded. Existing mappings in the region are overwritten. 1831 */ 1832 void 1833 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1834 { 1835 vm_offset_t va; 1836 1837 va = sva; 1838 while (count-- > 0) { 1839 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1840 va += PAGE_SIZE; 1841 m++; 1842 } 1843 } 1844 1845 /* 1846 * Remove page mappings from kernel virtual address space. Intended for 1847 * temporary mappings entered by moea_qenter. 1848 */ 1849 void 1850 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1851 { 1852 vm_offset_t va; 1853 1854 va = sva; 1855 while (count-- > 0) { 1856 moea_kremove(mmu, va); 1857 va += PAGE_SIZE; 1858 } 1859 } 1860 1861 void 1862 moea_release(mmu_t mmu, pmap_t pmap) 1863 { 1864 int idx, mask; 1865 1866 /* 1867 * Free segment register's VSID 1868 */ 1869 if (pmap->pm_sr[0] == 0) 1870 panic("moea_release"); 1871 1872 mtx_lock(&moea_vsid_mutex); 1873 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1874 mask = 1 << (idx % VSID_NBPW); 1875 idx /= VSID_NBPW; 1876 moea_vsid_bitmap[idx] &= ~mask; 1877 mtx_unlock(&moea_vsid_mutex); 1878 } 1879 1880 /* 1881 * Remove the given range of addresses from the specified map. 1882 */ 1883 void 1884 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1885 { 1886 struct pvo_entry *pvo, *tpvo, key; 1887 1888 rw_wlock(&pvh_global_lock); 1889 PMAP_LOCK(pm); 1890 key.pvo_vaddr = sva; 1891 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1892 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1893 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1894 moea_pvo_remove(pvo, -1); 1895 } 1896 PMAP_UNLOCK(pm); 1897 rw_wunlock(&pvh_global_lock); 1898 } 1899 1900 /* 1901 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1902 * will reflect changes in pte's back to the vm_page. 1903 */ 1904 void 1905 moea_remove_all(mmu_t mmu, vm_page_t m) 1906 { 1907 struct pvo_head *pvo_head; 1908 struct pvo_entry *pvo, *next_pvo; 1909 pmap_t pmap; 1910 1911 rw_wlock(&pvh_global_lock); 1912 pvo_head = vm_page_to_pvoh(m); 1913 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1914 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1915 1916 pmap = pvo->pvo_pmap; 1917 PMAP_LOCK(pmap); 1918 moea_pvo_remove(pvo, -1); 1919 PMAP_UNLOCK(pmap); 1920 } 1921 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1922 moea_attr_clear(m, PTE_CHG); 1923 vm_page_dirty(m); 1924 } 1925 vm_page_aflag_clear(m, PGA_WRITEABLE); 1926 rw_wunlock(&pvh_global_lock); 1927 } 1928 1929 /* 1930 * Allocate a physical page of memory directly from the phys_avail map. 1931 * Can only be called from moea_bootstrap before avail start and end are 1932 * calculated. 1933 */ 1934 static vm_offset_t 1935 moea_bootstrap_alloc(vm_size_t size, u_int align) 1936 { 1937 vm_offset_t s, e; 1938 int i, j; 1939 1940 size = round_page(size); 1941 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1942 if (align != 0) 1943 s = roundup2(phys_avail[i], align); 1944 else 1945 s = phys_avail[i]; 1946 e = s + size; 1947 1948 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1949 continue; 1950 1951 if (s == phys_avail[i]) { 1952 phys_avail[i] += size; 1953 } else if (e == phys_avail[i + 1]) { 1954 phys_avail[i + 1] -= size; 1955 } else { 1956 for (j = phys_avail_count * 2; j > i; j -= 2) { 1957 phys_avail[j] = phys_avail[j - 2]; 1958 phys_avail[j + 1] = phys_avail[j - 1]; 1959 } 1960 1961 phys_avail[i + 3] = phys_avail[i + 1]; 1962 phys_avail[i + 1] = s; 1963 phys_avail[i + 2] = e; 1964 phys_avail_count++; 1965 } 1966 1967 return (s); 1968 } 1969 panic("moea_bootstrap_alloc: could not allocate memory"); 1970 } 1971 1972 static void 1973 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1974 { 1975 __syncicache((void *)pa, len); 1976 } 1977 1978 static int 1979 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1980 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1981 { 1982 struct pvo_entry *pvo; 1983 u_int sr; 1984 int first; 1985 u_int ptegidx; 1986 int i; 1987 int bootstrap; 1988 1989 moea_pvo_enter_calls++; 1990 first = 0; 1991 bootstrap = 0; 1992 1993 /* 1994 * Compute the PTE Group index. 1995 */ 1996 va &= ~ADDR_POFF; 1997 sr = va_to_sr(pm->pm_sr, va); 1998 ptegidx = va_to_pteg(sr, va); 1999 2000 /* 2001 * Remove any existing mapping for this page. Reuse the pvo entry if 2002 * there is a mapping. 2003 */ 2004 mtx_lock(&moea_table_mutex); 2005 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2006 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2007 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 2008 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2009 (pte_lo & PTE_PP)) { 2010 /* 2011 * The PTE is not changing. Instead, this may 2012 * be a request to change the mapping's wired 2013 * attribute. 2014 */ 2015 mtx_unlock(&moea_table_mutex); 2016 if ((flags & PVO_WIRED) != 0 && 2017 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2018 pvo->pvo_vaddr |= PVO_WIRED; 2019 pm->pm_stats.wired_count++; 2020 } else if ((flags & PVO_WIRED) == 0 && 2021 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2022 pvo->pvo_vaddr &= ~PVO_WIRED; 2023 pm->pm_stats.wired_count--; 2024 } 2025 return (0); 2026 } 2027 moea_pvo_remove(pvo, -1); 2028 break; 2029 } 2030 } 2031 2032 /* 2033 * If we aren't overwriting a mapping, try to allocate. 2034 */ 2035 if (moea_initialized) { 2036 pvo = uma_zalloc(zone, M_NOWAIT); 2037 } else { 2038 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2039 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2040 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2041 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2042 } 2043 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2044 moea_bpvo_pool_index++; 2045 bootstrap = 1; 2046 } 2047 2048 if (pvo == NULL) { 2049 mtx_unlock(&moea_table_mutex); 2050 return (ENOMEM); 2051 } 2052 2053 moea_pvo_entries++; 2054 pvo->pvo_vaddr = va; 2055 pvo->pvo_pmap = pm; 2056 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2057 pvo->pvo_vaddr &= ~ADDR_POFF; 2058 if (flags & PVO_WIRED) 2059 pvo->pvo_vaddr |= PVO_WIRED; 2060 if (pvo_head != &moea_pvo_kunmanaged) 2061 pvo->pvo_vaddr |= PVO_MANAGED; 2062 if (bootstrap) 2063 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2064 2065 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2066 2067 /* 2068 * Add to pmap list 2069 */ 2070 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2071 2072 /* 2073 * Remember if the list was empty and therefore will be the first 2074 * item. 2075 */ 2076 if (LIST_FIRST(pvo_head) == NULL) 2077 first = 1; 2078 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2079 2080 if (pvo->pvo_vaddr & PVO_WIRED) 2081 pm->pm_stats.wired_count++; 2082 pm->pm_stats.resident_count++; 2083 2084 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2085 KASSERT(i < 8, ("Invalid PTE index")); 2086 if (i >= 0) { 2087 PVO_PTEGIDX_SET(pvo, i); 2088 } else { 2089 panic("moea_pvo_enter: overflow"); 2090 moea_pte_overflow++; 2091 } 2092 mtx_unlock(&moea_table_mutex); 2093 2094 return (first ? ENOENT : 0); 2095 } 2096 2097 static void 2098 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2099 { 2100 struct pte *pt; 2101 2102 /* 2103 * If there is an active pte entry, we need to deactivate it (and 2104 * save the ref & cfg bits). 2105 */ 2106 pt = moea_pvo_to_pte(pvo, pteidx); 2107 if (pt != NULL) { 2108 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2109 mtx_unlock(&moea_table_mutex); 2110 PVO_PTEGIDX_CLR(pvo); 2111 } else { 2112 moea_pte_overflow--; 2113 } 2114 2115 /* 2116 * Update our statistics. 2117 */ 2118 pvo->pvo_pmap->pm_stats.resident_count--; 2119 if (pvo->pvo_vaddr & PVO_WIRED) 2120 pvo->pvo_pmap->pm_stats.wired_count--; 2121 2122 /* 2123 * Save the REF/CHG bits into their cache if the page is managed. 2124 */ 2125 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2126 struct vm_page *pg; 2127 2128 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2129 if (pg != NULL) { 2130 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2131 (PTE_REF | PTE_CHG)); 2132 } 2133 } 2134 2135 /* 2136 * Remove this PVO from the PV and pmap lists. 2137 */ 2138 LIST_REMOVE(pvo, pvo_vlink); 2139 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2140 2141 /* 2142 * Remove this from the overflow list and return it to the pool 2143 * if we aren't going to reuse it. 2144 */ 2145 LIST_REMOVE(pvo, pvo_olink); 2146 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2147 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2148 moea_upvo_zone, pvo); 2149 moea_pvo_entries--; 2150 moea_pvo_remove_calls++; 2151 } 2152 2153 static __inline int 2154 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2155 { 2156 int pteidx; 2157 2158 /* 2159 * We can find the actual pte entry without searching by grabbing 2160 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2161 * noticing the HID bit. 2162 */ 2163 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2164 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2165 pteidx ^= moea_pteg_mask * 8; 2166 2167 return (pteidx); 2168 } 2169 2170 static struct pvo_entry * 2171 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2172 { 2173 struct pvo_entry *pvo; 2174 int ptegidx; 2175 u_int sr; 2176 2177 va &= ~ADDR_POFF; 2178 sr = va_to_sr(pm->pm_sr, va); 2179 ptegidx = va_to_pteg(sr, va); 2180 2181 mtx_lock(&moea_table_mutex); 2182 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2183 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2184 if (pteidx_p) 2185 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2186 break; 2187 } 2188 } 2189 mtx_unlock(&moea_table_mutex); 2190 2191 return (pvo); 2192 } 2193 2194 static struct pte * 2195 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2196 { 2197 struct pte *pt; 2198 2199 /* 2200 * If we haven't been supplied the ptegidx, calculate it. 2201 */ 2202 if (pteidx == -1) { 2203 int ptegidx; 2204 u_int sr; 2205 2206 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2207 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2208 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2209 } 2210 2211 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2212 mtx_lock(&moea_table_mutex); 2213 2214 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2215 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2216 "valid pte index", pvo); 2217 } 2218 2219 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2220 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2221 "pvo but no valid pte", pvo); 2222 } 2223 2224 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2225 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2226 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2227 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2228 } 2229 2230 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2231 != 0) { 2232 panic("moea_pvo_to_pte: pvo %p pte does not match " 2233 "pte %p in moea_pteg_table", pvo, pt); 2234 } 2235 2236 mtx_assert(&moea_table_mutex, MA_OWNED); 2237 return (pt); 2238 } 2239 2240 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2241 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2242 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2243 } 2244 2245 mtx_unlock(&moea_table_mutex); 2246 return (NULL); 2247 } 2248 2249 /* 2250 * XXX: THIS STUFF SHOULD BE IN pte.c? 2251 */ 2252 int 2253 moea_pte_spill(vm_offset_t addr) 2254 { 2255 struct pvo_entry *source_pvo, *victim_pvo; 2256 struct pvo_entry *pvo; 2257 int ptegidx, i, j; 2258 u_int sr; 2259 struct pteg *pteg; 2260 struct pte *pt; 2261 2262 moea_pte_spills++; 2263 2264 sr = mfsrin(addr); 2265 ptegidx = va_to_pteg(sr, addr); 2266 2267 /* 2268 * Have to substitute some entry. Use the primary hash for this. 2269 * Use low bits of timebase as random generator. 2270 */ 2271 pteg = &moea_pteg_table[ptegidx]; 2272 mtx_lock(&moea_table_mutex); 2273 __asm __volatile("mftb %0" : "=r"(i)); 2274 i &= 7; 2275 pt = &pteg->pt[i]; 2276 2277 source_pvo = NULL; 2278 victim_pvo = NULL; 2279 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2280 /* 2281 * We need to find a pvo entry for this address. 2282 */ 2283 if (source_pvo == NULL && 2284 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2285 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2286 /* 2287 * Now found an entry to be spilled into the pteg. 2288 * The PTE is now valid, so we know it's active. 2289 */ 2290 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2291 2292 if (j >= 0) { 2293 PVO_PTEGIDX_SET(pvo, j); 2294 moea_pte_overflow--; 2295 mtx_unlock(&moea_table_mutex); 2296 return (1); 2297 } 2298 2299 source_pvo = pvo; 2300 2301 if (victim_pvo != NULL) 2302 break; 2303 } 2304 2305 /* 2306 * We also need the pvo entry of the victim we are replacing 2307 * so save the R & C bits of the PTE. 2308 */ 2309 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2310 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2311 victim_pvo = pvo; 2312 if (source_pvo != NULL) 2313 break; 2314 } 2315 } 2316 2317 if (source_pvo == NULL) { 2318 mtx_unlock(&moea_table_mutex); 2319 return (0); 2320 } 2321 2322 if (victim_pvo == NULL) { 2323 if ((pt->pte_hi & PTE_HID) == 0) 2324 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2325 "entry", pt); 2326 2327 /* 2328 * If this is a secondary PTE, we need to search it's primary 2329 * pvo bucket for the matching PVO. 2330 */ 2331 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2332 pvo_olink) { 2333 /* 2334 * We also need the pvo entry of the victim we are 2335 * replacing so save the R & C bits of the PTE. 2336 */ 2337 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2338 victim_pvo = pvo; 2339 break; 2340 } 2341 } 2342 2343 if (victim_pvo == NULL) 2344 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2345 "entry", pt); 2346 } 2347 2348 /* 2349 * We are invalidating the TLB entry for the EA we are replacing even 2350 * though it's valid. If we don't, we lose any ref/chg bit changes 2351 * contained in the TLB entry. 2352 */ 2353 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2354 2355 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2356 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2357 2358 PVO_PTEGIDX_CLR(victim_pvo); 2359 PVO_PTEGIDX_SET(source_pvo, i); 2360 moea_pte_replacements++; 2361 2362 mtx_unlock(&moea_table_mutex); 2363 return (1); 2364 } 2365 2366 static __inline struct pvo_entry * 2367 moea_pte_spillable_ident(u_int ptegidx) 2368 { 2369 struct pte *pt; 2370 struct pvo_entry *pvo_walk, *pvo = NULL; 2371 2372 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2373 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2374 continue; 2375 2376 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2377 continue; 2378 2379 pt = moea_pvo_to_pte(pvo_walk, -1); 2380 2381 if (pt == NULL) 2382 continue; 2383 2384 pvo = pvo_walk; 2385 2386 mtx_unlock(&moea_table_mutex); 2387 if (!(pt->pte_lo & PTE_REF)) 2388 return (pvo_walk); 2389 } 2390 2391 return (pvo); 2392 } 2393 2394 static int 2395 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2396 { 2397 struct pte *pt; 2398 struct pvo_entry *victim_pvo; 2399 int i; 2400 int victim_idx; 2401 u_int pteg_bkpidx = ptegidx; 2402 2403 mtx_assert(&moea_table_mutex, MA_OWNED); 2404 2405 /* 2406 * First try primary hash. 2407 */ 2408 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2409 if ((pt->pte_hi & PTE_VALID) == 0) { 2410 pvo_pt->pte_hi &= ~PTE_HID; 2411 moea_pte_set(pt, pvo_pt); 2412 return (i); 2413 } 2414 } 2415 2416 /* 2417 * Now try secondary hash. 2418 */ 2419 ptegidx ^= moea_pteg_mask; 2420 2421 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2422 if ((pt->pte_hi & PTE_VALID) == 0) { 2423 pvo_pt->pte_hi |= PTE_HID; 2424 moea_pte_set(pt, pvo_pt); 2425 return (i); 2426 } 2427 } 2428 2429 /* Try again, but this time try to force a PTE out. */ 2430 ptegidx = pteg_bkpidx; 2431 2432 victim_pvo = moea_pte_spillable_ident(ptegidx); 2433 if (victim_pvo == NULL) { 2434 ptegidx ^= moea_pteg_mask; 2435 victim_pvo = moea_pte_spillable_ident(ptegidx); 2436 } 2437 2438 if (victim_pvo == NULL) { 2439 panic("moea_pte_insert: overflow"); 2440 return (-1); 2441 } 2442 2443 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2444 2445 if (pteg_bkpidx == ptegidx) 2446 pvo_pt->pte_hi &= ~PTE_HID; 2447 else 2448 pvo_pt->pte_hi |= PTE_HID; 2449 2450 /* 2451 * Synchronize the sacrifice PTE with its PVO, then mark both 2452 * invalid. The PVO will be reused when/if the VM system comes 2453 * here after a fault. 2454 */ 2455 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2456 2457 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2458 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2459 2460 /* 2461 * Set the new PTE. 2462 */ 2463 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2464 PVO_PTEGIDX_CLR(victim_pvo); 2465 moea_pte_overflow++; 2466 moea_pte_set(pt, pvo_pt); 2467 2468 return (victim_idx & 7); 2469 } 2470 2471 static boolean_t 2472 moea_query_bit(vm_page_t m, int ptebit) 2473 { 2474 struct pvo_entry *pvo; 2475 struct pte *pt; 2476 2477 rw_assert(&pvh_global_lock, RA_WLOCKED); 2478 if (moea_attr_fetch(m) & ptebit) 2479 return (TRUE); 2480 2481 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2482 2483 /* 2484 * See if we saved the bit off. If so, cache it and return 2485 * success. 2486 */ 2487 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2488 moea_attr_save(m, ptebit); 2489 return (TRUE); 2490 } 2491 } 2492 2493 /* 2494 * No luck, now go through the hard part of looking at the PTEs 2495 * themselves. Sync so that any pending REF/CHG bits are flushed to 2496 * the PTEs. 2497 */ 2498 powerpc_sync(); 2499 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2500 2501 /* 2502 * See if this pvo has a valid PTE. if so, fetch the 2503 * REF/CHG bits from the valid PTE. If the appropriate 2504 * ptebit is set, cache it and return success. 2505 */ 2506 pt = moea_pvo_to_pte(pvo, -1); 2507 if (pt != NULL) { 2508 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2509 mtx_unlock(&moea_table_mutex); 2510 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2511 moea_attr_save(m, ptebit); 2512 return (TRUE); 2513 } 2514 } 2515 } 2516 2517 return (FALSE); 2518 } 2519 2520 static u_int 2521 moea_clear_bit(vm_page_t m, int ptebit) 2522 { 2523 u_int count; 2524 struct pvo_entry *pvo; 2525 struct pte *pt; 2526 2527 rw_assert(&pvh_global_lock, RA_WLOCKED); 2528 2529 /* 2530 * Clear the cached value. 2531 */ 2532 moea_attr_clear(m, ptebit); 2533 2534 /* 2535 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2536 * we can reset the right ones). note that since the pvo entries and 2537 * list heads are accessed via BAT0 and are never placed in the page 2538 * table, we don't have to worry about further accesses setting the 2539 * REF/CHG bits. 2540 */ 2541 powerpc_sync(); 2542 2543 /* 2544 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2545 * valid pte clear the ptebit from the valid pte. 2546 */ 2547 count = 0; 2548 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2549 pt = moea_pvo_to_pte(pvo, -1); 2550 if (pt != NULL) { 2551 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2552 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2553 count++; 2554 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2555 } 2556 mtx_unlock(&moea_table_mutex); 2557 } 2558 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2559 } 2560 2561 return (count); 2562 } 2563 2564 /* 2565 * Return true if the physical range is encompassed by the battable[idx] 2566 */ 2567 static int 2568 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2569 { 2570 u_int prot; 2571 u_int32_t start; 2572 u_int32_t end; 2573 u_int32_t bat_ble; 2574 2575 /* 2576 * Return immediately if not a valid mapping 2577 */ 2578 if (!(battable[idx].batu & BAT_Vs)) 2579 return (EINVAL); 2580 2581 /* 2582 * The BAT entry must be cache-inhibited, guarded, and r/w 2583 * so it can function as an i/o page 2584 */ 2585 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2586 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2587 return (EPERM); 2588 2589 /* 2590 * The address should be within the BAT range. Assume that the 2591 * start address in the BAT has the correct alignment (thus 2592 * not requiring masking) 2593 */ 2594 start = battable[idx].batl & BAT_PBS; 2595 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2596 end = start | (bat_ble << 15) | 0x7fff; 2597 2598 if ((pa < start) || ((pa + size) > end)) 2599 return (ERANGE); 2600 2601 return (0); 2602 } 2603 2604 boolean_t 2605 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2606 { 2607 int i; 2608 2609 /* 2610 * This currently does not work for entries that 2611 * overlap 256M BAT segments. 2612 */ 2613 2614 for(i = 0; i < 16; i++) 2615 if (moea_bat_mapped(i, pa, size) == 0) 2616 return (0); 2617 2618 return (EFAULT); 2619 } 2620 2621 /* 2622 * Map a set of physical memory pages into the kernel virtual 2623 * address space. Return a pointer to where it is mapped. This 2624 * routine is intended to be used for mapping device memory, 2625 * NOT real memory. 2626 */ 2627 void * 2628 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2629 { 2630 2631 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2632 } 2633 2634 void * 2635 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2636 { 2637 vm_offset_t va, tmpva, ppa, offset; 2638 int i; 2639 2640 ppa = trunc_page(pa); 2641 offset = pa & PAGE_MASK; 2642 size = roundup(offset + size, PAGE_SIZE); 2643 2644 /* 2645 * If the physical address lies within a valid BAT table entry, 2646 * return the 1:1 mapping. This currently doesn't work 2647 * for regions that overlap 256M BAT segments. 2648 */ 2649 for (i = 0; i < 16; i++) { 2650 if (moea_bat_mapped(i, pa, size) == 0) 2651 return ((void *) pa); 2652 } 2653 2654 va = kva_alloc(size); 2655 if (!va) 2656 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2657 2658 for (tmpva = va; size > 0;) { 2659 moea_kenter_attr(mmu, tmpva, ppa, ma); 2660 tlbie(tmpva); 2661 size -= PAGE_SIZE; 2662 tmpva += PAGE_SIZE; 2663 ppa += PAGE_SIZE; 2664 } 2665 2666 return ((void *)(va + offset)); 2667 } 2668 2669 void 2670 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2671 { 2672 vm_offset_t base, offset; 2673 2674 /* 2675 * If this is outside kernel virtual space, then it's a 2676 * battable entry and doesn't require unmapping 2677 */ 2678 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2679 base = trunc_page(va); 2680 offset = va & PAGE_MASK; 2681 size = roundup(offset + size, PAGE_SIZE); 2682 kva_free(base, size); 2683 } 2684 } 2685 2686 static void 2687 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2688 { 2689 struct pvo_entry *pvo; 2690 vm_offset_t lim; 2691 vm_paddr_t pa; 2692 vm_size_t len; 2693 2694 PMAP_LOCK(pm); 2695 while (sz > 0) { 2696 lim = round_page(va); 2697 len = MIN(lim - va, sz); 2698 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2699 if (pvo != NULL) { 2700 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2701 (va & ADDR_POFF); 2702 moea_syncicache(pa, len); 2703 } 2704 va += len; 2705 sz -= len; 2706 } 2707 PMAP_UNLOCK(pm); 2708 } 2709 2710 void 2711 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2712 { 2713 2714 *va = (void *)pa; 2715 } 2716 2717 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2718 2719 void 2720 moea_scan_init(mmu_t mmu) 2721 { 2722 struct pvo_entry *pvo; 2723 vm_offset_t va; 2724 int i; 2725 2726 if (!do_minidump) { 2727 /* Initialize phys. segments for dumpsys(). */ 2728 memset(&dump_map, 0, sizeof(dump_map)); 2729 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2730 for (i = 0; i < pregions_sz; i++) { 2731 dump_map[i].pa_start = pregions[i].mr_start; 2732 dump_map[i].pa_size = pregions[i].mr_size; 2733 } 2734 return; 2735 } 2736 2737 /* Virtual segments for minidumps: */ 2738 memset(&dump_map, 0, sizeof(dump_map)); 2739 2740 /* 1st: kernel .data and .bss. */ 2741 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2742 dump_map[0].pa_size = 2743 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2744 2745 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2746 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2747 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2748 2749 /* 3rd: kernel VM. */ 2750 va = dump_map[1].pa_start + dump_map[1].pa_size; 2751 /* Find start of next chunk (from va). */ 2752 while (va < virtual_end) { 2753 /* Don't dump the buffer cache. */ 2754 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2755 va = kmi.buffer_eva; 2756 continue; 2757 } 2758 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2759 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2760 break; 2761 va += PAGE_SIZE; 2762 } 2763 if (va < virtual_end) { 2764 dump_map[2].pa_start = va; 2765 va += PAGE_SIZE; 2766 /* Find last page in chunk. */ 2767 while (va < virtual_end) { 2768 /* Don't run into the buffer cache. */ 2769 if (va == kmi.buffer_sva) 2770 break; 2771 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2772 NULL); 2773 if (pvo == NULL || 2774 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2775 break; 2776 va += PAGE_SIZE; 2777 } 2778 dump_map[2].pa_size = va - dump_map[2].pa_start; 2779 } 2780 } 2781