1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/queue.h> 122 #include <sys/cpuset.h> 123 #include <sys/ktr.h> 124 #include <sys/lock.h> 125 #include <sys/msgbuf.h> 126 #include <sys/mutex.h> 127 #include <sys/proc.h> 128 #include <sys/sched.h> 129 #include <sys/sysctl.h> 130 #include <sys/systm.h> 131 #include <sys/vmmeter.h> 132 133 #include <dev/ofw/openfirm.h> 134 135 #include <vm/vm.h> 136 #include <vm/vm_param.h> 137 #include <vm/vm_kern.h> 138 #include <vm/vm_page.h> 139 #include <vm/vm_map.h> 140 #include <vm/vm_object.h> 141 #include <vm/vm_extern.h> 142 #include <vm/vm_pageout.h> 143 #include <vm/vm_pager.h> 144 #include <vm/uma.h> 145 146 #include <machine/cpu.h> 147 #include <machine/platform.h> 148 #include <machine/bat.h> 149 #include <machine/frame.h> 150 #include <machine/md_var.h> 151 #include <machine/psl.h> 152 #include <machine/pte.h> 153 #include <machine/smp.h> 154 #include <machine/sr.h> 155 #include <machine/mmuvar.h> 156 157 #include "mmu_if.h" 158 159 #define MOEA_DEBUG 160 161 #define TODO panic("%s: not implemented", __func__); 162 163 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 165 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 166 167 struct ofw_map { 168 vm_offset_t om_va; 169 vm_size_t om_len; 170 vm_offset_t om_pa; 171 u_int om_mode; 172 }; 173 174 /* 175 * Map of physical memory regions. 176 */ 177 static struct mem_region *regions; 178 static struct mem_region *pregions; 179 static u_int phys_avail_count; 180 static int regions_sz, pregions_sz; 181 static struct ofw_map *translations; 182 183 /* 184 * Lock for the pteg and pvo tables. 185 */ 186 struct mtx moea_table_mutex; 187 struct mtx moea_vsid_mutex; 188 189 /* tlbie instruction synchronization */ 190 static struct mtx tlbie_mtx; 191 192 /* 193 * PTEG data. 194 */ 195 static struct pteg *moea_pteg_table; 196 u_int moea_pteg_count; 197 u_int moea_pteg_mask; 198 199 /* 200 * PVO data. 201 */ 202 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 203 struct pvo_head moea_pvo_kunmanaged = 204 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 205 206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 208 209 #define BPVO_POOL_SIZE 32768 210 static struct pvo_entry *moea_bpvo_pool; 211 static int moea_bpvo_pool_index = 0; 212 213 #define VSID_NBPW (sizeof(u_int32_t) * 8) 214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 215 216 static boolean_t moea_initialized = FALSE; 217 218 /* 219 * Statistics. 220 */ 221 u_int moea_pte_valid = 0; 222 u_int moea_pte_overflow = 0; 223 u_int moea_pte_replacements = 0; 224 u_int moea_pvo_entries = 0; 225 u_int moea_pvo_enter_calls = 0; 226 u_int moea_pvo_remove_calls = 0; 227 u_int moea_pte_spills = 0; 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 229 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 231 &moea_pte_overflow, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 233 &moea_pte_replacements, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 235 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 237 &moea_pvo_enter_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 239 &moea_pvo_remove_calls, 0, ""); 240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 241 &moea_pte_spills, 0, ""); 242 243 /* 244 * Allocate physical memory for use in moea_bootstrap. 245 */ 246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 247 248 /* 249 * PTE calls. 250 */ 251 static int moea_pte_insert(u_int, struct pte *); 252 253 /* 254 * PVO calls. 255 */ 256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 257 vm_offset_t, vm_offset_t, u_int, int); 258 static void moea_pvo_remove(struct pvo_entry *, int); 259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 261 262 /* 263 * Utility routines. 264 */ 265 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 266 vm_prot_t, boolean_t); 267 static void moea_syncicache(vm_offset_t, vm_size_t); 268 static boolean_t moea_query_bit(vm_page_t, int); 269 static u_int moea_clear_bit(vm_page_t, int); 270 static void moea_kremove(mmu_t, vm_offset_t); 271 int moea_pte_spill(vm_offset_t); 272 273 /* 274 * Kernel MMU interface 275 */ 276 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 277 void moea_clear_modify(mmu_t, vm_page_t); 278 void moea_clear_reference(mmu_t, vm_page_t); 279 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 280 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 281 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 282 vm_prot_t); 283 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 284 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 285 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 286 void moea_init(mmu_t); 287 boolean_t moea_is_modified(mmu_t, vm_page_t); 288 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 289 boolean_t moea_is_referenced(mmu_t, vm_page_t); 290 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 291 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 292 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 293 int moea_page_wired_mappings(mmu_t, vm_page_t); 294 void moea_pinit(mmu_t, pmap_t); 295 void moea_pinit0(mmu_t, pmap_t); 296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 298 void moea_qremove(mmu_t, vm_offset_t, int); 299 void moea_release(mmu_t, pmap_t); 300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(mmu_t, vm_page_t); 302 void moea_remove_write(mmu_t, vm_page_t); 303 void moea_zero_page(mmu_t, vm_page_t); 304 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 305 void moea_zero_page_idle(mmu_t, vm_page_t); 306 void moea_activate(mmu_t, struct thread *); 307 void moea_deactivate(mmu_t, struct thread *); 308 void moea_cpu_bootstrap(mmu_t, int); 309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 310 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 311 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 313 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 315 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 319 320 static mmu_method_t moea_methods[] = { 321 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 322 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 323 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 324 MMUMETHOD(mmu_copy_page, moea_copy_page), 325 MMUMETHOD(mmu_enter, moea_enter), 326 MMUMETHOD(mmu_enter_object, moea_enter_object), 327 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 328 MMUMETHOD(mmu_extract, moea_extract), 329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 330 MMUMETHOD(mmu_init, moea_init), 331 MMUMETHOD(mmu_is_modified, moea_is_modified), 332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 333 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 335 MMUMETHOD(mmu_map, moea_map), 336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 338 MMUMETHOD(mmu_pinit, moea_pinit), 339 MMUMETHOD(mmu_pinit0, moea_pinit0), 340 MMUMETHOD(mmu_protect, moea_protect), 341 MMUMETHOD(mmu_qenter, moea_qenter), 342 MMUMETHOD(mmu_qremove, moea_qremove), 343 MMUMETHOD(mmu_release, moea_release), 344 MMUMETHOD(mmu_remove, moea_remove), 345 MMUMETHOD(mmu_remove_all, moea_remove_all), 346 MMUMETHOD(mmu_remove_write, moea_remove_write), 347 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 348 MMUMETHOD(mmu_zero_page, moea_zero_page), 349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 351 MMUMETHOD(mmu_activate, moea_activate), 352 MMUMETHOD(mmu_deactivate, moea_deactivate), 353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 354 355 /* Internal interfaces */ 356 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 359 MMUMETHOD(mmu_mapdev, moea_mapdev), 360 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 361 MMUMETHOD(mmu_kextract, moea_kextract), 362 MMUMETHOD(mmu_kenter, moea_kenter), 363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 365 366 { 0, 0 } 367 }; 368 369 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 370 371 static __inline uint32_t 372 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 373 { 374 uint32_t pte_lo; 375 int i; 376 377 if (ma != VM_MEMATTR_DEFAULT) { 378 switch (ma) { 379 case VM_MEMATTR_UNCACHEABLE: 380 return (PTE_I | PTE_G); 381 case VM_MEMATTR_WRITE_COMBINING: 382 case VM_MEMATTR_WRITE_BACK: 383 case VM_MEMATTR_PREFETCHABLE: 384 return (PTE_I); 385 case VM_MEMATTR_WRITE_THROUGH: 386 return (PTE_W | PTE_M); 387 } 388 } 389 390 /* 391 * Assume the page is cache inhibited and access is guarded unless 392 * it's in our available memory array. 393 */ 394 pte_lo = PTE_I | PTE_G; 395 for (i = 0; i < pregions_sz; i++) { 396 if ((pa >= pregions[i].mr_start) && 397 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 398 pte_lo = PTE_M; 399 break; 400 } 401 } 402 403 return pte_lo; 404 } 405 406 static void 407 tlbie(vm_offset_t va) 408 { 409 410 mtx_lock_spin(&tlbie_mtx); 411 __asm __volatile("ptesync"); 412 __asm __volatile("tlbie %0" :: "r"(va)); 413 __asm __volatile("eieio; tlbsync; ptesync"); 414 mtx_unlock_spin(&tlbie_mtx); 415 } 416 417 static void 418 tlbia(void) 419 { 420 vm_offset_t va; 421 422 for (va = 0; va < 0x00040000; va += 0x00001000) { 423 __asm __volatile("tlbie %0" :: "r"(va)); 424 powerpc_sync(); 425 } 426 __asm __volatile("tlbsync"); 427 powerpc_sync(); 428 } 429 430 static __inline int 431 va_to_sr(u_int *sr, vm_offset_t va) 432 { 433 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 434 } 435 436 static __inline u_int 437 va_to_pteg(u_int sr, vm_offset_t addr) 438 { 439 u_int hash; 440 441 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 442 ADDR_PIDX_SHFT); 443 return (hash & moea_pteg_mask); 444 } 445 446 static __inline struct pvo_head * 447 vm_page_to_pvoh(vm_page_t m) 448 { 449 450 return (&m->md.mdpg_pvoh); 451 } 452 453 static __inline void 454 moea_attr_clear(vm_page_t m, int ptebit) 455 { 456 457 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 458 m->md.mdpg_attrs &= ~ptebit; 459 } 460 461 static __inline int 462 moea_attr_fetch(vm_page_t m) 463 { 464 465 return (m->md.mdpg_attrs); 466 } 467 468 static __inline void 469 moea_attr_save(vm_page_t m, int ptebit) 470 { 471 472 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 473 m->md.mdpg_attrs |= ptebit; 474 } 475 476 static __inline int 477 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 478 { 479 if (pt->pte_hi == pvo_pt->pte_hi) 480 return (1); 481 482 return (0); 483 } 484 485 static __inline int 486 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 487 { 488 return (pt->pte_hi & ~PTE_VALID) == 489 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 490 ((va >> ADDR_API_SHFT) & PTE_API) | which); 491 } 492 493 static __inline void 494 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 495 { 496 497 mtx_assert(&moea_table_mutex, MA_OWNED); 498 499 /* 500 * Construct a PTE. Default to IMB initially. Valid bit only gets 501 * set when the real pte is set in memory. 502 * 503 * Note: Don't set the valid bit for correct operation of tlb update. 504 */ 505 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 506 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 507 pt->pte_lo = pte_lo; 508 } 509 510 static __inline void 511 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 512 { 513 514 mtx_assert(&moea_table_mutex, MA_OWNED); 515 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 516 } 517 518 static __inline void 519 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 520 { 521 522 mtx_assert(&moea_table_mutex, MA_OWNED); 523 524 /* 525 * As shown in Section 7.6.3.2.3 526 */ 527 pt->pte_lo &= ~ptebit; 528 tlbie(va); 529 } 530 531 static __inline void 532 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 533 { 534 535 mtx_assert(&moea_table_mutex, MA_OWNED); 536 pvo_pt->pte_hi |= PTE_VALID; 537 538 /* 539 * Update the PTE as defined in section 7.6.3.1. 540 * Note that the REF/CHG bits are from pvo_pt and thus should havce 541 * been saved so this routine can restore them (if desired). 542 */ 543 pt->pte_lo = pvo_pt->pte_lo; 544 powerpc_sync(); 545 pt->pte_hi = pvo_pt->pte_hi; 546 powerpc_sync(); 547 moea_pte_valid++; 548 } 549 550 static __inline void 551 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 552 { 553 554 mtx_assert(&moea_table_mutex, MA_OWNED); 555 pvo_pt->pte_hi &= ~PTE_VALID; 556 557 /* 558 * Force the reg & chg bits back into the PTEs. 559 */ 560 powerpc_sync(); 561 562 /* 563 * Invalidate the pte. 564 */ 565 pt->pte_hi &= ~PTE_VALID; 566 567 tlbie(va); 568 569 /* 570 * Save the reg & chg bits. 571 */ 572 moea_pte_synch(pt, pvo_pt); 573 moea_pte_valid--; 574 } 575 576 static __inline void 577 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 578 { 579 580 /* 581 * Invalidate the PTE 582 */ 583 moea_pte_unset(pt, pvo_pt, va); 584 moea_pte_set(pt, pvo_pt); 585 } 586 587 /* 588 * Quick sort callout for comparing memory regions. 589 */ 590 static int om_cmp(const void *a, const void *b); 591 592 static int 593 om_cmp(const void *a, const void *b) 594 { 595 const struct ofw_map *mapa; 596 const struct ofw_map *mapb; 597 598 mapa = a; 599 mapb = b; 600 if (mapa->om_pa < mapb->om_pa) 601 return (-1); 602 else if (mapa->om_pa > mapb->om_pa) 603 return (1); 604 else 605 return (0); 606 } 607 608 void 609 moea_cpu_bootstrap(mmu_t mmup, int ap) 610 { 611 u_int sdr; 612 int i; 613 614 if (ap) { 615 powerpc_sync(); 616 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 617 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 618 isync(); 619 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 620 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 621 isync(); 622 } 623 624 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 625 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 626 isync(); 627 628 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 629 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 630 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 631 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 632 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 633 isync(); 634 635 for (i = 0; i < 16; i++) 636 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 637 powerpc_sync(); 638 639 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 640 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 641 isync(); 642 643 tlbia(); 644 } 645 646 void 647 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 648 { 649 ihandle_t mmui; 650 phandle_t chosen, mmu; 651 int sz; 652 int i, j; 653 vm_size_t size, physsz, hwphyssz; 654 vm_offset_t pa, va, off; 655 void *dpcpu; 656 register_t msr; 657 658 /* 659 * Set up BAT0 to map the lowest 256 MB area 660 */ 661 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 662 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 663 664 /* 665 * Map PCI memory space. 666 */ 667 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 668 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 669 670 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 671 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 672 673 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 674 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 675 676 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 677 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 678 679 /* 680 * Map obio devices. 681 */ 682 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 683 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 684 685 /* 686 * Use an IBAT and a DBAT to map the bottom segment of memory 687 * where we are. Turn off instruction relocation temporarily 688 * to prevent faults while reprogramming the IBAT. 689 */ 690 msr = mfmsr(); 691 mtmsr(msr & ~PSL_IR); 692 __asm (".balign 32; \n" 693 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 694 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 695 :: "r"(battable[0].batu), "r"(battable[0].batl)); 696 mtmsr(msr); 697 698 /* map pci space */ 699 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 700 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 701 isync(); 702 703 /* set global direct map flag */ 704 hw_direct_map = 1; 705 706 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 707 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 708 709 for (i = 0; i < pregions_sz; i++) { 710 vm_offset_t pa; 711 vm_offset_t end; 712 713 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 714 pregions[i].mr_start, 715 pregions[i].mr_start + pregions[i].mr_size, 716 pregions[i].mr_size); 717 /* 718 * Install entries into the BAT table to allow all 719 * of physmem to be convered by on-demand BAT entries. 720 * The loop will sometimes set the same battable element 721 * twice, but that's fine since they won't be used for 722 * a while yet. 723 */ 724 pa = pregions[i].mr_start & 0xf0000000; 725 end = pregions[i].mr_start + pregions[i].mr_size; 726 do { 727 u_int n = pa >> ADDR_SR_SHFT; 728 729 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 730 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 731 pa += SEGMENT_LENGTH; 732 } while (pa < end); 733 } 734 735 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 736 panic("moea_bootstrap: phys_avail too small"); 737 738 phys_avail_count = 0; 739 physsz = 0; 740 hwphyssz = 0; 741 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 742 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 743 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 744 regions[i].mr_start + regions[i].mr_size, 745 regions[i].mr_size); 746 if (hwphyssz != 0 && 747 (physsz + regions[i].mr_size) >= hwphyssz) { 748 if (physsz < hwphyssz) { 749 phys_avail[j] = regions[i].mr_start; 750 phys_avail[j + 1] = regions[i].mr_start + 751 hwphyssz - physsz; 752 physsz = hwphyssz; 753 phys_avail_count++; 754 } 755 break; 756 } 757 phys_avail[j] = regions[i].mr_start; 758 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 759 phys_avail_count++; 760 physsz += regions[i].mr_size; 761 } 762 physmem = btoc(physsz); 763 764 /* 765 * Allocate PTEG table. 766 */ 767 #ifdef PTEGCOUNT 768 moea_pteg_count = PTEGCOUNT; 769 #else 770 moea_pteg_count = 0x1000; 771 772 while (moea_pteg_count < physmem) 773 moea_pteg_count <<= 1; 774 775 moea_pteg_count >>= 1; 776 #endif /* PTEGCOUNT */ 777 778 size = moea_pteg_count * sizeof(struct pteg); 779 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 780 size); 781 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 782 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 783 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 784 moea_pteg_mask = moea_pteg_count - 1; 785 786 /* 787 * Allocate pv/overflow lists. 788 */ 789 size = sizeof(struct pvo_head) * moea_pteg_count; 790 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 791 PAGE_SIZE); 792 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 793 for (i = 0; i < moea_pteg_count; i++) 794 LIST_INIT(&moea_pvo_table[i]); 795 796 /* 797 * Initialize the lock that synchronizes access to the pteg and pvo 798 * tables. 799 */ 800 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 801 MTX_RECURSE); 802 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 803 804 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 805 806 /* 807 * Initialise the unmanaged pvo pool. 808 */ 809 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 810 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 811 moea_bpvo_pool_index = 0; 812 813 /* 814 * Make sure kernel vsid is allocated as well as VSID 0. 815 */ 816 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 817 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 818 moea_vsid_bitmap[0] |= 1; 819 820 /* 821 * Initialize the kernel pmap (which is statically allocated). 822 */ 823 PMAP_LOCK_INIT(kernel_pmap); 824 for (i = 0; i < 16; i++) 825 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 826 CPU_FILL(&kernel_pmap->pm_active); 827 LIST_INIT(&kernel_pmap->pmap_pvo); 828 829 /* 830 * Set up the Open Firmware mappings 831 */ 832 if ((chosen = OF_finddevice("/chosen")) == -1) 833 panic("moea_bootstrap: can't find /chosen"); 834 OF_getprop(chosen, "mmu", &mmui, 4); 835 if ((mmu = OF_instance_to_package(mmui)) == -1) 836 panic("moea_bootstrap: can't get mmu package"); 837 if ((sz = OF_getproplen(mmu, "translations")) == -1) 838 panic("moea_bootstrap: can't get ofw translation count"); 839 translations = NULL; 840 for (i = 0; phys_avail[i] != 0; i += 2) { 841 if (phys_avail[i + 1] >= sz) { 842 translations = (struct ofw_map *)phys_avail[i]; 843 break; 844 } 845 } 846 if (translations == NULL) 847 panic("moea_bootstrap: no space to copy translations"); 848 bzero(translations, sz); 849 if (OF_getprop(mmu, "translations", translations, sz) == -1) 850 panic("moea_bootstrap: can't get ofw translations"); 851 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 852 sz /= sizeof(*translations); 853 qsort(translations, sz, sizeof (*translations), om_cmp); 854 for (i = 0; i < sz; i++) { 855 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 856 translations[i].om_pa, translations[i].om_va, 857 translations[i].om_len); 858 859 /* 860 * If the mapping is 1:1, let the RAM and device on-demand 861 * BAT tables take care of the translation. 862 */ 863 if (translations[i].om_va == translations[i].om_pa) 864 continue; 865 866 /* Enter the pages */ 867 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) 868 moea_kenter(mmup, translations[i].om_va + off, 869 translations[i].om_pa + off); 870 } 871 872 /* 873 * Calculate the last available physical address. 874 */ 875 for (i = 0; phys_avail[i + 2] != 0; i += 2) 876 ; 877 Maxmem = powerpc_btop(phys_avail[i + 1]); 878 879 moea_cpu_bootstrap(mmup,0); 880 881 pmap_bootstrapped++; 882 883 /* 884 * Set the start and end of kva. 885 */ 886 virtual_avail = VM_MIN_KERNEL_ADDRESS; 887 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 888 889 /* 890 * Allocate a kernel stack with a guard page for thread0 and map it 891 * into the kernel page map. 892 */ 893 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 894 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 895 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 896 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 897 thread0.td_kstack = va; 898 thread0.td_kstack_pages = KSTACK_PAGES; 899 for (i = 0; i < KSTACK_PAGES; i++) { 900 moea_kenter(mmup, va, pa); 901 pa += PAGE_SIZE; 902 va += PAGE_SIZE; 903 } 904 905 /* 906 * Allocate virtual address space for the message buffer. 907 */ 908 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 909 msgbufp = (struct msgbuf *)virtual_avail; 910 va = virtual_avail; 911 virtual_avail += round_page(msgbufsize); 912 while (va < virtual_avail) { 913 moea_kenter(mmup, va, pa); 914 pa += PAGE_SIZE; 915 va += PAGE_SIZE; 916 } 917 918 /* 919 * Allocate virtual address space for the dynamic percpu area. 920 */ 921 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 922 dpcpu = (void *)virtual_avail; 923 va = virtual_avail; 924 virtual_avail += DPCPU_SIZE; 925 while (va < virtual_avail) { 926 moea_kenter(mmup, va, pa); 927 pa += PAGE_SIZE; 928 va += PAGE_SIZE; 929 } 930 dpcpu_init(dpcpu, 0); 931 } 932 933 /* 934 * Activate a user pmap. The pmap must be activated before it's address 935 * space can be accessed in any way. 936 */ 937 void 938 moea_activate(mmu_t mmu, struct thread *td) 939 { 940 pmap_t pm, pmr; 941 942 /* 943 * Load all the data we need up front to encourage the compiler to 944 * not issue any loads while we have interrupts disabled below. 945 */ 946 pm = &td->td_proc->p_vmspace->vm_pmap; 947 pmr = pm->pmap_phys; 948 949 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 950 PCPU_SET(curpmap, pmr); 951 } 952 953 void 954 moea_deactivate(mmu_t mmu, struct thread *td) 955 { 956 pmap_t pm; 957 958 pm = &td->td_proc->p_vmspace->vm_pmap; 959 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 960 PCPU_SET(curpmap, NULL); 961 } 962 963 void 964 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 965 { 966 struct pvo_entry *pvo; 967 968 PMAP_LOCK(pm); 969 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 970 971 if (pvo != NULL) { 972 if (wired) { 973 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 974 pm->pm_stats.wired_count++; 975 pvo->pvo_vaddr |= PVO_WIRED; 976 } else { 977 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 978 pm->pm_stats.wired_count--; 979 pvo->pvo_vaddr &= ~PVO_WIRED; 980 } 981 } 982 PMAP_UNLOCK(pm); 983 } 984 985 void 986 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 987 { 988 vm_offset_t dst; 989 vm_offset_t src; 990 991 dst = VM_PAGE_TO_PHYS(mdst); 992 src = VM_PAGE_TO_PHYS(msrc); 993 994 kcopy((void *)src, (void *)dst, PAGE_SIZE); 995 } 996 997 /* 998 * Zero a page of physical memory by temporarily mapping it into the tlb. 999 */ 1000 void 1001 moea_zero_page(mmu_t mmu, vm_page_t m) 1002 { 1003 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1004 void *va = (void *)pa; 1005 1006 bzero(va, PAGE_SIZE); 1007 } 1008 1009 void 1010 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1011 { 1012 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1013 void *va = (void *)(pa + off); 1014 1015 bzero(va, size); 1016 } 1017 1018 void 1019 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1020 { 1021 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1022 void *va = (void *)pa; 1023 1024 bzero(va, PAGE_SIZE); 1025 } 1026 1027 /* 1028 * Map the given physical page at the specified virtual address in the 1029 * target pmap with the protection requested. If specified the page 1030 * will be wired down. 1031 */ 1032 void 1033 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1034 boolean_t wired) 1035 { 1036 1037 vm_page_lock_queues(); 1038 PMAP_LOCK(pmap); 1039 moea_enter_locked(pmap, va, m, prot, wired); 1040 vm_page_unlock_queues(); 1041 PMAP_UNLOCK(pmap); 1042 } 1043 1044 /* 1045 * Map the given physical page at the specified virtual address in the 1046 * target pmap with the protection requested. If specified the page 1047 * will be wired down. 1048 * 1049 * The page queues and pmap must be locked. 1050 */ 1051 static void 1052 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1053 boolean_t wired) 1054 { 1055 struct pvo_head *pvo_head; 1056 uma_zone_t zone; 1057 vm_page_t pg; 1058 u_int pte_lo, pvo_flags, was_exec; 1059 int error; 1060 1061 if (!moea_initialized) { 1062 pvo_head = &moea_pvo_kunmanaged; 1063 zone = moea_upvo_zone; 1064 pvo_flags = 0; 1065 pg = NULL; 1066 was_exec = PTE_EXEC; 1067 } else { 1068 pvo_head = vm_page_to_pvoh(m); 1069 pg = m; 1070 zone = moea_mpvo_zone; 1071 pvo_flags = PVO_MANAGED; 1072 was_exec = 0; 1073 } 1074 if (pmap_bootstrapped) 1075 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1076 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1077 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1078 VM_OBJECT_LOCKED(m->object), 1079 ("moea_enter_locked: page %p is not busy", m)); 1080 1081 /* XXX change the pvo head for fake pages */ 1082 if ((m->oflags & VPO_UNMANAGED) != 0) { 1083 pvo_flags &= ~PVO_MANAGED; 1084 pvo_head = &moea_pvo_kunmanaged; 1085 zone = moea_upvo_zone; 1086 } 1087 1088 /* 1089 * If this is a managed page, and it's the first reference to the page, 1090 * clear the execness of the page. Otherwise fetch the execness. 1091 */ 1092 if ((pg != NULL) && ((m->oflags & VPO_UNMANAGED) == 0)) { 1093 if (LIST_EMPTY(pvo_head)) { 1094 moea_attr_clear(pg, PTE_EXEC); 1095 } else { 1096 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1097 } 1098 } 1099 1100 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1101 1102 if (prot & VM_PROT_WRITE) { 1103 pte_lo |= PTE_BW; 1104 if (pmap_bootstrapped && 1105 (m->oflags & VPO_UNMANAGED) == 0) 1106 vm_page_aflag_set(m, PGA_WRITEABLE); 1107 } else 1108 pte_lo |= PTE_BR; 1109 1110 if (prot & VM_PROT_EXECUTE) 1111 pvo_flags |= PVO_EXECUTABLE; 1112 1113 if (wired) 1114 pvo_flags |= PVO_WIRED; 1115 1116 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1117 pte_lo, pvo_flags); 1118 1119 /* 1120 * Flush the real page from the instruction cache if this page is 1121 * mapped executable and cacheable and was not previously mapped (or 1122 * was not mapped executable). 1123 */ 1124 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1125 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1126 /* 1127 * Flush the real memory from the cache. 1128 */ 1129 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1130 if (pg != NULL) 1131 moea_attr_save(pg, PTE_EXEC); 1132 } 1133 1134 /* XXX syncicache always until problems are sorted */ 1135 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1136 } 1137 1138 /* 1139 * Maps a sequence of resident pages belonging to the same object. 1140 * The sequence begins with the given page m_start. This page is 1141 * mapped at the given virtual address start. Each subsequent page is 1142 * mapped at a virtual address that is offset from start by the same 1143 * amount as the page is offset from m_start within the object. The 1144 * last page in the sequence is the page with the largest offset from 1145 * m_start that can be mapped at a virtual address less than the given 1146 * virtual address end. Not every virtual page between start and end 1147 * is mapped; only those for which a resident page exists with the 1148 * corresponding offset from m_start are mapped. 1149 */ 1150 void 1151 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1152 vm_page_t m_start, vm_prot_t prot) 1153 { 1154 vm_page_t m; 1155 vm_pindex_t diff, psize; 1156 1157 psize = atop(end - start); 1158 m = m_start; 1159 vm_page_lock_queues(); 1160 PMAP_LOCK(pm); 1161 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1162 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1163 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1164 m = TAILQ_NEXT(m, listq); 1165 } 1166 vm_page_unlock_queues(); 1167 PMAP_UNLOCK(pm); 1168 } 1169 1170 void 1171 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1172 vm_prot_t prot) 1173 { 1174 1175 vm_page_lock_queues(); 1176 PMAP_LOCK(pm); 1177 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1178 FALSE); 1179 vm_page_unlock_queues(); 1180 PMAP_UNLOCK(pm); 1181 } 1182 1183 vm_paddr_t 1184 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1185 { 1186 struct pvo_entry *pvo; 1187 vm_paddr_t pa; 1188 1189 PMAP_LOCK(pm); 1190 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1191 if (pvo == NULL) 1192 pa = 0; 1193 else 1194 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1195 PMAP_UNLOCK(pm); 1196 return (pa); 1197 } 1198 1199 /* 1200 * Atomically extract and hold the physical page with the given 1201 * pmap and virtual address pair if that mapping permits the given 1202 * protection. 1203 */ 1204 vm_page_t 1205 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1206 { 1207 struct pvo_entry *pvo; 1208 vm_page_t m; 1209 vm_paddr_t pa; 1210 1211 m = NULL; 1212 pa = 0; 1213 PMAP_LOCK(pmap); 1214 retry: 1215 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1216 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1217 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1218 (prot & VM_PROT_WRITE) == 0)) { 1219 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1220 goto retry; 1221 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1222 vm_page_hold(m); 1223 } 1224 PA_UNLOCK_COND(pa); 1225 PMAP_UNLOCK(pmap); 1226 return (m); 1227 } 1228 1229 void 1230 moea_init(mmu_t mmu) 1231 { 1232 1233 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1234 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1235 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1236 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1237 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1238 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1239 moea_initialized = TRUE; 1240 } 1241 1242 boolean_t 1243 moea_is_referenced(mmu_t mmu, vm_page_t m) 1244 { 1245 1246 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1247 ("moea_is_referenced: page %p is not managed", m)); 1248 return (moea_query_bit(m, PTE_REF)); 1249 } 1250 1251 boolean_t 1252 moea_is_modified(mmu_t mmu, vm_page_t m) 1253 { 1254 1255 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1256 ("moea_is_modified: page %p is not managed", m)); 1257 1258 /* 1259 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1260 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1261 * is clear, no PTEs can have PTE_CHG set. 1262 */ 1263 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1264 if ((m->oflags & VPO_BUSY) == 0 && 1265 (m->aflags & PGA_WRITEABLE) == 0) 1266 return (FALSE); 1267 return (moea_query_bit(m, PTE_CHG)); 1268 } 1269 1270 boolean_t 1271 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1272 { 1273 struct pvo_entry *pvo; 1274 boolean_t rv; 1275 1276 PMAP_LOCK(pmap); 1277 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1278 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1279 PMAP_UNLOCK(pmap); 1280 return (rv); 1281 } 1282 1283 void 1284 moea_clear_reference(mmu_t mmu, vm_page_t m) 1285 { 1286 1287 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1288 ("moea_clear_reference: page %p is not managed", m)); 1289 moea_clear_bit(m, PTE_REF); 1290 } 1291 1292 void 1293 moea_clear_modify(mmu_t mmu, vm_page_t m) 1294 { 1295 1296 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1297 ("moea_clear_modify: page %p is not managed", m)); 1298 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1299 KASSERT((m->oflags & VPO_BUSY) == 0, 1300 ("moea_clear_modify: page %p is busy", m)); 1301 1302 /* 1303 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1304 * set. If the object containing the page is locked and the page is 1305 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1306 */ 1307 if ((m->aflags & PGA_WRITEABLE) == 0) 1308 return; 1309 moea_clear_bit(m, PTE_CHG); 1310 } 1311 1312 /* 1313 * Clear the write and modified bits in each of the given page's mappings. 1314 */ 1315 void 1316 moea_remove_write(mmu_t mmu, vm_page_t m) 1317 { 1318 struct pvo_entry *pvo; 1319 struct pte *pt; 1320 pmap_t pmap; 1321 u_int lo; 1322 1323 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1324 ("moea_remove_write: page %p is not managed", m)); 1325 1326 /* 1327 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1328 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1329 * is clear, no page table entries need updating. 1330 */ 1331 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1332 if ((m->oflags & VPO_BUSY) == 0 && 1333 (m->aflags & PGA_WRITEABLE) == 0) 1334 return; 1335 vm_page_lock_queues(); 1336 lo = moea_attr_fetch(m); 1337 powerpc_sync(); 1338 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1339 pmap = pvo->pvo_pmap; 1340 PMAP_LOCK(pmap); 1341 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1342 pt = moea_pvo_to_pte(pvo, -1); 1343 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1344 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1345 if (pt != NULL) { 1346 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1347 lo |= pvo->pvo_pte.pte.pte_lo; 1348 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1349 moea_pte_change(pt, &pvo->pvo_pte.pte, 1350 pvo->pvo_vaddr); 1351 mtx_unlock(&moea_table_mutex); 1352 } 1353 } 1354 PMAP_UNLOCK(pmap); 1355 } 1356 if ((lo & PTE_CHG) != 0) { 1357 moea_attr_clear(m, PTE_CHG); 1358 vm_page_dirty(m); 1359 } 1360 vm_page_aflag_clear(m, PGA_WRITEABLE); 1361 vm_page_unlock_queues(); 1362 } 1363 1364 /* 1365 * moea_ts_referenced: 1366 * 1367 * Return a count of reference bits for a page, clearing those bits. 1368 * It is not necessary for every reference bit to be cleared, but it 1369 * is necessary that 0 only be returned when there are truly no 1370 * reference bits set. 1371 * 1372 * XXX: The exact number of bits to check and clear is a matter that 1373 * should be tested and standardized at some point in the future for 1374 * optimal aging of shared pages. 1375 */ 1376 boolean_t 1377 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1378 { 1379 1380 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1381 ("moea_ts_referenced: page %p is not managed", m)); 1382 return (moea_clear_bit(m, PTE_REF)); 1383 } 1384 1385 /* 1386 * Modify the WIMG settings of all mappings for a page. 1387 */ 1388 void 1389 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1390 { 1391 struct pvo_entry *pvo; 1392 struct pvo_head *pvo_head; 1393 struct pte *pt; 1394 pmap_t pmap; 1395 u_int lo; 1396 1397 if ((m->oflags & VPO_UNMANAGED) != 0) { 1398 m->md.mdpg_cache_attrs = ma; 1399 return; 1400 } 1401 1402 vm_page_lock_queues(); 1403 pvo_head = vm_page_to_pvoh(m); 1404 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1405 1406 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1407 pmap = pvo->pvo_pmap; 1408 PMAP_LOCK(pmap); 1409 pt = moea_pvo_to_pte(pvo, -1); 1410 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1411 pvo->pvo_pte.pte.pte_lo |= lo; 1412 if (pt != NULL) { 1413 moea_pte_change(pt, &pvo->pvo_pte.pte, 1414 pvo->pvo_vaddr); 1415 if (pvo->pvo_pmap == kernel_pmap) 1416 isync(); 1417 } 1418 mtx_unlock(&moea_table_mutex); 1419 PMAP_UNLOCK(pmap); 1420 } 1421 m->md.mdpg_cache_attrs = ma; 1422 vm_page_unlock_queues(); 1423 } 1424 1425 /* 1426 * Map a wired page into kernel virtual address space. 1427 */ 1428 void 1429 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1430 { 1431 1432 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1433 } 1434 1435 void 1436 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1437 { 1438 u_int pte_lo; 1439 int error; 1440 1441 #if 0 1442 if (va < VM_MIN_KERNEL_ADDRESS) 1443 panic("moea_kenter: attempt to enter non-kernel address %#x", 1444 va); 1445 #endif 1446 1447 pte_lo = moea_calc_wimg(pa, ma); 1448 1449 PMAP_LOCK(kernel_pmap); 1450 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1451 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1452 1453 if (error != 0 && error != ENOENT) 1454 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1455 pa, error); 1456 1457 /* 1458 * Flush the real memory from the instruction cache. 1459 */ 1460 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1461 moea_syncicache(pa, PAGE_SIZE); 1462 } 1463 PMAP_UNLOCK(kernel_pmap); 1464 } 1465 1466 /* 1467 * Extract the physical page address associated with the given kernel virtual 1468 * address. 1469 */ 1470 vm_offset_t 1471 moea_kextract(mmu_t mmu, vm_offset_t va) 1472 { 1473 struct pvo_entry *pvo; 1474 vm_paddr_t pa; 1475 1476 /* 1477 * Allow direct mappings on 32-bit OEA 1478 */ 1479 if (va < VM_MIN_KERNEL_ADDRESS) { 1480 return (va); 1481 } 1482 1483 PMAP_LOCK(kernel_pmap); 1484 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1485 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1486 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1487 PMAP_UNLOCK(kernel_pmap); 1488 return (pa); 1489 } 1490 1491 /* 1492 * Remove a wired page from kernel virtual address space. 1493 */ 1494 void 1495 moea_kremove(mmu_t mmu, vm_offset_t va) 1496 { 1497 1498 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1499 } 1500 1501 /* 1502 * Map a range of physical addresses into kernel virtual address space. 1503 * 1504 * The value passed in *virt is a suggested virtual address for the mapping. 1505 * Architectures which can support a direct-mapped physical to virtual region 1506 * can return the appropriate address within that region, leaving '*virt' 1507 * unchanged. We cannot and therefore do not; *virt is updated with the 1508 * first usable address after the mapped region. 1509 */ 1510 vm_offset_t 1511 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1512 vm_offset_t pa_end, int prot) 1513 { 1514 vm_offset_t sva, va; 1515 1516 sva = *virt; 1517 va = sva; 1518 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1519 moea_kenter(mmu, va, pa_start); 1520 *virt = va; 1521 return (sva); 1522 } 1523 1524 /* 1525 * Returns true if the pmap's pv is one of the first 1526 * 16 pvs linked to from this page. This count may 1527 * be changed upwards or downwards in the future; it 1528 * is only necessary that true be returned for a small 1529 * subset of pmaps for proper page aging. 1530 */ 1531 boolean_t 1532 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1533 { 1534 int loops; 1535 struct pvo_entry *pvo; 1536 boolean_t rv; 1537 1538 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1539 ("moea_page_exists_quick: page %p is not managed", m)); 1540 loops = 0; 1541 rv = FALSE; 1542 vm_page_lock_queues(); 1543 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1544 if (pvo->pvo_pmap == pmap) { 1545 rv = TRUE; 1546 break; 1547 } 1548 if (++loops >= 16) 1549 break; 1550 } 1551 vm_page_unlock_queues(); 1552 return (rv); 1553 } 1554 1555 /* 1556 * Return the number of managed mappings to the given physical page 1557 * that are wired. 1558 */ 1559 int 1560 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1561 { 1562 struct pvo_entry *pvo; 1563 int count; 1564 1565 count = 0; 1566 if ((m->oflags & VPO_UNMANAGED) != 0) 1567 return (count); 1568 vm_page_lock_queues(); 1569 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1570 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1571 count++; 1572 vm_page_unlock_queues(); 1573 return (count); 1574 } 1575 1576 static u_int moea_vsidcontext; 1577 1578 void 1579 moea_pinit(mmu_t mmu, pmap_t pmap) 1580 { 1581 int i, mask; 1582 u_int entropy; 1583 1584 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1585 PMAP_LOCK_INIT(pmap); 1586 LIST_INIT(&pmap->pmap_pvo); 1587 1588 entropy = 0; 1589 __asm __volatile("mftb %0" : "=r"(entropy)); 1590 1591 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1592 == NULL) { 1593 pmap->pmap_phys = pmap; 1594 } 1595 1596 1597 mtx_lock(&moea_vsid_mutex); 1598 /* 1599 * Allocate some segment registers for this pmap. 1600 */ 1601 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1602 u_int hash, n; 1603 1604 /* 1605 * Create a new value by mutiplying by a prime and adding in 1606 * entropy from the timebase register. This is to make the 1607 * VSID more random so that the PT hash function collides 1608 * less often. (Note that the prime casues gcc to do shifts 1609 * instead of a multiply.) 1610 */ 1611 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1612 hash = moea_vsidcontext & (NPMAPS - 1); 1613 if (hash == 0) /* 0 is special, avoid it */ 1614 continue; 1615 n = hash >> 5; 1616 mask = 1 << (hash & (VSID_NBPW - 1)); 1617 hash = (moea_vsidcontext & 0xfffff); 1618 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1619 /* anything free in this bucket? */ 1620 if (moea_vsid_bitmap[n] == 0xffffffff) { 1621 entropy = (moea_vsidcontext >> 20); 1622 continue; 1623 } 1624 i = ffs(~moea_vsid_bitmap[n]) - 1; 1625 mask = 1 << i; 1626 hash &= 0xfffff & ~(VSID_NBPW - 1); 1627 hash |= i; 1628 } 1629 KASSERT(!(moea_vsid_bitmap[n] & mask), 1630 ("Allocating in-use VSID group %#x\n", hash)); 1631 moea_vsid_bitmap[n] |= mask; 1632 for (i = 0; i < 16; i++) 1633 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1634 mtx_unlock(&moea_vsid_mutex); 1635 return; 1636 } 1637 1638 mtx_unlock(&moea_vsid_mutex); 1639 panic("moea_pinit: out of segments"); 1640 } 1641 1642 /* 1643 * Initialize the pmap associated with process 0. 1644 */ 1645 void 1646 moea_pinit0(mmu_t mmu, pmap_t pm) 1647 { 1648 1649 moea_pinit(mmu, pm); 1650 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1651 } 1652 1653 /* 1654 * Set the physical protection on the specified range of this map as requested. 1655 */ 1656 void 1657 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1658 vm_prot_t prot) 1659 { 1660 struct pvo_entry *pvo; 1661 struct pte *pt; 1662 int pteidx; 1663 1664 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1665 ("moea_protect: non current pmap")); 1666 1667 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1668 moea_remove(mmu, pm, sva, eva); 1669 return; 1670 } 1671 1672 vm_page_lock_queues(); 1673 PMAP_LOCK(pm); 1674 for (; sva < eva; sva += PAGE_SIZE) { 1675 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1676 if (pvo == NULL) 1677 continue; 1678 1679 if ((prot & VM_PROT_EXECUTE) == 0) 1680 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1681 1682 /* 1683 * Grab the PTE pointer before we diddle with the cached PTE 1684 * copy. 1685 */ 1686 pt = moea_pvo_to_pte(pvo, pteidx); 1687 /* 1688 * Change the protection of the page. 1689 */ 1690 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1691 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1692 1693 /* 1694 * If the PVO is in the page table, update that pte as well. 1695 */ 1696 if (pt != NULL) { 1697 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1698 mtx_unlock(&moea_table_mutex); 1699 } 1700 } 1701 vm_page_unlock_queues(); 1702 PMAP_UNLOCK(pm); 1703 } 1704 1705 /* 1706 * Map a list of wired pages into kernel virtual address space. This is 1707 * intended for temporary mappings which do not need page modification or 1708 * references recorded. Existing mappings in the region are overwritten. 1709 */ 1710 void 1711 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1712 { 1713 vm_offset_t va; 1714 1715 va = sva; 1716 while (count-- > 0) { 1717 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1718 va += PAGE_SIZE; 1719 m++; 1720 } 1721 } 1722 1723 /* 1724 * Remove page mappings from kernel virtual address space. Intended for 1725 * temporary mappings entered by moea_qenter. 1726 */ 1727 void 1728 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1729 { 1730 vm_offset_t va; 1731 1732 va = sva; 1733 while (count-- > 0) { 1734 moea_kremove(mmu, va); 1735 va += PAGE_SIZE; 1736 } 1737 } 1738 1739 void 1740 moea_release(mmu_t mmu, pmap_t pmap) 1741 { 1742 int idx, mask; 1743 1744 /* 1745 * Free segment register's VSID 1746 */ 1747 if (pmap->pm_sr[0] == 0) 1748 panic("moea_release"); 1749 1750 mtx_lock(&moea_vsid_mutex); 1751 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1752 mask = 1 << (idx % VSID_NBPW); 1753 idx /= VSID_NBPW; 1754 moea_vsid_bitmap[idx] &= ~mask; 1755 mtx_unlock(&moea_vsid_mutex); 1756 PMAP_LOCK_DESTROY(pmap); 1757 } 1758 1759 /* 1760 * Remove the given range of addresses from the specified map. 1761 */ 1762 void 1763 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1764 { 1765 struct pvo_entry *pvo; 1766 int pteidx; 1767 1768 vm_page_lock_queues(); 1769 PMAP_LOCK(pm); 1770 if ((eva - sva)/PAGE_SIZE < 10) { 1771 for (; sva < eva; sva += PAGE_SIZE) { 1772 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1773 if (pvo != NULL) 1774 moea_pvo_remove(pvo, pteidx); 1775 } 1776 } else { 1777 LIST_FOREACH(pvo, &pm->pmap_pvo, pvo_plink) { 1778 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva) 1779 continue; 1780 moea_pvo_remove(pvo, -1); 1781 } 1782 } 1783 PMAP_UNLOCK(pm); 1784 vm_page_unlock_queues(); 1785 } 1786 1787 /* 1788 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1789 * will reflect changes in pte's back to the vm_page. 1790 */ 1791 void 1792 moea_remove_all(mmu_t mmu, vm_page_t m) 1793 { 1794 struct pvo_head *pvo_head; 1795 struct pvo_entry *pvo, *next_pvo; 1796 pmap_t pmap; 1797 1798 vm_page_lock_queues(); 1799 pvo_head = vm_page_to_pvoh(m); 1800 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1801 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1802 1803 pmap = pvo->pvo_pmap; 1804 PMAP_LOCK(pmap); 1805 moea_pvo_remove(pvo, -1); 1806 PMAP_UNLOCK(pmap); 1807 } 1808 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) { 1809 moea_attr_clear(m, PTE_CHG); 1810 vm_page_dirty(m); 1811 } 1812 vm_page_aflag_clear(m, PGA_WRITEABLE); 1813 vm_page_unlock_queues(); 1814 } 1815 1816 /* 1817 * Allocate a physical page of memory directly from the phys_avail map. 1818 * Can only be called from moea_bootstrap before avail start and end are 1819 * calculated. 1820 */ 1821 static vm_offset_t 1822 moea_bootstrap_alloc(vm_size_t size, u_int align) 1823 { 1824 vm_offset_t s, e; 1825 int i, j; 1826 1827 size = round_page(size); 1828 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1829 if (align != 0) 1830 s = (phys_avail[i] + align - 1) & ~(align - 1); 1831 else 1832 s = phys_avail[i]; 1833 e = s + size; 1834 1835 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1836 continue; 1837 1838 if (s == phys_avail[i]) { 1839 phys_avail[i] += size; 1840 } else if (e == phys_avail[i + 1]) { 1841 phys_avail[i + 1] -= size; 1842 } else { 1843 for (j = phys_avail_count * 2; j > i; j -= 2) { 1844 phys_avail[j] = phys_avail[j - 2]; 1845 phys_avail[j + 1] = phys_avail[j - 1]; 1846 } 1847 1848 phys_avail[i + 3] = phys_avail[i + 1]; 1849 phys_avail[i + 1] = s; 1850 phys_avail[i + 2] = e; 1851 phys_avail_count++; 1852 } 1853 1854 return (s); 1855 } 1856 panic("moea_bootstrap_alloc: could not allocate memory"); 1857 } 1858 1859 static void 1860 moea_syncicache(vm_offset_t pa, vm_size_t len) 1861 { 1862 __syncicache((void *)pa, len); 1863 } 1864 1865 static int 1866 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1867 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1868 { 1869 struct pvo_entry *pvo; 1870 u_int sr; 1871 int first; 1872 u_int ptegidx; 1873 int i; 1874 int bootstrap; 1875 1876 moea_pvo_enter_calls++; 1877 first = 0; 1878 bootstrap = 0; 1879 1880 /* 1881 * Compute the PTE Group index. 1882 */ 1883 va &= ~ADDR_POFF; 1884 sr = va_to_sr(pm->pm_sr, va); 1885 ptegidx = va_to_pteg(sr, va); 1886 1887 /* 1888 * Remove any existing mapping for this page. Reuse the pvo entry if 1889 * there is a mapping. 1890 */ 1891 mtx_lock(&moea_table_mutex); 1892 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1893 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1894 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1895 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1896 (pte_lo & PTE_PP)) { 1897 mtx_unlock(&moea_table_mutex); 1898 return (0); 1899 } 1900 moea_pvo_remove(pvo, -1); 1901 break; 1902 } 1903 } 1904 1905 /* 1906 * If we aren't overwriting a mapping, try to allocate. 1907 */ 1908 if (moea_initialized) { 1909 pvo = uma_zalloc(zone, M_NOWAIT); 1910 } else { 1911 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1912 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1913 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1914 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1915 } 1916 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1917 moea_bpvo_pool_index++; 1918 bootstrap = 1; 1919 } 1920 1921 if (pvo == NULL) { 1922 mtx_unlock(&moea_table_mutex); 1923 return (ENOMEM); 1924 } 1925 1926 moea_pvo_entries++; 1927 pvo->pvo_vaddr = va; 1928 pvo->pvo_pmap = pm; 1929 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1930 pvo->pvo_vaddr &= ~ADDR_POFF; 1931 if (flags & VM_PROT_EXECUTE) 1932 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1933 if (flags & PVO_WIRED) 1934 pvo->pvo_vaddr |= PVO_WIRED; 1935 if (pvo_head != &moea_pvo_kunmanaged) 1936 pvo->pvo_vaddr |= PVO_MANAGED; 1937 if (bootstrap) 1938 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1939 1940 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1941 1942 /* 1943 * Add to pmap list 1944 */ 1945 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink); 1946 1947 /* 1948 * Remember if the list was empty and therefore will be the first 1949 * item. 1950 */ 1951 if (LIST_FIRST(pvo_head) == NULL) 1952 first = 1; 1953 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1954 1955 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1956 pm->pm_stats.wired_count++; 1957 pm->pm_stats.resident_count++; 1958 1959 /* 1960 * We hope this succeeds but it isn't required. 1961 */ 1962 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1963 if (i >= 0) { 1964 PVO_PTEGIDX_SET(pvo, i); 1965 } else { 1966 panic("moea_pvo_enter: overflow"); 1967 moea_pte_overflow++; 1968 } 1969 mtx_unlock(&moea_table_mutex); 1970 1971 return (first ? ENOENT : 0); 1972 } 1973 1974 static void 1975 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1976 { 1977 struct pte *pt; 1978 1979 /* 1980 * If there is an active pte entry, we need to deactivate it (and 1981 * save the ref & cfg bits). 1982 */ 1983 pt = moea_pvo_to_pte(pvo, pteidx); 1984 if (pt != NULL) { 1985 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1986 mtx_unlock(&moea_table_mutex); 1987 PVO_PTEGIDX_CLR(pvo); 1988 } else { 1989 moea_pte_overflow--; 1990 } 1991 1992 /* 1993 * Update our statistics. 1994 */ 1995 pvo->pvo_pmap->pm_stats.resident_count--; 1996 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1997 pvo->pvo_pmap->pm_stats.wired_count--; 1998 1999 /* 2000 * Save the REF/CHG bits into their cache if the page is managed. 2001 */ 2002 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2003 struct vm_page *pg; 2004 2005 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2006 if (pg != NULL) { 2007 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2008 (PTE_REF | PTE_CHG)); 2009 } 2010 } 2011 2012 /* 2013 * Remove this PVO from the PV and pmap lists. 2014 */ 2015 LIST_REMOVE(pvo, pvo_vlink); 2016 LIST_REMOVE(pvo, pvo_plink); 2017 2018 /* 2019 * Remove this from the overflow list and return it to the pool 2020 * if we aren't going to reuse it. 2021 */ 2022 LIST_REMOVE(pvo, pvo_olink); 2023 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2024 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2025 moea_upvo_zone, pvo); 2026 moea_pvo_entries--; 2027 moea_pvo_remove_calls++; 2028 } 2029 2030 static __inline int 2031 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2032 { 2033 int pteidx; 2034 2035 /* 2036 * We can find the actual pte entry without searching by grabbing 2037 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2038 * noticing the HID bit. 2039 */ 2040 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2041 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2042 pteidx ^= moea_pteg_mask * 8; 2043 2044 return (pteidx); 2045 } 2046 2047 static struct pvo_entry * 2048 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2049 { 2050 struct pvo_entry *pvo; 2051 int ptegidx; 2052 u_int sr; 2053 2054 va &= ~ADDR_POFF; 2055 sr = va_to_sr(pm->pm_sr, va); 2056 ptegidx = va_to_pteg(sr, va); 2057 2058 mtx_lock(&moea_table_mutex); 2059 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2060 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2061 if (pteidx_p) 2062 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2063 break; 2064 } 2065 } 2066 mtx_unlock(&moea_table_mutex); 2067 2068 return (pvo); 2069 } 2070 2071 static struct pte * 2072 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2073 { 2074 struct pte *pt; 2075 2076 /* 2077 * If we haven't been supplied the ptegidx, calculate it. 2078 */ 2079 if (pteidx == -1) { 2080 int ptegidx; 2081 u_int sr; 2082 2083 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2084 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2085 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2086 } 2087 2088 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2089 mtx_lock(&moea_table_mutex); 2090 2091 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2092 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2093 "valid pte index", pvo); 2094 } 2095 2096 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2097 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2098 "pvo but no valid pte", pvo); 2099 } 2100 2101 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2102 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2103 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2104 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2105 } 2106 2107 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2108 != 0) { 2109 panic("moea_pvo_to_pte: pvo %p pte does not match " 2110 "pte %p in moea_pteg_table", pvo, pt); 2111 } 2112 2113 mtx_assert(&moea_table_mutex, MA_OWNED); 2114 return (pt); 2115 } 2116 2117 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2118 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2119 "moea_pteg_table but valid in pvo", pvo, pt); 2120 } 2121 2122 mtx_unlock(&moea_table_mutex); 2123 return (NULL); 2124 } 2125 2126 /* 2127 * XXX: THIS STUFF SHOULD BE IN pte.c? 2128 */ 2129 int 2130 moea_pte_spill(vm_offset_t addr) 2131 { 2132 struct pvo_entry *source_pvo, *victim_pvo; 2133 struct pvo_entry *pvo; 2134 int ptegidx, i, j; 2135 u_int sr; 2136 struct pteg *pteg; 2137 struct pte *pt; 2138 2139 moea_pte_spills++; 2140 2141 sr = mfsrin(addr); 2142 ptegidx = va_to_pteg(sr, addr); 2143 2144 /* 2145 * Have to substitute some entry. Use the primary hash for this. 2146 * Use low bits of timebase as random generator. 2147 */ 2148 pteg = &moea_pteg_table[ptegidx]; 2149 mtx_lock(&moea_table_mutex); 2150 __asm __volatile("mftb %0" : "=r"(i)); 2151 i &= 7; 2152 pt = &pteg->pt[i]; 2153 2154 source_pvo = NULL; 2155 victim_pvo = NULL; 2156 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2157 /* 2158 * We need to find a pvo entry for this address. 2159 */ 2160 if (source_pvo == NULL && 2161 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2162 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2163 /* 2164 * Now found an entry to be spilled into the pteg. 2165 * The PTE is now valid, so we know it's active. 2166 */ 2167 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2168 2169 if (j >= 0) { 2170 PVO_PTEGIDX_SET(pvo, j); 2171 moea_pte_overflow--; 2172 mtx_unlock(&moea_table_mutex); 2173 return (1); 2174 } 2175 2176 source_pvo = pvo; 2177 2178 if (victim_pvo != NULL) 2179 break; 2180 } 2181 2182 /* 2183 * We also need the pvo entry of the victim we are replacing 2184 * so save the R & C bits of the PTE. 2185 */ 2186 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2187 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2188 victim_pvo = pvo; 2189 if (source_pvo != NULL) 2190 break; 2191 } 2192 } 2193 2194 if (source_pvo == NULL) { 2195 mtx_unlock(&moea_table_mutex); 2196 return (0); 2197 } 2198 2199 if (victim_pvo == NULL) { 2200 if ((pt->pte_hi & PTE_HID) == 0) 2201 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2202 "entry", pt); 2203 2204 /* 2205 * If this is a secondary PTE, we need to search it's primary 2206 * pvo bucket for the matching PVO. 2207 */ 2208 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2209 pvo_olink) { 2210 /* 2211 * We also need the pvo entry of the victim we are 2212 * replacing so save the R & C bits of the PTE. 2213 */ 2214 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2215 victim_pvo = pvo; 2216 break; 2217 } 2218 } 2219 2220 if (victim_pvo == NULL) 2221 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2222 "entry", pt); 2223 } 2224 2225 /* 2226 * We are invalidating the TLB entry for the EA we are replacing even 2227 * though it's valid. If we don't, we lose any ref/chg bit changes 2228 * contained in the TLB entry. 2229 */ 2230 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2231 2232 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2233 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2234 2235 PVO_PTEGIDX_CLR(victim_pvo); 2236 PVO_PTEGIDX_SET(source_pvo, i); 2237 moea_pte_replacements++; 2238 2239 mtx_unlock(&moea_table_mutex); 2240 return (1); 2241 } 2242 2243 static int 2244 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2245 { 2246 struct pte *pt; 2247 int i; 2248 2249 mtx_assert(&moea_table_mutex, MA_OWNED); 2250 2251 /* 2252 * First try primary hash. 2253 */ 2254 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2255 if ((pt->pte_hi & PTE_VALID) == 0) { 2256 pvo_pt->pte_hi &= ~PTE_HID; 2257 moea_pte_set(pt, pvo_pt); 2258 return (i); 2259 } 2260 } 2261 2262 /* 2263 * Now try secondary hash. 2264 */ 2265 ptegidx ^= moea_pteg_mask; 2266 2267 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2268 if ((pt->pte_hi & PTE_VALID) == 0) { 2269 pvo_pt->pte_hi |= PTE_HID; 2270 moea_pte_set(pt, pvo_pt); 2271 return (i); 2272 } 2273 } 2274 2275 panic("moea_pte_insert: overflow"); 2276 return (-1); 2277 } 2278 2279 static boolean_t 2280 moea_query_bit(vm_page_t m, int ptebit) 2281 { 2282 struct pvo_entry *pvo; 2283 struct pte *pt; 2284 2285 if (moea_attr_fetch(m) & ptebit) 2286 return (TRUE); 2287 2288 vm_page_lock_queues(); 2289 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2290 2291 /* 2292 * See if we saved the bit off. If so, cache it and return 2293 * success. 2294 */ 2295 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2296 moea_attr_save(m, ptebit); 2297 vm_page_unlock_queues(); 2298 return (TRUE); 2299 } 2300 } 2301 2302 /* 2303 * No luck, now go through the hard part of looking at the PTEs 2304 * themselves. Sync so that any pending REF/CHG bits are flushed to 2305 * the PTEs. 2306 */ 2307 powerpc_sync(); 2308 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2309 2310 /* 2311 * See if this pvo has a valid PTE. if so, fetch the 2312 * REF/CHG bits from the valid PTE. If the appropriate 2313 * ptebit is set, cache it and return success. 2314 */ 2315 pt = moea_pvo_to_pte(pvo, -1); 2316 if (pt != NULL) { 2317 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2318 mtx_unlock(&moea_table_mutex); 2319 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2320 moea_attr_save(m, ptebit); 2321 vm_page_unlock_queues(); 2322 return (TRUE); 2323 } 2324 } 2325 } 2326 2327 vm_page_unlock_queues(); 2328 return (FALSE); 2329 } 2330 2331 static u_int 2332 moea_clear_bit(vm_page_t m, int ptebit) 2333 { 2334 u_int count; 2335 struct pvo_entry *pvo; 2336 struct pte *pt; 2337 2338 vm_page_lock_queues(); 2339 2340 /* 2341 * Clear the cached value. 2342 */ 2343 moea_attr_clear(m, ptebit); 2344 2345 /* 2346 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2347 * we can reset the right ones). note that since the pvo entries and 2348 * list heads are accessed via BAT0 and are never placed in the page 2349 * table, we don't have to worry about further accesses setting the 2350 * REF/CHG bits. 2351 */ 2352 powerpc_sync(); 2353 2354 /* 2355 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2356 * valid pte clear the ptebit from the valid pte. 2357 */ 2358 count = 0; 2359 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2360 pt = moea_pvo_to_pte(pvo, -1); 2361 if (pt != NULL) { 2362 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2363 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2364 count++; 2365 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2366 } 2367 mtx_unlock(&moea_table_mutex); 2368 } 2369 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2370 } 2371 2372 vm_page_unlock_queues(); 2373 return (count); 2374 } 2375 2376 /* 2377 * Return true if the physical range is encompassed by the battable[idx] 2378 */ 2379 static int 2380 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2381 { 2382 u_int prot; 2383 u_int32_t start; 2384 u_int32_t end; 2385 u_int32_t bat_ble; 2386 2387 /* 2388 * Return immediately if not a valid mapping 2389 */ 2390 if (!(battable[idx].batu & BAT_Vs)) 2391 return (EINVAL); 2392 2393 /* 2394 * The BAT entry must be cache-inhibited, guarded, and r/w 2395 * so it can function as an i/o page 2396 */ 2397 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2398 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2399 return (EPERM); 2400 2401 /* 2402 * The address should be within the BAT range. Assume that the 2403 * start address in the BAT has the correct alignment (thus 2404 * not requiring masking) 2405 */ 2406 start = battable[idx].batl & BAT_PBS; 2407 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2408 end = start | (bat_ble << 15) | 0x7fff; 2409 2410 if ((pa < start) || ((pa + size) > end)) 2411 return (ERANGE); 2412 2413 return (0); 2414 } 2415 2416 boolean_t 2417 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2418 { 2419 int i; 2420 2421 /* 2422 * This currently does not work for entries that 2423 * overlap 256M BAT segments. 2424 */ 2425 2426 for(i = 0; i < 16; i++) 2427 if (moea_bat_mapped(i, pa, size) == 0) 2428 return (0); 2429 2430 return (EFAULT); 2431 } 2432 2433 /* 2434 * Map a set of physical memory pages into the kernel virtual 2435 * address space. Return a pointer to where it is mapped. This 2436 * routine is intended to be used for mapping device memory, 2437 * NOT real memory. 2438 */ 2439 void * 2440 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2441 { 2442 2443 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2444 } 2445 2446 void * 2447 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2448 { 2449 vm_offset_t va, tmpva, ppa, offset; 2450 int i; 2451 2452 ppa = trunc_page(pa); 2453 offset = pa & PAGE_MASK; 2454 size = roundup(offset + size, PAGE_SIZE); 2455 2456 /* 2457 * If the physical address lies within a valid BAT table entry, 2458 * return the 1:1 mapping. This currently doesn't work 2459 * for regions that overlap 256M BAT segments. 2460 */ 2461 for (i = 0; i < 16; i++) { 2462 if (moea_bat_mapped(i, pa, size) == 0) 2463 return ((void *) pa); 2464 } 2465 2466 va = kmem_alloc_nofault(kernel_map, size); 2467 if (!va) 2468 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2469 2470 for (tmpva = va; size > 0;) { 2471 moea_kenter_attr(mmu, tmpva, ppa, ma); 2472 tlbie(tmpva); 2473 size -= PAGE_SIZE; 2474 tmpva += PAGE_SIZE; 2475 ppa += PAGE_SIZE; 2476 } 2477 2478 return ((void *)(va + offset)); 2479 } 2480 2481 void 2482 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2483 { 2484 vm_offset_t base, offset; 2485 2486 /* 2487 * If this is outside kernel virtual space, then it's a 2488 * battable entry and doesn't require unmapping 2489 */ 2490 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2491 base = trunc_page(va); 2492 offset = va & PAGE_MASK; 2493 size = roundup(offset + size, PAGE_SIZE); 2494 kmem_free(kernel_map, base, size); 2495 } 2496 } 2497 2498 static void 2499 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2500 { 2501 struct pvo_entry *pvo; 2502 vm_offset_t lim; 2503 vm_paddr_t pa; 2504 vm_size_t len; 2505 2506 PMAP_LOCK(pm); 2507 while (sz > 0) { 2508 lim = round_page(va); 2509 len = MIN(lim - va, sz); 2510 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2511 if (pvo != NULL) { 2512 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2513 (va & ADDR_POFF); 2514 moea_syncicache(pa, len); 2515 } 2516 va += len; 2517 sz -= len; 2518 } 2519 PMAP_UNLOCK(pm); 2520 } 2521