1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/cpu.h> 141 #include <machine/platform.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/smp.h> 148 #include <machine/sr.h> 149 #include <machine/mmuvar.h> 150 #include <machine/trap.h> 151 152 #define MOEA_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 157 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 159 160 struct ofw_map { 161 vm_offset_t om_va; 162 vm_size_t om_len; 163 vm_offset_t om_pa; 164 u_int om_mode; 165 }; 166 167 extern unsigned char _etext[]; 168 extern unsigned char _end[]; 169 170 /* 171 * Map of physical memory regions. 172 */ 173 static struct mem_region *regions; 174 static struct mem_region *pregions; 175 static u_int phys_avail_count; 176 static int regions_sz, pregions_sz; 177 static struct ofw_map *translations; 178 179 /* 180 * Lock for the pteg and pvo tables. 181 */ 182 struct mtx moea_table_mutex; 183 struct mtx moea_vsid_mutex; 184 185 /* tlbie instruction synchronization */ 186 static struct mtx tlbie_mtx; 187 188 /* 189 * PTEG data. 190 */ 191 static struct pteg *moea_pteg_table; 192 u_int moea_pteg_count; 193 u_int moea_pteg_mask; 194 195 /* 196 * PVO data. 197 */ 198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 199 struct pvo_head moea_pvo_kunmanaged = 200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 201 202 static struct rwlock_padalign pvh_global_lock; 203 204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 206 207 #define BPVO_POOL_SIZE 32768 208 static struct pvo_entry *moea_bpvo_pool; 209 static int moea_bpvo_pool_index = 0; 210 211 #define VSID_NBPW (sizeof(u_int32_t) * 8) 212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 213 214 static boolean_t moea_initialized = FALSE; 215 216 /* 217 * Statistics. 218 */ 219 u_int moea_pte_valid = 0; 220 u_int moea_pte_overflow = 0; 221 u_int moea_pte_replacements = 0; 222 u_int moea_pvo_entries = 0; 223 u_int moea_pvo_enter_calls = 0; 224 u_int moea_pvo_remove_calls = 0; 225 u_int moea_pte_spills = 0; 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 227 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 229 &moea_pte_overflow, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 231 &moea_pte_replacements, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 233 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 235 &moea_pvo_enter_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 237 &moea_pvo_remove_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 239 &moea_pte_spills, 0, ""); 240 241 /* 242 * Allocate physical memory for use in moea_bootstrap. 243 */ 244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 245 246 /* 247 * PTE calls. 248 */ 249 static int moea_pte_insert(u_int, struct pte *); 250 251 /* 252 * PVO calls. 253 */ 254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 255 vm_offset_t, vm_paddr_t, u_int, int); 256 static void moea_pvo_remove(struct pvo_entry *, int); 257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 259 260 /* 261 * Utility routines. 262 */ 263 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 264 vm_prot_t, u_int, int8_t); 265 static void moea_syncicache(vm_paddr_t, vm_size_t); 266 static boolean_t moea_query_bit(vm_page_t, int); 267 static u_int moea_clear_bit(vm_page_t, int); 268 static void moea_kremove(vm_offset_t); 269 int moea_pte_spill(vm_offset_t); 270 271 /* 272 * Kernel MMU interface 273 */ 274 void moea_clear_modify(vm_page_t); 275 void moea_copy_page(vm_page_t, vm_page_t); 276 void moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 277 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 278 int moea_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 279 int8_t); 280 void moea_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 void moea_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283 vm_paddr_t moea_extract(pmap_t, vm_offset_t); 284 vm_page_t moea_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 285 void moea_init(void); 286 boolean_t moea_is_modified(vm_page_t); 287 boolean_t moea_is_prefaultable(pmap_t, vm_offset_t); 288 boolean_t moea_is_referenced(vm_page_t); 289 int moea_ts_referenced(vm_page_t); 290 vm_offset_t moea_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 291 boolean_t moea_page_exists_quick(pmap_t, vm_page_t); 292 void moea_page_init(vm_page_t); 293 int moea_page_wired_mappings(vm_page_t); 294 int moea_pinit(pmap_t); 295 void moea_pinit0(pmap_t); 296 void moea_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(vm_offset_t, vm_page_t *, int); 298 void moea_qremove(vm_offset_t, int); 299 void moea_release(pmap_t); 300 void moea_remove(pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(vm_page_t); 302 void moea_remove_write(vm_page_t); 303 void moea_unwire(pmap_t, vm_offset_t, vm_offset_t); 304 void moea_zero_page(vm_page_t); 305 void moea_zero_page_area(vm_page_t, int, int); 306 void moea_activate(struct thread *); 307 void moea_deactivate(struct thread *); 308 void moea_cpu_bootstrap(int); 309 void moea_bootstrap(vm_offset_t, vm_offset_t); 310 void *moea_mapdev(vm_paddr_t, vm_size_t); 311 void *moea_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(vm_offset_t, vm_size_t); 313 vm_paddr_t moea_kextract(vm_offset_t); 314 void moea_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 315 void moea_kenter(vm_offset_t, vm_paddr_t); 316 void moea_page_set_memattr(vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(vm_paddr_t, vm_size_t); 318 static void moea_sync_icache(pmap_t, vm_offset_t, vm_size_t); 319 void moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va); 320 void moea_scan_init(void); 321 vm_offset_t moea_quick_enter_page(vm_page_t m); 322 void moea_quick_remove_page(vm_offset_t addr); 323 boolean_t moea_page_is_mapped(vm_page_t m); 324 static int moea_map_user_ptr(pmap_t pm, 325 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 326 static int moea_decode_kernel_ptr(vm_offset_t addr, 327 int *is_user, vm_offset_t *decoded_addr); 328 329 330 static struct pmap_funcs moea_methods = { 331 .clear_modify = moea_clear_modify, 332 .copy_page = moea_copy_page, 333 .copy_pages = moea_copy_pages, 334 .enter = moea_enter, 335 .enter_object = moea_enter_object, 336 .enter_quick = moea_enter_quick, 337 .extract = moea_extract, 338 .extract_and_hold = moea_extract_and_hold, 339 .init = moea_init, 340 .is_modified = moea_is_modified, 341 .is_prefaultable = moea_is_prefaultable, 342 .is_referenced = moea_is_referenced, 343 .ts_referenced = moea_ts_referenced, 344 .map = moea_map, 345 .page_exists_quick = moea_page_exists_quick, 346 .page_init = moea_page_init, 347 .page_wired_mappings = moea_page_wired_mappings, 348 .pinit = moea_pinit, 349 .pinit0 = moea_pinit0, 350 .protect = moea_protect, 351 .qenter = moea_qenter, 352 .qremove = moea_qremove, 353 .release = moea_release, 354 .remove = moea_remove, 355 .remove_all = moea_remove_all, 356 .remove_write = moea_remove_write, 357 .sync_icache = moea_sync_icache, 358 .unwire = moea_unwire, 359 .zero_page = moea_zero_page, 360 .zero_page_area = moea_zero_page_area, 361 .activate = moea_activate, 362 .deactivate = moea_deactivate, 363 .page_set_memattr = moea_page_set_memattr, 364 .quick_enter_page = moea_quick_enter_page, 365 .quick_remove_page = moea_quick_remove_page, 366 .page_is_mapped = moea_page_is_mapped, 367 368 /* Internal interfaces */ 369 .bootstrap = moea_bootstrap, 370 .cpu_bootstrap = moea_cpu_bootstrap, 371 .mapdev_attr = moea_mapdev_attr, 372 .mapdev = moea_mapdev, 373 .unmapdev = moea_unmapdev, 374 .kextract = moea_kextract, 375 .kenter = moea_kenter, 376 .kenter_attr = moea_kenter_attr, 377 .dev_direct_mapped = moea_dev_direct_mapped, 378 .dumpsys_pa_init = moea_scan_init, 379 .dumpsys_map_chunk = moea_dumpsys_map, 380 .map_user_ptr = moea_map_user_ptr, 381 .decode_kernel_ptr = moea_decode_kernel_ptr, 382 }; 383 384 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods); 385 386 static __inline uint32_t 387 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 388 { 389 uint32_t pte_lo; 390 int i; 391 392 if (ma != VM_MEMATTR_DEFAULT) { 393 switch (ma) { 394 case VM_MEMATTR_UNCACHEABLE: 395 return (PTE_I | PTE_G); 396 case VM_MEMATTR_CACHEABLE: 397 return (PTE_M); 398 case VM_MEMATTR_WRITE_COMBINING: 399 case VM_MEMATTR_WRITE_BACK: 400 case VM_MEMATTR_PREFETCHABLE: 401 return (PTE_I); 402 case VM_MEMATTR_WRITE_THROUGH: 403 return (PTE_W | PTE_M); 404 } 405 } 406 407 /* 408 * Assume the page is cache inhibited and access is guarded unless 409 * it's in our available memory array. 410 */ 411 pte_lo = PTE_I | PTE_G; 412 for (i = 0; i < pregions_sz; i++) { 413 if ((pa >= pregions[i].mr_start) && 414 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 415 pte_lo = PTE_M; 416 break; 417 } 418 } 419 420 return pte_lo; 421 } 422 423 /* 424 * Translate OFW translations into VM attributes. 425 */ 426 static __inline vm_memattr_t 427 moea_bootstrap_convert_wimg(uint32_t mode) 428 { 429 430 switch (mode) { 431 case (PTE_I | PTE_G): 432 /* PCI device memory */ 433 return VM_MEMATTR_UNCACHEABLE; 434 case (PTE_M): 435 /* Explicitly coherent */ 436 return VM_MEMATTR_CACHEABLE; 437 case 0: /* Default claim */ 438 case 2: /* Alternate PP bits set by OF for the original payload */ 439 /* "Normal" memory. */ 440 return VM_MEMATTR_DEFAULT; 441 442 default: 443 /* Err on the side of caution for unknowns */ 444 /* XXX should we panic instead? */ 445 return VM_MEMATTR_UNCACHEABLE; 446 } 447 } 448 449 static void 450 tlbie(vm_offset_t va) 451 { 452 453 mtx_lock_spin(&tlbie_mtx); 454 __asm __volatile("ptesync"); 455 __asm __volatile("tlbie %0" :: "r"(va)); 456 __asm __volatile("eieio; tlbsync; ptesync"); 457 mtx_unlock_spin(&tlbie_mtx); 458 } 459 460 static void 461 tlbia(void) 462 { 463 vm_offset_t va; 464 465 for (va = 0; va < 0x00040000; va += 0x00001000) { 466 __asm __volatile("tlbie %0" :: "r"(va)); 467 powerpc_sync(); 468 } 469 __asm __volatile("tlbsync"); 470 powerpc_sync(); 471 } 472 473 static __inline int 474 va_to_sr(u_int *sr, vm_offset_t va) 475 { 476 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 477 } 478 479 static __inline u_int 480 va_to_pteg(u_int sr, vm_offset_t addr) 481 { 482 u_int hash; 483 484 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 485 ADDR_PIDX_SHFT); 486 return (hash & moea_pteg_mask); 487 } 488 489 static __inline struct pvo_head * 490 vm_page_to_pvoh(vm_page_t m) 491 { 492 493 return (&m->md.mdpg_pvoh); 494 } 495 496 static __inline void 497 moea_attr_clear(vm_page_t m, int ptebit) 498 { 499 500 rw_assert(&pvh_global_lock, RA_WLOCKED); 501 m->md.mdpg_attrs &= ~ptebit; 502 } 503 504 static __inline int 505 moea_attr_fetch(vm_page_t m) 506 { 507 508 return (m->md.mdpg_attrs); 509 } 510 511 static __inline void 512 moea_attr_save(vm_page_t m, int ptebit) 513 { 514 515 rw_assert(&pvh_global_lock, RA_WLOCKED); 516 m->md.mdpg_attrs |= ptebit; 517 } 518 519 static __inline int 520 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 521 { 522 if (pt->pte_hi == pvo_pt->pte_hi) 523 return (1); 524 525 return (0); 526 } 527 528 static __inline int 529 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 530 { 531 return (pt->pte_hi & ~PTE_VALID) == 532 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 533 ((va >> ADDR_API_SHFT) & PTE_API) | which); 534 } 535 536 static __inline void 537 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 538 { 539 540 mtx_assert(&moea_table_mutex, MA_OWNED); 541 542 /* 543 * Construct a PTE. Default to IMB initially. Valid bit only gets 544 * set when the real pte is set in memory. 545 * 546 * Note: Don't set the valid bit for correct operation of tlb update. 547 */ 548 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 549 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 550 pt->pte_lo = pte_lo; 551 } 552 553 static __inline void 554 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 555 { 556 557 mtx_assert(&moea_table_mutex, MA_OWNED); 558 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 559 } 560 561 static __inline void 562 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 563 { 564 565 mtx_assert(&moea_table_mutex, MA_OWNED); 566 567 /* 568 * As shown in Section 7.6.3.2.3 569 */ 570 pt->pte_lo &= ~ptebit; 571 tlbie(va); 572 } 573 574 static __inline void 575 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 576 { 577 578 mtx_assert(&moea_table_mutex, MA_OWNED); 579 pvo_pt->pte_hi |= PTE_VALID; 580 581 /* 582 * Update the PTE as defined in section 7.6.3.1. 583 * Note that the REF/CHG bits are from pvo_pt and thus should have 584 * been saved so this routine can restore them (if desired). 585 */ 586 pt->pte_lo = pvo_pt->pte_lo; 587 powerpc_sync(); 588 pt->pte_hi = pvo_pt->pte_hi; 589 powerpc_sync(); 590 moea_pte_valid++; 591 } 592 593 static __inline void 594 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 595 { 596 597 mtx_assert(&moea_table_mutex, MA_OWNED); 598 pvo_pt->pte_hi &= ~PTE_VALID; 599 600 /* 601 * Force the reg & chg bits back into the PTEs. 602 */ 603 powerpc_sync(); 604 605 /* 606 * Invalidate the pte. 607 */ 608 pt->pte_hi &= ~PTE_VALID; 609 610 tlbie(va); 611 612 /* 613 * Save the reg & chg bits. 614 */ 615 moea_pte_synch(pt, pvo_pt); 616 moea_pte_valid--; 617 } 618 619 static __inline void 620 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 621 { 622 623 /* 624 * Invalidate the PTE 625 */ 626 moea_pte_unset(pt, pvo_pt, va); 627 moea_pte_set(pt, pvo_pt); 628 } 629 630 /* 631 * Quick sort callout for comparing memory regions. 632 */ 633 static int om_cmp(const void *a, const void *b); 634 635 static int 636 om_cmp(const void *a, const void *b) 637 { 638 const struct ofw_map *mapa; 639 const struct ofw_map *mapb; 640 641 mapa = a; 642 mapb = b; 643 if (mapa->om_pa < mapb->om_pa) 644 return (-1); 645 else if (mapa->om_pa > mapb->om_pa) 646 return (1); 647 else 648 return (0); 649 } 650 651 void 652 moea_cpu_bootstrap(int ap) 653 { 654 u_int sdr; 655 int i; 656 657 if (ap) { 658 powerpc_sync(); 659 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 660 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 661 isync(); 662 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 663 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 664 isync(); 665 } 666 667 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 668 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 669 isync(); 670 671 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 672 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 673 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 674 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 675 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 676 isync(); 677 678 for (i = 0; i < 16; i++) 679 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 680 powerpc_sync(); 681 682 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 683 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 684 isync(); 685 686 tlbia(); 687 } 688 689 void 690 moea_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 691 { 692 ihandle_t mmui; 693 phandle_t chosen, mmu; 694 int sz; 695 int i, j; 696 vm_size_t size, physsz, hwphyssz; 697 vm_offset_t pa, va, off; 698 void *dpcpu; 699 700 /* 701 * Map PCI memory space. 702 */ 703 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 704 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 705 706 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 707 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 708 709 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 710 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 711 712 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 713 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 714 715 powerpc_sync(); 716 717 /* map pci space */ 718 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 719 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 720 isync(); 721 722 /* set global direct map flag */ 723 hw_direct_map = 1; 724 725 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 726 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 727 728 for (i = 0; i < pregions_sz; i++) { 729 vm_offset_t pa; 730 vm_offset_t end; 731 732 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 733 pregions[i].mr_start, 734 pregions[i].mr_start + pregions[i].mr_size, 735 pregions[i].mr_size); 736 /* 737 * Install entries into the BAT table to allow all 738 * of physmem to be convered by on-demand BAT entries. 739 * The loop will sometimes set the same battable element 740 * twice, but that's fine since they won't be used for 741 * a while yet. 742 */ 743 pa = pregions[i].mr_start & 0xf0000000; 744 end = pregions[i].mr_start + pregions[i].mr_size; 745 do { 746 u_int n = pa >> ADDR_SR_SHFT; 747 748 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 749 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 750 pa += SEGMENT_LENGTH; 751 } while (pa < end); 752 } 753 754 if (PHYS_AVAIL_ENTRIES < regions_sz) 755 panic("moea_bootstrap: phys_avail too small"); 756 757 phys_avail_count = 0; 758 physsz = 0; 759 hwphyssz = 0; 760 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 761 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 762 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 763 regions[i].mr_start + regions[i].mr_size, 764 regions[i].mr_size); 765 if (hwphyssz != 0 && 766 (physsz + regions[i].mr_size) >= hwphyssz) { 767 if (physsz < hwphyssz) { 768 phys_avail[j] = regions[i].mr_start; 769 phys_avail[j + 1] = regions[i].mr_start + 770 hwphyssz - physsz; 771 physsz = hwphyssz; 772 phys_avail_count++; 773 } 774 break; 775 } 776 phys_avail[j] = regions[i].mr_start; 777 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 778 phys_avail_count++; 779 physsz += regions[i].mr_size; 780 } 781 782 /* Check for overlap with the kernel and exception vectors */ 783 for (j = 0; j < 2*phys_avail_count; j+=2) { 784 if (phys_avail[j] < EXC_LAST) 785 phys_avail[j] += EXC_LAST; 786 787 if (kernelstart >= phys_avail[j] && 788 kernelstart < phys_avail[j+1]) { 789 if (kernelend < phys_avail[j+1]) { 790 phys_avail[2*phys_avail_count] = 791 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 792 phys_avail[2*phys_avail_count + 1] = 793 phys_avail[j+1]; 794 phys_avail_count++; 795 } 796 797 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 798 } 799 800 if (kernelend >= phys_avail[j] && 801 kernelend < phys_avail[j+1]) { 802 if (kernelstart > phys_avail[j]) { 803 phys_avail[2*phys_avail_count] = phys_avail[j]; 804 phys_avail[2*phys_avail_count + 1] = 805 kernelstart & ~PAGE_MASK; 806 phys_avail_count++; 807 } 808 809 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 810 } 811 } 812 813 physmem = btoc(physsz); 814 815 /* 816 * Allocate PTEG table. 817 */ 818 #ifdef PTEGCOUNT 819 moea_pteg_count = PTEGCOUNT; 820 #else 821 moea_pteg_count = 0x1000; 822 823 while (moea_pteg_count < physmem) 824 moea_pteg_count <<= 1; 825 826 moea_pteg_count >>= 1; 827 #endif /* PTEGCOUNT */ 828 829 size = moea_pteg_count * sizeof(struct pteg); 830 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 831 size); 832 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 833 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 834 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 835 moea_pteg_mask = moea_pteg_count - 1; 836 837 /* 838 * Allocate pv/overflow lists. 839 */ 840 size = sizeof(struct pvo_head) * moea_pteg_count; 841 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 842 PAGE_SIZE); 843 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 844 for (i = 0; i < moea_pteg_count; i++) 845 LIST_INIT(&moea_pvo_table[i]); 846 847 /* 848 * Initialize the lock that synchronizes access to the pteg and pvo 849 * tables. 850 */ 851 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 852 MTX_RECURSE); 853 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 854 855 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 856 857 /* 858 * Initialise the unmanaged pvo pool. 859 */ 860 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 861 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 862 moea_bpvo_pool_index = 0; 863 864 /* 865 * Make sure kernel vsid is allocated as well as VSID 0. 866 */ 867 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 868 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 869 moea_vsid_bitmap[0] |= 1; 870 871 /* 872 * Initialize the kernel pmap (which is statically allocated). 873 */ 874 PMAP_LOCK_INIT(kernel_pmap); 875 for (i = 0; i < 16; i++) 876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 877 CPU_FILL(&kernel_pmap->pm_active); 878 RB_INIT(&kernel_pmap->pmap_pvo); 879 880 /* 881 * Initialize the global pv list lock. 882 */ 883 rw_init(&pvh_global_lock, "pmap pv global"); 884 885 /* 886 * Set up the Open Firmware mappings 887 */ 888 chosen = OF_finddevice("/chosen"); 889 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 890 (mmu = OF_instance_to_package(mmui)) != -1 && 891 (sz = OF_getproplen(mmu, "translations")) != -1) { 892 translations = NULL; 893 for (i = 0; phys_avail[i] != 0; i += 2) { 894 if (phys_avail[i + 1] >= sz) { 895 translations = (struct ofw_map *)phys_avail[i]; 896 break; 897 } 898 } 899 if (translations == NULL) 900 panic("moea_bootstrap: no space to copy translations"); 901 bzero(translations, sz); 902 if (OF_getprop(mmu, "translations", translations, sz) == -1) 903 panic("moea_bootstrap: can't get ofw translations"); 904 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 905 sz /= sizeof(*translations); 906 qsort(translations, sz, sizeof (*translations), om_cmp); 907 for (i = 0; i < sz; i++) { 908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 909 translations[i].om_pa, translations[i].om_va, 910 translations[i].om_len); 911 912 /* 913 * If the mapping is 1:1, let the RAM and device 914 * on-demand BAT tables take care of the translation. 915 * 916 * However, always enter mappings for segment 16, 917 * which is mixed-protection and therefore not 918 * compatible with a BAT entry. 919 */ 920 if ((translations[i].om_va >> ADDR_SR_SHFT) != 0xf && 921 translations[i].om_va == translations[i].om_pa) 922 continue; 923 924 /* Enter the pages */ 925 for (off = 0; off < translations[i].om_len; 926 off += PAGE_SIZE) 927 moea_kenter_attr(translations[i].om_va + off, 928 translations[i].om_pa + off, 929 moea_bootstrap_convert_wimg(translations[i].om_mode)); 930 } 931 } 932 933 /* 934 * Calculate the last available physical address. 935 */ 936 for (i = 0; phys_avail[i + 2] != 0; i += 2) 937 ; 938 Maxmem = powerpc_btop(phys_avail[i + 1]); 939 940 moea_cpu_bootstrap(0); 941 mtmsr(mfmsr() | PSL_DR | PSL_IR); 942 pmap_bootstrapped++; 943 944 /* 945 * Set the start and end of kva. 946 */ 947 virtual_avail = VM_MIN_KERNEL_ADDRESS; 948 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 949 950 /* 951 * Allocate a kernel stack with a guard page for thread0 and map it 952 * into the kernel page map. 953 */ 954 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 955 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 956 virtual_avail = va + kstack_pages * PAGE_SIZE; 957 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 958 thread0.td_kstack = va; 959 thread0.td_kstack_pages = kstack_pages; 960 for (i = 0; i < kstack_pages; i++) { 961 moea_kenter(va, pa); 962 pa += PAGE_SIZE; 963 va += PAGE_SIZE; 964 } 965 966 /* 967 * Allocate virtual address space for the message buffer. 968 */ 969 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 970 msgbufp = (struct msgbuf *)virtual_avail; 971 va = virtual_avail; 972 virtual_avail += round_page(msgbufsize); 973 while (va < virtual_avail) { 974 moea_kenter(va, pa); 975 pa += PAGE_SIZE; 976 va += PAGE_SIZE; 977 } 978 979 /* 980 * Allocate virtual address space for the dynamic percpu area. 981 */ 982 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 983 dpcpu = (void *)virtual_avail; 984 va = virtual_avail; 985 virtual_avail += DPCPU_SIZE; 986 while (va < virtual_avail) { 987 moea_kenter(va, pa); 988 pa += PAGE_SIZE; 989 va += PAGE_SIZE; 990 } 991 dpcpu_init(dpcpu, 0); 992 } 993 994 /* 995 * Activate a user pmap. The pmap must be activated before it's address 996 * space can be accessed in any way. 997 */ 998 void 999 moea_activate(struct thread *td) 1000 { 1001 pmap_t pm, pmr; 1002 1003 /* 1004 * Load all the data we need up front to encourage the compiler to 1005 * not issue any loads while we have interrupts disabled below. 1006 */ 1007 pm = &td->td_proc->p_vmspace->vm_pmap; 1008 pmr = pm->pmap_phys; 1009 1010 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1011 PCPU_SET(curpmap, pmr); 1012 1013 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1014 } 1015 1016 void 1017 moea_deactivate(struct thread *td) 1018 { 1019 pmap_t pm; 1020 1021 pm = &td->td_proc->p_vmspace->vm_pmap; 1022 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1023 PCPU_SET(curpmap, NULL); 1024 } 1025 1026 void 1027 moea_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1028 { 1029 struct pvo_entry key, *pvo; 1030 1031 PMAP_LOCK(pm); 1032 key.pvo_vaddr = sva; 1033 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1034 pvo != NULL && PVO_VADDR(pvo) < eva; 1035 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1036 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1037 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1038 pvo->pvo_vaddr &= ~PVO_WIRED; 1039 pm->pm_stats.wired_count--; 1040 } 1041 PMAP_UNLOCK(pm); 1042 } 1043 1044 void 1045 moea_copy_page(vm_page_t msrc, vm_page_t mdst) 1046 { 1047 vm_offset_t dst; 1048 vm_offset_t src; 1049 1050 dst = VM_PAGE_TO_PHYS(mdst); 1051 src = VM_PAGE_TO_PHYS(msrc); 1052 1053 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1054 } 1055 1056 void 1057 moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1058 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1059 { 1060 void *a_cp, *b_cp; 1061 vm_offset_t a_pg_offset, b_pg_offset; 1062 int cnt; 1063 1064 while (xfersize > 0) { 1065 a_pg_offset = a_offset & PAGE_MASK; 1066 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1067 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1068 a_pg_offset; 1069 b_pg_offset = b_offset & PAGE_MASK; 1070 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1071 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1072 b_pg_offset; 1073 bcopy(a_cp, b_cp, cnt); 1074 a_offset += cnt; 1075 b_offset += cnt; 1076 xfersize -= cnt; 1077 } 1078 } 1079 1080 /* 1081 * Zero a page of physical memory by temporarily mapping it into the tlb. 1082 */ 1083 void 1084 moea_zero_page(vm_page_t m) 1085 { 1086 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1087 1088 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1089 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1090 } 1091 1092 void 1093 moea_zero_page_area(vm_page_t m, int off, int size) 1094 { 1095 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1096 void *va = (void *)(pa + off); 1097 1098 bzero(va, size); 1099 } 1100 1101 vm_offset_t 1102 moea_quick_enter_page(vm_page_t m) 1103 { 1104 1105 return (VM_PAGE_TO_PHYS(m)); 1106 } 1107 1108 void 1109 moea_quick_remove_page(vm_offset_t addr) 1110 { 1111 } 1112 1113 boolean_t 1114 moea_page_is_mapped(vm_page_t m) 1115 { 1116 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1117 } 1118 1119 /* 1120 * Map the given physical page at the specified virtual address in the 1121 * target pmap with the protection requested. If specified the page 1122 * will be wired down. 1123 */ 1124 int 1125 moea_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1126 u_int flags, int8_t psind) 1127 { 1128 int error; 1129 1130 for (;;) { 1131 rw_wlock(&pvh_global_lock); 1132 PMAP_LOCK(pmap); 1133 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1134 rw_wunlock(&pvh_global_lock); 1135 PMAP_UNLOCK(pmap); 1136 if (error != ENOMEM) 1137 return (KERN_SUCCESS); 1138 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1139 return (KERN_RESOURCE_SHORTAGE); 1140 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1141 vm_wait(NULL); 1142 } 1143 } 1144 1145 /* 1146 * Map the given physical page at the specified virtual address in the 1147 * target pmap with the protection requested. If specified the page 1148 * will be wired down. 1149 * 1150 * The global pvh and pmap must be locked. 1151 */ 1152 static int 1153 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1154 u_int flags, int8_t psind __unused) 1155 { 1156 struct pvo_head *pvo_head; 1157 uma_zone_t zone; 1158 u_int pte_lo, pvo_flags; 1159 int error; 1160 1161 if (pmap_bootstrapped) 1162 rw_assert(&pvh_global_lock, RA_WLOCKED); 1163 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1164 if ((m->oflags & VPO_UNMANAGED) == 0) { 1165 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1166 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1167 else 1168 VM_OBJECT_ASSERT_LOCKED(m->object); 1169 } 1170 1171 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1172 pvo_head = &moea_pvo_kunmanaged; 1173 zone = moea_upvo_zone; 1174 pvo_flags = 0; 1175 } else { 1176 pvo_head = vm_page_to_pvoh(m); 1177 zone = moea_mpvo_zone; 1178 pvo_flags = PVO_MANAGED; 1179 } 1180 1181 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1182 1183 if (prot & VM_PROT_WRITE) { 1184 pte_lo |= PTE_BW; 1185 if (pmap_bootstrapped && 1186 (m->oflags & VPO_UNMANAGED) == 0) 1187 vm_page_aflag_set(m, PGA_WRITEABLE); 1188 } else 1189 pte_lo |= PTE_BR; 1190 1191 if ((flags & PMAP_ENTER_WIRED) != 0) 1192 pvo_flags |= PVO_WIRED; 1193 1194 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1195 pte_lo, pvo_flags); 1196 1197 /* 1198 * Flush the real page from the instruction cache. This has be done 1199 * for all user mappings to prevent information leakage via the 1200 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1201 * mapping for a page. 1202 */ 1203 if (pmap != kernel_pmap && error == ENOENT && 1204 (pte_lo & (PTE_I | PTE_G)) == 0) 1205 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1206 1207 return (error); 1208 } 1209 1210 /* 1211 * Maps a sequence of resident pages belonging to the same object. 1212 * The sequence begins with the given page m_start. This page is 1213 * mapped at the given virtual address start. Each subsequent page is 1214 * mapped at a virtual address that is offset from start by the same 1215 * amount as the page is offset from m_start within the object. The 1216 * last page in the sequence is the page with the largest offset from 1217 * m_start that can be mapped at a virtual address less than the given 1218 * virtual address end. Not every virtual page between start and end 1219 * is mapped; only those for which a resident page exists with the 1220 * corresponding offset from m_start are mapped. 1221 */ 1222 void 1223 moea_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1224 vm_page_t m_start, vm_prot_t prot) 1225 { 1226 vm_page_t m; 1227 vm_pindex_t diff, psize; 1228 1229 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1230 1231 psize = atop(end - start); 1232 m = m_start; 1233 rw_wlock(&pvh_global_lock); 1234 PMAP_LOCK(pm); 1235 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1236 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1237 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_QUICK_LOCKED, 1238 0); 1239 m = TAILQ_NEXT(m, listq); 1240 } 1241 rw_wunlock(&pvh_global_lock); 1242 PMAP_UNLOCK(pm); 1243 } 1244 1245 void 1246 moea_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1247 vm_prot_t prot) 1248 { 1249 1250 rw_wlock(&pvh_global_lock); 1251 PMAP_LOCK(pm); 1252 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1253 PMAP_ENTER_QUICK_LOCKED, 0); 1254 rw_wunlock(&pvh_global_lock); 1255 PMAP_UNLOCK(pm); 1256 } 1257 1258 vm_paddr_t 1259 moea_extract(pmap_t pm, vm_offset_t va) 1260 { 1261 struct pvo_entry *pvo; 1262 vm_paddr_t pa; 1263 1264 PMAP_LOCK(pm); 1265 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1266 if (pvo == NULL) 1267 pa = 0; 1268 else 1269 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1270 PMAP_UNLOCK(pm); 1271 return (pa); 1272 } 1273 1274 /* 1275 * Atomically extract and hold the physical page with the given 1276 * pmap and virtual address pair if that mapping permits the given 1277 * protection. 1278 */ 1279 vm_page_t 1280 moea_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1281 { 1282 struct pvo_entry *pvo; 1283 vm_page_t m; 1284 1285 m = NULL; 1286 PMAP_LOCK(pmap); 1287 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1288 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1289 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1290 (prot & VM_PROT_WRITE) == 0)) { 1291 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1292 if (!vm_page_wire_mapped(m)) 1293 m = NULL; 1294 } 1295 PMAP_UNLOCK(pmap); 1296 return (m); 1297 } 1298 1299 void 1300 moea_init() 1301 { 1302 1303 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1304 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1305 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1306 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1307 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1308 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1309 moea_initialized = TRUE; 1310 } 1311 1312 boolean_t 1313 moea_is_referenced(vm_page_t m) 1314 { 1315 boolean_t rv; 1316 1317 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1318 ("moea_is_referenced: page %p is not managed", m)); 1319 rw_wlock(&pvh_global_lock); 1320 rv = moea_query_bit(m, PTE_REF); 1321 rw_wunlock(&pvh_global_lock); 1322 return (rv); 1323 } 1324 1325 boolean_t 1326 moea_is_modified(vm_page_t m) 1327 { 1328 boolean_t rv; 1329 1330 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1331 ("moea_is_modified: page %p is not managed", m)); 1332 1333 /* 1334 * If the page is not busied then this check is racy. 1335 */ 1336 if (!pmap_page_is_write_mapped(m)) 1337 return (FALSE); 1338 1339 rw_wlock(&pvh_global_lock); 1340 rv = moea_query_bit(m, PTE_CHG); 1341 rw_wunlock(&pvh_global_lock); 1342 return (rv); 1343 } 1344 1345 boolean_t 1346 moea_is_prefaultable(pmap_t pmap, vm_offset_t va) 1347 { 1348 struct pvo_entry *pvo; 1349 boolean_t rv; 1350 1351 PMAP_LOCK(pmap); 1352 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1353 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1354 PMAP_UNLOCK(pmap); 1355 return (rv); 1356 } 1357 1358 void 1359 moea_clear_modify(vm_page_t m) 1360 { 1361 1362 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1363 ("moea_clear_modify: page %p is not managed", m)); 1364 vm_page_assert_busied(m); 1365 1366 if (!pmap_page_is_write_mapped(m)) 1367 return; 1368 rw_wlock(&pvh_global_lock); 1369 moea_clear_bit(m, PTE_CHG); 1370 rw_wunlock(&pvh_global_lock); 1371 } 1372 1373 /* 1374 * Clear the write and modified bits in each of the given page's mappings. 1375 */ 1376 void 1377 moea_remove_write(vm_page_t m) 1378 { 1379 struct pvo_entry *pvo; 1380 struct pte *pt; 1381 pmap_t pmap; 1382 u_int lo; 1383 1384 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1385 ("moea_remove_write: page %p is not managed", m)); 1386 vm_page_assert_busied(m); 1387 1388 if (!pmap_page_is_write_mapped(m)) 1389 return; 1390 rw_wlock(&pvh_global_lock); 1391 lo = moea_attr_fetch(m); 1392 powerpc_sync(); 1393 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1394 pmap = pvo->pvo_pmap; 1395 PMAP_LOCK(pmap); 1396 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1397 pt = moea_pvo_to_pte(pvo, -1); 1398 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1399 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1400 if (pt != NULL) { 1401 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1402 lo |= pvo->pvo_pte.pte.pte_lo; 1403 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1404 moea_pte_change(pt, &pvo->pvo_pte.pte, 1405 pvo->pvo_vaddr); 1406 mtx_unlock(&moea_table_mutex); 1407 } 1408 } 1409 PMAP_UNLOCK(pmap); 1410 } 1411 if ((lo & PTE_CHG) != 0) { 1412 moea_attr_clear(m, PTE_CHG); 1413 vm_page_dirty(m); 1414 } 1415 vm_page_aflag_clear(m, PGA_WRITEABLE); 1416 rw_wunlock(&pvh_global_lock); 1417 } 1418 1419 /* 1420 * moea_ts_referenced: 1421 * 1422 * Return a count of reference bits for a page, clearing those bits. 1423 * It is not necessary for every reference bit to be cleared, but it 1424 * is necessary that 0 only be returned when there are truly no 1425 * reference bits set. 1426 * 1427 * XXX: The exact number of bits to check and clear is a matter that 1428 * should be tested and standardized at some point in the future for 1429 * optimal aging of shared pages. 1430 */ 1431 int 1432 moea_ts_referenced(vm_page_t m) 1433 { 1434 int count; 1435 1436 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1437 ("moea_ts_referenced: page %p is not managed", m)); 1438 rw_wlock(&pvh_global_lock); 1439 count = moea_clear_bit(m, PTE_REF); 1440 rw_wunlock(&pvh_global_lock); 1441 return (count); 1442 } 1443 1444 /* 1445 * Modify the WIMG settings of all mappings for a page. 1446 */ 1447 void 1448 moea_page_set_memattr(vm_page_t m, vm_memattr_t ma) 1449 { 1450 struct pvo_entry *pvo; 1451 struct pvo_head *pvo_head; 1452 struct pte *pt; 1453 pmap_t pmap; 1454 u_int lo; 1455 1456 if ((m->oflags & VPO_UNMANAGED) != 0) { 1457 m->md.mdpg_cache_attrs = ma; 1458 return; 1459 } 1460 1461 rw_wlock(&pvh_global_lock); 1462 pvo_head = vm_page_to_pvoh(m); 1463 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1464 1465 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1466 pmap = pvo->pvo_pmap; 1467 PMAP_LOCK(pmap); 1468 pt = moea_pvo_to_pte(pvo, -1); 1469 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1470 pvo->pvo_pte.pte.pte_lo |= lo; 1471 if (pt != NULL) { 1472 moea_pte_change(pt, &pvo->pvo_pte.pte, 1473 pvo->pvo_vaddr); 1474 if (pvo->pvo_pmap == kernel_pmap) 1475 isync(); 1476 } 1477 mtx_unlock(&moea_table_mutex); 1478 PMAP_UNLOCK(pmap); 1479 } 1480 m->md.mdpg_cache_attrs = ma; 1481 rw_wunlock(&pvh_global_lock); 1482 } 1483 1484 /* 1485 * Map a wired page into kernel virtual address space. 1486 */ 1487 void 1488 moea_kenter(vm_offset_t va, vm_paddr_t pa) 1489 { 1490 1491 moea_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1492 } 1493 1494 void 1495 moea_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1496 { 1497 u_int pte_lo; 1498 int error; 1499 1500 #if 0 1501 if (va < VM_MIN_KERNEL_ADDRESS) 1502 panic("moea_kenter: attempt to enter non-kernel address %#x", 1503 va); 1504 #endif 1505 1506 pte_lo = moea_calc_wimg(pa, ma); 1507 1508 PMAP_LOCK(kernel_pmap); 1509 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1510 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1511 1512 if (error != 0 && error != ENOENT) 1513 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1514 pa, error); 1515 1516 PMAP_UNLOCK(kernel_pmap); 1517 } 1518 1519 /* 1520 * Extract the physical page address associated with the given kernel virtual 1521 * address. 1522 */ 1523 vm_paddr_t 1524 moea_kextract(vm_offset_t va) 1525 { 1526 struct pvo_entry *pvo; 1527 vm_paddr_t pa; 1528 1529 /* 1530 * Allow direct mappings on 32-bit OEA 1531 */ 1532 if (va < VM_MIN_KERNEL_ADDRESS) { 1533 return (va); 1534 } 1535 1536 PMAP_LOCK(kernel_pmap); 1537 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1538 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1539 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1540 PMAP_UNLOCK(kernel_pmap); 1541 return (pa); 1542 } 1543 1544 /* 1545 * Remove a wired page from kernel virtual address space. 1546 */ 1547 void 1548 moea_kremove(vm_offset_t va) 1549 { 1550 1551 moea_remove(kernel_pmap, va, va + PAGE_SIZE); 1552 } 1553 1554 /* 1555 * Provide a kernel pointer corresponding to a given userland pointer. 1556 * The returned pointer is valid until the next time this function is 1557 * called in this thread. This is used internally in copyin/copyout. 1558 */ 1559 int 1560 moea_map_user_ptr(pmap_t pm, volatile const void *uaddr, 1561 void **kaddr, size_t ulen, size_t *klen) 1562 { 1563 size_t l; 1564 register_t vsid; 1565 1566 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1567 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1568 if (l > ulen) 1569 l = ulen; 1570 if (klen) 1571 *klen = l; 1572 else if (l != ulen) 1573 return (EFAULT); 1574 1575 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1576 1577 /* Mark segment no-execute */ 1578 vsid |= SR_N; 1579 1580 /* If we have already set this VSID, we can just return */ 1581 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1582 return (0); 1583 1584 __asm __volatile("isync"); 1585 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1586 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1587 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1588 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1589 1590 return (0); 1591 } 1592 1593 /* 1594 * Figure out where a given kernel pointer (usually in a fault) points 1595 * to from the VM's perspective, potentially remapping into userland's 1596 * address space. 1597 */ 1598 static int 1599 moea_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1600 vm_offset_t *decoded_addr) 1601 { 1602 vm_offset_t user_sr; 1603 1604 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1605 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1606 addr &= ADDR_PIDX | ADDR_POFF; 1607 addr |= user_sr << ADDR_SR_SHFT; 1608 *decoded_addr = addr; 1609 *is_user = 1; 1610 } else { 1611 *decoded_addr = addr; 1612 *is_user = 0; 1613 } 1614 1615 return (0); 1616 } 1617 1618 /* 1619 * Map a range of physical addresses into kernel virtual address space. 1620 * 1621 * The value passed in *virt is a suggested virtual address for the mapping. 1622 * Architectures which can support a direct-mapped physical to virtual region 1623 * can return the appropriate address within that region, leaving '*virt' 1624 * unchanged. We cannot and therefore do not; *virt is updated with the 1625 * first usable address after the mapped region. 1626 */ 1627 vm_offset_t 1628 moea_map(vm_offset_t *virt, vm_paddr_t pa_start, 1629 vm_paddr_t pa_end, int prot) 1630 { 1631 vm_offset_t sva, va; 1632 1633 sva = *virt; 1634 va = sva; 1635 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1636 moea_kenter(va, pa_start); 1637 *virt = va; 1638 return (sva); 1639 } 1640 1641 /* 1642 * Returns true if the pmap's pv is one of the first 1643 * 16 pvs linked to from this page. This count may 1644 * be changed upwards or downwards in the future; it 1645 * is only necessary that true be returned for a small 1646 * subset of pmaps for proper page aging. 1647 */ 1648 boolean_t 1649 moea_page_exists_quick(pmap_t pmap, vm_page_t m) 1650 { 1651 int loops; 1652 struct pvo_entry *pvo; 1653 boolean_t rv; 1654 1655 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1656 ("moea_page_exists_quick: page %p is not managed", m)); 1657 loops = 0; 1658 rv = FALSE; 1659 rw_wlock(&pvh_global_lock); 1660 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1661 if (pvo->pvo_pmap == pmap) { 1662 rv = TRUE; 1663 break; 1664 } 1665 if (++loops >= 16) 1666 break; 1667 } 1668 rw_wunlock(&pvh_global_lock); 1669 return (rv); 1670 } 1671 1672 void 1673 moea_page_init(vm_page_t m) 1674 { 1675 1676 m->md.mdpg_attrs = 0; 1677 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1678 LIST_INIT(&m->md.mdpg_pvoh); 1679 } 1680 1681 /* 1682 * Return the number of managed mappings to the given physical page 1683 * that are wired. 1684 */ 1685 int 1686 moea_page_wired_mappings(vm_page_t m) 1687 { 1688 struct pvo_entry *pvo; 1689 int count; 1690 1691 count = 0; 1692 if ((m->oflags & VPO_UNMANAGED) != 0) 1693 return (count); 1694 rw_wlock(&pvh_global_lock); 1695 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1696 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1697 count++; 1698 rw_wunlock(&pvh_global_lock); 1699 return (count); 1700 } 1701 1702 static u_int moea_vsidcontext; 1703 1704 int 1705 moea_pinit(pmap_t pmap) 1706 { 1707 int i, mask; 1708 u_int entropy; 1709 1710 RB_INIT(&pmap->pmap_pvo); 1711 1712 entropy = 0; 1713 __asm __volatile("mftb %0" : "=r"(entropy)); 1714 1715 if ((pmap->pmap_phys = (pmap_t)moea_kextract((vm_offset_t)pmap)) 1716 == NULL) { 1717 pmap->pmap_phys = pmap; 1718 } 1719 1720 1721 mtx_lock(&moea_vsid_mutex); 1722 /* 1723 * Allocate some segment registers for this pmap. 1724 */ 1725 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1726 u_int hash, n; 1727 1728 /* 1729 * Create a new value by mutiplying by a prime and adding in 1730 * entropy from the timebase register. This is to make the 1731 * VSID more random so that the PT hash function collides 1732 * less often. (Note that the prime casues gcc to do shifts 1733 * instead of a multiply.) 1734 */ 1735 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1736 hash = moea_vsidcontext & (NPMAPS - 1); 1737 if (hash == 0) /* 0 is special, avoid it */ 1738 continue; 1739 n = hash >> 5; 1740 mask = 1 << (hash & (VSID_NBPW - 1)); 1741 hash = (moea_vsidcontext & 0xfffff); 1742 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1743 /* anything free in this bucket? */ 1744 if (moea_vsid_bitmap[n] == 0xffffffff) { 1745 entropy = (moea_vsidcontext >> 20); 1746 continue; 1747 } 1748 i = ffs(~moea_vsid_bitmap[n]) - 1; 1749 mask = 1 << i; 1750 hash &= rounddown2(0xfffff, VSID_NBPW); 1751 hash |= i; 1752 } 1753 KASSERT(!(moea_vsid_bitmap[n] & mask), 1754 ("Allocating in-use VSID group %#x\n", hash)); 1755 moea_vsid_bitmap[n] |= mask; 1756 for (i = 0; i < 16; i++) 1757 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1758 mtx_unlock(&moea_vsid_mutex); 1759 return (1); 1760 } 1761 1762 mtx_unlock(&moea_vsid_mutex); 1763 panic("moea_pinit: out of segments"); 1764 } 1765 1766 /* 1767 * Initialize the pmap associated with process 0. 1768 */ 1769 void 1770 moea_pinit0(pmap_t pm) 1771 { 1772 1773 PMAP_LOCK_INIT(pm); 1774 moea_pinit(pm); 1775 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1776 } 1777 1778 /* 1779 * Set the physical protection on the specified range of this map as requested. 1780 */ 1781 void 1782 moea_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1783 vm_prot_t prot) 1784 { 1785 struct pvo_entry *pvo, *tpvo, key; 1786 struct pte *pt; 1787 1788 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1789 ("moea_protect: non current pmap")); 1790 1791 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1792 moea_remove(pm, sva, eva); 1793 return; 1794 } 1795 1796 rw_wlock(&pvh_global_lock); 1797 PMAP_LOCK(pm); 1798 key.pvo_vaddr = sva; 1799 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1800 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1801 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1802 1803 /* 1804 * Grab the PTE pointer before we diddle with the cached PTE 1805 * copy. 1806 */ 1807 pt = moea_pvo_to_pte(pvo, -1); 1808 /* 1809 * Change the protection of the page. 1810 */ 1811 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1812 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1813 1814 /* 1815 * If the PVO is in the page table, update that pte as well. 1816 */ 1817 if (pt != NULL) { 1818 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1819 mtx_unlock(&moea_table_mutex); 1820 } 1821 } 1822 rw_wunlock(&pvh_global_lock); 1823 PMAP_UNLOCK(pm); 1824 } 1825 1826 /* 1827 * Map a list of wired pages into kernel virtual address space. This is 1828 * intended for temporary mappings which do not need page modification or 1829 * references recorded. Existing mappings in the region are overwritten. 1830 */ 1831 void 1832 moea_qenter(vm_offset_t sva, vm_page_t *m, int count) 1833 { 1834 vm_offset_t va; 1835 1836 va = sva; 1837 while (count-- > 0) { 1838 moea_kenter(va, VM_PAGE_TO_PHYS(*m)); 1839 va += PAGE_SIZE; 1840 m++; 1841 } 1842 } 1843 1844 /* 1845 * Remove page mappings from kernel virtual address space. Intended for 1846 * temporary mappings entered by moea_qenter. 1847 */ 1848 void 1849 moea_qremove(vm_offset_t sva, int count) 1850 { 1851 vm_offset_t va; 1852 1853 va = sva; 1854 while (count-- > 0) { 1855 moea_kremove(va); 1856 va += PAGE_SIZE; 1857 } 1858 } 1859 1860 void 1861 moea_release(pmap_t pmap) 1862 { 1863 int idx, mask; 1864 1865 /* 1866 * Free segment register's VSID 1867 */ 1868 if (pmap->pm_sr[0] == 0) 1869 panic("moea_release"); 1870 1871 mtx_lock(&moea_vsid_mutex); 1872 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1873 mask = 1 << (idx % VSID_NBPW); 1874 idx /= VSID_NBPW; 1875 moea_vsid_bitmap[idx] &= ~mask; 1876 mtx_unlock(&moea_vsid_mutex); 1877 } 1878 1879 /* 1880 * Remove the given range of addresses from the specified map. 1881 */ 1882 void 1883 moea_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1884 { 1885 struct pvo_entry *pvo, *tpvo, key; 1886 1887 rw_wlock(&pvh_global_lock); 1888 PMAP_LOCK(pm); 1889 key.pvo_vaddr = sva; 1890 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1891 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1892 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1893 moea_pvo_remove(pvo, -1); 1894 } 1895 PMAP_UNLOCK(pm); 1896 rw_wunlock(&pvh_global_lock); 1897 } 1898 1899 /* 1900 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1901 * will reflect changes in pte's back to the vm_page. 1902 */ 1903 void 1904 moea_remove_all(vm_page_t m) 1905 { 1906 struct pvo_head *pvo_head; 1907 struct pvo_entry *pvo, *next_pvo; 1908 pmap_t pmap; 1909 1910 rw_wlock(&pvh_global_lock); 1911 pvo_head = vm_page_to_pvoh(m); 1912 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1913 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1914 1915 pmap = pvo->pvo_pmap; 1916 PMAP_LOCK(pmap); 1917 moea_pvo_remove(pvo, -1); 1918 PMAP_UNLOCK(pmap); 1919 } 1920 if ((m->a.flags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1921 moea_attr_clear(m, PTE_CHG); 1922 vm_page_dirty(m); 1923 } 1924 vm_page_aflag_clear(m, PGA_WRITEABLE); 1925 rw_wunlock(&pvh_global_lock); 1926 } 1927 1928 /* 1929 * Allocate a physical page of memory directly from the phys_avail map. 1930 * Can only be called from moea_bootstrap before avail start and end are 1931 * calculated. 1932 */ 1933 static vm_offset_t 1934 moea_bootstrap_alloc(vm_size_t size, u_int align) 1935 { 1936 vm_offset_t s, e; 1937 int i, j; 1938 1939 size = round_page(size); 1940 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1941 if (align != 0) 1942 s = roundup2(phys_avail[i], align); 1943 else 1944 s = phys_avail[i]; 1945 e = s + size; 1946 1947 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1948 continue; 1949 1950 if (s == phys_avail[i]) { 1951 phys_avail[i] += size; 1952 } else if (e == phys_avail[i + 1]) { 1953 phys_avail[i + 1] -= size; 1954 } else { 1955 for (j = phys_avail_count * 2; j > i; j -= 2) { 1956 phys_avail[j] = phys_avail[j - 2]; 1957 phys_avail[j + 1] = phys_avail[j - 1]; 1958 } 1959 1960 phys_avail[i + 3] = phys_avail[i + 1]; 1961 phys_avail[i + 1] = s; 1962 phys_avail[i + 2] = e; 1963 phys_avail_count++; 1964 } 1965 1966 return (s); 1967 } 1968 panic("moea_bootstrap_alloc: could not allocate memory"); 1969 } 1970 1971 static void 1972 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1973 { 1974 __syncicache((void *)pa, len); 1975 } 1976 1977 static int 1978 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1979 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1980 { 1981 struct pvo_entry *pvo; 1982 u_int sr; 1983 int first; 1984 u_int ptegidx; 1985 int i; 1986 int bootstrap; 1987 1988 moea_pvo_enter_calls++; 1989 first = 0; 1990 bootstrap = 0; 1991 1992 /* 1993 * Compute the PTE Group index. 1994 */ 1995 va &= ~ADDR_POFF; 1996 sr = va_to_sr(pm->pm_sr, va); 1997 ptegidx = va_to_pteg(sr, va); 1998 1999 /* 2000 * Remove any existing mapping for this page. Reuse the pvo entry if 2001 * there is a mapping. 2002 */ 2003 mtx_lock(&moea_table_mutex); 2004 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2005 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2006 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 2007 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2008 (pte_lo & PTE_PP)) { 2009 /* 2010 * The PTE is not changing. Instead, this may 2011 * be a request to change the mapping's wired 2012 * attribute. 2013 */ 2014 mtx_unlock(&moea_table_mutex); 2015 if ((flags & PVO_WIRED) != 0 && 2016 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2017 pvo->pvo_vaddr |= PVO_WIRED; 2018 pm->pm_stats.wired_count++; 2019 } else if ((flags & PVO_WIRED) == 0 && 2020 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2021 pvo->pvo_vaddr &= ~PVO_WIRED; 2022 pm->pm_stats.wired_count--; 2023 } 2024 return (0); 2025 } 2026 moea_pvo_remove(pvo, -1); 2027 break; 2028 } 2029 } 2030 2031 /* 2032 * If we aren't overwriting a mapping, try to allocate. 2033 */ 2034 if (moea_initialized) { 2035 pvo = uma_zalloc(zone, M_NOWAIT); 2036 } else { 2037 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2038 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2039 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2040 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2041 } 2042 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2043 moea_bpvo_pool_index++; 2044 bootstrap = 1; 2045 } 2046 2047 if (pvo == NULL) { 2048 mtx_unlock(&moea_table_mutex); 2049 return (ENOMEM); 2050 } 2051 2052 moea_pvo_entries++; 2053 pvo->pvo_vaddr = va; 2054 pvo->pvo_pmap = pm; 2055 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2056 pvo->pvo_vaddr &= ~ADDR_POFF; 2057 if (flags & PVO_WIRED) 2058 pvo->pvo_vaddr |= PVO_WIRED; 2059 if (pvo_head != &moea_pvo_kunmanaged) 2060 pvo->pvo_vaddr |= PVO_MANAGED; 2061 if (bootstrap) 2062 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2063 2064 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2065 2066 /* 2067 * Add to pmap list 2068 */ 2069 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2070 2071 /* 2072 * Remember if the list was empty and therefore will be the first 2073 * item. 2074 */ 2075 if (LIST_FIRST(pvo_head) == NULL) 2076 first = 1; 2077 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2078 2079 if (pvo->pvo_vaddr & PVO_WIRED) 2080 pm->pm_stats.wired_count++; 2081 pm->pm_stats.resident_count++; 2082 2083 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2084 KASSERT(i < 8, ("Invalid PTE index")); 2085 if (i >= 0) { 2086 PVO_PTEGIDX_SET(pvo, i); 2087 } else { 2088 panic("moea_pvo_enter: overflow"); 2089 moea_pte_overflow++; 2090 } 2091 mtx_unlock(&moea_table_mutex); 2092 2093 return (first ? ENOENT : 0); 2094 } 2095 2096 static void 2097 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2098 { 2099 struct pte *pt; 2100 2101 /* 2102 * If there is an active pte entry, we need to deactivate it (and 2103 * save the ref & cfg bits). 2104 */ 2105 pt = moea_pvo_to_pte(pvo, pteidx); 2106 if (pt != NULL) { 2107 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2108 mtx_unlock(&moea_table_mutex); 2109 PVO_PTEGIDX_CLR(pvo); 2110 } else { 2111 moea_pte_overflow--; 2112 } 2113 2114 /* 2115 * Update our statistics. 2116 */ 2117 pvo->pvo_pmap->pm_stats.resident_count--; 2118 if (pvo->pvo_vaddr & PVO_WIRED) 2119 pvo->pvo_pmap->pm_stats.wired_count--; 2120 2121 /* 2122 * Remove this PVO from the PV and pmap lists. 2123 */ 2124 LIST_REMOVE(pvo, pvo_vlink); 2125 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2126 2127 /* 2128 * Save the REF/CHG bits into their cache if the page is managed. 2129 * Clear PGA_WRITEABLE if all mappings of the page have been removed. 2130 */ 2131 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2132 struct vm_page *pg; 2133 2134 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2135 if (pg != NULL) { 2136 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2137 (PTE_REF | PTE_CHG)); 2138 if (LIST_EMPTY(&pg->md.mdpg_pvoh)) 2139 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2140 } 2141 } 2142 2143 /* 2144 * Remove this from the overflow list and return it to the pool 2145 * if we aren't going to reuse it. 2146 */ 2147 LIST_REMOVE(pvo, pvo_olink); 2148 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2149 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2150 moea_upvo_zone, pvo); 2151 moea_pvo_entries--; 2152 moea_pvo_remove_calls++; 2153 } 2154 2155 static __inline int 2156 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2157 { 2158 int pteidx; 2159 2160 /* 2161 * We can find the actual pte entry without searching by grabbing 2162 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2163 * noticing the HID bit. 2164 */ 2165 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2166 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2167 pteidx ^= moea_pteg_mask * 8; 2168 2169 return (pteidx); 2170 } 2171 2172 static struct pvo_entry * 2173 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2174 { 2175 struct pvo_entry *pvo; 2176 int ptegidx; 2177 u_int sr; 2178 2179 va &= ~ADDR_POFF; 2180 sr = va_to_sr(pm->pm_sr, va); 2181 ptegidx = va_to_pteg(sr, va); 2182 2183 mtx_lock(&moea_table_mutex); 2184 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2185 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2186 if (pteidx_p) 2187 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2188 break; 2189 } 2190 } 2191 mtx_unlock(&moea_table_mutex); 2192 2193 return (pvo); 2194 } 2195 2196 static struct pte * 2197 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2198 { 2199 struct pte *pt; 2200 2201 /* 2202 * If we haven't been supplied the ptegidx, calculate it. 2203 */ 2204 if (pteidx == -1) { 2205 int ptegidx; 2206 u_int sr; 2207 2208 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2209 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2210 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2211 } 2212 2213 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2214 mtx_lock(&moea_table_mutex); 2215 2216 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2217 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2218 "valid pte index", pvo); 2219 } 2220 2221 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2222 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2223 "pvo but no valid pte", pvo); 2224 } 2225 2226 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2227 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2228 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2229 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2230 } 2231 2232 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2233 != 0) { 2234 panic("moea_pvo_to_pte: pvo %p pte does not match " 2235 "pte %p in moea_pteg_table", pvo, pt); 2236 } 2237 2238 mtx_assert(&moea_table_mutex, MA_OWNED); 2239 return (pt); 2240 } 2241 2242 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2243 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2244 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2245 } 2246 2247 mtx_unlock(&moea_table_mutex); 2248 return (NULL); 2249 } 2250 2251 /* 2252 * XXX: THIS STUFF SHOULD BE IN pte.c? 2253 */ 2254 int 2255 moea_pte_spill(vm_offset_t addr) 2256 { 2257 struct pvo_entry *source_pvo, *victim_pvo; 2258 struct pvo_entry *pvo; 2259 int ptegidx, i, j; 2260 u_int sr; 2261 struct pteg *pteg; 2262 struct pte *pt; 2263 2264 moea_pte_spills++; 2265 2266 sr = mfsrin(addr); 2267 ptegidx = va_to_pteg(sr, addr); 2268 2269 /* 2270 * Have to substitute some entry. Use the primary hash for this. 2271 * Use low bits of timebase as random generator. 2272 */ 2273 pteg = &moea_pteg_table[ptegidx]; 2274 mtx_lock(&moea_table_mutex); 2275 __asm __volatile("mftb %0" : "=r"(i)); 2276 i &= 7; 2277 pt = &pteg->pt[i]; 2278 2279 source_pvo = NULL; 2280 victim_pvo = NULL; 2281 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2282 /* 2283 * We need to find a pvo entry for this address. 2284 */ 2285 if (source_pvo == NULL && 2286 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2287 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2288 /* 2289 * Now found an entry to be spilled into the pteg. 2290 * The PTE is now valid, so we know it's active. 2291 */ 2292 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2293 2294 if (j >= 0) { 2295 PVO_PTEGIDX_SET(pvo, j); 2296 moea_pte_overflow--; 2297 mtx_unlock(&moea_table_mutex); 2298 return (1); 2299 } 2300 2301 source_pvo = pvo; 2302 2303 if (victim_pvo != NULL) 2304 break; 2305 } 2306 2307 /* 2308 * We also need the pvo entry of the victim we are replacing 2309 * so save the R & C bits of the PTE. 2310 */ 2311 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2312 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2313 victim_pvo = pvo; 2314 if (source_pvo != NULL) 2315 break; 2316 } 2317 } 2318 2319 if (source_pvo == NULL) { 2320 mtx_unlock(&moea_table_mutex); 2321 return (0); 2322 } 2323 2324 if (victim_pvo == NULL) { 2325 if ((pt->pte_hi & PTE_HID) == 0) 2326 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2327 "entry", pt); 2328 2329 /* 2330 * If this is a secondary PTE, we need to search it's primary 2331 * pvo bucket for the matching PVO. 2332 */ 2333 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2334 pvo_olink) { 2335 /* 2336 * We also need the pvo entry of the victim we are 2337 * replacing so save the R & C bits of the PTE. 2338 */ 2339 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2340 victim_pvo = pvo; 2341 break; 2342 } 2343 } 2344 2345 if (victim_pvo == NULL) 2346 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2347 "entry", pt); 2348 } 2349 2350 /* 2351 * We are invalidating the TLB entry for the EA we are replacing even 2352 * though it's valid. If we don't, we lose any ref/chg bit changes 2353 * contained in the TLB entry. 2354 */ 2355 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2356 2357 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2358 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2359 2360 PVO_PTEGIDX_CLR(victim_pvo); 2361 PVO_PTEGIDX_SET(source_pvo, i); 2362 moea_pte_replacements++; 2363 2364 mtx_unlock(&moea_table_mutex); 2365 return (1); 2366 } 2367 2368 static __inline struct pvo_entry * 2369 moea_pte_spillable_ident(u_int ptegidx) 2370 { 2371 struct pte *pt; 2372 struct pvo_entry *pvo_walk, *pvo = NULL; 2373 2374 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2375 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2376 continue; 2377 2378 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2379 continue; 2380 2381 pt = moea_pvo_to_pte(pvo_walk, -1); 2382 2383 if (pt == NULL) 2384 continue; 2385 2386 pvo = pvo_walk; 2387 2388 mtx_unlock(&moea_table_mutex); 2389 if (!(pt->pte_lo & PTE_REF)) 2390 return (pvo_walk); 2391 } 2392 2393 return (pvo); 2394 } 2395 2396 static int 2397 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2398 { 2399 struct pte *pt; 2400 struct pvo_entry *victim_pvo; 2401 int i; 2402 int victim_idx; 2403 u_int pteg_bkpidx = ptegidx; 2404 2405 mtx_assert(&moea_table_mutex, MA_OWNED); 2406 2407 /* 2408 * First try primary hash. 2409 */ 2410 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2411 if ((pt->pte_hi & PTE_VALID) == 0) { 2412 pvo_pt->pte_hi &= ~PTE_HID; 2413 moea_pte_set(pt, pvo_pt); 2414 return (i); 2415 } 2416 } 2417 2418 /* 2419 * Now try secondary hash. 2420 */ 2421 ptegidx ^= moea_pteg_mask; 2422 2423 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2424 if ((pt->pte_hi & PTE_VALID) == 0) { 2425 pvo_pt->pte_hi |= PTE_HID; 2426 moea_pte_set(pt, pvo_pt); 2427 return (i); 2428 } 2429 } 2430 2431 /* Try again, but this time try to force a PTE out. */ 2432 ptegidx = pteg_bkpidx; 2433 2434 victim_pvo = moea_pte_spillable_ident(ptegidx); 2435 if (victim_pvo == NULL) { 2436 ptegidx ^= moea_pteg_mask; 2437 victim_pvo = moea_pte_spillable_ident(ptegidx); 2438 } 2439 2440 if (victim_pvo == NULL) { 2441 panic("moea_pte_insert: overflow"); 2442 return (-1); 2443 } 2444 2445 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2446 2447 if (pteg_bkpidx == ptegidx) 2448 pvo_pt->pte_hi &= ~PTE_HID; 2449 else 2450 pvo_pt->pte_hi |= PTE_HID; 2451 2452 /* 2453 * Synchronize the sacrifice PTE with its PVO, then mark both 2454 * invalid. The PVO will be reused when/if the VM system comes 2455 * here after a fault. 2456 */ 2457 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2458 2459 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2460 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2461 2462 /* 2463 * Set the new PTE. 2464 */ 2465 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2466 PVO_PTEGIDX_CLR(victim_pvo); 2467 moea_pte_overflow++; 2468 moea_pte_set(pt, pvo_pt); 2469 2470 return (victim_idx & 7); 2471 } 2472 2473 static boolean_t 2474 moea_query_bit(vm_page_t m, int ptebit) 2475 { 2476 struct pvo_entry *pvo; 2477 struct pte *pt; 2478 2479 rw_assert(&pvh_global_lock, RA_WLOCKED); 2480 if (moea_attr_fetch(m) & ptebit) 2481 return (TRUE); 2482 2483 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2484 2485 /* 2486 * See if we saved the bit off. If so, cache it and return 2487 * success. 2488 */ 2489 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2490 moea_attr_save(m, ptebit); 2491 return (TRUE); 2492 } 2493 } 2494 2495 /* 2496 * No luck, now go through the hard part of looking at the PTEs 2497 * themselves. Sync so that any pending REF/CHG bits are flushed to 2498 * the PTEs. 2499 */ 2500 powerpc_sync(); 2501 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2502 2503 /* 2504 * See if this pvo has a valid PTE. if so, fetch the 2505 * REF/CHG bits from the valid PTE. If the appropriate 2506 * ptebit is set, cache it and return success. 2507 */ 2508 pt = moea_pvo_to_pte(pvo, -1); 2509 if (pt != NULL) { 2510 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2511 mtx_unlock(&moea_table_mutex); 2512 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2513 moea_attr_save(m, ptebit); 2514 return (TRUE); 2515 } 2516 } 2517 } 2518 2519 return (FALSE); 2520 } 2521 2522 static u_int 2523 moea_clear_bit(vm_page_t m, int ptebit) 2524 { 2525 u_int count; 2526 struct pvo_entry *pvo; 2527 struct pte *pt; 2528 2529 rw_assert(&pvh_global_lock, RA_WLOCKED); 2530 2531 /* 2532 * Clear the cached value. 2533 */ 2534 moea_attr_clear(m, ptebit); 2535 2536 /* 2537 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2538 * we can reset the right ones). note that since the pvo entries and 2539 * list heads are accessed via BAT0 and are never placed in the page 2540 * table, we don't have to worry about further accesses setting the 2541 * REF/CHG bits. 2542 */ 2543 powerpc_sync(); 2544 2545 /* 2546 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2547 * valid pte clear the ptebit from the valid pte. 2548 */ 2549 count = 0; 2550 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2551 pt = moea_pvo_to_pte(pvo, -1); 2552 if (pt != NULL) { 2553 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2554 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2555 count++; 2556 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2557 } 2558 mtx_unlock(&moea_table_mutex); 2559 } 2560 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2561 } 2562 2563 return (count); 2564 } 2565 2566 /* 2567 * Return true if the physical range is encompassed by the battable[idx] 2568 */ 2569 static int 2570 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2571 { 2572 u_int prot; 2573 u_int32_t start; 2574 u_int32_t end; 2575 u_int32_t bat_ble; 2576 2577 /* 2578 * Return immediately if not a valid mapping 2579 */ 2580 if (!(battable[idx].batu & BAT_Vs)) 2581 return (EINVAL); 2582 2583 /* 2584 * The BAT entry must be cache-inhibited, guarded, and r/w 2585 * so it can function as an i/o page 2586 */ 2587 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2588 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2589 return (EPERM); 2590 2591 /* 2592 * The address should be within the BAT range. Assume that the 2593 * start address in the BAT has the correct alignment (thus 2594 * not requiring masking) 2595 */ 2596 start = battable[idx].batl & BAT_PBS; 2597 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2598 end = start | (bat_ble << 15) | 0x7fff; 2599 2600 if ((pa < start) || ((pa + size) > end)) 2601 return (ERANGE); 2602 2603 return (0); 2604 } 2605 2606 boolean_t 2607 moea_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2608 { 2609 int i; 2610 2611 /* 2612 * This currently does not work for entries that 2613 * overlap 256M BAT segments. 2614 */ 2615 2616 for(i = 0; i < 16; i++) 2617 if (moea_bat_mapped(i, pa, size) == 0) 2618 return (0); 2619 2620 return (EFAULT); 2621 } 2622 2623 /* 2624 * Map a set of physical memory pages into the kernel virtual 2625 * address space. Return a pointer to where it is mapped. This 2626 * routine is intended to be used for mapping device memory, 2627 * NOT real memory. 2628 */ 2629 void * 2630 moea_mapdev(vm_paddr_t pa, vm_size_t size) 2631 { 2632 2633 return (moea_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2634 } 2635 2636 void * 2637 moea_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2638 { 2639 vm_offset_t va, tmpva, ppa, offset; 2640 int i; 2641 2642 ppa = trunc_page(pa); 2643 offset = pa & PAGE_MASK; 2644 size = roundup(offset + size, PAGE_SIZE); 2645 2646 /* 2647 * If the physical address lies within a valid BAT table entry, 2648 * return the 1:1 mapping. This currently doesn't work 2649 * for regions that overlap 256M BAT segments. 2650 */ 2651 for (i = 0; i < 16; i++) { 2652 if (moea_bat_mapped(i, pa, size) == 0) 2653 return ((void *) pa); 2654 } 2655 2656 va = kva_alloc(size); 2657 if (!va) 2658 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2659 2660 for (tmpva = va; size > 0;) { 2661 moea_kenter_attr(tmpva, ppa, ma); 2662 tlbie(tmpva); 2663 size -= PAGE_SIZE; 2664 tmpva += PAGE_SIZE; 2665 ppa += PAGE_SIZE; 2666 } 2667 2668 return ((void *)(va + offset)); 2669 } 2670 2671 void 2672 moea_unmapdev(vm_offset_t va, vm_size_t size) 2673 { 2674 vm_offset_t base, offset; 2675 2676 /* 2677 * If this is outside kernel virtual space, then it's a 2678 * battable entry and doesn't require unmapping 2679 */ 2680 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2681 base = trunc_page(va); 2682 offset = va & PAGE_MASK; 2683 size = roundup(offset + size, PAGE_SIZE); 2684 moea_qremove(base, atop(size)); 2685 kva_free(base, size); 2686 } 2687 } 2688 2689 static void 2690 moea_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2691 { 2692 struct pvo_entry *pvo; 2693 vm_offset_t lim; 2694 vm_paddr_t pa; 2695 vm_size_t len; 2696 2697 PMAP_LOCK(pm); 2698 while (sz > 0) { 2699 lim = round_page(va + 1); 2700 len = MIN(lim - va, sz); 2701 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2702 if (pvo != NULL) { 2703 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2704 (va & ADDR_POFF); 2705 moea_syncicache(pa, len); 2706 } 2707 va += len; 2708 sz -= len; 2709 } 2710 PMAP_UNLOCK(pm); 2711 } 2712 2713 void 2714 moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2715 { 2716 2717 *va = (void *)pa; 2718 } 2719 2720 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2721 2722 void 2723 moea_scan_init() 2724 { 2725 struct pvo_entry *pvo; 2726 vm_offset_t va; 2727 int i; 2728 2729 if (!do_minidump) { 2730 /* Initialize phys. segments for dumpsys(). */ 2731 memset(&dump_map, 0, sizeof(dump_map)); 2732 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2733 for (i = 0; i < pregions_sz; i++) { 2734 dump_map[i].pa_start = pregions[i].mr_start; 2735 dump_map[i].pa_size = pregions[i].mr_size; 2736 } 2737 return; 2738 } 2739 2740 /* Virtual segments for minidumps: */ 2741 memset(&dump_map, 0, sizeof(dump_map)); 2742 2743 /* 1st: kernel .data and .bss. */ 2744 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2745 dump_map[0].pa_size = 2746 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2747 2748 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2749 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2750 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2751 2752 /* 3rd: kernel VM. */ 2753 va = dump_map[1].pa_start + dump_map[1].pa_size; 2754 /* Find start of next chunk (from va). */ 2755 while (va < virtual_end) { 2756 /* Don't dump the buffer cache. */ 2757 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2758 va = kmi.buffer_eva; 2759 continue; 2760 } 2761 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2762 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2763 break; 2764 va += PAGE_SIZE; 2765 } 2766 if (va < virtual_end) { 2767 dump_map[2].pa_start = va; 2768 va += PAGE_SIZE; 2769 /* Find last page in chunk. */ 2770 while (va < virtual_end) { 2771 /* Don't run into the buffer cache. */ 2772 if (va == kmi.buffer_sva) 2773 break; 2774 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2775 NULL); 2776 if (pvo == NULL || 2777 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2778 break; 2779 va += PAGE_SIZE; 2780 } 2781 dump_map[2].pa_size = va - dump_map[2].pa_start; 2782 } 2783 } 2784