1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/conf.h> 110 #include <sys/queue.h> 111 #include <sys/cpuset.h> 112 #include <sys/kerneldump.h> 113 #include <sys/ktr.h> 114 #include <sys/lock.h> 115 #include <sys/mman.h> 116 #include <sys/msgbuf.h> 117 #include <sys/mutex.h> 118 #include <sys/proc.h> 119 #include <sys/rwlock.h> 120 #include <sys/sched.h> 121 #include <sys/sysctl.h> 122 #include <sys/systm.h> 123 #include <sys/vmmeter.h> 124 125 #include <dev/ofw/openfirm.h> 126 127 #include <vm/vm.h> 128 #include <vm/pmap.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/vm_radix.h> 139 #include <vm/uma.h> 140 141 #include <machine/cpu.h> 142 #include <machine/platform.h> 143 #include <machine/bat.h> 144 #include <machine/frame.h> 145 #include <machine/md_var.h> 146 #include <machine/psl.h> 147 #include <machine/pte.h> 148 #include <machine/smp.h> 149 #include <machine/sr.h> 150 #include <machine/mmuvar.h> 151 #include <machine/trap.h> 152 153 #define MOEA_DEBUG 154 155 #define TODO panic("%s: not implemented", __func__); 156 157 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 158 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 159 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 160 161 /* Get physical address from PVO. */ 162 #define PVO_PADDR(pvo) ((pvo)->pvo_pte.pte.pte_lo & PTE_RPGN) 163 164 struct ofw_map { 165 vm_offset_t om_va; 166 vm_size_t om_len; 167 vm_offset_t om_pa; 168 u_int om_mode; 169 }; 170 171 extern unsigned char _etext[]; 172 extern unsigned char _end[]; 173 174 /* 175 * Map of physical memory regions. 176 */ 177 static struct mem_region *regions; 178 static struct mem_region *pregions; 179 static u_int phys_avail_count; 180 static int regions_sz, pregions_sz; 181 static struct ofw_map *translations; 182 183 /* 184 * Lock for the pteg and pvo tables. 185 */ 186 struct mtx moea_table_mutex; 187 struct mtx moea_vsid_mutex; 188 189 /* tlbie instruction synchronization */ 190 static struct mtx tlbie_mtx; 191 192 /* 193 * PTEG data. 194 */ 195 static struct pteg *moea_pteg_table; 196 u_int moea_pteg_count; 197 u_int moea_pteg_mask; 198 199 /* 200 * PVO data. 201 */ 202 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 203 struct pvo_head moea_pvo_kunmanaged = 204 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 205 206 static struct rwlock_padalign pvh_global_lock; 207 208 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 209 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 210 211 #define BPVO_POOL_SIZE 32768 212 static struct pvo_entry *moea_bpvo_pool; 213 static int moea_bpvo_pool_index = 0; 214 215 #define VSID_NBPW (sizeof(u_int32_t) * 8) 216 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 217 218 static bool moea_initialized = false; 219 220 /* 221 * Statistics. 222 */ 223 u_int moea_pte_valid = 0; 224 u_int moea_pte_overflow = 0; 225 u_int moea_pte_replacements = 0; 226 u_int moea_pvo_entries = 0; 227 u_int moea_pvo_enter_calls = 0; 228 u_int moea_pvo_remove_calls = 0; 229 u_int moea_pte_spills = 0; 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 233 &moea_pte_overflow, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 235 &moea_pte_replacements, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 237 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 239 &moea_pvo_enter_calls, 0, ""); 240 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 241 &moea_pvo_remove_calls, 0, ""); 242 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 243 &moea_pte_spills, 0, ""); 244 245 /* 246 * Allocate physical memory for use in moea_bootstrap. 247 */ 248 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 249 250 /* 251 * PTE calls. 252 */ 253 static int moea_pte_insert(u_int, struct pte *); 254 255 /* 256 * PVO calls. 257 */ 258 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 259 vm_offset_t, vm_paddr_t, u_int, int); 260 static void moea_pvo_remove(struct pvo_entry *, int); 261 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 262 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 263 264 /* 265 * Utility routines. 266 */ 267 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 268 vm_prot_t, u_int, int8_t); 269 static void moea_syncicache(vm_paddr_t, vm_size_t); 270 static bool moea_query_bit(vm_page_t, int); 271 static u_int moea_clear_bit(vm_page_t, int); 272 static void moea_kremove(vm_offset_t); 273 int moea_pte_spill(vm_offset_t); 274 275 /* 276 * Kernel MMU interface 277 */ 278 void moea_clear_modify(vm_page_t); 279 void moea_copy_page(vm_page_t, vm_page_t); 280 void moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 281 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 282 int moea_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 283 int8_t); 284 void moea_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 285 vm_prot_t); 286 void moea_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 287 vm_paddr_t moea_extract(pmap_t, vm_offset_t); 288 vm_page_t moea_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 289 void moea_init(void); 290 bool moea_is_modified(vm_page_t); 291 bool moea_is_prefaultable(pmap_t, vm_offset_t); 292 bool moea_is_referenced(vm_page_t); 293 int moea_ts_referenced(vm_page_t); 294 vm_offset_t moea_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 295 static int moea_mincore(pmap_t, vm_offset_t, vm_paddr_t *); 296 bool moea_page_exists_quick(pmap_t, vm_page_t); 297 void moea_page_init(vm_page_t); 298 int moea_page_wired_mappings(vm_page_t); 299 int moea_pinit(pmap_t); 300 void moea_pinit0(pmap_t); 301 void moea_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 302 void moea_qenter(vm_offset_t, vm_page_t *, int); 303 void moea_qremove(vm_offset_t, int); 304 void moea_release(pmap_t); 305 void moea_remove(pmap_t, vm_offset_t, vm_offset_t); 306 void moea_remove_all(vm_page_t); 307 void moea_remove_write(vm_page_t); 308 void moea_unwire(pmap_t, vm_offset_t, vm_offset_t); 309 void moea_zero_page(vm_page_t); 310 void moea_zero_page_area(vm_page_t, int, int); 311 void moea_activate(struct thread *); 312 void moea_deactivate(struct thread *); 313 void moea_cpu_bootstrap(int); 314 void moea_bootstrap(vm_offset_t, vm_offset_t); 315 void *moea_mapdev(vm_paddr_t, vm_size_t); 316 void *moea_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 317 void moea_unmapdev(void *, vm_size_t); 318 vm_paddr_t moea_kextract(vm_offset_t); 319 void moea_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 320 void moea_kenter(vm_offset_t, vm_paddr_t); 321 void moea_page_set_memattr(vm_page_t m, vm_memattr_t ma); 322 int moea_dev_direct_mapped(vm_paddr_t, vm_size_t); 323 static void moea_sync_icache(pmap_t, vm_offset_t, vm_size_t); 324 void moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va); 325 void moea_scan_init(void); 326 vm_offset_t moea_quick_enter_page(vm_page_t m); 327 void moea_quick_remove_page(vm_offset_t addr); 328 bool moea_page_is_mapped(vm_page_t m); 329 bool moea_ps_enabled(pmap_t pmap); 330 static int moea_map_user_ptr(pmap_t pm, 331 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 332 static int moea_decode_kernel_ptr(vm_offset_t addr, 333 int *is_user, vm_offset_t *decoded_addr); 334 335 static struct pmap_funcs moea_methods = { 336 .clear_modify = moea_clear_modify, 337 .copy_page = moea_copy_page, 338 .copy_pages = moea_copy_pages, 339 .enter = moea_enter, 340 .enter_object = moea_enter_object, 341 .enter_quick = moea_enter_quick, 342 .extract = moea_extract, 343 .extract_and_hold = moea_extract_and_hold, 344 .init = moea_init, 345 .is_modified = moea_is_modified, 346 .is_prefaultable = moea_is_prefaultable, 347 .is_referenced = moea_is_referenced, 348 .ts_referenced = moea_ts_referenced, 349 .map = moea_map, 350 .page_exists_quick = moea_page_exists_quick, 351 .page_init = moea_page_init, 352 .page_wired_mappings = moea_page_wired_mappings, 353 .pinit = moea_pinit, 354 .pinit0 = moea_pinit0, 355 .protect = moea_protect, 356 .qenter = moea_qenter, 357 .qremove = moea_qremove, 358 .release = moea_release, 359 .remove = moea_remove, 360 .remove_all = moea_remove_all, 361 .mincore = moea_mincore, 362 .remove_write = moea_remove_write, 363 .sync_icache = moea_sync_icache, 364 .unwire = moea_unwire, 365 .zero_page = moea_zero_page, 366 .zero_page_area = moea_zero_page_area, 367 .activate = moea_activate, 368 .deactivate = moea_deactivate, 369 .page_set_memattr = moea_page_set_memattr, 370 .quick_enter_page = moea_quick_enter_page, 371 .quick_remove_page = moea_quick_remove_page, 372 .page_is_mapped = moea_page_is_mapped, 373 .ps_enabled = moea_ps_enabled, 374 375 /* Internal interfaces */ 376 .bootstrap = moea_bootstrap, 377 .cpu_bootstrap = moea_cpu_bootstrap, 378 .mapdev_attr = moea_mapdev_attr, 379 .mapdev = moea_mapdev, 380 .unmapdev = moea_unmapdev, 381 .kextract = moea_kextract, 382 .kenter = moea_kenter, 383 .kenter_attr = moea_kenter_attr, 384 .dev_direct_mapped = moea_dev_direct_mapped, 385 .dumpsys_pa_init = moea_scan_init, 386 .dumpsys_map_chunk = moea_dumpsys_map, 387 .map_user_ptr = moea_map_user_ptr, 388 .decode_kernel_ptr = moea_decode_kernel_ptr, 389 }; 390 391 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods); 392 393 static __inline uint32_t 394 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 395 { 396 uint32_t pte_lo; 397 int i; 398 399 if (ma != VM_MEMATTR_DEFAULT) { 400 switch (ma) { 401 case VM_MEMATTR_UNCACHEABLE: 402 return (PTE_I | PTE_G); 403 case VM_MEMATTR_CACHEABLE: 404 return (PTE_M); 405 case VM_MEMATTR_WRITE_COMBINING: 406 case VM_MEMATTR_WRITE_BACK: 407 case VM_MEMATTR_PREFETCHABLE: 408 return (PTE_I); 409 case VM_MEMATTR_WRITE_THROUGH: 410 return (PTE_W | PTE_M); 411 } 412 } 413 414 /* 415 * Assume the page is cache inhibited and access is guarded unless 416 * it's in our available memory array. 417 */ 418 pte_lo = PTE_I | PTE_G; 419 for (i = 0; i < pregions_sz; i++) { 420 if ((pa >= pregions[i].mr_start) && 421 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 422 pte_lo = PTE_M; 423 break; 424 } 425 } 426 427 return pte_lo; 428 } 429 430 /* 431 * Translate OFW translations into VM attributes. 432 */ 433 static __inline vm_memattr_t 434 moea_bootstrap_convert_wimg(uint32_t mode) 435 { 436 437 switch (mode) { 438 case (PTE_I | PTE_G): 439 /* PCI device memory */ 440 return VM_MEMATTR_UNCACHEABLE; 441 case (PTE_M): 442 /* Explicitly coherent */ 443 return VM_MEMATTR_CACHEABLE; 444 case 0: /* Default claim */ 445 case 2: /* Alternate PP bits set by OF for the original payload */ 446 /* "Normal" memory. */ 447 return VM_MEMATTR_DEFAULT; 448 449 default: 450 /* Err on the side of caution for unknowns */ 451 /* XXX should we panic instead? */ 452 return VM_MEMATTR_UNCACHEABLE; 453 } 454 } 455 456 static void 457 tlbie(vm_offset_t va) 458 { 459 460 mtx_lock_spin(&tlbie_mtx); 461 __asm __volatile("ptesync"); 462 __asm __volatile("tlbie %0" :: "r"(va)); 463 __asm __volatile("eieio; tlbsync; ptesync"); 464 mtx_unlock_spin(&tlbie_mtx); 465 } 466 467 static void 468 tlbia(void) 469 { 470 vm_offset_t va; 471 472 for (va = 0; va < 0x00040000; va += 0x00001000) { 473 __asm __volatile("tlbie %0" :: "r"(va)); 474 powerpc_sync(); 475 } 476 __asm __volatile("tlbsync"); 477 powerpc_sync(); 478 } 479 480 static __inline int 481 va_to_sr(u_int *sr, vm_offset_t va) 482 { 483 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 484 } 485 486 static __inline u_int 487 va_to_pteg(u_int sr, vm_offset_t addr) 488 { 489 u_int hash; 490 491 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 492 ADDR_PIDX_SHFT); 493 return (hash & moea_pteg_mask); 494 } 495 496 static __inline struct pvo_head * 497 vm_page_to_pvoh(vm_page_t m) 498 { 499 500 return (&m->md.mdpg_pvoh); 501 } 502 503 static __inline void 504 moea_attr_clear(vm_page_t m, int ptebit) 505 { 506 507 rw_assert(&pvh_global_lock, RA_WLOCKED); 508 m->md.mdpg_attrs &= ~ptebit; 509 } 510 511 static __inline int 512 moea_attr_fetch(vm_page_t m) 513 { 514 515 return (m->md.mdpg_attrs); 516 } 517 518 static __inline void 519 moea_attr_save(vm_page_t m, int ptebit) 520 { 521 522 rw_assert(&pvh_global_lock, RA_WLOCKED); 523 m->md.mdpg_attrs |= ptebit; 524 } 525 526 static __inline int 527 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 528 { 529 if (pt->pte_hi == pvo_pt->pte_hi) 530 return (1); 531 532 return (0); 533 } 534 535 static __inline int 536 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 537 { 538 return (pt->pte_hi & ~PTE_VALID) == 539 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 540 ((va >> ADDR_API_SHFT) & PTE_API) | which); 541 } 542 543 static __inline void 544 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 545 { 546 547 mtx_assert(&moea_table_mutex, MA_OWNED); 548 549 /* 550 * Construct a PTE. Default to IMB initially. Valid bit only gets 551 * set when the real pte is set in memory. 552 * 553 * Note: Don't set the valid bit for correct operation of tlb update. 554 */ 555 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 556 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 557 pt->pte_lo = pte_lo; 558 } 559 560 static __inline void 561 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 562 { 563 564 mtx_assert(&moea_table_mutex, MA_OWNED); 565 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 566 } 567 568 static __inline void 569 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 570 { 571 572 mtx_assert(&moea_table_mutex, MA_OWNED); 573 574 /* 575 * As shown in Section 7.6.3.2.3 576 */ 577 pt->pte_lo &= ~ptebit; 578 tlbie(va); 579 } 580 581 static __inline void 582 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 583 { 584 585 mtx_assert(&moea_table_mutex, MA_OWNED); 586 pvo_pt->pte_hi |= PTE_VALID; 587 588 /* 589 * Update the PTE as defined in section 7.6.3.1. 590 * Note that the REF/CHG bits are from pvo_pt and thus should have 591 * been saved so this routine can restore them (if desired). 592 */ 593 pt->pte_lo = pvo_pt->pte_lo; 594 powerpc_sync(); 595 pt->pte_hi = pvo_pt->pte_hi; 596 powerpc_sync(); 597 moea_pte_valid++; 598 } 599 600 static __inline void 601 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 602 { 603 604 mtx_assert(&moea_table_mutex, MA_OWNED); 605 pvo_pt->pte_hi &= ~PTE_VALID; 606 607 /* 608 * Force the reg & chg bits back into the PTEs. 609 */ 610 powerpc_sync(); 611 612 /* 613 * Invalidate the pte. 614 */ 615 pt->pte_hi &= ~PTE_VALID; 616 617 tlbie(va); 618 619 /* 620 * Save the reg & chg bits. 621 */ 622 moea_pte_synch(pt, pvo_pt); 623 moea_pte_valid--; 624 } 625 626 static __inline void 627 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 628 { 629 630 /* 631 * Invalidate the PTE 632 */ 633 moea_pte_unset(pt, pvo_pt, va); 634 moea_pte_set(pt, pvo_pt); 635 } 636 637 /* 638 * Quick sort callout for comparing memory regions. 639 */ 640 static int om_cmp(const void *a, const void *b); 641 642 static int 643 om_cmp(const void *a, const void *b) 644 { 645 const struct ofw_map *mapa; 646 const struct ofw_map *mapb; 647 648 mapa = a; 649 mapb = b; 650 if (mapa->om_pa < mapb->om_pa) 651 return (-1); 652 else if (mapa->om_pa > mapb->om_pa) 653 return (1); 654 else 655 return (0); 656 } 657 658 void 659 moea_cpu_bootstrap(int ap) 660 { 661 u_int sdr; 662 int i; 663 664 if (ap) { 665 powerpc_sync(); 666 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 667 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 668 isync(); 669 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 670 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 671 isync(); 672 } 673 674 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 675 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 676 isync(); 677 678 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 679 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 680 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 681 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 682 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 683 isync(); 684 685 for (i = 0; i < 16; i++) 686 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 687 powerpc_sync(); 688 689 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 690 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 691 isync(); 692 693 tlbia(); 694 } 695 696 void 697 moea_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 698 { 699 ihandle_t mmui; 700 phandle_t chosen, mmu; 701 int sz; 702 int i, j; 703 vm_size_t size, physsz, hwphyssz; 704 vm_offset_t pa, va, off; 705 void *dpcpu; 706 707 /* 708 * Map PCI memory space. 709 */ 710 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 711 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 712 713 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 714 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 715 716 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 717 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 718 719 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 720 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 721 722 powerpc_sync(); 723 724 /* map pci space */ 725 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 726 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 727 isync(); 728 729 /* set global direct map flag */ 730 hw_direct_map = 1; 731 732 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 733 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 734 735 for (i = 0; i < pregions_sz; i++) { 736 vm_offset_t pa; 737 vm_offset_t end; 738 739 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 740 pregions[i].mr_start, 741 pregions[i].mr_start + pregions[i].mr_size, 742 pregions[i].mr_size); 743 /* 744 * Install entries into the BAT table to allow all 745 * of physmem to be convered by on-demand BAT entries. 746 * The loop will sometimes set the same battable element 747 * twice, but that's fine since they won't be used for 748 * a while yet. 749 */ 750 pa = pregions[i].mr_start & 0xf0000000; 751 end = pregions[i].mr_start + pregions[i].mr_size; 752 do { 753 u_int n = pa >> ADDR_SR_SHFT; 754 755 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 756 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 757 pa += SEGMENT_LENGTH; 758 } while (pa < end); 759 } 760 761 if (PHYS_AVAIL_ENTRIES < regions_sz) 762 panic("moea_bootstrap: phys_avail too small"); 763 764 phys_avail_count = 0; 765 physsz = 0; 766 hwphyssz = 0; 767 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 768 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 769 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 770 regions[i].mr_start + regions[i].mr_size, 771 regions[i].mr_size); 772 if (hwphyssz != 0 && 773 (physsz + regions[i].mr_size) >= hwphyssz) { 774 if (physsz < hwphyssz) { 775 phys_avail[j] = regions[i].mr_start; 776 phys_avail[j + 1] = regions[i].mr_start + 777 hwphyssz - physsz; 778 physsz = hwphyssz; 779 phys_avail_count++; 780 } 781 break; 782 } 783 phys_avail[j] = regions[i].mr_start; 784 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 785 phys_avail_count++; 786 physsz += regions[i].mr_size; 787 } 788 789 /* Check for overlap with the kernel and exception vectors */ 790 for (j = 0; j < 2*phys_avail_count; j+=2) { 791 if (phys_avail[j] < EXC_LAST) 792 phys_avail[j] += EXC_LAST; 793 794 if (kernelstart >= phys_avail[j] && 795 kernelstart < phys_avail[j+1]) { 796 if (kernelend < phys_avail[j+1]) { 797 phys_avail[2*phys_avail_count] = 798 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 799 phys_avail[2*phys_avail_count + 1] = 800 phys_avail[j+1]; 801 phys_avail_count++; 802 } 803 804 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 805 } 806 807 if (kernelend >= phys_avail[j] && 808 kernelend < phys_avail[j+1]) { 809 if (kernelstart > phys_avail[j]) { 810 phys_avail[2*phys_avail_count] = phys_avail[j]; 811 phys_avail[2*phys_avail_count + 1] = 812 kernelstart & ~PAGE_MASK; 813 phys_avail_count++; 814 } 815 816 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 817 } 818 } 819 820 physmem = btoc(physsz); 821 822 /* 823 * Allocate PTEG table. 824 */ 825 #ifdef PTEGCOUNT 826 moea_pteg_count = PTEGCOUNT; 827 #else 828 moea_pteg_count = 0x1000; 829 830 while (moea_pteg_count < physmem) 831 moea_pteg_count <<= 1; 832 833 moea_pteg_count >>= 1; 834 #endif /* PTEGCOUNT */ 835 836 size = moea_pteg_count * sizeof(struct pteg); 837 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 838 size); 839 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 840 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 841 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 842 moea_pteg_mask = moea_pteg_count - 1; 843 844 /* 845 * Allocate pv/overflow lists. 846 */ 847 size = sizeof(struct pvo_head) * moea_pteg_count; 848 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 849 PAGE_SIZE); 850 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 851 for (i = 0; i < moea_pteg_count; i++) 852 LIST_INIT(&moea_pvo_table[i]); 853 854 /* 855 * Initialize the lock that synchronizes access to the pteg and pvo 856 * tables. 857 */ 858 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 859 MTX_RECURSE); 860 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 861 862 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 863 864 /* 865 * Initialise the unmanaged pvo pool. 866 */ 867 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 868 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 869 moea_bpvo_pool_index = 0; 870 871 /* 872 * Make sure kernel vsid is allocated as well as VSID 0. 873 */ 874 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 875 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 876 moea_vsid_bitmap[0] |= 1; 877 878 /* 879 * Initialize the kernel pmap (which is statically allocated). 880 */ 881 PMAP_LOCK_INIT(kernel_pmap); 882 for (i = 0; i < 16; i++) 883 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 884 CPU_FILL(&kernel_pmap->pm_active); 885 RB_INIT(&kernel_pmap->pmap_pvo); 886 887 /* 888 * Initialize the global pv list lock. 889 */ 890 rw_init(&pvh_global_lock, "pmap pv global"); 891 892 /* 893 * Set up the Open Firmware mappings 894 */ 895 chosen = OF_finddevice("/chosen"); 896 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 897 (mmu = OF_instance_to_package(mmui)) != -1 && 898 (sz = OF_getproplen(mmu, "translations")) != -1) { 899 translations = NULL; 900 for (i = 0; phys_avail[i] != 0; i += 2) { 901 if (phys_avail[i + 1] >= sz) { 902 translations = (struct ofw_map *)phys_avail[i]; 903 break; 904 } 905 } 906 if (translations == NULL) 907 panic("moea_bootstrap: no space to copy translations"); 908 bzero(translations, sz); 909 if (OF_getprop(mmu, "translations", translations, sz) == -1) 910 panic("moea_bootstrap: can't get ofw translations"); 911 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 912 sz /= sizeof(*translations); 913 qsort(translations, sz, sizeof (*translations), om_cmp); 914 for (i = 0; i < sz; i++) { 915 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 916 translations[i].om_pa, translations[i].om_va, 917 translations[i].om_len); 918 919 /* 920 * If the mapping is 1:1, let the RAM and device 921 * on-demand BAT tables take care of the translation. 922 * 923 * However, always enter mappings for segment 16, 924 * which is mixed-protection and therefore not 925 * compatible with a BAT entry. 926 */ 927 if ((translations[i].om_va >> ADDR_SR_SHFT) != 0xf && 928 translations[i].om_va == translations[i].om_pa) 929 continue; 930 931 /* Enter the pages */ 932 for (off = 0; off < translations[i].om_len; 933 off += PAGE_SIZE) 934 moea_kenter_attr(translations[i].om_va + off, 935 translations[i].om_pa + off, 936 moea_bootstrap_convert_wimg(translations[i].om_mode)); 937 } 938 } 939 940 /* 941 * Calculate the last available physical address. 942 */ 943 for (i = 0; phys_avail[i + 2] != 0; i += 2) 944 ; 945 Maxmem = powerpc_btop(phys_avail[i + 1]); 946 947 moea_cpu_bootstrap(0); 948 mtmsr(mfmsr() | PSL_DR | PSL_IR); 949 pmap_bootstrapped++; 950 951 /* 952 * Set the start and end of kva. 953 */ 954 virtual_avail = VM_MIN_KERNEL_ADDRESS; 955 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 956 957 /* 958 * Allocate a kernel stack with a guard page for thread0 and map it 959 * into the kernel page map. 960 */ 961 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 962 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 963 virtual_avail = va + kstack_pages * PAGE_SIZE; 964 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 965 thread0.td_kstack = va; 966 thread0.td_kstack_pages = kstack_pages; 967 for (i = 0; i < kstack_pages; i++) { 968 moea_kenter(va, pa); 969 pa += PAGE_SIZE; 970 va += PAGE_SIZE; 971 } 972 973 /* 974 * Allocate virtual address space for the message buffer. 975 */ 976 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 977 msgbufp = (struct msgbuf *)virtual_avail; 978 va = virtual_avail; 979 virtual_avail += round_page(msgbufsize); 980 while (va < virtual_avail) { 981 moea_kenter(va, pa); 982 pa += PAGE_SIZE; 983 va += PAGE_SIZE; 984 } 985 986 /* 987 * Allocate virtual address space for the dynamic percpu area. 988 */ 989 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 990 dpcpu = (void *)virtual_avail; 991 va = virtual_avail; 992 virtual_avail += DPCPU_SIZE; 993 while (va < virtual_avail) { 994 moea_kenter(va, pa); 995 pa += PAGE_SIZE; 996 va += PAGE_SIZE; 997 } 998 dpcpu_init(dpcpu, 0); 999 } 1000 1001 /* 1002 * Activate a user pmap. The pmap must be activated before it's address 1003 * space can be accessed in any way. 1004 */ 1005 void 1006 moea_activate(struct thread *td) 1007 { 1008 pmap_t pm, pmr; 1009 1010 /* 1011 * Load all the data we need up front to encourage the compiler to 1012 * not issue any loads while we have interrupts disabled below. 1013 */ 1014 pm = &td->td_proc->p_vmspace->vm_pmap; 1015 pmr = pm->pmap_phys; 1016 1017 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1018 PCPU_SET(curpmap, pmr); 1019 1020 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1021 } 1022 1023 void 1024 moea_deactivate(struct thread *td) 1025 { 1026 pmap_t pm; 1027 1028 pm = &td->td_proc->p_vmspace->vm_pmap; 1029 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1030 PCPU_SET(curpmap, NULL); 1031 } 1032 1033 void 1034 moea_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1035 { 1036 struct pvo_entry key, *pvo; 1037 1038 PMAP_LOCK(pm); 1039 key.pvo_vaddr = sva; 1040 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1041 pvo != NULL && PVO_VADDR(pvo) < eva; 1042 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1043 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1044 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1045 pvo->pvo_vaddr &= ~PVO_WIRED; 1046 pm->pm_stats.wired_count--; 1047 } 1048 PMAP_UNLOCK(pm); 1049 } 1050 1051 void 1052 moea_copy_page(vm_page_t msrc, vm_page_t mdst) 1053 { 1054 vm_offset_t dst; 1055 vm_offset_t src; 1056 1057 dst = VM_PAGE_TO_PHYS(mdst); 1058 src = VM_PAGE_TO_PHYS(msrc); 1059 1060 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1061 } 1062 1063 void 1064 moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1065 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1066 { 1067 void *a_cp, *b_cp; 1068 vm_offset_t a_pg_offset, b_pg_offset; 1069 int cnt; 1070 1071 while (xfersize > 0) { 1072 a_pg_offset = a_offset & PAGE_MASK; 1073 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1074 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1075 a_pg_offset; 1076 b_pg_offset = b_offset & PAGE_MASK; 1077 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1078 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1079 b_pg_offset; 1080 bcopy(a_cp, b_cp, cnt); 1081 a_offset += cnt; 1082 b_offset += cnt; 1083 xfersize -= cnt; 1084 } 1085 } 1086 1087 /* 1088 * Zero a page of physical memory by temporarily mapping it into the tlb. 1089 */ 1090 void 1091 moea_zero_page(vm_page_t m) 1092 { 1093 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1094 1095 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1096 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1097 } 1098 1099 void 1100 moea_zero_page_area(vm_page_t m, int off, int size) 1101 { 1102 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1103 void *va = (void *)(pa + off); 1104 1105 bzero(va, size); 1106 } 1107 1108 vm_offset_t 1109 moea_quick_enter_page(vm_page_t m) 1110 { 1111 1112 return (VM_PAGE_TO_PHYS(m)); 1113 } 1114 1115 void 1116 moea_quick_remove_page(vm_offset_t addr) 1117 { 1118 } 1119 1120 bool 1121 moea_page_is_mapped(vm_page_t m) 1122 { 1123 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1124 } 1125 1126 bool 1127 moea_ps_enabled(pmap_t pmap __unused) 1128 { 1129 return (false); 1130 } 1131 1132 /* 1133 * Map the given physical page at the specified virtual address in the 1134 * target pmap with the protection requested. If specified the page 1135 * will be wired down. 1136 */ 1137 int 1138 moea_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1139 u_int flags, int8_t psind) 1140 { 1141 int error; 1142 1143 for (;;) { 1144 rw_wlock(&pvh_global_lock); 1145 PMAP_LOCK(pmap); 1146 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1147 rw_wunlock(&pvh_global_lock); 1148 PMAP_UNLOCK(pmap); 1149 if (error != ENOMEM) 1150 return (KERN_SUCCESS); 1151 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1152 return (KERN_RESOURCE_SHORTAGE); 1153 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1154 vm_wait(NULL); 1155 } 1156 } 1157 1158 /* 1159 * Map the given physical page at the specified virtual address in the 1160 * target pmap with the protection requested. If specified the page 1161 * will be wired down. 1162 * 1163 * The global pvh and pmap must be locked. 1164 */ 1165 static int 1166 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1167 u_int flags, int8_t psind __unused) 1168 { 1169 struct pvo_head *pvo_head; 1170 uma_zone_t zone; 1171 u_int pte_lo, pvo_flags; 1172 int error; 1173 1174 if (pmap_bootstrapped) 1175 rw_assert(&pvh_global_lock, RA_WLOCKED); 1176 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1177 if ((m->oflags & VPO_UNMANAGED) == 0) { 1178 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1179 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1180 else 1181 VM_OBJECT_ASSERT_LOCKED(m->object); 1182 } 1183 1184 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1185 pvo_head = &moea_pvo_kunmanaged; 1186 zone = moea_upvo_zone; 1187 pvo_flags = 0; 1188 } else { 1189 pvo_head = vm_page_to_pvoh(m); 1190 zone = moea_mpvo_zone; 1191 pvo_flags = PVO_MANAGED; 1192 } 1193 1194 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1195 1196 if (prot & VM_PROT_WRITE) { 1197 pte_lo |= PTE_BW; 1198 if (pmap_bootstrapped && 1199 (m->oflags & VPO_UNMANAGED) == 0) 1200 vm_page_aflag_set(m, PGA_WRITEABLE); 1201 } else 1202 pte_lo |= PTE_BR; 1203 1204 if ((flags & PMAP_ENTER_WIRED) != 0) 1205 pvo_flags |= PVO_WIRED; 1206 1207 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1208 pte_lo, pvo_flags); 1209 1210 /* 1211 * Flush the real page from the instruction cache. This has be done 1212 * for all user mappings to prevent information leakage via the 1213 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1214 * mapping for a page. 1215 */ 1216 if (pmap != kernel_pmap && error == ENOENT && 1217 (pte_lo & (PTE_I | PTE_G)) == 0) 1218 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1219 1220 return (error); 1221 } 1222 1223 /* 1224 * Maps a sequence of resident pages belonging to the same object. 1225 * The sequence begins with the given page m_start. This page is 1226 * mapped at the given virtual address start. Each subsequent page is 1227 * mapped at a virtual address that is offset from start by the same 1228 * amount as the page is offset from m_start within the object. The 1229 * last page in the sequence is the page with the largest offset from 1230 * m_start that can be mapped at a virtual address less than the given 1231 * virtual address end. Not every virtual page between start and end 1232 * is mapped; only those for which a resident page exists with the 1233 * corresponding offset from m_start are mapped. 1234 */ 1235 void 1236 moea_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1237 vm_page_t m_start, vm_prot_t prot) 1238 { 1239 struct pctrie_iter pages; 1240 vm_offset_t va; 1241 vm_page_t m; 1242 1243 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1244 1245 vm_page_iter_limit_init(&pages, m_start->object, 1246 m_start->pindex + atop(end - start)); 1247 m = vm_radix_iter_lookup(&pages, m_start->pindex); 1248 rw_wlock(&pvh_global_lock); 1249 PMAP_LOCK(pm); 1250 while (m != NULL) { 1251 va = start + ptoa(m->pindex - m_start->pindex); 1252 moea_enter_locked(pm, va, m, prot & 1253 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_QUICK_LOCKED, 1254 0); 1255 m = vm_radix_iter_step(&pages); 1256 } 1257 rw_wunlock(&pvh_global_lock); 1258 PMAP_UNLOCK(pm); 1259 } 1260 1261 void 1262 moea_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1263 vm_prot_t prot) 1264 { 1265 1266 rw_wlock(&pvh_global_lock); 1267 PMAP_LOCK(pm); 1268 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1269 PMAP_ENTER_QUICK_LOCKED, 0); 1270 rw_wunlock(&pvh_global_lock); 1271 PMAP_UNLOCK(pm); 1272 } 1273 1274 vm_paddr_t 1275 moea_extract(pmap_t pm, vm_offset_t va) 1276 { 1277 struct pvo_entry *pvo; 1278 vm_paddr_t pa; 1279 1280 PMAP_LOCK(pm); 1281 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1282 if (pvo == NULL) 1283 pa = 0; 1284 else 1285 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 1286 PMAP_UNLOCK(pm); 1287 return (pa); 1288 } 1289 1290 /* 1291 * Atomically extract and hold the physical page with the given 1292 * pmap and virtual address pair if that mapping permits the given 1293 * protection. 1294 */ 1295 vm_page_t 1296 moea_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1297 { 1298 struct pvo_entry *pvo; 1299 vm_page_t m; 1300 1301 m = NULL; 1302 PMAP_LOCK(pmap); 1303 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1304 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1305 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1306 (prot & VM_PROT_WRITE) == 0)) { 1307 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1308 if (!vm_page_wire_mapped(m)) 1309 m = NULL; 1310 } 1311 PMAP_UNLOCK(pmap); 1312 return (m); 1313 } 1314 1315 void 1316 moea_init(void) 1317 { 1318 1319 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1320 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1321 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1322 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1323 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1324 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1325 moea_initialized = true; 1326 } 1327 1328 bool 1329 moea_is_referenced(vm_page_t m) 1330 { 1331 bool rv; 1332 1333 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1334 ("moea_is_referenced: page %p is not managed", m)); 1335 rw_wlock(&pvh_global_lock); 1336 rv = moea_query_bit(m, PTE_REF); 1337 rw_wunlock(&pvh_global_lock); 1338 return (rv); 1339 } 1340 1341 bool 1342 moea_is_modified(vm_page_t m) 1343 { 1344 bool rv; 1345 1346 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1347 ("moea_is_modified: page %p is not managed", m)); 1348 1349 /* 1350 * If the page is not busied then this check is racy. 1351 */ 1352 if (!pmap_page_is_write_mapped(m)) 1353 return (false); 1354 1355 rw_wlock(&pvh_global_lock); 1356 rv = moea_query_bit(m, PTE_CHG); 1357 rw_wunlock(&pvh_global_lock); 1358 return (rv); 1359 } 1360 1361 bool 1362 moea_is_prefaultable(pmap_t pmap, vm_offset_t va) 1363 { 1364 struct pvo_entry *pvo; 1365 bool rv; 1366 1367 PMAP_LOCK(pmap); 1368 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1369 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1370 PMAP_UNLOCK(pmap); 1371 return (rv); 1372 } 1373 1374 void 1375 moea_clear_modify(vm_page_t m) 1376 { 1377 1378 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1379 ("moea_clear_modify: page %p is not managed", m)); 1380 vm_page_assert_busied(m); 1381 1382 if (!pmap_page_is_write_mapped(m)) 1383 return; 1384 rw_wlock(&pvh_global_lock); 1385 moea_clear_bit(m, PTE_CHG); 1386 rw_wunlock(&pvh_global_lock); 1387 } 1388 1389 /* 1390 * Clear the write and modified bits in each of the given page's mappings. 1391 */ 1392 void 1393 moea_remove_write(vm_page_t m) 1394 { 1395 struct pvo_entry *pvo; 1396 struct pte *pt; 1397 pmap_t pmap; 1398 u_int lo; 1399 1400 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1401 ("moea_remove_write: page %p is not managed", m)); 1402 vm_page_assert_busied(m); 1403 1404 if (!pmap_page_is_write_mapped(m)) 1405 return; 1406 rw_wlock(&pvh_global_lock); 1407 lo = moea_attr_fetch(m); 1408 powerpc_sync(); 1409 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1410 pmap = pvo->pvo_pmap; 1411 PMAP_LOCK(pmap); 1412 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1413 pt = moea_pvo_to_pte(pvo, -1); 1414 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1415 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1416 if (pt != NULL) { 1417 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1418 lo |= pvo->pvo_pte.pte.pte_lo; 1419 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1420 moea_pte_change(pt, &pvo->pvo_pte.pte, 1421 pvo->pvo_vaddr); 1422 mtx_unlock(&moea_table_mutex); 1423 } 1424 } 1425 PMAP_UNLOCK(pmap); 1426 } 1427 if ((lo & PTE_CHG) != 0) { 1428 moea_attr_clear(m, PTE_CHG); 1429 vm_page_dirty(m); 1430 } 1431 vm_page_aflag_clear(m, PGA_WRITEABLE); 1432 rw_wunlock(&pvh_global_lock); 1433 } 1434 1435 /* 1436 * moea_ts_referenced: 1437 * 1438 * Return a count of reference bits for a page, clearing those bits. 1439 * It is not necessary for every reference bit to be cleared, but it 1440 * is necessary that 0 only be returned when there are truly no 1441 * reference bits set. 1442 * 1443 * XXX: The exact number of bits to check and clear is a matter that 1444 * should be tested and standardized at some point in the future for 1445 * optimal aging of shared pages. 1446 */ 1447 int 1448 moea_ts_referenced(vm_page_t m) 1449 { 1450 int count; 1451 1452 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1453 ("moea_ts_referenced: page %p is not managed", m)); 1454 rw_wlock(&pvh_global_lock); 1455 count = moea_clear_bit(m, PTE_REF); 1456 rw_wunlock(&pvh_global_lock); 1457 return (count); 1458 } 1459 1460 /* 1461 * Modify the WIMG settings of all mappings for a page. 1462 */ 1463 void 1464 moea_page_set_memattr(vm_page_t m, vm_memattr_t ma) 1465 { 1466 struct pvo_entry *pvo; 1467 struct pvo_head *pvo_head; 1468 struct pte *pt; 1469 pmap_t pmap; 1470 u_int lo; 1471 1472 if ((m->oflags & VPO_UNMANAGED) != 0) { 1473 m->md.mdpg_cache_attrs = ma; 1474 return; 1475 } 1476 1477 rw_wlock(&pvh_global_lock); 1478 pvo_head = vm_page_to_pvoh(m); 1479 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1480 1481 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1482 pmap = pvo->pvo_pmap; 1483 PMAP_LOCK(pmap); 1484 pt = moea_pvo_to_pte(pvo, -1); 1485 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1486 pvo->pvo_pte.pte.pte_lo |= lo; 1487 if (pt != NULL) { 1488 moea_pte_change(pt, &pvo->pvo_pte.pte, 1489 pvo->pvo_vaddr); 1490 if (pvo->pvo_pmap == kernel_pmap) 1491 isync(); 1492 } 1493 mtx_unlock(&moea_table_mutex); 1494 PMAP_UNLOCK(pmap); 1495 } 1496 m->md.mdpg_cache_attrs = ma; 1497 rw_wunlock(&pvh_global_lock); 1498 } 1499 1500 /* 1501 * Map a wired page into kernel virtual address space. 1502 */ 1503 void 1504 moea_kenter(vm_offset_t va, vm_paddr_t pa) 1505 { 1506 1507 moea_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1508 } 1509 1510 void 1511 moea_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1512 { 1513 u_int pte_lo; 1514 int error; 1515 1516 #if 0 1517 if (va < VM_MIN_KERNEL_ADDRESS) 1518 panic("moea_kenter: attempt to enter non-kernel address %#x", 1519 va); 1520 #endif 1521 1522 pte_lo = moea_calc_wimg(pa, ma); 1523 1524 PMAP_LOCK(kernel_pmap); 1525 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1526 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1527 1528 if (error != 0 && error != ENOENT) 1529 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1530 pa, error); 1531 1532 PMAP_UNLOCK(kernel_pmap); 1533 } 1534 1535 /* 1536 * Extract the physical page address associated with the given kernel virtual 1537 * address. 1538 */ 1539 vm_paddr_t 1540 moea_kextract(vm_offset_t va) 1541 { 1542 struct pvo_entry *pvo; 1543 vm_paddr_t pa; 1544 1545 /* 1546 * Allow direct mappings on 32-bit OEA 1547 */ 1548 if (va < VM_MIN_KERNEL_ADDRESS) { 1549 return (va); 1550 } 1551 1552 PMAP_LOCK(kernel_pmap); 1553 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1554 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1555 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 1556 PMAP_UNLOCK(kernel_pmap); 1557 return (pa); 1558 } 1559 1560 /* 1561 * Remove a wired page from kernel virtual address space. 1562 */ 1563 void 1564 moea_kremove(vm_offset_t va) 1565 { 1566 1567 moea_remove(kernel_pmap, va, va + PAGE_SIZE); 1568 } 1569 1570 /* 1571 * Provide a kernel pointer corresponding to a given userland pointer. 1572 * The returned pointer is valid until the next time this function is 1573 * called in this thread. This is used internally in copyin/copyout. 1574 */ 1575 int 1576 moea_map_user_ptr(pmap_t pm, volatile const void *uaddr, 1577 void **kaddr, size_t ulen, size_t *klen) 1578 { 1579 size_t l; 1580 register_t vsid; 1581 1582 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1583 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1584 if (l > ulen) 1585 l = ulen; 1586 if (klen) 1587 *klen = l; 1588 else if (l != ulen) 1589 return (EFAULT); 1590 1591 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1592 1593 /* Mark segment no-execute */ 1594 vsid |= SR_N; 1595 1596 /* If we have already set this VSID, we can just return */ 1597 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1598 return (0); 1599 1600 __asm __volatile("isync"); 1601 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1602 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1603 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1604 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1605 1606 return (0); 1607 } 1608 1609 /* 1610 * Figure out where a given kernel pointer (usually in a fault) points 1611 * to from the VM's perspective, potentially remapping into userland's 1612 * address space. 1613 */ 1614 static int 1615 moea_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1616 vm_offset_t *decoded_addr) 1617 { 1618 vm_offset_t user_sr; 1619 1620 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1621 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1622 addr &= ADDR_PIDX | ADDR_POFF; 1623 addr |= user_sr << ADDR_SR_SHFT; 1624 *decoded_addr = addr; 1625 *is_user = 1; 1626 } else { 1627 *decoded_addr = addr; 1628 *is_user = 0; 1629 } 1630 1631 return (0); 1632 } 1633 1634 /* 1635 * Map a range of physical addresses into kernel virtual address space. 1636 * 1637 * The value passed in *virt is a suggested virtual address for the mapping. 1638 * Architectures which can support a direct-mapped physical to virtual region 1639 * can return the appropriate address within that region, leaving '*virt' 1640 * unchanged. We cannot and therefore do not; *virt is updated with the 1641 * first usable address after the mapped region. 1642 */ 1643 vm_offset_t 1644 moea_map(vm_offset_t *virt, vm_paddr_t pa_start, 1645 vm_paddr_t pa_end, int prot) 1646 { 1647 vm_offset_t sva, va; 1648 1649 sva = *virt; 1650 va = sva; 1651 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1652 moea_kenter(va, pa_start); 1653 *virt = va; 1654 return (sva); 1655 } 1656 1657 /* 1658 * Returns true if the pmap's pv is one of the first 1659 * 16 pvs linked to from this page. This count may 1660 * be changed upwards or downwards in the future; it 1661 * is only necessary that true be returned for a small 1662 * subset of pmaps for proper page aging. 1663 */ 1664 bool 1665 moea_page_exists_quick(pmap_t pmap, vm_page_t m) 1666 { 1667 int loops; 1668 struct pvo_entry *pvo; 1669 bool rv; 1670 1671 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1672 ("moea_page_exists_quick: page %p is not managed", m)); 1673 loops = 0; 1674 rv = false; 1675 rw_wlock(&pvh_global_lock); 1676 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1677 if (pvo->pvo_pmap == pmap) { 1678 rv = true; 1679 break; 1680 } 1681 if (++loops >= 16) 1682 break; 1683 } 1684 rw_wunlock(&pvh_global_lock); 1685 return (rv); 1686 } 1687 1688 void 1689 moea_page_init(vm_page_t m) 1690 { 1691 1692 m->md.mdpg_attrs = 0; 1693 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1694 LIST_INIT(&m->md.mdpg_pvoh); 1695 } 1696 1697 /* 1698 * Return the number of managed mappings to the given physical page 1699 * that are wired. 1700 */ 1701 int 1702 moea_page_wired_mappings(vm_page_t m) 1703 { 1704 struct pvo_entry *pvo; 1705 int count; 1706 1707 count = 0; 1708 if ((m->oflags & VPO_UNMANAGED) != 0) 1709 return (count); 1710 rw_wlock(&pvh_global_lock); 1711 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1712 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1713 count++; 1714 rw_wunlock(&pvh_global_lock); 1715 return (count); 1716 } 1717 1718 static u_int moea_vsidcontext; 1719 1720 int 1721 moea_pinit(pmap_t pmap) 1722 { 1723 int i, mask; 1724 u_int entropy; 1725 1726 RB_INIT(&pmap->pmap_pvo); 1727 1728 entropy = 0; 1729 __asm __volatile("mftb %0" : "=r"(entropy)); 1730 1731 if ((pmap->pmap_phys = (pmap_t)moea_kextract((vm_offset_t)pmap)) 1732 == NULL) { 1733 pmap->pmap_phys = pmap; 1734 } 1735 1736 mtx_lock(&moea_vsid_mutex); 1737 /* 1738 * Allocate some segment registers for this pmap. 1739 */ 1740 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1741 u_int hash, n; 1742 1743 /* 1744 * Create a new value by multiplying by a prime and adding in 1745 * entropy from the timebase register. This is to make the 1746 * VSID more random so that the PT hash function collides 1747 * less often. (Note that the prime casues gcc to do shifts 1748 * instead of a multiply.) 1749 */ 1750 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1751 hash = moea_vsidcontext & (NPMAPS - 1); 1752 if (hash == 0) /* 0 is special, avoid it */ 1753 continue; 1754 n = hash >> 5; 1755 mask = 1 << (hash & (VSID_NBPW - 1)); 1756 hash = (moea_vsidcontext & 0xfffff); 1757 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1758 /* anything free in this bucket? */ 1759 if (moea_vsid_bitmap[n] == 0xffffffff) { 1760 entropy = (moea_vsidcontext >> 20); 1761 continue; 1762 } 1763 i = ffs(~moea_vsid_bitmap[n]) - 1; 1764 mask = 1 << i; 1765 hash &= rounddown2(0xfffff, VSID_NBPW); 1766 hash |= i; 1767 } 1768 KASSERT(!(moea_vsid_bitmap[n] & mask), 1769 ("Allocating in-use VSID group %#x\n", hash)); 1770 moea_vsid_bitmap[n] |= mask; 1771 for (i = 0; i < 16; i++) 1772 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1773 mtx_unlock(&moea_vsid_mutex); 1774 return (1); 1775 } 1776 1777 mtx_unlock(&moea_vsid_mutex); 1778 panic("moea_pinit: out of segments"); 1779 } 1780 1781 /* 1782 * Initialize the pmap associated with process 0. 1783 */ 1784 void 1785 moea_pinit0(pmap_t pm) 1786 { 1787 1788 PMAP_LOCK_INIT(pm); 1789 moea_pinit(pm); 1790 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1791 } 1792 1793 /* 1794 * Set the physical protection on the specified range of this map as requested. 1795 */ 1796 void 1797 moea_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1798 vm_prot_t prot) 1799 { 1800 struct pvo_entry *pvo, *tpvo, key; 1801 struct pte *pt; 1802 1803 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1804 ("moea_protect: non current pmap")); 1805 1806 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1807 moea_remove(pm, sva, eva); 1808 return; 1809 } 1810 1811 rw_wlock(&pvh_global_lock); 1812 PMAP_LOCK(pm); 1813 key.pvo_vaddr = sva; 1814 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1815 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1816 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1817 1818 /* 1819 * Grab the PTE pointer before we diddle with the cached PTE 1820 * copy. 1821 */ 1822 pt = moea_pvo_to_pte(pvo, -1); 1823 /* 1824 * Change the protection of the page. 1825 */ 1826 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1827 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1828 1829 /* 1830 * If the PVO is in the page table, update that pte as well. 1831 */ 1832 if (pt != NULL) { 1833 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1834 mtx_unlock(&moea_table_mutex); 1835 } 1836 } 1837 rw_wunlock(&pvh_global_lock); 1838 PMAP_UNLOCK(pm); 1839 } 1840 1841 /* 1842 * Map a list of wired pages into kernel virtual address space. This is 1843 * intended for temporary mappings which do not need page modification or 1844 * references recorded. Existing mappings in the region are overwritten. 1845 */ 1846 void 1847 moea_qenter(vm_offset_t sva, vm_page_t *m, int count) 1848 { 1849 vm_offset_t va; 1850 1851 va = sva; 1852 while (count-- > 0) { 1853 moea_kenter(va, VM_PAGE_TO_PHYS(*m)); 1854 va += PAGE_SIZE; 1855 m++; 1856 } 1857 } 1858 1859 /* 1860 * Remove page mappings from kernel virtual address space. Intended for 1861 * temporary mappings entered by moea_qenter. 1862 */ 1863 void 1864 moea_qremove(vm_offset_t sva, int count) 1865 { 1866 vm_offset_t va; 1867 1868 va = sva; 1869 while (count-- > 0) { 1870 moea_kremove(va); 1871 va += PAGE_SIZE; 1872 } 1873 } 1874 1875 void 1876 moea_release(pmap_t pmap) 1877 { 1878 int idx, mask; 1879 1880 /* 1881 * Free segment register's VSID 1882 */ 1883 if (pmap->pm_sr[0] == 0) 1884 panic("moea_release"); 1885 1886 mtx_lock(&moea_vsid_mutex); 1887 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1888 mask = 1 << (idx % VSID_NBPW); 1889 idx /= VSID_NBPW; 1890 moea_vsid_bitmap[idx] &= ~mask; 1891 mtx_unlock(&moea_vsid_mutex); 1892 } 1893 1894 /* 1895 * Remove the given range of addresses from the specified map. 1896 */ 1897 void 1898 moea_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1899 { 1900 struct pvo_entry *pvo, *tpvo, key; 1901 1902 rw_wlock(&pvh_global_lock); 1903 PMAP_LOCK(pm); 1904 key.pvo_vaddr = sva; 1905 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1906 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1907 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1908 moea_pvo_remove(pvo, -1); 1909 } 1910 PMAP_UNLOCK(pm); 1911 rw_wunlock(&pvh_global_lock); 1912 } 1913 1914 /* 1915 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1916 * will reflect changes in pte's back to the vm_page. 1917 */ 1918 void 1919 moea_remove_all(vm_page_t m) 1920 { 1921 struct pvo_head *pvo_head; 1922 struct pvo_entry *pvo, *next_pvo; 1923 pmap_t pmap; 1924 1925 rw_wlock(&pvh_global_lock); 1926 pvo_head = vm_page_to_pvoh(m); 1927 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1928 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1929 1930 pmap = pvo->pvo_pmap; 1931 PMAP_LOCK(pmap); 1932 moea_pvo_remove(pvo, -1); 1933 PMAP_UNLOCK(pmap); 1934 } 1935 if ((m->a.flags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1936 moea_attr_clear(m, PTE_CHG); 1937 vm_page_dirty(m); 1938 } 1939 vm_page_aflag_clear(m, PGA_WRITEABLE); 1940 rw_wunlock(&pvh_global_lock); 1941 } 1942 1943 static int 1944 moea_mincore(pmap_t pm, vm_offset_t va, vm_paddr_t *pap) 1945 { 1946 struct pvo_entry *pvo; 1947 vm_paddr_t pa; 1948 vm_page_t m; 1949 int val; 1950 bool managed; 1951 1952 PMAP_LOCK(pm); 1953 1954 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1955 if (pvo != NULL) { 1956 pa = PVO_PADDR(pvo); 1957 m = PHYS_TO_VM_PAGE(pa); 1958 managed = (pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED; 1959 val = MINCORE_INCORE; 1960 } else { 1961 PMAP_UNLOCK(pm); 1962 return (0); 1963 } 1964 1965 PMAP_UNLOCK(pm); 1966 1967 if (m == NULL) 1968 return (0); 1969 1970 if (managed) { 1971 if (moea_is_modified(m)) 1972 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 1973 1974 if (moea_is_referenced(m)) 1975 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 1976 } 1977 1978 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 1979 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 1980 managed) { 1981 *pap = pa; 1982 } 1983 1984 return (val); 1985 } 1986 1987 /* 1988 * Allocate a physical page of memory directly from the phys_avail map. 1989 * Can only be called from moea_bootstrap before avail start and end are 1990 * calculated. 1991 */ 1992 static vm_offset_t 1993 moea_bootstrap_alloc(vm_size_t size, u_int align) 1994 { 1995 vm_offset_t s, e; 1996 int i, j; 1997 1998 size = round_page(size); 1999 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2000 if (align != 0) 2001 s = roundup2(phys_avail[i], align); 2002 else 2003 s = phys_avail[i]; 2004 e = s + size; 2005 2006 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2007 continue; 2008 2009 if (s == phys_avail[i]) { 2010 phys_avail[i] += size; 2011 } else if (e == phys_avail[i + 1]) { 2012 phys_avail[i + 1] -= size; 2013 } else { 2014 for (j = phys_avail_count * 2; j > i; j -= 2) { 2015 phys_avail[j] = phys_avail[j - 2]; 2016 phys_avail[j + 1] = phys_avail[j - 1]; 2017 } 2018 2019 phys_avail[i + 3] = phys_avail[i + 1]; 2020 phys_avail[i + 1] = s; 2021 phys_avail[i + 2] = e; 2022 phys_avail_count++; 2023 } 2024 2025 return (s); 2026 } 2027 panic("moea_bootstrap_alloc: could not allocate memory"); 2028 } 2029 2030 static void 2031 moea_syncicache(vm_paddr_t pa, vm_size_t len) 2032 { 2033 __syncicache((void *)pa, len); 2034 } 2035 2036 static int 2037 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 2038 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 2039 { 2040 struct pvo_entry *pvo; 2041 u_int sr; 2042 int first; 2043 u_int ptegidx; 2044 int i; 2045 int bootstrap; 2046 2047 moea_pvo_enter_calls++; 2048 first = 0; 2049 bootstrap = 0; 2050 2051 /* 2052 * Compute the PTE Group index. 2053 */ 2054 va &= ~ADDR_POFF; 2055 sr = va_to_sr(pm->pm_sr, va); 2056 ptegidx = va_to_pteg(sr, va); 2057 2058 /* 2059 * Remove any existing mapping for this page. Reuse the pvo entry if 2060 * there is a mapping. 2061 */ 2062 mtx_lock(&moea_table_mutex); 2063 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2064 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2065 if (PVO_PADDR(pvo) == pa && 2066 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2067 (pte_lo & PTE_PP)) { 2068 /* 2069 * The PTE is not changing. Instead, this may 2070 * be a request to change the mapping's wired 2071 * attribute. 2072 */ 2073 mtx_unlock(&moea_table_mutex); 2074 if ((flags & PVO_WIRED) != 0 && 2075 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2076 pvo->pvo_vaddr |= PVO_WIRED; 2077 pm->pm_stats.wired_count++; 2078 } else if ((flags & PVO_WIRED) == 0 && 2079 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2080 pvo->pvo_vaddr &= ~PVO_WIRED; 2081 pm->pm_stats.wired_count--; 2082 } 2083 return (0); 2084 } 2085 moea_pvo_remove(pvo, -1); 2086 break; 2087 } 2088 } 2089 2090 /* 2091 * If we aren't overwriting a mapping, try to allocate. 2092 */ 2093 if (moea_initialized) { 2094 pvo = uma_zalloc(zone, M_NOWAIT); 2095 } else { 2096 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2097 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2098 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2099 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2100 } 2101 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2102 moea_bpvo_pool_index++; 2103 bootstrap = 1; 2104 } 2105 2106 if (pvo == NULL) { 2107 mtx_unlock(&moea_table_mutex); 2108 return (ENOMEM); 2109 } 2110 2111 moea_pvo_entries++; 2112 pvo->pvo_vaddr = va; 2113 pvo->pvo_pmap = pm; 2114 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2115 pvo->pvo_vaddr &= ~ADDR_POFF; 2116 if (flags & PVO_WIRED) 2117 pvo->pvo_vaddr |= PVO_WIRED; 2118 if (pvo_head != &moea_pvo_kunmanaged) 2119 pvo->pvo_vaddr |= PVO_MANAGED; 2120 if (bootstrap) 2121 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2122 2123 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2124 2125 /* 2126 * Add to pmap list 2127 */ 2128 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2129 2130 /* 2131 * Remember if the list was empty and therefore will be the first 2132 * item. 2133 */ 2134 if (LIST_FIRST(pvo_head) == NULL) 2135 first = 1; 2136 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2137 2138 if (pvo->pvo_vaddr & PVO_WIRED) 2139 pm->pm_stats.wired_count++; 2140 pm->pm_stats.resident_count++; 2141 2142 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2143 KASSERT(i < 8, ("Invalid PTE index")); 2144 if (i >= 0) { 2145 PVO_PTEGIDX_SET(pvo, i); 2146 } else { 2147 panic("moea_pvo_enter: overflow"); 2148 moea_pte_overflow++; 2149 } 2150 mtx_unlock(&moea_table_mutex); 2151 2152 return (first ? ENOENT : 0); 2153 } 2154 2155 static void 2156 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2157 { 2158 struct pte *pt; 2159 2160 /* 2161 * If there is an active pte entry, we need to deactivate it (and 2162 * save the ref & cfg bits). 2163 */ 2164 pt = moea_pvo_to_pte(pvo, pteidx); 2165 if (pt != NULL) { 2166 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2167 mtx_unlock(&moea_table_mutex); 2168 PVO_PTEGIDX_CLR(pvo); 2169 } else { 2170 moea_pte_overflow--; 2171 } 2172 2173 /* 2174 * Update our statistics. 2175 */ 2176 pvo->pvo_pmap->pm_stats.resident_count--; 2177 if (pvo->pvo_vaddr & PVO_WIRED) 2178 pvo->pvo_pmap->pm_stats.wired_count--; 2179 2180 /* 2181 * Remove this PVO from the PV and pmap lists. 2182 */ 2183 LIST_REMOVE(pvo, pvo_vlink); 2184 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2185 2186 /* 2187 * Save the REF/CHG bits into their cache if the page is managed. 2188 * Clear PGA_WRITEABLE if all mappings of the page have been removed. 2189 */ 2190 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2191 struct vm_page *pg; 2192 2193 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2194 if (pg != NULL) { 2195 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2196 (PTE_REF | PTE_CHG)); 2197 if (LIST_EMPTY(&pg->md.mdpg_pvoh)) 2198 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2199 } 2200 } 2201 2202 /* 2203 * Remove this from the overflow list and return it to the pool 2204 * if we aren't going to reuse it. 2205 */ 2206 LIST_REMOVE(pvo, pvo_olink); 2207 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2208 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2209 moea_upvo_zone, pvo); 2210 moea_pvo_entries--; 2211 moea_pvo_remove_calls++; 2212 } 2213 2214 static __inline int 2215 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2216 { 2217 int pteidx; 2218 2219 /* 2220 * We can find the actual pte entry without searching by grabbing 2221 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2222 * noticing the HID bit. 2223 */ 2224 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2225 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2226 pteidx ^= moea_pteg_mask * 8; 2227 2228 return (pteidx); 2229 } 2230 2231 static struct pvo_entry * 2232 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2233 { 2234 struct pvo_entry *pvo; 2235 int ptegidx; 2236 u_int sr; 2237 2238 va &= ~ADDR_POFF; 2239 sr = va_to_sr(pm->pm_sr, va); 2240 ptegidx = va_to_pteg(sr, va); 2241 2242 mtx_lock(&moea_table_mutex); 2243 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2244 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2245 if (pteidx_p) 2246 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2247 break; 2248 } 2249 } 2250 mtx_unlock(&moea_table_mutex); 2251 2252 return (pvo); 2253 } 2254 2255 static struct pte * 2256 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2257 { 2258 struct pte *pt; 2259 2260 /* 2261 * If we haven't been supplied the ptegidx, calculate it. 2262 */ 2263 if (pteidx == -1) { 2264 int ptegidx; 2265 u_int sr; 2266 2267 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2268 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2269 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2270 } 2271 2272 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2273 mtx_lock(&moea_table_mutex); 2274 2275 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2276 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2277 "valid pte index", pvo); 2278 } 2279 2280 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2281 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2282 "pvo but no valid pte", pvo); 2283 } 2284 2285 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2286 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2287 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2288 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2289 } 2290 2291 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2292 != 0) { 2293 panic("moea_pvo_to_pte: pvo %p pte does not match " 2294 "pte %p in moea_pteg_table", pvo, pt); 2295 } 2296 2297 mtx_assert(&moea_table_mutex, MA_OWNED); 2298 return (pt); 2299 } 2300 2301 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2302 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2303 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2304 } 2305 2306 mtx_unlock(&moea_table_mutex); 2307 return (NULL); 2308 } 2309 2310 /* 2311 * XXX: THIS STUFF SHOULD BE IN pte.c? 2312 */ 2313 int 2314 moea_pte_spill(vm_offset_t addr) 2315 { 2316 struct pvo_entry *source_pvo, *victim_pvo; 2317 struct pvo_entry *pvo; 2318 int ptegidx, i, j; 2319 u_int sr; 2320 struct pteg *pteg; 2321 struct pte *pt; 2322 2323 moea_pte_spills++; 2324 2325 sr = mfsrin(addr); 2326 ptegidx = va_to_pteg(sr, addr); 2327 2328 /* 2329 * Have to substitute some entry. Use the primary hash for this. 2330 * Use low bits of timebase as random generator. 2331 */ 2332 pteg = &moea_pteg_table[ptegidx]; 2333 mtx_lock(&moea_table_mutex); 2334 __asm __volatile("mftb %0" : "=r"(i)); 2335 i &= 7; 2336 pt = &pteg->pt[i]; 2337 2338 source_pvo = NULL; 2339 victim_pvo = NULL; 2340 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2341 /* 2342 * We need to find a pvo entry for this address. 2343 */ 2344 if (source_pvo == NULL && 2345 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2346 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2347 /* 2348 * Now found an entry to be spilled into the pteg. 2349 * The PTE is now valid, so we know it's active. 2350 */ 2351 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2352 2353 if (j >= 0) { 2354 PVO_PTEGIDX_SET(pvo, j); 2355 moea_pte_overflow--; 2356 mtx_unlock(&moea_table_mutex); 2357 return (1); 2358 } 2359 2360 source_pvo = pvo; 2361 2362 if (victim_pvo != NULL) 2363 break; 2364 } 2365 2366 /* 2367 * We also need the pvo entry of the victim we are replacing 2368 * so save the R & C bits of the PTE. 2369 */ 2370 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2371 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2372 victim_pvo = pvo; 2373 if (source_pvo != NULL) 2374 break; 2375 } 2376 } 2377 2378 if (source_pvo == NULL) { 2379 mtx_unlock(&moea_table_mutex); 2380 return (0); 2381 } 2382 2383 if (victim_pvo == NULL) { 2384 if ((pt->pte_hi & PTE_HID) == 0) 2385 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2386 "entry", pt); 2387 2388 /* 2389 * If this is a secondary PTE, we need to search it's primary 2390 * pvo bucket for the matching PVO. 2391 */ 2392 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2393 pvo_olink) { 2394 /* 2395 * We also need the pvo entry of the victim we are 2396 * replacing so save the R & C bits of the PTE. 2397 */ 2398 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2399 victim_pvo = pvo; 2400 break; 2401 } 2402 } 2403 2404 if (victim_pvo == NULL) 2405 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2406 "entry", pt); 2407 } 2408 2409 /* 2410 * We are invalidating the TLB entry for the EA we are replacing even 2411 * though it's valid. If we don't, we lose any ref/chg bit changes 2412 * contained in the TLB entry. 2413 */ 2414 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2415 2416 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2417 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2418 2419 PVO_PTEGIDX_CLR(victim_pvo); 2420 PVO_PTEGIDX_SET(source_pvo, i); 2421 moea_pte_replacements++; 2422 2423 mtx_unlock(&moea_table_mutex); 2424 return (1); 2425 } 2426 2427 static __inline struct pvo_entry * 2428 moea_pte_spillable_ident(u_int ptegidx) 2429 { 2430 struct pte *pt; 2431 struct pvo_entry *pvo_walk, *pvo = NULL; 2432 2433 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2434 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2435 continue; 2436 2437 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2438 continue; 2439 2440 pt = moea_pvo_to_pte(pvo_walk, -1); 2441 2442 if (pt == NULL) 2443 continue; 2444 2445 pvo = pvo_walk; 2446 2447 mtx_unlock(&moea_table_mutex); 2448 if (!(pt->pte_lo & PTE_REF)) 2449 return (pvo_walk); 2450 } 2451 2452 return (pvo); 2453 } 2454 2455 static int 2456 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2457 { 2458 struct pte *pt; 2459 struct pvo_entry *victim_pvo; 2460 int i; 2461 int victim_idx; 2462 u_int pteg_bkpidx = ptegidx; 2463 2464 mtx_assert(&moea_table_mutex, MA_OWNED); 2465 2466 /* 2467 * First try primary hash. 2468 */ 2469 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2470 if ((pt->pte_hi & PTE_VALID) == 0) { 2471 pvo_pt->pte_hi &= ~PTE_HID; 2472 moea_pte_set(pt, pvo_pt); 2473 return (i); 2474 } 2475 } 2476 2477 /* 2478 * Now try secondary hash. 2479 */ 2480 ptegidx ^= moea_pteg_mask; 2481 2482 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2483 if ((pt->pte_hi & PTE_VALID) == 0) { 2484 pvo_pt->pte_hi |= PTE_HID; 2485 moea_pte_set(pt, pvo_pt); 2486 return (i); 2487 } 2488 } 2489 2490 /* Try again, but this time try to force a PTE out. */ 2491 ptegidx = pteg_bkpidx; 2492 2493 victim_pvo = moea_pte_spillable_ident(ptegidx); 2494 if (victim_pvo == NULL) { 2495 ptegidx ^= moea_pteg_mask; 2496 victim_pvo = moea_pte_spillable_ident(ptegidx); 2497 } 2498 2499 if (victim_pvo == NULL) { 2500 panic("moea_pte_insert: overflow"); 2501 return (-1); 2502 } 2503 2504 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2505 2506 if (pteg_bkpidx == ptegidx) 2507 pvo_pt->pte_hi &= ~PTE_HID; 2508 else 2509 pvo_pt->pte_hi |= PTE_HID; 2510 2511 /* 2512 * Synchronize the sacrifice PTE with its PVO, then mark both 2513 * invalid. The PVO will be reused when/if the VM system comes 2514 * here after a fault. 2515 */ 2516 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2517 2518 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2519 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2520 2521 /* 2522 * Set the new PTE. 2523 */ 2524 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2525 PVO_PTEGIDX_CLR(victim_pvo); 2526 moea_pte_overflow++; 2527 moea_pte_set(pt, pvo_pt); 2528 2529 return (victim_idx & 7); 2530 } 2531 2532 static bool 2533 moea_query_bit(vm_page_t m, int ptebit) 2534 { 2535 struct pvo_entry *pvo; 2536 struct pte *pt; 2537 2538 rw_assert(&pvh_global_lock, RA_WLOCKED); 2539 if (moea_attr_fetch(m) & ptebit) 2540 return (true); 2541 2542 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2543 /* 2544 * See if we saved the bit off. If so, cache it and return 2545 * success. 2546 */ 2547 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2548 moea_attr_save(m, ptebit); 2549 return (true); 2550 } 2551 } 2552 2553 /* 2554 * No luck, now go through the hard part of looking at the PTEs 2555 * themselves. Sync so that any pending REF/CHG bits are flushed to 2556 * the PTEs. 2557 */ 2558 powerpc_sync(); 2559 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2560 /* 2561 * See if this pvo has a valid PTE. if so, fetch the 2562 * REF/CHG bits from the valid PTE. If the appropriate 2563 * ptebit is set, cache it and return success. 2564 */ 2565 pt = moea_pvo_to_pte(pvo, -1); 2566 if (pt != NULL) { 2567 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2568 mtx_unlock(&moea_table_mutex); 2569 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2570 moea_attr_save(m, ptebit); 2571 return (true); 2572 } 2573 } 2574 } 2575 2576 return (false); 2577 } 2578 2579 static u_int 2580 moea_clear_bit(vm_page_t m, int ptebit) 2581 { 2582 u_int count; 2583 struct pvo_entry *pvo; 2584 struct pte *pt; 2585 2586 rw_assert(&pvh_global_lock, RA_WLOCKED); 2587 2588 /* 2589 * Clear the cached value. 2590 */ 2591 moea_attr_clear(m, ptebit); 2592 2593 /* 2594 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2595 * we can reset the right ones). note that since the pvo entries and 2596 * list heads are accessed via BAT0 and are never placed in the page 2597 * table, we don't have to worry about further accesses setting the 2598 * REF/CHG bits. 2599 */ 2600 powerpc_sync(); 2601 2602 /* 2603 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2604 * valid pte clear the ptebit from the valid pte. 2605 */ 2606 count = 0; 2607 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2608 pt = moea_pvo_to_pte(pvo, -1); 2609 if (pt != NULL) { 2610 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2611 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2612 count++; 2613 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2614 } 2615 mtx_unlock(&moea_table_mutex); 2616 } 2617 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2618 } 2619 2620 return (count); 2621 } 2622 2623 /* 2624 * Return true if the physical range is encompassed by the battable[idx] 2625 */ 2626 static int 2627 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2628 { 2629 u_int prot; 2630 u_int32_t start; 2631 u_int32_t end; 2632 u_int32_t bat_ble; 2633 2634 /* 2635 * Return immediately if not a valid mapping 2636 */ 2637 if (!(battable[idx].batu & BAT_Vs)) 2638 return (EINVAL); 2639 2640 /* 2641 * The BAT entry must be cache-inhibited, guarded, and r/w 2642 * so it can function as an i/o page 2643 */ 2644 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2645 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2646 return (EPERM); 2647 2648 /* 2649 * The address should be within the BAT range. Assume that the 2650 * start address in the BAT has the correct alignment (thus 2651 * not requiring masking) 2652 */ 2653 start = battable[idx].batl & BAT_PBS; 2654 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2655 end = start | (bat_ble << 15) | 0x7fff; 2656 2657 if ((pa < start) || ((pa + size) > end)) 2658 return (ERANGE); 2659 2660 return (0); 2661 } 2662 2663 int 2664 moea_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2665 { 2666 int i; 2667 2668 /* 2669 * This currently does not work for entries that 2670 * overlap 256M BAT segments. 2671 */ 2672 2673 for(i = 0; i < 16; i++) 2674 if (moea_bat_mapped(i, pa, size) == 0) 2675 return (0); 2676 2677 return (EFAULT); 2678 } 2679 2680 /* 2681 * Map a set of physical memory pages into the kernel virtual 2682 * address space. Return a pointer to where it is mapped. This 2683 * routine is intended to be used for mapping device memory, 2684 * NOT real memory. 2685 */ 2686 void * 2687 moea_mapdev(vm_paddr_t pa, vm_size_t size) 2688 { 2689 2690 return (moea_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2691 } 2692 2693 void * 2694 moea_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2695 { 2696 vm_offset_t va, tmpva, ppa, offset; 2697 int i; 2698 2699 ppa = trunc_page(pa); 2700 offset = pa & PAGE_MASK; 2701 size = roundup(offset + size, PAGE_SIZE); 2702 2703 /* 2704 * If the physical address lies within a valid BAT table entry, 2705 * return the 1:1 mapping. This currently doesn't work 2706 * for regions that overlap 256M BAT segments. 2707 */ 2708 for (i = 0; i < 16; i++) { 2709 if (moea_bat_mapped(i, pa, size) == 0) 2710 return ((void *) pa); 2711 } 2712 2713 va = kva_alloc(size); 2714 if (!va) 2715 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2716 2717 for (tmpva = va; size > 0;) { 2718 moea_kenter_attr(tmpva, ppa, ma); 2719 tlbie(tmpva); 2720 size -= PAGE_SIZE; 2721 tmpva += PAGE_SIZE; 2722 ppa += PAGE_SIZE; 2723 } 2724 2725 return ((void *)(va + offset)); 2726 } 2727 2728 void 2729 moea_unmapdev(void *p, vm_size_t size) 2730 { 2731 vm_offset_t base, offset, va; 2732 2733 /* 2734 * If this is outside kernel virtual space, then it's a 2735 * battable entry and doesn't require unmapping 2736 */ 2737 va = (vm_offset_t)p; 2738 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2739 base = trunc_page(va); 2740 offset = va & PAGE_MASK; 2741 size = roundup(offset + size, PAGE_SIZE); 2742 moea_qremove(base, atop(size)); 2743 kva_free(base, size); 2744 } 2745 } 2746 2747 static void 2748 moea_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2749 { 2750 struct pvo_entry *pvo; 2751 vm_offset_t lim; 2752 vm_paddr_t pa; 2753 vm_size_t len; 2754 2755 PMAP_LOCK(pm); 2756 while (sz > 0) { 2757 lim = round_page(va + 1); 2758 len = MIN(lim - va, sz); 2759 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2760 if (pvo != NULL) { 2761 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 2762 moea_syncicache(pa, len); 2763 } 2764 va += len; 2765 sz -= len; 2766 } 2767 PMAP_UNLOCK(pm); 2768 } 2769 2770 void 2771 moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2772 { 2773 2774 *va = (void *)pa; 2775 } 2776 2777 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2778 2779 void 2780 moea_scan_init(void) 2781 { 2782 struct pvo_entry *pvo; 2783 vm_offset_t va; 2784 int i; 2785 2786 if (!do_minidump) { 2787 /* Initialize phys. segments for dumpsys(). */ 2788 memset(&dump_map, 0, sizeof(dump_map)); 2789 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2790 for (i = 0; i < pregions_sz; i++) { 2791 dump_map[i].pa_start = pregions[i].mr_start; 2792 dump_map[i].pa_size = pregions[i].mr_size; 2793 } 2794 return; 2795 } 2796 2797 /* Virtual segments for minidumps: */ 2798 memset(&dump_map, 0, sizeof(dump_map)); 2799 2800 /* 1st: kernel .data and .bss. */ 2801 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2802 dump_map[0].pa_size = 2803 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2804 2805 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2806 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2807 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2808 2809 /* 3rd: kernel VM. */ 2810 va = dump_map[1].pa_start + dump_map[1].pa_size; 2811 /* Find start of next chunk (from va). */ 2812 while (va < virtual_end) { 2813 /* Don't dump the buffer cache. */ 2814 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2815 va = kmi.buffer_eva; 2816 continue; 2817 } 2818 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2819 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2820 break; 2821 va += PAGE_SIZE; 2822 } 2823 if (va < virtual_end) { 2824 dump_map[2].pa_start = va; 2825 va += PAGE_SIZE; 2826 /* Find last page in chunk. */ 2827 while (va < virtual_end) { 2828 /* Don't run into the buffer cache. */ 2829 if (va == kmi.buffer_sva) 2830 break; 2831 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2832 NULL); 2833 if (pvo == NULL || 2834 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2835 break; 2836 va += PAGE_SIZE; 2837 } 2838 dump_map[2].pa_size = va - dump_map[2].pa_start; 2839 } 2840 } 2841