1 /*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by TooLs GmbH. 17 * 4. The name of TooLs GmbH may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 2001 Benno Rice 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57 #include <sys/cdefs.h> 58 __FBSDID("$FreeBSD$"); 59 60 #include "opt_ddb.h" 61 #include "opt_kstack_pages.h" 62 #include "opt_platform.h" 63 64 #include <sys/endian.h> 65 #include <sys/param.h> 66 #include <sys/proc.h> 67 #include <sys/systm.h> 68 #include <sys/bio.h> 69 #include <sys/buf.h> 70 #include <sys/bus.h> 71 #include <sys/cons.h> 72 #include <sys/cpu.h> 73 #include <sys/eventhandler.h> 74 #include <sys/exec.h> 75 #include <sys/imgact.h> 76 #include <sys/kdb.h> 77 #include <sys/kernel.h> 78 #include <sys/ktr.h> 79 #include <sys/linker.h> 80 #include <sys/lock.h> 81 #include <sys/malloc.h> 82 #include <sys/mbuf.h> 83 #include <sys/msgbuf.h> 84 #include <sys/mutex.h> 85 #include <sys/ptrace.h> 86 #include <sys/reboot.h> 87 #include <sys/rwlock.h> 88 #include <sys/signalvar.h> 89 #include <sys/syscallsubr.h> 90 #include <sys/sysctl.h> 91 #include <sys/sysent.h> 92 #include <sys/sysproto.h> 93 #include <sys/ucontext.h> 94 #include <sys/uio.h> 95 #include <sys/vmmeter.h> 96 #include <sys/vnode.h> 97 98 #include <net/netisr.h> 99 100 #include <vm/vm.h> 101 #include <vm/vm_extern.h> 102 #include <vm/vm_kern.h> 103 #include <vm/vm_page.h> 104 #include <vm/vm_map.h> 105 #include <vm/vm_object.h> 106 #include <vm/vm_pager.h> 107 108 #include <machine/altivec.h> 109 #ifndef __powerpc64__ 110 #include <machine/bat.h> 111 #endif 112 #include <machine/cpu.h> 113 #include <machine/elf.h> 114 #include <machine/fpu.h> 115 #include <machine/hid.h> 116 #include <machine/kdb.h> 117 #include <machine/md_var.h> 118 #include <machine/metadata.h> 119 #include <machine/mmuvar.h> 120 #include <machine/pcb.h> 121 #include <machine/sigframe.h> 122 #include <machine/spr.h> 123 #include <machine/trap.h> 124 #include <machine/vmparam.h> 125 #include <machine/ofw_machdep.h> 126 127 #include <ddb/ddb.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #ifdef __powerpc64__ 132 #include "mmu_oea64.h" 133 #endif 134 135 #ifndef __powerpc64__ 136 struct bat battable[16]; 137 #endif 138 139 int radix_mmu = 0; 140 141 #ifndef __powerpc64__ 142 /* Bits for running on 64-bit systems in 32-bit mode. */ 143 extern void *testppc64, *testppc64size; 144 extern void *restorebridge, *restorebridgesize; 145 extern void *rfid_patch, *rfi_patch1, *rfi_patch2; 146 extern void *trapcode64; 147 148 extern Elf_Addr _GLOBAL_OFFSET_TABLE_[]; 149 #endif 150 151 extern void *rstcode, *rstcodeend; 152 extern void *trapcode, *trapcodeend; 153 extern void *hypertrapcode, *hypertrapcodeend; 154 extern void *generictrap, *generictrap64; 155 extern void *alitrap, *aliend; 156 extern void *dsitrap, *dsiend; 157 extern void *decrint, *decrsize; 158 extern void *extint, *extsize; 159 extern void *dblow, *dbend; 160 extern void *imisstrap, *imisssize; 161 extern void *dlmisstrap, *dlmisssize; 162 extern void *dsmisstrap, *dsmisssize; 163 164 extern void *ap_pcpu; 165 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); 166 extern void __restartkernel_virtual(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); 167 168 void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, 169 void *mdp, uint32_t mdp_cookie); 170 void aim_cpu_init(vm_offset_t toc); 171 172 void 173 aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp, 174 uint32_t mdp_cookie) 175 { 176 register_t scratch; 177 178 /* 179 * If running from an FDT, make sure we are in real mode to avoid 180 * tromping on firmware page tables. Everything in the kernel assumes 181 * 1:1 mappings out of firmware, so this won't break anything not 182 * already broken. This doesn't work if there is live OF, since OF 183 * may internally use non-1:1 mappings. 184 */ 185 if (ofentry == 0) 186 mtmsr(mfmsr() & ~(PSL_IR | PSL_DR)); 187 188 #ifdef __powerpc64__ 189 /* 190 * Relocate to high memory so that the kernel 191 * can execute from the direct map. 192 * 193 * If we are in virtual mode already, use a special entry point 194 * that sets up a temporary DMAP to execute from until we can 195 * properly set up the MMU. 196 */ 197 if ((vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS) { 198 if (mfmsr() & PSL_DR) { 199 __restartkernel_virtual(fdt, 0, ofentry, mdp, 200 mdp_cookie, DMAP_BASE_ADDRESS, mfmsr()); 201 } else { 202 __restartkernel(fdt, 0, ofentry, mdp, mdp_cookie, 203 DMAP_BASE_ADDRESS, mfmsr()); 204 } 205 } 206 #endif 207 208 /* Various very early CPU fix ups */ 209 switch (mfpvr() >> 16) { 210 /* 211 * PowerPC 970 CPUs have a misfeature requested by Apple that 212 * makes them pretend they have a 32-byte cacheline. Turn this 213 * off before we measure the cacheline size. 214 */ 215 case IBM970: 216 case IBM970FX: 217 case IBM970MP: 218 case IBM970GX: 219 scratch = mfspr(SPR_HID5); 220 scratch &= ~HID5_970_DCBZ_SIZE_HI; 221 mtspr(SPR_HID5, scratch); 222 break; 223 #ifdef __powerpc64__ 224 case IBMPOWER7: 225 case IBMPOWER7PLUS: 226 case IBMPOWER8: 227 case IBMPOWER8E: 228 case IBMPOWER8NVL: 229 case IBMPOWER9: 230 /* XXX: get from ibm,slb-size in device tree */ 231 n_slbs = 32; 232 break; 233 #endif 234 } 235 } 236 237 void 238 aim_cpu_init(vm_offset_t toc) 239 { 240 size_t trap_offset, trapsize; 241 vm_offset_t trap; 242 register_t msr; 243 uint8_t *cache_check; 244 int cacheline_warn; 245 #ifndef __powerpc64__ 246 register_t scratch; 247 int ppc64; 248 #endif 249 250 trap_offset = 0; 251 cacheline_warn = 0; 252 253 /* General setup for AIM CPUs */ 254 psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 255 256 #ifdef __powerpc64__ 257 psl_kernset |= PSL_SF; 258 if (mfmsr() & PSL_HV) 259 psl_kernset |= PSL_HV; 260 261 #if BYTE_ORDER == LITTLE_ENDIAN 262 psl_kernset |= PSL_LE; 263 #endif 264 265 #endif 266 psl_userset = psl_kernset | PSL_PR; 267 #ifdef __powerpc64__ 268 psl_userset32 = psl_userset & ~PSL_SF; 269 #endif 270 271 /* 272 * Zeroed bits in this variable signify that the value of the bit 273 * in its position is allowed to vary between userspace contexts. 274 * 275 * All other bits are required to be identical for every userspace 276 * context. The actual *value* of the bit is determined by 277 * psl_userset and/or psl_userset32, and is not allowed to change. 278 * 279 * Remember to update this set when implementing support for 280 * *conditionally* enabling a processor facility. Failing to do 281 * this will cause swapcontext() in userspace to break when a 282 * process uses a conditionally-enabled facility. 283 * 284 * When *unconditionally* implementing support for a processor 285 * facility, update psl_userset / psl_userset32 instead. 286 * 287 * See the access control check in set_mcontext(). 288 */ 289 psl_userstatic = ~(PSL_VSX | PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 290 /* 291 * Mask bits from the SRR1 that aren't really the MSR: 292 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) 293 */ 294 psl_userstatic &= ~0x783f0000UL; 295 296 /* 297 * Initialize the interrupt tables and figure out our cache line 298 * size and whether or not we need the 64-bit bridge code. 299 */ 300 301 /* 302 * Disable translation in case the vector area hasn't been 303 * mapped (G5). Note that no OFW calls can be made until 304 * translation is re-enabled. 305 */ 306 307 msr = mfmsr(); 308 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); 309 310 /* 311 * Measure the cacheline size using dcbz 312 * 313 * Use EXC_PGM as a playground. We are about to overwrite it 314 * anyway, we know it exists, and we know it is cache-aligned. 315 */ 316 317 cache_check = (void *)EXC_PGM; 318 319 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++) 320 cache_check[cacheline_size] = 0xff; 321 322 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory"); 323 324 /* Find the first byte dcbz did not zero to get the cache line size */ 325 for (cacheline_size = 0; cacheline_size < 0x100 && 326 cache_check[cacheline_size] == 0; cacheline_size++); 327 328 /* Work around psim bug */ 329 if (cacheline_size == 0) { 330 cacheline_warn = 1; 331 cacheline_size = 32; 332 } 333 334 #ifndef __powerpc64__ 335 /* 336 * Figure out whether we need to use the 64 bit PMAP. This works by 337 * executing an instruction that is only legal on 64-bit PPC (mtmsrd), 338 * and setting ppc64 = 0 if that causes a trap. 339 */ 340 341 ppc64 = 1; 342 343 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size); 344 __syncicache((void *)EXC_PGM, (size_t)&testppc64size); 345 346 __asm __volatile("\ 347 mfmsr %0; \ 348 mtsprg2 %1; \ 349 \ 350 mtmsrd %0; \ 351 mfsprg2 %1;" 352 : "=r"(scratch), "=r"(ppc64)); 353 354 if (ppc64) 355 cpu_features |= PPC_FEATURE_64; 356 357 /* 358 * Now copy restorebridge into all the handlers, if necessary, 359 * and set up the trap tables. 360 */ 361 362 if (cpu_features & PPC_FEATURE_64) { 363 /* Patch the two instances of rfi -> rfid */ 364 bcopy(&rfid_patch,&rfi_patch1,4); 365 #ifdef KDB 366 /* rfi_patch2 is at the end of dbleave */ 367 bcopy(&rfid_patch,&rfi_patch2,4); 368 #endif 369 } 370 #else /* powerpc64 */ 371 cpu_features |= PPC_FEATURE_64; 372 #endif 373 374 trapsize = (size_t)&trapcodeend - (size_t)&trapcode; 375 376 /* 377 * Copy generic handler into every possible trap. Special cases will get 378 * different ones in a minute. 379 */ 380 for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20) 381 bcopy(&trapcode, (void *)trap, trapsize); 382 383 #ifndef __powerpc64__ 384 if (cpu_features & PPC_FEATURE_64) { 385 /* 386 * Copy a code snippet to restore 32-bit bridge mode 387 * to the top of every non-generic trap handler 388 */ 389 390 trap_offset += (size_t)&restorebridgesize; 391 bcopy(&restorebridge, (void *)EXC_RST, trap_offset); 392 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset); 393 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset); 394 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset); 395 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset); 396 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset); 397 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset); 398 } else { 399 /* 400 * Use an IBAT and a DBAT to map the bottom 256M segment. 401 * 402 * It is very important to do it *now* to avoid taking a 403 * fault in .text / .data before the MMU is bootstrapped, 404 * because until then, the translation data has not been 405 * copied over from OpenFirmware, so our DSI/ISI will fail 406 * to find a match. 407 */ 408 409 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 410 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 411 412 __asm (".balign 32; \n" 413 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 414 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 415 :: "r"(battable[0].batu), "r"(battable[0].batl)); 416 } 417 #else 418 trapsize = (size_t)&hypertrapcodeend - (size_t)&hypertrapcode; 419 bcopy(&hypertrapcode, (void *)(EXC_HEA + trap_offset), trapsize); 420 bcopy(&hypertrapcode, (void *)(EXC_HMI + trap_offset), trapsize); 421 bcopy(&hypertrapcode, (void *)(EXC_HVI + trap_offset), trapsize); 422 bcopy(&hypertrapcode, (void *)(EXC_SOFT_PATCH + trap_offset), trapsize); 423 #endif 424 425 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend - 426 (size_t)&rstcode); 427 428 #ifdef KDB 429 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend - 430 (size_t)&dblow); 431 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend - 432 (size_t)&dblow); 433 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend - 434 (size_t)&dblow); 435 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend - 436 (size_t)&dblow); 437 #endif 438 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend - 439 (size_t)&alitrap); 440 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend - 441 (size_t)&dsitrap); 442 443 /* Set address of generictrap for self-reloc calculations */ 444 *((void **)TRAP_GENTRAP) = &generictrap; 445 #ifdef __powerpc64__ 446 /* Set TOC base so that the interrupt code can get at it */ 447 *((void **)TRAP_ENTRY) = &generictrap; 448 *((register_t *)TRAP_TOCBASE) = toc; 449 #else 450 /* Set branch address for trap code */ 451 if (cpu_features & PPC_FEATURE_64) 452 *((void **)TRAP_ENTRY) = &generictrap64; 453 else 454 *((void **)TRAP_ENTRY) = &generictrap; 455 *((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_; 456 457 /* G2-specific TLB miss helper handlers */ 458 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); 459 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); 460 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 461 #endif 462 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 463 464 /* 465 * Restore MSR 466 */ 467 mtmsr(msr); 468 469 /* Warn if cachline size was not determined */ 470 if (cacheline_warn == 1) { 471 printf("WARNING: cacheline size undetermined, setting to 32\n"); 472 } 473 474 /* 475 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority 476 * in case the platform module had a better idea of what we 477 * should do. 478 */ 479 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 480 radix_mmu = 0; 481 TUNABLE_INT_FETCH("radix_mmu", &radix_mmu); 482 if (radix_mmu) 483 pmap_mmu_install(MMU_TYPE_RADIX, BUS_PROBE_GENERIC); 484 else 485 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 486 } else if (cpu_features & PPC_FEATURE_64) 487 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 488 else 489 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 490 } 491 492 /* 493 * Shutdown the CPU as much as possible. 494 */ 495 void 496 cpu_halt(void) 497 { 498 499 OF_exit(); 500 } 501 502 int 503 ptrace_single_step(struct thread *td) 504 { 505 struct trapframe *tf; 506 507 tf = td->td_frame; 508 tf->srr1 |= PSL_SE; 509 510 return (0); 511 } 512 513 int 514 ptrace_clear_single_step(struct thread *td) 515 { 516 struct trapframe *tf; 517 518 tf = td->td_frame; 519 tf->srr1 &= ~PSL_SE; 520 521 return (0); 522 } 523 524 void 525 kdb_cpu_clear_singlestep(void) 526 { 527 528 kdb_frame->srr1 &= ~PSL_SE; 529 } 530 531 void 532 kdb_cpu_set_singlestep(void) 533 { 534 535 kdb_frame->srr1 |= PSL_SE; 536 } 537 538 /* 539 * Initialise a struct pcpu. 540 */ 541 void 542 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 543 { 544 #ifdef __powerpc64__ 545 /* Copy the SLB contents from the current CPU */ 546 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb)); 547 #endif 548 } 549 550 /* Return 0 on handled success, otherwise signal number. */ 551 int 552 cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode) 553 { 554 #ifdef __powerpc64__ 555 /* 556 * This block is 64-bit CPU specific currently. Punt running in 32-bit 557 * mode on 64-bit CPUs. 558 */ 559 /* Check if the important information is in DSISR */ 560 if ((frame->srr1 & SRR1_MCHK_DATA) != 0) { 561 printf("Machine check, DSISR: %016lx\n", frame->cpu.aim.dsisr); 562 /* SLB multi-hit is recoverable. */ 563 if ((frame->cpu.aim.dsisr & DSISR_MC_SLB_MULTIHIT) != 0) 564 return (0); 565 if ((frame->cpu.aim.dsisr & 566 (DSISR_MC_DERAT_MULTIHIT | DSISR_MC_TLB_MULTIHIT)) != 0) { 567 pmap_tlbie_all(); 568 return (0); 569 } 570 /* TODO: Add other machine check recovery procedures. */ 571 } else { 572 if ((frame->srr1 & SRR1_MCHK_IFETCH_M) == SRR1_MCHK_IFETCH_SLBMH) 573 return (0); 574 } 575 #endif 576 *ucode = BUS_OBJERR; 577 return (SIGBUS); 578 } 579 580 #ifndef __powerpc64__ 581 uint64_t 582 va_to_vsid(pmap_t pm, vm_offset_t va) 583 { 584 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 585 } 586 587 #endif 588 589 /* 590 * These functions need to provide addresses that both (a) work in real mode 591 * (or whatever mode/circumstances the kernel is in in early boot (now)) and 592 * (b) can still, in principle, work once the kernel is going. Because these 593 * rely on existing mappings/real mode, unmap is a no-op. 594 */ 595 vm_offset_t 596 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 597 { 598 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 599 600 /* 601 * If we have the MMU up in early boot, assume it is 1:1. Otherwise, 602 * try to get the address in a memory region compatible with the 603 * direct map for efficiency later. 604 */ 605 if (mfmsr() & PSL_DR) 606 return (pa); 607 else 608 return (DMAP_BASE_ADDRESS + pa); 609 } 610 611 void 612 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 613 { 614 615 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 616 } 617 618 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */ 619 void 620 flush_disable_caches(void) 621 { 622 register_t msr; 623 register_t msscr0; 624 register_t cache_reg; 625 volatile uint32_t *memp; 626 uint32_t temp; 627 int i; 628 int x; 629 630 msr = mfmsr(); 631 powerpc_sync(); 632 mtmsr(msr & ~(PSL_EE | PSL_DR)); 633 msscr0 = mfspr(SPR_MSSCR0); 634 msscr0 &= ~MSSCR0_L2PFE; 635 mtspr(SPR_MSSCR0, msscr0); 636 powerpc_sync(); 637 isync(); 638 /* 7e00066c: dssall */ 639 __asm__ __volatile__(".long 0x7e00066c; sync"); 640 powerpc_sync(); 641 isync(); 642 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 643 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 644 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 645 646 /* Lock the L1 Data cache. */ 647 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); 648 powerpc_sync(); 649 isync(); 650 651 mtspr(SPR_LDSTCR, 0); 652 653 /* 654 * Perform this in two stages: Flush the cache starting in RAM, then do it 655 * from ROM. 656 */ 657 memp = (volatile uint32_t *)0x00000000; 658 for (i = 0; i < 128 * 1024; i++) { 659 temp = *memp; 660 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 661 memp += 32/sizeof(*memp); 662 } 663 664 memp = (volatile uint32_t *)0xfff00000; 665 x = 0xfe; 666 667 for (; x != 0xff;) { 668 mtspr(SPR_LDSTCR, x); 669 for (i = 0; i < 128; i++) { 670 temp = *memp; 671 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 672 memp += 32/sizeof(*memp); 673 } 674 x = ((x << 1) | 1) & 0xff; 675 } 676 mtspr(SPR_LDSTCR, 0); 677 678 cache_reg = mfspr(SPR_L2CR); 679 if (cache_reg & L2CR_L2E) { 680 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450); 681 mtspr(SPR_L2CR, cache_reg); 682 powerpc_sync(); 683 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); 684 while (mfspr(SPR_L2CR) & L2CR_L2HWF) 685 ; /* Busy wait for cache to flush */ 686 powerpc_sync(); 687 cache_reg &= ~L2CR_L2E; 688 mtspr(SPR_L2CR, cache_reg); 689 powerpc_sync(); 690 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); 691 powerpc_sync(); 692 while (mfspr(SPR_L2CR) & L2CR_L2I) 693 ; /* Busy wait for L2 cache invalidate */ 694 powerpc_sync(); 695 } 696 697 cache_reg = mfspr(SPR_L3CR); 698 if (cache_reg & L3CR_L3E) { 699 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO); 700 mtspr(SPR_L3CR, cache_reg); 701 powerpc_sync(); 702 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); 703 while (mfspr(SPR_L3CR) & L3CR_L3HWF) 704 ; /* Busy wait for cache to flush */ 705 powerpc_sync(); 706 cache_reg &= ~L3CR_L3E; 707 mtspr(SPR_L3CR, cache_reg); 708 powerpc_sync(); 709 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); 710 powerpc_sync(); 711 while (mfspr(SPR_L3CR) & L3CR_L3I) 712 ; /* Busy wait for L3 cache invalidate */ 713 powerpc_sync(); 714 } 715 716 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); 717 powerpc_sync(); 718 isync(); 719 720 mtmsr(msr); 721 } 722 723 #ifndef __powerpc64__ 724 void 725 mpc745x_sleep() 726 { 727 static u_quad_t timebase = 0; 728 static register_t sprgs[4]; 729 static register_t srrs[2]; 730 731 jmp_buf resetjb; 732 struct thread *fputd; 733 struct thread *vectd; 734 register_t hid0; 735 register_t msr; 736 register_t saved_msr; 737 738 ap_pcpu = pcpup; 739 740 PCPU_SET(restore, &resetjb); 741 742 saved_msr = mfmsr(); 743 fputd = PCPU_GET(fputhread); 744 vectd = PCPU_GET(vecthread); 745 if (fputd != NULL) 746 save_fpu(fputd); 747 if (vectd != NULL) 748 save_vec(vectd); 749 if (setjmp(resetjb) == 0) { 750 sprgs[0] = mfspr(SPR_SPRG0); 751 sprgs[1] = mfspr(SPR_SPRG1); 752 sprgs[2] = mfspr(SPR_SPRG2); 753 sprgs[3] = mfspr(SPR_SPRG3); 754 srrs[0] = mfspr(SPR_SRR0); 755 srrs[1] = mfspr(SPR_SRR1); 756 timebase = mftb(); 757 powerpc_sync(); 758 flush_disable_caches(); 759 hid0 = mfspr(SPR_HID0); 760 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP; 761 powerpc_sync(); 762 isync(); 763 msr = mfmsr() | PSL_POW; 764 mtspr(SPR_HID0, hid0); 765 powerpc_sync(); 766 767 while (1) 768 mtmsr(msr); 769 } 770 /* XXX: The mttb() means this *only* works on single-CPU systems. */ 771 mttb(timebase); 772 PCPU_SET(curthread, curthread); 773 PCPU_SET(curpcb, curthread->td_pcb); 774 pmap_activate(curthread); 775 powerpc_sync(); 776 mtspr(SPR_SPRG0, sprgs[0]); 777 mtspr(SPR_SPRG1, sprgs[1]); 778 mtspr(SPR_SPRG2, sprgs[2]); 779 mtspr(SPR_SPRG3, sprgs[3]); 780 mtspr(SPR_SRR0, srrs[0]); 781 mtspr(SPR_SRR1, srrs[1]); 782 mtmsr(saved_msr); 783 if (fputd == curthread) 784 enable_fpu(curthread); 785 if (vectd == curthread) 786 enable_vec(curthread); 787 powerpc_sync(); 788 } 789 #endif 790