xref: /freebsd/sys/powerpc/aim/aim_machdep.c (revision 4f52dfbb8d6c4d446500c5b097e3806ec219fbd4)
1 /*-
2  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3  * Copyright (C) 1995, 1996 TooLs GmbH.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by TooLs GmbH.
17  * 4. The name of TooLs GmbH may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /*-
32  * Copyright (C) 2001 Benno Rice
33  * All rights reserved.
34  *
35  * Redistribution and use in source and binary forms, with or without
36  * modification, are permitted provided that the following conditions
37  * are met:
38  * 1. Redistributions of source code must retain the above copyright
39  *    notice, this list of conditions and the following disclaimer.
40  * 2. Redistributions in binary form must reproduce the above copyright
41  *    notice, this list of conditions and the following disclaimer in the
42  *    documentation and/or other materials provided with the distribution.
43  *
44  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
45  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
49  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
50  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54  *	$NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
55  */
56 
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
59 
60 #include "opt_ddb.h"
61 #include "opt_kstack_pages.h"
62 #include "opt_platform.h"
63 
64 #include <sys/param.h>
65 #include <sys/proc.h>
66 #include <sys/systm.h>
67 #include <sys/bio.h>
68 #include <sys/buf.h>
69 #include <sys/bus.h>
70 #include <sys/cons.h>
71 #include <sys/cpu.h>
72 #include <sys/eventhandler.h>
73 #include <sys/exec.h>
74 #include <sys/imgact.h>
75 #include <sys/kdb.h>
76 #include <sys/kernel.h>
77 #include <sys/ktr.h>
78 #include <sys/linker.h>
79 #include <sys/lock.h>
80 #include <sys/malloc.h>
81 #include <sys/mbuf.h>
82 #include <sys/msgbuf.h>
83 #include <sys/mutex.h>
84 #include <sys/ptrace.h>
85 #include <sys/reboot.h>
86 #include <sys/rwlock.h>
87 #include <sys/signalvar.h>
88 #include <sys/syscallsubr.h>
89 #include <sys/sysctl.h>
90 #include <sys/sysent.h>
91 #include <sys/sysproto.h>
92 #include <sys/ucontext.h>
93 #include <sys/uio.h>
94 #include <sys/vmmeter.h>
95 #include <sys/vnode.h>
96 
97 #include <net/netisr.h>
98 
99 #include <vm/vm.h>
100 #include <vm/vm_extern.h>
101 #include <vm/vm_kern.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_map.h>
104 #include <vm/vm_object.h>
105 #include <vm/vm_pager.h>
106 
107 #include <machine/altivec.h>
108 #ifndef __powerpc64__
109 #include <machine/bat.h>
110 #endif
111 #include <machine/cpu.h>
112 #include <machine/elf.h>
113 #include <machine/fpu.h>
114 #include <machine/hid.h>
115 #include <machine/kdb.h>
116 #include <machine/md_var.h>
117 #include <machine/metadata.h>
118 #include <machine/mmuvar.h>
119 #include <machine/pcb.h>
120 #include <machine/reg.h>
121 #include <machine/sigframe.h>
122 #include <machine/spr.h>
123 #include <machine/trap.h>
124 #include <machine/vmparam.h>
125 #include <machine/ofw_machdep.h>
126 
127 #include <ddb/ddb.h>
128 
129 #include <dev/ofw/openfirm.h>
130 
131 #ifdef __powerpc64__
132 #include "mmu_oea64.h"
133 #endif
134 
135 #ifndef __powerpc64__
136 struct bat	battable[16];
137 #endif
138 
139 #ifndef __powerpc64__
140 /* Bits for running on 64-bit systems in 32-bit mode. */
141 extern void	*testppc64, *testppc64size;
142 extern void	*restorebridge, *restorebridgesize;
143 extern void	*rfid_patch, *rfi_patch1, *rfi_patch2;
144 extern void	*trapcode64;
145 
146 extern Elf_Addr	_GLOBAL_OFFSET_TABLE_[];
147 #endif
148 
149 extern void	*rstcode, *rstcodeend;
150 extern void	*trapcode, *trapcodeend;
151 extern void	*generictrap, *generictrap64;
152 extern void	*alitrap, *aliend;
153 extern void	*dsitrap, *dsiend;
154 extern void	*decrint, *decrsize;
155 extern void     *extint, *extsize;
156 extern void	*dblow, *dbend;
157 extern void	*imisstrap, *imisssize;
158 extern void	*dlmisstrap, *dlmisssize;
159 extern void	*dsmisstrap, *dsmisssize;
160 
161 extern void *ap_pcpu;
162 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr);
163 
164 void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry,
165     void *mdp, uint32_t mdp_cookie);
166 void aim_cpu_init(vm_offset_t toc);
167 
168 void
169 aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp,
170     uint32_t mdp_cookie)
171 {
172 	register_t	scratch;
173 
174 	/*
175 	 * If running from an FDT, make sure we are in real mode to avoid
176 	 * tromping on firmware page tables. Everything in the kernel assumes
177 	 * 1:1 mappings out of firmware, so this won't break anything not
178 	 * already broken. This doesn't work if there is live OF, since OF
179 	 * may internally use non-1:1 mappings.
180 	 */
181 	if (ofentry == 0)
182 		mtmsr(mfmsr() & ~(PSL_IR | PSL_DR));
183 
184 #ifdef __powerpc64__
185 	/*
186 	 * If in real mode, relocate to high memory so that the kernel
187 	 * can execute from the direct map.
188 	 */
189 	if (!(mfmsr() & PSL_DR) &&
190 	    (vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS)
191 		__restartkernel(fdt, 0, ofentry, mdp, mdp_cookie,
192 		    DMAP_BASE_ADDRESS, mfmsr());
193 #endif
194 
195 	/* Various very early CPU fix ups */
196 	switch (mfpvr() >> 16) {
197 		/*
198 		 * PowerPC 970 CPUs have a misfeature requested by Apple that
199 		 * makes them pretend they have a 32-byte cacheline. Turn this
200 		 * off before we measure the cacheline size.
201 		 */
202 		case IBM970:
203 		case IBM970FX:
204 		case IBM970MP:
205 		case IBM970GX:
206 			scratch = mfspr(SPR_HID5);
207 			scratch &= ~HID5_970_DCBZ_SIZE_HI;
208 			mtspr(SPR_HID5, scratch);
209 			break;
210 	#ifdef __powerpc64__
211 		case IBMPOWER7:
212 		case IBMPOWER7PLUS:
213 		case IBMPOWER8:
214 		case IBMPOWER8E:
215 		case IBMPOWER9:
216 			/* XXX: get from ibm,slb-size in device tree */
217 			n_slbs = 32;
218 			break;
219 	#endif
220 	}
221 }
222 
223 void
224 aim_cpu_init(vm_offset_t toc)
225 {
226 	size_t		trap_offset, trapsize;
227 	vm_offset_t	trap;
228 	register_t	msr;
229 	uint8_t		*cache_check;
230 	int		cacheline_warn;
231 #ifndef __powerpc64__
232 	register_t	scratch;
233 	int		ppc64;
234 #endif
235 
236 	trap_offset = 0;
237 	cacheline_warn = 0;
238 
239 	/* General setup for AIM CPUs */
240 	psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
241 
242 #ifdef __powerpc64__
243 	psl_kernset |= PSL_SF;
244 	if (mfmsr() & PSL_HV)
245 		psl_kernset |= PSL_HV;
246 #endif
247 	psl_userset = psl_kernset | PSL_PR;
248 #ifdef __powerpc64__
249 	psl_userset32 = psl_userset & ~PSL_SF;
250 #endif
251 
252 	/* Bits that users aren't allowed to change */
253 	psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
254 	/*
255 	 * Mask bits from the SRR1 that aren't really the MSR:
256 	 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64)
257 	 */
258 	psl_userstatic &= ~0x783f0000UL;
259 
260 	/*
261 	 * Initialize the interrupt tables and figure out our cache line
262 	 * size and whether or not we need the 64-bit bridge code.
263 	 */
264 
265 	/*
266 	 * Disable translation in case the vector area hasn't been
267 	 * mapped (G5). Note that no OFW calls can be made until
268 	 * translation is re-enabled.
269 	 */
270 
271 	msr = mfmsr();
272 	mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI);
273 
274 	/*
275 	 * Measure the cacheline size using dcbz
276 	 *
277 	 * Use EXC_PGM as a playground. We are about to overwrite it
278 	 * anyway, we know it exists, and we know it is cache-aligned.
279 	 */
280 
281 	cache_check = (void *)EXC_PGM;
282 
283 	for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++)
284 		cache_check[cacheline_size] = 0xff;
285 
286 	__asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory");
287 
288 	/* Find the first byte dcbz did not zero to get the cache line size */
289 	for (cacheline_size = 0; cacheline_size < 0x100 &&
290 	    cache_check[cacheline_size] == 0; cacheline_size++);
291 
292 	/* Work around psim bug */
293 	if (cacheline_size == 0) {
294 		cacheline_warn = 1;
295 		cacheline_size = 32;
296 	}
297 
298 	#ifndef __powerpc64__
299 	/*
300 	 * Figure out whether we need to use the 64 bit PMAP. This works by
301 	 * executing an instruction that is only legal on 64-bit PPC (mtmsrd),
302 	 * and setting ppc64 = 0 if that causes a trap.
303 	 */
304 
305 	ppc64 = 1;
306 
307 	bcopy(&testppc64, (void *)EXC_PGM,  (size_t)&testppc64size);
308 	__syncicache((void *)EXC_PGM, (size_t)&testppc64size);
309 
310 	__asm __volatile("\
311 		mfmsr %0;	\
312 		mtsprg2 %1;	\
313 				\
314 		mtmsrd %0;	\
315 		mfsprg2 %1;"
316 	    : "=r"(scratch), "=r"(ppc64));
317 
318 	if (ppc64)
319 		cpu_features |= PPC_FEATURE_64;
320 
321 	/*
322 	 * Now copy restorebridge into all the handlers, if necessary,
323 	 * and set up the trap tables.
324 	 */
325 
326 	if (cpu_features & PPC_FEATURE_64) {
327 		/* Patch the two instances of rfi -> rfid */
328 		bcopy(&rfid_patch,&rfi_patch1,4);
329 	#ifdef KDB
330 		/* rfi_patch2 is at the end of dbleave */
331 		bcopy(&rfid_patch,&rfi_patch2,4);
332 	#endif
333 	}
334 	#else /* powerpc64 */
335 	cpu_features |= PPC_FEATURE_64;
336 	#endif
337 
338 	trapsize = (size_t)&trapcodeend - (size_t)&trapcode;
339 
340 	/*
341 	 * Copy generic handler into every possible trap. Special cases will get
342 	 * different ones in a minute.
343 	 */
344 	for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20)
345 		bcopy(&trapcode, (void *)trap, trapsize);
346 
347 	#ifndef __powerpc64__
348 	if (cpu_features & PPC_FEATURE_64) {
349 		/*
350 		 * Copy a code snippet to restore 32-bit bridge mode
351 		 * to the top of every non-generic trap handler
352 		 */
353 
354 		trap_offset += (size_t)&restorebridgesize;
355 		bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
356 		bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
357 		bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
358 		bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
359 		bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
360 		bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
361 		bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
362 	}
363 	#endif
364 
365 	bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend -
366 	    (size_t)&rstcode);
367 
368 #ifdef KDB
369 	bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend -
370 	    (size_t)&dblow);
371 	bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend -
372 	    (size_t)&dblow);
373 	bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend -
374 	    (size_t)&dblow);
375 	bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend -
376 	    (size_t)&dblow);
377 #endif
378 	bcopy(&alitrap,  (void *)(EXC_ALI + trap_offset),  (size_t)&aliend -
379 	    (size_t)&alitrap);
380 	bcopy(&dsitrap,  (void *)(EXC_DSI + trap_offset),  (size_t)&dsiend -
381 	    (size_t)&dsitrap);
382 
383 	#ifdef __powerpc64__
384 	/* Set TOC base so that the interrupt code can get at it */
385 	*((void **)TRAP_GENTRAP) = &generictrap;
386 	*((register_t *)TRAP_TOCBASE) = toc;
387 	#else
388 	/* Set branch address for trap code */
389 	if (cpu_features & PPC_FEATURE_64)
390 		*((void **)TRAP_GENTRAP) = &generictrap64;
391 	else
392 		*((void **)TRAP_GENTRAP) = &generictrap;
393 	*((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_;
394 
395 	/* G2-specific TLB miss helper handlers */
396 	bcopy(&imisstrap, (void *)EXC_IMISS,  (size_t)&imisssize);
397 	bcopy(&dlmisstrap, (void *)EXC_DLMISS,  (size_t)&dlmisssize);
398 	bcopy(&dsmisstrap, (void *)EXC_DSMISS,  (size_t)&dsmisssize);
399 	#endif
400 	__syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
401 
402 	/*
403 	 * Restore MSR
404 	 */
405 	mtmsr(msr);
406 
407 	/* Warn if cachline size was not determined */
408 	if (cacheline_warn == 1) {
409 		printf("WARNING: cacheline size undetermined, setting to 32\n");
410 	}
411 
412 	/*
413 	 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority
414 	 * in case the platform module had a better idea of what we
415 	 * should do.
416 	 */
417 	if (cpu_features & PPC_FEATURE_64)
418 		pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC);
419 	else
420 		pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC);
421 }
422 
423 /*
424  * Shutdown the CPU as much as possible.
425  */
426 void
427 cpu_halt(void)
428 {
429 
430 	OF_exit();
431 }
432 
433 int
434 ptrace_single_step(struct thread *td)
435 {
436 	struct trapframe *tf;
437 
438 	tf = td->td_frame;
439 	tf->srr1 |= PSL_SE;
440 
441 	return (0);
442 }
443 
444 int
445 ptrace_clear_single_step(struct thread *td)
446 {
447 	struct trapframe *tf;
448 
449 	tf = td->td_frame;
450 	tf->srr1 &= ~PSL_SE;
451 
452 	return (0);
453 }
454 
455 void
456 kdb_cpu_clear_singlestep(void)
457 {
458 
459 	kdb_frame->srr1 &= ~PSL_SE;
460 }
461 
462 void
463 kdb_cpu_set_singlestep(void)
464 {
465 
466 	kdb_frame->srr1 |= PSL_SE;
467 }
468 
469 /*
470  * Initialise a struct pcpu.
471  */
472 void
473 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
474 {
475 #ifdef __powerpc64__
476 /* Copy the SLB contents from the current CPU */
477 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb));
478 #endif
479 }
480 
481 #ifndef __powerpc64__
482 uint64_t
483 va_to_vsid(pmap_t pm, vm_offset_t va)
484 {
485 	return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
486 }
487 
488 #endif
489 
490 /*
491  * These functions need to provide addresses that both (a) work in real mode
492  * (or whatever mode/circumstances the kernel is in in early boot (now)) and
493  * (b) can still, in principle, work once the kernel is going. Because these
494  * rely on existing mappings/real mode, unmap is a no-op.
495  */
496 vm_offset_t
497 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
498 {
499 	KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!"));
500 
501 	/*
502 	 * If we have the MMU up in early boot, assume it is 1:1. Otherwise,
503 	 * try to get the address in a memory region compatible with the
504 	 * direct map for efficiency later.
505 	 */
506 	if (mfmsr() & PSL_DR)
507 		return (pa);
508 	else
509 		return (DMAP_BASE_ADDRESS + pa);
510 }
511 
512 void
513 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
514 {
515 
516 	KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!"));
517 }
518 
519 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
520 void
521 flush_disable_caches(void)
522 {
523 	register_t msr;
524 	register_t msscr0;
525 	register_t cache_reg;
526 	volatile uint32_t *memp;
527 	uint32_t temp;
528 	int i;
529 	int x;
530 
531 	msr = mfmsr();
532 	powerpc_sync();
533 	mtmsr(msr & ~(PSL_EE | PSL_DR));
534 	msscr0 = mfspr(SPR_MSSCR0);
535 	msscr0 &= ~MSSCR0_L2PFE;
536 	mtspr(SPR_MSSCR0, msscr0);
537 	powerpc_sync();
538 	isync();
539 	__asm__ __volatile__("dssall; sync");
540 	powerpc_sync();
541 	isync();
542 	__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
543 	__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
544 	__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
545 
546 	/* Lock the L1 Data cache. */
547 	mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
548 	powerpc_sync();
549 	isync();
550 
551 	mtspr(SPR_LDSTCR, 0);
552 
553 	/*
554 	 * Perform this in two stages: Flush the cache starting in RAM, then do it
555 	 * from ROM.
556 	 */
557 	memp = (volatile uint32_t *)0x00000000;
558 	for (i = 0; i < 128 * 1024; i++) {
559 		temp = *memp;
560 		__asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
561 		memp += 32/sizeof(*memp);
562 	}
563 
564 	memp = (volatile uint32_t *)0xfff00000;
565 	x = 0xfe;
566 
567 	for (; x != 0xff;) {
568 		mtspr(SPR_LDSTCR, x);
569 		for (i = 0; i < 128; i++) {
570 			temp = *memp;
571 			__asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
572 			memp += 32/sizeof(*memp);
573 		}
574 		x = ((x << 1) | 1) & 0xff;
575 	}
576 	mtspr(SPR_LDSTCR, 0);
577 
578 	cache_reg = mfspr(SPR_L2CR);
579 	if (cache_reg & L2CR_L2E) {
580 		cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
581 		mtspr(SPR_L2CR, cache_reg);
582 		powerpc_sync();
583 		mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
584 		while (mfspr(SPR_L2CR) & L2CR_L2HWF)
585 			; /* Busy wait for cache to flush */
586 		powerpc_sync();
587 		cache_reg &= ~L2CR_L2E;
588 		mtspr(SPR_L2CR, cache_reg);
589 		powerpc_sync();
590 		mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
591 		powerpc_sync();
592 		while (mfspr(SPR_L2CR) & L2CR_L2I)
593 			; /* Busy wait for L2 cache invalidate */
594 		powerpc_sync();
595 	}
596 
597 	cache_reg = mfspr(SPR_L3CR);
598 	if (cache_reg & L3CR_L3E) {
599 		cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
600 		mtspr(SPR_L3CR, cache_reg);
601 		powerpc_sync();
602 		mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
603 		while (mfspr(SPR_L3CR) & L3CR_L3HWF)
604 			; /* Busy wait for cache to flush */
605 		powerpc_sync();
606 		cache_reg &= ~L3CR_L3E;
607 		mtspr(SPR_L3CR, cache_reg);
608 		powerpc_sync();
609 		mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
610 		powerpc_sync();
611 		while (mfspr(SPR_L3CR) & L3CR_L3I)
612 			; /* Busy wait for L3 cache invalidate */
613 		powerpc_sync();
614 	}
615 
616 	mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
617 	powerpc_sync();
618 	isync();
619 
620 	mtmsr(msr);
621 }
622 
623 void
624 cpu_sleep()
625 {
626 	static u_quad_t timebase = 0;
627 	static register_t sprgs[4];
628 	static register_t srrs[2];
629 
630 	jmp_buf resetjb;
631 	struct thread *fputd;
632 	struct thread *vectd;
633 	register_t hid0;
634 	register_t msr;
635 	register_t saved_msr;
636 
637 	ap_pcpu = pcpup;
638 
639 	PCPU_SET(restore, &resetjb);
640 
641 	saved_msr = mfmsr();
642 	fputd = PCPU_GET(fputhread);
643 	vectd = PCPU_GET(vecthread);
644 	if (fputd != NULL)
645 		save_fpu(fputd);
646 	if (vectd != NULL)
647 		save_vec(vectd);
648 	if (setjmp(resetjb) == 0) {
649 		sprgs[0] = mfspr(SPR_SPRG0);
650 		sprgs[1] = mfspr(SPR_SPRG1);
651 		sprgs[2] = mfspr(SPR_SPRG2);
652 		sprgs[3] = mfspr(SPR_SPRG3);
653 		srrs[0] = mfspr(SPR_SRR0);
654 		srrs[1] = mfspr(SPR_SRR1);
655 		timebase = mftb();
656 		powerpc_sync();
657 		flush_disable_caches();
658 		hid0 = mfspr(SPR_HID0);
659 		hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
660 		powerpc_sync();
661 		isync();
662 		msr = mfmsr() | PSL_POW;
663 		mtspr(SPR_HID0, hid0);
664 		powerpc_sync();
665 
666 		while (1)
667 			mtmsr(msr);
668 	}
669 	platform_smp_timebase_sync(timebase, 0);
670 	PCPU_SET(curthread, curthread);
671 	PCPU_SET(curpcb, curthread->td_pcb);
672 	pmap_activate(curthread);
673 	powerpc_sync();
674 	mtspr(SPR_SPRG0, sprgs[0]);
675 	mtspr(SPR_SPRG1, sprgs[1]);
676 	mtspr(SPR_SPRG2, sprgs[2]);
677 	mtspr(SPR_SPRG3, sprgs[3]);
678 	mtspr(SPR_SRR0, srrs[0]);
679 	mtspr(SPR_SRR1, srrs[1]);
680 	mtmsr(saved_msr);
681 	if (fputd == curthread)
682 		enable_fpu(curthread);
683 	if (vectd == curthread)
684 		enable_vec(curthread);
685 	powerpc_sync();
686 }
687 
688