1 /*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by TooLs GmbH. 17 * 4. The name of TooLs GmbH may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 2001 Benno Rice 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57 #include <sys/cdefs.h> 58 __FBSDID("$FreeBSD$"); 59 60 #include "opt_ddb.h" 61 #include "opt_kstack_pages.h" 62 #include "opt_platform.h" 63 64 #include <sys/param.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/bio.h> 68 #include <sys/buf.h> 69 #include <sys/bus.h> 70 #include <sys/cons.h> 71 #include <sys/cpu.h> 72 #include <sys/eventhandler.h> 73 #include <sys/exec.h> 74 #include <sys/imgact.h> 75 #include <sys/kdb.h> 76 #include <sys/kernel.h> 77 #include <sys/ktr.h> 78 #include <sys/linker.h> 79 #include <sys/lock.h> 80 #include <sys/malloc.h> 81 #include <sys/mbuf.h> 82 #include <sys/msgbuf.h> 83 #include <sys/mutex.h> 84 #include <sys/ptrace.h> 85 #include <sys/reboot.h> 86 #include <sys/rwlock.h> 87 #include <sys/signalvar.h> 88 #include <sys/syscallsubr.h> 89 #include <sys/sysctl.h> 90 #include <sys/sysent.h> 91 #include <sys/sysproto.h> 92 #include <sys/ucontext.h> 93 #include <sys/uio.h> 94 #include <sys/vmmeter.h> 95 #include <sys/vnode.h> 96 97 #include <net/netisr.h> 98 99 #include <vm/vm.h> 100 #include <vm/vm_extern.h> 101 #include <vm/vm_kern.h> 102 #include <vm/vm_page.h> 103 #include <vm/vm_map.h> 104 #include <vm/vm_object.h> 105 #include <vm/vm_pager.h> 106 107 #include <machine/altivec.h> 108 #ifndef __powerpc64__ 109 #include <machine/bat.h> 110 #endif 111 #include <machine/cpu.h> 112 #include <machine/elf.h> 113 #include <machine/fpu.h> 114 #include <machine/hid.h> 115 #include <machine/kdb.h> 116 #include <machine/md_var.h> 117 #include <machine/metadata.h> 118 #include <machine/mmuvar.h> 119 #include <machine/pcb.h> 120 #include <machine/reg.h> 121 #include <machine/sigframe.h> 122 #include <machine/spr.h> 123 #include <machine/trap.h> 124 #include <machine/vmparam.h> 125 #include <machine/ofw_machdep.h> 126 127 #include <ddb/ddb.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #ifdef __powerpc64__ 132 #include "mmu_oea64.h" 133 #endif 134 135 #ifndef __powerpc64__ 136 struct bat battable[16]; 137 #endif 138 139 #ifndef __powerpc64__ 140 /* Bits for running on 64-bit systems in 32-bit mode. */ 141 extern void *testppc64, *testppc64size; 142 extern void *restorebridge, *restorebridgesize; 143 extern void *rfid_patch, *rfi_patch1, *rfi_patch2; 144 extern void *trapcode64; 145 146 extern Elf_Addr _GLOBAL_OFFSET_TABLE_[]; 147 #endif 148 149 extern void *rstcode, *rstcodeend; 150 extern void *trapcode, *trapcodeend; 151 extern void *hypertrapcode, *hypertrapcodeend; 152 extern void *generictrap, *generictrap64; 153 extern void *alitrap, *aliend; 154 extern void *dsitrap, *dsiend; 155 extern void *decrint, *decrsize; 156 extern void *extint, *extsize; 157 extern void *dblow, *dbend; 158 extern void *imisstrap, *imisssize; 159 extern void *dlmisstrap, *dlmisssize; 160 extern void *dsmisstrap, *dsmisssize; 161 162 extern void *ap_pcpu; 163 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); 164 165 void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, 166 void *mdp, uint32_t mdp_cookie); 167 void aim_cpu_init(vm_offset_t toc); 168 169 void 170 aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp, 171 uint32_t mdp_cookie) 172 { 173 register_t scratch; 174 175 /* 176 * If running from an FDT, make sure we are in real mode to avoid 177 * tromping on firmware page tables. Everything in the kernel assumes 178 * 1:1 mappings out of firmware, so this won't break anything not 179 * already broken. This doesn't work if there is live OF, since OF 180 * may internally use non-1:1 mappings. 181 */ 182 if (ofentry == 0) 183 mtmsr(mfmsr() & ~(PSL_IR | PSL_DR)); 184 185 #ifdef __powerpc64__ 186 /* 187 * If in real mode, relocate to high memory so that the kernel 188 * can execute from the direct map. 189 */ 190 if (!(mfmsr() & PSL_DR) && 191 (vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS) 192 __restartkernel(fdt, 0, ofentry, mdp, mdp_cookie, 193 DMAP_BASE_ADDRESS, mfmsr()); 194 #endif 195 196 /* Various very early CPU fix ups */ 197 switch (mfpvr() >> 16) { 198 /* 199 * PowerPC 970 CPUs have a misfeature requested by Apple that 200 * makes them pretend they have a 32-byte cacheline. Turn this 201 * off before we measure the cacheline size. 202 */ 203 case IBM970: 204 case IBM970FX: 205 case IBM970MP: 206 case IBM970GX: 207 scratch = mfspr(SPR_HID5); 208 scratch &= ~HID5_970_DCBZ_SIZE_HI; 209 mtspr(SPR_HID5, scratch); 210 break; 211 #ifdef __powerpc64__ 212 case IBMPOWER7: 213 case IBMPOWER7PLUS: 214 case IBMPOWER8: 215 case IBMPOWER8E: 216 case IBMPOWER8NVL: 217 case IBMPOWER9: 218 /* XXX: get from ibm,slb-size in device tree */ 219 n_slbs = 32; 220 break; 221 #endif 222 } 223 } 224 225 void 226 aim_cpu_init(vm_offset_t toc) 227 { 228 size_t trap_offset, trapsize; 229 vm_offset_t trap; 230 register_t msr; 231 uint8_t *cache_check; 232 int cacheline_warn; 233 #ifndef __powerpc64__ 234 register_t scratch; 235 int ppc64; 236 #endif 237 238 trap_offset = 0; 239 cacheline_warn = 0; 240 241 /* General setup for AIM CPUs */ 242 psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 243 244 #ifdef __powerpc64__ 245 psl_kernset |= PSL_SF; 246 if (mfmsr() & PSL_HV) 247 psl_kernset |= PSL_HV; 248 #endif 249 psl_userset = psl_kernset | PSL_PR; 250 #ifdef __powerpc64__ 251 psl_userset32 = psl_userset & ~PSL_SF; 252 #endif 253 254 /* 255 * Zeroed bits in this variable signify that the value of the bit 256 * in its position is allowed to vary between userspace contexts. 257 * 258 * All other bits are required to be identical for every userspace 259 * context. The actual *value* of the bit is determined by 260 * psl_userset and/or psl_userset32, and is not allowed to change. 261 * 262 * Remember to update this set when implementing support for 263 * *conditionally* enabling a processor facility. Failing to do 264 * this will cause swapcontext() in userspace to break when a 265 * process uses a conditionally-enabled facility. 266 * 267 * When *unconditionally* implementing support for a processor 268 * facility, update psl_userset / psl_userset32 instead. 269 * 270 * See the access control check in set_mcontext(). 271 */ 272 psl_userstatic = ~(PSL_VSX | PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 273 /* 274 * Mask bits from the SRR1 that aren't really the MSR: 275 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) 276 */ 277 psl_userstatic &= ~0x783f0000UL; 278 279 /* 280 * Initialize the interrupt tables and figure out our cache line 281 * size and whether or not we need the 64-bit bridge code. 282 */ 283 284 /* 285 * Disable translation in case the vector area hasn't been 286 * mapped (G5). Note that no OFW calls can be made until 287 * translation is re-enabled. 288 */ 289 290 msr = mfmsr(); 291 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); 292 293 /* 294 * Measure the cacheline size using dcbz 295 * 296 * Use EXC_PGM as a playground. We are about to overwrite it 297 * anyway, we know it exists, and we know it is cache-aligned. 298 */ 299 300 cache_check = (void *)EXC_PGM; 301 302 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++) 303 cache_check[cacheline_size] = 0xff; 304 305 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory"); 306 307 /* Find the first byte dcbz did not zero to get the cache line size */ 308 for (cacheline_size = 0; cacheline_size < 0x100 && 309 cache_check[cacheline_size] == 0; cacheline_size++); 310 311 /* Work around psim bug */ 312 if (cacheline_size == 0) { 313 cacheline_warn = 1; 314 cacheline_size = 32; 315 } 316 317 #ifndef __powerpc64__ 318 /* 319 * Figure out whether we need to use the 64 bit PMAP. This works by 320 * executing an instruction that is only legal on 64-bit PPC (mtmsrd), 321 * and setting ppc64 = 0 if that causes a trap. 322 */ 323 324 ppc64 = 1; 325 326 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size); 327 __syncicache((void *)EXC_PGM, (size_t)&testppc64size); 328 329 __asm __volatile("\ 330 mfmsr %0; \ 331 mtsprg2 %1; \ 332 \ 333 mtmsrd %0; \ 334 mfsprg2 %1;" 335 : "=r"(scratch), "=r"(ppc64)); 336 337 if (ppc64) 338 cpu_features |= PPC_FEATURE_64; 339 340 /* 341 * Now copy restorebridge into all the handlers, if necessary, 342 * and set up the trap tables. 343 */ 344 345 if (cpu_features & PPC_FEATURE_64) { 346 /* Patch the two instances of rfi -> rfid */ 347 bcopy(&rfid_patch,&rfi_patch1,4); 348 #ifdef KDB 349 /* rfi_patch2 is at the end of dbleave */ 350 bcopy(&rfid_patch,&rfi_patch2,4); 351 #endif 352 } 353 #else /* powerpc64 */ 354 cpu_features |= PPC_FEATURE_64; 355 #endif 356 357 trapsize = (size_t)&trapcodeend - (size_t)&trapcode; 358 359 /* 360 * Copy generic handler into every possible trap. Special cases will get 361 * different ones in a minute. 362 */ 363 for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20) 364 bcopy(&trapcode, (void *)trap, trapsize); 365 366 #ifndef __powerpc64__ 367 if (cpu_features & PPC_FEATURE_64) { 368 /* 369 * Copy a code snippet to restore 32-bit bridge mode 370 * to the top of every non-generic trap handler 371 */ 372 373 trap_offset += (size_t)&restorebridgesize; 374 bcopy(&restorebridge, (void *)EXC_RST, trap_offset); 375 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset); 376 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset); 377 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset); 378 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset); 379 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset); 380 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset); 381 } 382 #else 383 trapsize = (size_t)&hypertrapcodeend - (size_t)&hypertrapcode; 384 bcopy(&hypertrapcode, (void *)(EXC_HEA + trap_offset), trapsize); 385 bcopy(&hypertrapcode, (void *)(EXC_HMI + trap_offset), trapsize); 386 bcopy(&hypertrapcode, (void *)(EXC_HVI + trap_offset), trapsize); 387 bcopy(&hypertrapcode, (void *)(EXC_SOFT_PATCH + trap_offset), trapsize); 388 #endif 389 390 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend - 391 (size_t)&rstcode); 392 393 #ifdef KDB 394 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend - 395 (size_t)&dblow); 396 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend - 397 (size_t)&dblow); 398 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend - 399 (size_t)&dblow); 400 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend - 401 (size_t)&dblow); 402 #endif 403 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend - 404 (size_t)&alitrap); 405 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend - 406 (size_t)&dsitrap); 407 408 /* Set address of generictrap for self-reloc calculations */ 409 *((void **)TRAP_GENTRAP) = &generictrap; 410 #ifdef __powerpc64__ 411 /* Set TOC base so that the interrupt code can get at it */ 412 *((void **)TRAP_ENTRY) = &generictrap; 413 *((register_t *)TRAP_TOCBASE) = toc; 414 #else 415 /* Set branch address for trap code */ 416 if (cpu_features & PPC_FEATURE_64) 417 *((void **)TRAP_ENTRY) = &generictrap64; 418 else 419 *((void **)TRAP_ENTRY) = &generictrap; 420 *((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_; 421 422 /* G2-specific TLB miss helper handlers */ 423 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); 424 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); 425 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 426 #endif 427 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 428 429 /* 430 * Restore MSR 431 */ 432 mtmsr(msr); 433 434 /* Warn if cachline size was not determined */ 435 if (cacheline_warn == 1) { 436 printf("WARNING: cacheline size undetermined, setting to 32\n"); 437 } 438 439 /* 440 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority 441 * in case the platform module had a better idea of what we 442 * should do. 443 */ 444 if (cpu_features & PPC_FEATURE_64) 445 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 446 else 447 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 448 } 449 450 /* 451 * Shutdown the CPU as much as possible. 452 */ 453 void 454 cpu_halt(void) 455 { 456 457 OF_exit(); 458 } 459 460 int 461 ptrace_single_step(struct thread *td) 462 { 463 struct trapframe *tf; 464 465 tf = td->td_frame; 466 tf->srr1 |= PSL_SE; 467 468 return (0); 469 } 470 471 int 472 ptrace_clear_single_step(struct thread *td) 473 { 474 struct trapframe *tf; 475 476 tf = td->td_frame; 477 tf->srr1 &= ~PSL_SE; 478 479 return (0); 480 } 481 482 void 483 kdb_cpu_clear_singlestep(void) 484 { 485 486 kdb_frame->srr1 &= ~PSL_SE; 487 } 488 489 void 490 kdb_cpu_set_singlestep(void) 491 { 492 493 kdb_frame->srr1 |= PSL_SE; 494 } 495 496 /* 497 * Initialise a struct pcpu. 498 */ 499 void 500 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 501 { 502 #ifdef __powerpc64__ 503 /* Copy the SLB contents from the current CPU */ 504 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb)); 505 #endif 506 } 507 508 #ifndef __powerpc64__ 509 uint64_t 510 va_to_vsid(pmap_t pm, vm_offset_t va) 511 { 512 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 513 } 514 515 #endif 516 517 /* 518 * These functions need to provide addresses that both (a) work in real mode 519 * (or whatever mode/circumstances the kernel is in in early boot (now)) and 520 * (b) can still, in principle, work once the kernel is going. Because these 521 * rely on existing mappings/real mode, unmap is a no-op. 522 */ 523 vm_offset_t 524 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 525 { 526 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 527 528 /* 529 * If we have the MMU up in early boot, assume it is 1:1. Otherwise, 530 * try to get the address in a memory region compatible with the 531 * direct map for efficiency later. 532 */ 533 if (mfmsr() & PSL_DR) 534 return (pa); 535 else 536 return (DMAP_BASE_ADDRESS + pa); 537 } 538 539 void 540 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 541 { 542 543 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 544 } 545 546 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */ 547 void 548 flush_disable_caches(void) 549 { 550 register_t msr; 551 register_t msscr0; 552 register_t cache_reg; 553 volatile uint32_t *memp; 554 uint32_t temp; 555 int i; 556 int x; 557 558 msr = mfmsr(); 559 powerpc_sync(); 560 mtmsr(msr & ~(PSL_EE | PSL_DR)); 561 msscr0 = mfspr(SPR_MSSCR0); 562 msscr0 &= ~MSSCR0_L2PFE; 563 mtspr(SPR_MSSCR0, msscr0); 564 powerpc_sync(); 565 isync(); 566 __asm__ __volatile__("dssall; sync"); 567 powerpc_sync(); 568 isync(); 569 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 570 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 571 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 572 573 /* Lock the L1 Data cache. */ 574 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); 575 powerpc_sync(); 576 isync(); 577 578 mtspr(SPR_LDSTCR, 0); 579 580 /* 581 * Perform this in two stages: Flush the cache starting in RAM, then do it 582 * from ROM. 583 */ 584 memp = (volatile uint32_t *)0x00000000; 585 for (i = 0; i < 128 * 1024; i++) { 586 temp = *memp; 587 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 588 memp += 32/sizeof(*memp); 589 } 590 591 memp = (volatile uint32_t *)0xfff00000; 592 x = 0xfe; 593 594 for (; x != 0xff;) { 595 mtspr(SPR_LDSTCR, x); 596 for (i = 0; i < 128; i++) { 597 temp = *memp; 598 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 599 memp += 32/sizeof(*memp); 600 } 601 x = ((x << 1) | 1) & 0xff; 602 } 603 mtspr(SPR_LDSTCR, 0); 604 605 cache_reg = mfspr(SPR_L2CR); 606 if (cache_reg & L2CR_L2E) { 607 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450); 608 mtspr(SPR_L2CR, cache_reg); 609 powerpc_sync(); 610 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); 611 while (mfspr(SPR_L2CR) & L2CR_L2HWF) 612 ; /* Busy wait for cache to flush */ 613 powerpc_sync(); 614 cache_reg &= ~L2CR_L2E; 615 mtspr(SPR_L2CR, cache_reg); 616 powerpc_sync(); 617 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); 618 powerpc_sync(); 619 while (mfspr(SPR_L2CR) & L2CR_L2I) 620 ; /* Busy wait for L2 cache invalidate */ 621 powerpc_sync(); 622 } 623 624 cache_reg = mfspr(SPR_L3CR); 625 if (cache_reg & L3CR_L3E) { 626 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO); 627 mtspr(SPR_L3CR, cache_reg); 628 powerpc_sync(); 629 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); 630 while (mfspr(SPR_L3CR) & L3CR_L3HWF) 631 ; /* Busy wait for cache to flush */ 632 powerpc_sync(); 633 cache_reg &= ~L3CR_L3E; 634 mtspr(SPR_L3CR, cache_reg); 635 powerpc_sync(); 636 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); 637 powerpc_sync(); 638 while (mfspr(SPR_L3CR) & L3CR_L3I) 639 ; /* Busy wait for L3 cache invalidate */ 640 powerpc_sync(); 641 } 642 643 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); 644 powerpc_sync(); 645 isync(); 646 647 mtmsr(msr); 648 } 649 650 void 651 cpu_sleep() 652 { 653 static u_quad_t timebase = 0; 654 static register_t sprgs[4]; 655 static register_t srrs[2]; 656 657 jmp_buf resetjb; 658 struct thread *fputd; 659 struct thread *vectd; 660 register_t hid0; 661 register_t msr; 662 register_t saved_msr; 663 664 ap_pcpu = pcpup; 665 666 PCPU_SET(restore, &resetjb); 667 668 saved_msr = mfmsr(); 669 fputd = PCPU_GET(fputhread); 670 vectd = PCPU_GET(vecthread); 671 if (fputd != NULL) 672 save_fpu(fputd); 673 if (vectd != NULL) 674 save_vec(vectd); 675 if (setjmp(resetjb) == 0) { 676 sprgs[0] = mfspr(SPR_SPRG0); 677 sprgs[1] = mfspr(SPR_SPRG1); 678 sprgs[2] = mfspr(SPR_SPRG2); 679 sprgs[3] = mfspr(SPR_SPRG3); 680 srrs[0] = mfspr(SPR_SRR0); 681 srrs[1] = mfspr(SPR_SRR1); 682 timebase = mftb(); 683 powerpc_sync(); 684 flush_disable_caches(); 685 hid0 = mfspr(SPR_HID0); 686 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP; 687 powerpc_sync(); 688 isync(); 689 msr = mfmsr() | PSL_POW; 690 mtspr(SPR_HID0, hid0); 691 powerpc_sync(); 692 693 while (1) 694 mtmsr(msr); 695 } 696 platform_smp_timebase_sync(timebase, 0); 697 PCPU_SET(curthread, curthread); 698 PCPU_SET(curpcb, curthread->td_pcb); 699 pmap_activate(curthread); 700 powerpc_sync(); 701 mtspr(SPR_SPRG0, sprgs[0]); 702 mtspr(SPR_SPRG1, sprgs[1]); 703 mtspr(SPR_SPRG2, sprgs[2]); 704 mtspr(SPR_SPRG3, sprgs[3]); 705 mtspr(SPR_SRR0, srrs[0]); 706 mtspr(SPR_SRR1, srrs[1]); 707 mtmsr(saved_msr); 708 if (fputd == curthread) 709 enable_fpu(curthread); 710 if (vectd == curthread) 711 enable_vec(curthread); 712 powerpc_sync(); 713 } 714 715