1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef MLX5_ABI_USER_H 36 #define MLX5_ABI_USER_H 37 38 #ifdef _KERNEL 39 #include <linux/types.h> 40 #else 41 #include <infiniband/types.h> 42 #endif 43 44 enum { 45 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 46 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 47 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 48 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 49 }; 50 51 enum { 52 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 53 }; 54 55 enum { 56 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 57 }; 58 59 /* Increment this value if any changes that break userspace ABI 60 * compatibility are made. 61 */ 62 #define MLX5_IB_UVERBS_ABI_VERSION 1 63 64 /* Make sure that all structs defined in this file remain laid out so 65 * that they pack the same way on 32-bit and 64-bit architectures (to 66 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 67 * In particular do not use pointer types -- pass pointers in __u64 68 * instead. 69 */ 70 71 struct mlx5_ib_alloc_ucontext_req { 72 __u32 total_num_bfregs; 73 __u32 num_low_latency_bfregs; 74 }; 75 76 enum mlx5_lib_caps { 77 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 78 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, 79 }; 80 81 enum mlx5_ib_alloc_uctx_v2_flags { 82 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 83 }; 84 struct mlx5_ib_alloc_ucontext_req_v2 { 85 __u32 total_num_bfregs; 86 __u32 num_low_latency_bfregs; 87 __u32 flags; 88 __u32 comp_mask; 89 __u8 max_cqe_version; 90 __u8 reserved0; 91 __u16 reserved1; 92 __u32 reserved2; 93 __aligned_u64 lib_caps; 94 }; 95 96 enum mlx5_ib_alloc_ucontext_resp_mask { 97 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 98 }; 99 100 enum mlx5_user_cmds_supp_uhw { 101 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 102 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 103 }; 104 105 struct mlx5_ib_alloc_ucontext_resp { 106 __u32 qp_tab_size; 107 __u32 bf_reg_size; 108 __u32 tot_bfregs; 109 __u32 cache_line_size; 110 __u16 max_sq_desc_sz; 111 __u16 max_rq_desc_sz; 112 __u32 max_send_wqebb; 113 __u32 max_recv_wr; 114 __u32 max_srq_recv_wr; 115 __u16 num_ports; 116 __u16 reserved1; 117 __u32 comp_mask; 118 __u32 response_length; 119 __u8 cqe_version; 120 __u8 cmds_supp_uhw; 121 __u16 reserved2; 122 __u64 hca_core_clock_offset; 123 __u32 log_uar_size; 124 __u32 num_uars_per_page; 125 __u32 num_dyn_bfregs; 126 }; 127 128 struct mlx5_ib_alloc_pd_resp { 129 __u32 pdn; 130 }; 131 132 struct mlx5_ib_tso_caps { 133 __u32 max_tso; /* Maximum tso payload size in bytes */ 134 135 /* Corresponding bit will be set if qp type from 136 * 'enum ib_qp_type' is supported, e.g. 137 * supported_qpts |= 1 << IB_QPT_UD 138 */ 139 __u32 supported_qpts; 140 }; 141 142 struct mlx5_ib_rss_caps { 143 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 144 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 145 __u8 reserved[7]; 146 }; 147 148 struct mlx5_ib_query_device_resp { 149 __u32 comp_mask; 150 __u32 response_length; 151 struct mlx5_ib_tso_caps tso_caps; 152 struct mlx5_ib_rss_caps rss_caps; 153 }; 154 155 enum mlx5_ib_create_cq_flags { 156 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 157 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 158 }; 159 160 struct mlx5_ib_create_cq { 161 __u64 buf_addr; 162 __u64 db_addr; 163 __u32 cqe_size; 164 __u16 flags; 165 __u16 uar_page_index; 166 }; 167 168 struct mlx5_ib_create_cq_resp { 169 __u32 cqn; 170 __u32 reserved; 171 }; 172 173 struct mlx5_ib_resize_cq { 174 __u64 buf_addr; 175 __u16 cqe_size; 176 __u16 reserved0; 177 __u32 reserved1; 178 }; 179 180 struct mlx5_ib_create_srq { 181 __u64 buf_addr; 182 __u64 db_addr; 183 __u32 flags; 184 __u32 reserved0; /* explicit padding (optional on i386) */ 185 __u32 uidx; 186 __u32 reserved1; 187 }; 188 189 struct mlx5_ib_create_srq_resp { 190 __u32 srqn; 191 __u32 reserved; 192 }; 193 194 struct mlx5_ib_create_qp { 195 __u64 buf_addr; 196 __u64 db_addr; 197 __u32 sq_wqe_count; 198 __u32 rq_wqe_count; 199 __u32 rq_wqe_shift; 200 __u32 flags; 201 __u32 uidx; 202 __u32 bfreg_index; 203 __u64 sq_buf_addr; 204 }; 205 206 /* RX Hash function flags */ 207 enum mlx5_rx_hash_function_flags { 208 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 209 }; 210 211 /* 212 * RX Hash flags, these flags allows to set which incoming packet's field should 213 * participates in RX Hash. Each flag represent certain packet's field, 214 * when the flag is set the field that is represented by the flag will 215 * participate in RX Hash calculation. 216 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 217 * and *TCP and *UDP flags can't be enabled together on the same QP. 218 */ 219 enum mlx5_rx_hash_fields { 220 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 221 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 222 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 223 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 224 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 225 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 226 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 227 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 228 }; 229 230 struct mlx5_ib_create_qp_rss { 231 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 232 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 233 __u8 rx_key_len; /* valid only for Toeplitz */ 234 __u8 reserved[6]; 235 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 236 __u32 comp_mask; 237 __u32 reserved1; 238 }; 239 240 struct mlx5_ib_create_qp_resp { 241 __u32 bfreg_index; 242 }; 243 244 struct mlx5_ib_alloc_mw { 245 __u32 comp_mask; 246 __u8 num_klms; 247 __u8 reserved1; 248 __u16 reserved2; 249 }; 250 251 struct mlx5_ib_create_wq { 252 __u64 buf_addr; 253 __u64 db_addr; 254 __u32 rq_wqe_count; 255 __u32 rq_wqe_shift; 256 __u32 user_index; 257 __u32 flags; 258 __u32 comp_mask; 259 __u32 reserved; 260 }; 261 262 struct mlx5_ib_create_ah_resp { 263 __u32 response_length; 264 __u8 dmac[ETH_ALEN]; 265 __u8 reserved[6]; 266 }; 267 268 struct mlx5_ib_create_wq_resp { 269 __u32 response_length; 270 __u32 reserved; 271 }; 272 273 struct mlx5_ib_create_rwq_ind_tbl_resp { 274 __u32 response_length; 275 __u32 reserved; 276 }; 277 278 struct mlx5_ib_modify_wq { 279 __u32 comp_mask; 280 __u32 reserved; 281 }; 282 283 enum mlx5_ib_mmap_cmd { 284 MLX5_IB_MMAP_REGULAR_PAGE = 0, 285 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 286 MLX5_IB_MMAP_WC_PAGE = 2, 287 MLX5_IB_MMAP_NC_PAGE = 3, 288 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 289 MLX5_IB_MMAP_CORE_CLOCK = 5, 290 MLX5_IB_MMAP_ALLOC_WC = 6, 291 MLX5_IB_MMAP_CLOCK_INFO = 7, 292 MLX5_IB_MMAP_DEVICE_MEM = 8, 293 }; 294 295 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 296 enum { 297 MLX5_IB_CLOCK_INFO_V1 = 0, 298 }; 299 300 struct mlx5_ib_flow_counters_desc { 301 __u32 description; 302 __u32 index; 303 }; 304 305 struct mlx5_ib_flow_counters_data { 306 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 307 __u32 ncounters; 308 __u32 reserved; 309 }; 310 311 struct mlx5_ib_create_flow { 312 __u32 ncounters_data; 313 __u32 reserved; 314 /* 315 * Following are counters data based on ncounters_data, each 316 * entry in the data[] should match a corresponding counter object 317 * that was pointed by a counters spec upon the flow creation 318 */ 319 struct mlx5_ib_flow_counters_data data[]; 320 }; 321 322 #endif /* MLX5_ABI_USER_H */ 323