xref: /freebsd/sys/net/sff8472.h (revision e716630d4cf89e69ec3f675ebfceee09f1a85e05)
1  /*-
2   * SPDX-License-Identifier: BSD-2-Clause
3   *
4   * Copyright (c) 2013 George V. Neville-Neil
5   * All rights reserved.
6   *
7   * Redistribution and use in source and binary forms, with or without
8   * modification, are permitted provided that the following conditions
9   * are met:
10   * 1. Redistributions of source code must retain the above copyright
11   *    notice, this list of conditions and the following disclaimer.
12   * 2. Redistributions in binary form must reproduce the above copyright
13   *    notice, this list of conditions and the following disclaimer in the
14   *    documentation and/or other materials provided with the distribution.
15   *
16   * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17   * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19   * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22   * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23   * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26   * SUCH DAMAGE.
27   */
28  
29  /*
30   * The following set of constants are from Document SFF-8472
31   * "Diagnostic Monitoring Interface for Optical Transceivers" revision
32   * 11.3 published by the SFF Committee on June 11, 2013
33   *
34   * The SFF standard defines two ranges of addresses, each 255 bytes
35   * long for the storage of data and diagnostics on cables, such as
36   * SFP+ optics and TwinAx cables.  The ranges are defined in the
37   * following way:
38   *
39   * Base Address 0xa0 (Identification Data)
40   * 0-95    Serial ID Defined by SFP MSA
41   * 96-127  Vendor Specific Data
42   * 128-255 Reserved
43   *
44   * Base Address 0xa2 (Diagnostic Data)
45   * 0-55    Alarm and Warning Thresholds
46   * 56-95   Cal Constants
47   * 96-119  Real Time Diagnostic Interface
48   * 120-127 Vendor Specific
49   * 128-247 User Writable EEPROM
50   * 248-255 Vendor Specific
51   *
52   * Note that not all addresses are supported.  Where support is
53   * optional this is noted and instructions for checking for the
54   * support are supplied.
55   *
56   * All these values are read across an I2C (i squared C) bus.  Any
57   * device wishing to read these addresses must first have support for
58   * i2c calls.  The Chelsio T4/T5 driver (dev/cxgbe) is one such
59   * driver.
60   */
61  
62  /* Table 3.1 Two-wire interface ID: Data Fields */
63  
64  enum {
65  	SFF_8472_BASE 		= 0xa0,   /* Base address for all our queries. */
66  	SFF_8472_ID		= 0,  /* Transceiver Type (Table 3.2) */
67  	SFF_8472_EXT_ID		= 1,  /* Extended transceiver type (Table 3.3) */
68  	SFF_8472_CONNECTOR	= 2,  /* Connector type (Table 3.4) */
69  	SFF_8472_TRANS_START	= 3,  /* Elec or Optical Compatibility
70  				    * (Table 3.5) */
71  	SFF_8472_TRANS_END	= 10,
72  	SFF_8472_ENCODING	= 11, /* Encoding Code for high speed
73  				     * serial encoding algorithm (see
74  				     * Table 3.6) */
75  	SFF_8472_BITRATE	= 12, /* Nominal signaling rate, units
76  				     * of 100MBd.  (see details for
77  				     * rates > 25.0Gb/s) */
78  	SFF_8472_RATEID		= 13, /* Type of rate select
79  				     * functionality (see Table
80  				     * 3.6a) */
81  	SFF_8472_LEN_SMF_KM	= 14, /* Link length supported for single
82  				    * mode fiber, units of km */
83  	SFF_8472_LEN_SMF	= 15, /* Link length supported for single
84  				    * mode fiber, units of 100 m */
85  	SFF_8472_LEN_50UM	= 16, /* Link length supported for 50 um
86  				    * OM2 fiber, units of 10 m */
87  	SFF_8472_LEN_625UM	= 17, /* Link length supported for 62.5
88  				    * um OM1 fiber, units of 10 m */
89  	SFF_8472_LEN_OM4	= 18, /* Link length supported for 50um
90  				    * OM4 fiber, units of 10m.
91  				    * Alternatively copper or direct
92  				    * attach cable, units of m */
93  	SFF_8472_LEN_OM3	= 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */
94  	SFF_8472_VENDOR_START 	= 20, /* Vendor name [Address A0h, Bytes
95  				    * 20-35] */
96  	SFF_8472_VENDOR_END 	= 35,
97  	SFF_8472_TRANS		= 36, /* Transceiver Code for electronic
98  				    * or optical compatibility (see
99  				    * Table 3.5) */
100  	SFF_8472_VENDOR_OUI_START	= 37, /* Vendor OUI SFP vendor IEEE
101  				    * company ID */
102  	SFF_8472_VENDOR_OUI_END	= 39,
103  	SFF_8472_PN_START 	= 40, /* Vendor PN */
104  	SFF_8472_PN_END 	= 55,
105  	SFF_8472_REV_START 	= 56, /* Vendor Revision */
106  	SFF_8472_REV_END 	= 59,
107  	SFF_8472_WAVELEN_START	= 60, /* Wavelength Laser wavelength
108  				    * (Passive/Active Cable
109  				    * Specification Compliance) */
110  	SFF_8472_WAVELEN_END	= 61,
111  	SFF_8472_CC_BASE	= 63, /* CC_BASE Check code for Base ID
112  				    * Fields (addresses 0 to 62) */
113  
114  /*
115   * Extension Fields (optional) check the options before reading other
116   * addresses.
117   */
118  	SFF_8472_OPTIONS_MSB	= 64, /* Options Indicates which optional
119  				    * transceiver signals are
120  				    * implemented */
121  	SFF_8472_OPTIONS_LSB	= 65, /* (see Table 3.7) */
122  	SFF_8472_BR_MAX		= 66, /* BR max Upper bit rate margin,
123  				    * units of % (see details for
124  				    * rates > 25.0Gb/s) */
125  	SFF_8472_BR_MIN		= 67, /* Lower bit rate margin, units of
126  				    * % (see details for rates >
127  				    * 25.0Gb/s) */
128  	SFF_8472_SN_START 	= 68, /* Vendor SN [Address A0h, Bytes 68-83] */
129  	SFF_8472_SN_END 	= 83,
130  	SFF_8472_DATE_START	= 84, /* Date code Vendor’s manufacturing
131  				    * date code (see Table 3.8) */
132  	SFF_8472_DATE_END	= 91,
133  	SFF_8472_DIAG_TYPE	= 92, /* Diagnostic Monitoring Type
134  				    * Indicates which type of
135  				    * diagnostic monitoring is
136  				    * implemented (if any) in the
137  				    * transceiver (see Table 3.9)
138  				    */
139  
140  	SFF_8472_ENHANCED	= 93, /* Enhanced Options Indicates which
141  				    * optional enhanced features are
142  				    * implemented (if any) in the
143  				    * transceiver (see Table 3.10) */
144  	SFF_8472_COMPLIANCE	= 94, /* SFF-8472 Compliance Indicates
145  				    * which revision of SFF-8472 the
146  				    * transceiver complies with.  (see
147  				    * Table 3.12)*/
148  	SFF_8472_CC_EXT		= 95, /* Check code for the Extended ID
149  				    * Fields (addresses 64 to 94)
150  				    */
151  
152  	SFF_8472_VENDOR_RSRVD_START	= 96,
153  	SFF_8472_VENDOR_RSRVD_END	= 127,
154  
155  	SFF_8472_RESERVED_START	= 128,
156  	SFF_8472_RESERVED_END	= 255
157  };
158  
159  #define SFF_8472_DIAG_IMPL	(1 << 6) /* Required to be 1 */
160  #define SFF_8472_DIAG_INTERNAL	(1 << 5) /* Internal measurements. */
161  #define SFF_8472_DIAG_EXTERNAL	(1 << 4) /* External measurements. */
162  #define SFF_8472_DIAG_POWER	(1 << 3) /* Power measurement type */
163  #define SFF_8472_DIAG_ADDR_CHG	(1 << 2) /* Address change required.
164  					  * See SFF-8472 doc. */
165  
166   /*
167    * Diagnostics are available at the two wire address 0xa2.  All
168    * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to
169    * see which, if any are supported.
170    */
171  
172  enum {SFF_8472_DIAG = 0xa2};  /* Base address for diagnostics. */
173  
174   /*
175    *  Table 3.15 Alarm and Warning Thresholds All values are 2 bytes
176    * and MUST be read in a single read operation starting at the MSB
177    */
178  
179  enum {
180  	SFF_8472_TEMP_HIGH_ALM		= 0, /* Temp High Alarm  */
181  	SFF_8472_TEMP_LOW_ALM		= 2, /* Temp Low Alarm */
182  	SFF_8472_TEMP_HIGH_WARN		= 4, /* Temp High Warning */
183  	SFF_8472_TEMP_LOW_WARN		= 6, /* Temp Low Warning */
184  	SFF_8472_VOLTAGE_HIGH_ALM	= 8, /* Voltage High Alarm */
185  	SFF_8472_VOLTAGE_LOW_ALM	= 10, /* Voltage Low Alarm */
186  	SFF_8472_VOLTAGE_HIGH_WARN	= 12, /* Voltage High Warning */
187  	SFF_8472_VOLTAGE_LOW_WARN	= 14, /* Voltage Low Warning */
188  	SFF_8472_BIAS_HIGH_ALM		= 16, /* Bias High Alarm */
189  	SFF_8472_BIAS_LOW_ALM		= 18, /* Bias Low Alarm */
190  	SFF_8472_BIAS_HIGH_WARN		= 20, /* Bias High Warning */
191  	SFF_8472_BIAS_LOW_WARN		= 22, /* Bias Low Warning */
192  	SFF_8472_TX_POWER_HIGH_ALM	= 24, /* TX Power High Alarm */
193  	SFF_8472_TX_POWER_LOW_ALM	= 26, /* TX Power Low Alarm */
194  	SFF_8472_TX_POWER_HIGH_WARN	= 28, /* TX Power High Warning */
195  	SFF_8472_TX_POWER_LOW_WARN	= 30, /* TX Power Low Warning */
196  	SFF_8472_RX_POWER_HIGH_ALM	= 32, /* RX Power High Alarm */
197  	SFF_8472_RX_POWER_LOW_ALM	= 34, /* RX Power Low Alarm */
198  	SFF_8472_RX_POWER_HIGH_WARN	= 36, /* RX Power High Warning */
199  	SFF_8472_RX_POWER_LOW_WARN	= 38, /* RX Power Low Warning */
200  
201  	SFF_8472_RX_POWER4	= 56, /* Rx_PWR(4) Single precision
202  				    *  floating point calibration data
203  				    *  - Rx optical power. Bit 7 of
204  				    *  byte 56 is MSB. Bit 0 of byte
205  				    *  59 is LSB. Rx_PWR(4) should be
206  				    *  set to zero for “internally
207  				    *  calibrated” devices. */
208  	SFF_8472_RX_POWER3	= 60, /* Rx_PWR(3) Single precision
209  				    * floating point calibration data
210  				    * - Rx optical power.  Bit 7 of
211  				    * byte 60 is MSB. Bit 0 of byte 63
212  				    * is LSB. Rx_PWR(3) should be set
213  				    * to zero for “internally
214  				    * calibrated” devices.*/
215  	SFF_8472_RX_POWER2	= 64, /* Rx_PWR(2) Single precision
216  				    * floating point calibration data,
217  				    * Rx optical power.  Bit 7 of byte
218  				    * 64 is MSB, bit 0 of byte 67 is
219  				    * LSB. Rx_PWR(2) should be set to
220  				    * zero for “internally calibrated”
221  				    * devices. */
222  	SFF_8472_RX_POWER1	= 68, /* Rx_PWR(1) Single precision
223  				    * floating point calibration data,
224  				    * Rx optical power. Bit 7 of byte
225  				    * 68 is MSB, bit 0 of byte 71 is
226  				    * LSB. Rx_PWR(1) should be set to
227  				    * 1 for “internally calibrated”
228  				    * devices. */
229  	SFF_8472_RX_POWER0	= 72, /* Rx_PWR(0) Single precision
230  				    * floating point calibration data,
231  				    * Rx optical power. Bit 7 of byte
232  				    * 72 is MSB, bit 0 of byte 75 is
233  				    * LSB. Rx_PWR(0) should be set to
234  				    * zero for “internally calibrated”
235  				    * devices. */
236  	SFF_8472_TX_I_SLOPE	= 76, /* Tx_I(Slope) Fixed decimal
237  				    * (unsigned) calibration data,
238  				    * laser bias current. Bit 7 of
239  				    * byte 76 is MSB, bit 0 of byte 77
240  				    * is LSB. Tx_I(Slope) should be
241  				    * set to 1 for “internally
242  				    * calibrated” devices. */
243  	SFF_8472_TX_I_OFFSET	= 78, /* Tx_I(Offset) Fixed decimal
244  				    * (signed two’s complement)
245  				    * calibration data, laser bias
246  				    * current. Bit 7 of byte 78 is
247  				    * MSB, bit 0 of byte 79 is
248  				    * LSB. Tx_I(Offset) should be set
249  				    * to zero for “internally
250  				    * calibrated” devices. */
251  	SFF_8472_TX_POWER_SLOPE	= 80, /* Tx_PWR(Slope) Fixed decimal
252  				    * (unsigned) calibration data,
253  				    * transmitter coupled output
254  				    * power. Bit 7 of byte 80 is MSB,
255  				    * bit 0 of byte 81 is LSB.
256  				    * Tx_PWR(Slope) should be set to 1
257  				    * for “internally calibrated”
258  				    * devices. */
259  	SFF_8472_TX_POWER_OFFSET	= 82, /* Tx_PWR(Offset) Fixed decimal
260  					    * (signed two’s complement)
261  					    * calibration data, transmitter
262  					    * coupled output power. Bit 7 of
263  					    * byte 82 is MSB, bit 0 of byte 83
264  					    * is LSB. Tx_PWR(Offset) should be
265  					    * set to zero for “internally
266  					    * calibrated” devices. */
267  	SFF_8472_T_SLOPE	= 84, /* T (Slope) Fixed decimal
268  				    * (unsigned) calibration data,
269  				    * internal module temperature. Bit
270  				    * 7 of byte 84 is MSB, bit 0 of
271  				    * byte 85 is LSB.  T(Slope) should
272  				    * be set to 1 for “internally
273  				    * calibrated” devices. */
274  	SFF_8472_T_OFFSET	= 86, /* T (Offset) Fixed decimal (signed
275  				    * two’s complement) calibration
276  				    * data, internal module
277  				    * temperature. Bit 7 of byte 86 is
278  				    * MSB, bit 0 of byte 87 is LSB.
279  				    * T(Offset) should be set to zero
280  				    * for “internally calibrated”
281  				    * devices. */
282  	SFF_8472_V_SLOPE	= 88, /* V (Slope) Fixed decimal
283  				    * (unsigned) calibration data,
284  				    * internal module supply
285  				    * voltage. Bit 7 of byte 88 is
286  				    * MSB, bit 0 of byte 89 is
287  				    * LSB. V(Slope) should be set to 1
288  				    * for “internally calibrated”
289  				    * devices. */
290  	SFF_8472_V_OFFSET	= 90, /* V (Offset) Fixed decimal (signed
291  				    * two’s complement) calibration
292  				    * data, internal module supply
293  				    * voltage. Bit 7 of byte 90 is
294  				    * MSB. Bit 0 of byte 91 is
295  				    * LSB. V(Offset) should be set to
296  				    * zero for “internally calibrated”
297  				    * devices. */
298  	SFF_8472_CHECKSUM	= 95, /* Checksum Byte 95 contains the
299  				    * low order 8 bits of the sum of
300  				    * bytes 0 – 94. */
301  	/* Internal measurements. */
302  
303  	SFF_8472_TEMP	 	= 96, /* Internally measured module temperature. */
304  	SFF_8472_VCC 		= 98, /* Internally measured supply
305  				    * voltage in transceiver.
306  				    */
307  	SFF_8472_TX_BIAS	= 100, /* Internally measured TX Bias Current. */
308  	SFF_8472_TX_POWER	= 102, /* Measured TX output power. */
309  	SFF_8472_RX_POWER	= 104, /* Measured RX input power. */
310  
311  	SFF_8472_STATUS		= 110 /* See below */
312  };
313   /* Status Bits Described */
314  
315  /*
316   * TX Disable State Digital state of the TX Disable Input Pin. Updated
317   * within 100ms of change on pin.
318   */
319  #define SFF_8472_STATUS_TX_DISABLE  (1 << 7)
320  
321  /*
322   * Select Read/write bit that allows software disable of
323   * laser. Writing ‘1’ disables laser. See Table 3.11 for
324   * enable/disable timing requirements. This bit is “OR”d with the hard
325   * TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default
326   * enabled unless pulled low by hardware. If Soft TX Disable is not
327   * implemented, the transceiver ignores the value of this bit. Default
328   * power up value is zero/low.
329   */
330  #define SFF_8472_STATUS_SOFT_TX_DISABLE (1 << 6)
331  
332  /*
333   * RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or
334   * RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h
335   * Byte 118, Bit 3 for Soft RS(1) Select control information.
336   */
337  #define SFF_8472_RS_STATE (1 << 5)
338  
339  /*
340   * Rate_Select State [aka. “RS(0)”] Digital state of the SFP
341   * Rate_Select Input Pin. Updated within 100ms of change on pin. Note:
342   * This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431.
343   */
344  #define SFF_8472_STATUS_SELECT_STATE (1 << 4)
345  
346  /*
347   * Read/write bit that allows software rate select control. Writing
348   * ‘1’ selects full bandwidth operation. This bit is “OR’d with the
349   * hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for
350   * timing requirements. Default at power up is logic zero/low. If Soft
351   * Rate Select is not implemented, the transceiver ignores the value
352   * of this bit. Note: Specific transceiver behaviors of this bit are
353   * identified in Table 3.6a and referenced documents. See Table 3.18a,
354   * byte 118, bit 3 for Soft RS(1) Select.
355   */
356  #define SFF_8472_STATUS_SOFT_RATE_SELECT (1 << 3)
357  
358  /*
359   * TX Fault State Digital state of the TX Fault Output Pin. Updated
360   * within 100ms of change on pin.
361   */
362  #define SFF_8472_STATUS_TX_FAULT_STATE (1 << 2)
363  
364  /*
365   * Digital state of the RX_LOS Output Pin. Updated within 100ms of
366   * change on pin.
367   */
368  #define SFF_8472_STATUS_RX_LOS (1 << 1)
369  
370  /*
371   * Indicates transceiver has achieved power up and data is ready. Bit
372   * remains high until data is ready to be read at which time the
373   * device sets the bit low.
374   */
375  #define SFF_8472_STATUS_DATA_READY (1 << 0)
376  
377  /*
378   * Table 3.2 Identifier values.
379   * Identifier constants has taken from SFF-8024 rev 4.6 table 4.1
380   * (as referenced by table 3.2 footer)
381   * */
382  enum {
383  	SFF_8024_ID_UNKNOWN	= 0x0, /* Unknown or unspecified */
384  	SFF_8024_ID_GBIC	= 0x1, /* GBIC */
385  	SFF_8024_ID_SFF		= 0x2, /* Module soldered to motherboard (ex: SFF)*/
386  	SFF_8024_ID_SFP		= 0x3, /* SFP or SFP “Plus” */
387  	SFF_8024_ID_XBI		= 0x4, /* 300 pin XBI */
388  	SFF_8024_ID_XENPAK	= 0x5, /* Xenpak */
389  	SFF_8024_ID_XFP		= 0x6, /* XFP */
390  	SFF_8024_ID_XFF		= 0x7, /* XFF */
391  	SFF_8024_ID_XFPE	= 0x8, /* XFP-E */
392  	SFF_8024_ID_XPAK	= 0x9, /* XPAk */
393  	SFF_8024_ID_X2		= 0xA, /* X2 */
394  	SFF_8024_ID_DWDM_SFP	= 0xB, /* DWDM-SFP */
395  	SFF_8024_ID_QSFP	= 0xC, /* QSFP */
396  	SFF_8024_ID_QSFPPLUS	= 0xD, /* QSFP+ or later */
397  	SFF_8024_ID_CXP		= 0xE, /* CXP */
398  	SFF_8024_ID_HD4X	= 0xF, /* Shielded Mini Multilane HD 4X */
399  	SFF_8024_ID_HD8X	= 0x10, /* Shielded Mini Multilane HD 8X */
400  	SFF_8024_ID_QSFP28	= 0x11, /* QSFP28 or later */
401  	SFF_8024_ID_CXP2	= 0x12, /* CXP2 (aka CXP28) */
402  	SFF_8024_ID_CDFP	= 0x13, /* CDFP (Style 1/Style 2) */
403  	SFF_8024_ID_SMM4	= 0x14, /* Shielded Mini Multilate HD 4X Fanout */
404  	SFF_8024_ID_SMM8	= 0x15, /* Shielded Mini Multilate HD 8X Fanout */
405  	SFF_8024_ID_CDFP3	= 0x16, /* CDFP (Style3) */
406  	SFF_8024_ID_MICROQSFP	= 0x17, /* microQSFP */
407  	SFF_8024_ID_QSFP_DD	= 0x18, /* QSFP-DD 8X Pluggable Transceiver */
408  	SFF_8024_ID_OSFP8X	= 0x19, /* OSFP 8X Pluggable Transceiver */
409  	SFF_8024_ID_SFP_DD	= 0x1A, /* SFP-DD 2X Pluggable Transceiver */
410  	SFF_8024_ID_DSFP	= 0x1B, /* DSFP Dual SFF Pluggable Transceiver */
411  	SFF_8024_ID_X4ML	= 0x1C, /* x4 MiniLink/OcuLink */
412  	SFF_8024_ID_X8ML	= 0x1D, /* x8 MiniLink */
413  	SFF_8024_ID_QSFP_CMIS	= 0x1E, /* QSFP+ or later w/ Common Management
414  					   Interface Specification */
415  	SFF_8024_ID_LAST	= SFF_8024_ID_QSFP_CMIS
416  };
417  
418  static const char *sff_8024_id[SFF_8024_ID_LAST + 1] = {
419  	"Unknown",
420  	"GBIC",
421  	"SFF",
422  	"SFP/SFP+/SFP28",
423  	"XBI",
424  	"Xenpak",
425  	"XFP",
426  	"XFF",
427  	"XFP-E",
428  	"XPAK",
429  	"X2",
430  	"DWDM-SFP/SFP+",
431  	"QSFP",
432  	"QSFP+",
433  	"CXP",
434  	"HD4X",
435  	"HD8X",
436  	"QSFP28",
437  	"CXP2",
438  	"CDFP",
439  	"SMM4",
440  	"SMM8",
441  	"CDFP3",
442  	"microQSFP",
443  	"QSFP-DD",
444  	"QSFP8X",
445  	"SFP-DD",
446  	"DSFP",
447  	"x4MiniLink/OcuLink",
448  	"x8MiniLink",
449  	"QSFP+(CIMS)"
450  };
451  
452  /* Keep compatibility with old definitions */
453  #define	SFF_8472_ID_UNKNOWN	SFF_8024_ID_UNKNOWN
454  #define	SFF_8472_ID_GBIC	SFF_8024_ID_GBIC
455  #define	SFF_8472_ID_SFF		SFF_8024_ID_SFF
456  #define	SFF_8472_ID_SFP		SFF_8024_ID_SFP
457  #define	SFF_8472_ID_XBI		SFF_8024_ID_XBI
458  #define	SFF_8472_ID_XENPAK	SFF_8024_ID_XENPAK
459  #define	SFF_8472_ID_XFP		SFF_8024_ID_XFP
460  #define	SFF_8472_ID_XFF		SFF_8024_ID_XFF
461  #define	SFF_8472_ID_XFPE	SFF_8024_ID_XFPE
462  #define	SFF_8472_ID_XPAK	SFF_8024_ID_XPAK
463  #define	SFF_8472_ID_X2		SFF_8024_ID_X2
464  #define	SFF_8472_ID_DWDM_SFP	SFF_8024_ID_DWDM_SFP
465  #define	SFF_8472_ID_QSFP	SFF_8024_ID_QSFP
466  #define	SFF_8472_ID_LAST	SFF_8024_ID_LAST
467  
468  #define	sff_8472_id		sff_8024_id
469  
470  /*
471   * Table 3.9 Diagnostic Monitoring Type (byte 92)
472   * bits described.
473   */
474  
475  /*
476   * Digital diagnostic monitoring implemented.
477   * Set to 1 for transceivers implementing DDM.
478   */
479  #define	SFF_8472_DDM_DONE	(1 << 6)
480  
481  /*
482   * Measurements are internally calibrated.
483   */
484  #define	SFF_8472_DDM_INTERNAL	(1 << 5)
485  
486  /*
487   * Measurements are externally calibrated.
488   */
489  #define	SFF_8472_DDM_EXTERNAL	(1 << 4)
490  
491  /*
492   * Received power measurement type
493   * 0 = OMA, 1 = average power
494   */
495  #define	SFF_8472_DDM_PMTYPE	(1 << 3)
496  
497  /* Table 3.13 and 3.14 Temperature Conversion Values */
498  #define SFF_8472_TEMP_SIGN (1 << 15)
499  #define SFF_8472_TEMP_SHIFT  8
500  #define SFF_8472_TEMP_MSK  0xEF00
501  #define SFF_8472_TEMP_FRAC 0x00FF
502  
503  /* Internal Callibration Conversion factors */
504  
505  /*
506   * Represented as a 16 bit unsigned integer with the voltage defined
507   * as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt,
508   * yielding a total range of 0 to +6.55 Volts.
509   */
510  #define SFF_8472_VCC_FACTOR 10000.0
511  
512  /*
513   * Represented as a 16 bit unsigned integer with the current defined
514   * as the full 16 bit value (0 – 65535) with LSB equal to 2 uA,
515   * yielding a total range of 0 to 131 mA.
516   */
517  
518  #define SFF_8472_BIAS_FACTOR 2000.0
519  
520  /*
521   * Represented as a 16 bit unsigned integer with the power defined as
522   * the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW,
523   * yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm).
524   */
525  
526  #define SFF_8472_POWER_FACTOR 10000.0
527