1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 struct ether_addr ifc_mac; 213 }; 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_mediap); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 311 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 351 if_txsd_vec_t ift_sds; 352 uint8_t ift_qstatus; 353 uint8_t ift_closed; 354 uint8_t ift_update_freq; 355 struct iflib_filter_info ift_filter_info; 356 bus_dma_tag_t ift_buf_tag; 357 bus_dma_tag_t ift_tso_buf_tag; 358 iflib_dma_info_t ift_ifdi; 359 #define MTX_NAME_LEN 32 360 char ift_mtx_name[MTX_NAME_LEN]; 361 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 362 #ifdef IFLIB_DIAGNOSTICS 363 uint64_t ift_cpu_exec_count[256]; 364 #endif 365 } __aligned(CACHE_LINE_SIZE); 366 367 struct iflib_fl { 368 qidx_t ifl_cidx; 369 qidx_t ifl_pidx; 370 qidx_t ifl_credits; 371 uint8_t ifl_gen; 372 uint8_t ifl_rxd_size; 373 #if MEMORY_LOGGING 374 uint64_t ifl_m_enqueued; 375 uint64_t ifl_m_dequeued; 376 uint64_t ifl_cl_enqueued; 377 uint64_t ifl_cl_dequeued; 378 #endif 379 /* implicit pad */ 380 bitstr_t *ifl_rx_bitmap; 381 qidx_t ifl_fragidx; 382 /* constant */ 383 qidx_t ifl_size; 384 uint16_t ifl_buf_size; 385 uint16_t ifl_cltype; 386 uma_zone_t ifl_zone; 387 iflib_rxsd_array_t ifl_sds; 388 iflib_rxq_t ifl_rxq; 389 uint8_t ifl_id; 390 bus_dma_tag_t ifl_buf_tag; 391 iflib_dma_info_t ifl_ifdi; 392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the completion queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct callout ifr_watchdog; 438 struct iflib_filter_info ifr_filter_info; 439 iflib_dma_info_t ifr_ifdi; 440 441 /* dynamically allocate if any drivers need a value substantially larger than this */ 442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 443 #ifdef IFLIB_DIAGNOSTICS 444 uint64_t ifr_cpu_exec_count[256]; 445 #endif 446 } __aligned(CACHE_LINE_SIZE); 447 448 typedef struct if_rxsd { 449 caddr_t *ifsd_cl; 450 iflib_fl_t ifsd_fl; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_deregister(if_ctx_t); 706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 707 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 708 static void iflib_init_locked(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 710 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 711 static void iflib_ifmp_purge(iflib_txq_t txq); 712 static void _iflib_pre_assert(if_softc_ctx_t scctx); 713 static void iflib_if_init_locked(if_ctx_t ctx); 714 static void iflib_free_intr_mem(if_ctx_t ctx); 715 #ifndef __NO_STRICT_ALIGNMENT 716 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 717 #endif 718 719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 720 SLIST_HEAD_INITIALIZER(cpu_offsets); 721 struct cpu_offset { 722 SLIST_ENTRY(cpu_offset) entries; 723 cpuset_t set; 724 unsigned int refcount; 725 uint16_t offset; 726 }; 727 static struct mtx cpu_offset_mtx; 728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 729 MTX_DEF); 730 731 DEBUGNET_DEFINE(iflib); 732 733 static int 734 iflib_num_rx_descs(if_ctx_t ctx) 735 { 736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 737 if_shared_ctx_t sctx = ctx->ifc_sctx; 738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 739 740 return scctx->isc_nrxd[first_rxq]; 741 } 742 743 static int 744 iflib_num_tx_descs(if_ctx_t ctx) 745 { 746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 747 if_shared_ctx_t sctx = ctx->ifc_sctx; 748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 749 750 return scctx->isc_ntxd[first_txq]; 751 } 752 753 #ifdef DEV_NETMAP 754 #include <sys/selinfo.h> 755 #include <net/netmap.h> 756 #include <dev/netmap/netmap_kern.h> 757 758 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 759 760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 761 762 /* 763 * device-specific sysctl variables: 764 * 765 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 766 * During regular operations the CRC is stripped, but on some 767 * hardware reception of frames not multiple of 64 is slower, 768 * so using crcstrip=0 helps in benchmarks. 769 * 770 * iflib_rx_miss, iflib_rx_miss_bufs: 771 * count packets that might be missed due to lost interrupts. 772 */ 773 SYSCTL_DECL(_dev_netmap); 774 /* 775 * The xl driver by default strips CRCs and we do not override it. 776 */ 777 778 int iflib_crcstrip = 1; 779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 780 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 781 782 int iflib_rx_miss, iflib_rx_miss_bufs; 783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 784 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 786 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 787 788 /* 789 * Register/unregister. We are already under netmap lock. 790 * Only called on the first register or the last unregister. 791 */ 792 static int 793 iflib_netmap_register(struct netmap_adapter *na, int onoff) 794 { 795 if_t ifp = na->ifp; 796 if_ctx_t ctx = ifp->if_softc; 797 int status; 798 799 CTX_LOCK(ctx); 800 IFDI_INTR_DISABLE(ctx); 801 802 /* Tell the stack that the interface is no longer active */ 803 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 804 805 if (!CTX_IS_VF(ctx)) 806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 807 808 iflib_stop(ctx); 809 810 /* 811 * Enable (or disable) netmap flags, and intercept (or restore) 812 * ifp->if_transmit. This is done once the device has been stopped 813 * to prevent race conditions. 814 */ 815 if (onoff) { 816 nm_set_native_flags(na); 817 } else { 818 nm_clear_native_flags(na); 819 } 820 821 iflib_init_locked(ctx); 822 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 823 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 824 if (status) 825 nm_clear_native_flags(na); 826 CTX_UNLOCK(ctx); 827 return (status); 828 } 829 830 static int 831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 832 { 833 struct netmap_adapter *na = kring->na; 834 u_int const lim = kring->nkr_num_slots - 1; 835 u_int nm_i = kring->nr_hwcur; 836 struct netmap_ring *ring = kring->ring; 837 bus_dmamap_t *map; 838 struct if_rxd_update iru; 839 if_ctx_t ctx = rxq->ifr_ctx; 840 iflib_fl_t fl = &rxq->ifr_fl[0]; 841 u_int nic_i_first, nic_i; 842 int i, n; 843 #if IFLIB_DEBUG_COUNTERS 844 int rf_count = 0; 845 #endif 846 847 /* 848 * This function is used both at initialization and in rxsync. 849 * At initialization we need to prepare (with isc_rxd_refill()) 850 * all the (N) netmap buffers in the ring, in such a way to keep 851 * fl->ifl_pidx and kring->nr_hwcur in sync (except for 852 * kring->nkr_hwofs); at rxsync time, both indexes point to the 853 * next buffer to be refilled. 854 * In any case we publish (with isc_rxd_flush()) up to 855 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 856 * pointer to overrun the head/cons pointer, although this is 857 * not necessary for some NICs (e.g. vmx). 858 */ 859 if (__predict_false(init)) 860 n = kring->nkr_num_slots; 861 else { 862 n = kring->rhead - nm_i; 863 if (n == 0) 864 return (0); /* Nothing to do. */ 865 if (n < 0) 866 n += kring->nkr_num_slots; 867 } 868 869 /* Start to refill from nr_hwcur, publishing n buffers. */ 870 iru_init(&iru, rxq, 0 /* flid */); 871 map = fl->ifl_sds.ifsd_map; 872 nic_i = fl->ifl_pidx; 873 MPASS(nic_i == netmap_idx_k2n(kring, nm_i)); 874 DBG_COUNTER_INC(fl_refills); 875 while (n > 0) { 876 #if IFLIB_DEBUG_COUNTERS 877 if (++rf_count == 9) 878 DBG_COUNTER_INC(fl_refills_large); 879 #endif 880 nic_i_first = nic_i; 881 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 882 struct netmap_slot *slot = &ring->slot[nm_i]; 883 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 884 885 MPASS(i < IFLIB_MAX_RX_REFRESH); 886 887 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 888 return netmap_ring_reinit(kring); 889 890 fl->ifl_rxd_idxs[i] = nic_i; 891 892 if (__predict_false(init)) { 893 netmap_load_map(na, fl->ifl_buf_tag, 894 map[nic_i], addr); 895 } else if (slot->flags & NS_BUF_CHANGED) { 896 /* buffer has changed, reload map */ 897 netmap_reload_map(na, fl->ifl_buf_tag, 898 map[nic_i], addr); 899 } 900 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 901 BUS_DMASYNC_PREREAD); 902 slot->flags &= ~NS_BUF_CHANGED; 903 904 nm_i = nm_next(nm_i, lim); 905 nic_i = nm_next(nic_i, lim); 906 } 907 908 iru.iru_pidx = nic_i_first; 909 iru.iru_count = i; 910 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 911 } 912 fl->ifl_pidx = nic_i; 913 MPASS(!init || nm_i == 0); 914 MPASS(nm_i == kring->rhead); 915 kring->nr_hwcur = nm_i; 916 917 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 918 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 919 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 920 nm_prev(nic_i, lim)); 921 DBG_COUNTER_INC(rxd_flush); 922 923 return (0); 924 } 925 926 /* 927 * Reconcile kernel and user view of the transmit ring. 928 * 929 * All information is in the kring. 930 * Userspace wants to send packets up to the one before kring->rhead, 931 * kernel knows kring->nr_hwcur is the first unsent packet. 932 * 933 * Here we push packets out (as many as possible), and possibly 934 * reclaim buffers from previously completed transmission. 935 * 936 * The caller (netmap) guarantees that there is only one instance 937 * running at any time. Any interference with other driver 938 * methods should be handled by the individual drivers. 939 */ 940 static int 941 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 942 { 943 struct netmap_adapter *na = kring->na; 944 if_t ifp = na->ifp; 945 struct netmap_ring *ring = kring->ring; 946 u_int nm_i; /* index into the netmap kring */ 947 u_int nic_i; /* index into the NIC ring */ 948 u_int n; 949 u_int const lim = kring->nkr_num_slots - 1; 950 u_int const head = kring->rhead; 951 struct if_pkt_info pi; 952 953 /* 954 * interrupts on every tx packet are expensive so request 955 * them every half ring, or where NS_REPORT is set 956 */ 957 u_int report_frequency = kring->nkr_num_slots >> 1; 958 /* device-specific */ 959 if_ctx_t ctx = ifp->if_softc; 960 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 961 962 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 963 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 964 965 /* 966 * First part: process new packets to send. 967 * nm_i is the current index in the netmap kring, 968 * nic_i is the corresponding index in the NIC ring. 969 * 970 * If we have packets to send (nm_i != head) 971 * iterate over the netmap ring, fetch length and update 972 * the corresponding slot in the NIC ring. Some drivers also 973 * need to update the buffer's physical address in the NIC slot 974 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 975 * 976 * The netmap_reload_map() calls is especially expensive, 977 * even when (as in this case) the tag is 0, so do only 978 * when the buffer has actually changed. 979 * 980 * If possible do not set the report/intr bit on all slots, 981 * but only a few times per ring or when NS_REPORT is set. 982 * 983 * Finally, on 10G and faster drivers, it might be useful 984 * to prefetch the next slot and txr entry. 985 */ 986 987 nm_i = kring->nr_hwcur; 988 if (nm_i != head) { /* we have new packets to send */ 989 pkt_info_zero(&pi); 990 pi.ipi_segs = txq->ift_segs; 991 pi.ipi_qsidx = kring->ring_id; 992 nic_i = netmap_idx_k2n(kring, nm_i); 993 994 __builtin_prefetch(&ring->slot[nm_i]); 995 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 996 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 997 998 for (n = 0; nm_i != head; n++) { 999 struct netmap_slot *slot = &ring->slot[nm_i]; 1000 u_int len = slot->len; 1001 uint64_t paddr; 1002 void *addr = PNMB(na, slot, &paddr); 1003 int flags = (slot->flags & NS_REPORT || 1004 nic_i == 0 || nic_i == report_frequency) ? 1005 IPI_TX_INTR : 0; 1006 1007 /* device-specific */ 1008 pi.ipi_len = len; 1009 pi.ipi_segs[0].ds_addr = paddr; 1010 pi.ipi_segs[0].ds_len = len; 1011 pi.ipi_nsegs = 1; 1012 pi.ipi_ndescs = 0; 1013 pi.ipi_pidx = nic_i; 1014 pi.ipi_flags = flags; 1015 1016 /* Fill the slot in the NIC ring. */ 1017 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1018 DBG_COUNTER_INC(tx_encap); 1019 1020 /* prefetch for next round */ 1021 __builtin_prefetch(&ring->slot[nm_i + 1]); 1022 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1023 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1024 1025 NM_CHECK_ADDR_LEN(na, addr, len); 1026 1027 if (slot->flags & NS_BUF_CHANGED) { 1028 /* buffer has changed, reload map */ 1029 netmap_reload_map(na, txq->ift_buf_tag, 1030 txq->ift_sds.ifsd_map[nic_i], addr); 1031 } 1032 /* make sure changes to the buffer are synced */ 1033 bus_dmamap_sync(txq->ift_buf_tag, 1034 txq->ift_sds.ifsd_map[nic_i], 1035 BUS_DMASYNC_PREWRITE); 1036 1037 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1038 nm_i = nm_next(nm_i, lim); 1039 nic_i = nm_next(nic_i, lim); 1040 } 1041 kring->nr_hwcur = nm_i; 1042 1043 /* synchronize the NIC ring */ 1044 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1046 1047 /* (re)start the tx unit up to slot nic_i (excluded) */ 1048 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1049 } 1050 1051 /* 1052 * Second part: reclaim buffers for completed transmissions. 1053 * 1054 * If there are unclaimed buffers, attempt to reclaim them. 1055 * If none are reclaimed, and TX IRQs are not in use, do an initial 1056 * minimal delay, then trigger the tx handler which will spin in the 1057 * group task queue. 1058 */ 1059 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1060 if (iflib_tx_credits_update(ctx, txq)) { 1061 /* some tx completed, increment avail */ 1062 nic_i = txq->ift_cidx_processed; 1063 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1064 } 1065 } 1066 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1067 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1068 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1069 iflib_timer, txq, txq->ift_timer.c_cpu); 1070 } 1071 return (0); 1072 } 1073 1074 /* 1075 * Reconcile kernel and user view of the receive ring. 1076 * Same as for the txsync, this routine must be efficient. 1077 * The caller guarantees a single invocations, but races against 1078 * the rest of the driver should be handled here. 1079 * 1080 * On call, kring->rhead is the first packet that userspace wants 1081 * to keep, and kring->rcur is the wakeup point. 1082 * The kernel has previously reported packets up to kring->rtail. 1083 * 1084 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1085 * of whether or not we received an interrupt. 1086 */ 1087 static int 1088 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1089 { 1090 struct netmap_adapter *na = kring->na; 1091 struct netmap_ring *ring = kring->ring; 1092 if_t ifp = na->ifp; 1093 uint32_t nm_i; /* index into the netmap ring */ 1094 uint32_t nic_i; /* index into the NIC ring */ 1095 u_int n; 1096 u_int const lim = kring->nkr_num_slots - 1; 1097 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1098 1099 if_ctx_t ctx = ifp->if_softc; 1100 if_shared_ctx_t sctx = ctx->ifc_sctx; 1101 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1102 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1103 iflib_fl_t fl = &rxq->ifr_fl[0]; 1104 struct if_rxd_info ri; 1105 qidx_t *cidxp; 1106 1107 /* 1108 * netmap only uses free list 0, to avoid out of order consumption 1109 * of receive buffers 1110 */ 1111 1112 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1113 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1114 1115 /* 1116 * First part: import newly received packets. 1117 * 1118 * nm_i is the index of the next free slot in the netmap ring, 1119 * nic_i is the index of the next received packet in the NIC ring 1120 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1121 * differ in case if_init() has been called while 1122 * in netmap mode. For the receive ring we have 1123 * 1124 * nic_i = fl->ifl_cidx; 1125 * nm_i = kring->nr_hwtail (previous) 1126 * and 1127 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1128 * 1129 * fl->ifl_cidx is set to 0 on a ring reinit 1130 */ 1131 if (netmap_no_pendintr || force_update) { 1132 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1133 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1134 int crclen = iflib_crcstrip ? 0 : 4; 1135 int error, avail; 1136 1137 /* 1138 * For the free list consumer index, we use the same 1139 * logic as in iflib_rxeof(). 1140 */ 1141 if (have_rxcq) 1142 cidxp = &rxq->ifr_cq_cidx; 1143 else 1144 cidxp = &fl->ifl_cidx; 1145 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1146 rxq->ifr_id, *cidxp, USHRT_MAX); 1147 1148 nic_i = fl->ifl_cidx; 1149 nm_i = netmap_idx_n2k(kring, nic_i); 1150 MPASS(nm_i == kring->nr_hwtail); 1151 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1152 rxd_info_zero(&ri); 1153 ri.iri_frags = rxq->ifr_frags; 1154 ri.iri_qsidx = kring->ring_id; 1155 ri.iri_ifp = ctx->ifc_ifp; 1156 ri.iri_cidx = *cidxp; 1157 1158 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1159 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1160 ring->slot[nm_i].flags = 0; 1161 if (have_rxcq) { 1162 *cidxp = ri.iri_cidx; 1163 while (*cidxp >= scctx->isc_nrxd[0]) 1164 *cidxp -= scctx->isc_nrxd[0]; 1165 } 1166 bus_dmamap_sync(fl->ifl_buf_tag, 1167 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1168 nm_i = nm_next(nm_i, lim); 1169 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1170 } 1171 if (n) { /* update the state variables */ 1172 if (netmap_no_pendintr && !force_update) { 1173 /* diagnostics */ 1174 iflib_rx_miss ++; 1175 iflib_rx_miss_bufs += n; 1176 } 1177 kring->nr_hwtail = nm_i; 1178 } 1179 kring->nr_kflags &= ~NKR_PENDINTR; 1180 } 1181 /* 1182 * Second part: skip past packets that userspace has released. 1183 * (kring->nr_hwcur to head excluded), 1184 * and make the buffers available for reception. 1185 * As usual nm_i is the index in the netmap ring, 1186 * nic_i is the index in the NIC ring, and 1187 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1188 */ 1189 netmap_fl_refill(rxq, kring, false); 1190 1191 return (0); 1192 } 1193 1194 static void 1195 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1196 { 1197 if_ctx_t ctx = na->ifp->if_softc; 1198 1199 CTX_LOCK(ctx); 1200 if (onoff) { 1201 IFDI_INTR_ENABLE(ctx); 1202 } else { 1203 IFDI_INTR_DISABLE(ctx); 1204 } 1205 CTX_UNLOCK(ctx); 1206 } 1207 1208 1209 static int 1210 iflib_netmap_attach(if_ctx_t ctx) 1211 { 1212 struct netmap_adapter na; 1213 1214 bzero(&na, sizeof(na)); 1215 1216 na.ifp = ctx->ifc_ifp; 1217 na.na_flags = NAF_BDG_MAYSLEEP; 1218 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1219 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1220 1221 na.num_tx_desc = iflib_num_tx_descs(ctx); 1222 na.num_rx_desc = iflib_num_rx_descs(ctx); 1223 na.nm_txsync = iflib_netmap_txsync; 1224 na.nm_rxsync = iflib_netmap_rxsync; 1225 na.nm_register = iflib_netmap_register; 1226 na.nm_intr = iflib_netmap_intr; 1227 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1228 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1229 return (netmap_attach(&na)); 1230 } 1231 1232 static int 1233 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1234 { 1235 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1236 struct netmap_slot *slot; 1237 1238 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1239 if (slot == NULL) 1240 return (0); 1241 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1242 1243 /* 1244 * In netmap mode, set the map for the packet buffer. 1245 * NOTE: Some drivers (not this one) also need to set 1246 * the physical buffer address in the NIC ring. 1247 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1248 * netmap slot index, si 1249 */ 1250 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1251 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1252 NMB(na, slot + si)); 1253 } 1254 return (1); 1255 } 1256 1257 static int 1258 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1259 { 1260 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1261 struct netmap_kring *kring; 1262 struct netmap_slot *slot; 1263 1264 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1265 if (slot == NULL) 1266 return (0); 1267 kring = na->rx_rings[rxq->ifr_id]; 1268 netmap_fl_refill(rxq, kring, true); 1269 return (1); 1270 } 1271 1272 static void 1273 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1274 { 1275 struct netmap_kring *kring; 1276 uint16_t txqid; 1277 1278 txqid = txq->ift_id; 1279 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX); 1280 if (kring == NULL) 1281 return; 1282 1283 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1284 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1285 BUS_DMASYNC_POSTREAD); 1286 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1287 netmap_tx_irq(ctx->ifc_ifp, txqid); 1288 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1289 if (hz < 2000) 1290 *reset_on = 1; 1291 else 1292 *reset_on = hz / 1000; 1293 } 1294 } 1295 } 1296 1297 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1298 1299 #else 1300 #define iflib_netmap_txq_init(ctx, txq) (0) 1301 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1302 #define iflib_netmap_detach(ifp) 1303 1304 #define iflib_netmap_attach(ctx) (0) 1305 #define netmap_rx_irq(ifp, qid, budget) (0) 1306 #define netmap_tx_irq(ifp, qid) do {} while (0) 1307 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1308 #endif 1309 1310 #if defined(__i386__) || defined(__amd64__) 1311 static __inline void 1312 prefetch(void *x) 1313 { 1314 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1315 } 1316 static __inline void 1317 prefetch2cachelines(void *x) 1318 { 1319 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1320 #if (CACHE_LINE_SIZE < 128) 1321 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1322 #endif 1323 } 1324 #else 1325 #define prefetch(x) 1326 #define prefetch2cachelines(x) 1327 #endif 1328 1329 static void 1330 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1331 { 1332 iflib_fl_t fl; 1333 1334 fl = &rxq->ifr_fl[flid]; 1335 iru->iru_paddrs = fl->ifl_bus_addrs; 1336 iru->iru_idxs = fl->ifl_rxd_idxs; 1337 iru->iru_qsidx = rxq->ifr_id; 1338 iru->iru_buf_size = fl->ifl_buf_size; 1339 iru->iru_flidx = fl->ifl_id; 1340 } 1341 1342 static void 1343 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1344 { 1345 if (err) 1346 return; 1347 *(bus_addr_t *) arg = segs[0].ds_addr; 1348 } 1349 1350 int 1351 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1352 { 1353 int err; 1354 device_t dev = ctx->ifc_dev; 1355 1356 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1357 align, 0, /* alignment, bounds */ 1358 BUS_SPACE_MAXADDR, /* lowaddr */ 1359 BUS_SPACE_MAXADDR, /* highaddr */ 1360 NULL, NULL, /* filter, filterarg */ 1361 size, /* maxsize */ 1362 1, /* nsegments */ 1363 size, /* maxsegsize */ 1364 BUS_DMA_ALLOCNOW, /* flags */ 1365 NULL, /* lockfunc */ 1366 NULL, /* lockarg */ 1367 &dma->idi_tag); 1368 if (err) { 1369 device_printf(dev, 1370 "%s: bus_dma_tag_create failed: %d\n", 1371 __func__, err); 1372 goto fail_0; 1373 } 1374 1375 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1376 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1377 if (err) { 1378 device_printf(dev, 1379 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1380 __func__, (uintmax_t)size, err); 1381 goto fail_1; 1382 } 1383 1384 dma->idi_paddr = IF_BAD_DMA; 1385 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1386 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1387 if (err || dma->idi_paddr == IF_BAD_DMA) { 1388 device_printf(dev, 1389 "%s: bus_dmamap_load failed: %d\n", 1390 __func__, err); 1391 goto fail_2; 1392 } 1393 1394 dma->idi_size = size; 1395 return (0); 1396 1397 fail_2: 1398 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1399 fail_1: 1400 bus_dma_tag_destroy(dma->idi_tag); 1401 fail_0: 1402 dma->idi_tag = NULL; 1403 1404 return (err); 1405 } 1406 1407 int 1408 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1409 { 1410 if_shared_ctx_t sctx = ctx->ifc_sctx; 1411 1412 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1413 1414 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1415 } 1416 1417 int 1418 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1419 { 1420 int i, err; 1421 iflib_dma_info_t *dmaiter; 1422 1423 dmaiter = dmalist; 1424 for (i = 0; i < count; i++, dmaiter++) { 1425 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1426 break; 1427 } 1428 if (err) 1429 iflib_dma_free_multi(dmalist, i); 1430 return (err); 1431 } 1432 1433 void 1434 iflib_dma_free(iflib_dma_info_t dma) 1435 { 1436 if (dma->idi_tag == NULL) 1437 return; 1438 if (dma->idi_paddr != IF_BAD_DMA) { 1439 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1440 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1441 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1442 dma->idi_paddr = IF_BAD_DMA; 1443 } 1444 if (dma->idi_vaddr != NULL) { 1445 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1446 dma->idi_vaddr = NULL; 1447 } 1448 bus_dma_tag_destroy(dma->idi_tag); 1449 dma->idi_tag = NULL; 1450 } 1451 1452 void 1453 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1454 { 1455 int i; 1456 iflib_dma_info_t *dmaiter = dmalist; 1457 1458 for (i = 0; i < count; i++, dmaiter++) 1459 iflib_dma_free(*dmaiter); 1460 } 1461 1462 static int 1463 iflib_fast_intr(void *arg) 1464 { 1465 iflib_filter_info_t info = arg; 1466 struct grouptask *gtask = info->ifi_task; 1467 int result; 1468 1469 DBG_COUNTER_INC(fast_intrs); 1470 if (info->ifi_filter != NULL) { 1471 result = info->ifi_filter(info->ifi_filter_arg); 1472 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1473 return (result); 1474 } 1475 1476 GROUPTASK_ENQUEUE(gtask); 1477 return (FILTER_HANDLED); 1478 } 1479 1480 static int 1481 iflib_fast_intr_rxtx(void *arg) 1482 { 1483 iflib_filter_info_t info = arg; 1484 struct grouptask *gtask = info->ifi_task; 1485 if_ctx_t ctx; 1486 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1487 iflib_txq_t txq; 1488 void *sc; 1489 int i, cidx, result; 1490 qidx_t txqid; 1491 bool intr_enable, intr_legacy; 1492 1493 DBG_COUNTER_INC(fast_intrs); 1494 if (info->ifi_filter != NULL) { 1495 result = info->ifi_filter(info->ifi_filter_arg); 1496 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1497 return (result); 1498 } 1499 1500 ctx = rxq->ifr_ctx; 1501 sc = ctx->ifc_softc; 1502 intr_enable = false; 1503 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1504 MPASS(rxq->ifr_ntxqirq); 1505 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1506 txqid = rxq->ifr_txqid[i]; 1507 txq = &ctx->ifc_txqs[txqid]; 1508 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1509 BUS_DMASYNC_POSTREAD); 1510 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1511 if (intr_legacy) 1512 intr_enable = true; 1513 else 1514 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1515 continue; 1516 } 1517 GROUPTASK_ENQUEUE(&txq->ift_task); 1518 } 1519 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1520 cidx = rxq->ifr_cq_cidx; 1521 else 1522 cidx = rxq->ifr_fl[0].ifl_cidx; 1523 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1524 GROUPTASK_ENQUEUE(gtask); 1525 else { 1526 if (intr_legacy) 1527 intr_enable = true; 1528 else 1529 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1530 DBG_COUNTER_INC(rx_intr_enables); 1531 } 1532 if (intr_enable) 1533 IFDI_INTR_ENABLE(ctx); 1534 return (FILTER_HANDLED); 1535 } 1536 1537 1538 static int 1539 iflib_fast_intr_ctx(void *arg) 1540 { 1541 iflib_filter_info_t info = arg; 1542 struct grouptask *gtask = info->ifi_task; 1543 int result; 1544 1545 DBG_COUNTER_INC(fast_intrs); 1546 if (info->ifi_filter != NULL) { 1547 result = info->ifi_filter(info->ifi_filter_arg); 1548 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1549 return (result); 1550 } 1551 1552 GROUPTASK_ENQUEUE(gtask); 1553 return (FILTER_HANDLED); 1554 } 1555 1556 static int 1557 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1558 driver_filter_t filter, driver_intr_t handler, void *arg, 1559 const char *name) 1560 { 1561 struct resource *res; 1562 void *tag = NULL; 1563 device_t dev = ctx->ifc_dev; 1564 int flags, i, rc; 1565 1566 flags = RF_ACTIVE; 1567 if (ctx->ifc_flags & IFC_LEGACY) 1568 flags |= RF_SHAREABLE; 1569 MPASS(rid < 512); 1570 i = rid; 1571 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1572 if (res == NULL) { 1573 device_printf(dev, 1574 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1575 return (ENOMEM); 1576 } 1577 irq->ii_res = res; 1578 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1579 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1580 filter, handler, arg, &tag); 1581 if (rc != 0) { 1582 device_printf(dev, 1583 "failed to setup interrupt for rid %d, name %s: %d\n", 1584 rid, name ? name : "unknown", rc); 1585 return (rc); 1586 } else if (name) 1587 bus_describe_intr(dev, res, tag, "%s", name); 1588 1589 irq->ii_tag = tag; 1590 return (0); 1591 } 1592 1593 /********************************************************************* 1594 * 1595 * Allocate DMA resources for TX buffers as well as memory for the TX 1596 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1597 * iflib_sw_tx_desc_array structure, storing all the information that 1598 * is needed to transmit a packet on the wire. This is called only 1599 * once at attach, setup is done every reset. 1600 * 1601 **********************************************************************/ 1602 static int 1603 iflib_txsd_alloc(iflib_txq_t txq) 1604 { 1605 if_ctx_t ctx = txq->ift_ctx; 1606 if_shared_ctx_t sctx = ctx->ifc_sctx; 1607 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1608 device_t dev = ctx->ifc_dev; 1609 bus_size_t tsomaxsize; 1610 int err, nsegments, ntsosegments; 1611 bool tso; 1612 1613 nsegments = scctx->isc_tx_nsegments; 1614 ntsosegments = scctx->isc_tx_tso_segments_max; 1615 tsomaxsize = scctx->isc_tx_tso_size_max; 1616 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1617 tsomaxsize += sizeof(struct ether_vlan_header); 1618 MPASS(scctx->isc_ntxd[0] > 0); 1619 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1620 MPASS(nsegments > 0); 1621 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1622 MPASS(ntsosegments > 0); 1623 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1624 } 1625 1626 /* 1627 * Set up DMA tags for TX buffers. 1628 */ 1629 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1630 1, 0, /* alignment, bounds */ 1631 BUS_SPACE_MAXADDR, /* lowaddr */ 1632 BUS_SPACE_MAXADDR, /* highaddr */ 1633 NULL, NULL, /* filter, filterarg */ 1634 sctx->isc_tx_maxsize, /* maxsize */ 1635 nsegments, /* nsegments */ 1636 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1637 0, /* flags */ 1638 NULL, /* lockfunc */ 1639 NULL, /* lockfuncarg */ 1640 &txq->ift_buf_tag))) { 1641 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1642 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1643 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1644 goto fail; 1645 } 1646 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1647 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1648 1, 0, /* alignment, bounds */ 1649 BUS_SPACE_MAXADDR, /* lowaddr */ 1650 BUS_SPACE_MAXADDR, /* highaddr */ 1651 NULL, NULL, /* filter, filterarg */ 1652 tsomaxsize, /* maxsize */ 1653 ntsosegments, /* nsegments */ 1654 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1655 0, /* flags */ 1656 NULL, /* lockfunc */ 1657 NULL, /* lockfuncarg */ 1658 &txq->ift_tso_buf_tag))) { 1659 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1660 err); 1661 goto fail; 1662 } 1663 1664 /* Allocate memory for the TX mbuf map. */ 1665 if (!(txq->ift_sds.ifsd_m = 1666 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1667 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1668 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1669 err = ENOMEM; 1670 goto fail; 1671 } 1672 1673 /* 1674 * Create the DMA maps for TX buffers. 1675 */ 1676 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1677 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1678 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1679 device_printf(dev, 1680 "Unable to allocate TX buffer DMA map memory\n"); 1681 err = ENOMEM; 1682 goto fail; 1683 } 1684 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1685 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1686 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1687 device_printf(dev, 1688 "Unable to allocate TSO TX buffer map memory\n"); 1689 err = ENOMEM; 1690 goto fail; 1691 } 1692 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1693 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1694 &txq->ift_sds.ifsd_map[i]); 1695 if (err != 0) { 1696 device_printf(dev, "Unable to create TX DMA map\n"); 1697 goto fail; 1698 } 1699 if (!tso) 1700 continue; 1701 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1702 &txq->ift_sds.ifsd_tso_map[i]); 1703 if (err != 0) { 1704 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1705 goto fail; 1706 } 1707 } 1708 return (0); 1709 fail: 1710 /* We free all, it handles case where we are in the middle */ 1711 iflib_tx_structures_free(ctx); 1712 return (err); 1713 } 1714 1715 static void 1716 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1717 { 1718 bus_dmamap_t map; 1719 1720 if (txq->ift_sds.ifsd_map != NULL) { 1721 map = txq->ift_sds.ifsd_map[i]; 1722 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1723 bus_dmamap_unload(txq->ift_buf_tag, map); 1724 bus_dmamap_destroy(txq->ift_buf_tag, map); 1725 txq->ift_sds.ifsd_map[i] = NULL; 1726 } 1727 1728 if (txq->ift_sds.ifsd_tso_map != NULL) { 1729 map = txq->ift_sds.ifsd_tso_map[i]; 1730 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1731 BUS_DMASYNC_POSTWRITE); 1732 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1733 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1734 txq->ift_sds.ifsd_tso_map[i] = NULL; 1735 } 1736 } 1737 1738 static void 1739 iflib_txq_destroy(iflib_txq_t txq) 1740 { 1741 if_ctx_t ctx = txq->ift_ctx; 1742 1743 for (int i = 0; i < txq->ift_size; i++) 1744 iflib_txsd_destroy(ctx, txq, i); 1745 1746 if (txq->ift_br != NULL) { 1747 ifmp_ring_free(txq->ift_br); 1748 txq->ift_br = NULL; 1749 } 1750 1751 mtx_destroy(&txq->ift_mtx); 1752 1753 if (txq->ift_sds.ifsd_map != NULL) { 1754 free(txq->ift_sds.ifsd_map, M_IFLIB); 1755 txq->ift_sds.ifsd_map = NULL; 1756 } 1757 if (txq->ift_sds.ifsd_tso_map != NULL) { 1758 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1759 txq->ift_sds.ifsd_tso_map = NULL; 1760 } 1761 if (txq->ift_sds.ifsd_m != NULL) { 1762 free(txq->ift_sds.ifsd_m, M_IFLIB); 1763 txq->ift_sds.ifsd_m = NULL; 1764 } 1765 if (txq->ift_buf_tag != NULL) { 1766 bus_dma_tag_destroy(txq->ift_buf_tag); 1767 txq->ift_buf_tag = NULL; 1768 } 1769 if (txq->ift_tso_buf_tag != NULL) { 1770 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1771 txq->ift_tso_buf_tag = NULL; 1772 } 1773 if (txq->ift_ifdi != NULL) { 1774 free(txq->ift_ifdi, M_IFLIB); 1775 } 1776 } 1777 1778 static void 1779 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1780 { 1781 struct mbuf **mp; 1782 1783 mp = &txq->ift_sds.ifsd_m[i]; 1784 if (*mp == NULL) 1785 return; 1786 1787 if (txq->ift_sds.ifsd_map != NULL) { 1788 bus_dmamap_sync(txq->ift_buf_tag, 1789 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1790 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1791 } 1792 if (txq->ift_sds.ifsd_tso_map != NULL) { 1793 bus_dmamap_sync(txq->ift_tso_buf_tag, 1794 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1795 bus_dmamap_unload(txq->ift_tso_buf_tag, 1796 txq->ift_sds.ifsd_tso_map[i]); 1797 } 1798 m_free(*mp); 1799 DBG_COUNTER_INC(tx_frees); 1800 *mp = NULL; 1801 } 1802 1803 static int 1804 iflib_txq_setup(iflib_txq_t txq) 1805 { 1806 if_ctx_t ctx = txq->ift_ctx; 1807 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1808 if_shared_ctx_t sctx = ctx->ifc_sctx; 1809 iflib_dma_info_t di; 1810 int i; 1811 1812 /* Set number of descriptors available */ 1813 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1814 /* XXX make configurable */ 1815 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1816 1817 /* Reset indices */ 1818 txq->ift_cidx_processed = 0; 1819 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1820 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1821 1822 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1823 bzero((void *)di->idi_vaddr, di->idi_size); 1824 1825 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1826 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1827 bus_dmamap_sync(di->idi_tag, di->idi_map, 1828 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1829 return (0); 1830 } 1831 1832 /********************************************************************* 1833 * 1834 * Allocate DMA resources for RX buffers as well as memory for the RX 1835 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1836 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1837 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1838 * Since we use use one entry in iflib_sw_rx_desc_array per received 1839 * packet, the maximum number of entries we'll need is equal to the 1840 * number of hardware receive descriptors that we've allocated. 1841 * 1842 **********************************************************************/ 1843 static int 1844 iflib_rxsd_alloc(iflib_rxq_t rxq) 1845 { 1846 if_ctx_t ctx = rxq->ifr_ctx; 1847 if_shared_ctx_t sctx = ctx->ifc_sctx; 1848 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1849 device_t dev = ctx->ifc_dev; 1850 iflib_fl_t fl; 1851 int err; 1852 1853 MPASS(scctx->isc_nrxd[0] > 0); 1854 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1855 1856 fl = rxq->ifr_fl; 1857 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1858 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1859 /* Set up DMA tag for RX buffers. */ 1860 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1861 1, 0, /* alignment, bounds */ 1862 BUS_SPACE_MAXADDR, /* lowaddr */ 1863 BUS_SPACE_MAXADDR, /* highaddr */ 1864 NULL, NULL, /* filter, filterarg */ 1865 sctx->isc_rx_maxsize, /* maxsize */ 1866 sctx->isc_rx_nsegments, /* nsegments */ 1867 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1868 0, /* flags */ 1869 NULL, /* lockfunc */ 1870 NULL, /* lockarg */ 1871 &fl->ifl_buf_tag); 1872 if (err) { 1873 device_printf(dev, 1874 "Unable to allocate RX DMA tag: %d\n", err); 1875 goto fail; 1876 } 1877 1878 /* Allocate memory for the RX mbuf map. */ 1879 if (!(fl->ifl_sds.ifsd_m = 1880 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1881 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1882 device_printf(dev, 1883 "Unable to allocate RX mbuf map memory\n"); 1884 err = ENOMEM; 1885 goto fail; 1886 } 1887 1888 /* Allocate memory for the direct RX cluster pointer map. */ 1889 if (!(fl->ifl_sds.ifsd_cl = 1890 (caddr_t *) malloc(sizeof(caddr_t) * 1891 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1892 device_printf(dev, 1893 "Unable to allocate RX cluster map memory\n"); 1894 err = ENOMEM; 1895 goto fail; 1896 } 1897 1898 /* Allocate memory for the RX cluster bus address map. */ 1899 if (!(fl->ifl_sds.ifsd_ba = 1900 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1901 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1902 device_printf(dev, 1903 "Unable to allocate RX bus address map memory\n"); 1904 err = ENOMEM; 1905 goto fail; 1906 } 1907 1908 /* 1909 * Create the DMA maps for RX buffers. 1910 */ 1911 if (!(fl->ifl_sds.ifsd_map = 1912 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1913 device_printf(dev, 1914 "Unable to allocate RX buffer DMA map memory\n"); 1915 err = ENOMEM; 1916 goto fail; 1917 } 1918 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1919 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1920 &fl->ifl_sds.ifsd_map[i]); 1921 if (err != 0) { 1922 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1923 goto fail; 1924 } 1925 } 1926 } 1927 return (0); 1928 1929 fail: 1930 iflib_rx_structures_free(ctx); 1931 return (err); 1932 } 1933 1934 1935 /* 1936 * Internal service routines 1937 */ 1938 1939 struct rxq_refill_cb_arg { 1940 int error; 1941 bus_dma_segment_t seg; 1942 int nseg; 1943 }; 1944 1945 static void 1946 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1947 { 1948 struct rxq_refill_cb_arg *cb_arg = arg; 1949 1950 cb_arg->error = error; 1951 cb_arg->seg = segs[0]; 1952 cb_arg->nseg = nseg; 1953 } 1954 1955 /** 1956 * iflib_fl_refill - refill an rxq free-buffer list 1957 * @ctx: the iflib context 1958 * @fl: the free list to refill 1959 * @count: the number of new buffers to allocate 1960 * 1961 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1962 * The caller must assure that @count does not exceed the queue's capacity. 1963 */ 1964 static uint8_t 1965 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1966 { 1967 struct if_rxd_update iru; 1968 struct rxq_refill_cb_arg cb_arg; 1969 struct mbuf *m; 1970 caddr_t cl, *sd_cl; 1971 struct mbuf **sd_m; 1972 bus_dmamap_t *sd_map; 1973 bus_addr_t bus_addr, *sd_ba; 1974 int err, frag_idx, i, idx, n, pidx; 1975 qidx_t credits; 1976 1977 sd_m = fl->ifl_sds.ifsd_m; 1978 sd_map = fl->ifl_sds.ifsd_map; 1979 sd_cl = fl->ifl_sds.ifsd_cl; 1980 sd_ba = fl->ifl_sds.ifsd_ba; 1981 pidx = fl->ifl_pidx; 1982 idx = pidx; 1983 frag_idx = fl->ifl_fragidx; 1984 credits = fl->ifl_credits; 1985 1986 i = 0; 1987 n = count; 1988 MPASS(n > 0); 1989 MPASS(credits + n <= fl->ifl_size); 1990 1991 if (pidx < fl->ifl_cidx) 1992 MPASS(pidx + n <= fl->ifl_cidx); 1993 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1994 MPASS(fl->ifl_gen == 0); 1995 if (pidx > fl->ifl_cidx) 1996 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1997 1998 DBG_COUNTER_INC(fl_refills); 1999 if (n > 8) 2000 DBG_COUNTER_INC(fl_refills_large); 2001 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2002 while (n-- > 0) { 2003 /* 2004 * We allocate an uninitialized mbuf + cluster, mbuf is 2005 * initialized after rx. 2006 * 2007 * If the cluster is still set then we know a minimum sized 2008 * packet was received 2009 */ 2010 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2011 &frag_idx); 2012 if (frag_idx < 0) 2013 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2014 MPASS(frag_idx >= 0); 2015 if ((cl = sd_cl[frag_idx]) == NULL) { 2016 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2017 if (__predict_false(cl == NULL)) 2018 break; 2019 2020 cb_arg.error = 0; 2021 MPASS(sd_map != NULL); 2022 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2023 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2024 BUS_DMA_NOWAIT); 2025 if (__predict_false(err != 0 || cb_arg.error)) { 2026 uma_zfree(fl->ifl_zone, cl); 2027 break; 2028 } 2029 2030 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2031 sd_cl[frag_idx] = cl; 2032 #if MEMORY_LOGGING 2033 fl->ifl_cl_enqueued++; 2034 #endif 2035 } else { 2036 bus_addr = sd_ba[frag_idx]; 2037 } 2038 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2039 BUS_DMASYNC_PREREAD); 2040 2041 if (sd_m[frag_idx] == NULL) { 2042 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2043 if (__predict_false(m == NULL)) 2044 break; 2045 sd_m[frag_idx] = m; 2046 } 2047 bit_set(fl->ifl_rx_bitmap, frag_idx); 2048 #if MEMORY_LOGGING 2049 fl->ifl_m_enqueued++; 2050 #endif 2051 2052 DBG_COUNTER_INC(rx_allocs); 2053 fl->ifl_rxd_idxs[i] = frag_idx; 2054 fl->ifl_bus_addrs[i] = bus_addr; 2055 credits++; 2056 i++; 2057 MPASS(credits <= fl->ifl_size); 2058 if (++idx == fl->ifl_size) { 2059 #ifdef INVARIANTS 2060 fl->ifl_gen = 1; 2061 #endif 2062 idx = 0; 2063 } 2064 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2065 iru.iru_pidx = pidx; 2066 iru.iru_count = i; 2067 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2068 fl->ifl_pidx = idx; 2069 fl->ifl_credits = credits; 2070 pidx = idx; 2071 i = 0; 2072 } 2073 } 2074 2075 if (n < count - 1) { 2076 if (i != 0) { 2077 iru.iru_pidx = pidx; 2078 iru.iru_count = i; 2079 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2080 fl->ifl_pidx = idx; 2081 fl->ifl_credits = credits; 2082 } 2083 DBG_COUNTER_INC(rxd_flush); 2084 if (fl->ifl_pidx == 0) 2085 pidx = fl->ifl_size - 1; 2086 else 2087 pidx = fl->ifl_pidx - 1; 2088 2089 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2090 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2091 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2092 fl->ifl_id, pidx); 2093 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2094 fl->ifl_fragidx = frag_idx + 1; 2095 if (fl->ifl_fragidx == fl->ifl_size) 2096 fl->ifl_fragidx = 0; 2097 } else { 2098 fl->ifl_fragidx = frag_idx; 2099 } 2100 } 2101 2102 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2103 } 2104 2105 static inline uint8_t 2106 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2107 { 2108 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2109 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2110 #ifdef INVARIANTS 2111 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2112 #endif 2113 2114 MPASS(fl->ifl_credits <= fl->ifl_size); 2115 MPASS(reclaimable == delta); 2116 2117 if (reclaimable > 0) 2118 return (iflib_fl_refill(ctx, fl, reclaimable)); 2119 return (0); 2120 } 2121 2122 uint8_t 2123 iflib_in_detach(if_ctx_t ctx) 2124 { 2125 bool in_detach; 2126 2127 STATE_LOCK(ctx); 2128 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2129 STATE_UNLOCK(ctx); 2130 return (in_detach); 2131 } 2132 2133 static void 2134 iflib_fl_bufs_free(iflib_fl_t fl) 2135 { 2136 iflib_dma_info_t idi = fl->ifl_ifdi; 2137 bus_dmamap_t sd_map; 2138 uint32_t i; 2139 2140 for (i = 0; i < fl->ifl_size; i++) { 2141 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2142 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2143 2144 if (*sd_cl != NULL) { 2145 sd_map = fl->ifl_sds.ifsd_map[i]; 2146 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2147 BUS_DMASYNC_POSTREAD); 2148 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2149 uma_zfree(fl->ifl_zone, *sd_cl); 2150 *sd_cl = NULL; 2151 if (*sd_m != NULL) { 2152 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2153 uma_zfree(zone_mbuf, *sd_m); 2154 *sd_m = NULL; 2155 } 2156 } else { 2157 MPASS(*sd_m == NULL); 2158 } 2159 #if MEMORY_LOGGING 2160 fl->ifl_m_dequeued++; 2161 fl->ifl_cl_dequeued++; 2162 #endif 2163 } 2164 #ifdef INVARIANTS 2165 for (i = 0; i < fl->ifl_size; i++) { 2166 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2167 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2168 } 2169 #endif 2170 /* 2171 * Reset free list values 2172 */ 2173 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2174 bzero(idi->idi_vaddr, idi->idi_size); 2175 } 2176 2177 /********************************************************************* 2178 * 2179 * Initialize a free list and its buffers. 2180 * 2181 **********************************************************************/ 2182 static int 2183 iflib_fl_setup(iflib_fl_t fl) 2184 { 2185 iflib_rxq_t rxq = fl->ifl_rxq; 2186 if_ctx_t ctx = rxq->ifr_ctx; 2187 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2188 int qidx; 2189 2190 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2191 /* 2192 ** Free current RX buffer structs and their mbufs 2193 */ 2194 iflib_fl_bufs_free(fl); 2195 /* Now replenish the mbufs */ 2196 MPASS(fl->ifl_credits == 0); 2197 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2198 if (scctx->isc_rxd_buf_size[qidx] != 0) 2199 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2200 else 2201 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2202 /* 2203 * ifl_buf_size may be a driver-supplied value, so pull it up 2204 * to the selected mbuf size. 2205 */ 2206 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2207 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2208 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2209 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2210 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2211 2212 2213 /* avoid pre-allocating zillions of clusters to an idle card 2214 * potentially speeding up attach 2215 */ 2216 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2217 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2218 if (min(128, fl->ifl_size) != fl->ifl_credits) 2219 return (ENOBUFS); 2220 /* 2221 * handle failure 2222 */ 2223 MPASS(rxq != NULL); 2224 MPASS(fl->ifl_ifdi != NULL); 2225 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2227 return (0); 2228 } 2229 2230 /********************************************************************* 2231 * 2232 * Free receive ring data structures 2233 * 2234 **********************************************************************/ 2235 static void 2236 iflib_rx_sds_free(iflib_rxq_t rxq) 2237 { 2238 iflib_fl_t fl; 2239 int i, j; 2240 2241 if (rxq->ifr_fl != NULL) { 2242 for (i = 0; i < rxq->ifr_nfl; i++) { 2243 fl = &rxq->ifr_fl[i]; 2244 if (fl->ifl_buf_tag != NULL) { 2245 if (fl->ifl_sds.ifsd_map != NULL) { 2246 for (j = 0; j < fl->ifl_size; j++) { 2247 bus_dmamap_sync( 2248 fl->ifl_buf_tag, 2249 fl->ifl_sds.ifsd_map[j], 2250 BUS_DMASYNC_POSTREAD); 2251 bus_dmamap_unload( 2252 fl->ifl_buf_tag, 2253 fl->ifl_sds.ifsd_map[j]); 2254 bus_dmamap_destroy( 2255 fl->ifl_buf_tag, 2256 fl->ifl_sds.ifsd_map[j]); 2257 } 2258 } 2259 bus_dma_tag_destroy(fl->ifl_buf_tag); 2260 fl->ifl_buf_tag = NULL; 2261 } 2262 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2263 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2264 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2265 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2266 fl->ifl_sds.ifsd_m = NULL; 2267 fl->ifl_sds.ifsd_cl = NULL; 2268 fl->ifl_sds.ifsd_ba = NULL; 2269 fl->ifl_sds.ifsd_map = NULL; 2270 } 2271 free(rxq->ifr_fl, M_IFLIB); 2272 rxq->ifr_fl = NULL; 2273 free(rxq->ifr_ifdi, M_IFLIB); 2274 rxq->ifr_ifdi = NULL; 2275 rxq->ifr_cq_cidx = 0; 2276 } 2277 } 2278 2279 /* 2280 * Timer routine 2281 */ 2282 static void 2283 iflib_timer(void *arg) 2284 { 2285 iflib_txq_t txq = arg; 2286 if_ctx_t ctx = txq->ift_ctx; 2287 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2288 uint64_t this_tick = ticks; 2289 uint32_t reset_on = hz / 2; 2290 2291 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2292 return; 2293 2294 /* 2295 ** Check on the state of the TX queue(s), this 2296 ** can be done without the lock because its RO 2297 ** and the HUNG state will be static if set. 2298 */ 2299 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2300 txq->ift_last_timer_tick = this_tick; 2301 IFDI_TIMER(ctx, txq->ift_id); 2302 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2303 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2304 (sctx->isc_pause_frames == 0))) 2305 goto hung; 2306 2307 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2308 ifmp_ring_is_stalled(txq->ift_br)) { 2309 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2310 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2311 } 2312 txq->ift_cleaned_prev = txq->ift_cleaned; 2313 } 2314 #ifdef DEV_NETMAP 2315 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2316 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2317 #endif 2318 /* handle any laggards */ 2319 if (txq->ift_db_pending) 2320 GROUPTASK_ENQUEUE(&txq->ift_task); 2321 2322 sctx->isc_pause_frames = 0; 2323 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2324 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2325 return; 2326 2327 hung: 2328 device_printf(ctx->ifc_dev, 2329 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2330 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2331 STATE_LOCK(ctx); 2332 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2333 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2334 iflib_admin_intr_deferred(ctx); 2335 STATE_UNLOCK(ctx); 2336 } 2337 2338 static uint16_t 2339 iflib_get_mbuf_size_for(unsigned int size) 2340 { 2341 2342 if (size <= MCLBYTES) 2343 return (MCLBYTES); 2344 else 2345 return (MJUMPAGESIZE); 2346 } 2347 2348 static void 2349 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2350 { 2351 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2352 2353 /* 2354 * XXX don't set the max_frame_size to larger 2355 * than the hardware can handle 2356 */ 2357 ctx->ifc_rx_mbuf_sz = 2358 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2359 } 2360 2361 uint32_t 2362 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2363 { 2364 2365 return (ctx->ifc_rx_mbuf_sz); 2366 } 2367 2368 static void 2369 iflib_init_locked(if_ctx_t ctx) 2370 { 2371 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2372 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2373 if_t ifp = ctx->ifc_ifp; 2374 iflib_fl_t fl; 2375 iflib_txq_t txq; 2376 iflib_rxq_t rxq; 2377 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2378 2379 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2380 IFDI_INTR_DISABLE(ctx); 2381 2382 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2383 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2384 /* Set hardware offload abilities */ 2385 if_clearhwassist(ifp); 2386 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2387 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2388 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2389 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2390 if (if_getcapenable(ifp) & IFCAP_TSO4) 2391 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2392 if (if_getcapenable(ifp) & IFCAP_TSO6) 2393 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2394 2395 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2396 CALLOUT_LOCK(txq); 2397 callout_stop(&txq->ift_timer); 2398 CALLOUT_UNLOCK(txq); 2399 iflib_netmap_txq_init(ctx, txq); 2400 } 2401 2402 /* 2403 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2404 * that drivers can use the value when setting up the hardware receive 2405 * buffers. 2406 */ 2407 iflib_calc_rx_mbuf_sz(ctx); 2408 2409 #ifdef INVARIANTS 2410 i = if_getdrvflags(ifp); 2411 #endif 2412 IFDI_INIT(ctx); 2413 MPASS(if_getdrvflags(ifp) == i); 2414 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2415 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2416 /* This rxq is in netmap mode. Skip normal init. */ 2417 continue; 2418 } 2419 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2420 if (iflib_fl_setup(fl)) { 2421 device_printf(ctx->ifc_dev, 2422 "setting up free list %d failed - " 2423 "check cluster settings\n", j); 2424 goto done; 2425 } 2426 } 2427 } 2428 done: 2429 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2430 IFDI_INTR_ENABLE(ctx); 2431 txq = ctx->ifc_txqs; 2432 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2433 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2434 txq->ift_timer.c_cpu); 2435 } 2436 2437 static int 2438 iflib_media_change(if_t ifp) 2439 { 2440 if_ctx_t ctx = if_getsoftc(ifp); 2441 int err; 2442 2443 CTX_LOCK(ctx); 2444 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2445 iflib_init_locked(ctx); 2446 CTX_UNLOCK(ctx); 2447 return (err); 2448 } 2449 2450 static void 2451 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2452 { 2453 if_ctx_t ctx = if_getsoftc(ifp); 2454 2455 CTX_LOCK(ctx); 2456 IFDI_UPDATE_ADMIN_STATUS(ctx); 2457 IFDI_MEDIA_STATUS(ctx, ifmr); 2458 CTX_UNLOCK(ctx); 2459 } 2460 2461 void 2462 iflib_stop(if_ctx_t ctx) 2463 { 2464 iflib_txq_t txq = ctx->ifc_txqs; 2465 iflib_rxq_t rxq = ctx->ifc_rxqs; 2466 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2467 if_shared_ctx_t sctx = ctx->ifc_sctx; 2468 iflib_dma_info_t di; 2469 iflib_fl_t fl; 2470 int i, j; 2471 2472 /* Tell the stack that the interface is no longer active */ 2473 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2474 2475 IFDI_INTR_DISABLE(ctx); 2476 DELAY(1000); 2477 IFDI_STOP(ctx); 2478 DELAY(1000); 2479 2480 iflib_debug_reset(); 2481 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2482 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2483 /* make sure all transmitters have completed before proceeding XXX */ 2484 2485 CALLOUT_LOCK(txq); 2486 callout_stop(&txq->ift_timer); 2487 CALLOUT_UNLOCK(txq); 2488 2489 /* clean any enqueued buffers */ 2490 iflib_ifmp_purge(txq); 2491 /* Free any existing tx buffers. */ 2492 for (j = 0; j < txq->ift_size; j++) { 2493 iflib_txsd_free(ctx, txq, j); 2494 } 2495 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2496 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2497 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2498 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2499 txq->ift_pullups = 0; 2500 ifmp_ring_reset_stats(txq->ift_br); 2501 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2502 bzero((void *)di->idi_vaddr, di->idi_size); 2503 } 2504 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2505 /* make sure all transmitters have completed before proceeding XXX */ 2506 2507 rxq->ifr_cq_cidx = 0; 2508 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2509 bzero((void *)di->idi_vaddr, di->idi_size); 2510 /* also resets the free lists pidx/cidx */ 2511 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2512 iflib_fl_bufs_free(fl); 2513 } 2514 } 2515 2516 static inline caddr_t 2517 calc_next_rxd(iflib_fl_t fl, int cidx) 2518 { 2519 qidx_t size; 2520 int nrxd; 2521 caddr_t start, end, cur, next; 2522 2523 nrxd = fl->ifl_size; 2524 size = fl->ifl_rxd_size; 2525 start = fl->ifl_ifdi->idi_vaddr; 2526 2527 if (__predict_false(size == 0)) 2528 return (start); 2529 cur = start + size*cidx; 2530 end = start + size*nrxd; 2531 next = CACHE_PTR_NEXT(cur); 2532 return (next < end ? next : start); 2533 } 2534 2535 static inline void 2536 prefetch_pkts(iflib_fl_t fl, int cidx) 2537 { 2538 int nextptr; 2539 int nrxd = fl->ifl_size; 2540 caddr_t next_rxd; 2541 2542 2543 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2544 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2545 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2546 next_rxd = calc_next_rxd(fl, cidx); 2547 prefetch(next_rxd); 2548 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2549 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2550 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2551 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2552 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2553 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2554 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2555 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2556 } 2557 2558 static struct mbuf * 2559 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2560 int *pf_rv, if_rxd_info_t ri) 2561 { 2562 bus_dmamap_t map; 2563 iflib_fl_t fl; 2564 caddr_t payload; 2565 struct mbuf *m; 2566 int flid, cidx, len, next; 2567 2568 map = NULL; 2569 flid = irf->irf_flid; 2570 cidx = irf->irf_idx; 2571 fl = &rxq->ifr_fl[flid]; 2572 sd->ifsd_fl = fl; 2573 m = fl->ifl_sds.ifsd_m[cidx]; 2574 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2575 fl->ifl_credits--; 2576 #if MEMORY_LOGGING 2577 fl->ifl_m_dequeued++; 2578 #endif 2579 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2580 prefetch_pkts(fl, cidx); 2581 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2582 prefetch(&fl->ifl_sds.ifsd_map[next]); 2583 map = fl->ifl_sds.ifsd_map[cidx]; 2584 2585 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2586 2587 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2588 irf->irf_len != 0) { 2589 payload = *sd->ifsd_cl; 2590 payload += ri->iri_pad; 2591 len = ri->iri_len - ri->iri_pad; 2592 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2593 len | PFIL_MEMPTR | PFIL_IN, NULL); 2594 switch (*pf_rv) { 2595 case PFIL_DROPPED: 2596 case PFIL_CONSUMED: 2597 /* 2598 * The filter ate it. Everything is recycled. 2599 */ 2600 m = NULL; 2601 unload = 0; 2602 break; 2603 case PFIL_REALLOCED: 2604 /* 2605 * The filter copied it. Everything is recycled. 2606 */ 2607 m = pfil_mem2mbuf(payload); 2608 unload = 0; 2609 break; 2610 case PFIL_PASS: 2611 /* 2612 * Filter said it was OK, so receive like 2613 * normal 2614 */ 2615 fl->ifl_sds.ifsd_m[cidx] = NULL; 2616 break; 2617 default: 2618 MPASS(0); 2619 } 2620 } else { 2621 fl->ifl_sds.ifsd_m[cidx] = NULL; 2622 *pf_rv = PFIL_PASS; 2623 } 2624 2625 if (unload && irf->irf_len != 0) 2626 bus_dmamap_unload(fl->ifl_buf_tag, map); 2627 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2628 if (__predict_false(fl->ifl_cidx == 0)) 2629 fl->ifl_gen = 0; 2630 bit_clear(fl->ifl_rx_bitmap, cidx); 2631 return (m); 2632 } 2633 2634 static struct mbuf * 2635 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2636 { 2637 struct mbuf *m, *mh, *mt; 2638 caddr_t cl; 2639 int *pf_rv_ptr, flags, i, padlen; 2640 bool consumed; 2641 2642 i = 0; 2643 mh = NULL; 2644 consumed = false; 2645 *pf_rv = PFIL_PASS; 2646 pf_rv_ptr = pf_rv; 2647 do { 2648 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2649 pf_rv_ptr, ri); 2650 2651 MPASS(*sd->ifsd_cl != NULL); 2652 2653 /* 2654 * Exclude zero-length frags & frags from 2655 * packets the filter has consumed or dropped 2656 */ 2657 if (ri->iri_frags[i].irf_len == 0 || consumed || 2658 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2659 if (mh == NULL) { 2660 /* everything saved here */ 2661 consumed = true; 2662 pf_rv_ptr = NULL; 2663 continue; 2664 } 2665 /* XXX we can save the cluster here, but not the mbuf */ 2666 m_init(m, M_NOWAIT, MT_DATA, 0); 2667 m_free(m); 2668 continue; 2669 } 2670 if (mh == NULL) { 2671 flags = M_PKTHDR|M_EXT; 2672 mh = mt = m; 2673 padlen = ri->iri_pad; 2674 } else { 2675 flags = M_EXT; 2676 mt->m_next = m; 2677 mt = m; 2678 /* assuming padding is only on the first fragment */ 2679 padlen = 0; 2680 } 2681 cl = *sd->ifsd_cl; 2682 *sd->ifsd_cl = NULL; 2683 2684 /* Can these two be made one ? */ 2685 m_init(m, M_NOWAIT, MT_DATA, flags); 2686 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2687 /* 2688 * These must follow m_init and m_cljset 2689 */ 2690 m->m_data += padlen; 2691 ri->iri_len -= padlen; 2692 m->m_len = ri->iri_frags[i].irf_len; 2693 } while (++i < ri->iri_nfrags); 2694 2695 return (mh); 2696 } 2697 2698 /* 2699 * Process one software descriptor 2700 */ 2701 static struct mbuf * 2702 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2703 { 2704 struct if_rxsd sd; 2705 struct mbuf *m; 2706 int pf_rv; 2707 2708 /* should I merge this back in now that the two paths are basically duplicated? */ 2709 if (ri->iri_nfrags == 1 && 2710 ri->iri_frags[0].irf_len != 0 && 2711 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2712 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2713 &pf_rv, ri); 2714 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2715 return (m); 2716 if (pf_rv == PFIL_PASS) { 2717 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2718 #ifndef __NO_STRICT_ALIGNMENT 2719 if (!IP_ALIGNED(m)) 2720 m->m_data += 2; 2721 #endif 2722 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2723 m->m_len = ri->iri_frags[0].irf_len; 2724 } 2725 } else { 2726 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2727 if (m == NULL) 2728 return (NULL); 2729 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2730 return (m); 2731 } 2732 m->m_pkthdr.len = ri->iri_len; 2733 m->m_pkthdr.rcvif = ri->iri_ifp; 2734 m->m_flags |= ri->iri_flags; 2735 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2736 m->m_pkthdr.flowid = ri->iri_flowid; 2737 M_HASHTYPE_SET(m, ri->iri_rsstype); 2738 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2739 m->m_pkthdr.csum_data = ri->iri_csum_data; 2740 return (m); 2741 } 2742 2743 #if defined(INET6) || defined(INET) 2744 static void 2745 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2746 { 2747 CURVNET_SET(lc->ifp->if_vnet); 2748 #if defined(INET6) 2749 *v6 = V_ip6_forwarding; 2750 #endif 2751 #if defined(INET) 2752 *v4 = V_ipforwarding; 2753 #endif 2754 CURVNET_RESTORE(); 2755 } 2756 2757 /* 2758 * Returns true if it's possible this packet could be LROed. 2759 * if it returns false, it is guaranteed that tcp_lro_rx() 2760 * would not return zero. 2761 */ 2762 static bool 2763 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2764 { 2765 struct ether_header *eh; 2766 2767 eh = mtod(m, struct ether_header *); 2768 switch (eh->ether_type) { 2769 #if defined(INET6) 2770 case htons(ETHERTYPE_IPV6): 2771 return (!v6_forwarding); 2772 #endif 2773 #if defined (INET) 2774 case htons(ETHERTYPE_IP): 2775 return (!v4_forwarding); 2776 #endif 2777 } 2778 2779 return false; 2780 } 2781 #else 2782 static void 2783 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2784 { 2785 } 2786 #endif 2787 2788 static void 2789 _task_fn_rx_watchdog(void *context) 2790 { 2791 iflib_rxq_t rxq = context; 2792 2793 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2794 } 2795 2796 static uint8_t 2797 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2798 { 2799 if_t ifp; 2800 if_ctx_t ctx = rxq->ifr_ctx; 2801 if_shared_ctx_t sctx = ctx->ifc_sctx; 2802 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2803 int avail, i; 2804 qidx_t *cidxp; 2805 struct if_rxd_info ri; 2806 int err, budget_left, rx_bytes, rx_pkts; 2807 iflib_fl_t fl; 2808 int lro_enabled; 2809 bool v4_forwarding, v6_forwarding, lro_possible; 2810 uint8_t retval = 0; 2811 2812 /* 2813 * XXX early demux data packets so that if_input processing only handles 2814 * acks in interrupt context 2815 */ 2816 struct mbuf *m, *mh, *mt, *mf; 2817 2818 NET_EPOCH_ASSERT(); 2819 2820 lro_possible = v4_forwarding = v6_forwarding = false; 2821 ifp = ctx->ifc_ifp; 2822 mh = mt = NULL; 2823 MPASS(budget > 0); 2824 rx_pkts = rx_bytes = 0; 2825 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2826 cidxp = &rxq->ifr_cq_cidx; 2827 else 2828 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2829 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2830 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2831 retval |= iflib_fl_refill_all(ctx, fl); 2832 DBG_COUNTER_INC(rx_unavail); 2833 return (retval); 2834 } 2835 2836 /* pfil needs the vnet to be set */ 2837 CURVNET_SET_QUIET(ifp->if_vnet); 2838 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2839 if (__predict_false(!CTX_ACTIVE(ctx))) { 2840 DBG_COUNTER_INC(rx_ctx_inactive); 2841 break; 2842 } 2843 /* 2844 * Reset client set fields to their default values 2845 */ 2846 rxd_info_zero(&ri); 2847 ri.iri_qsidx = rxq->ifr_id; 2848 ri.iri_cidx = *cidxp; 2849 ri.iri_ifp = ifp; 2850 ri.iri_frags = rxq->ifr_frags; 2851 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2852 2853 if (err) 2854 goto err; 2855 rx_pkts += 1; 2856 rx_bytes += ri.iri_len; 2857 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2858 *cidxp = ri.iri_cidx; 2859 /* Update our consumer index */ 2860 /* XXX NB: shurd - check if this is still safe */ 2861 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2862 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2863 /* was this only a completion queue message? */ 2864 if (__predict_false(ri.iri_nfrags == 0)) 2865 continue; 2866 } 2867 MPASS(ri.iri_nfrags != 0); 2868 MPASS(ri.iri_len != 0); 2869 2870 /* will advance the cidx on the corresponding free lists */ 2871 m = iflib_rxd_pkt_get(rxq, &ri); 2872 avail--; 2873 budget_left--; 2874 if (avail == 0 && budget_left) 2875 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2876 2877 if (__predict_false(m == NULL)) 2878 continue; 2879 2880 /* imm_pkt: -- cxgb */ 2881 if (mh == NULL) 2882 mh = mt = m; 2883 else { 2884 mt->m_nextpkt = m; 2885 mt = m; 2886 } 2887 } 2888 CURVNET_RESTORE(); 2889 /* make sure that we can refill faster than drain */ 2890 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2891 retval |= iflib_fl_refill_all(ctx, fl); 2892 2893 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2894 if (lro_enabled) 2895 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2896 mt = mf = NULL; 2897 while (mh != NULL) { 2898 m = mh; 2899 mh = mh->m_nextpkt; 2900 m->m_nextpkt = NULL; 2901 #ifndef __NO_STRICT_ALIGNMENT 2902 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2903 continue; 2904 #endif 2905 rx_bytes += m->m_pkthdr.len; 2906 rx_pkts++; 2907 #if defined(INET6) || defined(INET) 2908 if (lro_enabled) { 2909 if (!lro_possible) { 2910 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2911 if (lro_possible && mf != NULL) { 2912 ifp->if_input(ifp, mf); 2913 DBG_COUNTER_INC(rx_if_input); 2914 mt = mf = NULL; 2915 } 2916 } 2917 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2918 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2919 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2920 continue; 2921 } 2922 } 2923 #endif 2924 if (lro_possible) { 2925 ifp->if_input(ifp, m); 2926 DBG_COUNTER_INC(rx_if_input); 2927 continue; 2928 } 2929 2930 if (mf == NULL) 2931 mf = m; 2932 if (mt != NULL) 2933 mt->m_nextpkt = m; 2934 mt = m; 2935 } 2936 if (mf != NULL) { 2937 ifp->if_input(ifp, mf); 2938 DBG_COUNTER_INC(rx_if_input); 2939 } 2940 2941 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2942 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2943 2944 /* 2945 * Flush any outstanding LRO work 2946 */ 2947 #if defined(INET6) || defined(INET) 2948 tcp_lro_flush_all(&rxq->ifr_lc); 2949 #endif 2950 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2951 retval |= IFLIB_RXEOF_MORE; 2952 return (retval); 2953 err: 2954 STATE_LOCK(ctx); 2955 ctx->ifc_flags |= IFC_DO_RESET; 2956 iflib_admin_intr_deferred(ctx); 2957 STATE_UNLOCK(ctx); 2958 return (0); 2959 } 2960 2961 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2962 static inline qidx_t 2963 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2964 { 2965 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2966 qidx_t minthresh = txq->ift_size / 8; 2967 if (in_use > 4*minthresh) 2968 return (notify_count); 2969 if (in_use > 2*minthresh) 2970 return (notify_count >> 1); 2971 if (in_use > minthresh) 2972 return (notify_count >> 3); 2973 return (0); 2974 } 2975 2976 static inline qidx_t 2977 txq_max_rs_deferred(iflib_txq_t txq) 2978 { 2979 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2980 qidx_t minthresh = txq->ift_size / 8; 2981 if (txq->ift_in_use > 4*minthresh) 2982 return (notify_count); 2983 if (txq->ift_in_use > 2*minthresh) 2984 return (notify_count >> 1); 2985 if (txq->ift_in_use > minthresh) 2986 return (notify_count >> 2); 2987 return (2); 2988 } 2989 2990 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2991 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2992 2993 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2994 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2995 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2996 2997 /* forward compatibility for cxgb */ 2998 #define FIRST_QSET(ctx) 0 2999 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3000 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3001 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3002 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3003 3004 /* XXX we should be setting this to something other than zero */ 3005 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3006 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3007 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3008 3009 static inline bool 3010 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 3011 { 3012 qidx_t dbval, max; 3013 bool rang; 3014 3015 rang = false; 3016 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 3017 if (ring || txq->ift_db_pending >= max) { 3018 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3019 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3021 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3022 txq->ift_db_pending = txq->ift_npending = 0; 3023 rang = true; 3024 } 3025 return (rang); 3026 } 3027 3028 #ifdef PKT_DEBUG 3029 static void 3030 print_pkt(if_pkt_info_t pi) 3031 { 3032 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3033 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3034 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3035 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3036 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3037 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3038 } 3039 #endif 3040 3041 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3042 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3043 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3044 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3045 3046 static int 3047 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3048 { 3049 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3050 struct ether_vlan_header *eh; 3051 struct mbuf *m; 3052 3053 m = *mp; 3054 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3055 M_WRITABLE(m) == 0) { 3056 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3057 return (ENOMEM); 3058 } else { 3059 m_freem(*mp); 3060 DBG_COUNTER_INC(tx_frees); 3061 *mp = m; 3062 } 3063 } 3064 3065 /* 3066 * Determine where frame payload starts. 3067 * Jump over vlan headers if already present, 3068 * helpful for QinQ too. 3069 */ 3070 if (__predict_false(m->m_len < sizeof(*eh))) { 3071 txq->ift_pullups++; 3072 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3073 return (ENOMEM); 3074 } 3075 eh = mtod(m, struct ether_vlan_header *); 3076 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3077 pi->ipi_etype = ntohs(eh->evl_proto); 3078 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3079 } else { 3080 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3081 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3082 } 3083 3084 switch (pi->ipi_etype) { 3085 #ifdef INET 3086 case ETHERTYPE_IP: 3087 { 3088 struct mbuf *n; 3089 struct ip *ip = NULL; 3090 struct tcphdr *th = NULL; 3091 int minthlen; 3092 3093 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3094 if (__predict_false(m->m_len < minthlen)) { 3095 /* 3096 * if this code bloat is causing too much of a hit 3097 * move it to a separate function and mark it noinline 3098 */ 3099 if (m->m_len == pi->ipi_ehdrlen) { 3100 n = m->m_next; 3101 MPASS(n); 3102 if (n->m_len >= sizeof(*ip)) { 3103 ip = (struct ip *)n->m_data; 3104 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3105 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3106 } else { 3107 txq->ift_pullups++; 3108 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3109 return (ENOMEM); 3110 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3111 } 3112 } else { 3113 txq->ift_pullups++; 3114 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3115 return (ENOMEM); 3116 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3117 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3118 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3119 } 3120 } else { 3121 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3122 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3123 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3124 } 3125 pi->ipi_ip_hlen = ip->ip_hl << 2; 3126 pi->ipi_ipproto = ip->ip_p; 3127 pi->ipi_flags |= IPI_TX_IPV4; 3128 3129 /* TCP checksum offload may require TCP header length */ 3130 if (IS_TX_OFFLOAD4(pi)) { 3131 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3132 if (__predict_false(th == NULL)) { 3133 txq->ift_pullups++; 3134 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3135 return (ENOMEM); 3136 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3137 } 3138 pi->ipi_tcp_hflags = th->th_flags; 3139 pi->ipi_tcp_hlen = th->th_off << 2; 3140 pi->ipi_tcp_seq = th->th_seq; 3141 } 3142 if (IS_TSO4(pi)) { 3143 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3144 return (ENXIO); 3145 /* 3146 * TSO always requires hardware checksum offload. 3147 */ 3148 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3149 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3150 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3151 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3152 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3153 ip->ip_sum = 0; 3154 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3155 } 3156 } 3157 } 3158 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3159 ip->ip_sum = 0; 3160 3161 break; 3162 } 3163 #endif 3164 #ifdef INET6 3165 case ETHERTYPE_IPV6: 3166 { 3167 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3168 struct tcphdr *th; 3169 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3170 3171 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3172 txq->ift_pullups++; 3173 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3174 return (ENOMEM); 3175 } 3176 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3177 3178 /* XXX-BZ this will go badly in case of ext hdrs. */ 3179 pi->ipi_ipproto = ip6->ip6_nxt; 3180 pi->ipi_flags |= IPI_TX_IPV6; 3181 3182 /* TCP checksum offload may require TCP header length */ 3183 if (IS_TX_OFFLOAD6(pi)) { 3184 if (pi->ipi_ipproto == IPPROTO_TCP) { 3185 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3186 txq->ift_pullups++; 3187 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3188 return (ENOMEM); 3189 } 3190 pi->ipi_tcp_hflags = th->th_flags; 3191 pi->ipi_tcp_hlen = th->th_off << 2; 3192 pi->ipi_tcp_seq = th->th_seq; 3193 } 3194 if (IS_TSO6(pi)) { 3195 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3196 return (ENXIO); 3197 /* 3198 * TSO always requires hardware checksum offload. 3199 */ 3200 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3201 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3202 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3203 } 3204 } 3205 break; 3206 } 3207 #endif 3208 default: 3209 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3210 pi->ipi_ip_hlen = 0; 3211 break; 3212 } 3213 *mp = m; 3214 3215 return (0); 3216 } 3217 3218 /* 3219 * If dodgy hardware rejects the scatter gather chain we've handed it 3220 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3221 * m_defrag'd mbufs 3222 */ 3223 static __noinline struct mbuf * 3224 iflib_remove_mbuf(iflib_txq_t txq) 3225 { 3226 int ntxd, pidx; 3227 struct mbuf *m, **ifsd_m; 3228 3229 ifsd_m = txq->ift_sds.ifsd_m; 3230 ntxd = txq->ift_size; 3231 pidx = txq->ift_pidx & (ntxd - 1); 3232 ifsd_m = txq->ift_sds.ifsd_m; 3233 m = ifsd_m[pidx]; 3234 ifsd_m[pidx] = NULL; 3235 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3236 if (txq->ift_sds.ifsd_tso_map != NULL) 3237 bus_dmamap_unload(txq->ift_tso_buf_tag, 3238 txq->ift_sds.ifsd_tso_map[pidx]); 3239 #if MEMORY_LOGGING 3240 txq->ift_dequeued++; 3241 #endif 3242 return (m); 3243 } 3244 3245 static inline caddr_t 3246 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3247 { 3248 qidx_t size; 3249 int ntxd; 3250 caddr_t start, end, cur, next; 3251 3252 ntxd = txq->ift_size; 3253 size = txq->ift_txd_size[qid]; 3254 start = txq->ift_ifdi[qid].idi_vaddr; 3255 3256 if (__predict_false(size == 0)) 3257 return (start); 3258 cur = start + size*cidx; 3259 end = start + size*ntxd; 3260 next = CACHE_PTR_NEXT(cur); 3261 return (next < end ? next : start); 3262 } 3263 3264 /* 3265 * Pad an mbuf to ensure a minimum ethernet frame size. 3266 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3267 */ 3268 static __noinline int 3269 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3270 { 3271 /* 3272 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3273 * and ARP message is the smallest common payload I can think of 3274 */ 3275 static char pad[18]; /* just zeros */ 3276 int n; 3277 struct mbuf *new_head; 3278 3279 if (!M_WRITABLE(*m_head)) { 3280 new_head = m_dup(*m_head, M_NOWAIT); 3281 if (new_head == NULL) { 3282 m_freem(*m_head); 3283 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3284 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3285 DBG_COUNTER_INC(tx_frees); 3286 return ENOMEM; 3287 } 3288 m_freem(*m_head); 3289 *m_head = new_head; 3290 } 3291 3292 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3293 n > 0; n -= sizeof(pad)) 3294 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3295 break; 3296 3297 if (n > 0) { 3298 m_freem(*m_head); 3299 device_printf(dev, "cannot pad short frame\n"); 3300 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3301 DBG_COUNTER_INC(tx_frees); 3302 return (ENOBUFS); 3303 } 3304 3305 return 0; 3306 } 3307 3308 static int 3309 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3310 { 3311 if_ctx_t ctx; 3312 if_shared_ctx_t sctx; 3313 if_softc_ctx_t scctx; 3314 bus_dma_tag_t buf_tag; 3315 bus_dma_segment_t *segs; 3316 struct mbuf *m_head, **ifsd_m; 3317 void *next_txd; 3318 bus_dmamap_t map; 3319 struct if_pkt_info pi; 3320 int remap = 0; 3321 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3322 3323 ctx = txq->ift_ctx; 3324 sctx = ctx->ifc_sctx; 3325 scctx = &ctx->ifc_softc_ctx; 3326 segs = txq->ift_segs; 3327 ntxd = txq->ift_size; 3328 m_head = *m_headp; 3329 map = NULL; 3330 3331 /* 3332 * If we're doing TSO the next descriptor to clean may be quite far ahead 3333 */ 3334 cidx = txq->ift_cidx; 3335 pidx = txq->ift_pidx; 3336 if (ctx->ifc_flags & IFC_PREFETCH) { 3337 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3338 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3339 next_txd = calc_next_txd(txq, cidx, 0); 3340 prefetch(next_txd); 3341 } 3342 3343 /* prefetch the next cache line of mbuf pointers and flags */ 3344 prefetch(&txq->ift_sds.ifsd_m[next]); 3345 prefetch(&txq->ift_sds.ifsd_map[next]); 3346 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3347 } 3348 map = txq->ift_sds.ifsd_map[pidx]; 3349 ifsd_m = txq->ift_sds.ifsd_m; 3350 3351 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3352 buf_tag = txq->ift_tso_buf_tag; 3353 max_segs = scctx->isc_tx_tso_segments_max; 3354 map = txq->ift_sds.ifsd_tso_map[pidx]; 3355 MPASS(buf_tag != NULL); 3356 MPASS(max_segs > 0); 3357 } else { 3358 buf_tag = txq->ift_buf_tag; 3359 max_segs = scctx->isc_tx_nsegments; 3360 map = txq->ift_sds.ifsd_map[pidx]; 3361 } 3362 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3363 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3364 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3365 if (err) { 3366 DBG_COUNTER_INC(encap_txd_encap_fail); 3367 return err; 3368 } 3369 } 3370 m_head = *m_headp; 3371 3372 pkt_info_zero(&pi); 3373 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3374 pi.ipi_pidx = pidx; 3375 pi.ipi_qsidx = txq->ift_id; 3376 pi.ipi_len = m_head->m_pkthdr.len; 3377 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3378 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3379 3380 /* deliberate bitwise OR to make one condition */ 3381 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3382 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3383 DBG_COUNTER_INC(encap_txd_encap_fail); 3384 return (err); 3385 } 3386 m_head = *m_headp; 3387 } 3388 3389 retry: 3390 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3391 BUS_DMA_NOWAIT); 3392 defrag: 3393 if (__predict_false(err)) { 3394 switch (err) { 3395 case EFBIG: 3396 /* try collapse once and defrag once */ 3397 if (remap == 0) { 3398 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3399 /* try defrag if collapsing fails */ 3400 if (m_head == NULL) 3401 remap++; 3402 } 3403 if (remap == 1) { 3404 txq->ift_mbuf_defrag++; 3405 m_head = m_defrag(*m_headp, M_NOWAIT); 3406 } 3407 /* 3408 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3409 * failed to map an mbuf that was run through m_defrag 3410 */ 3411 MPASS(remap <= 1); 3412 if (__predict_false(m_head == NULL || remap > 1)) 3413 goto defrag_failed; 3414 remap++; 3415 *m_headp = m_head; 3416 goto retry; 3417 break; 3418 case ENOMEM: 3419 txq->ift_no_tx_dma_setup++; 3420 break; 3421 default: 3422 txq->ift_no_tx_dma_setup++; 3423 m_freem(*m_headp); 3424 DBG_COUNTER_INC(tx_frees); 3425 *m_headp = NULL; 3426 break; 3427 } 3428 txq->ift_map_failed++; 3429 DBG_COUNTER_INC(encap_load_mbuf_fail); 3430 DBG_COUNTER_INC(encap_txd_encap_fail); 3431 return (err); 3432 } 3433 ifsd_m[pidx] = m_head; 3434 /* 3435 * XXX assumes a 1 to 1 relationship between segments and 3436 * descriptors - this does not hold true on all drivers, e.g. 3437 * cxgb 3438 */ 3439 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3440 txq->ift_no_desc_avail++; 3441 bus_dmamap_unload(buf_tag, map); 3442 DBG_COUNTER_INC(encap_txq_avail_fail); 3443 DBG_COUNTER_INC(encap_txd_encap_fail); 3444 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3445 GROUPTASK_ENQUEUE(&txq->ift_task); 3446 return (ENOBUFS); 3447 } 3448 /* 3449 * On Intel cards we can greatly reduce the number of TX interrupts 3450 * we see by only setting report status on every Nth descriptor. 3451 * However, this also means that the driver will need to keep track 3452 * of the descriptors that RS was set on to check them for the DD bit. 3453 */ 3454 txq->ift_rs_pending += nsegs + 1; 3455 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3456 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3457 pi.ipi_flags |= IPI_TX_INTR; 3458 txq->ift_rs_pending = 0; 3459 } 3460 3461 pi.ipi_segs = segs; 3462 pi.ipi_nsegs = nsegs; 3463 3464 MPASS(pidx >= 0 && pidx < txq->ift_size); 3465 #ifdef PKT_DEBUG 3466 print_pkt(&pi); 3467 #endif 3468 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3469 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3470 DBG_COUNTER_INC(tx_encap); 3471 MPASS(pi.ipi_new_pidx < txq->ift_size); 3472 3473 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3474 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3475 ndesc += txq->ift_size; 3476 txq->ift_gen = 1; 3477 } 3478 /* 3479 * drivers can need as many as 3480 * two sentinels 3481 */ 3482 MPASS(ndesc <= pi.ipi_nsegs + 2); 3483 MPASS(pi.ipi_new_pidx != pidx); 3484 MPASS(ndesc > 0); 3485 txq->ift_in_use += ndesc; 3486 3487 /* 3488 * We update the last software descriptor again here because there may 3489 * be a sentinel and/or there may be more mbufs than segments 3490 */ 3491 txq->ift_pidx = pi.ipi_new_pidx; 3492 txq->ift_npending += pi.ipi_ndescs; 3493 } else { 3494 *m_headp = m_head = iflib_remove_mbuf(txq); 3495 if (err == EFBIG) { 3496 txq->ift_txd_encap_efbig++; 3497 if (remap < 2) { 3498 remap = 1; 3499 goto defrag; 3500 } 3501 } 3502 goto defrag_failed; 3503 } 3504 /* 3505 * err can't possibly be non-zero here, so we don't neet to test it 3506 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3507 */ 3508 return (err); 3509 3510 defrag_failed: 3511 txq->ift_mbuf_defrag_failed++; 3512 txq->ift_map_failed++; 3513 m_freem(*m_headp); 3514 DBG_COUNTER_INC(tx_frees); 3515 *m_headp = NULL; 3516 DBG_COUNTER_INC(encap_txd_encap_fail); 3517 return (ENOMEM); 3518 } 3519 3520 static void 3521 iflib_tx_desc_free(iflib_txq_t txq, int n) 3522 { 3523 uint32_t qsize, cidx, mask, gen; 3524 struct mbuf *m, **ifsd_m; 3525 bool do_prefetch; 3526 3527 cidx = txq->ift_cidx; 3528 gen = txq->ift_gen; 3529 qsize = txq->ift_size; 3530 mask = qsize-1; 3531 ifsd_m = txq->ift_sds.ifsd_m; 3532 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3533 3534 while (n-- > 0) { 3535 if (do_prefetch) { 3536 prefetch(ifsd_m[(cidx + 3) & mask]); 3537 prefetch(ifsd_m[(cidx + 4) & mask]); 3538 } 3539 if ((m = ifsd_m[cidx]) != NULL) { 3540 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3541 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3542 bus_dmamap_sync(txq->ift_tso_buf_tag, 3543 txq->ift_sds.ifsd_tso_map[cidx], 3544 BUS_DMASYNC_POSTWRITE); 3545 bus_dmamap_unload(txq->ift_tso_buf_tag, 3546 txq->ift_sds.ifsd_tso_map[cidx]); 3547 } else { 3548 bus_dmamap_sync(txq->ift_buf_tag, 3549 txq->ift_sds.ifsd_map[cidx], 3550 BUS_DMASYNC_POSTWRITE); 3551 bus_dmamap_unload(txq->ift_buf_tag, 3552 txq->ift_sds.ifsd_map[cidx]); 3553 } 3554 /* XXX we don't support any drivers that batch packets yet */ 3555 MPASS(m->m_nextpkt == NULL); 3556 m_freem(m); 3557 ifsd_m[cidx] = NULL; 3558 #if MEMORY_LOGGING 3559 txq->ift_dequeued++; 3560 #endif 3561 DBG_COUNTER_INC(tx_frees); 3562 } 3563 if (__predict_false(++cidx == qsize)) { 3564 cidx = 0; 3565 gen = 0; 3566 } 3567 } 3568 txq->ift_cidx = cidx; 3569 txq->ift_gen = gen; 3570 } 3571 3572 static __inline int 3573 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3574 { 3575 int reclaim; 3576 if_ctx_t ctx = txq->ift_ctx; 3577 3578 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3579 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3580 3581 /* 3582 * Need a rate-limiting check so that this isn't called every time 3583 */ 3584 iflib_tx_credits_update(ctx, txq); 3585 reclaim = DESC_RECLAIMABLE(txq); 3586 3587 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3588 #ifdef INVARIANTS 3589 if (iflib_verbose_debug) { 3590 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3591 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3592 reclaim, thresh); 3593 3594 } 3595 #endif 3596 return (0); 3597 } 3598 iflib_tx_desc_free(txq, reclaim); 3599 txq->ift_cleaned += reclaim; 3600 txq->ift_in_use -= reclaim; 3601 3602 return (reclaim); 3603 } 3604 3605 static struct mbuf ** 3606 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3607 { 3608 int next, size; 3609 struct mbuf **items; 3610 3611 size = r->size; 3612 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3613 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3614 3615 prefetch(items[(cidx + offset) & (size-1)]); 3616 if (remaining > 1) { 3617 prefetch2cachelines(&items[next]); 3618 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3619 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3620 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3621 } 3622 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3623 } 3624 3625 static void 3626 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3627 { 3628 3629 ifmp_ring_check_drainage(txq->ift_br, budget); 3630 } 3631 3632 static uint32_t 3633 iflib_txq_can_drain(struct ifmp_ring *r) 3634 { 3635 iflib_txq_t txq = r->cookie; 3636 if_ctx_t ctx = txq->ift_ctx; 3637 3638 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3639 return (1); 3640 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3641 BUS_DMASYNC_POSTREAD); 3642 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3643 false)); 3644 } 3645 3646 static uint32_t 3647 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3648 { 3649 iflib_txq_t txq = r->cookie; 3650 if_ctx_t ctx = txq->ift_ctx; 3651 if_t ifp = ctx->ifc_ifp; 3652 struct mbuf *m, **mp; 3653 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3654 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3655 bool do_prefetch, rang, ring; 3656 3657 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3658 !LINK_ACTIVE(ctx))) { 3659 DBG_COUNTER_INC(txq_drain_notready); 3660 return (0); 3661 } 3662 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3663 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3664 avail = IDXDIFF(pidx, cidx, r->size); 3665 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3666 DBG_COUNTER_INC(txq_drain_flushing); 3667 for (i = 0; i < avail; i++) { 3668 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3669 m_free(r->items[(cidx + i) & (r->size-1)]); 3670 r->items[(cidx + i) & (r->size-1)] = NULL; 3671 } 3672 return (avail); 3673 } 3674 3675 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3676 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3677 CALLOUT_LOCK(txq); 3678 callout_stop(&txq->ift_timer); 3679 CALLOUT_UNLOCK(txq); 3680 DBG_COUNTER_INC(txq_drain_oactive); 3681 return (0); 3682 } 3683 if (reclaimed) 3684 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3685 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3686 count = MIN(avail, TX_BATCH_SIZE); 3687 #ifdef INVARIANTS 3688 if (iflib_verbose_debug) 3689 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3690 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3691 #endif 3692 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3693 txq_avail = TXQ_AVAIL(txq); 3694 err = 0; 3695 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3696 int rem = do_prefetch ? count - i : 0; 3697 3698 mp = _ring_peek_one(r, cidx, i, rem); 3699 MPASS(mp != NULL && *mp != NULL); 3700 if (__predict_false(*mp == (struct mbuf *)txq)) { 3701 consumed++; 3702 continue; 3703 } 3704 in_use_prev = txq->ift_in_use; 3705 err = iflib_encap(txq, mp); 3706 if (__predict_false(err)) { 3707 /* no room - bail out */ 3708 if (err == ENOBUFS) 3709 break; 3710 consumed++; 3711 /* we can't send this packet - skip it */ 3712 continue; 3713 } 3714 consumed++; 3715 pkt_sent++; 3716 m = *mp; 3717 DBG_COUNTER_INC(tx_sent); 3718 bytes_sent += m->m_pkthdr.len; 3719 mcast_sent += !!(m->m_flags & M_MCAST); 3720 txq_avail = TXQ_AVAIL(txq); 3721 3722 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3723 ETHER_BPF_MTAP(ifp, m); 3724 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3725 break; 3726 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3727 } 3728 3729 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3730 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3731 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3732 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3733 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3734 if (mcast_sent) 3735 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3736 #ifdef INVARIANTS 3737 if (iflib_verbose_debug) 3738 printf("consumed=%d\n", consumed); 3739 #endif 3740 return (consumed); 3741 } 3742 3743 static uint32_t 3744 iflib_txq_drain_always(struct ifmp_ring *r) 3745 { 3746 return (1); 3747 } 3748 3749 static uint32_t 3750 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3751 { 3752 int i, avail; 3753 struct mbuf **mp; 3754 iflib_txq_t txq; 3755 3756 txq = r->cookie; 3757 3758 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3759 CALLOUT_LOCK(txq); 3760 callout_stop(&txq->ift_timer); 3761 CALLOUT_UNLOCK(txq); 3762 3763 avail = IDXDIFF(pidx, cidx, r->size); 3764 for (i = 0; i < avail; i++) { 3765 mp = _ring_peek_one(r, cidx, i, avail - i); 3766 if (__predict_false(*mp == (struct mbuf *)txq)) 3767 continue; 3768 m_freem(*mp); 3769 DBG_COUNTER_INC(tx_frees); 3770 } 3771 MPASS(ifmp_ring_is_stalled(r) == 0); 3772 return (avail); 3773 } 3774 3775 static void 3776 iflib_ifmp_purge(iflib_txq_t txq) 3777 { 3778 struct ifmp_ring *r; 3779 3780 r = txq->ift_br; 3781 r->drain = iflib_txq_drain_free; 3782 r->can_drain = iflib_txq_drain_always; 3783 3784 ifmp_ring_check_drainage(r, r->size); 3785 3786 r->drain = iflib_txq_drain; 3787 r->can_drain = iflib_txq_can_drain; 3788 } 3789 3790 static void 3791 _task_fn_tx(void *context) 3792 { 3793 iflib_txq_t txq = context; 3794 if_ctx_t ctx = txq->ift_ctx; 3795 if_t ifp = ctx->ifc_ifp; 3796 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3797 3798 #ifdef IFLIB_DIAGNOSTICS 3799 txq->ift_cpu_exec_count[curcpu]++; 3800 #endif 3801 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3802 return; 3803 #ifdef DEV_NETMAP 3804 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3805 netmap_tx_irq(ifp, txq->ift_id)) 3806 goto skip_ifmp; 3807 #endif 3808 #ifdef ALTQ 3809 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3810 iflib_altq_if_start(ifp); 3811 #endif 3812 if (txq->ift_db_pending) 3813 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3814 else if (!abdicate) 3815 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3816 /* 3817 * When abdicating, we always need to check drainage, not just when we don't enqueue 3818 */ 3819 if (abdicate) 3820 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3821 #ifdef DEV_NETMAP 3822 skip_ifmp: 3823 #endif 3824 if (ctx->ifc_flags & IFC_LEGACY) 3825 IFDI_INTR_ENABLE(ctx); 3826 else 3827 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3828 } 3829 3830 static void 3831 _task_fn_rx(void *context) 3832 { 3833 iflib_rxq_t rxq = context; 3834 if_ctx_t ctx = rxq->ifr_ctx; 3835 uint8_t more; 3836 uint16_t budget; 3837 #ifdef DEV_NETMAP 3838 u_int work = 0; 3839 int nmirq; 3840 #endif 3841 3842 #ifdef IFLIB_DIAGNOSTICS 3843 rxq->ifr_cpu_exec_count[curcpu]++; 3844 #endif 3845 DBG_COUNTER_INC(task_fn_rxs); 3846 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3847 return; 3848 #ifdef DEV_NETMAP 3849 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3850 if (nmirq != NM_IRQ_PASS) { 3851 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3852 goto skip_rxeof; 3853 } 3854 #endif 3855 budget = ctx->ifc_sysctl_rx_budget; 3856 if (budget == 0) 3857 budget = 16; /* XXX */ 3858 more = iflib_rxeof(rxq, budget); 3859 #ifdef DEV_NETMAP 3860 skip_rxeof: 3861 #endif 3862 if ((more & IFLIB_RXEOF_MORE) == 0) { 3863 if (ctx->ifc_flags & IFC_LEGACY) 3864 IFDI_INTR_ENABLE(ctx); 3865 else 3866 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3867 DBG_COUNTER_INC(rx_intr_enables); 3868 } 3869 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3870 return; 3871 3872 if (more & IFLIB_RXEOF_MORE) 3873 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3874 else if (more & IFLIB_RXEOF_EMPTY) 3875 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3876 } 3877 3878 static void 3879 _task_fn_admin(void *context) 3880 { 3881 if_ctx_t ctx = context; 3882 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3883 iflib_txq_t txq; 3884 int i; 3885 bool oactive, running, do_reset, do_watchdog, in_detach; 3886 uint32_t reset_on = hz / 2; 3887 3888 STATE_LOCK(ctx); 3889 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3890 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3891 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3892 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3893 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3894 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3895 STATE_UNLOCK(ctx); 3896 3897 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3898 return; 3899 if (in_detach) 3900 return; 3901 3902 CTX_LOCK(ctx); 3903 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3904 CALLOUT_LOCK(txq); 3905 callout_stop(&txq->ift_timer); 3906 CALLOUT_UNLOCK(txq); 3907 } 3908 if (do_watchdog) { 3909 ctx->ifc_watchdog_events++; 3910 IFDI_WATCHDOG_RESET(ctx); 3911 } 3912 IFDI_UPDATE_ADMIN_STATUS(ctx); 3913 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3914 #ifdef DEV_NETMAP 3915 reset_on = hz / 2; 3916 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3917 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3918 #endif 3919 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3920 } 3921 IFDI_LINK_INTR_ENABLE(ctx); 3922 if (do_reset) 3923 iflib_if_init_locked(ctx); 3924 CTX_UNLOCK(ctx); 3925 3926 if (LINK_ACTIVE(ctx) == 0) 3927 return; 3928 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3929 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3930 } 3931 3932 3933 static void 3934 _task_fn_iov(void *context) 3935 { 3936 if_ctx_t ctx = context; 3937 3938 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3939 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3940 return; 3941 3942 CTX_LOCK(ctx); 3943 IFDI_VFLR_HANDLE(ctx); 3944 CTX_UNLOCK(ctx); 3945 } 3946 3947 static int 3948 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3949 { 3950 int err; 3951 if_int_delay_info_t info; 3952 if_ctx_t ctx; 3953 3954 info = (if_int_delay_info_t)arg1; 3955 ctx = info->iidi_ctx; 3956 info->iidi_req = req; 3957 info->iidi_oidp = oidp; 3958 CTX_LOCK(ctx); 3959 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3960 CTX_UNLOCK(ctx); 3961 return (err); 3962 } 3963 3964 /********************************************************************* 3965 * 3966 * IFNET FUNCTIONS 3967 * 3968 **********************************************************************/ 3969 3970 static void 3971 iflib_if_init_locked(if_ctx_t ctx) 3972 { 3973 iflib_stop(ctx); 3974 iflib_init_locked(ctx); 3975 } 3976 3977 3978 static void 3979 iflib_if_init(void *arg) 3980 { 3981 if_ctx_t ctx = arg; 3982 3983 CTX_LOCK(ctx); 3984 iflib_if_init_locked(ctx); 3985 CTX_UNLOCK(ctx); 3986 } 3987 3988 static int 3989 iflib_if_transmit(if_t ifp, struct mbuf *m) 3990 { 3991 if_ctx_t ctx = if_getsoftc(ifp); 3992 3993 iflib_txq_t txq; 3994 int err, qidx; 3995 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3996 3997 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3998 DBG_COUNTER_INC(tx_frees); 3999 m_freem(m); 4000 return (ENETDOWN); 4001 } 4002 4003 MPASS(m->m_nextpkt == NULL); 4004 /* ALTQ-enabled interfaces always use queue 0. */ 4005 qidx = 0; 4006 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4007 qidx = QIDX(ctx, m); 4008 /* 4009 * XXX calculate buf_ring based on flowid (divvy up bits?) 4010 */ 4011 txq = &ctx->ifc_txqs[qidx]; 4012 4013 #ifdef DRIVER_BACKPRESSURE 4014 if (txq->ift_closed) { 4015 while (m != NULL) { 4016 next = m->m_nextpkt; 4017 m->m_nextpkt = NULL; 4018 m_freem(m); 4019 DBG_COUNTER_INC(tx_frees); 4020 m = next; 4021 } 4022 return (ENOBUFS); 4023 } 4024 #endif 4025 #ifdef notyet 4026 qidx = count = 0; 4027 mp = marr; 4028 next = m; 4029 do { 4030 count++; 4031 next = next->m_nextpkt; 4032 } while (next != NULL); 4033 4034 if (count > nitems(marr)) 4035 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4036 /* XXX check nextpkt */ 4037 m_freem(m); 4038 /* XXX simplify for now */ 4039 DBG_COUNTER_INC(tx_frees); 4040 return (ENOBUFS); 4041 } 4042 for (next = m, i = 0; next != NULL; i++) { 4043 mp[i] = next; 4044 next = next->m_nextpkt; 4045 mp[i]->m_nextpkt = NULL; 4046 } 4047 #endif 4048 DBG_COUNTER_INC(tx_seen); 4049 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4050 4051 if (abdicate) 4052 GROUPTASK_ENQUEUE(&txq->ift_task); 4053 if (err) { 4054 if (!abdicate) 4055 GROUPTASK_ENQUEUE(&txq->ift_task); 4056 /* support forthcoming later */ 4057 #ifdef DRIVER_BACKPRESSURE 4058 txq->ift_closed = TRUE; 4059 #endif 4060 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4061 m_freem(m); 4062 DBG_COUNTER_INC(tx_frees); 4063 } 4064 4065 return (err); 4066 } 4067 4068 #ifdef ALTQ 4069 /* 4070 * The overall approach to integrating iflib with ALTQ is to continue to use 4071 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4072 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4073 * is redundant/unnecessary, but doing so minimizes the amount of 4074 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4075 * redundantly queueing to an intermediate mp_ring is swamped by the 4076 * performance limitations inherent in using ALTQ. 4077 * 4078 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4079 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4080 * given interface. If ALTQ is enabled for an interface, then all 4081 * transmitted packets for that interface will be submitted to the ALTQ 4082 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4083 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4084 * update stats that the iflib machinery handles, and which is sensitve to 4085 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4086 * will be installed as the start routine for use by ALTQ facilities that 4087 * need to trigger queue drains on a scheduled basis. 4088 * 4089 */ 4090 static void 4091 iflib_altq_if_start(if_t ifp) 4092 { 4093 struct ifaltq *ifq = &ifp->if_snd; 4094 struct mbuf *m; 4095 4096 IFQ_LOCK(ifq); 4097 IFQ_DEQUEUE_NOLOCK(ifq, m); 4098 while (m != NULL) { 4099 iflib_if_transmit(ifp, m); 4100 IFQ_DEQUEUE_NOLOCK(ifq, m); 4101 } 4102 IFQ_UNLOCK(ifq); 4103 } 4104 4105 static int 4106 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4107 { 4108 int err; 4109 4110 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4111 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4112 if (err == 0) 4113 iflib_altq_if_start(ifp); 4114 } else 4115 err = iflib_if_transmit(ifp, m); 4116 4117 return (err); 4118 } 4119 #endif /* ALTQ */ 4120 4121 static void 4122 iflib_if_qflush(if_t ifp) 4123 { 4124 if_ctx_t ctx = if_getsoftc(ifp); 4125 iflib_txq_t txq = ctx->ifc_txqs; 4126 int i; 4127 4128 STATE_LOCK(ctx); 4129 ctx->ifc_flags |= IFC_QFLUSH; 4130 STATE_UNLOCK(ctx); 4131 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4132 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4133 iflib_txq_check_drain(txq, 0); 4134 STATE_LOCK(ctx); 4135 ctx->ifc_flags &= ~IFC_QFLUSH; 4136 STATE_UNLOCK(ctx); 4137 4138 /* 4139 * When ALTQ is enabled, this will also take care of purging the 4140 * ALTQ queue(s). 4141 */ 4142 if_qflush(ifp); 4143 } 4144 4145 4146 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4147 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4148 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4149 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4150 4151 static int 4152 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4153 { 4154 if_ctx_t ctx = if_getsoftc(ifp); 4155 struct ifreq *ifr = (struct ifreq *)data; 4156 #if defined(INET) || defined(INET6) 4157 struct ifaddr *ifa = (struct ifaddr *)data; 4158 #endif 4159 bool avoid_reset = false; 4160 int err = 0, reinit = 0, bits; 4161 4162 switch (command) { 4163 case SIOCSIFADDR: 4164 #ifdef INET 4165 if (ifa->ifa_addr->sa_family == AF_INET) 4166 avoid_reset = true; 4167 #endif 4168 #ifdef INET6 4169 if (ifa->ifa_addr->sa_family == AF_INET6) 4170 avoid_reset = true; 4171 #endif 4172 /* 4173 ** Calling init results in link renegotiation, 4174 ** so we avoid doing it when possible. 4175 */ 4176 if (avoid_reset) { 4177 if_setflagbits(ifp, IFF_UP,0); 4178 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4179 reinit = 1; 4180 #ifdef INET 4181 if (!(if_getflags(ifp) & IFF_NOARP)) 4182 arp_ifinit(ifp, ifa); 4183 #endif 4184 } else 4185 err = ether_ioctl(ifp, command, data); 4186 break; 4187 case SIOCSIFMTU: 4188 CTX_LOCK(ctx); 4189 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4190 CTX_UNLOCK(ctx); 4191 break; 4192 } 4193 bits = if_getdrvflags(ifp); 4194 /* stop the driver and free any clusters before proceeding */ 4195 iflib_stop(ctx); 4196 4197 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4198 STATE_LOCK(ctx); 4199 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4200 ctx->ifc_flags |= IFC_MULTISEG; 4201 else 4202 ctx->ifc_flags &= ~IFC_MULTISEG; 4203 STATE_UNLOCK(ctx); 4204 err = if_setmtu(ifp, ifr->ifr_mtu); 4205 } 4206 iflib_init_locked(ctx); 4207 STATE_LOCK(ctx); 4208 if_setdrvflags(ifp, bits); 4209 STATE_UNLOCK(ctx); 4210 CTX_UNLOCK(ctx); 4211 break; 4212 case SIOCSIFFLAGS: 4213 CTX_LOCK(ctx); 4214 if (if_getflags(ifp) & IFF_UP) { 4215 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4216 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4217 (IFF_PROMISC | IFF_ALLMULTI)) { 4218 CTX_UNLOCK(ctx); 4219 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4220 CTX_LOCK(ctx); 4221 } 4222 } else 4223 reinit = 1; 4224 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4225 iflib_stop(ctx); 4226 } 4227 ctx->ifc_if_flags = if_getflags(ifp); 4228 CTX_UNLOCK(ctx); 4229 break; 4230 case SIOCADDMULTI: 4231 case SIOCDELMULTI: 4232 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4233 CTX_LOCK(ctx); 4234 IFDI_INTR_DISABLE(ctx); 4235 IFDI_MULTI_SET(ctx); 4236 IFDI_INTR_ENABLE(ctx); 4237 CTX_UNLOCK(ctx); 4238 } 4239 break; 4240 case SIOCSIFMEDIA: 4241 CTX_LOCK(ctx); 4242 IFDI_MEDIA_SET(ctx); 4243 CTX_UNLOCK(ctx); 4244 /* FALLTHROUGH */ 4245 case SIOCGIFMEDIA: 4246 case SIOCGIFXMEDIA: 4247 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4248 break; 4249 case SIOCGI2C: 4250 { 4251 struct ifi2creq i2c; 4252 4253 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4254 if (err != 0) 4255 break; 4256 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4257 err = EINVAL; 4258 break; 4259 } 4260 if (i2c.len > sizeof(i2c.data)) { 4261 err = EINVAL; 4262 break; 4263 } 4264 4265 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4266 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4267 sizeof(i2c)); 4268 break; 4269 } 4270 case SIOCSIFCAP: 4271 { 4272 int mask, setmask, oldmask; 4273 4274 oldmask = if_getcapenable(ifp); 4275 mask = ifr->ifr_reqcap ^ oldmask; 4276 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4277 setmask = 0; 4278 #ifdef TCP_OFFLOAD 4279 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4280 #endif 4281 setmask |= (mask & IFCAP_FLAGS); 4282 setmask |= (mask & IFCAP_WOL); 4283 4284 /* 4285 * If any RX csum has changed, change all the ones that 4286 * are supported by the driver. 4287 */ 4288 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4289 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4290 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4291 } 4292 4293 /* 4294 * want to ensure that traffic has stopped before we change any of the flags 4295 */ 4296 if (setmask) { 4297 CTX_LOCK(ctx); 4298 bits = if_getdrvflags(ifp); 4299 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4300 iflib_stop(ctx); 4301 STATE_LOCK(ctx); 4302 if_togglecapenable(ifp, setmask); 4303 STATE_UNLOCK(ctx); 4304 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4305 iflib_init_locked(ctx); 4306 STATE_LOCK(ctx); 4307 if_setdrvflags(ifp, bits); 4308 STATE_UNLOCK(ctx); 4309 CTX_UNLOCK(ctx); 4310 } 4311 if_vlancap(ifp); 4312 break; 4313 } 4314 case SIOCGPRIVATE_0: 4315 case SIOCSDRVSPEC: 4316 case SIOCGDRVSPEC: 4317 CTX_LOCK(ctx); 4318 err = IFDI_PRIV_IOCTL(ctx, command, data); 4319 CTX_UNLOCK(ctx); 4320 break; 4321 default: 4322 err = ether_ioctl(ifp, command, data); 4323 break; 4324 } 4325 if (reinit) 4326 iflib_if_init(ctx); 4327 return (err); 4328 } 4329 4330 static uint64_t 4331 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4332 { 4333 if_ctx_t ctx = if_getsoftc(ifp); 4334 4335 return (IFDI_GET_COUNTER(ctx, cnt)); 4336 } 4337 4338 /********************************************************************* 4339 * 4340 * OTHER FUNCTIONS EXPORTED TO THE STACK 4341 * 4342 **********************************************************************/ 4343 4344 static void 4345 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4346 { 4347 if_ctx_t ctx = if_getsoftc(ifp); 4348 4349 if ((void *)ctx != arg) 4350 return; 4351 4352 if ((vtag == 0) || (vtag > 4095)) 4353 return; 4354 4355 if (iflib_in_detach(ctx)) 4356 return; 4357 4358 CTX_LOCK(ctx); 4359 /* Driver may need all untagged packets to be flushed */ 4360 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4361 iflib_stop(ctx); 4362 IFDI_VLAN_REGISTER(ctx, vtag); 4363 /* Re-init to load the changes, if required */ 4364 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4365 iflib_init_locked(ctx); 4366 CTX_UNLOCK(ctx); 4367 } 4368 4369 static void 4370 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4371 { 4372 if_ctx_t ctx = if_getsoftc(ifp); 4373 4374 if ((void *)ctx != arg) 4375 return; 4376 4377 if ((vtag == 0) || (vtag > 4095)) 4378 return; 4379 4380 CTX_LOCK(ctx); 4381 /* Driver may need all tagged packets to be flushed */ 4382 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4383 iflib_stop(ctx); 4384 IFDI_VLAN_UNREGISTER(ctx, vtag); 4385 /* Re-init to load the changes, if required */ 4386 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4387 iflib_init_locked(ctx); 4388 CTX_UNLOCK(ctx); 4389 } 4390 4391 static void 4392 iflib_led_func(void *arg, int onoff) 4393 { 4394 if_ctx_t ctx = arg; 4395 4396 CTX_LOCK(ctx); 4397 IFDI_LED_FUNC(ctx, onoff); 4398 CTX_UNLOCK(ctx); 4399 } 4400 4401 /********************************************************************* 4402 * 4403 * BUS FUNCTION DEFINITIONS 4404 * 4405 **********************************************************************/ 4406 4407 int 4408 iflib_device_probe(device_t dev) 4409 { 4410 const pci_vendor_info_t *ent; 4411 if_shared_ctx_t sctx; 4412 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4413 uint16_t pci_vendor_id; 4414 4415 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4416 return (ENOTSUP); 4417 4418 pci_vendor_id = pci_get_vendor(dev); 4419 pci_device_id = pci_get_device(dev); 4420 pci_subvendor_id = pci_get_subvendor(dev); 4421 pci_subdevice_id = pci_get_subdevice(dev); 4422 pci_rev_id = pci_get_revid(dev); 4423 if (sctx->isc_parse_devinfo != NULL) 4424 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4425 4426 ent = sctx->isc_vendor_info; 4427 while (ent->pvi_vendor_id != 0) { 4428 if (pci_vendor_id != ent->pvi_vendor_id) { 4429 ent++; 4430 continue; 4431 } 4432 if ((pci_device_id == ent->pvi_device_id) && 4433 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4434 (ent->pvi_subvendor_id == 0)) && 4435 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4436 (ent->pvi_subdevice_id == 0)) && 4437 ((pci_rev_id == ent->pvi_rev_id) || 4438 (ent->pvi_rev_id == 0))) { 4439 4440 device_set_desc_copy(dev, ent->pvi_name); 4441 /* this needs to be changed to zero if the bus probing code 4442 * ever stops re-probing on best match because the sctx 4443 * may have its values over written by register calls 4444 * in subsequent probes 4445 */ 4446 return (BUS_PROBE_DEFAULT); 4447 } 4448 ent++; 4449 } 4450 return (ENXIO); 4451 } 4452 4453 int 4454 iflib_device_probe_vendor(device_t dev) 4455 { 4456 int probe; 4457 4458 probe = iflib_device_probe(dev); 4459 if (probe == BUS_PROBE_DEFAULT) 4460 return (BUS_PROBE_VENDOR); 4461 else 4462 return (probe); 4463 } 4464 4465 static void 4466 iflib_reset_qvalues(if_ctx_t ctx) 4467 { 4468 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4469 if_shared_ctx_t sctx = ctx->ifc_sctx; 4470 device_t dev = ctx->ifc_dev; 4471 int i; 4472 4473 if (ctx->ifc_sysctl_ntxqs != 0) 4474 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4475 if (ctx->ifc_sysctl_nrxqs != 0) 4476 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4477 4478 for (i = 0; i < sctx->isc_ntxqs; i++) { 4479 if (ctx->ifc_sysctl_ntxds[i] != 0) 4480 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4481 else 4482 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4483 } 4484 4485 for (i = 0; i < sctx->isc_nrxqs; i++) { 4486 if (ctx->ifc_sysctl_nrxds[i] != 0) 4487 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4488 else 4489 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4490 } 4491 4492 for (i = 0; i < sctx->isc_nrxqs; i++) { 4493 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4494 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4495 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4496 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4497 } 4498 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4499 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4500 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4501 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4502 } 4503 if (!powerof2(scctx->isc_nrxd[i])) { 4504 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4505 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4506 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4507 } 4508 } 4509 4510 for (i = 0; i < sctx->isc_ntxqs; i++) { 4511 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4512 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4513 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4514 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4515 } 4516 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4517 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4518 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4519 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4520 } 4521 if (!powerof2(scctx->isc_ntxd[i])) { 4522 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4523 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4524 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4525 } 4526 } 4527 } 4528 4529 static void 4530 iflib_add_pfil(if_ctx_t ctx) 4531 { 4532 struct pfil_head *pfil; 4533 struct pfil_head_args pa; 4534 iflib_rxq_t rxq; 4535 int i; 4536 4537 pa.pa_version = PFIL_VERSION; 4538 pa.pa_flags = PFIL_IN; 4539 pa.pa_type = PFIL_TYPE_ETHERNET; 4540 pa.pa_headname = ctx->ifc_ifp->if_xname; 4541 pfil = pfil_head_register(&pa); 4542 4543 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4544 rxq->pfil = pfil; 4545 } 4546 } 4547 4548 static void 4549 iflib_rem_pfil(if_ctx_t ctx) 4550 { 4551 struct pfil_head *pfil; 4552 iflib_rxq_t rxq; 4553 int i; 4554 4555 rxq = ctx->ifc_rxqs; 4556 pfil = rxq->pfil; 4557 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4558 rxq->pfil = NULL; 4559 } 4560 pfil_head_unregister(pfil); 4561 } 4562 4563 static uint16_t 4564 get_ctx_core_offset(if_ctx_t ctx) 4565 { 4566 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4567 struct cpu_offset *op; 4568 uint16_t qc; 4569 uint16_t ret = ctx->ifc_sysctl_core_offset; 4570 4571 if (ret != CORE_OFFSET_UNSPECIFIED) 4572 return (ret); 4573 4574 if (ctx->ifc_sysctl_separate_txrx) 4575 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4576 else 4577 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4578 4579 mtx_lock(&cpu_offset_mtx); 4580 SLIST_FOREACH(op, &cpu_offsets, entries) { 4581 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4582 ret = op->offset; 4583 op->offset += qc; 4584 MPASS(op->refcount < UINT_MAX); 4585 op->refcount++; 4586 break; 4587 } 4588 } 4589 if (ret == CORE_OFFSET_UNSPECIFIED) { 4590 ret = 0; 4591 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4592 M_NOWAIT | M_ZERO); 4593 if (op == NULL) { 4594 device_printf(ctx->ifc_dev, 4595 "allocation for cpu offset failed.\n"); 4596 } else { 4597 op->offset = qc; 4598 op->refcount = 1; 4599 CPU_COPY(&ctx->ifc_cpus, &op->set); 4600 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4601 } 4602 } 4603 mtx_unlock(&cpu_offset_mtx); 4604 4605 return (ret); 4606 } 4607 4608 static void 4609 unref_ctx_core_offset(if_ctx_t ctx) 4610 { 4611 struct cpu_offset *op, *top; 4612 4613 mtx_lock(&cpu_offset_mtx); 4614 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4615 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4616 MPASS(op->refcount > 0); 4617 op->refcount--; 4618 if (op->refcount == 0) { 4619 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4620 free(op, M_IFLIB); 4621 } 4622 break; 4623 } 4624 } 4625 mtx_unlock(&cpu_offset_mtx); 4626 } 4627 4628 int 4629 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4630 { 4631 if_ctx_t ctx; 4632 if_t ifp; 4633 if_softc_ctx_t scctx; 4634 kobjop_desc_t kobj_desc; 4635 kobj_method_t *kobj_method; 4636 int err, msix, rid; 4637 int num_txd, num_rxd; 4638 4639 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4640 4641 if (sc == NULL) { 4642 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4643 device_set_softc(dev, ctx); 4644 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4645 } 4646 4647 ctx->ifc_sctx = sctx; 4648 ctx->ifc_dev = dev; 4649 ctx->ifc_softc = sc; 4650 4651 if ((err = iflib_register(ctx)) != 0) { 4652 device_printf(dev, "iflib_register failed %d\n", err); 4653 goto fail_ctx_free; 4654 } 4655 iflib_add_device_sysctl_pre(ctx); 4656 4657 scctx = &ctx->ifc_softc_ctx; 4658 ifp = ctx->ifc_ifp; 4659 4660 iflib_reset_qvalues(ctx); 4661 CTX_LOCK(ctx); 4662 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4663 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4664 goto fail_unlock; 4665 } 4666 _iflib_pre_assert(scctx); 4667 ctx->ifc_txrx = *scctx->isc_txrx; 4668 4669 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4670 ctx->ifc_mediap = scctx->isc_media; 4671 4672 #ifdef INVARIANTS 4673 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4674 MPASS(scctx->isc_tx_csum_flags); 4675 #endif 4676 4677 if_setcapabilities(ifp, 4678 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4679 if_setcapenable(ifp, 4680 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4681 4682 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4683 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4684 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4685 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4686 4687 num_txd = iflib_num_tx_descs(ctx); 4688 num_rxd = iflib_num_rx_descs(ctx); 4689 4690 /* XXX change for per-queue sizes */ 4691 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4692 num_txd, num_rxd); 4693 4694 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4695 scctx->isc_tx_nsegments = max(1, num_txd / 4696 MAX_SINGLE_PACKET_FRACTION); 4697 if (scctx->isc_tx_tso_segments_max > num_txd / 4698 MAX_SINGLE_PACKET_FRACTION) 4699 scctx->isc_tx_tso_segments_max = max(1, 4700 num_txd / MAX_SINGLE_PACKET_FRACTION); 4701 4702 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4703 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4704 /* 4705 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4706 * but some MACs do. 4707 */ 4708 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4709 IP_MAXPACKET)); 4710 /* 4711 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4712 * into account. In the worst case, each of these calls will 4713 * add another mbuf and, thus, the requirement for another DMA 4714 * segment. So for best performance, it doesn't make sense to 4715 * advertize a maximum of TSO segments that typically will 4716 * require defragmentation in iflib_encap(). 4717 */ 4718 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4719 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4720 } 4721 if (scctx->isc_rss_table_size == 0) 4722 scctx->isc_rss_table_size = 64; 4723 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4724 4725 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4726 /* XXX format name */ 4727 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4728 NULL, NULL, "admin"); 4729 4730 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4731 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4732 device_printf(dev, "Unable to fetch CPU list\n"); 4733 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4734 } 4735 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4736 4737 /* 4738 ** Now set up MSI or MSI-X, should return us the number of supported 4739 ** vectors (will be 1 for a legacy interrupt and MSI). 4740 */ 4741 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4742 msix = scctx->isc_vectors; 4743 } else if (scctx->isc_msix_bar != 0) 4744 /* 4745 * The simple fact that isc_msix_bar is not 0 does not mean we 4746 * we have a good value there that is known to work. 4747 */ 4748 msix = iflib_msix_init(ctx); 4749 else { 4750 scctx->isc_vectors = 1; 4751 scctx->isc_ntxqsets = 1; 4752 scctx->isc_nrxqsets = 1; 4753 scctx->isc_intr = IFLIB_INTR_LEGACY; 4754 msix = 0; 4755 } 4756 /* Get memory for the station queues */ 4757 if ((err = iflib_queues_alloc(ctx))) { 4758 device_printf(dev, "Unable to allocate queue memory\n"); 4759 goto fail_intr_free; 4760 } 4761 4762 if ((err = iflib_qset_structures_setup(ctx))) 4763 goto fail_queues; 4764 4765 /* 4766 * Now that we know how many queues there are, get the core offset. 4767 */ 4768 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4769 4770 if (msix > 1) { 4771 /* 4772 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4773 * aren't the default NULL implementation. 4774 */ 4775 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4776 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4777 kobj_desc); 4778 if (kobj_method == &kobj_desc->deflt) { 4779 device_printf(dev, 4780 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4781 err = EOPNOTSUPP; 4782 goto fail_queues; 4783 } 4784 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4785 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4786 kobj_desc); 4787 if (kobj_method == &kobj_desc->deflt) { 4788 device_printf(dev, 4789 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4790 err = EOPNOTSUPP; 4791 goto fail_queues; 4792 } 4793 4794 /* 4795 * Assign the MSI-X vectors. 4796 * Note that the default NULL ifdi_msix_intr_assign method will 4797 * fail here, too. 4798 */ 4799 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4800 if (err != 0) { 4801 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4802 err); 4803 goto fail_queues; 4804 } 4805 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4806 rid = 0; 4807 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4808 MPASS(msix == 1); 4809 rid = 1; 4810 } 4811 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4812 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4813 goto fail_queues; 4814 } 4815 } else { 4816 device_printf(dev, 4817 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4818 err = ENODEV; 4819 goto fail_intr_free; 4820 } 4821 4822 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4823 4824 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4825 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4826 goto fail_detach; 4827 } 4828 4829 /* 4830 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4831 * This must appear after the call to ether_ifattach() because 4832 * ether_ifattach() sets if_hdrlen to the default value. 4833 */ 4834 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4835 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4836 4837 if ((err = iflib_netmap_attach(ctx))) { 4838 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4839 goto fail_detach; 4840 } 4841 *ctxp = ctx; 4842 4843 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4844 4845 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4846 iflib_add_device_sysctl_post(ctx); 4847 iflib_add_pfil(ctx); 4848 ctx->ifc_flags |= IFC_INIT_DONE; 4849 CTX_UNLOCK(ctx); 4850 4851 return (0); 4852 4853 fail_detach: 4854 ether_ifdetach(ctx->ifc_ifp); 4855 fail_intr_free: 4856 iflib_free_intr_mem(ctx); 4857 fail_queues: 4858 iflib_tx_structures_free(ctx); 4859 iflib_rx_structures_free(ctx); 4860 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4861 IFDI_DETACH(ctx); 4862 fail_unlock: 4863 CTX_UNLOCK(ctx); 4864 iflib_deregister(ctx); 4865 fail_ctx_free: 4866 device_set_softc(ctx->ifc_dev, NULL); 4867 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4868 free(ctx->ifc_softc, M_IFLIB); 4869 free(ctx, M_IFLIB); 4870 return (err); 4871 } 4872 4873 int 4874 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4875 struct iflib_cloneattach_ctx *clctx) 4876 { 4877 int num_txd, num_rxd; 4878 int err; 4879 if_ctx_t ctx; 4880 if_t ifp; 4881 if_softc_ctx_t scctx; 4882 int i; 4883 void *sc; 4884 4885 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4886 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4887 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4888 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4889 ctx->ifc_flags |= IFC_PSEUDO; 4890 4891 ctx->ifc_sctx = sctx; 4892 ctx->ifc_softc = sc; 4893 ctx->ifc_dev = dev; 4894 4895 if ((err = iflib_register(ctx)) != 0) { 4896 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4897 goto fail_ctx_free; 4898 } 4899 iflib_add_device_sysctl_pre(ctx); 4900 4901 scctx = &ctx->ifc_softc_ctx; 4902 ifp = ctx->ifc_ifp; 4903 4904 iflib_reset_qvalues(ctx); 4905 CTX_LOCK(ctx); 4906 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4907 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4908 goto fail_unlock; 4909 } 4910 if (sctx->isc_flags & IFLIB_GEN_MAC) 4911 ether_gen_addr(ifp, &ctx->ifc_mac); 4912 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4913 clctx->cc_params)) != 0) { 4914 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4915 goto fail_unlock; 4916 } 4917 #ifdef INVARIANTS 4918 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4919 MPASS(scctx->isc_tx_csum_flags); 4920 #endif 4921 4922 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4923 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4924 4925 ifp->if_flags |= IFF_NOGROUP; 4926 if (sctx->isc_flags & IFLIB_PSEUDO) { 4927 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4928 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4929 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4930 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4931 } else { 4932 if_attach(ctx->ifc_ifp); 4933 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4934 } 4935 4936 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4937 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4938 goto fail_detach; 4939 } 4940 *ctxp = ctx; 4941 4942 /* 4943 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4944 * This must appear after the call to ether_ifattach() because 4945 * ether_ifattach() sets if_hdrlen to the default value. 4946 */ 4947 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4948 if_setifheaderlen(ifp, 4949 sizeof(struct ether_vlan_header)); 4950 4951 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4952 iflib_add_device_sysctl_post(ctx); 4953 ctx->ifc_flags |= IFC_INIT_DONE; 4954 CTX_UNLOCK(ctx); 4955 return (0); 4956 } 4957 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4958 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4959 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4960 4961 _iflib_pre_assert(scctx); 4962 ctx->ifc_txrx = *scctx->isc_txrx; 4963 4964 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4965 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4966 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4967 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4968 4969 num_txd = iflib_num_tx_descs(ctx); 4970 num_rxd = iflib_num_rx_descs(ctx); 4971 4972 /* XXX change for per-queue sizes */ 4973 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4974 num_txd, num_rxd); 4975 4976 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4977 scctx->isc_tx_nsegments = max(1, num_txd / 4978 MAX_SINGLE_PACKET_FRACTION); 4979 if (scctx->isc_tx_tso_segments_max > num_txd / 4980 MAX_SINGLE_PACKET_FRACTION) 4981 scctx->isc_tx_tso_segments_max = max(1, 4982 num_txd / MAX_SINGLE_PACKET_FRACTION); 4983 4984 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4985 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4986 /* 4987 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4988 * but some MACs do. 4989 */ 4990 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4991 IP_MAXPACKET)); 4992 /* 4993 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4994 * into account. In the worst case, each of these calls will 4995 * add another mbuf and, thus, the requirement for another DMA 4996 * segment. So for best performance, it doesn't make sense to 4997 * advertize a maximum of TSO segments that typically will 4998 * require defragmentation in iflib_encap(). 4999 */ 5000 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5001 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5002 } 5003 if (scctx->isc_rss_table_size == 0) 5004 scctx->isc_rss_table_size = 64; 5005 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5006 5007 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5008 /* XXX format name */ 5009 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5010 NULL, NULL, "admin"); 5011 5012 /* XXX --- can support > 1 -- but keep it simple for now */ 5013 scctx->isc_intr = IFLIB_INTR_LEGACY; 5014 5015 /* Get memory for the station queues */ 5016 if ((err = iflib_queues_alloc(ctx))) { 5017 device_printf(dev, "Unable to allocate queue memory\n"); 5018 goto fail_iflib_detach; 5019 } 5020 5021 if ((err = iflib_qset_structures_setup(ctx))) { 5022 device_printf(dev, "qset structure setup failed %d\n", err); 5023 goto fail_queues; 5024 } 5025 5026 /* 5027 * XXX What if anything do we want to do about interrupts? 5028 */ 5029 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5030 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5031 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5032 goto fail_detach; 5033 } 5034 5035 /* 5036 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5037 * This must appear after the call to ether_ifattach() because 5038 * ether_ifattach() sets if_hdrlen to the default value. 5039 */ 5040 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5041 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5042 5043 /* XXX handle more than one queue */ 5044 for (i = 0; i < scctx->isc_nrxqsets; i++) 5045 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5046 5047 *ctxp = ctx; 5048 5049 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5050 iflib_add_device_sysctl_post(ctx); 5051 ctx->ifc_flags |= IFC_INIT_DONE; 5052 CTX_UNLOCK(ctx); 5053 5054 return (0); 5055 fail_detach: 5056 ether_ifdetach(ctx->ifc_ifp); 5057 fail_queues: 5058 iflib_tx_structures_free(ctx); 5059 iflib_rx_structures_free(ctx); 5060 fail_iflib_detach: 5061 IFDI_DETACH(ctx); 5062 fail_unlock: 5063 CTX_UNLOCK(ctx); 5064 iflib_deregister(ctx); 5065 fail_ctx_free: 5066 free(ctx->ifc_softc, M_IFLIB); 5067 free(ctx, M_IFLIB); 5068 return (err); 5069 } 5070 5071 int 5072 iflib_pseudo_deregister(if_ctx_t ctx) 5073 { 5074 if_t ifp = ctx->ifc_ifp; 5075 if_shared_ctx_t sctx = ctx->ifc_sctx; 5076 iflib_txq_t txq; 5077 iflib_rxq_t rxq; 5078 int i, j; 5079 struct taskqgroup *tqg; 5080 iflib_fl_t fl; 5081 5082 /* Unregister VLAN event handlers early */ 5083 iflib_unregister_vlan_handlers(ctx); 5084 5085 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5086 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5087 bpfdetach(ifp); 5088 if_detach(ifp); 5089 } else { 5090 ether_ifdetach(ifp); 5091 } 5092 /* XXX drain any dependent tasks */ 5093 tqg = qgroup_if_io_tqg; 5094 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5095 callout_drain(&txq->ift_timer); 5096 if (txq->ift_task.gt_uniq != NULL) 5097 taskqgroup_detach(tqg, &txq->ift_task); 5098 } 5099 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5100 callout_drain(&rxq->ifr_watchdog); 5101 if (rxq->ifr_task.gt_uniq != NULL) 5102 taskqgroup_detach(tqg, &rxq->ifr_task); 5103 5104 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5105 free(fl->ifl_rx_bitmap, M_IFLIB); 5106 } 5107 tqg = qgroup_if_config_tqg; 5108 if (ctx->ifc_admin_task.gt_uniq != NULL) 5109 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5110 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5111 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5112 5113 iflib_tx_structures_free(ctx); 5114 iflib_rx_structures_free(ctx); 5115 5116 iflib_deregister(ctx); 5117 5118 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5119 free(ctx->ifc_softc, M_IFLIB); 5120 free(ctx, M_IFLIB); 5121 return (0); 5122 } 5123 5124 int 5125 iflib_device_attach(device_t dev) 5126 { 5127 if_ctx_t ctx; 5128 if_shared_ctx_t sctx; 5129 5130 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5131 return (ENOTSUP); 5132 5133 pci_enable_busmaster(dev); 5134 5135 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5136 } 5137 5138 int 5139 iflib_device_deregister(if_ctx_t ctx) 5140 { 5141 if_t ifp = ctx->ifc_ifp; 5142 iflib_txq_t txq; 5143 iflib_rxq_t rxq; 5144 device_t dev = ctx->ifc_dev; 5145 int i, j; 5146 struct taskqgroup *tqg; 5147 iflib_fl_t fl; 5148 5149 /* Make sure VLANS are not using driver */ 5150 if (if_vlantrunkinuse(ifp)) { 5151 device_printf(dev, "Vlan in use, detach first\n"); 5152 return (EBUSY); 5153 } 5154 #ifdef PCI_IOV 5155 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5156 device_printf(dev, "SR-IOV in use; detach first.\n"); 5157 return (EBUSY); 5158 } 5159 #endif 5160 5161 STATE_LOCK(ctx); 5162 ctx->ifc_flags |= IFC_IN_DETACH; 5163 STATE_UNLOCK(ctx); 5164 5165 /* Unregister VLAN handlers before calling iflib_stop() */ 5166 iflib_unregister_vlan_handlers(ctx); 5167 5168 iflib_netmap_detach(ifp); 5169 ether_ifdetach(ifp); 5170 5171 CTX_LOCK(ctx); 5172 iflib_stop(ctx); 5173 CTX_UNLOCK(ctx); 5174 5175 iflib_rem_pfil(ctx); 5176 if (ctx->ifc_led_dev != NULL) 5177 led_destroy(ctx->ifc_led_dev); 5178 /* XXX drain any dependent tasks */ 5179 tqg = qgroup_if_io_tqg; 5180 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5181 callout_drain(&txq->ift_timer); 5182 if (txq->ift_task.gt_uniq != NULL) 5183 taskqgroup_detach(tqg, &txq->ift_task); 5184 } 5185 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5186 if (rxq->ifr_task.gt_uniq != NULL) 5187 taskqgroup_detach(tqg, &rxq->ifr_task); 5188 5189 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5190 free(fl->ifl_rx_bitmap, M_IFLIB); 5191 } 5192 tqg = qgroup_if_config_tqg; 5193 if (ctx->ifc_admin_task.gt_uniq != NULL) 5194 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5195 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5196 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5197 CTX_LOCK(ctx); 5198 IFDI_DETACH(ctx); 5199 CTX_UNLOCK(ctx); 5200 5201 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5202 iflib_free_intr_mem(ctx); 5203 5204 bus_generic_detach(dev); 5205 5206 iflib_tx_structures_free(ctx); 5207 iflib_rx_structures_free(ctx); 5208 5209 iflib_deregister(ctx); 5210 5211 device_set_softc(ctx->ifc_dev, NULL); 5212 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5213 free(ctx->ifc_softc, M_IFLIB); 5214 unref_ctx_core_offset(ctx); 5215 free(ctx, M_IFLIB); 5216 return (0); 5217 } 5218 5219 static void 5220 iflib_free_intr_mem(if_ctx_t ctx) 5221 { 5222 5223 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5224 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5225 } 5226 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5227 pci_release_msi(ctx->ifc_dev); 5228 } 5229 if (ctx->ifc_msix_mem != NULL) { 5230 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5231 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5232 ctx->ifc_msix_mem = NULL; 5233 } 5234 } 5235 5236 int 5237 iflib_device_detach(device_t dev) 5238 { 5239 if_ctx_t ctx = device_get_softc(dev); 5240 5241 return (iflib_device_deregister(ctx)); 5242 } 5243 5244 int 5245 iflib_device_suspend(device_t dev) 5246 { 5247 if_ctx_t ctx = device_get_softc(dev); 5248 5249 CTX_LOCK(ctx); 5250 IFDI_SUSPEND(ctx); 5251 CTX_UNLOCK(ctx); 5252 5253 return bus_generic_suspend(dev); 5254 } 5255 int 5256 iflib_device_shutdown(device_t dev) 5257 { 5258 if_ctx_t ctx = device_get_softc(dev); 5259 5260 CTX_LOCK(ctx); 5261 IFDI_SHUTDOWN(ctx); 5262 CTX_UNLOCK(ctx); 5263 5264 return bus_generic_suspend(dev); 5265 } 5266 5267 5268 int 5269 iflib_device_resume(device_t dev) 5270 { 5271 if_ctx_t ctx = device_get_softc(dev); 5272 iflib_txq_t txq = ctx->ifc_txqs; 5273 5274 CTX_LOCK(ctx); 5275 IFDI_RESUME(ctx); 5276 iflib_if_init_locked(ctx); 5277 CTX_UNLOCK(ctx); 5278 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5279 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5280 5281 return (bus_generic_resume(dev)); 5282 } 5283 5284 int 5285 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5286 { 5287 int error; 5288 if_ctx_t ctx = device_get_softc(dev); 5289 5290 CTX_LOCK(ctx); 5291 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5292 CTX_UNLOCK(ctx); 5293 5294 return (error); 5295 } 5296 5297 void 5298 iflib_device_iov_uninit(device_t dev) 5299 { 5300 if_ctx_t ctx = device_get_softc(dev); 5301 5302 CTX_LOCK(ctx); 5303 IFDI_IOV_UNINIT(ctx); 5304 CTX_UNLOCK(ctx); 5305 } 5306 5307 int 5308 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5309 { 5310 int error; 5311 if_ctx_t ctx = device_get_softc(dev); 5312 5313 CTX_LOCK(ctx); 5314 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5315 CTX_UNLOCK(ctx); 5316 5317 return (error); 5318 } 5319 5320 /********************************************************************* 5321 * 5322 * MODULE FUNCTION DEFINITIONS 5323 * 5324 **********************************************************************/ 5325 5326 /* 5327 * - Start a fast taskqueue thread for each core 5328 * - Start a taskqueue for control operations 5329 */ 5330 static int 5331 iflib_module_init(void) 5332 { 5333 return (0); 5334 } 5335 5336 static int 5337 iflib_module_event_handler(module_t mod, int what, void *arg) 5338 { 5339 int err; 5340 5341 switch (what) { 5342 case MOD_LOAD: 5343 if ((err = iflib_module_init()) != 0) 5344 return (err); 5345 break; 5346 case MOD_UNLOAD: 5347 return (EBUSY); 5348 default: 5349 return (EOPNOTSUPP); 5350 } 5351 5352 return (0); 5353 } 5354 5355 /********************************************************************* 5356 * 5357 * PUBLIC FUNCTION DEFINITIONS 5358 * ordered as in iflib.h 5359 * 5360 **********************************************************************/ 5361 5362 5363 static void 5364 _iflib_assert(if_shared_ctx_t sctx) 5365 { 5366 int i; 5367 5368 MPASS(sctx->isc_tx_maxsize); 5369 MPASS(sctx->isc_tx_maxsegsize); 5370 5371 MPASS(sctx->isc_rx_maxsize); 5372 MPASS(sctx->isc_rx_nsegments); 5373 MPASS(sctx->isc_rx_maxsegsize); 5374 5375 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5376 for (i = 0; i < sctx->isc_nrxqs; i++) { 5377 MPASS(sctx->isc_nrxd_min[i]); 5378 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5379 MPASS(sctx->isc_nrxd_max[i]); 5380 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5381 MPASS(sctx->isc_nrxd_default[i]); 5382 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5383 } 5384 5385 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5386 for (i = 0; i < sctx->isc_ntxqs; i++) { 5387 MPASS(sctx->isc_ntxd_min[i]); 5388 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5389 MPASS(sctx->isc_ntxd_max[i]); 5390 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5391 MPASS(sctx->isc_ntxd_default[i]); 5392 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5393 } 5394 } 5395 5396 static void 5397 _iflib_pre_assert(if_softc_ctx_t scctx) 5398 { 5399 5400 MPASS(scctx->isc_txrx->ift_txd_encap); 5401 MPASS(scctx->isc_txrx->ift_txd_flush); 5402 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5403 MPASS(scctx->isc_txrx->ift_rxd_available); 5404 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5405 MPASS(scctx->isc_txrx->ift_rxd_refill); 5406 MPASS(scctx->isc_txrx->ift_rxd_flush); 5407 } 5408 5409 static int 5410 iflib_register(if_ctx_t ctx) 5411 { 5412 if_shared_ctx_t sctx = ctx->ifc_sctx; 5413 driver_t *driver = sctx->isc_driver; 5414 device_t dev = ctx->ifc_dev; 5415 if_t ifp; 5416 u_char type; 5417 int iflags; 5418 5419 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5420 _iflib_assert(sctx); 5421 5422 CTX_LOCK_INIT(ctx); 5423 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5424 if (sctx->isc_flags & IFLIB_PSEUDO) { 5425 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5426 type = IFT_ETHER; 5427 else 5428 type = IFT_PPP; 5429 } else 5430 type = IFT_ETHER; 5431 ifp = ctx->ifc_ifp = if_alloc(type); 5432 if (ifp == NULL) { 5433 device_printf(dev, "can not allocate ifnet structure\n"); 5434 return (ENOMEM); 5435 } 5436 5437 /* 5438 * Initialize our context's device specific methods 5439 */ 5440 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5441 kobj_class_compile((kobj_class_t) driver); 5442 5443 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5444 if_setsoftc(ifp, ctx); 5445 if_setdev(ifp, dev); 5446 if_setinitfn(ifp, iflib_if_init); 5447 if_setioctlfn(ifp, iflib_if_ioctl); 5448 #ifdef ALTQ 5449 if_setstartfn(ifp, iflib_altq_if_start); 5450 if_settransmitfn(ifp, iflib_altq_if_transmit); 5451 if_setsendqready(ifp); 5452 #else 5453 if_settransmitfn(ifp, iflib_if_transmit); 5454 #endif 5455 if_setqflushfn(ifp, iflib_if_qflush); 5456 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5457 5458 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5459 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5460 iflags |= IFF_POINTOPOINT; 5461 else 5462 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5463 if_setflags(ifp, iflags); 5464 ctx->ifc_vlan_attach_event = 5465 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5466 EVENTHANDLER_PRI_FIRST); 5467 ctx->ifc_vlan_detach_event = 5468 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5469 EVENTHANDLER_PRI_FIRST); 5470 5471 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5472 ctx->ifc_mediap = &ctx->ifc_media; 5473 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5474 iflib_media_change, iflib_media_status); 5475 } 5476 return (0); 5477 } 5478 5479 static void 5480 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5481 { 5482 /* Unregister VLAN events */ 5483 if (ctx->ifc_vlan_attach_event != NULL) { 5484 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5485 ctx->ifc_vlan_attach_event = NULL; 5486 } 5487 if (ctx->ifc_vlan_detach_event != NULL) { 5488 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5489 ctx->ifc_vlan_detach_event = NULL; 5490 } 5491 5492 } 5493 5494 static void 5495 iflib_deregister(if_ctx_t ctx) 5496 { 5497 if_t ifp = ctx->ifc_ifp; 5498 5499 /* Remove all media */ 5500 ifmedia_removeall(&ctx->ifc_media); 5501 5502 /* Ensure that VLAN event handlers are unregistered */ 5503 iflib_unregister_vlan_handlers(ctx); 5504 5505 /* Release kobject reference */ 5506 kobj_delete((kobj_t) ctx, NULL); 5507 5508 /* Free the ifnet structure */ 5509 if_free(ifp); 5510 5511 STATE_LOCK_DESTROY(ctx); 5512 5513 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5514 CTX_LOCK_DESTROY(ctx); 5515 } 5516 5517 static int 5518 iflib_queues_alloc(if_ctx_t ctx) 5519 { 5520 if_shared_ctx_t sctx = ctx->ifc_sctx; 5521 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5522 device_t dev = ctx->ifc_dev; 5523 int nrxqsets = scctx->isc_nrxqsets; 5524 int ntxqsets = scctx->isc_ntxqsets; 5525 iflib_txq_t txq; 5526 iflib_rxq_t rxq; 5527 iflib_fl_t fl = NULL; 5528 int i, j, cpu, err, txconf, rxconf; 5529 iflib_dma_info_t ifdip; 5530 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5531 uint32_t *txqsizes = scctx->isc_txqsizes; 5532 uint8_t nrxqs = sctx->isc_nrxqs; 5533 uint8_t ntxqs = sctx->isc_ntxqs; 5534 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5535 caddr_t *vaddrs; 5536 uint64_t *paddrs; 5537 5538 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5539 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5540 5541 /* Allocate the TX ring struct memory */ 5542 if (!(ctx->ifc_txqs = 5543 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5544 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5545 device_printf(dev, "Unable to allocate TX ring memory\n"); 5546 err = ENOMEM; 5547 goto fail; 5548 } 5549 5550 /* Now allocate the RX */ 5551 if (!(ctx->ifc_rxqs = 5552 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5553 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5554 device_printf(dev, "Unable to allocate RX ring memory\n"); 5555 err = ENOMEM; 5556 goto rx_fail; 5557 } 5558 5559 txq = ctx->ifc_txqs; 5560 rxq = ctx->ifc_rxqs; 5561 5562 /* 5563 * XXX handle allocation failure 5564 */ 5565 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5566 /* Set up some basics */ 5567 5568 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5569 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5570 device_printf(dev, 5571 "Unable to allocate TX DMA info memory\n"); 5572 err = ENOMEM; 5573 goto err_tx_desc; 5574 } 5575 txq->ift_ifdi = ifdip; 5576 for (j = 0; j < ntxqs; j++, ifdip++) { 5577 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5578 device_printf(dev, 5579 "Unable to allocate TX descriptors\n"); 5580 err = ENOMEM; 5581 goto err_tx_desc; 5582 } 5583 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5584 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5585 } 5586 txq->ift_ctx = ctx; 5587 txq->ift_id = i; 5588 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5589 txq->ift_br_offset = 1; 5590 } else { 5591 txq->ift_br_offset = 0; 5592 } 5593 /* XXX fix this */ 5594 txq->ift_timer.c_cpu = cpu; 5595 5596 if (iflib_txsd_alloc(txq)) { 5597 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5598 err = ENOMEM; 5599 goto err_tx_desc; 5600 } 5601 5602 /* Initialize the TX lock */ 5603 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5604 device_get_nameunit(dev), txq->ift_id); 5605 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5606 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5607 5608 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5609 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5610 if (err) { 5611 /* XXX free any allocated rings */ 5612 device_printf(dev, "Unable to allocate buf_ring\n"); 5613 goto err_tx_desc; 5614 } 5615 } 5616 5617 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5618 /* Set up some basics */ 5619 callout_init(&rxq->ifr_watchdog, 1); 5620 5621 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5622 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5623 device_printf(dev, 5624 "Unable to allocate RX DMA info memory\n"); 5625 err = ENOMEM; 5626 goto err_tx_desc; 5627 } 5628 5629 rxq->ifr_ifdi = ifdip; 5630 /* XXX this needs to be changed if #rx queues != #tx queues */ 5631 rxq->ifr_ntxqirq = 1; 5632 rxq->ifr_txqid[0] = i; 5633 for (j = 0; j < nrxqs; j++, ifdip++) { 5634 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5635 device_printf(dev, 5636 "Unable to allocate RX descriptors\n"); 5637 err = ENOMEM; 5638 goto err_tx_desc; 5639 } 5640 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5641 } 5642 rxq->ifr_ctx = ctx; 5643 rxq->ifr_id = i; 5644 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5645 rxq->ifr_fl_offset = 1; 5646 } else { 5647 rxq->ifr_fl_offset = 0; 5648 } 5649 rxq->ifr_nfl = nfree_lists; 5650 if (!(fl = 5651 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5652 device_printf(dev, "Unable to allocate free list memory\n"); 5653 err = ENOMEM; 5654 goto err_tx_desc; 5655 } 5656 rxq->ifr_fl = fl; 5657 for (j = 0; j < nfree_lists; j++) { 5658 fl[j].ifl_rxq = rxq; 5659 fl[j].ifl_id = j; 5660 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5661 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5662 } 5663 /* Allocate receive buffers for the ring */ 5664 if (iflib_rxsd_alloc(rxq)) { 5665 device_printf(dev, 5666 "Critical Failure setting up receive buffers\n"); 5667 err = ENOMEM; 5668 goto err_rx_desc; 5669 } 5670 5671 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5672 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5673 M_WAITOK); 5674 } 5675 5676 /* TXQs */ 5677 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5678 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5679 for (i = 0; i < ntxqsets; i++) { 5680 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5681 5682 for (j = 0; j < ntxqs; j++, di++) { 5683 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5684 paddrs[i*ntxqs + j] = di->idi_paddr; 5685 } 5686 } 5687 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5688 device_printf(ctx->ifc_dev, 5689 "Unable to allocate device TX queue\n"); 5690 iflib_tx_structures_free(ctx); 5691 free(vaddrs, M_IFLIB); 5692 free(paddrs, M_IFLIB); 5693 goto err_rx_desc; 5694 } 5695 free(vaddrs, M_IFLIB); 5696 free(paddrs, M_IFLIB); 5697 5698 /* RXQs */ 5699 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5700 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5701 for (i = 0; i < nrxqsets; i++) { 5702 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5703 5704 for (j = 0; j < nrxqs; j++, di++) { 5705 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5706 paddrs[i*nrxqs + j] = di->idi_paddr; 5707 } 5708 } 5709 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5710 device_printf(ctx->ifc_dev, 5711 "Unable to allocate device RX queue\n"); 5712 iflib_tx_structures_free(ctx); 5713 free(vaddrs, M_IFLIB); 5714 free(paddrs, M_IFLIB); 5715 goto err_rx_desc; 5716 } 5717 free(vaddrs, M_IFLIB); 5718 free(paddrs, M_IFLIB); 5719 5720 return (0); 5721 5722 /* XXX handle allocation failure changes */ 5723 err_rx_desc: 5724 err_tx_desc: 5725 rx_fail: 5726 if (ctx->ifc_rxqs != NULL) 5727 free(ctx->ifc_rxqs, M_IFLIB); 5728 ctx->ifc_rxqs = NULL; 5729 if (ctx->ifc_txqs != NULL) 5730 free(ctx->ifc_txqs, M_IFLIB); 5731 ctx->ifc_txqs = NULL; 5732 fail: 5733 return (err); 5734 } 5735 5736 static int 5737 iflib_tx_structures_setup(if_ctx_t ctx) 5738 { 5739 iflib_txq_t txq = ctx->ifc_txqs; 5740 int i; 5741 5742 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5743 iflib_txq_setup(txq); 5744 5745 return (0); 5746 } 5747 5748 static void 5749 iflib_tx_structures_free(if_ctx_t ctx) 5750 { 5751 iflib_txq_t txq = ctx->ifc_txqs; 5752 if_shared_ctx_t sctx = ctx->ifc_sctx; 5753 int i, j; 5754 5755 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5756 for (j = 0; j < sctx->isc_ntxqs; j++) 5757 iflib_dma_free(&txq->ift_ifdi[j]); 5758 iflib_txq_destroy(txq); 5759 } 5760 free(ctx->ifc_txqs, M_IFLIB); 5761 ctx->ifc_txqs = NULL; 5762 IFDI_QUEUES_FREE(ctx); 5763 } 5764 5765 /********************************************************************* 5766 * 5767 * Initialize all receive rings. 5768 * 5769 **********************************************************************/ 5770 static int 5771 iflib_rx_structures_setup(if_ctx_t ctx) 5772 { 5773 iflib_rxq_t rxq = ctx->ifc_rxqs; 5774 int q; 5775 #if defined(INET6) || defined(INET) 5776 int err, i; 5777 #endif 5778 5779 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5780 #if defined(INET6) || defined(INET) 5781 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5782 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5783 TCP_LRO_ENTRIES, min(1024, 5784 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5785 if (err != 0) { 5786 device_printf(ctx->ifc_dev, 5787 "LRO Initialization failed!\n"); 5788 goto fail; 5789 } 5790 } 5791 #endif 5792 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5793 } 5794 return (0); 5795 #if defined(INET6) || defined(INET) 5796 fail: 5797 /* 5798 * Free LRO resources allocated so far, we will only handle 5799 * the rings that completed, the failing case will have 5800 * cleaned up for itself. 'q' failed, so its the terminus. 5801 */ 5802 rxq = ctx->ifc_rxqs; 5803 for (i = 0; i < q; ++i, rxq++) { 5804 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5805 tcp_lro_free(&rxq->ifr_lc); 5806 } 5807 return (err); 5808 #endif 5809 } 5810 5811 /********************************************************************* 5812 * 5813 * Free all receive rings. 5814 * 5815 **********************************************************************/ 5816 static void 5817 iflib_rx_structures_free(if_ctx_t ctx) 5818 { 5819 iflib_rxq_t rxq = ctx->ifc_rxqs; 5820 if_shared_ctx_t sctx = ctx->ifc_sctx; 5821 int i, j; 5822 5823 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5824 for (j = 0; j < sctx->isc_nrxqs; j++) 5825 iflib_dma_free(&rxq->ifr_ifdi[j]); 5826 iflib_rx_sds_free(rxq); 5827 #if defined(INET6) || defined(INET) 5828 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5829 tcp_lro_free(&rxq->ifr_lc); 5830 #endif 5831 } 5832 free(ctx->ifc_rxqs, M_IFLIB); 5833 ctx->ifc_rxqs = NULL; 5834 } 5835 5836 static int 5837 iflib_qset_structures_setup(if_ctx_t ctx) 5838 { 5839 int err; 5840 5841 /* 5842 * It is expected that the caller takes care of freeing queues if this 5843 * fails. 5844 */ 5845 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5846 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5847 return (err); 5848 } 5849 5850 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5851 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5852 5853 return (err); 5854 } 5855 5856 int 5857 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5858 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5859 { 5860 5861 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5862 } 5863 5864 #ifdef SMP 5865 static int 5866 find_nth(if_ctx_t ctx, int qid) 5867 { 5868 cpuset_t cpus; 5869 int i, cpuid, eqid, count; 5870 5871 CPU_COPY(&ctx->ifc_cpus, &cpus); 5872 count = CPU_COUNT(&cpus); 5873 eqid = qid % count; 5874 /* clear up to the qid'th bit */ 5875 for (i = 0; i < eqid; i++) { 5876 cpuid = CPU_FFS(&cpus); 5877 MPASS(cpuid != 0); 5878 CPU_CLR(cpuid-1, &cpus); 5879 } 5880 cpuid = CPU_FFS(&cpus); 5881 MPASS(cpuid != 0); 5882 return (cpuid-1); 5883 } 5884 5885 #ifdef SCHED_ULE 5886 extern struct cpu_group *cpu_top; /* CPU topology */ 5887 5888 static int 5889 find_child_with_core(int cpu, struct cpu_group *grp) 5890 { 5891 int i; 5892 5893 if (grp->cg_children == 0) 5894 return -1; 5895 5896 MPASS(grp->cg_child); 5897 for (i = 0; i < grp->cg_children; i++) { 5898 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5899 return i; 5900 } 5901 5902 return -1; 5903 } 5904 5905 /* 5906 * Find the nth "close" core to the specified core 5907 * "close" is defined as the deepest level that shares 5908 * at least an L2 cache. With threads, this will be 5909 * threads on the same core. If the shared cache is L3 5910 * or higher, simply returns the same core. 5911 */ 5912 static int 5913 find_close_core(int cpu, int core_offset) 5914 { 5915 struct cpu_group *grp; 5916 int i; 5917 int fcpu; 5918 cpuset_t cs; 5919 5920 grp = cpu_top; 5921 if (grp == NULL) 5922 return cpu; 5923 i = 0; 5924 while ((i = find_child_with_core(cpu, grp)) != -1) { 5925 /* If the child only has one cpu, don't descend */ 5926 if (grp->cg_child[i].cg_count <= 1) 5927 break; 5928 grp = &grp->cg_child[i]; 5929 } 5930 5931 /* If they don't share at least an L2 cache, use the same CPU */ 5932 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5933 return cpu; 5934 5935 /* Now pick one */ 5936 CPU_COPY(&grp->cg_mask, &cs); 5937 5938 /* Add the selected CPU offset to core offset. */ 5939 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5940 if (fcpu - 1 == cpu) 5941 break; 5942 CPU_CLR(fcpu - 1, &cs); 5943 } 5944 MPASS(fcpu); 5945 5946 core_offset += i; 5947 5948 CPU_COPY(&grp->cg_mask, &cs); 5949 for (i = core_offset % grp->cg_count; i > 0; i--) { 5950 MPASS(CPU_FFS(&cs)); 5951 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5952 } 5953 MPASS(CPU_FFS(&cs)); 5954 return CPU_FFS(&cs) - 1; 5955 } 5956 #else 5957 static int 5958 find_close_core(int cpu, int core_offset __unused) 5959 { 5960 return cpu; 5961 } 5962 #endif 5963 5964 static int 5965 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5966 { 5967 switch (type) { 5968 case IFLIB_INTR_TX: 5969 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5970 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5971 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5972 case IFLIB_INTR_RX: 5973 case IFLIB_INTR_RXTX: 5974 /* RX queues get the specified core */ 5975 return qid / CPU_COUNT(&ctx->ifc_cpus); 5976 default: 5977 return -1; 5978 } 5979 } 5980 #else 5981 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5982 #define find_close_core(cpuid, tid) CPU_FIRST() 5983 #define find_nth(ctx, gid) CPU_FIRST() 5984 #endif 5985 5986 /* Just to avoid copy/paste */ 5987 static inline int 5988 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5989 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5990 const char *name) 5991 { 5992 device_t dev; 5993 int co, cpuid, err, tid; 5994 5995 dev = ctx->ifc_dev; 5996 co = ctx->ifc_sysctl_core_offset; 5997 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5998 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5999 cpuid = find_nth(ctx, qid + co); 6000 tid = get_core_offset(ctx, type, qid); 6001 if (tid < 0) { 6002 device_printf(dev, "get_core_offset failed\n"); 6003 return (EOPNOTSUPP); 6004 } 6005 cpuid = find_close_core(cpuid, tid); 6006 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 6007 name); 6008 if (err) { 6009 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6010 return (err); 6011 } 6012 #ifdef notyet 6013 if (cpuid > ctx->ifc_cpuid_highest) 6014 ctx->ifc_cpuid_highest = cpuid; 6015 #endif 6016 return (0); 6017 } 6018 6019 int 6020 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6021 iflib_intr_type_t type, driver_filter_t *filter, 6022 void *filter_arg, int qid, const char *name) 6023 { 6024 device_t dev; 6025 struct grouptask *gtask; 6026 struct taskqgroup *tqg; 6027 iflib_filter_info_t info; 6028 gtask_fn_t *fn; 6029 int tqrid, err; 6030 driver_filter_t *intr_fast; 6031 void *q; 6032 6033 info = &ctx->ifc_filter_info; 6034 tqrid = rid; 6035 6036 switch (type) { 6037 /* XXX merge tx/rx for netmap? */ 6038 case IFLIB_INTR_TX: 6039 q = &ctx->ifc_txqs[qid]; 6040 info = &ctx->ifc_txqs[qid].ift_filter_info; 6041 gtask = &ctx->ifc_txqs[qid].ift_task; 6042 tqg = qgroup_if_io_tqg; 6043 fn = _task_fn_tx; 6044 intr_fast = iflib_fast_intr; 6045 GROUPTASK_INIT(gtask, 0, fn, q); 6046 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6047 break; 6048 case IFLIB_INTR_RX: 6049 q = &ctx->ifc_rxqs[qid]; 6050 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6051 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6052 tqg = qgroup_if_io_tqg; 6053 fn = _task_fn_rx; 6054 intr_fast = iflib_fast_intr; 6055 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6056 break; 6057 case IFLIB_INTR_RXTX: 6058 q = &ctx->ifc_rxqs[qid]; 6059 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6060 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6061 tqg = qgroup_if_io_tqg; 6062 fn = _task_fn_rx; 6063 intr_fast = iflib_fast_intr_rxtx; 6064 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6065 break; 6066 case IFLIB_INTR_ADMIN: 6067 q = ctx; 6068 tqrid = -1; 6069 info = &ctx->ifc_filter_info; 6070 gtask = &ctx->ifc_admin_task; 6071 tqg = qgroup_if_config_tqg; 6072 fn = _task_fn_admin; 6073 intr_fast = iflib_fast_intr_ctx; 6074 break; 6075 default: 6076 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6077 __func__); 6078 return (EINVAL); 6079 } 6080 6081 info->ifi_filter = filter; 6082 info->ifi_filter_arg = filter_arg; 6083 info->ifi_task = gtask; 6084 info->ifi_ctx = q; 6085 6086 dev = ctx->ifc_dev; 6087 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6088 if (err != 0) { 6089 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6090 return (err); 6091 } 6092 if (type == IFLIB_INTR_ADMIN) 6093 return (0); 6094 6095 if (tqrid != -1) { 6096 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6097 q, name); 6098 if (err) 6099 return (err); 6100 } else { 6101 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6102 } 6103 6104 return (0); 6105 } 6106 6107 void 6108 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6109 { 6110 struct grouptask *gtask; 6111 struct taskqgroup *tqg; 6112 gtask_fn_t *fn; 6113 void *q; 6114 int err; 6115 6116 switch (type) { 6117 case IFLIB_INTR_TX: 6118 q = &ctx->ifc_txqs[qid]; 6119 gtask = &ctx->ifc_txqs[qid].ift_task; 6120 tqg = qgroup_if_io_tqg; 6121 fn = _task_fn_tx; 6122 GROUPTASK_INIT(gtask, 0, fn, q); 6123 break; 6124 case IFLIB_INTR_RX: 6125 q = &ctx->ifc_rxqs[qid]; 6126 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6127 tqg = qgroup_if_io_tqg; 6128 fn = _task_fn_rx; 6129 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6130 break; 6131 case IFLIB_INTR_IOV: 6132 q = ctx; 6133 gtask = &ctx->ifc_vflr_task; 6134 tqg = qgroup_if_config_tqg; 6135 fn = _task_fn_iov; 6136 GROUPTASK_INIT(gtask, 0, fn, q); 6137 break; 6138 default: 6139 panic("unknown net intr type"); 6140 } 6141 if (irq != NULL) { 6142 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6143 q, name); 6144 if (err) 6145 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6146 irq->ii_res, name); 6147 } else { 6148 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6149 } 6150 } 6151 6152 void 6153 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6154 { 6155 6156 if (irq->ii_tag) 6157 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6158 6159 if (irq->ii_res) 6160 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6161 rman_get_rid(irq->ii_res), irq->ii_res); 6162 } 6163 6164 static int 6165 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6166 { 6167 iflib_txq_t txq = ctx->ifc_txqs; 6168 iflib_rxq_t rxq = ctx->ifc_rxqs; 6169 if_irq_t irq = &ctx->ifc_legacy_irq; 6170 iflib_filter_info_t info; 6171 device_t dev; 6172 struct grouptask *gtask; 6173 struct resource *res; 6174 struct taskqgroup *tqg; 6175 void *q; 6176 int err, tqrid; 6177 bool rx_only; 6178 6179 q = &ctx->ifc_rxqs[0]; 6180 info = &rxq[0].ifr_filter_info; 6181 gtask = &rxq[0].ifr_task; 6182 tqg = qgroup_if_io_tqg; 6183 tqrid = *rid; 6184 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6185 6186 ctx->ifc_flags |= IFC_LEGACY; 6187 info->ifi_filter = filter; 6188 info->ifi_filter_arg = filter_arg; 6189 info->ifi_task = gtask; 6190 info->ifi_ctx = rx_only ? ctx : q; 6191 6192 dev = ctx->ifc_dev; 6193 /* We allocate a single interrupt resource */ 6194 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6195 iflib_fast_intr_rxtx, NULL, info, name); 6196 if (err != 0) 6197 return (err); 6198 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6199 res = irq->ii_res; 6200 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6201 6202 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6203 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6204 "tx"); 6205 return (0); 6206 } 6207 6208 void 6209 iflib_led_create(if_ctx_t ctx) 6210 { 6211 6212 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6213 device_get_nameunit(ctx->ifc_dev)); 6214 } 6215 6216 void 6217 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6218 { 6219 6220 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6221 } 6222 6223 void 6224 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6225 { 6226 6227 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6228 } 6229 6230 void 6231 iflib_admin_intr_deferred(if_ctx_t ctx) 6232 { 6233 6234 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6235 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6236 } 6237 6238 void 6239 iflib_iov_intr_deferred(if_ctx_t ctx) 6240 { 6241 6242 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6243 } 6244 6245 void 6246 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6247 { 6248 6249 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6250 name); 6251 } 6252 6253 void 6254 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6255 const char *name) 6256 { 6257 6258 GROUPTASK_INIT(gtask, 0, fn, ctx); 6259 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6260 name); 6261 } 6262 6263 void 6264 iflib_config_gtask_deinit(struct grouptask *gtask) 6265 { 6266 6267 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6268 } 6269 6270 void 6271 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6272 { 6273 if_t ifp = ctx->ifc_ifp; 6274 iflib_txq_t txq = ctx->ifc_txqs; 6275 6276 if_setbaudrate(ifp, baudrate); 6277 if (baudrate >= IF_Gbps(10)) { 6278 STATE_LOCK(ctx); 6279 ctx->ifc_flags |= IFC_PREFETCH; 6280 STATE_UNLOCK(ctx); 6281 } 6282 /* If link down, disable watchdog */ 6283 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6284 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6285 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6286 } 6287 ctx->ifc_link_state = link_state; 6288 if_link_state_change(ifp, link_state); 6289 } 6290 6291 static int 6292 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6293 { 6294 int credits; 6295 #ifdef INVARIANTS 6296 int credits_pre = txq->ift_cidx_processed; 6297 #endif 6298 6299 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6300 BUS_DMASYNC_POSTREAD); 6301 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6302 return (0); 6303 6304 txq->ift_processed += credits; 6305 txq->ift_cidx_processed += credits; 6306 6307 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6308 if (txq->ift_cidx_processed >= txq->ift_size) 6309 txq->ift_cidx_processed -= txq->ift_size; 6310 return (credits); 6311 } 6312 6313 static int 6314 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6315 { 6316 iflib_fl_t fl; 6317 u_int i; 6318 6319 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6320 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6321 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6322 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6323 budget)); 6324 } 6325 6326 void 6327 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6328 const char *description, if_int_delay_info_t info, 6329 int offset, int value) 6330 { 6331 info->iidi_ctx = ctx; 6332 info->iidi_offset = offset; 6333 info->iidi_value = value; 6334 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6335 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6336 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6337 info, 0, iflib_sysctl_int_delay, "I", description); 6338 } 6339 6340 struct sx * 6341 iflib_ctx_lock_get(if_ctx_t ctx) 6342 { 6343 6344 return (&ctx->ifc_ctx_sx); 6345 } 6346 6347 static int 6348 iflib_msix_init(if_ctx_t ctx) 6349 { 6350 device_t dev = ctx->ifc_dev; 6351 if_shared_ctx_t sctx = ctx->ifc_sctx; 6352 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6353 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6354 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6355 6356 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6357 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6358 6359 if (bootverbose) 6360 device_printf(dev, "msix_init qsets capped at %d\n", 6361 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6362 6363 /* Override by tuneable */ 6364 if (scctx->isc_disable_msix) 6365 goto msi; 6366 6367 /* First try MSI-X */ 6368 if ((msgs = pci_msix_count(dev)) == 0) { 6369 if (bootverbose) 6370 device_printf(dev, "MSI-X not supported or disabled\n"); 6371 goto msi; 6372 } 6373 6374 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6375 /* 6376 * bar == -1 => "trust me I know what I'm doing" 6377 * Some drivers are for hardware that is so shoddily 6378 * documented that no one knows which bars are which 6379 * so the developer has to map all bars. This hack 6380 * allows shoddy garbage to use MSI-X in this framework. 6381 */ 6382 if (bar != -1) { 6383 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6384 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6385 if (ctx->ifc_msix_mem == NULL) { 6386 device_printf(dev, "Unable to map MSI-X table\n"); 6387 goto msi; 6388 } 6389 } 6390 6391 admincnt = sctx->isc_admin_intrcnt; 6392 #if IFLIB_DEBUG 6393 /* use only 1 qset in debug mode */ 6394 queuemsgs = min(msgs - admincnt, 1); 6395 #else 6396 queuemsgs = msgs - admincnt; 6397 #endif 6398 #ifdef RSS 6399 queues = imin(queuemsgs, rss_getnumbuckets()); 6400 #else 6401 queues = queuemsgs; 6402 #endif 6403 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6404 if (bootverbose) 6405 device_printf(dev, 6406 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6407 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6408 #ifdef RSS 6409 /* If we're doing RSS, clamp at the number of RSS buckets */ 6410 if (queues > rss_getnumbuckets()) 6411 queues = rss_getnumbuckets(); 6412 #endif 6413 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6414 rx_queues = iflib_num_rx_queues; 6415 else 6416 rx_queues = queues; 6417 6418 if (rx_queues > scctx->isc_nrxqsets) 6419 rx_queues = scctx->isc_nrxqsets; 6420 6421 /* 6422 * We want this to be all logical CPUs by default 6423 */ 6424 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6425 tx_queues = iflib_num_tx_queues; 6426 else 6427 tx_queues = mp_ncpus; 6428 6429 if (tx_queues > scctx->isc_ntxqsets) 6430 tx_queues = scctx->isc_ntxqsets; 6431 6432 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6433 #ifdef INVARIANTS 6434 if (tx_queues != rx_queues) 6435 device_printf(dev, 6436 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6437 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6438 #endif 6439 tx_queues = min(rx_queues, tx_queues); 6440 rx_queues = min(rx_queues, tx_queues); 6441 } 6442 6443 vectors = rx_queues + admincnt; 6444 if (msgs < vectors) { 6445 device_printf(dev, 6446 "insufficient number of MSI-X vectors " 6447 "(supported %d, need %d)\n", msgs, vectors); 6448 goto msi; 6449 } 6450 6451 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6452 tx_queues); 6453 msgs = vectors; 6454 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6455 if (vectors != msgs) { 6456 device_printf(dev, 6457 "Unable to allocate sufficient MSI-X vectors " 6458 "(got %d, need %d)\n", vectors, msgs); 6459 pci_release_msi(dev); 6460 if (bar != -1) { 6461 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6462 ctx->ifc_msix_mem); 6463 ctx->ifc_msix_mem = NULL; 6464 } 6465 goto msi; 6466 } 6467 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6468 vectors); 6469 scctx->isc_vectors = vectors; 6470 scctx->isc_nrxqsets = rx_queues; 6471 scctx->isc_ntxqsets = tx_queues; 6472 scctx->isc_intr = IFLIB_INTR_MSIX; 6473 6474 return (vectors); 6475 } else { 6476 device_printf(dev, 6477 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6478 err); 6479 if (bar != -1) { 6480 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6481 ctx->ifc_msix_mem); 6482 ctx->ifc_msix_mem = NULL; 6483 } 6484 } 6485 6486 msi: 6487 vectors = pci_msi_count(dev); 6488 scctx->isc_nrxqsets = 1; 6489 scctx->isc_ntxqsets = 1; 6490 scctx->isc_vectors = vectors; 6491 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6492 device_printf(dev,"Using an MSI interrupt\n"); 6493 scctx->isc_intr = IFLIB_INTR_MSI; 6494 } else { 6495 scctx->isc_vectors = 1; 6496 device_printf(dev,"Using a Legacy interrupt\n"); 6497 scctx->isc_intr = IFLIB_INTR_LEGACY; 6498 } 6499 6500 return (vectors); 6501 } 6502 6503 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6504 6505 static int 6506 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6507 { 6508 int rc; 6509 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6510 struct sbuf *sb; 6511 const char *ring_state = "UNKNOWN"; 6512 6513 /* XXX needed ? */ 6514 rc = sysctl_wire_old_buffer(req, 0); 6515 MPASS(rc == 0); 6516 if (rc != 0) 6517 return (rc); 6518 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6519 MPASS(sb != NULL); 6520 if (sb == NULL) 6521 return (ENOMEM); 6522 if (state[3] <= 3) 6523 ring_state = ring_states[state[3]]; 6524 6525 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6526 state[0], state[1], state[2], ring_state); 6527 rc = sbuf_finish(sb); 6528 sbuf_delete(sb); 6529 return(rc); 6530 } 6531 6532 enum iflib_ndesc_handler { 6533 IFLIB_NTXD_HANDLER, 6534 IFLIB_NRXD_HANDLER, 6535 }; 6536 6537 static int 6538 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6539 { 6540 if_ctx_t ctx = (void *)arg1; 6541 enum iflib_ndesc_handler type = arg2; 6542 char buf[256] = {0}; 6543 qidx_t *ndesc; 6544 char *p, *next; 6545 int nqs, rc, i; 6546 6547 nqs = 8; 6548 switch(type) { 6549 case IFLIB_NTXD_HANDLER: 6550 ndesc = ctx->ifc_sysctl_ntxds; 6551 if (ctx->ifc_sctx) 6552 nqs = ctx->ifc_sctx->isc_ntxqs; 6553 break; 6554 case IFLIB_NRXD_HANDLER: 6555 ndesc = ctx->ifc_sysctl_nrxds; 6556 if (ctx->ifc_sctx) 6557 nqs = ctx->ifc_sctx->isc_nrxqs; 6558 break; 6559 default: 6560 printf("%s: unhandled type\n", __func__); 6561 return (EINVAL); 6562 } 6563 if (nqs == 0) 6564 nqs = 8; 6565 6566 for (i=0; i<8; i++) { 6567 if (i >= nqs) 6568 break; 6569 if (i) 6570 strcat(buf, ","); 6571 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6572 } 6573 6574 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6575 if (rc || req->newptr == NULL) 6576 return rc; 6577 6578 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6579 i++, p = strsep(&next, " ,")) { 6580 ndesc[i] = strtoul(p, NULL, 10); 6581 } 6582 6583 return(rc); 6584 } 6585 6586 #define NAME_BUFLEN 32 6587 static void 6588 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6589 { 6590 device_t dev = iflib_get_dev(ctx); 6591 struct sysctl_oid_list *child, *oid_list; 6592 struct sysctl_ctx_list *ctx_list; 6593 struct sysctl_oid *node; 6594 6595 ctx_list = device_get_sysctl_ctx(dev); 6596 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6597 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6598 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6599 oid_list = SYSCTL_CHILDREN(node); 6600 6601 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6602 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6603 "driver version"); 6604 6605 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6606 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6607 "# of txqs to use, 0 => use default #"); 6608 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6609 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6610 "# of rxqs to use, 0 => use default #"); 6611 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6612 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6613 "permit #txq != #rxq"); 6614 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6615 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6616 "disable MSI-X (default 0)"); 6617 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6618 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6619 "set the RX budget"); 6620 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6621 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6622 "cause TX to abdicate instead of running to completion"); 6623 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6624 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6625 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6626 "offset to start using cores at"); 6627 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6628 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6629 "use separate cores for TX and RX"); 6630 6631 /* XXX change for per-queue sizes */ 6632 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6633 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6634 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6635 "list of # of TX descriptors to use, 0 = use default #"); 6636 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6637 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6638 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6639 "list of # of RX descriptors to use, 0 = use default #"); 6640 } 6641 6642 static void 6643 iflib_add_device_sysctl_post(if_ctx_t ctx) 6644 { 6645 if_shared_ctx_t sctx = ctx->ifc_sctx; 6646 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6647 device_t dev = iflib_get_dev(ctx); 6648 struct sysctl_oid_list *child; 6649 struct sysctl_ctx_list *ctx_list; 6650 iflib_fl_t fl; 6651 iflib_txq_t txq; 6652 iflib_rxq_t rxq; 6653 int i, j; 6654 char namebuf[NAME_BUFLEN]; 6655 char *qfmt; 6656 struct sysctl_oid *queue_node, *fl_node, *node; 6657 struct sysctl_oid_list *queue_list, *fl_list; 6658 ctx_list = device_get_sysctl_ctx(dev); 6659 6660 node = ctx->ifc_sysctl_node; 6661 child = SYSCTL_CHILDREN(node); 6662 6663 if (scctx->isc_ntxqsets > 100) 6664 qfmt = "txq%03d"; 6665 else if (scctx->isc_ntxqsets > 10) 6666 qfmt = "txq%02d"; 6667 else 6668 qfmt = "txq%d"; 6669 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6670 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6671 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6672 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6673 queue_list = SYSCTL_CHILDREN(queue_node); 6674 #if MEMORY_LOGGING 6675 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6676 CTLFLAG_RD, 6677 &txq->ift_dequeued, "total mbufs freed"); 6678 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6679 CTLFLAG_RD, 6680 &txq->ift_enqueued, "total mbufs enqueued"); 6681 #endif 6682 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6683 CTLFLAG_RD, 6684 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6685 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6686 CTLFLAG_RD, 6687 &txq->ift_pullups, "# of times m_pullup was called"); 6688 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6689 CTLFLAG_RD, 6690 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6691 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6692 CTLFLAG_RD, 6693 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6694 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6695 CTLFLAG_RD, 6696 &txq->ift_map_failed, "# of times DMA map failed"); 6697 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6698 CTLFLAG_RD, 6699 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6700 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6701 CTLFLAG_RD, 6702 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6703 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6704 CTLFLAG_RD, 6705 &txq->ift_pidx, 1, "Producer Index"); 6706 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6707 CTLFLAG_RD, 6708 &txq->ift_cidx, 1, "Consumer Index"); 6709 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6710 CTLFLAG_RD, 6711 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6712 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6713 CTLFLAG_RD, 6714 &txq->ift_in_use, 1, "descriptors in use"); 6715 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6716 CTLFLAG_RD, 6717 &txq->ift_processed, "descriptors procesed for clean"); 6718 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6719 CTLFLAG_RD, 6720 &txq->ift_cleaned, "total cleaned"); 6721 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6722 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6723 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6724 mp_ring_state_handler, "A", "soft ring state"); 6725 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6726 CTLFLAG_RD, &txq->ift_br->enqueues, 6727 "# of enqueues to the mp_ring for this queue"); 6728 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6729 CTLFLAG_RD, &txq->ift_br->drops, 6730 "# of drops in the mp_ring for this queue"); 6731 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6732 CTLFLAG_RD, &txq->ift_br->starts, 6733 "# of normal consumer starts in the mp_ring for this queue"); 6734 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6735 CTLFLAG_RD, &txq->ift_br->stalls, 6736 "# of consumer stalls in the mp_ring for this queue"); 6737 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6738 CTLFLAG_RD, &txq->ift_br->restarts, 6739 "# of consumer restarts in the mp_ring for this queue"); 6740 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6741 CTLFLAG_RD, &txq->ift_br->abdications, 6742 "# of consumer abdications in the mp_ring for this queue"); 6743 } 6744 6745 if (scctx->isc_nrxqsets > 100) 6746 qfmt = "rxq%03d"; 6747 else if (scctx->isc_nrxqsets > 10) 6748 qfmt = "rxq%02d"; 6749 else 6750 qfmt = "rxq%d"; 6751 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6752 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6753 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6754 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6755 queue_list = SYSCTL_CHILDREN(queue_node); 6756 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6757 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6758 CTLFLAG_RD, 6759 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6760 } 6761 6762 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6763 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6764 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6765 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6766 fl_list = SYSCTL_CHILDREN(fl_node); 6767 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6768 CTLFLAG_RD, 6769 &fl->ifl_pidx, 1, "Producer Index"); 6770 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6771 CTLFLAG_RD, 6772 &fl->ifl_cidx, 1, "Consumer Index"); 6773 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6774 CTLFLAG_RD, 6775 &fl->ifl_credits, 1, "credits available"); 6776 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6777 CTLFLAG_RD, 6778 &fl->ifl_buf_size, 1, "buffer size"); 6779 #if MEMORY_LOGGING 6780 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6781 CTLFLAG_RD, 6782 &fl->ifl_m_enqueued, "mbufs allocated"); 6783 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6784 CTLFLAG_RD, 6785 &fl->ifl_m_dequeued, "mbufs freed"); 6786 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6787 CTLFLAG_RD, 6788 &fl->ifl_cl_enqueued, "clusters allocated"); 6789 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6790 CTLFLAG_RD, 6791 &fl->ifl_cl_dequeued, "clusters freed"); 6792 #endif 6793 6794 } 6795 } 6796 6797 } 6798 6799 void 6800 iflib_request_reset(if_ctx_t ctx) 6801 { 6802 6803 STATE_LOCK(ctx); 6804 ctx->ifc_flags |= IFC_DO_RESET; 6805 STATE_UNLOCK(ctx); 6806 } 6807 6808 #ifndef __NO_STRICT_ALIGNMENT 6809 static struct mbuf * 6810 iflib_fixup_rx(struct mbuf *m) 6811 { 6812 struct mbuf *n; 6813 6814 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6815 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6816 m->m_data += ETHER_HDR_LEN; 6817 n = m; 6818 } else { 6819 MGETHDR(n, M_NOWAIT, MT_DATA); 6820 if (n == NULL) { 6821 m_freem(m); 6822 return (NULL); 6823 } 6824 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6825 m->m_data += ETHER_HDR_LEN; 6826 m->m_len -= ETHER_HDR_LEN; 6827 n->m_len = ETHER_HDR_LEN; 6828 M_MOVE_PKTHDR(n, m); 6829 n->m_next = m; 6830 } 6831 return (n); 6832 } 6833 #endif 6834 6835 #ifdef DEBUGNET 6836 static void 6837 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6838 { 6839 if_ctx_t ctx; 6840 6841 ctx = if_getsoftc(ifp); 6842 CTX_LOCK(ctx); 6843 *nrxr = NRXQSETS(ctx); 6844 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6845 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6846 CTX_UNLOCK(ctx); 6847 } 6848 6849 static void 6850 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6851 { 6852 if_ctx_t ctx; 6853 if_softc_ctx_t scctx; 6854 iflib_fl_t fl; 6855 iflib_rxq_t rxq; 6856 int i, j; 6857 6858 ctx = if_getsoftc(ifp); 6859 scctx = &ctx->ifc_softc_ctx; 6860 6861 switch (event) { 6862 case DEBUGNET_START: 6863 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6864 rxq = &ctx->ifc_rxqs[i]; 6865 for (j = 0; j < rxq->ifr_nfl; j++) { 6866 fl = rxq->ifr_fl; 6867 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6868 } 6869 } 6870 iflib_no_tx_batch = 1; 6871 break; 6872 default: 6873 break; 6874 } 6875 } 6876 6877 static int 6878 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6879 { 6880 if_ctx_t ctx; 6881 iflib_txq_t txq; 6882 int error; 6883 6884 ctx = if_getsoftc(ifp); 6885 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6886 IFF_DRV_RUNNING) 6887 return (EBUSY); 6888 6889 txq = &ctx->ifc_txqs[0]; 6890 error = iflib_encap(txq, &m); 6891 if (error == 0) 6892 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6893 return (error); 6894 } 6895 6896 static int 6897 iflib_debugnet_poll(if_t ifp, int count) 6898 { 6899 struct epoch_tracker et; 6900 if_ctx_t ctx; 6901 if_softc_ctx_t scctx; 6902 iflib_txq_t txq; 6903 int i; 6904 6905 ctx = if_getsoftc(ifp); 6906 scctx = &ctx->ifc_softc_ctx; 6907 6908 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6909 IFF_DRV_RUNNING) 6910 return (EBUSY); 6911 6912 txq = &ctx->ifc_txqs[0]; 6913 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6914 6915 NET_EPOCH_ENTER(et); 6916 for (i = 0; i < scctx->isc_nrxqsets; i++) 6917 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6918 NET_EPOCH_EXIT(et); 6919 return (0); 6920 } 6921 #endif /* DEBUGNET */ 6922