1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 175 int ifc_link_state; 176 int ifc_link_irq; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 194 qidx_t ifc_sysctl_ntxds[8]; 195 qidx_t ifc_sysctl_nrxds[8]; 196 struct if_txrx ifc_txrx; 197 #define isc_txd_encap ifc_txrx.ift_txd_encap 198 #define isc_txd_flush ifc_txrx.ift_txd_flush 199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 200 #define isc_rxd_available ifc_txrx.ift_rxd_available 201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 207 eventhandler_tag ifc_vlan_attach_event; 208 eventhandler_tag ifc_vlan_detach_event; 209 uint8_t ifc_mac[ETHER_ADDR_LEN]; 210 char ifc_mtx_name[16]; 211 }; 212 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (&ctx->ifc_media); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 309 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 310 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 311 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 351 if_txsd_vec_t ift_sds; 352 uint8_t ift_qstatus; 353 uint8_t ift_closed; 354 uint8_t ift_update_freq; 355 struct iflib_filter_info ift_filter_info; 356 bus_dma_tag_t ift_buf_tag; 357 bus_dma_tag_t ift_tso_buf_tag; 358 iflib_dma_info_t ift_ifdi; 359 #define MTX_NAME_LEN 16 360 char ift_mtx_name[MTX_NAME_LEN]; 361 char ift_db_mtx_name[MTX_NAME_LEN]; 362 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 363 #ifdef IFLIB_DIAGNOSTICS 364 uint64_t ift_cpu_exec_count[256]; 365 #endif 366 } __aligned(CACHE_LINE_SIZE); 367 368 struct iflib_fl { 369 qidx_t ifl_cidx; 370 qidx_t ifl_pidx; 371 qidx_t ifl_credits; 372 uint8_t ifl_gen; 373 uint8_t ifl_rxd_size; 374 #if MEMORY_LOGGING 375 uint64_t ifl_m_enqueued; 376 uint64_t ifl_m_dequeued; 377 uint64_t ifl_cl_enqueued; 378 uint64_t ifl_cl_dequeued; 379 #endif 380 /* implicit pad */ 381 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 /* If there is a separate completion queue - 425 * these are the cq cidx and pidx. Otherwise 426 * these are unused. 427 */ 428 qidx_t ifr_size; 429 qidx_t ifr_cq_cidx; 430 qidx_t ifr_cq_pidx; 431 uint8_t ifr_cq_gen; 432 uint8_t ifr_fl_offset; 433 434 if_ctx_t ifr_ctx; 435 iflib_fl_t ifr_fl; 436 uint64_t ifr_rx_irq; 437 uint16_t ifr_id; 438 uint8_t ifr_lro_enabled; 439 uint8_t ifr_nfl; 440 uint8_t ifr_ntxqirq; 441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 442 struct lro_ctrl ifr_lc; 443 struct grouptask ifr_task; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 struct mbuf **ifsd_m; 457 iflib_fl_t ifsd_fl; 458 qidx_t ifsd_cidx; 459 } *if_rxsd_t; 460 461 /* multiple of word size */ 462 #ifdef __LP64__ 463 #define PKT_INFO_SIZE 6 464 #define RXD_INFO_SIZE 5 465 #define PKT_TYPE uint64_t 466 #else 467 #define PKT_INFO_SIZE 11 468 #define RXD_INFO_SIZE 8 469 #define PKT_TYPE uint32_t 470 #endif 471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 473 474 typedef struct if_pkt_info_pad { 475 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 476 } *if_pkt_info_pad_t; 477 typedef struct if_rxd_info_pad { 478 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 479 } *if_rxd_info_pad_t; 480 481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 483 484 485 static inline void 486 pkt_info_zero(if_pkt_info_t pi) 487 { 488 if_pkt_info_pad_t pi_pad; 489 490 pi_pad = (if_pkt_info_pad_t)pi; 491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 493 #ifndef __LP64__ 494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 496 #endif 497 } 498 499 static device_method_t iflib_pseudo_methods[] = { 500 DEVMETHOD(device_attach, noop_attach), 501 DEVMETHOD(device_detach, iflib_pseudo_detach), 502 DEVMETHOD_END 503 }; 504 505 driver_t iflib_pseudodriver = { 506 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 507 }; 508 509 static inline void 510 rxd_info_zero(if_rxd_info_t ri) 511 { 512 if_rxd_info_pad_t ri_pad; 513 int i; 514 515 ri_pad = (if_rxd_info_pad_t)ri; 516 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 517 ri_pad->rxd_val[i] = 0; 518 ri_pad->rxd_val[i+1] = 0; 519 ri_pad->rxd_val[i+2] = 0; 520 ri_pad->rxd_val[i+3] = 0; 521 } 522 #ifdef __LP64__ 523 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 524 #endif 525 } 526 527 /* 528 * Only allow a single packet to take up most 1/nth of the tx ring 529 */ 530 #define MAX_SINGLE_PACKET_FRACTION 12 531 #define IF_BAD_DMA (bus_addr_t)-1 532 533 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 534 535 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 536 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 537 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 538 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 539 540 541 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 542 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 543 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 544 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 545 546 547 548 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 549 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 550 551 void 552 iflib_set_detach(if_ctx_t ctx) 553 { 554 STATE_LOCK(ctx); 555 ctx->ifc_flags |= IFC_IN_DETACH; 556 STATE_UNLOCK(ctx); 557 } 558 559 /* Our boot-time initialization hook */ 560 static int iflib_module_event_handler(module_t, int, void *); 561 562 static moduledata_t iflib_moduledata = { 563 "iflib", 564 iflib_module_event_handler, 565 NULL 566 }; 567 568 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 569 MODULE_VERSION(iflib, 1); 570 571 MODULE_DEPEND(iflib, pci, 1, 1, 1); 572 MODULE_DEPEND(iflib, ether, 1, 1, 1); 573 574 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 575 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 576 577 #ifndef IFLIB_DEBUG_COUNTERS 578 #ifdef INVARIANTS 579 #define IFLIB_DEBUG_COUNTERS 1 580 #else 581 #define IFLIB_DEBUG_COUNTERS 0 582 #endif /* !INVARIANTS */ 583 #endif 584 585 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 586 "iflib driver parameters"); 587 588 /* 589 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 590 */ 591 static int iflib_min_tx_latency = 0; 592 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 593 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 594 static int iflib_no_tx_batch = 0; 595 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 596 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 597 598 599 #if IFLIB_DEBUG_COUNTERS 600 601 static int iflib_tx_seen; 602 static int iflib_tx_sent; 603 static int iflib_tx_encap; 604 static int iflib_rx_allocs; 605 static int iflib_fl_refills; 606 static int iflib_fl_refills_large; 607 static int iflib_tx_frees; 608 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 610 &iflib_tx_seen, 0, "# tx mbufs seen"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 612 &iflib_tx_sent, 0, "# tx mbufs sent"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 614 &iflib_tx_encap, 0, "# tx mbufs encapped"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 616 &iflib_tx_frees, 0, "# tx frees"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 618 &iflib_rx_allocs, 0, "# rx allocations"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 620 &iflib_fl_refills, 0, "# refills"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 622 &iflib_fl_refills_large, 0, "# large refills"); 623 624 625 static int iflib_txq_drain_flushing; 626 static int iflib_txq_drain_oactive; 627 static int iflib_txq_drain_notready; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 630 &iflib_txq_drain_flushing, 0, "# drain flushes"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 632 &iflib_txq_drain_oactive, 0, "# drain oactives"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 634 &iflib_txq_drain_notready, 0, "# drain notready"); 635 636 637 static int iflib_encap_load_mbuf_fail; 638 static int iflib_encap_pad_mbuf_fail; 639 static int iflib_encap_txq_avail_fail; 640 static int iflib_encap_txd_encap_fail; 641 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 643 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 645 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 647 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 649 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 650 651 static int iflib_task_fn_rxs; 652 static int iflib_rx_intr_enables; 653 static int iflib_fast_intrs; 654 static int iflib_rx_unavail; 655 static int iflib_rx_ctx_inactive; 656 static int iflib_rx_if_input; 657 static int iflib_rx_mbuf_null; 658 static int iflib_rxd_flush; 659 660 static int iflib_verbose_debug; 661 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 673 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 675 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 677 &iflib_rxd_flush, 0, "# times rxd_flush called"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 679 &iflib_verbose_debug, 0, "enable verbose debugging"); 680 681 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 682 static void 683 iflib_debug_reset(void) 684 { 685 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 686 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 687 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 688 iflib_txq_drain_notready = 689 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 690 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 691 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 692 iflib_rx_unavail = 693 iflib_rx_ctx_inactive = iflib_rx_if_input = 694 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 695 } 696 697 #else 698 #define DBG_COUNTER_INC(name) 699 static void iflib_debug_reset(void) {} 700 #endif 701 702 #define IFLIB_DEBUG 0 703 704 static void iflib_tx_structures_free(if_ctx_t ctx); 705 static void iflib_rx_structures_free(if_ctx_t ctx); 706 static int iflib_queues_alloc(if_ctx_t ctx); 707 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 708 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 709 static int iflib_qset_structures_setup(if_ctx_t ctx); 710 static int iflib_msix_init(if_ctx_t ctx); 711 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 712 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 713 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 714 #ifdef ALTQ 715 static void iflib_altq_if_start(if_t ifp); 716 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 717 #endif 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_if_init_locked(if_ctx_t ctx); 725 static void iflib_free_intr_mem(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 NETDUMP_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 struct ifnet *ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init) && map) { 849 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 850 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 851 /* buffer has changed, reload map */ 852 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 853 } 854 slot->flags &= ~NS_BUF_CHANGED; 855 856 nm_i = nm_next(nm_i, lim); 857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 859 continue; 860 861 iru.iru_pidx = refill_pidx; 862 iru.iru_count = tmp_pidx+1; 863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 864 865 refill_pidx = nic_i; 866 if (map == NULL) 867 continue; 868 869 for (int n = 0; n < iru.iru_count; n++) { 870 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 871 BUS_DMASYNC_PREREAD); 872 /* XXX - change this to not use the netmap func*/ 873 nic_i_dma = nm_next(nic_i_dma, lim); 874 } 875 } 876 } 877 kring->nr_hwcur = head; 878 879 if (map) 880 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 if (__predict_true(nic_i != UINT_MAX)) { 883 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 884 DBG_COUNTER_INC(rxd_flush); 885 } 886 return (0); 887 } 888 889 /* 890 * Reconcile kernel and user view of the transmit ring. 891 * 892 * All information is in the kring. 893 * Userspace wants to send packets up to the one before kring->rhead, 894 * kernel knows kring->nr_hwcur is the first unsent packet. 895 * 896 * Here we push packets out (as many as possible), and possibly 897 * reclaim buffers from previously completed transmission. 898 * 899 * The caller (netmap) guarantees that there is only one instance 900 * running at any time. Any interference with other driver 901 * methods should be handled by the individual drivers. 902 */ 903 static int 904 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 905 { 906 struct netmap_adapter *na = kring->na; 907 struct ifnet *ifp = na->ifp; 908 struct netmap_ring *ring = kring->ring; 909 u_int nm_i; /* index into the netmap kring */ 910 u_int nic_i; /* index into the NIC ring */ 911 u_int n; 912 u_int const lim = kring->nkr_num_slots - 1; 913 u_int const head = kring->rhead; 914 struct if_pkt_info pi; 915 916 /* 917 * interrupts on every tx packet are expensive so request 918 * them every half ring, or where NS_REPORT is set 919 */ 920 u_int report_frequency = kring->nkr_num_slots >> 1; 921 /* device-specific */ 922 if_ctx_t ctx = ifp->if_softc; 923 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 924 925 bus_dmamap_sync(txq->ift_buf_tag, txq->ift_ifdi->idi_map, 926 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 927 928 /* 929 * First part: process new packets to send. 930 * nm_i is the current index in the netmap kring, 931 * nic_i is the corresponding index in the NIC ring. 932 * 933 * If we have packets to send (nm_i != head) 934 * iterate over the netmap ring, fetch length and update 935 * the corresponding slot in the NIC ring. Some drivers also 936 * need to update the buffer's physical address in the NIC slot 937 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 938 * 939 * The netmap_reload_map() calls is especially expensive, 940 * even when (as in this case) the tag is 0, so do only 941 * when the buffer has actually changed. 942 * 943 * If possible do not set the report/intr bit on all slots, 944 * but only a few times per ring or when NS_REPORT is set. 945 * 946 * Finally, on 10G and faster drivers, it might be useful 947 * to prefetch the next slot and txr entry. 948 */ 949 950 nm_i = kring->nr_hwcur; 951 if (nm_i != head) { /* we have new packets to send */ 952 pkt_info_zero(&pi); 953 pi.ipi_segs = txq->ift_segs; 954 pi.ipi_qsidx = kring->ring_id; 955 nic_i = netmap_idx_k2n(kring, nm_i); 956 957 __builtin_prefetch(&ring->slot[nm_i]); 958 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 959 if (txq->ift_sds.ifsd_map) 960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 961 962 for (n = 0; nm_i != head; n++) { 963 struct netmap_slot *slot = &ring->slot[nm_i]; 964 u_int len = slot->len; 965 uint64_t paddr; 966 void *addr = PNMB(na, slot, &paddr); 967 int flags = (slot->flags & NS_REPORT || 968 nic_i == 0 || nic_i == report_frequency) ? 969 IPI_TX_INTR : 0; 970 971 /* device-specific */ 972 pi.ipi_len = len; 973 pi.ipi_segs[0].ds_addr = paddr; 974 pi.ipi_segs[0].ds_len = len; 975 pi.ipi_nsegs = 1; 976 pi.ipi_ndescs = 0; 977 pi.ipi_pidx = nic_i; 978 pi.ipi_flags = flags; 979 980 /* Fill the slot in the NIC ring. */ 981 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 982 DBG_COUNTER_INC(tx_encap); 983 984 /* prefetch for next round */ 985 __builtin_prefetch(&ring->slot[nm_i + 1]); 986 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 987 if (txq->ift_sds.ifsd_map) { 988 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 989 990 NM_CHECK_ADDR_LEN(na, addr, len); 991 992 if (slot->flags & NS_BUF_CHANGED) { 993 /* buffer has changed, reload map */ 994 netmap_reload_map(na, txq->ift_buf_tag, 995 txq->ift_sds.ifsd_map[nic_i], addr); 996 } 997 /* make sure changes to the buffer are synced */ 998 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 999 BUS_DMASYNC_PREWRITE); 1000 } 1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1002 nm_i = nm_next(nm_i, lim); 1003 nic_i = nm_next(nic_i, lim); 1004 } 1005 kring->nr_hwcur = nm_i; 1006 1007 /* synchronize the NIC ring */ 1008 bus_dmamap_sync(txq->ift_buf_tag, txq->ift_ifdi->idi_map, 1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1010 1011 /* (re)start the tx unit up to slot nic_i (excluded) */ 1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1013 } 1014 1015 /* 1016 * Second part: reclaim buffers for completed transmissions. 1017 * 1018 * If there are unclaimed buffers, attempt to reclaim them. 1019 * If none are reclaimed, and TX IRQs are not in use, do an initial 1020 * minimal delay, then trigger the tx handler which will spin in the 1021 * group task queue. 1022 */ 1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1024 if (iflib_tx_credits_update(ctx, txq)) { 1025 /* some tx completed, increment avail */ 1026 nic_i = txq->ift_cidx_processed; 1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1028 } 1029 } 1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1033 iflib_timer, txq, txq->ift_timer.c_cpu); 1034 } 1035 return (0); 1036 } 1037 1038 /* 1039 * Reconcile kernel and user view of the receive ring. 1040 * Same as for the txsync, this routine must be efficient. 1041 * The caller guarantees a single invocations, but races against 1042 * the rest of the driver should be handled here. 1043 * 1044 * On call, kring->rhead is the first packet that userspace wants 1045 * to keep, and kring->rcur is the wakeup point. 1046 * The kernel has previously reported packets up to kring->rtail. 1047 * 1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1049 * of whether or not we received an interrupt. 1050 */ 1051 static int 1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1053 { 1054 struct netmap_adapter *na = kring->na; 1055 struct netmap_ring *ring = kring->ring; 1056 uint32_t nm_i; /* index into the netmap ring */ 1057 uint32_t nic_i; /* index into the NIC ring */ 1058 u_int i, n; 1059 u_int const lim = kring->nkr_num_slots - 1; 1060 u_int const head = kring->rhead; 1061 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1062 struct if_rxd_info ri; 1063 1064 struct ifnet *ifp = na->ifp; 1065 if_ctx_t ctx = ifp->if_softc; 1066 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1067 iflib_fl_t fl = rxq->ifr_fl; 1068 if (head > lim) 1069 return netmap_ring_reinit(kring); 1070 1071 /* XXX check sync modes */ 1072 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1073 if (fl->ifl_sds.ifsd_map == NULL) 1074 continue; 1075 bus_dmamap_sync(rxq->ifr_fl[i].ifl_buf_tag, 1076 fl->ifl_ifdi->idi_map, 1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1078 } 1079 /* 1080 * First part: import newly received packets. 1081 * 1082 * nm_i is the index of the next free slot in the netmap ring, 1083 * nic_i is the index of the next received packet in the NIC ring, 1084 * and they may differ in case if_init() has been called while 1085 * in netmap mode. For the receive ring we have 1086 * 1087 * nic_i = rxr->next_check; 1088 * nm_i = kring->nr_hwtail (previous) 1089 * and 1090 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1091 * 1092 * rxr->next_check is set to 0 on a ring reinit 1093 */ 1094 if (netmap_no_pendintr || force_update) { 1095 int crclen = iflib_crcstrip ? 0 : 4; 1096 int error, avail; 1097 1098 for (i = 0; i < rxq->ifr_nfl; i++) { 1099 fl = &rxq->ifr_fl[i]; 1100 nic_i = fl->ifl_cidx; 1101 nm_i = netmap_idx_n2k(kring, nic_i); 1102 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1103 for (n = 0; avail > 0; n++, avail--) { 1104 rxd_info_zero(&ri); 1105 ri.iri_frags = rxq->ifr_frags; 1106 ri.iri_qsidx = kring->ring_id; 1107 ri.iri_ifp = ctx->ifc_ifp; 1108 ri.iri_cidx = nic_i; 1109 1110 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1111 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1112 ring->slot[nm_i].flags = 0; 1113 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1114 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1115 nm_i = nm_next(nm_i, lim); 1116 nic_i = nm_next(nic_i, lim); 1117 } 1118 if (n) { /* update the state variables */ 1119 if (netmap_no_pendintr && !force_update) { 1120 /* diagnostics */ 1121 iflib_rx_miss ++; 1122 iflib_rx_miss_bufs += n; 1123 } 1124 fl->ifl_cidx = nic_i; 1125 kring->nr_hwtail = nm_i; 1126 } 1127 kring->nr_kflags &= ~NKR_PENDINTR; 1128 } 1129 } 1130 /* 1131 * Second part: skip past packets that userspace has released. 1132 * (kring->nr_hwcur to head excluded), 1133 * and make the buffers available for reception. 1134 * As usual nm_i is the index in the netmap ring, 1135 * nic_i is the index in the NIC ring, and 1136 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1137 */ 1138 /* XXX not sure how this will work with multiple free lists */ 1139 nm_i = kring->nr_hwcur; 1140 1141 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1142 } 1143 1144 static void 1145 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1146 { 1147 struct ifnet *ifp = na->ifp; 1148 if_ctx_t ctx = ifp->if_softc; 1149 1150 CTX_LOCK(ctx); 1151 if (onoff) { 1152 IFDI_INTR_ENABLE(ctx); 1153 } else { 1154 IFDI_INTR_DISABLE(ctx); 1155 } 1156 CTX_UNLOCK(ctx); 1157 } 1158 1159 1160 static int 1161 iflib_netmap_attach(if_ctx_t ctx) 1162 { 1163 struct netmap_adapter na; 1164 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1165 1166 bzero(&na, sizeof(na)); 1167 1168 na.ifp = ctx->ifc_ifp; 1169 na.na_flags = NAF_BDG_MAYSLEEP; 1170 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1171 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1172 1173 na.num_tx_desc = scctx->isc_ntxd[0]; 1174 na.num_rx_desc = scctx->isc_nrxd[0]; 1175 na.nm_txsync = iflib_netmap_txsync; 1176 na.nm_rxsync = iflib_netmap_rxsync; 1177 na.nm_register = iflib_netmap_register; 1178 na.nm_intr = iflib_netmap_intr; 1179 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1180 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1181 return (netmap_attach(&na)); 1182 } 1183 1184 static void 1185 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1186 { 1187 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1188 struct netmap_slot *slot; 1189 1190 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1191 if (slot == NULL) 1192 return; 1193 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1194 1195 /* 1196 * In netmap mode, set the map for the packet buffer. 1197 * NOTE: Some drivers (not this one) also need to set 1198 * the physical buffer address in the NIC ring. 1199 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1200 * netmap slot index, si 1201 */ 1202 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1203 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1204 NMB(na, slot + si)); 1205 } 1206 } 1207 1208 static void 1209 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1210 { 1211 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1212 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1213 struct netmap_slot *slot; 1214 uint32_t nm_i; 1215 1216 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1217 if (slot == NULL) 1218 return; 1219 nm_i = netmap_idx_n2k(kring, 0); 1220 netmap_fl_refill(rxq, kring, nm_i, true); 1221 } 1222 1223 static void 1224 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1225 { 1226 struct netmap_kring *kring; 1227 1228 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1229 1230 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1231 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1232 netmap_tx_irq(ctx->ifc_ifp, txqid); 1233 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1234 if (hz < 2000) 1235 *reset_on = 1; 1236 else 1237 *reset_on = hz / 1000; 1238 } 1239 } 1240 } 1241 1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1243 1244 #else 1245 #define iflib_netmap_txq_init(ctx, txq) 1246 #define iflib_netmap_rxq_init(ctx, rxq) 1247 #define iflib_netmap_detach(ifp) 1248 1249 #define iflib_netmap_attach(ctx) (0) 1250 #define netmap_rx_irq(ifp, qid, budget) (0) 1251 #define netmap_tx_irq(ifp, qid) do {} while (0) 1252 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1253 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iflib_gen_mac(if_ctx_t ctx) 1277 { 1278 struct thread *td; 1279 MD5_CTX mdctx; 1280 char uuid[HOSTUUIDLEN+1]; 1281 char buf[HOSTUUIDLEN+16]; 1282 uint8_t *mac; 1283 unsigned char digest[16]; 1284 1285 td = curthread; 1286 mac = ctx->ifc_mac; 1287 uuid[HOSTUUIDLEN] = 0; 1288 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1289 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1290 /* 1291 * Generate a pseudo-random, deterministic MAC 1292 * address based on the UUID and unit number. 1293 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1294 */ 1295 MD5Init(&mdctx); 1296 MD5Update(&mdctx, buf, strlen(buf)); 1297 MD5Final(digest, &mdctx); 1298 1299 mac[0] = 0x58; 1300 mac[1] = 0x9C; 1301 mac[2] = 0xFC; 1302 mac[3] = digest[0]; 1303 mac[4] = digest[1]; 1304 mac[5] = digest[2]; 1305 } 1306 1307 static void 1308 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1309 { 1310 iflib_fl_t fl; 1311 1312 fl = &rxq->ifr_fl[flid]; 1313 iru->iru_paddrs = fl->ifl_bus_addrs; 1314 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1315 iru->iru_idxs = fl->ifl_rxd_idxs; 1316 iru->iru_qsidx = rxq->ifr_id; 1317 iru->iru_buf_size = fl->ifl_buf_size; 1318 iru->iru_flidx = fl->ifl_id; 1319 } 1320 1321 static void 1322 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1323 { 1324 if (err) 1325 return; 1326 *(bus_addr_t *) arg = segs[0].ds_addr; 1327 } 1328 1329 int 1330 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1331 { 1332 int err; 1333 device_t dev = ctx->ifc_dev; 1334 1335 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1336 align, 0, /* alignment, bounds */ 1337 BUS_SPACE_MAXADDR, /* lowaddr */ 1338 BUS_SPACE_MAXADDR, /* highaddr */ 1339 NULL, NULL, /* filter, filterarg */ 1340 size, /* maxsize */ 1341 1, /* nsegments */ 1342 size, /* maxsegsize */ 1343 BUS_DMA_ALLOCNOW, /* flags */ 1344 NULL, /* lockfunc */ 1345 NULL, /* lockarg */ 1346 &dma->idi_tag); 1347 if (err) { 1348 device_printf(dev, 1349 "%s: bus_dma_tag_create failed: %d\n", 1350 __func__, err); 1351 goto fail_0; 1352 } 1353 1354 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1355 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1356 if (err) { 1357 device_printf(dev, 1358 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1359 __func__, (uintmax_t)size, err); 1360 goto fail_1; 1361 } 1362 1363 dma->idi_paddr = IF_BAD_DMA; 1364 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1365 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1366 if (err || dma->idi_paddr == IF_BAD_DMA) { 1367 device_printf(dev, 1368 "%s: bus_dmamap_load failed: %d\n", 1369 __func__, err); 1370 goto fail_2; 1371 } 1372 1373 dma->idi_size = size; 1374 return (0); 1375 1376 fail_2: 1377 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1378 fail_1: 1379 bus_dma_tag_destroy(dma->idi_tag); 1380 fail_0: 1381 dma->idi_tag = NULL; 1382 1383 return (err); 1384 } 1385 1386 int 1387 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1388 { 1389 if_shared_ctx_t sctx = ctx->ifc_sctx; 1390 1391 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1392 1393 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1394 } 1395 1396 int 1397 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1398 { 1399 int i, err; 1400 iflib_dma_info_t *dmaiter; 1401 1402 dmaiter = dmalist; 1403 for (i = 0; i < count; i++, dmaiter++) { 1404 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1405 break; 1406 } 1407 if (err) 1408 iflib_dma_free_multi(dmalist, i); 1409 return (err); 1410 } 1411 1412 void 1413 iflib_dma_free(iflib_dma_info_t dma) 1414 { 1415 if (dma->idi_tag == NULL) 1416 return; 1417 if (dma->idi_paddr != IF_BAD_DMA) { 1418 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1419 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1420 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1421 dma->idi_paddr = IF_BAD_DMA; 1422 } 1423 if (dma->idi_vaddr != NULL) { 1424 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1425 dma->idi_vaddr = NULL; 1426 } 1427 bus_dma_tag_destroy(dma->idi_tag); 1428 dma->idi_tag = NULL; 1429 } 1430 1431 void 1432 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1433 { 1434 int i; 1435 iflib_dma_info_t *dmaiter = dmalist; 1436 1437 for (i = 0; i < count; i++, dmaiter++) 1438 iflib_dma_free(*dmaiter); 1439 } 1440 1441 #ifdef EARLY_AP_STARTUP 1442 static const int iflib_started = 1; 1443 #else 1444 /* 1445 * We used to abuse the smp_started flag to decide if the queues have been 1446 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1447 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1448 * is set. Run a SYSINIT() strictly after that to just set a usable 1449 * completion flag. 1450 */ 1451 1452 static int iflib_started; 1453 1454 static void 1455 iflib_record_started(void *arg) 1456 { 1457 iflib_started = 1; 1458 } 1459 1460 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1461 iflib_record_started, NULL); 1462 #endif 1463 1464 static int 1465 iflib_fast_intr(void *arg) 1466 { 1467 iflib_filter_info_t info = arg; 1468 struct grouptask *gtask = info->ifi_task; 1469 if (!iflib_started) 1470 return (FILTER_HANDLED); 1471 1472 DBG_COUNTER_INC(fast_intrs); 1473 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1474 return (FILTER_HANDLED); 1475 1476 GROUPTASK_ENQUEUE(gtask); 1477 return (FILTER_HANDLED); 1478 } 1479 1480 static int 1481 iflib_fast_intr_rxtx(void *arg) 1482 { 1483 iflib_filter_info_t info = arg; 1484 struct grouptask *gtask = info->ifi_task; 1485 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1486 if_ctx_t ctx = NULL;; 1487 int i, cidx; 1488 1489 if (!iflib_started) 1490 return (FILTER_HANDLED); 1491 1492 DBG_COUNTER_INC(fast_intrs); 1493 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1494 return (FILTER_HANDLED); 1495 1496 MPASS(rxq->ifr_ntxqirq); 1497 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1498 qidx_t txqid = rxq->ifr_txqid[i]; 1499 1500 ctx = rxq->ifr_ctx; 1501 1502 bus_dmamap_sync(rxq->ifr_ifdi->idi_tag, rxq->ifr_ifdi->idi_map, 1503 BUS_DMASYNC_POSTREAD); 1504 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1505 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1506 continue; 1507 } 1508 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1509 } 1510 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1511 cidx = rxq->ifr_cq_cidx; 1512 else 1513 cidx = rxq->ifr_fl[0].ifl_cidx; 1514 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1515 GROUPTASK_ENQUEUE(gtask); 1516 else { 1517 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1518 DBG_COUNTER_INC(rx_intr_enables); 1519 } 1520 return (FILTER_HANDLED); 1521 } 1522 1523 1524 static int 1525 iflib_fast_intr_ctx(void *arg) 1526 { 1527 iflib_filter_info_t info = arg; 1528 struct grouptask *gtask = info->ifi_task; 1529 1530 if (!iflib_started) 1531 return (FILTER_HANDLED); 1532 1533 DBG_COUNTER_INC(fast_intrs); 1534 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1535 return (FILTER_HANDLED); 1536 1537 GROUPTASK_ENQUEUE(gtask); 1538 return (FILTER_HANDLED); 1539 } 1540 1541 static int 1542 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1543 driver_filter_t filter, driver_intr_t handler, void *arg, 1544 const char *name) 1545 { 1546 int rc, flags; 1547 struct resource *res; 1548 void *tag = NULL; 1549 device_t dev = ctx->ifc_dev; 1550 1551 flags = RF_ACTIVE; 1552 if (ctx->ifc_flags & IFC_LEGACY) 1553 flags |= RF_SHAREABLE; 1554 MPASS(rid < 512); 1555 irq->ii_rid = rid; 1556 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1557 if (res == NULL) { 1558 device_printf(dev, 1559 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1560 return (ENOMEM); 1561 } 1562 irq->ii_res = res; 1563 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1564 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1565 filter, handler, arg, &tag); 1566 if (rc != 0) { 1567 device_printf(dev, 1568 "failed to setup interrupt for rid %d, name %s: %d\n", 1569 rid, name ? name : "unknown", rc); 1570 return (rc); 1571 } else if (name) 1572 bus_describe_intr(dev, res, tag, "%s", name); 1573 1574 irq->ii_tag = tag; 1575 return (0); 1576 } 1577 1578 1579 /********************************************************************* 1580 * 1581 * Allocate DMA resources for TX buffers as well as memory for the TX 1582 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1583 * iflib_sw_tx_desc_array structure, storing all the information that 1584 * is needed to transmit a packet on the wire. This is called only 1585 * once at attach, setup is done every reset. 1586 * 1587 **********************************************************************/ 1588 static int 1589 iflib_txsd_alloc(iflib_txq_t txq) 1590 { 1591 if_ctx_t ctx = txq->ift_ctx; 1592 if_shared_ctx_t sctx = ctx->ifc_sctx; 1593 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1594 device_t dev = ctx->ifc_dev; 1595 bus_size_t tsomaxsize; 1596 int err, nsegments, ntsosegments; 1597 bool tso; 1598 1599 nsegments = scctx->isc_tx_nsegments; 1600 ntsosegments = scctx->isc_tx_tso_segments_max; 1601 tsomaxsize = scctx->isc_tx_tso_size_max; 1602 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1603 tsomaxsize += sizeof(struct ether_vlan_header); 1604 MPASS(scctx->isc_ntxd[0] > 0); 1605 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1606 MPASS(nsegments > 0); 1607 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1608 MPASS(ntsosegments > 0); 1609 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1610 } 1611 1612 /* 1613 * Set up DMA tags for TX buffers. 1614 */ 1615 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1616 1, 0, /* alignment, bounds */ 1617 BUS_SPACE_MAXADDR, /* lowaddr */ 1618 BUS_SPACE_MAXADDR, /* highaddr */ 1619 NULL, NULL, /* filter, filterarg */ 1620 sctx->isc_tx_maxsize, /* maxsize */ 1621 nsegments, /* nsegments */ 1622 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1623 0, /* flags */ 1624 NULL, /* lockfunc */ 1625 NULL, /* lockfuncarg */ 1626 &txq->ift_buf_tag))) { 1627 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1628 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1629 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1630 goto fail; 1631 } 1632 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1633 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1634 1, 0, /* alignment, bounds */ 1635 BUS_SPACE_MAXADDR, /* lowaddr */ 1636 BUS_SPACE_MAXADDR, /* highaddr */ 1637 NULL, NULL, /* filter, filterarg */ 1638 tsomaxsize, /* maxsize */ 1639 ntsosegments, /* nsegments */ 1640 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1641 0, /* flags */ 1642 NULL, /* lockfunc */ 1643 NULL, /* lockfuncarg */ 1644 &txq->ift_tso_buf_tag))) { 1645 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1646 err); 1647 goto fail; 1648 } 1649 1650 /* Allocate memory for the TX mbuf map. */ 1651 if (!(txq->ift_sds.ifsd_m = 1652 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1653 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1654 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1655 err = ENOMEM; 1656 goto fail; 1657 } 1658 1659 /* 1660 * Create the DMA maps for TX buffers. 1661 */ 1662 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1663 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1664 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1665 device_printf(dev, 1666 "Unable to allocate TX buffer DMA map memory\n"); 1667 err = ENOMEM; 1668 goto fail; 1669 } 1670 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1671 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1672 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1673 device_printf(dev, 1674 "Unable to allocate TSO TX buffer map memory\n"); 1675 err = ENOMEM; 1676 goto fail; 1677 } 1678 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1679 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1680 &txq->ift_sds.ifsd_map[i]); 1681 if (err != 0) { 1682 device_printf(dev, "Unable to create TX DMA map\n"); 1683 goto fail; 1684 } 1685 if (!tso) 1686 continue; 1687 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1688 &txq->ift_sds.ifsd_tso_map[i]); 1689 if (err != 0) { 1690 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1691 goto fail; 1692 } 1693 } 1694 return (0); 1695 fail: 1696 /* We free all, it handles case where we are in the middle */ 1697 iflib_tx_structures_free(ctx); 1698 return (err); 1699 } 1700 1701 static void 1702 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1703 { 1704 bus_dmamap_t map; 1705 1706 map = NULL; 1707 if (txq->ift_sds.ifsd_map != NULL) 1708 map = txq->ift_sds.ifsd_map[i]; 1709 if (map != NULL) { 1710 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1711 bus_dmamap_unload(txq->ift_buf_tag, map); 1712 bus_dmamap_destroy(txq->ift_buf_tag, map); 1713 txq->ift_sds.ifsd_map[i] = NULL; 1714 } 1715 1716 map = NULL; 1717 if (txq->ift_sds.ifsd_tso_map != NULL) 1718 map = txq->ift_sds.ifsd_tso_map[i]; 1719 if (map != NULL) { 1720 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1721 BUS_DMASYNC_POSTWRITE); 1722 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1723 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1724 txq->ift_sds.ifsd_tso_map[i] = NULL; 1725 } 1726 } 1727 1728 static void 1729 iflib_txq_destroy(iflib_txq_t txq) 1730 { 1731 if_ctx_t ctx = txq->ift_ctx; 1732 1733 for (int i = 0; i < txq->ift_size; i++) 1734 iflib_txsd_destroy(ctx, txq, i); 1735 if (txq->ift_sds.ifsd_map != NULL) { 1736 free(txq->ift_sds.ifsd_map, M_IFLIB); 1737 txq->ift_sds.ifsd_map = NULL; 1738 } 1739 if (txq->ift_sds.ifsd_tso_map != NULL) { 1740 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1741 txq->ift_sds.ifsd_tso_map = NULL; 1742 } 1743 if (txq->ift_sds.ifsd_m != NULL) { 1744 free(txq->ift_sds.ifsd_m, M_IFLIB); 1745 txq->ift_sds.ifsd_m = NULL; 1746 } 1747 if (txq->ift_buf_tag != NULL) { 1748 bus_dma_tag_destroy(txq->ift_buf_tag); 1749 txq->ift_buf_tag = NULL; 1750 } 1751 if (txq->ift_tso_buf_tag != NULL) { 1752 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1753 txq->ift_tso_buf_tag = NULL; 1754 } 1755 } 1756 1757 static void 1758 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1759 { 1760 struct mbuf **mp; 1761 1762 mp = &txq->ift_sds.ifsd_m[i]; 1763 if (*mp == NULL) 1764 return; 1765 1766 if (txq->ift_sds.ifsd_map != NULL) { 1767 bus_dmamap_sync(txq->ift_buf_tag, 1768 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1769 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1770 } 1771 if (txq->ift_sds.ifsd_tso_map != NULL) { 1772 bus_dmamap_sync(txq->ift_tso_buf_tag, 1773 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(txq->ift_tso_buf_tag, 1775 txq->ift_sds.ifsd_tso_map[i]); 1776 } 1777 m_free(*mp); 1778 DBG_COUNTER_INC(tx_frees); 1779 *mp = NULL; 1780 } 1781 1782 static int 1783 iflib_txq_setup(iflib_txq_t txq) 1784 { 1785 if_ctx_t ctx = txq->ift_ctx; 1786 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1787 if_shared_ctx_t sctx = ctx->ifc_sctx; 1788 iflib_dma_info_t di; 1789 int i; 1790 1791 /* Set number of descriptors available */ 1792 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1793 /* XXX make configurable */ 1794 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1795 1796 /* Reset indices */ 1797 txq->ift_cidx_processed = 0; 1798 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1799 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1800 1801 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1802 bzero((void *)di->idi_vaddr, di->idi_size); 1803 1804 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1805 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1806 bus_dmamap_sync(di->idi_tag, di->idi_map, 1807 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1808 return (0); 1809 } 1810 1811 /********************************************************************* 1812 * 1813 * Allocate DMA resources for RX buffers as well as memory for the RX 1814 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1815 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1816 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1817 * Since we use use one entry in iflib_sw_rx_desc_array per received 1818 * packet, the maximum number of entries we'll need is equal to the 1819 * number of hardware receive descriptors that we've allocated. 1820 * 1821 **********************************************************************/ 1822 static int 1823 iflib_rxsd_alloc(iflib_rxq_t rxq) 1824 { 1825 if_ctx_t ctx = rxq->ifr_ctx; 1826 if_shared_ctx_t sctx = ctx->ifc_sctx; 1827 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1828 device_t dev = ctx->ifc_dev; 1829 iflib_fl_t fl; 1830 int err; 1831 1832 MPASS(scctx->isc_nrxd[0] > 0); 1833 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1834 1835 fl = rxq->ifr_fl; 1836 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1837 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1838 /* Set up DMA tag for RX buffers. */ 1839 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1840 1, 0, /* alignment, bounds */ 1841 BUS_SPACE_MAXADDR, /* lowaddr */ 1842 BUS_SPACE_MAXADDR, /* highaddr */ 1843 NULL, NULL, /* filter, filterarg */ 1844 sctx->isc_rx_maxsize, /* maxsize */ 1845 sctx->isc_rx_nsegments, /* nsegments */ 1846 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1847 0, /* flags */ 1848 NULL, /* lockfunc */ 1849 NULL, /* lockarg */ 1850 &fl->ifl_buf_tag); 1851 if (err) { 1852 device_printf(dev, 1853 "Unable to allocate RX DMA tag: %d\n", err); 1854 goto fail; 1855 } 1856 1857 /* Allocate memory for the RX mbuf map. */ 1858 if (!(fl->ifl_sds.ifsd_m = 1859 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1860 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1861 device_printf(dev, 1862 "Unable to allocate RX mbuf map memory\n"); 1863 err = ENOMEM; 1864 goto fail; 1865 } 1866 1867 /* Allocate memory for the direct RX cluster pointer map. */ 1868 if (!(fl->ifl_sds.ifsd_cl = 1869 (caddr_t *) malloc(sizeof(caddr_t) * 1870 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1871 device_printf(dev, 1872 "Unable to allocate RX cluster map memory\n"); 1873 err = ENOMEM; 1874 goto fail; 1875 } 1876 1877 /* Allocate memory for the RX cluster bus address map. */ 1878 if (!(fl->ifl_sds.ifsd_ba = 1879 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1880 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1881 device_printf(dev, 1882 "Unable to allocate RX bus address map memory\n"); 1883 err = ENOMEM; 1884 goto fail; 1885 } 1886 1887 /* 1888 * Create the DMA maps for RX buffers. 1889 */ 1890 if (!(fl->ifl_sds.ifsd_map = 1891 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1892 device_printf(dev, 1893 "Unable to allocate RX buffer DMA map memory\n"); 1894 err = ENOMEM; 1895 goto fail; 1896 } 1897 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1898 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1899 &fl->ifl_sds.ifsd_map[i]); 1900 if (err != 0) { 1901 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1902 goto fail; 1903 } 1904 } 1905 } 1906 return (0); 1907 1908 fail: 1909 iflib_rx_structures_free(ctx); 1910 return (err); 1911 } 1912 1913 1914 /* 1915 * Internal service routines 1916 */ 1917 1918 struct rxq_refill_cb_arg { 1919 int error; 1920 bus_dma_segment_t seg; 1921 int nseg; 1922 }; 1923 1924 static void 1925 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1926 { 1927 struct rxq_refill_cb_arg *cb_arg = arg; 1928 1929 cb_arg->error = error; 1930 cb_arg->seg = segs[0]; 1931 cb_arg->nseg = nseg; 1932 } 1933 1934 /** 1935 * rxq_refill - refill an rxq free-buffer list 1936 * @ctx: the iflib context 1937 * @rxq: the free-list to refill 1938 * @n: the number of new buffers to allocate 1939 * 1940 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1941 * The caller must assure that @n does not exceed the queue's capacity. 1942 */ 1943 static void 1944 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1945 { 1946 struct if_rxd_update iru; 1947 struct rxq_refill_cb_arg cb_arg; 1948 struct mbuf *m; 1949 caddr_t cl, *sd_cl; 1950 struct mbuf **sd_m; 1951 bus_dmamap_t *sd_map; 1952 bus_addr_t bus_addr, *sd_ba; 1953 int err, frag_idx, i, idx, n, pidx; 1954 qidx_t credits; 1955 1956 sd_m = fl->ifl_sds.ifsd_m; 1957 sd_map = fl->ifl_sds.ifsd_map; 1958 sd_cl = fl->ifl_sds.ifsd_cl; 1959 sd_ba = fl->ifl_sds.ifsd_ba; 1960 pidx = fl->ifl_pidx; 1961 idx = pidx; 1962 frag_idx = fl->ifl_fragidx; 1963 credits = fl->ifl_credits; 1964 1965 i = 0; 1966 n = count; 1967 MPASS(n > 0); 1968 MPASS(credits + n <= fl->ifl_size); 1969 1970 if (pidx < fl->ifl_cidx) 1971 MPASS(pidx + n <= fl->ifl_cidx); 1972 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1973 MPASS(fl->ifl_gen == 0); 1974 if (pidx > fl->ifl_cidx) 1975 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1976 1977 DBG_COUNTER_INC(fl_refills); 1978 if (n > 8) 1979 DBG_COUNTER_INC(fl_refills_large); 1980 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1981 while (n--) { 1982 /* 1983 * We allocate an uninitialized mbuf + cluster, mbuf is 1984 * initialized after rx. 1985 * 1986 * If the cluster is still set then we know a minimum sized packet was received 1987 */ 1988 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1989 &frag_idx); 1990 if (frag_idx < 0) 1991 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1992 MPASS(frag_idx >= 0); 1993 if ((cl = sd_cl[frag_idx]) == NULL) { 1994 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1995 break; 1996 1997 cb_arg.error = 0; 1998 MPASS(sd_map != NULL); 1999 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2000 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2001 BUS_DMA_NOWAIT); 2002 if (err != 0 || cb_arg.error) { 2003 /* 2004 * !zone_pack ? 2005 */ 2006 if (fl->ifl_zone == zone_pack) 2007 uma_zfree(fl->ifl_zone, cl); 2008 break; 2009 } 2010 2011 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2012 BUS_DMASYNC_PREREAD); 2013 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2014 sd_cl[frag_idx] = cl; 2015 #if MEMORY_LOGGING 2016 fl->ifl_cl_enqueued++; 2017 #endif 2018 } else { 2019 bus_addr = sd_ba[frag_idx]; 2020 } 2021 2022 MPASS(sd_m[frag_idx] == NULL); 2023 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2024 break; 2025 } 2026 sd_m[frag_idx] = m; 2027 bit_set(fl->ifl_rx_bitmap, frag_idx); 2028 #if MEMORY_LOGGING 2029 fl->ifl_m_enqueued++; 2030 #endif 2031 2032 DBG_COUNTER_INC(rx_allocs); 2033 fl->ifl_rxd_idxs[i] = frag_idx; 2034 fl->ifl_bus_addrs[i] = bus_addr; 2035 fl->ifl_vm_addrs[i] = cl; 2036 credits++; 2037 i++; 2038 MPASS(credits <= fl->ifl_size); 2039 if (++idx == fl->ifl_size) { 2040 fl->ifl_gen = 1; 2041 idx = 0; 2042 } 2043 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2044 iru.iru_pidx = pidx; 2045 iru.iru_count = i; 2046 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2047 i = 0; 2048 pidx = idx; 2049 fl->ifl_pidx = idx; 2050 fl->ifl_credits = credits; 2051 } 2052 } 2053 2054 if (i) { 2055 iru.iru_pidx = pidx; 2056 iru.iru_count = i; 2057 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2058 fl->ifl_pidx = idx; 2059 fl->ifl_credits = credits; 2060 } 2061 DBG_COUNTER_INC(rxd_flush); 2062 if (fl->ifl_pidx == 0) 2063 pidx = fl->ifl_size - 1; 2064 else 2065 pidx = fl->ifl_pidx - 1; 2066 2067 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2068 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2069 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2070 fl->ifl_fragidx = frag_idx; 2071 } 2072 2073 static __inline void 2074 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2075 { 2076 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2077 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2078 #ifdef INVARIANTS 2079 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2080 #endif 2081 2082 MPASS(fl->ifl_credits <= fl->ifl_size); 2083 MPASS(reclaimable == delta); 2084 2085 if (reclaimable > 0) 2086 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2087 } 2088 2089 uint8_t 2090 iflib_in_detach(if_ctx_t ctx) 2091 { 2092 bool in_detach; 2093 STATE_LOCK(ctx); 2094 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2095 STATE_UNLOCK(ctx); 2096 return (in_detach); 2097 } 2098 2099 static void 2100 iflib_fl_bufs_free(iflib_fl_t fl) 2101 { 2102 iflib_dma_info_t idi = fl->ifl_ifdi; 2103 bus_dmamap_t sd_map; 2104 uint32_t i; 2105 2106 for (i = 0; i < fl->ifl_size; i++) { 2107 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2108 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2109 2110 if (*sd_cl != NULL) { 2111 sd_map = fl->ifl_sds.ifsd_map[i]; 2112 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2113 BUS_DMASYNC_POSTREAD); 2114 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2115 if (*sd_cl != NULL) 2116 uma_zfree(fl->ifl_zone, *sd_cl); 2117 // XXX: Should this get moved out? 2118 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2119 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2120 if (*sd_m != NULL) { 2121 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2122 uma_zfree(zone_mbuf, *sd_m); 2123 } 2124 } else { 2125 MPASS(*sd_cl == NULL); 2126 MPASS(*sd_m == NULL); 2127 } 2128 #if MEMORY_LOGGING 2129 fl->ifl_m_dequeued++; 2130 fl->ifl_cl_dequeued++; 2131 #endif 2132 *sd_cl = NULL; 2133 *sd_m = NULL; 2134 } 2135 #ifdef INVARIANTS 2136 for (i = 0; i < fl->ifl_size; i++) { 2137 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2138 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2139 } 2140 #endif 2141 /* 2142 * Reset free list values 2143 */ 2144 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2145 bzero(idi->idi_vaddr, idi->idi_size); 2146 } 2147 2148 /********************************************************************* 2149 * 2150 * Initialize a receive ring and its buffers. 2151 * 2152 **********************************************************************/ 2153 static int 2154 iflib_fl_setup(iflib_fl_t fl) 2155 { 2156 iflib_rxq_t rxq = fl->ifl_rxq; 2157 if_ctx_t ctx = rxq->ifr_ctx; 2158 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2159 2160 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2161 /* 2162 ** Free current RX buffer structs and their mbufs 2163 */ 2164 iflib_fl_bufs_free(fl); 2165 /* Now replenish the mbufs */ 2166 MPASS(fl->ifl_credits == 0); 2167 /* 2168 * XXX don't set the max_frame_size to larger 2169 * than the hardware can handle 2170 */ 2171 if (sctx->isc_max_frame_size <= 2048) 2172 fl->ifl_buf_size = MCLBYTES; 2173 #ifndef CONTIGMALLOC_WORKS 2174 else 2175 fl->ifl_buf_size = MJUMPAGESIZE; 2176 #else 2177 else if (sctx->isc_max_frame_size <= 4096) 2178 fl->ifl_buf_size = MJUMPAGESIZE; 2179 else if (sctx->isc_max_frame_size <= 9216) 2180 fl->ifl_buf_size = MJUM9BYTES; 2181 else 2182 fl->ifl_buf_size = MJUM16BYTES; 2183 #endif 2184 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2185 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2186 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2187 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2188 2189 2190 /* avoid pre-allocating zillions of clusters to an idle card 2191 * potentially speeding up attach 2192 */ 2193 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2194 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2195 if (min(128, fl->ifl_size) != fl->ifl_credits) 2196 return (ENOBUFS); 2197 /* 2198 * handle failure 2199 */ 2200 MPASS(rxq != NULL); 2201 MPASS(fl->ifl_ifdi != NULL); 2202 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2203 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2204 return (0); 2205 } 2206 2207 /********************************************************************* 2208 * 2209 * Free receive ring data structures 2210 * 2211 **********************************************************************/ 2212 static void 2213 iflib_rx_sds_free(iflib_rxq_t rxq) 2214 { 2215 iflib_fl_t fl; 2216 int i, j; 2217 2218 if (rxq->ifr_fl != NULL) { 2219 for (i = 0; i < rxq->ifr_nfl; i++) { 2220 fl = &rxq->ifr_fl[i]; 2221 if (fl->ifl_buf_tag != NULL) { 2222 if (fl->ifl_sds.ifsd_map != NULL) { 2223 for (j = 0; j < fl->ifl_size; j++) { 2224 if (fl->ifl_sds.ifsd_map[j] == 2225 NULL) 2226 continue; 2227 bus_dmamap_sync( 2228 fl->ifl_buf_tag, 2229 fl->ifl_sds.ifsd_map[j], 2230 BUS_DMASYNC_POSTREAD); 2231 bus_dmamap_unload( 2232 fl->ifl_buf_tag, 2233 fl->ifl_sds.ifsd_map[j]); 2234 } 2235 } 2236 bus_dma_tag_destroy(fl->ifl_buf_tag); 2237 fl->ifl_buf_tag = NULL; 2238 } 2239 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2240 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2241 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2242 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2243 fl->ifl_sds.ifsd_m = NULL; 2244 fl->ifl_sds.ifsd_cl = NULL; 2245 fl->ifl_sds.ifsd_ba = NULL; 2246 fl->ifl_sds.ifsd_map = NULL; 2247 } 2248 free(rxq->ifr_fl, M_IFLIB); 2249 rxq->ifr_fl = NULL; 2250 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2251 } 2252 } 2253 2254 /* 2255 * MI independent logic 2256 * 2257 */ 2258 static void 2259 iflib_timer(void *arg) 2260 { 2261 iflib_txq_t txq = arg; 2262 if_ctx_t ctx = txq->ift_ctx; 2263 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2264 uint64_t this_tick = ticks; 2265 uint32_t reset_on = hz / 2; 2266 2267 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2268 return; 2269 /* 2270 ** Check on the state of the TX queue(s), this 2271 ** can be done without the lock because its RO 2272 ** and the HUNG state will be static if set. 2273 */ 2274 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2275 txq->ift_last_timer_tick = this_tick; 2276 IFDI_TIMER(ctx, txq->ift_id); 2277 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2278 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2279 (sctx->isc_pause_frames == 0))) 2280 goto hung; 2281 2282 if (ifmp_ring_is_stalled(txq->ift_br)) 2283 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2284 txq->ift_cleaned_prev = txq->ift_cleaned; 2285 } 2286 #ifdef DEV_NETMAP 2287 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2288 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2289 #endif 2290 /* handle any laggards */ 2291 if (txq->ift_db_pending) 2292 GROUPTASK_ENQUEUE(&txq->ift_task); 2293 2294 sctx->isc_pause_frames = 0; 2295 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2296 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2297 return; 2298 hung: 2299 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2300 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2301 STATE_LOCK(ctx); 2302 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2303 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2304 iflib_admin_intr_deferred(ctx); 2305 STATE_UNLOCK(ctx); 2306 } 2307 2308 static void 2309 iflib_init_locked(if_ctx_t ctx) 2310 { 2311 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2312 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2313 if_t ifp = ctx->ifc_ifp; 2314 iflib_fl_t fl; 2315 iflib_txq_t txq; 2316 iflib_rxq_t rxq; 2317 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2318 2319 2320 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2321 IFDI_INTR_DISABLE(ctx); 2322 2323 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2324 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2325 /* Set hardware offload abilities */ 2326 if_clearhwassist(ifp); 2327 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2328 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2329 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2330 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2331 if (if_getcapenable(ifp) & IFCAP_TSO4) 2332 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2333 if (if_getcapenable(ifp) & IFCAP_TSO6) 2334 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2335 2336 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2337 CALLOUT_LOCK(txq); 2338 callout_stop(&txq->ift_timer); 2339 CALLOUT_UNLOCK(txq); 2340 iflib_netmap_txq_init(ctx, txq); 2341 } 2342 #ifdef INVARIANTS 2343 i = if_getdrvflags(ifp); 2344 #endif 2345 IFDI_INIT(ctx); 2346 MPASS(if_getdrvflags(ifp) == i); 2347 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2348 /* XXX this should really be done on a per-queue basis */ 2349 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2350 MPASS(rxq->ifr_id == i); 2351 iflib_netmap_rxq_init(ctx, rxq); 2352 continue; 2353 } 2354 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2355 if (iflib_fl_setup(fl)) { 2356 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2357 goto done; 2358 } 2359 } 2360 } 2361 done: 2362 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2363 IFDI_INTR_ENABLE(ctx); 2364 txq = ctx->ifc_txqs; 2365 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2366 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2367 txq->ift_timer.c_cpu); 2368 } 2369 2370 static int 2371 iflib_media_change(if_t ifp) 2372 { 2373 if_ctx_t ctx = if_getsoftc(ifp); 2374 int err; 2375 2376 CTX_LOCK(ctx); 2377 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2378 iflib_init_locked(ctx); 2379 CTX_UNLOCK(ctx); 2380 return (err); 2381 } 2382 2383 static void 2384 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2385 { 2386 if_ctx_t ctx = if_getsoftc(ifp); 2387 2388 CTX_LOCK(ctx); 2389 IFDI_UPDATE_ADMIN_STATUS(ctx); 2390 IFDI_MEDIA_STATUS(ctx, ifmr); 2391 CTX_UNLOCK(ctx); 2392 } 2393 2394 void 2395 iflib_stop(if_ctx_t ctx) 2396 { 2397 iflib_txq_t txq = ctx->ifc_txqs; 2398 iflib_rxq_t rxq = ctx->ifc_rxqs; 2399 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2400 if_shared_ctx_t sctx = ctx->ifc_sctx; 2401 iflib_dma_info_t di; 2402 iflib_fl_t fl; 2403 int i, j; 2404 2405 /* Tell the stack that the interface is no longer active */ 2406 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2407 2408 IFDI_INTR_DISABLE(ctx); 2409 DELAY(1000); 2410 IFDI_STOP(ctx); 2411 DELAY(1000); 2412 2413 iflib_debug_reset(); 2414 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2415 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2416 /* make sure all transmitters have completed before proceeding XXX */ 2417 2418 CALLOUT_LOCK(txq); 2419 callout_stop(&txq->ift_timer); 2420 CALLOUT_UNLOCK(txq); 2421 2422 /* clean any enqueued buffers */ 2423 iflib_ifmp_purge(txq); 2424 /* Free any existing tx buffers. */ 2425 for (j = 0; j < txq->ift_size; j++) { 2426 iflib_txsd_free(ctx, txq, j); 2427 } 2428 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2429 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2430 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2431 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2432 txq->ift_pullups = 0; 2433 ifmp_ring_reset_stats(txq->ift_br); 2434 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2435 bzero((void *)di->idi_vaddr, di->idi_size); 2436 } 2437 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2438 /* make sure all transmitters have completed before proceeding XXX */ 2439 2440 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2441 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2442 bzero((void *)di->idi_vaddr, di->idi_size); 2443 /* also resets the free lists pidx/cidx */ 2444 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2445 iflib_fl_bufs_free(fl); 2446 } 2447 } 2448 2449 static inline caddr_t 2450 calc_next_rxd(iflib_fl_t fl, int cidx) 2451 { 2452 qidx_t size; 2453 int nrxd; 2454 caddr_t start, end, cur, next; 2455 2456 nrxd = fl->ifl_size; 2457 size = fl->ifl_rxd_size; 2458 start = fl->ifl_ifdi->idi_vaddr; 2459 2460 if (__predict_false(size == 0)) 2461 return (start); 2462 cur = start + size*cidx; 2463 end = start + size*nrxd; 2464 next = CACHE_PTR_NEXT(cur); 2465 return (next < end ? next : start); 2466 } 2467 2468 static inline void 2469 prefetch_pkts(iflib_fl_t fl, int cidx) 2470 { 2471 int nextptr; 2472 int nrxd = fl->ifl_size; 2473 caddr_t next_rxd; 2474 2475 2476 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2477 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2478 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2479 next_rxd = calc_next_rxd(fl, cidx); 2480 prefetch(next_rxd); 2481 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2482 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2483 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2484 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2485 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2486 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2487 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2488 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2489 } 2490 2491 static void 2492 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2493 { 2494 int flid, cidx; 2495 bus_dmamap_t map; 2496 iflib_fl_t fl; 2497 iflib_dma_info_t di; 2498 int next; 2499 2500 map = NULL; 2501 flid = irf->irf_flid; 2502 cidx = irf->irf_idx; 2503 fl = &rxq->ifr_fl[flid]; 2504 sd->ifsd_fl = fl; 2505 sd->ifsd_cidx = cidx; 2506 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2507 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2508 fl->ifl_credits--; 2509 #if MEMORY_LOGGING 2510 fl->ifl_m_dequeued++; 2511 #endif 2512 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2513 prefetch_pkts(fl, cidx); 2514 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2515 prefetch(&fl->ifl_sds.ifsd_map[next]); 2516 map = fl->ifl_sds.ifsd_map[cidx]; 2517 di = fl->ifl_ifdi; 2518 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2519 2520 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2521 MPASS(fl->ifl_cidx == cidx); 2522 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2523 if (unload) 2524 bus_dmamap_unload(fl->ifl_buf_tag, map); 2525 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2526 if (__predict_false(fl->ifl_cidx == 0)) 2527 fl->ifl_gen = 0; 2528 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2530 bit_clear(fl->ifl_rx_bitmap, cidx); 2531 } 2532 2533 static struct mbuf * 2534 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2535 { 2536 int i, padlen , flags; 2537 struct mbuf *m, *mh, *mt; 2538 caddr_t cl; 2539 2540 i = 0; 2541 mh = NULL; 2542 do { 2543 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2544 2545 MPASS(*sd->ifsd_cl != NULL); 2546 MPASS(*sd->ifsd_m != NULL); 2547 2548 /* Don't include zero-length frags */ 2549 if (ri->iri_frags[i].irf_len == 0) { 2550 /* XXX we can save the cluster here, but not the mbuf */ 2551 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2552 m_free(*sd->ifsd_m); 2553 *sd->ifsd_m = NULL; 2554 continue; 2555 } 2556 m = *sd->ifsd_m; 2557 *sd->ifsd_m = NULL; 2558 if (mh == NULL) { 2559 flags = M_PKTHDR|M_EXT; 2560 mh = mt = m; 2561 padlen = ri->iri_pad; 2562 } else { 2563 flags = M_EXT; 2564 mt->m_next = m; 2565 mt = m; 2566 /* assuming padding is only on the first fragment */ 2567 padlen = 0; 2568 } 2569 cl = *sd->ifsd_cl; 2570 *sd->ifsd_cl = NULL; 2571 2572 /* Can these two be made one ? */ 2573 m_init(m, M_NOWAIT, MT_DATA, flags); 2574 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2575 /* 2576 * These must follow m_init and m_cljset 2577 */ 2578 m->m_data += padlen; 2579 ri->iri_len -= padlen; 2580 m->m_len = ri->iri_frags[i].irf_len; 2581 } while (++i < ri->iri_nfrags); 2582 2583 return (mh); 2584 } 2585 2586 /* 2587 * Process one software descriptor 2588 */ 2589 static struct mbuf * 2590 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2591 { 2592 struct if_rxsd sd; 2593 struct mbuf *m; 2594 2595 /* should I merge this back in now that the two paths are basically duplicated? */ 2596 if (ri->iri_nfrags == 1 && 2597 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2598 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2599 m = *sd.ifsd_m; 2600 *sd.ifsd_m = NULL; 2601 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2602 #ifndef __NO_STRICT_ALIGNMENT 2603 if (!IP_ALIGNED(m)) 2604 m->m_data += 2; 2605 #endif 2606 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2607 bus_dmamap_sync(rxq->ifr_fl->ifl_buf_tag, 2608 rxq->ifr_fl->ifl_sds.ifsd_map[ri->iri_frags[0].irf_idx], 2609 BUS_DMASYNC_PREREAD); 2610 m->m_len = ri->iri_frags[0].irf_len; 2611 } else { 2612 m = assemble_segments(rxq, ri, &sd); 2613 } 2614 m->m_pkthdr.len = ri->iri_len; 2615 m->m_pkthdr.rcvif = ri->iri_ifp; 2616 m->m_flags |= ri->iri_flags; 2617 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2618 m->m_pkthdr.flowid = ri->iri_flowid; 2619 M_HASHTYPE_SET(m, ri->iri_rsstype); 2620 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2621 m->m_pkthdr.csum_data = ri->iri_csum_data; 2622 return (m); 2623 } 2624 2625 #if defined(INET6) || defined(INET) 2626 static void 2627 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2628 { 2629 CURVNET_SET(lc->ifp->if_vnet); 2630 #if defined(INET6) 2631 *v6 = VNET(ip6_forwarding); 2632 #endif 2633 #if defined(INET) 2634 *v4 = VNET(ipforwarding); 2635 #endif 2636 CURVNET_RESTORE(); 2637 } 2638 2639 /* 2640 * Returns true if it's possible this packet could be LROed. 2641 * if it returns false, it is guaranteed that tcp_lro_rx() 2642 * would not return zero. 2643 */ 2644 static bool 2645 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2646 { 2647 struct ether_header *eh; 2648 uint16_t eh_type; 2649 2650 eh = mtod(m, struct ether_header *); 2651 eh_type = ntohs(eh->ether_type); 2652 switch (eh_type) { 2653 #if defined(INET6) 2654 case ETHERTYPE_IPV6: 2655 return !v6_forwarding; 2656 #endif 2657 #if defined (INET) 2658 case ETHERTYPE_IP: 2659 return !v4_forwarding; 2660 #endif 2661 } 2662 2663 return false; 2664 } 2665 #else 2666 static void 2667 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2668 { 2669 } 2670 #endif 2671 2672 static bool 2673 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2674 { 2675 if_ctx_t ctx = rxq->ifr_ctx; 2676 if_shared_ctx_t sctx = ctx->ifc_sctx; 2677 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2678 iflib_dma_info_t di; 2679 int avail, i; 2680 qidx_t *cidxp; 2681 struct if_rxd_info ri; 2682 int err, budget_left, rx_bytes, rx_pkts; 2683 iflib_fl_t fl; 2684 struct ifnet *ifp; 2685 int lro_enabled; 2686 bool v4_forwarding, v6_forwarding, lro_possible; 2687 2688 /* 2689 * XXX early demux data packets so that if_input processing only handles 2690 * acks in interrupt context 2691 */ 2692 struct mbuf *m, *mh, *mt, *mf; 2693 2694 lro_possible = v4_forwarding = v6_forwarding = false; 2695 ifp = ctx->ifc_ifp; 2696 mh = mt = NULL; 2697 MPASS(budget > 0); 2698 rx_pkts = rx_bytes = 0; 2699 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2700 cidxp = &rxq->ifr_cq_cidx; 2701 else 2702 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2703 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2704 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2705 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2706 DBG_COUNTER_INC(rx_unavail); 2707 return (false); 2708 } 2709 2710 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2711 if (__predict_false(!CTX_ACTIVE(ctx))) { 2712 DBG_COUNTER_INC(rx_ctx_inactive); 2713 break; 2714 } 2715 /* 2716 * Reset client set fields to their default values 2717 */ 2718 rxd_info_zero(&ri); 2719 ri.iri_qsidx = rxq->ifr_id; 2720 ri.iri_cidx = *cidxp; 2721 ri.iri_ifp = ifp; 2722 ri.iri_frags = rxq->ifr_frags; 2723 di = rxq->ifr_fl[rxq->ifr_frags[0].irf_flid].ifl_ifdi; 2724 bus_dmamap_sync(di->idi_tag, di->idi_map, 2725 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2726 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2727 2728 if (err) 2729 goto err; 2730 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2731 *cidxp = ri.iri_cidx; 2732 /* Update our consumer index */ 2733 /* XXX NB: shurd - check if this is still safe */ 2734 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2735 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2736 rxq->ifr_cq_gen = 0; 2737 } 2738 /* was this only a completion queue message? */ 2739 if (__predict_false(ri.iri_nfrags == 0)) 2740 continue; 2741 } 2742 MPASS(ri.iri_nfrags != 0); 2743 MPASS(ri.iri_len != 0); 2744 2745 /* will advance the cidx on the corresponding free lists */ 2746 m = iflib_rxd_pkt_get(rxq, &ri); 2747 avail--; 2748 budget_left--; 2749 if (avail == 0 && budget_left) 2750 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2751 2752 if (__predict_false(m == NULL)) { 2753 DBG_COUNTER_INC(rx_mbuf_null); 2754 continue; 2755 } 2756 /* imm_pkt: -- cxgb */ 2757 if (mh == NULL) 2758 mh = mt = m; 2759 else { 2760 mt->m_nextpkt = m; 2761 mt = m; 2762 } 2763 } 2764 /* make sure that we can refill faster than drain */ 2765 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2766 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2767 2768 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2769 if (lro_enabled) 2770 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2771 mt = mf = NULL; 2772 while (mh != NULL) { 2773 m = mh; 2774 mh = mh->m_nextpkt; 2775 m->m_nextpkt = NULL; 2776 #ifndef __NO_STRICT_ALIGNMENT 2777 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2778 continue; 2779 #endif 2780 rx_bytes += m->m_pkthdr.len; 2781 rx_pkts++; 2782 #if defined(INET6) || defined(INET) 2783 if (lro_enabled) { 2784 if (!lro_possible) { 2785 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2786 if (lro_possible && mf != NULL) { 2787 ifp->if_input(ifp, mf); 2788 DBG_COUNTER_INC(rx_if_input); 2789 mt = mf = NULL; 2790 } 2791 } 2792 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2793 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2794 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2795 continue; 2796 } 2797 } 2798 #endif 2799 if (lro_possible) { 2800 ifp->if_input(ifp, m); 2801 DBG_COUNTER_INC(rx_if_input); 2802 continue; 2803 } 2804 2805 if (mf == NULL) 2806 mf = m; 2807 if (mt != NULL) 2808 mt->m_nextpkt = m; 2809 mt = m; 2810 } 2811 if (mf != NULL) { 2812 ifp->if_input(ifp, mf); 2813 DBG_COUNTER_INC(rx_if_input); 2814 } 2815 2816 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2817 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2818 2819 /* 2820 * Flush any outstanding LRO work 2821 */ 2822 #if defined(INET6) || defined(INET) 2823 tcp_lro_flush_all(&rxq->ifr_lc); 2824 #endif 2825 if (avail) 2826 return true; 2827 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2828 err: 2829 STATE_LOCK(ctx); 2830 ctx->ifc_flags |= IFC_DO_RESET; 2831 iflib_admin_intr_deferred(ctx); 2832 STATE_UNLOCK(ctx); 2833 return (false); 2834 } 2835 2836 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2837 static inline qidx_t 2838 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2839 { 2840 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2841 qidx_t minthresh = txq->ift_size / 8; 2842 if (in_use > 4*minthresh) 2843 return (notify_count); 2844 if (in_use > 2*minthresh) 2845 return (notify_count >> 1); 2846 if (in_use > minthresh) 2847 return (notify_count >> 3); 2848 return (0); 2849 } 2850 2851 static inline qidx_t 2852 txq_max_rs_deferred(iflib_txq_t txq) 2853 { 2854 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2855 qidx_t minthresh = txq->ift_size / 8; 2856 if (txq->ift_in_use > 4*minthresh) 2857 return (notify_count); 2858 if (txq->ift_in_use > 2*minthresh) 2859 return (notify_count >> 1); 2860 if (txq->ift_in_use > minthresh) 2861 return (notify_count >> 2); 2862 return (2); 2863 } 2864 2865 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2866 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2867 2868 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2869 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2870 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2871 2872 /* forward compatibility for cxgb */ 2873 #define FIRST_QSET(ctx) 0 2874 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2875 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2876 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2877 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2878 2879 /* XXX we should be setting this to something other than zero */ 2880 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2881 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2882 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2883 2884 static inline bool 2885 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2886 { 2887 qidx_t dbval, max; 2888 bool rang; 2889 2890 rang = false; 2891 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2892 if (ring || txq->ift_db_pending >= max) { 2893 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2894 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2895 txq->ift_db_pending = txq->ift_npending = 0; 2896 rang = true; 2897 } 2898 return (rang); 2899 } 2900 2901 #ifdef PKT_DEBUG 2902 static void 2903 print_pkt(if_pkt_info_t pi) 2904 { 2905 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2906 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2907 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2908 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2909 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2910 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2911 } 2912 #endif 2913 2914 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2915 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2916 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2917 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2918 2919 static int 2920 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2921 { 2922 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2923 struct ether_vlan_header *eh; 2924 struct mbuf *m; 2925 2926 m = *mp; 2927 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2928 M_WRITABLE(m) == 0) { 2929 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2930 return (ENOMEM); 2931 } else { 2932 m_freem(*mp); 2933 DBG_COUNTER_INC(tx_frees); 2934 *mp = m; 2935 } 2936 } 2937 2938 /* 2939 * Determine where frame payload starts. 2940 * Jump over vlan headers if already present, 2941 * helpful for QinQ too. 2942 */ 2943 if (__predict_false(m->m_len < sizeof(*eh))) { 2944 txq->ift_pullups++; 2945 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2946 return (ENOMEM); 2947 } 2948 eh = mtod(m, struct ether_vlan_header *); 2949 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2950 pi->ipi_etype = ntohs(eh->evl_proto); 2951 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2952 } else { 2953 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2954 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2955 } 2956 2957 switch (pi->ipi_etype) { 2958 #ifdef INET 2959 case ETHERTYPE_IP: 2960 { 2961 struct mbuf *n; 2962 struct ip *ip = NULL; 2963 struct tcphdr *th = NULL; 2964 int minthlen; 2965 2966 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2967 if (__predict_false(m->m_len < minthlen)) { 2968 /* 2969 * if this code bloat is causing too much of a hit 2970 * move it to a separate function and mark it noinline 2971 */ 2972 if (m->m_len == pi->ipi_ehdrlen) { 2973 n = m->m_next; 2974 MPASS(n); 2975 if (n->m_len >= sizeof(*ip)) { 2976 ip = (struct ip *)n->m_data; 2977 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2978 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2979 } else { 2980 txq->ift_pullups++; 2981 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2982 return (ENOMEM); 2983 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2984 } 2985 } else { 2986 txq->ift_pullups++; 2987 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2988 return (ENOMEM); 2989 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2990 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2991 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2992 } 2993 } else { 2994 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2995 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2996 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2997 } 2998 pi->ipi_ip_hlen = ip->ip_hl << 2; 2999 pi->ipi_ipproto = ip->ip_p; 3000 pi->ipi_flags |= IPI_TX_IPV4; 3001 3002 /* TCP checksum offload may require TCP header length */ 3003 if (IS_TX_OFFLOAD4(pi)) { 3004 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3005 if (__predict_false(th == NULL)) { 3006 txq->ift_pullups++; 3007 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3008 return (ENOMEM); 3009 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3010 } 3011 pi->ipi_tcp_hflags = th->th_flags; 3012 pi->ipi_tcp_hlen = th->th_off << 2; 3013 pi->ipi_tcp_seq = th->th_seq; 3014 } 3015 if (IS_TSO4(pi)) { 3016 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3017 return (ENXIO); 3018 /* 3019 * TSO always requires hardware checksum offload. 3020 */ 3021 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3022 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3023 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3024 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3025 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3026 ip->ip_sum = 0; 3027 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3028 } 3029 } 3030 } 3031 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3032 ip->ip_sum = 0; 3033 3034 break; 3035 } 3036 #endif 3037 #ifdef INET6 3038 case ETHERTYPE_IPV6: 3039 { 3040 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3041 struct tcphdr *th; 3042 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3043 3044 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3045 txq->ift_pullups++; 3046 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3047 return (ENOMEM); 3048 } 3049 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3050 3051 /* XXX-BZ this will go badly in case of ext hdrs. */ 3052 pi->ipi_ipproto = ip6->ip6_nxt; 3053 pi->ipi_flags |= IPI_TX_IPV6; 3054 3055 /* TCP checksum offload may require TCP header length */ 3056 if (IS_TX_OFFLOAD6(pi)) { 3057 if (pi->ipi_ipproto == IPPROTO_TCP) { 3058 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3059 txq->ift_pullups++; 3060 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3061 return (ENOMEM); 3062 } 3063 pi->ipi_tcp_hflags = th->th_flags; 3064 pi->ipi_tcp_hlen = th->th_off << 2; 3065 pi->ipi_tcp_seq = th->th_seq; 3066 } 3067 if (IS_TSO6(pi)) { 3068 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3069 return (ENXIO); 3070 /* 3071 * TSO always requires hardware checksum offload. 3072 */ 3073 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3074 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3075 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3076 } 3077 } 3078 break; 3079 } 3080 #endif 3081 default: 3082 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3083 pi->ipi_ip_hlen = 0; 3084 break; 3085 } 3086 *mp = m; 3087 3088 return (0); 3089 } 3090 3091 /* 3092 * If dodgy hardware rejects the scatter gather chain we've handed it 3093 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3094 * m_defrag'd mbufs 3095 */ 3096 static __noinline struct mbuf * 3097 iflib_remove_mbuf(iflib_txq_t txq) 3098 { 3099 int ntxd, pidx; 3100 struct mbuf *m, **ifsd_m; 3101 3102 ifsd_m = txq->ift_sds.ifsd_m; 3103 ntxd = txq->ift_size; 3104 pidx = txq->ift_pidx & (ntxd - 1); 3105 ifsd_m = txq->ift_sds.ifsd_m; 3106 m = ifsd_m[pidx]; 3107 ifsd_m[pidx] = NULL; 3108 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3109 if (txq->ift_sds.ifsd_tso_map != NULL) 3110 bus_dmamap_unload(txq->ift_tso_buf_tag, 3111 txq->ift_sds.ifsd_tso_map[pidx]); 3112 #if MEMORY_LOGGING 3113 txq->ift_dequeued++; 3114 #endif 3115 return (m); 3116 } 3117 3118 static inline caddr_t 3119 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3120 { 3121 qidx_t size; 3122 int ntxd; 3123 caddr_t start, end, cur, next; 3124 3125 ntxd = txq->ift_size; 3126 size = txq->ift_txd_size[qid]; 3127 start = txq->ift_ifdi[qid].idi_vaddr; 3128 3129 if (__predict_false(size == 0)) 3130 return (start); 3131 cur = start + size*cidx; 3132 end = start + size*ntxd; 3133 next = CACHE_PTR_NEXT(cur); 3134 return (next < end ? next : start); 3135 } 3136 3137 /* 3138 * Pad an mbuf to ensure a minimum ethernet frame size. 3139 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3140 */ 3141 static __noinline int 3142 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3143 { 3144 /* 3145 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3146 * and ARP message is the smallest common payload I can think of 3147 */ 3148 static char pad[18]; /* just zeros */ 3149 int n; 3150 struct mbuf *new_head; 3151 3152 if (!M_WRITABLE(*m_head)) { 3153 new_head = m_dup(*m_head, M_NOWAIT); 3154 if (new_head == NULL) { 3155 m_freem(*m_head); 3156 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3157 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3158 DBG_COUNTER_INC(tx_frees); 3159 return ENOMEM; 3160 } 3161 m_freem(*m_head); 3162 *m_head = new_head; 3163 } 3164 3165 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3166 n > 0; n -= sizeof(pad)) 3167 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3168 break; 3169 3170 if (n > 0) { 3171 m_freem(*m_head); 3172 device_printf(dev, "cannot pad short frame\n"); 3173 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3174 DBG_COUNTER_INC(tx_frees); 3175 return (ENOBUFS); 3176 } 3177 3178 return 0; 3179 } 3180 3181 static int 3182 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3183 { 3184 if_ctx_t ctx; 3185 if_shared_ctx_t sctx; 3186 if_softc_ctx_t scctx; 3187 bus_dma_tag_t buf_tag; 3188 bus_dma_segment_t *segs; 3189 struct mbuf *m_head, **ifsd_m; 3190 void *next_txd; 3191 bus_dmamap_t map; 3192 struct if_pkt_info pi; 3193 int remap = 0; 3194 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3195 3196 ctx = txq->ift_ctx; 3197 sctx = ctx->ifc_sctx; 3198 scctx = &ctx->ifc_softc_ctx; 3199 segs = txq->ift_segs; 3200 ntxd = txq->ift_size; 3201 m_head = *m_headp; 3202 map = NULL; 3203 3204 /* 3205 * If we're doing TSO the next descriptor to clean may be quite far ahead 3206 */ 3207 cidx = txq->ift_cidx; 3208 pidx = txq->ift_pidx; 3209 if (ctx->ifc_flags & IFC_PREFETCH) { 3210 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3211 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3212 next_txd = calc_next_txd(txq, cidx, 0); 3213 prefetch(next_txd); 3214 } 3215 3216 /* prefetch the next cache line of mbuf pointers and flags */ 3217 prefetch(&txq->ift_sds.ifsd_m[next]); 3218 prefetch(&txq->ift_sds.ifsd_map[next]); 3219 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3220 } 3221 map = txq->ift_sds.ifsd_map[pidx]; 3222 ifsd_m = txq->ift_sds.ifsd_m; 3223 3224 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3225 buf_tag = txq->ift_tso_buf_tag; 3226 max_segs = scctx->isc_tx_tso_segments_max; 3227 map = txq->ift_sds.ifsd_tso_map[pidx]; 3228 MPASS(buf_tag != NULL); 3229 MPASS(max_segs > 0); 3230 } else { 3231 buf_tag = txq->ift_buf_tag; 3232 max_segs = scctx->isc_tx_nsegments; 3233 map = txq->ift_sds.ifsd_map[pidx]; 3234 } 3235 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3236 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3237 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3238 if (err) { 3239 DBG_COUNTER_INC(encap_txd_encap_fail); 3240 return err; 3241 } 3242 } 3243 m_head = *m_headp; 3244 3245 pkt_info_zero(&pi); 3246 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3247 pi.ipi_pidx = pidx; 3248 pi.ipi_qsidx = txq->ift_id; 3249 pi.ipi_len = m_head->m_pkthdr.len; 3250 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3251 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3252 3253 /* deliberate bitwise OR to make one condition */ 3254 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3255 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3256 DBG_COUNTER_INC(encap_txd_encap_fail); 3257 return (err); 3258 } 3259 m_head = *m_headp; 3260 } 3261 3262 retry: 3263 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3264 BUS_DMA_NOWAIT); 3265 defrag: 3266 if (__predict_false(err)) { 3267 switch (err) { 3268 case EFBIG: 3269 /* try collapse once and defrag once */ 3270 if (remap == 0) { 3271 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3272 /* try defrag if collapsing fails */ 3273 if (m_head == NULL) 3274 remap++; 3275 } 3276 if (remap == 1) { 3277 txq->ift_mbuf_defrag++; 3278 m_head = m_defrag(*m_headp, M_NOWAIT); 3279 } 3280 remap++; 3281 if (__predict_false(m_head == NULL)) 3282 goto defrag_failed; 3283 *m_headp = m_head; 3284 goto retry; 3285 break; 3286 case ENOMEM: 3287 txq->ift_no_tx_dma_setup++; 3288 break; 3289 default: 3290 txq->ift_no_tx_dma_setup++; 3291 m_freem(*m_headp); 3292 DBG_COUNTER_INC(tx_frees); 3293 *m_headp = NULL; 3294 break; 3295 } 3296 txq->ift_map_failed++; 3297 DBG_COUNTER_INC(encap_load_mbuf_fail); 3298 DBG_COUNTER_INC(encap_txd_encap_fail); 3299 return (err); 3300 } 3301 ifsd_m[pidx] = m_head; 3302 /* 3303 * XXX assumes a 1 to 1 relationship between segments and 3304 * descriptors - this does not hold true on all drivers, e.g. 3305 * cxgb 3306 */ 3307 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3308 txq->ift_no_desc_avail++; 3309 bus_dmamap_unload(buf_tag, map); 3310 DBG_COUNTER_INC(encap_txq_avail_fail); 3311 DBG_COUNTER_INC(encap_txd_encap_fail); 3312 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3313 GROUPTASK_ENQUEUE(&txq->ift_task); 3314 return (ENOBUFS); 3315 } 3316 /* 3317 * On Intel cards we can greatly reduce the number of TX interrupts 3318 * we see by only setting report status on every Nth descriptor. 3319 * However, this also means that the driver will need to keep track 3320 * of the descriptors that RS was set on to check them for the DD bit. 3321 */ 3322 txq->ift_rs_pending += nsegs + 1; 3323 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3324 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3325 pi.ipi_flags |= IPI_TX_INTR; 3326 txq->ift_rs_pending = 0; 3327 } 3328 3329 pi.ipi_segs = segs; 3330 pi.ipi_nsegs = nsegs; 3331 3332 MPASS(pidx >= 0 && pidx < txq->ift_size); 3333 #ifdef PKT_DEBUG 3334 print_pkt(&pi); 3335 #endif 3336 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3337 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3338 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3339 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3340 DBG_COUNTER_INC(tx_encap); 3341 MPASS(pi.ipi_new_pidx < txq->ift_size); 3342 3343 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3344 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3345 ndesc += txq->ift_size; 3346 txq->ift_gen = 1; 3347 } 3348 /* 3349 * drivers can need as many as 3350 * two sentinels 3351 */ 3352 MPASS(ndesc <= pi.ipi_nsegs + 2); 3353 MPASS(pi.ipi_new_pidx != pidx); 3354 MPASS(ndesc > 0); 3355 txq->ift_in_use += ndesc; 3356 3357 /* 3358 * We update the last software descriptor again here because there may 3359 * be a sentinel and/or there may be more mbufs than segments 3360 */ 3361 txq->ift_pidx = pi.ipi_new_pidx; 3362 txq->ift_npending += pi.ipi_ndescs; 3363 } else { 3364 *m_headp = m_head = iflib_remove_mbuf(txq); 3365 if (err == EFBIG) { 3366 txq->ift_txd_encap_efbig++; 3367 if (remap < 2) { 3368 remap = 1; 3369 goto defrag; 3370 } 3371 } 3372 goto defrag_failed; 3373 } 3374 /* 3375 * err can't possibly be non-zero here, so we don't neet to test it 3376 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3377 */ 3378 return (err); 3379 3380 defrag_failed: 3381 txq->ift_mbuf_defrag_failed++; 3382 txq->ift_map_failed++; 3383 m_freem(*m_headp); 3384 DBG_COUNTER_INC(tx_frees); 3385 *m_headp = NULL; 3386 DBG_COUNTER_INC(encap_txd_encap_fail); 3387 return (ENOMEM); 3388 } 3389 3390 static void 3391 iflib_tx_desc_free(iflib_txq_t txq, int n) 3392 { 3393 uint32_t qsize, cidx, mask, gen; 3394 struct mbuf *m, **ifsd_m; 3395 bool do_prefetch; 3396 3397 cidx = txq->ift_cidx; 3398 gen = txq->ift_gen; 3399 qsize = txq->ift_size; 3400 mask = qsize-1; 3401 ifsd_m = txq->ift_sds.ifsd_m; 3402 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3403 3404 while (n-- > 0) { 3405 if (do_prefetch) { 3406 prefetch(ifsd_m[(cidx + 3) & mask]); 3407 prefetch(ifsd_m[(cidx + 4) & mask]); 3408 } 3409 if ((m = ifsd_m[cidx]) != NULL) { 3410 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3411 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3412 bus_dmamap_sync(txq->ift_tso_buf_tag, 3413 txq->ift_sds.ifsd_tso_map[cidx], 3414 BUS_DMASYNC_POSTWRITE); 3415 bus_dmamap_unload(txq->ift_tso_buf_tag, 3416 txq->ift_sds.ifsd_tso_map[cidx]); 3417 } else { 3418 bus_dmamap_sync(txq->ift_buf_tag, 3419 txq->ift_sds.ifsd_map[cidx], 3420 BUS_DMASYNC_POSTWRITE); 3421 bus_dmamap_unload(txq->ift_buf_tag, 3422 txq->ift_sds.ifsd_map[cidx]); 3423 } 3424 /* XXX we don't support any drivers that batch packets yet */ 3425 MPASS(m->m_nextpkt == NULL); 3426 m_freem(m); 3427 ifsd_m[cidx] = NULL; 3428 #if MEMORY_LOGGING 3429 txq->ift_dequeued++; 3430 #endif 3431 DBG_COUNTER_INC(tx_frees); 3432 } 3433 if (__predict_false(++cidx == qsize)) { 3434 cidx = 0; 3435 gen = 0; 3436 } 3437 } 3438 txq->ift_cidx = cidx; 3439 txq->ift_gen = gen; 3440 } 3441 3442 static __inline int 3443 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3444 { 3445 int reclaim; 3446 if_ctx_t ctx = txq->ift_ctx; 3447 3448 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3449 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3450 3451 /* 3452 * Need a rate-limiting check so that this isn't called every time 3453 */ 3454 iflib_tx_credits_update(ctx, txq); 3455 reclaim = DESC_RECLAIMABLE(txq); 3456 3457 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3458 #ifdef INVARIANTS 3459 if (iflib_verbose_debug) { 3460 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3461 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3462 reclaim, thresh); 3463 3464 } 3465 #endif 3466 return (0); 3467 } 3468 iflib_tx_desc_free(txq, reclaim); 3469 txq->ift_cleaned += reclaim; 3470 txq->ift_in_use -= reclaim; 3471 3472 return (reclaim); 3473 } 3474 3475 static struct mbuf ** 3476 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3477 { 3478 int next, size; 3479 struct mbuf **items; 3480 3481 size = r->size; 3482 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3483 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3484 3485 prefetch(items[(cidx + offset) & (size-1)]); 3486 if (remaining > 1) { 3487 prefetch2cachelines(&items[next]); 3488 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3489 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3490 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3491 } 3492 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3493 } 3494 3495 static void 3496 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3497 { 3498 3499 ifmp_ring_check_drainage(txq->ift_br, budget); 3500 } 3501 3502 static uint32_t 3503 iflib_txq_can_drain(struct ifmp_ring *r) 3504 { 3505 iflib_txq_t txq = r->cookie; 3506 if_ctx_t ctx = txq->ift_ctx; 3507 3508 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3509 BUS_DMASYNC_POSTREAD); 3510 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3511 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3512 } 3513 3514 static uint32_t 3515 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3516 { 3517 iflib_txq_t txq = r->cookie; 3518 if_ctx_t ctx = txq->ift_ctx; 3519 struct ifnet *ifp = ctx->ifc_ifp; 3520 struct mbuf **mp, *m; 3521 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3522 int reclaimed, err, in_use_prev, desc_used; 3523 bool do_prefetch, ring, rang; 3524 3525 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3526 !LINK_ACTIVE(ctx))) { 3527 DBG_COUNTER_INC(txq_drain_notready); 3528 return (0); 3529 } 3530 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3531 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3532 avail = IDXDIFF(pidx, cidx, r->size); 3533 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3534 DBG_COUNTER_INC(txq_drain_flushing); 3535 for (i = 0; i < avail; i++) { 3536 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3537 m_free(r->items[(cidx + i) & (r->size-1)]); 3538 r->items[(cidx + i) & (r->size-1)] = NULL; 3539 } 3540 return (avail); 3541 } 3542 3543 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3544 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3545 CALLOUT_LOCK(txq); 3546 callout_stop(&txq->ift_timer); 3547 CALLOUT_UNLOCK(txq); 3548 DBG_COUNTER_INC(txq_drain_oactive); 3549 return (0); 3550 } 3551 if (reclaimed) 3552 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3553 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3554 count = MIN(avail, TX_BATCH_SIZE); 3555 #ifdef INVARIANTS 3556 if (iflib_verbose_debug) 3557 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3558 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3559 #endif 3560 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3561 avail = TXQ_AVAIL(txq); 3562 err = 0; 3563 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3564 int rem = do_prefetch ? count - i : 0; 3565 3566 mp = _ring_peek_one(r, cidx, i, rem); 3567 MPASS(mp != NULL && *mp != NULL); 3568 if (__predict_false(*mp == (struct mbuf *)txq)) { 3569 consumed++; 3570 reclaimed++; 3571 continue; 3572 } 3573 in_use_prev = txq->ift_in_use; 3574 err = iflib_encap(txq, mp); 3575 if (__predict_false(err)) { 3576 /* no room - bail out */ 3577 if (err == ENOBUFS) 3578 break; 3579 consumed++; 3580 /* we can't send this packet - skip it */ 3581 continue; 3582 } 3583 consumed++; 3584 pkt_sent++; 3585 m = *mp; 3586 DBG_COUNTER_INC(tx_sent); 3587 bytes_sent += m->m_pkthdr.len; 3588 mcast_sent += !!(m->m_flags & M_MCAST); 3589 avail = TXQ_AVAIL(txq); 3590 3591 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3592 desc_used += (txq->ift_in_use - in_use_prev); 3593 ETHER_BPF_MTAP(ifp, m); 3594 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3595 break; 3596 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3597 } 3598 3599 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3600 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3601 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3602 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3603 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3604 if (mcast_sent) 3605 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3606 #ifdef INVARIANTS 3607 if (iflib_verbose_debug) 3608 printf("consumed=%d\n", consumed); 3609 #endif 3610 return (consumed); 3611 } 3612 3613 static uint32_t 3614 iflib_txq_drain_always(struct ifmp_ring *r) 3615 { 3616 return (1); 3617 } 3618 3619 static uint32_t 3620 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3621 { 3622 int i, avail; 3623 struct mbuf **mp; 3624 iflib_txq_t txq; 3625 3626 txq = r->cookie; 3627 3628 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3629 CALLOUT_LOCK(txq); 3630 callout_stop(&txq->ift_timer); 3631 CALLOUT_UNLOCK(txq); 3632 3633 avail = IDXDIFF(pidx, cidx, r->size); 3634 for (i = 0; i < avail; i++) { 3635 mp = _ring_peek_one(r, cidx, i, avail - i); 3636 if (__predict_false(*mp == (struct mbuf *)txq)) 3637 continue; 3638 m_freem(*mp); 3639 DBG_COUNTER_INC(tx_frees); 3640 } 3641 MPASS(ifmp_ring_is_stalled(r) == 0); 3642 return (avail); 3643 } 3644 3645 static void 3646 iflib_ifmp_purge(iflib_txq_t txq) 3647 { 3648 struct ifmp_ring *r; 3649 3650 r = txq->ift_br; 3651 r->drain = iflib_txq_drain_free; 3652 r->can_drain = iflib_txq_drain_always; 3653 3654 ifmp_ring_check_drainage(r, r->size); 3655 3656 r->drain = iflib_txq_drain; 3657 r->can_drain = iflib_txq_can_drain; 3658 } 3659 3660 static void 3661 _task_fn_tx(void *context) 3662 { 3663 iflib_txq_t txq = context; 3664 if_ctx_t ctx = txq->ift_ctx; 3665 struct ifnet *ifp = ctx->ifc_ifp; 3666 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3667 3668 #ifdef IFLIB_DIAGNOSTICS 3669 txq->ift_cpu_exec_count[curcpu]++; 3670 #endif 3671 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3672 return; 3673 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3674 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3675 BUS_DMASYNC_POSTREAD); 3676 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3677 netmap_tx_irq(ifp, txq->ift_id); 3678 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3679 return; 3680 } 3681 #ifdef ALTQ 3682 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3683 iflib_altq_if_start(ifp); 3684 #endif 3685 if (txq->ift_db_pending) 3686 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3687 else if (!abdicate) 3688 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3689 /* 3690 * When abdicating, we always need to check drainage, not just when we don't enqueue 3691 */ 3692 if (abdicate) 3693 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3694 if (ctx->ifc_flags & IFC_LEGACY) 3695 IFDI_INTR_ENABLE(ctx); 3696 else { 3697 #ifdef INVARIANTS 3698 int rc = 3699 #endif 3700 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3701 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3702 } 3703 } 3704 3705 static void 3706 _task_fn_rx(void *context) 3707 { 3708 iflib_rxq_t rxq = context; 3709 if_ctx_t ctx = rxq->ifr_ctx; 3710 bool more; 3711 uint16_t budget; 3712 3713 #ifdef IFLIB_DIAGNOSTICS 3714 rxq->ifr_cpu_exec_count[curcpu]++; 3715 #endif 3716 DBG_COUNTER_INC(task_fn_rxs); 3717 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3718 return; 3719 more = true; 3720 #ifdef DEV_NETMAP 3721 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3722 u_int work = 0; 3723 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3724 more = false; 3725 } 3726 } 3727 #endif 3728 budget = ctx->ifc_sysctl_rx_budget; 3729 if (budget == 0) 3730 budget = 16; /* XXX */ 3731 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3732 if (ctx->ifc_flags & IFC_LEGACY) 3733 IFDI_INTR_ENABLE(ctx); 3734 else { 3735 #ifdef INVARIANTS 3736 int rc = 3737 #endif 3738 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3739 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3740 DBG_COUNTER_INC(rx_intr_enables); 3741 } 3742 } 3743 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3744 return; 3745 if (more) 3746 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3747 } 3748 3749 static void 3750 _task_fn_admin(void *context) 3751 { 3752 if_ctx_t ctx = context; 3753 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3754 iflib_txq_t txq; 3755 int i; 3756 bool oactive, running, do_reset, do_watchdog, in_detach; 3757 uint32_t reset_on = hz / 2; 3758 3759 STATE_LOCK(ctx); 3760 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3761 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3762 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3763 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3764 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3765 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3766 STATE_UNLOCK(ctx); 3767 3768 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3769 return; 3770 if (in_detach) 3771 return; 3772 3773 CTX_LOCK(ctx); 3774 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3775 CALLOUT_LOCK(txq); 3776 callout_stop(&txq->ift_timer); 3777 CALLOUT_UNLOCK(txq); 3778 } 3779 if (do_watchdog) { 3780 ctx->ifc_watchdog_events++; 3781 IFDI_WATCHDOG_RESET(ctx); 3782 } 3783 IFDI_UPDATE_ADMIN_STATUS(ctx); 3784 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3785 #ifdef DEV_NETMAP 3786 reset_on = hz / 2; 3787 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3788 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3789 #endif 3790 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3791 } 3792 IFDI_LINK_INTR_ENABLE(ctx); 3793 if (do_reset) 3794 iflib_if_init_locked(ctx); 3795 CTX_UNLOCK(ctx); 3796 3797 if (LINK_ACTIVE(ctx) == 0) 3798 return; 3799 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3800 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3801 } 3802 3803 3804 static void 3805 _task_fn_iov(void *context) 3806 { 3807 if_ctx_t ctx = context; 3808 3809 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3810 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3811 return; 3812 3813 CTX_LOCK(ctx); 3814 IFDI_VFLR_HANDLE(ctx); 3815 CTX_UNLOCK(ctx); 3816 } 3817 3818 static int 3819 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3820 { 3821 int err; 3822 if_int_delay_info_t info; 3823 if_ctx_t ctx; 3824 3825 info = (if_int_delay_info_t)arg1; 3826 ctx = info->iidi_ctx; 3827 info->iidi_req = req; 3828 info->iidi_oidp = oidp; 3829 CTX_LOCK(ctx); 3830 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3831 CTX_UNLOCK(ctx); 3832 return (err); 3833 } 3834 3835 /********************************************************************* 3836 * 3837 * IFNET FUNCTIONS 3838 * 3839 **********************************************************************/ 3840 3841 static void 3842 iflib_if_init_locked(if_ctx_t ctx) 3843 { 3844 iflib_stop(ctx); 3845 iflib_init_locked(ctx); 3846 } 3847 3848 3849 static void 3850 iflib_if_init(void *arg) 3851 { 3852 if_ctx_t ctx = arg; 3853 3854 CTX_LOCK(ctx); 3855 iflib_if_init_locked(ctx); 3856 CTX_UNLOCK(ctx); 3857 } 3858 3859 static int 3860 iflib_if_transmit(if_t ifp, struct mbuf *m) 3861 { 3862 if_ctx_t ctx = if_getsoftc(ifp); 3863 3864 iflib_txq_t txq; 3865 int err, qidx; 3866 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3867 3868 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3869 DBG_COUNTER_INC(tx_frees); 3870 m_freem(m); 3871 return (ENOBUFS); 3872 } 3873 3874 MPASS(m->m_nextpkt == NULL); 3875 /* ALTQ-enabled interfaces always use queue 0. */ 3876 qidx = 0; 3877 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3878 qidx = QIDX(ctx, m); 3879 /* 3880 * XXX calculate buf_ring based on flowid (divvy up bits?) 3881 */ 3882 txq = &ctx->ifc_txqs[qidx]; 3883 3884 #ifdef DRIVER_BACKPRESSURE 3885 if (txq->ift_closed) { 3886 while (m != NULL) { 3887 next = m->m_nextpkt; 3888 m->m_nextpkt = NULL; 3889 m_freem(m); 3890 DBG_COUNTER_INC(tx_frees); 3891 m = next; 3892 } 3893 return (ENOBUFS); 3894 } 3895 #endif 3896 #ifdef notyet 3897 qidx = count = 0; 3898 mp = marr; 3899 next = m; 3900 do { 3901 count++; 3902 next = next->m_nextpkt; 3903 } while (next != NULL); 3904 3905 if (count > nitems(marr)) 3906 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3907 /* XXX check nextpkt */ 3908 m_freem(m); 3909 /* XXX simplify for now */ 3910 DBG_COUNTER_INC(tx_frees); 3911 return (ENOBUFS); 3912 } 3913 for (next = m, i = 0; next != NULL; i++) { 3914 mp[i] = next; 3915 next = next->m_nextpkt; 3916 mp[i]->m_nextpkt = NULL; 3917 } 3918 #endif 3919 DBG_COUNTER_INC(tx_seen); 3920 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3921 3922 if (abdicate) 3923 GROUPTASK_ENQUEUE(&txq->ift_task); 3924 if (err) { 3925 if (!abdicate) 3926 GROUPTASK_ENQUEUE(&txq->ift_task); 3927 /* support forthcoming later */ 3928 #ifdef DRIVER_BACKPRESSURE 3929 txq->ift_closed = TRUE; 3930 #endif 3931 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3932 m_freem(m); 3933 DBG_COUNTER_INC(tx_frees); 3934 } 3935 3936 return (err); 3937 } 3938 3939 #ifdef ALTQ 3940 /* 3941 * The overall approach to integrating iflib with ALTQ is to continue to use 3942 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3943 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3944 * is redundant/unnecessary, but doing so minimizes the amount of 3945 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3946 * redundantly queueing to an intermediate mp_ring is swamped by the 3947 * performance limitations inherent in using ALTQ. 3948 * 3949 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3950 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3951 * given interface. If ALTQ is enabled for an interface, then all 3952 * transmitted packets for that interface will be submitted to the ALTQ 3953 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3954 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3955 * update stats that the iflib machinery handles, and which is sensitve to 3956 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3957 * will be installed as the start routine for use by ALTQ facilities that 3958 * need to trigger queue drains on a scheduled basis. 3959 * 3960 */ 3961 static void 3962 iflib_altq_if_start(if_t ifp) 3963 { 3964 struct ifaltq *ifq = &ifp->if_snd; 3965 struct mbuf *m; 3966 3967 IFQ_LOCK(ifq); 3968 IFQ_DEQUEUE_NOLOCK(ifq, m); 3969 while (m != NULL) { 3970 iflib_if_transmit(ifp, m); 3971 IFQ_DEQUEUE_NOLOCK(ifq, m); 3972 } 3973 IFQ_UNLOCK(ifq); 3974 } 3975 3976 static int 3977 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 3978 { 3979 int err; 3980 3981 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 3982 IFQ_ENQUEUE(&ifp->if_snd, m, err); 3983 if (err == 0) 3984 iflib_altq_if_start(ifp); 3985 } else 3986 err = iflib_if_transmit(ifp, m); 3987 3988 return (err); 3989 } 3990 #endif /* ALTQ */ 3991 3992 static void 3993 iflib_if_qflush(if_t ifp) 3994 { 3995 if_ctx_t ctx = if_getsoftc(ifp); 3996 iflib_txq_t txq = ctx->ifc_txqs; 3997 int i; 3998 3999 STATE_LOCK(ctx); 4000 ctx->ifc_flags |= IFC_QFLUSH; 4001 STATE_UNLOCK(ctx); 4002 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4003 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4004 iflib_txq_check_drain(txq, 0); 4005 STATE_LOCK(ctx); 4006 ctx->ifc_flags &= ~IFC_QFLUSH; 4007 STATE_UNLOCK(ctx); 4008 4009 /* 4010 * When ALTQ is enabled, this will also take care of purging the 4011 * ALTQ queue(s). 4012 */ 4013 if_qflush(ifp); 4014 } 4015 4016 4017 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4018 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4019 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4020 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4021 4022 static int 4023 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4024 { 4025 if_ctx_t ctx = if_getsoftc(ifp); 4026 struct ifreq *ifr = (struct ifreq *)data; 4027 #if defined(INET) || defined(INET6) 4028 struct ifaddr *ifa = (struct ifaddr *)data; 4029 #endif 4030 bool avoid_reset = FALSE; 4031 int err = 0, reinit = 0, bits; 4032 4033 switch (command) { 4034 case SIOCSIFADDR: 4035 #ifdef INET 4036 if (ifa->ifa_addr->sa_family == AF_INET) 4037 avoid_reset = TRUE; 4038 #endif 4039 #ifdef INET6 4040 if (ifa->ifa_addr->sa_family == AF_INET6) 4041 avoid_reset = TRUE; 4042 #endif 4043 /* 4044 ** Calling init results in link renegotiation, 4045 ** so we avoid doing it when possible. 4046 */ 4047 if (avoid_reset) { 4048 if_setflagbits(ifp, IFF_UP,0); 4049 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4050 reinit = 1; 4051 #ifdef INET 4052 if (!(if_getflags(ifp) & IFF_NOARP)) 4053 arp_ifinit(ifp, ifa); 4054 #endif 4055 } else 4056 err = ether_ioctl(ifp, command, data); 4057 break; 4058 case SIOCSIFMTU: 4059 CTX_LOCK(ctx); 4060 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4061 CTX_UNLOCK(ctx); 4062 break; 4063 } 4064 bits = if_getdrvflags(ifp); 4065 /* stop the driver and free any clusters before proceeding */ 4066 iflib_stop(ctx); 4067 4068 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4069 STATE_LOCK(ctx); 4070 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4071 ctx->ifc_flags |= IFC_MULTISEG; 4072 else 4073 ctx->ifc_flags &= ~IFC_MULTISEG; 4074 STATE_UNLOCK(ctx); 4075 err = if_setmtu(ifp, ifr->ifr_mtu); 4076 } 4077 iflib_init_locked(ctx); 4078 STATE_LOCK(ctx); 4079 if_setdrvflags(ifp, bits); 4080 STATE_UNLOCK(ctx); 4081 CTX_UNLOCK(ctx); 4082 break; 4083 case SIOCSIFFLAGS: 4084 CTX_LOCK(ctx); 4085 if (if_getflags(ifp) & IFF_UP) { 4086 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4087 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4088 (IFF_PROMISC | IFF_ALLMULTI)) { 4089 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4090 } 4091 } else 4092 reinit = 1; 4093 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4094 iflib_stop(ctx); 4095 } 4096 ctx->ifc_if_flags = if_getflags(ifp); 4097 CTX_UNLOCK(ctx); 4098 break; 4099 case SIOCADDMULTI: 4100 case SIOCDELMULTI: 4101 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4102 CTX_LOCK(ctx); 4103 IFDI_INTR_DISABLE(ctx); 4104 IFDI_MULTI_SET(ctx); 4105 IFDI_INTR_ENABLE(ctx); 4106 CTX_UNLOCK(ctx); 4107 } 4108 break; 4109 case SIOCSIFMEDIA: 4110 CTX_LOCK(ctx); 4111 IFDI_MEDIA_SET(ctx); 4112 CTX_UNLOCK(ctx); 4113 /* falls thru */ 4114 case SIOCGIFMEDIA: 4115 case SIOCGIFXMEDIA: 4116 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4117 break; 4118 case SIOCGI2C: 4119 { 4120 struct ifi2creq i2c; 4121 4122 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4123 if (err != 0) 4124 break; 4125 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4126 err = EINVAL; 4127 break; 4128 } 4129 if (i2c.len > sizeof(i2c.data)) { 4130 err = EINVAL; 4131 break; 4132 } 4133 4134 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4135 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4136 sizeof(i2c)); 4137 break; 4138 } 4139 case SIOCSIFCAP: 4140 { 4141 int mask, setmask, oldmask; 4142 4143 oldmask = if_getcapenable(ifp); 4144 mask = ifr->ifr_reqcap ^ oldmask; 4145 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4146 setmask = 0; 4147 #ifdef TCP_OFFLOAD 4148 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4149 #endif 4150 setmask |= (mask & IFCAP_FLAGS); 4151 setmask |= (mask & IFCAP_WOL); 4152 4153 /* 4154 * If any RX csum has changed, change all the ones that 4155 * are supported by the driver. 4156 */ 4157 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4158 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4159 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4160 } 4161 4162 /* 4163 * want to ensure that traffic has stopped before we change any of the flags 4164 */ 4165 if (setmask) { 4166 CTX_LOCK(ctx); 4167 bits = if_getdrvflags(ifp); 4168 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4169 iflib_stop(ctx); 4170 STATE_LOCK(ctx); 4171 if_togglecapenable(ifp, setmask); 4172 STATE_UNLOCK(ctx); 4173 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4174 iflib_init_locked(ctx); 4175 STATE_LOCK(ctx); 4176 if_setdrvflags(ifp, bits); 4177 STATE_UNLOCK(ctx); 4178 CTX_UNLOCK(ctx); 4179 } 4180 if_vlancap(ifp); 4181 break; 4182 } 4183 case SIOCGPRIVATE_0: 4184 case SIOCSDRVSPEC: 4185 case SIOCGDRVSPEC: 4186 CTX_LOCK(ctx); 4187 err = IFDI_PRIV_IOCTL(ctx, command, data); 4188 CTX_UNLOCK(ctx); 4189 break; 4190 default: 4191 err = ether_ioctl(ifp, command, data); 4192 break; 4193 } 4194 if (reinit) 4195 iflib_if_init(ctx); 4196 return (err); 4197 } 4198 4199 static uint64_t 4200 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4201 { 4202 if_ctx_t ctx = if_getsoftc(ifp); 4203 4204 return (IFDI_GET_COUNTER(ctx, cnt)); 4205 } 4206 4207 /********************************************************************* 4208 * 4209 * OTHER FUNCTIONS EXPORTED TO THE STACK 4210 * 4211 **********************************************************************/ 4212 4213 static void 4214 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4215 { 4216 if_ctx_t ctx = if_getsoftc(ifp); 4217 4218 if ((void *)ctx != arg) 4219 return; 4220 4221 if ((vtag == 0) || (vtag > 4095)) 4222 return; 4223 4224 CTX_LOCK(ctx); 4225 IFDI_VLAN_REGISTER(ctx, vtag); 4226 /* Re-init to load the changes */ 4227 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4228 iflib_if_init_locked(ctx); 4229 CTX_UNLOCK(ctx); 4230 } 4231 4232 static void 4233 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4234 { 4235 if_ctx_t ctx = if_getsoftc(ifp); 4236 4237 if ((void *)ctx != arg) 4238 return; 4239 4240 if ((vtag == 0) || (vtag > 4095)) 4241 return; 4242 4243 CTX_LOCK(ctx); 4244 IFDI_VLAN_UNREGISTER(ctx, vtag); 4245 /* Re-init to load the changes */ 4246 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4247 iflib_if_init_locked(ctx); 4248 CTX_UNLOCK(ctx); 4249 } 4250 4251 static void 4252 iflib_led_func(void *arg, int onoff) 4253 { 4254 if_ctx_t ctx = arg; 4255 4256 CTX_LOCK(ctx); 4257 IFDI_LED_FUNC(ctx, onoff); 4258 CTX_UNLOCK(ctx); 4259 } 4260 4261 /********************************************************************* 4262 * 4263 * BUS FUNCTION DEFINITIONS 4264 * 4265 **********************************************************************/ 4266 4267 int 4268 iflib_device_probe(device_t dev) 4269 { 4270 pci_vendor_info_t *ent; 4271 4272 uint16_t pci_vendor_id, pci_device_id; 4273 uint16_t pci_subvendor_id, pci_subdevice_id; 4274 uint16_t pci_rev_id; 4275 if_shared_ctx_t sctx; 4276 4277 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4278 return (ENOTSUP); 4279 4280 pci_vendor_id = pci_get_vendor(dev); 4281 pci_device_id = pci_get_device(dev); 4282 pci_subvendor_id = pci_get_subvendor(dev); 4283 pci_subdevice_id = pci_get_subdevice(dev); 4284 pci_rev_id = pci_get_revid(dev); 4285 if (sctx->isc_parse_devinfo != NULL) 4286 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4287 4288 ent = sctx->isc_vendor_info; 4289 while (ent->pvi_vendor_id != 0) { 4290 if (pci_vendor_id != ent->pvi_vendor_id) { 4291 ent++; 4292 continue; 4293 } 4294 if ((pci_device_id == ent->pvi_device_id) && 4295 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4296 (ent->pvi_subvendor_id == 0)) && 4297 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4298 (ent->pvi_subdevice_id == 0)) && 4299 ((pci_rev_id == ent->pvi_rev_id) || 4300 (ent->pvi_rev_id == 0))) { 4301 4302 device_set_desc_copy(dev, ent->pvi_name); 4303 /* this needs to be changed to zero if the bus probing code 4304 * ever stops re-probing on best match because the sctx 4305 * may have its values over written by register calls 4306 * in subsequent probes 4307 */ 4308 return (BUS_PROBE_DEFAULT); 4309 } 4310 ent++; 4311 } 4312 return (ENXIO); 4313 } 4314 4315 static void 4316 iflib_reset_qvalues(if_ctx_t ctx) 4317 { 4318 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4319 if_shared_ctx_t sctx = ctx->ifc_sctx; 4320 device_t dev = ctx->ifc_dev; 4321 int i; 4322 4323 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4324 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4325 /* 4326 * XXX sanity check that ntxd & nrxd are a power of 2 4327 */ 4328 if (ctx->ifc_sysctl_ntxqs != 0) 4329 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4330 if (ctx->ifc_sysctl_nrxqs != 0) 4331 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4332 4333 for (i = 0; i < sctx->isc_ntxqs; i++) { 4334 if (ctx->ifc_sysctl_ntxds[i] != 0) 4335 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4336 else 4337 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4338 } 4339 4340 for (i = 0; i < sctx->isc_nrxqs; i++) { 4341 if (ctx->ifc_sysctl_nrxds[i] != 0) 4342 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4343 else 4344 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4345 } 4346 4347 for (i = 0; i < sctx->isc_nrxqs; i++) { 4348 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4349 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4350 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4351 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4352 } 4353 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4354 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4355 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4356 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4357 } 4358 } 4359 4360 for (i = 0; i < sctx->isc_ntxqs; i++) { 4361 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4362 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4363 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4364 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4365 } 4366 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4367 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4368 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4369 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4370 } 4371 } 4372 } 4373 4374 int 4375 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4376 { 4377 int err, rid, msix; 4378 if_ctx_t ctx; 4379 if_t ifp; 4380 if_softc_ctx_t scctx; 4381 int i; 4382 uint16_t main_txq; 4383 uint16_t main_rxq; 4384 4385 4386 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4387 4388 if (sc == NULL) { 4389 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4390 device_set_softc(dev, ctx); 4391 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4392 } 4393 4394 ctx->ifc_sctx = sctx; 4395 ctx->ifc_dev = dev; 4396 ctx->ifc_softc = sc; 4397 4398 if ((err = iflib_register(ctx)) != 0) { 4399 device_printf(dev, "iflib_register failed %d\n", err); 4400 goto fail_ctx_free; 4401 } 4402 iflib_add_device_sysctl_pre(ctx); 4403 4404 scctx = &ctx->ifc_softc_ctx; 4405 ifp = ctx->ifc_ifp; 4406 4407 iflib_reset_qvalues(ctx); 4408 CTX_LOCK(ctx); 4409 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4410 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4411 goto fail_unlock; 4412 } 4413 _iflib_pre_assert(scctx); 4414 ctx->ifc_txrx = *scctx->isc_txrx; 4415 4416 #ifdef INVARIANTS 4417 MPASS(scctx->isc_capabilities); 4418 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4419 MPASS(scctx->isc_tx_csum_flags); 4420 #endif 4421 4422 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4423 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4424 4425 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4426 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4427 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4428 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4429 4430 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4431 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4432 4433 /* XXX change for per-queue sizes */ 4434 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4435 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4436 for (i = 0; i < sctx->isc_nrxqs; i++) { 4437 if (!powerof2(scctx->isc_nrxd[i])) { 4438 /* round down instead? */ 4439 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4440 err = EINVAL; 4441 goto fail_iflib_detach; 4442 } 4443 } 4444 for (i = 0; i < sctx->isc_ntxqs; i++) { 4445 if (!powerof2(scctx->isc_ntxd[i])) { 4446 device_printf(dev, 4447 "# tx descriptors must be a power of 2"); 4448 err = EINVAL; 4449 goto fail_iflib_detach; 4450 } 4451 } 4452 4453 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4454 MAX_SINGLE_PACKET_FRACTION) 4455 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4456 MAX_SINGLE_PACKET_FRACTION); 4457 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4458 MAX_SINGLE_PACKET_FRACTION) 4459 scctx->isc_tx_tso_segments_max = max(1, 4460 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4461 4462 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4463 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4464 /* 4465 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4466 * but some MACs do. 4467 */ 4468 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4469 IP_MAXPACKET)); 4470 /* 4471 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4472 * into account. In the worst case, each of these calls will 4473 * add another mbuf and, thus, the requirement for another DMA 4474 * segment. So for best performance, it doesn't make sense to 4475 * advertize a maximum of TSO segments that typically will 4476 * require defragmentation in iflib_encap(). 4477 */ 4478 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4479 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4480 } 4481 if (scctx->isc_rss_table_size == 0) 4482 scctx->isc_rss_table_size = 64; 4483 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4484 4485 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4486 /* XXX format name */ 4487 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4488 4489 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4490 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4491 device_printf(dev, "Unable to fetch CPU list\n"); 4492 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4493 } 4494 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4495 4496 /* 4497 ** Now set up MSI or MSI-X, should return us the number of supported 4498 ** vectors (will be 1 for a legacy interrupt and MSI). 4499 */ 4500 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4501 msix = scctx->isc_vectors; 4502 } else if (scctx->isc_msix_bar != 0) 4503 /* 4504 * The simple fact that isc_msix_bar is not 0 does not mean we 4505 * we have a good value there that is known to work. 4506 */ 4507 msix = iflib_msix_init(ctx); 4508 else { 4509 scctx->isc_vectors = 1; 4510 scctx->isc_ntxqsets = 1; 4511 scctx->isc_nrxqsets = 1; 4512 scctx->isc_intr = IFLIB_INTR_LEGACY; 4513 msix = 0; 4514 } 4515 /* Get memory for the station queues */ 4516 if ((err = iflib_queues_alloc(ctx))) { 4517 device_printf(dev, "Unable to allocate queue memory\n"); 4518 goto fail_intr_free; 4519 } 4520 4521 if ((err = iflib_qset_structures_setup(ctx))) 4522 goto fail_queues; 4523 4524 /* 4525 * Group taskqueues aren't properly set up until SMP is started, 4526 * so we disable interrupts until we can handle them post 4527 * SI_SUB_SMP. 4528 * 4529 * XXX: disabling interrupts doesn't actually work, at least for 4530 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4531 * we do null handling and depend on this not causing too large an 4532 * interrupt storm. 4533 */ 4534 IFDI_INTR_DISABLE(ctx); 4535 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4536 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4537 goto fail_queues; 4538 } 4539 if (msix <= 1) { 4540 rid = 0; 4541 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4542 MPASS(msix == 1); 4543 rid = 1; 4544 } 4545 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4546 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4547 goto fail_queues; 4548 } 4549 } 4550 4551 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4552 4553 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4554 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4555 goto fail_detach; 4556 } 4557 4558 /* 4559 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4560 * This must appear after the call to ether_ifattach() because 4561 * ether_ifattach() sets if_hdrlen to the default value. 4562 */ 4563 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4564 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4565 4566 if ((err = iflib_netmap_attach(ctx))) { 4567 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4568 goto fail_detach; 4569 } 4570 *ctxp = ctx; 4571 4572 NETDUMP_SET(ctx->ifc_ifp, iflib); 4573 4574 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4575 iflib_add_device_sysctl_post(ctx); 4576 ctx->ifc_flags |= IFC_INIT_DONE; 4577 CTX_UNLOCK(ctx); 4578 return (0); 4579 4580 fail_detach: 4581 ether_ifdetach(ctx->ifc_ifp); 4582 fail_intr_free: 4583 iflib_free_intr_mem(ctx); 4584 fail_queues: 4585 iflib_tx_structures_free(ctx); 4586 iflib_rx_structures_free(ctx); 4587 fail_iflib_detach: 4588 IFDI_DETACH(ctx); 4589 fail_unlock: 4590 CTX_UNLOCK(ctx); 4591 fail_ctx_free: 4592 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4593 free(ctx->ifc_softc, M_IFLIB); 4594 free(ctx, M_IFLIB); 4595 return (err); 4596 } 4597 4598 int 4599 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4600 struct iflib_cloneattach_ctx *clctx) 4601 { 4602 int err; 4603 if_ctx_t ctx; 4604 if_t ifp; 4605 if_softc_ctx_t scctx; 4606 int i; 4607 void *sc; 4608 uint16_t main_txq; 4609 uint16_t main_rxq; 4610 4611 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4612 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4613 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4614 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4615 ctx->ifc_flags |= IFC_PSEUDO; 4616 4617 ctx->ifc_sctx = sctx; 4618 ctx->ifc_softc = sc; 4619 ctx->ifc_dev = dev; 4620 4621 if ((err = iflib_register(ctx)) != 0) { 4622 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4623 goto fail_ctx_free; 4624 } 4625 iflib_add_device_sysctl_pre(ctx); 4626 4627 scctx = &ctx->ifc_softc_ctx; 4628 ifp = ctx->ifc_ifp; 4629 4630 /* 4631 * XXX sanity check that ntxd & nrxd are a power of 2 4632 */ 4633 iflib_reset_qvalues(ctx); 4634 4635 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4636 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4637 goto fail_ctx_free; 4638 } 4639 if (sctx->isc_flags & IFLIB_GEN_MAC) 4640 iflib_gen_mac(ctx); 4641 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4642 clctx->cc_params)) != 0) { 4643 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4644 goto fail_ctx_free; 4645 } 4646 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4647 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4648 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4649 4650 #ifdef INVARIANTS 4651 MPASS(scctx->isc_capabilities); 4652 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4653 MPASS(scctx->isc_tx_csum_flags); 4654 #endif 4655 4656 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4657 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4658 4659 ifp->if_flags |= IFF_NOGROUP; 4660 if (sctx->isc_flags & IFLIB_PSEUDO) { 4661 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4662 4663 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4664 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4665 goto fail_detach; 4666 } 4667 *ctxp = ctx; 4668 4669 /* 4670 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4671 * This must appear after the call to ether_ifattach() because 4672 * ether_ifattach() sets if_hdrlen to the default value. 4673 */ 4674 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4675 if_setifheaderlen(ifp, 4676 sizeof(struct ether_vlan_header)); 4677 4678 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4679 iflib_add_device_sysctl_post(ctx); 4680 ctx->ifc_flags |= IFC_INIT_DONE; 4681 return (0); 4682 } 4683 _iflib_pre_assert(scctx); 4684 ctx->ifc_txrx = *scctx->isc_txrx; 4685 4686 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4687 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4688 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4689 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4690 4691 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4692 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4693 4694 /* XXX change for per-queue sizes */ 4695 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4696 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4697 for (i = 0; i < sctx->isc_nrxqs; i++) { 4698 if (!powerof2(scctx->isc_nrxd[i])) { 4699 /* round down instead? */ 4700 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4701 err = EINVAL; 4702 goto fail_iflib_detach; 4703 } 4704 } 4705 for (i = 0; i < sctx->isc_ntxqs; i++) { 4706 if (!powerof2(scctx->isc_ntxd[i])) { 4707 device_printf(dev, 4708 "# tx descriptors must be a power of 2"); 4709 err = EINVAL; 4710 goto fail_iflib_detach; 4711 } 4712 } 4713 4714 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4715 MAX_SINGLE_PACKET_FRACTION) 4716 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4717 MAX_SINGLE_PACKET_FRACTION); 4718 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4719 MAX_SINGLE_PACKET_FRACTION) 4720 scctx->isc_tx_tso_segments_max = max(1, 4721 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4722 4723 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4724 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4725 /* 4726 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4727 * but some MACs do. 4728 */ 4729 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4730 IP_MAXPACKET)); 4731 /* 4732 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4733 * into account. In the worst case, each of these calls will 4734 * add another mbuf and, thus, the requirement for another DMA 4735 * segment. So for best performance, it doesn't make sense to 4736 * advertize a maximum of TSO segments that typically will 4737 * require defragmentation in iflib_encap(). 4738 */ 4739 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4740 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4741 } 4742 if (scctx->isc_rss_table_size == 0) 4743 scctx->isc_rss_table_size = 64; 4744 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4745 4746 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4747 /* XXX format name */ 4748 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4749 4750 /* XXX --- can support > 1 -- but keep it simple for now */ 4751 scctx->isc_intr = IFLIB_INTR_LEGACY; 4752 4753 /* Get memory for the station queues */ 4754 if ((err = iflib_queues_alloc(ctx))) { 4755 device_printf(dev, "Unable to allocate queue memory\n"); 4756 goto fail_iflib_detach; 4757 } 4758 4759 if ((err = iflib_qset_structures_setup(ctx))) { 4760 device_printf(dev, "qset structure setup failed %d\n", err); 4761 goto fail_queues; 4762 } 4763 4764 /* 4765 * XXX What if anything do we want to do about interrupts? 4766 */ 4767 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4768 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4769 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4770 goto fail_detach; 4771 } 4772 4773 /* 4774 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4775 * This must appear after the call to ether_ifattach() because 4776 * ether_ifattach() sets if_hdrlen to the default value. 4777 */ 4778 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4779 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4780 4781 /* XXX handle more than one queue */ 4782 for (i = 0; i < scctx->isc_nrxqsets; i++) 4783 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4784 4785 *ctxp = ctx; 4786 4787 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4788 iflib_add_device_sysctl_post(ctx); 4789 ctx->ifc_flags |= IFC_INIT_DONE; 4790 return (0); 4791 fail_detach: 4792 ether_ifdetach(ctx->ifc_ifp); 4793 fail_queues: 4794 iflib_tx_structures_free(ctx); 4795 iflib_rx_structures_free(ctx); 4796 fail_iflib_detach: 4797 IFDI_DETACH(ctx); 4798 fail_ctx_free: 4799 free(ctx->ifc_softc, M_IFLIB); 4800 free(ctx, M_IFLIB); 4801 return (err); 4802 } 4803 4804 int 4805 iflib_pseudo_deregister(if_ctx_t ctx) 4806 { 4807 if_t ifp = ctx->ifc_ifp; 4808 iflib_txq_t txq; 4809 iflib_rxq_t rxq; 4810 int i, j; 4811 struct taskqgroup *tqg; 4812 iflib_fl_t fl; 4813 4814 /* Unregister VLAN events */ 4815 if (ctx->ifc_vlan_attach_event != NULL) 4816 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4817 if (ctx->ifc_vlan_detach_event != NULL) 4818 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4819 4820 ether_ifdetach(ifp); 4821 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4822 CTX_LOCK_DESTROY(ctx); 4823 /* XXX drain any dependent tasks */ 4824 tqg = qgroup_if_io_tqg; 4825 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4826 callout_drain(&txq->ift_timer); 4827 if (txq->ift_task.gt_uniq != NULL) 4828 taskqgroup_detach(tqg, &txq->ift_task); 4829 } 4830 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4831 if (rxq->ifr_task.gt_uniq != NULL) 4832 taskqgroup_detach(tqg, &rxq->ifr_task); 4833 4834 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4835 free(fl->ifl_rx_bitmap, M_IFLIB); 4836 } 4837 tqg = qgroup_if_config_tqg; 4838 if (ctx->ifc_admin_task.gt_uniq != NULL) 4839 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4840 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4841 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4842 4843 if_free(ifp); 4844 4845 iflib_tx_structures_free(ctx); 4846 iflib_rx_structures_free(ctx); 4847 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4848 free(ctx->ifc_softc, M_IFLIB); 4849 free(ctx, M_IFLIB); 4850 return (0); 4851 } 4852 4853 int 4854 iflib_device_attach(device_t dev) 4855 { 4856 if_ctx_t ctx; 4857 if_shared_ctx_t sctx; 4858 4859 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4860 return (ENOTSUP); 4861 4862 pci_enable_busmaster(dev); 4863 4864 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4865 } 4866 4867 int 4868 iflib_device_deregister(if_ctx_t ctx) 4869 { 4870 if_t ifp = ctx->ifc_ifp; 4871 iflib_txq_t txq; 4872 iflib_rxq_t rxq; 4873 device_t dev = ctx->ifc_dev; 4874 int i, j; 4875 struct taskqgroup *tqg; 4876 iflib_fl_t fl; 4877 4878 /* Make sure VLANS are not using driver */ 4879 if (if_vlantrunkinuse(ifp)) { 4880 device_printf(dev, "Vlan in use, detach first\n"); 4881 return (EBUSY); 4882 } 4883 #ifdef PCI_IOV 4884 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4885 device_printf(dev, "SR-IOV in use; detach first.\n"); 4886 return (EBUSY); 4887 } 4888 #endif 4889 4890 STATE_LOCK(ctx); 4891 ctx->ifc_flags |= IFC_IN_DETACH; 4892 STATE_UNLOCK(ctx); 4893 4894 CTX_LOCK(ctx); 4895 iflib_stop(ctx); 4896 CTX_UNLOCK(ctx); 4897 4898 /* Unregister VLAN events */ 4899 if (ctx->ifc_vlan_attach_event != NULL) 4900 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4901 if (ctx->ifc_vlan_detach_event != NULL) 4902 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4903 4904 iflib_netmap_detach(ifp); 4905 ether_ifdetach(ifp); 4906 if (ctx->ifc_led_dev != NULL) 4907 led_destroy(ctx->ifc_led_dev); 4908 /* XXX drain any dependent tasks */ 4909 tqg = qgroup_if_io_tqg; 4910 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4911 callout_drain(&txq->ift_timer); 4912 if (txq->ift_task.gt_uniq != NULL) 4913 taskqgroup_detach(tqg, &txq->ift_task); 4914 } 4915 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4916 if (rxq->ifr_task.gt_uniq != NULL) 4917 taskqgroup_detach(tqg, &rxq->ifr_task); 4918 4919 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4920 free(fl->ifl_rx_bitmap, M_IFLIB); 4921 } 4922 tqg = qgroup_if_config_tqg; 4923 if (ctx->ifc_admin_task.gt_uniq != NULL) 4924 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4925 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4926 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4927 CTX_LOCK(ctx); 4928 IFDI_DETACH(ctx); 4929 CTX_UNLOCK(ctx); 4930 4931 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4932 CTX_LOCK_DESTROY(ctx); 4933 device_set_softc(ctx->ifc_dev, NULL); 4934 iflib_free_intr_mem(ctx); 4935 4936 bus_generic_detach(dev); 4937 if_free(ifp); 4938 4939 iflib_tx_structures_free(ctx); 4940 iflib_rx_structures_free(ctx); 4941 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4942 free(ctx->ifc_softc, M_IFLIB); 4943 STATE_LOCK_DESTROY(ctx); 4944 free(ctx, M_IFLIB); 4945 return (0); 4946 } 4947 4948 static void 4949 iflib_free_intr_mem(if_ctx_t ctx) 4950 { 4951 4952 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4953 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4954 } 4955 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4956 pci_release_msi(ctx->ifc_dev); 4957 } 4958 if (ctx->ifc_msix_mem != NULL) { 4959 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4960 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 4961 ctx->ifc_msix_mem = NULL; 4962 } 4963 } 4964 4965 int 4966 iflib_device_detach(device_t dev) 4967 { 4968 if_ctx_t ctx = device_get_softc(dev); 4969 4970 return (iflib_device_deregister(ctx)); 4971 } 4972 4973 int 4974 iflib_device_suspend(device_t dev) 4975 { 4976 if_ctx_t ctx = device_get_softc(dev); 4977 4978 CTX_LOCK(ctx); 4979 IFDI_SUSPEND(ctx); 4980 CTX_UNLOCK(ctx); 4981 4982 return bus_generic_suspend(dev); 4983 } 4984 int 4985 iflib_device_shutdown(device_t dev) 4986 { 4987 if_ctx_t ctx = device_get_softc(dev); 4988 4989 CTX_LOCK(ctx); 4990 IFDI_SHUTDOWN(ctx); 4991 CTX_UNLOCK(ctx); 4992 4993 return bus_generic_suspend(dev); 4994 } 4995 4996 4997 int 4998 iflib_device_resume(device_t dev) 4999 { 5000 if_ctx_t ctx = device_get_softc(dev); 5001 iflib_txq_t txq = ctx->ifc_txqs; 5002 5003 CTX_LOCK(ctx); 5004 IFDI_RESUME(ctx); 5005 iflib_if_init_locked(ctx); 5006 CTX_UNLOCK(ctx); 5007 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5008 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5009 5010 return (bus_generic_resume(dev)); 5011 } 5012 5013 int 5014 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5015 { 5016 int error; 5017 if_ctx_t ctx = device_get_softc(dev); 5018 5019 CTX_LOCK(ctx); 5020 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5021 CTX_UNLOCK(ctx); 5022 5023 return (error); 5024 } 5025 5026 void 5027 iflib_device_iov_uninit(device_t dev) 5028 { 5029 if_ctx_t ctx = device_get_softc(dev); 5030 5031 CTX_LOCK(ctx); 5032 IFDI_IOV_UNINIT(ctx); 5033 CTX_UNLOCK(ctx); 5034 } 5035 5036 int 5037 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5038 { 5039 int error; 5040 if_ctx_t ctx = device_get_softc(dev); 5041 5042 CTX_LOCK(ctx); 5043 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5044 CTX_UNLOCK(ctx); 5045 5046 return (error); 5047 } 5048 5049 /********************************************************************* 5050 * 5051 * MODULE FUNCTION DEFINITIONS 5052 * 5053 **********************************************************************/ 5054 5055 /* 5056 * - Start a fast taskqueue thread for each core 5057 * - Start a taskqueue for control operations 5058 */ 5059 static int 5060 iflib_module_init(void) 5061 { 5062 return (0); 5063 } 5064 5065 static int 5066 iflib_module_event_handler(module_t mod, int what, void *arg) 5067 { 5068 int err; 5069 5070 switch (what) { 5071 case MOD_LOAD: 5072 if ((err = iflib_module_init()) != 0) 5073 return (err); 5074 break; 5075 case MOD_UNLOAD: 5076 return (EBUSY); 5077 default: 5078 return (EOPNOTSUPP); 5079 } 5080 5081 return (0); 5082 } 5083 5084 /********************************************************************* 5085 * 5086 * PUBLIC FUNCTION DEFINITIONS 5087 * ordered as in iflib.h 5088 * 5089 **********************************************************************/ 5090 5091 5092 static void 5093 _iflib_assert(if_shared_ctx_t sctx) 5094 { 5095 MPASS(sctx->isc_tx_maxsize); 5096 MPASS(sctx->isc_tx_maxsegsize); 5097 5098 MPASS(sctx->isc_rx_maxsize); 5099 MPASS(sctx->isc_rx_nsegments); 5100 MPASS(sctx->isc_rx_maxsegsize); 5101 5102 MPASS(sctx->isc_nrxd_min[0]); 5103 MPASS(sctx->isc_nrxd_max[0]); 5104 MPASS(sctx->isc_nrxd_default[0]); 5105 MPASS(sctx->isc_ntxd_min[0]); 5106 MPASS(sctx->isc_ntxd_max[0]); 5107 MPASS(sctx->isc_ntxd_default[0]); 5108 } 5109 5110 static void 5111 _iflib_pre_assert(if_softc_ctx_t scctx) 5112 { 5113 5114 MPASS(scctx->isc_txrx->ift_txd_encap); 5115 MPASS(scctx->isc_txrx->ift_txd_flush); 5116 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5117 MPASS(scctx->isc_txrx->ift_rxd_available); 5118 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5119 MPASS(scctx->isc_txrx->ift_rxd_refill); 5120 MPASS(scctx->isc_txrx->ift_rxd_flush); 5121 } 5122 5123 static int 5124 iflib_register(if_ctx_t ctx) 5125 { 5126 if_shared_ctx_t sctx = ctx->ifc_sctx; 5127 driver_t *driver = sctx->isc_driver; 5128 device_t dev = ctx->ifc_dev; 5129 if_t ifp; 5130 5131 _iflib_assert(sctx); 5132 5133 CTX_LOCK_INIT(ctx); 5134 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5135 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5136 if (ifp == NULL) { 5137 device_printf(dev, "can not allocate ifnet structure\n"); 5138 return (ENOMEM); 5139 } 5140 5141 /* 5142 * Initialize our context's device specific methods 5143 */ 5144 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5145 kobj_class_compile((kobj_class_t) driver); 5146 driver->refs++; 5147 5148 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5149 if_setsoftc(ifp, ctx); 5150 if_setdev(ifp, dev); 5151 if_setinitfn(ifp, iflib_if_init); 5152 if_setioctlfn(ifp, iflib_if_ioctl); 5153 #ifdef ALTQ 5154 if_setstartfn(ifp, iflib_altq_if_start); 5155 if_settransmitfn(ifp, iflib_altq_if_transmit); 5156 if_setsendqready(ifp); 5157 #else 5158 if_settransmitfn(ifp, iflib_if_transmit); 5159 #endif 5160 if_setqflushfn(ifp, iflib_if_qflush); 5161 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5162 5163 ctx->ifc_vlan_attach_event = 5164 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5165 EVENTHANDLER_PRI_FIRST); 5166 ctx->ifc_vlan_detach_event = 5167 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5168 EVENTHANDLER_PRI_FIRST); 5169 5170 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5171 iflib_media_change, iflib_media_status); 5172 5173 return (0); 5174 } 5175 5176 5177 static int 5178 iflib_queues_alloc(if_ctx_t ctx) 5179 { 5180 if_shared_ctx_t sctx = ctx->ifc_sctx; 5181 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5182 device_t dev = ctx->ifc_dev; 5183 int nrxqsets = scctx->isc_nrxqsets; 5184 int ntxqsets = scctx->isc_ntxqsets; 5185 iflib_txq_t txq; 5186 iflib_rxq_t rxq; 5187 iflib_fl_t fl = NULL; 5188 int i, j, cpu, err, txconf, rxconf; 5189 iflib_dma_info_t ifdip; 5190 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5191 uint32_t *txqsizes = scctx->isc_txqsizes; 5192 uint8_t nrxqs = sctx->isc_nrxqs; 5193 uint8_t ntxqs = sctx->isc_ntxqs; 5194 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5195 caddr_t *vaddrs; 5196 uint64_t *paddrs; 5197 5198 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5199 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5200 5201 /* Allocate the TX ring struct memory */ 5202 if (!(ctx->ifc_txqs = 5203 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5204 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5205 device_printf(dev, "Unable to allocate TX ring memory\n"); 5206 err = ENOMEM; 5207 goto fail; 5208 } 5209 5210 /* Now allocate the RX */ 5211 if (!(ctx->ifc_rxqs = 5212 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5213 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5214 device_printf(dev, "Unable to allocate RX ring memory\n"); 5215 err = ENOMEM; 5216 goto rx_fail; 5217 } 5218 5219 txq = ctx->ifc_txqs; 5220 rxq = ctx->ifc_rxqs; 5221 5222 /* 5223 * XXX handle allocation failure 5224 */ 5225 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5226 /* Set up some basics */ 5227 5228 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5229 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5230 device_printf(dev, 5231 "Unable to allocate TX DMA info memory\n"); 5232 err = ENOMEM; 5233 goto err_tx_desc; 5234 } 5235 txq->ift_ifdi = ifdip; 5236 for (j = 0; j < ntxqs; j++, ifdip++) { 5237 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5238 device_printf(dev, 5239 "Unable to allocate TX descriptors\n"); 5240 err = ENOMEM; 5241 goto err_tx_desc; 5242 } 5243 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5244 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5245 } 5246 txq->ift_ctx = ctx; 5247 txq->ift_id = i; 5248 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5249 txq->ift_br_offset = 1; 5250 } else { 5251 txq->ift_br_offset = 0; 5252 } 5253 /* XXX fix this */ 5254 txq->ift_timer.c_cpu = cpu; 5255 5256 if (iflib_txsd_alloc(txq)) { 5257 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5258 err = ENOMEM; 5259 goto err_tx_desc; 5260 } 5261 5262 /* Initialize the TX lock */ 5263 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5264 device_get_nameunit(dev), txq->ift_id); 5265 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5266 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5267 5268 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5269 device_get_nameunit(dev), txq->ift_id); 5270 5271 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5272 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5273 if (err) { 5274 /* XXX free any allocated rings */ 5275 device_printf(dev, "Unable to allocate buf_ring\n"); 5276 goto err_tx_desc; 5277 } 5278 } 5279 5280 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5281 /* Set up some basics */ 5282 5283 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5284 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5285 device_printf(dev, 5286 "Unable to allocate RX DMA info memory\n"); 5287 err = ENOMEM; 5288 goto err_tx_desc; 5289 } 5290 5291 rxq->ifr_ifdi = ifdip; 5292 /* XXX this needs to be changed if #rx queues != #tx queues */ 5293 rxq->ifr_ntxqirq = 1; 5294 rxq->ifr_txqid[0] = i; 5295 for (j = 0; j < nrxqs; j++, ifdip++) { 5296 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5297 device_printf(dev, 5298 "Unable to allocate RX descriptors\n"); 5299 err = ENOMEM; 5300 goto err_tx_desc; 5301 } 5302 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5303 } 5304 rxq->ifr_ctx = ctx; 5305 rxq->ifr_id = i; 5306 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5307 rxq->ifr_fl_offset = 1; 5308 } else { 5309 rxq->ifr_fl_offset = 0; 5310 } 5311 rxq->ifr_nfl = nfree_lists; 5312 if (!(fl = 5313 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5314 device_printf(dev, "Unable to allocate free list memory\n"); 5315 err = ENOMEM; 5316 goto err_tx_desc; 5317 } 5318 rxq->ifr_fl = fl; 5319 for (j = 0; j < nfree_lists; j++) { 5320 fl[j].ifl_rxq = rxq; 5321 fl[j].ifl_id = j; 5322 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5323 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5324 } 5325 /* Allocate receive buffers for the ring */ 5326 if (iflib_rxsd_alloc(rxq)) { 5327 device_printf(dev, 5328 "Critical Failure setting up receive buffers\n"); 5329 err = ENOMEM; 5330 goto err_rx_desc; 5331 } 5332 5333 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5334 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5335 M_WAITOK); 5336 } 5337 5338 /* TXQs */ 5339 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5340 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5341 for (i = 0; i < ntxqsets; i++) { 5342 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5343 5344 for (j = 0; j < ntxqs; j++, di++) { 5345 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5346 paddrs[i*ntxqs + j] = di->idi_paddr; 5347 } 5348 } 5349 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5350 device_printf(ctx->ifc_dev, 5351 "Unable to allocate device TX queue\n"); 5352 iflib_tx_structures_free(ctx); 5353 free(vaddrs, M_IFLIB); 5354 free(paddrs, M_IFLIB); 5355 goto err_rx_desc; 5356 } 5357 free(vaddrs, M_IFLIB); 5358 free(paddrs, M_IFLIB); 5359 5360 /* RXQs */ 5361 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5362 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5363 for (i = 0; i < nrxqsets; i++) { 5364 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5365 5366 for (j = 0; j < nrxqs; j++, di++) { 5367 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5368 paddrs[i*nrxqs + j] = di->idi_paddr; 5369 } 5370 } 5371 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5372 device_printf(ctx->ifc_dev, 5373 "Unable to allocate device RX queue\n"); 5374 iflib_tx_structures_free(ctx); 5375 free(vaddrs, M_IFLIB); 5376 free(paddrs, M_IFLIB); 5377 goto err_rx_desc; 5378 } 5379 free(vaddrs, M_IFLIB); 5380 free(paddrs, M_IFLIB); 5381 5382 return (0); 5383 5384 /* XXX handle allocation failure changes */ 5385 err_rx_desc: 5386 err_tx_desc: 5387 rx_fail: 5388 if (ctx->ifc_rxqs != NULL) 5389 free(ctx->ifc_rxqs, M_IFLIB); 5390 ctx->ifc_rxqs = NULL; 5391 if (ctx->ifc_txqs != NULL) 5392 free(ctx->ifc_txqs, M_IFLIB); 5393 ctx->ifc_txqs = NULL; 5394 fail: 5395 return (err); 5396 } 5397 5398 static int 5399 iflib_tx_structures_setup(if_ctx_t ctx) 5400 { 5401 iflib_txq_t txq = ctx->ifc_txqs; 5402 int i; 5403 5404 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5405 iflib_txq_setup(txq); 5406 5407 return (0); 5408 } 5409 5410 static void 5411 iflib_tx_structures_free(if_ctx_t ctx) 5412 { 5413 iflib_txq_t txq = ctx->ifc_txqs; 5414 if_shared_ctx_t sctx = ctx->ifc_sctx; 5415 int i, j; 5416 5417 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5418 iflib_txq_destroy(txq); 5419 for (j = 0; j < sctx->isc_ntxqs; j++) 5420 iflib_dma_free(&txq->ift_ifdi[j]); 5421 } 5422 free(ctx->ifc_txqs, M_IFLIB); 5423 ctx->ifc_txqs = NULL; 5424 IFDI_QUEUES_FREE(ctx); 5425 } 5426 5427 /********************************************************************* 5428 * 5429 * Initialize all receive rings. 5430 * 5431 **********************************************************************/ 5432 static int 5433 iflib_rx_structures_setup(if_ctx_t ctx) 5434 { 5435 iflib_rxq_t rxq = ctx->ifc_rxqs; 5436 int q; 5437 #if defined(INET6) || defined(INET) 5438 int i, err; 5439 #endif 5440 5441 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5442 #if defined(INET6) || defined(INET) 5443 tcp_lro_free(&rxq->ifr_lc); 5444 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5445 TCP_LRO_ENTRIES, min(1024, 5446 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5447 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5448 goto fail; 5449 } 5450 rxq->ifr_lro_enabled = TRUE; 5451 #endif 5452 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5453 } 5454 return (0); 5455 #if defined(INET6) || defined(INET) 5456 fail: 5457 /* 5458 * Free RX software descriptors allocated so far, we will only handle 5459 * the rings that completed, the failing case will have 5460 * cleaned up for itself. 'q' failed, so its the terminus. 5461 */ 5462 rxq = ctx->ifc_rxqs; 5463 for (i = 0; i < q; ++i, rxq++) { 5464 iflib_rx_sds_free(rxq); 5465 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5466 } 5467 return (err); 5468 #endif 5469 } 5470 5471 /********************************************************************* 5472 * 5473 * Free all receive rings. 5474 * 5475 **********************************************************************/ 5476 static void 5477 iflib_rx_structures_free(if_ctx_t ctx) 5478 { 5479 iflib_rxq_t rxq = ctx->ifc_rxqs; 5480 5481 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5482 iflib_rx_sds_free(rxq); 5483 } 5484 free(ctx->ifc_rxqs, M_IFLIB); 5485 ctx->ifc_rxqs = NULL; 5486 } 5487 5488 static int 5489 iflib_qset_structures_setup(if_ctx_t ctx) 5490 { 5491 int err; 5492 5493 /* 5494 * It is expected that the caller takes care of freeing queues if this 5495 * fails. 5496 */ 5497 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5498 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5499 return (err); 5500 } 5501 5502 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5503 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5504 5505 return (err); 5506 } 5507 5508 int 5509 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5510 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5511 { 5512 5513 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5514 } 5515 5516 #ifdef SMP 5517 static int 5518 find_nth(if_ctx_t ctx, int qid) 5519 { 5520 cpuset_t cpus; 5521 int i, cpuid, eqid, count; 5522 5523 CPU_COPY(&ctx->ifc_cpus, &cpus); 5524 count = CPU_COUNT(&cpus); 5525 eqid = qid % count; 5526 /* clear up to the qid'th bit */ 5527 for (i = 0; i < eqid; i++) { 5528 cpuid = CPU_FFS(&cpus); 5529 MPASS(cpuid != 0); 5530 CPU_CLR(cpuid-1, &cpus); 5531 } 5532 cpuid = CPU_FFS(&cpus); 5533 MPASS(cpuid != 0); 5534 return (cpuid-1); 5535 } 5536 5537 #ifdef SCHED_ULE 5538 extern struct cpu_group *cpu_top; /* CPU topology */ 5539 5540 static int 5541 find_child_with_core(int cpu, struct cpu_group *grp) 5542 { 5543 int i; 5544 5545 if (grp->cg_children == 0) 5546 return -1; 5547 5548 MPASS(grp->cg_child); 5549 for (i = 0; i < grp->cg_children; i++) { 5550 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5551 return i; 5552 } 5553 5554 return -1; 5555 } 5556 5557 /* 5558 * Find the nth "close" core to the specified core 5559 * "close" is defined as the deepest level that shares 5560 * at least an L2 cache. With threads, this will be 5561 * threads on the same core. If the sahred cache is L3 5562 * or higher, simply returns the same core. 5563 */ 5564 static int 5565 find_close_core(int cpu, int core_offset) 5566 { 5567 struct cpu_group *grp; 5568 int i; 5569 int fcpu; 5570 cpuset_t cs; 5571 5572 grp = cpu_top; 5573 if (grp == NULL) 5574 return cpu; 5575 i = 0; 5576 while ((i = find_child_with_core(cpu, grp)) != -1) { 5577 /* If the child only has one cpu, don't descend */ 5578 if (grp->cg_child[i].cg_count <= 1) 5579 break; 5580 grp = &grp->cg_child[i]; 5581 } 5582 5583 /* If they don't share at least an L2 cache, use the same CPU */ 5584 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5585 return cpu; 5586 5587 /* Now pick one */ 5588 CPU_COPY(&grp->cg_mask, &cs); 5589 5590 /* Add the selected CPU offset to core offset. */ 5591 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5592 if (fcpu - 1 == cpu) 5593 break; 5594 CPU_CLR(fcpu - 1, &cs); 5595 } 5596 MPASS(fcpu); 5597 5598 core_offset += i; 5599 5600 CPU_COPY(&grp->cg_mask, &cs); 5601 for (i = core_offset % grp->cg_count; i > 0; i--) { 5602 MPASS(CPU_FFS(&cs)); 5603 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5604 } 5605 MPASS(CPU_FFS(&cs)); 5606 return CPU_FFS(&cs) - 1; 5607 } 5608 #else 5609 static int 5610 find_close_core(int cpu, int core_offset __unused) 5611 { 5612 return cpu; 5613 } 5614 #endif 5615 5616 static int 5617 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5618 { 5619 switch (type) { 5620 case IFLIB_INTR_TX: 5621 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5622 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5623 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5624 case IFLIB_INTR_RX: 5625 case IFLIB_INTR_RXTX: 5626 /* RX queues get the specified core */ 5627 return qid / CPU_COUNT(&ctx->ifc_cpus); 5628 default: 5629 return -1; 5630 } 5631 } 5632 #else 5633 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5634 #define find_close_core(cpuid, tid) CPU_FIRST() 5635 #define find_nth(ctx, gid) CPU_FIRST() 5636 #endif 5637 5638 /* Just to avoid copy/paste */ 5639 static inline int 5640 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5641 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5642 { 5643 int cpuid; 5644 int err, tid; 5645 5646 cpuid = find_nth(ctx, qid); 5647 tid = get_core_offset(ctx, type, qid); 5648 MPASS(tid >= 0); 5649 cpuid = find_close_core(cpuid, tid); 5650 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5651 if (err) { 5652 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5653 return (err); 5654 } 5655 #ifdef notyet 5656 if (cpuid > ctx->ifc_cpuid_highest) 5657 ctx->ifc_cpuid_highest = cpuid; 5658 #endif 5659 return 0; 5660 } 5661 5662 int 5663 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5664 iflib_intr_type_t type, driver_filter_t *filter, 5665 void *filter_arg, int qid, const char *name) 5666 { 5667 struct grouptask *gtask; 5668 struct taskqgroup *tqg; 5669 iflib_filter_info_t info; 5670 gtask_fn_t *fn; 5671 int tqrid, err; 5672 driver_filter_t *intr_fast; 5673 void *q; 5674 5675 info = &ctx->ifc_filter_info; 5676 tqrid = rid; 5677 5678 switch (type) { 5679 /* XXX merge tx/rx for netmap? */ 5680 case IFLIB_INTR_TX: 5681 q = &ctx->ifc_txqs[qid]; 5682 info = &ctx->ifc_txqs[qid].ift_filter_info; 5683 gtask = &ctx->ifc_txqs[qid].ift_task; 5684 tqg = qgroup_if_io_tqg; 5685 fn = _task_fn_tx; 5686 intr_fast = iflib_fast_intr; 5687 GROUPTASK_INIT(gtask, 0, fn, q); 5688 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5689 break; 5690 case IFLIB_INTR_RX: 5691 q = &ctx->ifc_rxqs[qid]; 5692 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5693 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5694 tqg = qgroup_if_io_tqg; 5695 fn = _task_fn_rx; 5696 intr_fast = iflib_fast_intr; 5697 GROUPTASK_INIT(gtask, 0, fn, q); 5698 break; 5699 case IFLIB_INTR_RXTX: 5700 q = &ctx->ifc_rxqs[qid]; 5701 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5702 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5703 tqg = qgroup_if_io_tqg; 5704 fn = _task_fn_rx; 5705 intr_fast = iflib_fast_intr_rxtx; 5706 GROUPTASK_INIT(gtask, 0, fn, q); 5707 break; 5708 case IFLIB_INTR_ADMIN: 5709 q = ctx; 5710 tqrid = -1; 5711 info = &ctx->ifc_filter_info; 5712 gtask = &ctx->ifc_admin_task; 5713 tqg = qgroup_if_config_tqg; 5714 fn = _task_fn_admin; 5715 intr_fast = iflib_fast_intr_ctx; 5716 break; 5717 default: 5718 panic("unknown net intr type"); 5719 } 5720 5721 info->ifi_filter = filter; 5722 info->ifi_filter_arg = filter_arg; 5723 info->ifi_task = gtask; 5724 info->ifi_ctx = q; 5725 5726 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5727 if (err != 0) { 5728 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5729 return (err); 5730 } 5731 if (type == IFLIB_INTR_ADMIN) 5732 return (0); 5733 5734 if (tqrid != -1) { 5735 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5736 if (err) 5737 return (err); 5738 } else { 5739 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5740 } 5741 5742 return (0); 5743 } 5744 5745 void 5746 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5747 { 5748 struct grouptask *gtask; 5749 struct taskqgroup *tqg; 5750 gtask_fn_t *fn; 5751 void *q; 5752 int irq_num = -1; 5753 int err; 5754 5755 switch (type) { 5756 case IFLIB_INTR_TX: 5757 q = &ctx->ifc_txqs[qid]; 5758 gtask = &ctx->ifc_txqs[qid].ift_task; 5759 tqg = qgroup_if_io_tqg; 5760 fn = _task_fn_tx; 5761 if (irq != NULL) 5762 irq_num = rman_get_start(irq->ii_res); 5763 break; 5764 case IFLIB_INTR_RX: 5765 q = &ctx->ifc_rxqs[qid]; 5766 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5767 tqg = qgroup_if_io_tqg; 5768 fn = _task_fn_rx; 5769 if (irq != NULL) 5770 irq_num = rman_get_start(irq->ii_res); 5771 break; 5772 case IFLIB_INTR_IOV: 5773 q = ctx; 5774 gtask = &ctx->ifc_vflr_task; 5775 tqg = qgroup_if_config_tqg; 5776 fn = _task_fn_iov; 5777 break; 5778 default: 5779 panic("unknown net intr type"); 5780 } 5781 GROUPTASK_INIT(gtask, 0, fn, q); 5782 if (irq_num != -1) { 5783 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5784 if (err) 5785 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5786 } 5787 else { 5788 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5789 } 5790 } 5791 5792 void 5793 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5794 { 5795 5796 if (irq->ii_tag) 5797 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5798 5799 if (irq->ii_res) 5800 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5801 rman_get_rid(irq->ii_res), irq->ii_res); 5802 } 5803 5804 static int 5805 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5806 { 5807 iflib_txq_t txq = ctx->ifc_txqs; 5808 iflib_rxq_t rxq = ctx->ifc_rxqs; 5809 if_irq_t irq = &ctx->ifc_legacy_irq; 5810 iflib_filter_info_t info; 5811 struct grouptask *gtask; 5812 struct taskqgroup *tqg; 5813 gtask_fn_t *fn; 5814 int tqrid; 5815 void *q; 5816 int err; 5817 5818 q = &ctx->ifc_rxqs[0]; 5819 info = &rxq[0].ifr_filter_info; 5820 gtask = &rxq[0].ifr_task; 5821 tqg = qgroup_if_io_tqg; 5822 tqrid = irq->ii_rid = *rid; 5823 fn = _task_fn_rx; 5824 5825 ctx->ifc_flags |= IFC_LEGACY; 5826 info->ifi_filter = filter; 5827 info->ifi_filter_arg = filter_arg; 5828 info->ifi_task = gtask; 5829 info->ifi_ctx = ctx; 5830 5831 /* We allocate a single interrupt resource */ 5832 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5833 return (err); 5834 GROUPTASK_INIT(gtask, 0, fn, q); 5835 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5836 5837 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5838 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5839 return (0); 5840 } 5841 5842 void 5843 iflib_led_create(if_ctx_t ctx) 5844 { 5845 5846 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5847 device_get_nameunit(ctx->ifc_dev)); 5848 } 5849 5850 void 5851 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5852 { 5853 5854 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5855 } 5856 5857 void 5858 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5859 { 5860 5861 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5862 } 5863 5864 void 5865 iflib_admin_intr_deferred(if_ctx_t ctx) 5866 { 5867 #ifdef INVARIANTS 5868 struct grouptask *gtask; 5869 5870 gtask = &ctx->ifc_admin_task; 5871 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5872 #endif 5873 5874 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5875 } 5876 5877 void 5878 iflib_iov_intr_deferred(if_ctx_t ctx) 5879 { 5880 5881 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5882 } 5883 5884 void 5885 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5886 { 5887 5888 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5889 } 5890 5891 void 5892 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5893 const char *name) 5894 { 5895 5896 GROUPTASK_INIT(gtask, 0, fn, ctx); 5897 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5898 } 5899 5900 void 5901 iflib_config_gtask_deinit(struct grouptask *gtask) 5902 { 5903 5904 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5905 } 5906 5907 void 5908 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5909 { 5910 if_t ifp = ctx->ifc_ifp; 5911 iflib_txq_t txq = ctx->ifc_txqs; 5912 5913 if_setbaudrate(ifp, baudrate); 5914 if (baudrate >= IF_Gbps(10)) { 5915 STATE_LOCK(ctx); 5916 ctx->ifc_flags |= IFC_PREFETCH; 5917 STATE_UNLOCK(ctx); 5918 } 5919 /* If link down, disable watchdog */ 5920 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5921 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5922 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5923 } 5924 ctx->ifc_link_state = link_state; 5925 if_link_state_change(ifp, link_state); 5926 } 5927 5928 static int 5929 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5930 { 5931 int credits; 5932 #ifdef INVARIANTS 5933 int credits_pre = txq->ift_cidx_processed; 5934 #endif 5935 5936 if (ctx->isc_txd_credits_update == NULL) 5937 return (0); 5938 5939 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 5940 BUS_DMASYNC_POSTREAD); 5941 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5942 return (0); 5943 5944 txq->ift_processed += credits; 5945 txq->ift_cidx_processed += credits; 5946 5947 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5948 if (txq->ift_cidx_processed >= txq->ift_size) 5949 txq->ift_cidx_processed -= txq->ift_size; 5950 return (credits); 5951 } 5952 5953 static int 5954 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5955 { 5956 5957 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5958 budget)); 5959 } 5960 5961 void 5962 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5963 const char *description, if_int_delay_info_t info, 5964 int offset, int value) 5965 { 5966 info->iidi_ctx = ctx; 5967 info->iidi_offset = offset; 5968 info->iidi_value = value; 5969 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5970 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5971 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5972 info, 0, iflib_sysctl_int_delay, "I", description); 5973 } 5974 5975 struct sx * 5976 iflib_ctx_lock_get(if_ctx_t ctx) 5977 { 5978 5979 return (&ctx->ifc_ctx_sx); 5980 } 5981 5982 static int 5983 iflib_msix_init(if_ctx_t ctx) 5984 { 5985 device_t dev = ctx->ifc_dev; 5986 if_shared_ctx_t sctx = ctx->ifc_sctx; 5987 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5988 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5989 int iflib_num_tx_queues, iflib_num_rx_queues; 5990 int err, admincnt, bar; 5991 5992 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5993 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5994 5995 if (bootverbose) 5996 device_printf(dev, "msix_init qsets capped at %d\n", 5997 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5998 5999 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6000 admincnt = sctx->isc_admin_intrcnt; 6001 /* Override by tuneable */ 6002 if (scctx->isc_disable_msix) 6003 goto msi; 6004 6005 /* First try MSI-X */ 6006 if ((msgs = pci_msix_count(dev)) == 0) { 6007 if (bootverbose) 6008 device_printf(dev, "MSI-X not supported or disabled\n"); 6009 goto msi; 6010 } 6011 /* 6012 * bar == -1 => "trust me I know what I'm doing" 6013 * Some drivers are for hardware that is so shoddily 6014 * documented that no one knows which bars are which 6015 * so the developer has to map all bars. This hack 6016 * allows shoddy garbage to use MSI-X in this framework. 6017 */ 6018 if (bar != -1) { 6019 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6020 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6021 if (ctx->ifc_msix_mem == NULL) { 6022 device_printf(dev, "Unable to map MSI-X table\n"); 6023 goto msi; 6024 } 6025 } 6026 #if IFLIB_DEBUG 6027 /* use only 1 qset in debug mode */ 6028 queuemsgs = min(msgs - admincnt, 1); 6029 #else 6030 queuemsgs = msgs - admincnt; 6031 #endif 6032 #ifdef RSS 6033 queues = imin(queuemsgs, rss_getnumbuckets()); 6034 #else 6035 queues = queuemsgs; 6036 #endif 6037 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6038 if (bootverbose) 6039 device_printf(dev, 6040 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6041 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6042 #ifdef RSS 6043 /* If we're doing RSS, clamp at the number of RSS buckets */ 6044 if (queues > rss_getnumbuckets()) 6045 queues = rss_getnumbuckets(); 6046 #endif 6047 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6048 rx_queues = iflib_num_rx_queues; 6049 else 6050 rx_queues = queues; 6051 6052 if (rx_queues > scctx->isc_nrxqsets) 6053 rx_queues = scctx->isc_nrxqsets; 6054 6055 /* 6056 * We want this to be all logical CPUs by default 6057 */ 6058 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6059 tx_queues = iflib_num_tx_queues; 6060 else 6061 tx_queues = mp_ncpus; 6062 6063 if (tx_queues > scctx->isc_ntxqsets) 6064 tx_queues = scctx->isc_ntxqsets; 6065 6066 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6067 #ifdef INVARIANTS 6068 if (tx_queues != rx_queues) 6069 device_printf(dev, 6070 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6071 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6072 #endif 6073 tx_queues = min(rx_queues, tx_queues); 6074 rx_queues = min(rx_queues, tx_queues); 6075 } 6076 6077 device_printf(dev, "Using %d rx queues %d tx queues\n", 6078 rx_queues, tx_queues); 6079 6080 vectors = rx_queues + admincnt; 6081 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6082 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6083 vectors); 6084 scctx->isc_vectors = vectors; 6085 scctx->isc_nrxqsets = rx_queues; 6086 scctx->isc_ntxqsets = tx_queues; 6087 scctx->isc_intr = IFLIB_INTR_MSIX; 6088 6089 return (vectors); 6090 } else { 6091 device_printf(dev, 6092 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n", 6093 vectors, err); 6094 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6095 ctx->ifc_msix_mem); 6096 ctx->ifc_msix_mem = NULL; 6097 } 6098 msi: 6099 vectors = pci_msi_count(dev); 6100 scctx->isc_nrxqsets = 1; 6101 scctx->isc_ntxqsets = 1; 6102 scctx->isc_vectors = vectors; 6103 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6104 device_printf(dev,"Using an MSI interrupt\n"); 6105 scctx->isc_intr = IFLIB_INTR_MSI; 6106 } else { 6107 scctx->isc_vectors = 1; 6108 device_printf(dev,"Using a Legacy interrupt\n"); 6109 scctx->isc_intr = IFLIB_INTR_LEGACY; 6110 } 6111 6112 return (vectors); 6113 } 6114 6115 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6116 6117 static int 6118 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6119 { 6120 int rc; 6121 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6122 struct sbuf *sb; 6123 const char *ring_state = "UNKNOWN"; 6124 6125 /* XXX needed ? */ 6126 rc = sysctl_wire_old_buffer(req, 0); 6127 MPASS(rc == 0); 6128 if (rc != 0) 6129 return (rc); 6130 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6131 MPASS(sb != NULL); 6132 if (sb == NULL) 6133 return (ENOMEM); 6134 if (state[3] <= 3) 6135 ring_state = ring_states[state[3]]; 6136 6137 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6138 state[0], state[1], state[2], ring_state); 6139 rc = sbuf_finish(sb); 6140 sbuf_delete(sb); 6141 return(rc); 6142 } 6143 6144 enum iflib_ndesc_handler { 6145 IFLIB_NTXD_HANDLER, 6146 IFLIB_NRXD_HANDLER, 6147 }; 6148 6149 static int 6150 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6151 { 6152 if_ctx_t ctx = (void *)arg1; 6153 enum iflib_ndesc_handler type = arg2; 6154 char buf[256] = {0}; 6155 qidx_t *ndesc; 6156 char *p, *next; 6157 int nqs, rc, i; 6158 6159 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6160 6161 nqs = 8; 6162 switch(type) { 6163 case IFLIB_NTXD_HANDLER: 6164 ndesc = ctx->ifc_sysctl_ntxds; 6165 if (ctx->ifc_sctx) 6166 nqs = ctx->ifc_sctx->isc_ntxqs; 6167 break; 6168 case IFLIB_NRXD_HANDLER: 6169 ndesc = ctx->ifc_sysctl_nrxds; 6170 if (ctx->ifc_sctx) 6171 nqs = ctx->ifc_sctx->isc_nrxqs; 6172 break; 6173 default: 6174 panic("unhandled type"); 6175 } 6176 if (nqs == 0) 6177 nqs = 8; 6178 6179 for (i=0; i<8; i++) { 6180 if (i >= nqs) 6181 break; 6182 if (i) 6183 strcat(buf, ","); 6184 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6185 } 6186 6187 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6188 if (rc || req->newptr == NULL) 6189 return rc; 6190 6191 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6192 i++, p = strsep(&next, " ,")) { 6193 ndesc[i] = strtoul(p, NULL, 10); 6194 } 6195 6196 return(rc); 6197 } 6198 6199 #define NAME_BUFLEN 32 6200 static void 6201 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6202 { 6203 device_t dev = iflib_get_dev(ctx); 6204 struct sysctl_oid_list *child, *oid_list; 6205 struct sysctl_ctx_list *ctx_list; 6206 struct sysctl_oid *node; 6207 6208 ctx_list = device_get_sysctl_ctx(dev); 6209 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6210 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6211 CTLFLAG_RD, NULL, "IFLIB fields"); 6212 oid_list = SYSCTL_CHILDREN(node); 6213 6214 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6215 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6216 "driver version"); 6217 6218 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6219 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6220 "# of txqs to use, 0 => use default #"); 6221 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6222 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6223 "# of rxqs to use, 0 => use default #"); 6224 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6225 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6226 "permit #txq != #rxq"); 6227 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6228 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6229 "disable MSI-X (default 0)"); 6230 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6231 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6232 "set the rx budget"); 6233 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6234 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6235 "cause tx to abdicate instead of running to completion"); 6236 6237 /* XXX change for per-queue sizes */ 6238 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6239 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6240 mp_ndesc_handler, "A", 6241 "list of # of tx descriptors to use, 0 = use default #"); 6242 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6243 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6244 mp_ndesc_handler, "A", 6245 "list of # of rx descriptors to use, 0 = use default #"); 6246 } 6247 6248 static void 6249 iflib_add_device_sysctl_post(if_ctx_t ctx) 6250 { 6251 if_shared_ctx_t sctx = ctx->ifc_sctx; 6252 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6253 device_t dev = iflib_get_dev(ctx); 6254 struct sysctl_oid_list *child; 6255 struct sysctl_ctx_list *ctx_list; 6256 iflib_fl_t fl; 6257 iflib_txq_t txq; 6258 iflib_rxq_t rxq; 6259 int i, j; 6260 char namebuf[NAME_BUFLEN]; 6261 char *qfmt; 6262 struct sysctl_oid *queue_node, *fl_node, *node; 6263 struct sysctl_oid_list *queue_list, *fl_list; 6264 ctx_list = device_get_sysctl_ctx(dev); 6265 6266 node = ctx->ifc_sysctl_node; 6267 child = SYSCTL_CHILDREN(node); 6268 6269 if (scctx->isc_ntxqsets > 100) 6270 qfmt = "txq%03d"; 6271 else if (scctx->isc_ntxqsets > 10) 6272 qfmt = "txq%02d"; 6273 else 6274 qfmt = "txq%d"; 6275 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6276 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6277 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6278 CTLFLAG_RD, NULL, "Queue Name"); 6279 queue_list = SYSCTL_CHILDREN(queue_node); 6280 #if MEMORY_LOGGING 6281 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6282 CTLFLAG_RD, 6283 &txq->ift_dequeued, "total mbufs freed"); 6284 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6285 CTLFLAG_RD, 6286 &txq->ift_enqueued, "total mbufs enqueued"); 6287 #endif 6288 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6289 CTLFLAG_RD, 6290 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6291 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6292 CTLFLAG_RD, 6293 &txq->ift_pullups, "# of times m_pullup was called"); 6294 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6295 CTLFLAG_RD, 6296 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6297 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6298 CTLFLAG_RD, 6299 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6300 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6301 CTLFLAG_RD, 6302 &txq->ift_map_failed, "# of times dma map failed"); 6303 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6304 CTLFLAG_RD, 6305 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6306 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6307 CTLFLAG_RD, 6308 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6309 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6310 CTLFLAG_RD, 6311 &txq->ift_pidx, 1, "Producer Index"); 6312 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6313 CTLFLAG_RD, 6314 &txq->ift_cidx, 1, "Consumer Index"); 6315 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6316 CTLFLAG_RD, 6317 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6318 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6319 CTLFLAG_RD, 6320 &txq->ift_in_use, 1, "descriptors in use"); 6321 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6322 CTLFLAG_RD, 6323 &txq->ift_processed, "descriptors procesed for clean"); 6324 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6325 CTLFLAG_RD, 6326 &txq->ift_cleaned, "total cleaned"); 6327 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6328 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6329 0, mp_ring_state_handler, "A", "soft ring state"); 6330 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6331 CTLFLAG_RD, &txq->ift_br->enqueues, 6332 "# of enqueues to the mp_ring for this queue"); 6333 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6334 CTLFLAG_RD, &txq->ift_br->drops, 6335 "# of drops in the mp_ring for this queue"); 6336 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6337 CTLFLAG_RD, &txq->ift_br->starts, 6338 "# of normal consumer starts in the mp_ring for this queue"); 6339 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6340 CTLFLAG_RD, &txq->ift_br->stalls, 6341 "# of consumer stalls in the mp_ring for this queue"); 6342 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6343 CTLFLAG_RD, &txq->ift_br->restarts, 6344 "# of consumer restarts in the mp_ring for this queue"); 6345 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6346 CTLFLAG_RD, &txq->ift_br->abdications, 6347 "# of consumer abdications in the mp_ring for this queue"); 6348 } 6349 6350 if (scctx->isc_nrxqsets > 100) 6351 qfmt = "rxq%03d"; 6352 else if (scctx->isc_nrxqsets > 10) 6353 qfmt = "rxq%02d"; 6354 else 6355 qfmt = "rxq%d"; 6356 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6357 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6358 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6359 CTLFLAG_RD, NULL, "Queue Name"); 6360 queue_list = SYSCTL_CHILDREN(queue_node); 6361 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6362 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6363 CTLFLAG_RD, 6364 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6365 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6366 CTLFLAG_RD, 6367 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6368 } 6369 6370 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6371 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6372 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6373 CTLFLAG_RD, NULL, "freelist Name"); 6374 fl_list = SYSCTL_CHILDREN(fl_node); 6375 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6376 CTLFLAG_RD, 6377 &fl->ifl_pidx, 1, "Producer Index"); 6378 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6379 CTLFLAG_RD, 6380 &fl->ifl_cidx, 1, "Consumer Index"); 6381 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6382 CTLFLAG_RD, 6383 &fl->ifl_credits, 1, "credits available"); 6384 #if MEMORY_LOGGING 6385 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6386 CTLFLAG_RD, 6387 &fl->ifl_m_enqueued, "mbufs allocated"); 6388 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6389 CTLFLAG_RD, 6390 &fl->ifl_m_dequeued, "mbufs freed"); 6391 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6392 CTLFLAG_RD, 6393 &fl->ifl_cl_enqueued, "clusters allocated"); 6394 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6395 CTLFLAG_RD, 6396 &fl->ifl_cl_dequeued, "clusters freed"); 6397 #endif 6398 6399 } 6400 } 6401 6402 } 6403 6404 void 6405 iflib_request_reset(if_ctx_t ctx) 6406 { 6407 6408 STATE_LOCK(ctx); 6409 ctx->ifc_flags |= IFC_DO_RESET; 6410 STATE_UNLOCK(ctx); 6411 } 6412 6413 #ifndef __NO_STRICT_ALIGNMENT 6414 static struct mbuf * 6415 iflib_fixup_rx(struct mbuf *m) 6416 { 6417 struct mbuf *n; 6418 6419 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6420 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6421 m->m_data += ETHER_HDR_LEN; 6422 n = m; 6423 } else { 6424 MGETHDR(n, M_NOWAIT, MT_DATA); 6425 if (n == NULL) { 6426 m_freem(m); 6427 return (NULL); 6428 } 6429 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6430 m->m_data += ETHER_HDR_LEN; 6431 m->m_len -= ETHER_HDR_LEN; 6432 n->m_len = ETHER_HDR_LEN; 6433 M_MOVE_PKTHDR(n, m); 6434 n->m_next = m; 6435 } 6436 return (n); 6437 } 6438 #endif 6439 6440 #ifdef NETDUMP 6441 static void 6442 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6443 { 6444 if_ctx_t ctx; 6445 6446 ctx = if_getsoftc(ifp); 6447 CTX_LOCK(ctx); 6448 *nrxr = NRXQSETS(ctx); 6449 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6450 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6451 CTX_UNLOCK(ctx); 6452 } 6453 6454 static void 6455 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6456 { 6457 if_ctx_t ctx; 6458 if_softc_ctx_t scctx; 6459 iflib_fl_t fl; 6460 iflib_rxq_t rxq; 6461 int i, j; 6462 6463 ctx = if_getsoftc(ifp); 6464 scctx = &ctx->ifc_softc_ctx; 6465 6466 switch (event) { 6467 case NETDUMP_START: 6468 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6469 rxq = &ctx->ifc_rxqs[i]; 6470 for (j = 0; j < rxq->ifr_nfl; j++) { 6471 fl = rxq->ifr_fl; 6472 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6473 } 6474 } 6475 iflib_no_tx_batch = 1; 6476 break; 6477 default: 6478 break; 6479 } 6480 } 6481 6482 static int 6483 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6484 { 6485 if_ctx_t ctx; 6486 iflib_txq_t txq; 6487 int error; 6488 6489 ctx = if_getsoftc(ifp); 6490 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6491 IFF_DRV_RUNNING) 6492 return (EBUSY); 6493 6494 txq = &ctx->ifc_txqs[0]; 6495 error = iflib_encap(txq, &m); 6496 if (error == 0) 6497 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6498 return (error); 6499 } 6500 6501 static int 6502 iflib_netdump_poll(struct ifnet *ifp, int count) 6503 { 6504 if_ctx_t ctx; 6505 if_softc_ctx_t scctx; 6506 iflib_txq_t txq; 6507 int i; 6508 6509 ctx = if_getsoftc(ifp); 6510 scctx = &ctx->ifc_softc_ctx; 6511 6512 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6513 IFF_DRV_RUNNING) 6514 return (EBUSY); 6515 6516 txq = &ctx->ifc_txqs[0]; 6517 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6518 6519 for (i = 0; i < scctx->isc_nrxqsets; i++) 6520 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6521 return (0); 6522 } 6523 #endif /* NETDUMP */ 6524