1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 qidx_t ifsd_cidx; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_deregister(if_ctx_t); 706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 707 static void iflib_init_locked(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 710 static void iflib_ifmp_purge(iflib_txq_t txq); 711 static void _iflib_pre_assert(if_softc_ctx_t scctx); 712 static void iflib_if_init_locked(if_ctx_t ctx); 713 static void iflib_free_intr_mem(if_ctx_t ctx); 714 #ifndef __NO_STRICT_ALIGNMENT 715 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 716 #endif 717 718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 719 SLIST_HEAD_INITIALIZER(cpu_offsets); 720 struct cpu_offset { 721 SLIST_ENTRY(cpu_offset) entries; 722 cpuset_t set; 723 unsigned int refcount; 724 uint16_t offset; 725 }; 726 static struct mtx cpu_offset_mtx; 727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 728 MTX_DEF); 729 730 DEBUGNET_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 if_t ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init)) { 849 netmap_load_map(na, fl->ifl_buf_tag, 850 map[nic_i], addr); 851 } else if (slot->flags & NS_BUF_CHANGED) { 852 /* buffer has changed, reload map */ 853 netmap_reload_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } 856 slot->flags &= ~NS_BUF_CHANGED; 857 858 nm_i = nm_next(nm_i, lim); 859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 861 continue; 862 863 iru.iru_pidx = refill_pidx; 864 iru.iru_count = tmp_pidx+1; 865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 866 refill_pidx = nic_i; 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 879 if (__predict_true(nic_i != UINT_MAX)) { 880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 881 DBG_COUNTER_INC(rxd_flush); 882 } 883 return (0); 884 } 885 886 /* 887 * Reconcile kernel and user view of the transmit ring. 888 * 889 * All information is in the kring. 890 * Userspace wants to send packets up to the one before kring->rhead, 891 * kernel knows kring->nr_hwcur is the first unsent packet. 892 * 893 * Here we push packets out (as many as possible), and possibly 894 * reclaim buffers from previously completed transmission. 895 * 896 * The caller (netmap) guarantees that there is only one instance 897 * running at any time. Any interference with other driver 898 * methods should be handled by the individual drivers. 899 */ 900 static int 901 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 902 { 903 struct netmap_adapter *na = kring->na; 904 if_t ifp = na->ifp; 905 struct netmap_ring *ring = kring->ring; 906 u_int nm_i; /* index into the netmap kring */ 907 u_int nic_i; /* index into the NIC ring */ 908 u_int n; 909 u_int const lim = kring->nkr_num_slots - 1; 910 u_int const head = kring->rhead; 911 struct if_pkt_info pi; 912 913 /* 914 * interrupts on every tx packet are expensive so request 915 * them every half ring, or where NS_REPORT is set 916 */ 917 u_int report_frequency = kring->nkr_num_slots >> 1; 918 /* device-specific */ 919 if_ctx_t ctx = ifp->if_softc; 920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 921 922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 924 925 /* 926 * First part: process new packets to send. 927 * nm_i is the current index in the netmap kring, 928 * nic_i is the corresponding index in the NIC ring. 929 * 930 * If we have packets to send (nm_i != head) 931 * iterate over the netmap ring, fetch length and update 932 * the corresponding slot in the NIC ring. Some drivers also 933 * need to update the buffer's physical address in the NIC slot 934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 935 * 936 * The netmap_reload_map() calls is especially expensive, 937 * even when (as in this case) the tag is 0, so do only 938 * when the buffer has actually changed. 939 * 940 * If possible do not set the report/intr bit on all slots, 941 * but only a few times per ring or when NS_REPORT is set. 942 * 943 * Finally, on 10G and faster drivers, it might be useful 944 * to prefetch the next slot and txr entry. 945 */ 946 947 nm_i = kring->nr_hwcur; 948 if (nm_i != head) { /* we have new packets to send */ 949 pkt_info_zero(&pi); 950 pi.ipi_segs = txq->ift_segs; 951 pi.ipi_qsidx = kring->ring_id; 952 nic_i = netmap_idx_k2n(kring, nm_i); 953 954 __builtin_prefetch(&ring->slot[nm_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 957 958 for (n = 0; nm_i != head; n++) { 959 struct netmap_slot *slot = &ring->slot[nm_i]; 960 u_int len = slot->len; 961 uint64_t paddr; 962 void *addr = PNMB(na, slot, &paddr); 963 int flags = (slot->flags & NS_REPORT || 964 nic_i == 0 || nic_i == report_frequency) ? 965 IPI_TX_INTR : 0; 966 967 /* device-specific */ 968 pi.ipi_len = len; 969 pi.ipi_segs[0].ds_addr = paddr; 970 pi.ipi_segs[0].ds_len = len; 971 pi.ipi_nsegs = 1; 972 pi.ipi_ndescs = 0; 973 pi.ipi_pidx = nic_i; 974 pi.ipi_flags = flags; 975 976 /* Fill the slot in the NIC ring. */ 977 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 978 DBG_COUNTER_INC(tx_encap); 979 980 /* prefetch for next round */ 981 __builtin_prefetch(&ring->slot[nm_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 984 985 NM_CHECK_ADDR_LEN(na, addr, len); 986 987 if (slot->flags & NS_BUF_CHANGED) { 988 /* buffer has changed, reload map */ 989 netmap_reload_map(na, txq->ift_buf_tag, 990 txq->ift_sds.ifsd_map[nic_i], addr); 991 } 992 /* make sure changes to the buffer are synced */ 993 bus_dmamap_sync(txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], 995 BUS_DMASYNC_PREWRITE); 996 997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 kring->nr_hwcur = nm_i; 1002 1003 /* synchronize the NIC ring */ 1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 /* (re)start the tx unit up to slot nic_i (excluded) */ 1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1009 } 1010 1011 /* 1012 * Second part: reclaim buffers for completed transmissions. 1013 * 1014 * If there are unclaimed buffers, attempt to reclaim them. 1015 * If none are reclaimed, and TX IRQs are not in use, do an initial 1016 * minimal delay, then trigger the tx handler which will spin in the 1017 * group task queue. 1018 */ 1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1020 if (iflib_tx_credits_update(ctx, txq)) { 1021 /* some tx completed, increment avail */ 1022 nic_i = txq->ift_cidx_processed; 1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1024 } 1025 } 1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1029 iflib_timer, txq, txq->ift_timer.c_cpu); 1030 } 1031 return (0); 1032 } 1033 1034 /* 1035 * Reconcile kernel and user view of the receive ring. 1036 * Same as for the txsync, this routine must be efficient. 1037 * The caller guarantees a single invocations, but races against 1038 * the rest of the driver should be handled here. 1039 * 1040 * On call, kring->rhead is the first packet that userspace wants 1041 * to keep, and kring->rcur is the wakeup point. 1042 * The kernel has previously reported packets up to kring->rtail. 1043 * 1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1045 * of whether or not we received an interrupt. 1046 */ 1047 static int 1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1049 { 1050 struct netmap_adapter *na = kring->na; 1051 struct netmap_ring *ring = kring->ring; 1052 if_t ifp = na->ifp; 1053 iflib_fl_t fl; 1054 uint32_t nm_i; /* index into the netmap ring */ 1055 uint32_t nic_i; /* index into the NIC ring */ 1056 u_int i, n; 1057 u_int const lim = kring->nkr_num_slots - 1; 1058 u_int const head = kring->rhead; 1059 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1060 struct if_rxd_info ri; 1061 1062 if_ctx_t ctx = ifp->if_softc; 1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1064 if (head > lim) 1065 return netmap_ring_reinit(kring); 1066 1067 /* 1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1069 */ 1070 1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1074 } 1075 1076 /* 1077 * First part: import newly received packets. 1078 * 1079 * nm_i is the index of the next free slot in the netmap ring, 1080 * nic_i is the index of the next received packet in the NIC ring, 1081 * and they may differ in case if_init() has been called while 1082 * in netmap mode. For the receive ring we have 1083 * 1084 * nic_i = rxr->next_check; 1085 * nm_i = kring->nr_hwtail (previous) 1086 * and 1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1088 * 1089 * rxr->next_check is set to 0 on a ring reinit 1090 */ 1091 if (netmap_no_pendintr || force_update) { 1092 int crclen = iflib_crcstrip ? 0 : 4; 1093 int error, avail; 1094 1095 for (i = 0; i < rxq->ifr_nfl; i++) { 1096 fl = &rxq->ifr_fl[i]; 1097 nic_i = fl->ifl_cidx; 1098 nm_i = netmap_idx_n2k(kring, nic_i); 1099 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1100 rxq->ifr_id, nic_i, USHRT_MAX); 1101 for (n = 0; avail > 0; n++, avail--) { 1102 rxd_info_zero(&ri); 1103 ri.iri_frags = rxq->ifr_frags; 1104 ri.iri_qsidx = kring->ring_id; 1105 ri.iri_ifp = ctx->ifc_ifp; 1106 ri.iri_cidx = nic_i; 1107 1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1110 ring->slot[nm_i].flags = 0; 1111 bus_dmamap_sync(fl->ifl_buf_tag, 1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1113 nm_i = nm_next(nm_i, lim); 1114 nic_i = nm_next(nic_i, lim); 1115 } 1116 if (n) { /* update the state variables */ 1117 if (netmap_no_pendintr && !force_update) { 1118 /* diagnostics */ 1119 iflib_rx_miss ++; 1120 iflib_rx_miss_bufs += n; 1121 } 1122 fl->ifl_cidx = nic_i; 1123 kring->nr_hwtail = nm_i; 1124 } 1125 kring->nr_kflags &= ~NKR_PENDINTR; 1126 } 1127 } 1128 /* 1129 * Second part: skip past packets that userspace has released. 1130 * (kring->nr_hwcur to head excluded), 1131 * and make the buffers available for reception. 1132 * As usual nm_i is the index in the netmap ring, 1133 * nic_i is the index in the NIC ring, and 1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1135 */ 1136 /* XXX not sure how this will work with multiple free lists */ 1137 nm_i = kring->nr_hwcur; 1138 1139 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1140 } 1141 1142 static void 1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1144 { 1145 if_ctx_t ctx = na->ifp->if_softc; 1146 1147 CTX_LOCK(ctx); 1148 if (onoff) { 1149 IFDI_INTR_ENABLE(ctx); 1150 } else { 1151 IFDI_INTR_DISABLE(ctx); 1152 } 1153 CTX_UNLOCK(ctx); 1154 } 1155 1156 1157 static int 1158 iflib_netmap_attach(if_ctx_t ctx) 1159 { 1160 struct netmap_adapter na; 1161 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1162 1163 bzero(&na, sizeof(na)); 1164 1165 na.ifp = ctx->ifc_ifp; 1166 na.na_flags = NAF_BDG_MAYSLEEP; 1167 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1168 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1169 1170 na.num_tx_desc = scctx->isc_ntxd[0]; 1171 na.num_rx_desc = scctx->isc_nrxd[0]; 1172 na.nm_txsync = iflib_netmap_txsync; 1173 na.nm_rxsync = iflib_netmap_rxsync; 1174 na.nm_register = iflib_netmap_register; 1175 na.nm_intr = iflib_netmap_intr; 1176 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1177 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1178 return (netmap_attach(&na)); 1179 } 1180 1181 static void 1182 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1183 { 1184 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1185 struct netmap_slot *slot; 1186 1187 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1188 if (slot == NULL) 1189 return; 1190 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1191 1192 /* 1193 * In netmap mode, set the map for the packet buffer. 1194 * NOTE: Some drivers (not this one) also need to set 1195 * the physical buffer address in the NIC ring. 1196 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1197 * netmap slot index, si 1198 */ 1199 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1200 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1201 NMB(na, slot + si)); 1202 } 1203 } 1204 1205 static void 1206 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1207 { 1208 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1209 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1210 struct netmap_slot *slot; 1211 uint32_t nm_i; 1212 1213 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1214 if (slot == NULL) 1215 return; 1216 nm_i = netmap_idx_n2k(kring, 0); 1217 netmap_fl_refill(rxq, kring, nm_i, true); 1218 } 1219 1220 static void 1221 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1222 { 1223 struct netmap_kring *kring; 1224 uint16_t txqid; 1225 1226 txqid = txq->ift_id; 1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1228 1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1230 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1231 BUS_DMASYNC_POSTREAD); 1232 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1233 netmap_tx_irq(ctx->ifc_ifp, txqid); 1234 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1235 if (hz < 2000) 1236 *reset_on = 1; 1237 else 1238 *reset_on = hz / 1000; 1239 } 1240 } 1241 } 1242 1243 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1244 1245 #else 1246 #define iflib_netmap_txq_init(ctx, txq) 1247 #define iflib_netmap_rxq_init(ctx, rxq) 1248 #define iflib_netmap_detach(ifp) 1249 1250 #define iflib_netmap_attach(ctx) (0) 1251 #define netmap_rx_irq(ifp, qid, budget) (0) 1252 #define netmap_tx_irq(ifp, qid) do {} while (0) 1253 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1277 { 1278 iflib_fl_t fl; 1279 1280 fl = &rxq->ifr_fl[flid]; 1281 iru->iru_paddrs = fl->ifl_bus_addrs; 1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1283 iru->iru_idxs = fl->ifl_rxd_idxs; 1284 iru->iru_qsidx = rxq->ifr_id; 1285 iru->iru_buf_size = fl->ifl_buf_size; 1286 iru->iru_flidx = fl->ifl_id; 1287 } 1288 1289 static void 1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1291 { 1292 if (err) 1293 return; 1294 *(bus_addr_t *) arg = segs[0].ds_addr; 1295 } 1296 1297 int 1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1299 { 1300 int err; 1301 device_t dev = ctx->ifc_dev; 1302 1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1304 align, 0, /* alignment, bounds */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 size, /* maxsize */ 1309 1, /* nsegments */ 1310 size, /* maxsegsize */ 1311 BUS_DMA_ALLOCNOW, /* flags */ 1312 NULL, /* lockfunc */ 1313 NULL, /* lockarg */ 1314 &dma->idi_tag); 1315 if (err) { 1316 device_printf(dev, 1317 "%s: bus_dma_tag_create failed: %d\n", 1318 __func__, err); 1319 goto fail_0; 1320 } 1321 1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1324 if (err) { 1325 device_printf(dev, 1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1327 __func__, (uintmax_t)size, err); 1328 goto fail_1; 1329 } 1330 1331 dma->idi_paddr = IF_BAD_DMA; 1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1334 if (err || dma->idi_paddr == IF_BAD_DMA) { 1335 device_printf(dev, 1336 "%s: bus_dmamap_load failed: %d\n", 1337 __func__, err); 1338 goto fail_2; 1339 } 1340 1341 dma->idi_size = size; 1342 return (0); 1343 1344 fail_2: 1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1346 fail_1: 1347 bus_dma_tag_destroy(dma->idi_tag); 1348 fail_0: 1349 dma->idi_tag = NULL; 1350 1351 return (err); 1352 } 1353 1354 int 1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1356 { 1357 if_shared_ctx_t sctx = ctx->ifc_sctx; 1358 1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1360 1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1362 } 1363 1364 int 1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1366 { 1367 int i, err; 1368 iflib_dma_info_t *dmaiter; 1369 1370 dmaiter = dmalist; 1371 for (i = 0; i < count; i++, dmaiter++) { 1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1373 break; 1374 } 1375 if (err) 1376 iflib_dma_free_multi(dmalist, i); 1377 return (err); 1378 } 1379 1380 void 1381 iflib_dma_free(iflib_dma_info_t dma) 1382 { 1383 if (dma->idi_tag == NULL) 1384 return; 1385 if (dma->idi_paddr != IF_BAD_DMA) { 1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1389 dma->idi_paddr = IF_BAD_DMA; 1390 } 1391 if (dma->idi_vaddr != NULL) { 1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1393 dma->idi_vaddr = NULL; 1394 } 1395 bus_dma_tag_destroy(dma->idi_tag); 1396 dma->idi_tag = NULL; 1397 } 1398 1399 void 1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1401 { 1402 int i; 1403 iflib_dma_info_t *dmaiter = dmalist; 1404 1405 for (i = 0; i < count; i++, dmaiter++) 1406 iflib_dma_free(*dmaiter); 1407 } 1408 1409 #ifdef EARLY_AP_STARTUP 1410 static const int iflib_started = 1; 1411 #else 1412 /* 1413 * We used to abuse the smp_started flag to decide if the queues have been 1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1416 * is set. Run a SYSINIT() strictly after that to just set a usable 1417 * completion flag. 1418 */ 1419 1420 static int iflib_started; 1421 1422 static void 1423 iflib_record_started(void *arg) 1424 { 1425 iflib_started = 1; 1426 } 1427 1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1429 iflib_record_started, NULL); 1430 #endif 1431 1432 static int 1433 iflib_fast_intr(void *arg) 1434 { 1435 iflib_filter_info_t info = arg; 1436 struct grouptask *gtask = info->ifi_task; 1437 int result; 1438 1439 if (!iflib_started) 1440 return (FILTER_STRAY); 1441 1442 DBG_COUNTER_INC(fast_intrs); 1443 if (info->ifi_filter != NULL) { 1444 result = info->ifi_filter(info->ifi_filter_arg); 1445 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1446 return (result); 1447 } 1448 1449 GROUPTASK_ENQUEUE(gtask); 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static int 1454 iflib_fast_intr_rxtx(void *arg) 1455 { 1456 iflib_filter_info_t info = arg; 1457 struct grouptask *gtask = info->ifi_task; 1458 if_ctx_t ctx; 1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1460 iflib_txq_t txq; 1461 void *sc; 1462 int i, cidx, result; 1463 qidx_t txqid; 1464 bool intr_enable, intr_legacy; 1465 1466 if (!iflib_started) 1467 return (FILTER_STRAY); 1468 1469 DBG_COUNTER_INC(fast_intrs); 1470 if (info->ifi_filter != NULL) { 1471 result = info->ifi_filter(info->ifi_filter_arg); 1472 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1473 return (result); 1474 } 1475 1476 ctx = rxq->ifr_ctx; 1477 sc = ctx->ifc_softc; 1478 intr_enable = false; 1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1480 MPASS(rxq->ifr_ntxqirq); 1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1482 txqid = rxq->ifr_txqid[i]; 1483 txq = &ctx->ifc_txqs[txqid]; 1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1485 BUS_DMASYNC_POSTREAD); 1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1487 if (intr_legacy) 1488 intr_enable = true; 1489 else 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&txq->ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else { 1502 if (intr_legacy) 1503 intr_enable = true; 1504 else 1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1506 DBG_COUNTER_INC(rx_intr_enables); 1507 } 1508 if (intr_enable) 1509 IFDI_INTR_ENABLE(ctx); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 1514 static int 1515 iflib_fast_intr_ctx(void *arg) 1516 { 1517 iflib_filter_info_t info = arg; 1518 struct grouptask *gtask = info->ifi_task; 1519 int result; 1520 1521 if (!iflib_started) 1522 return (FILTER_STRAY); 1523 1524 DBG_COUNTER_INC(fast_intrs); 1525 if (info->ifi_filter != NULL) { 1526 result = info->ifi_filter(info->ifi_filter_arg); 1527 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1528 return (result); 1529 } 1530 1531 GROUPTASK_ENQUEUE(gtask); 1532 return (FILTER_HANDLED); 1533 } 1534 1535 static int 1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1537 driver_filter_t filter, driver_intr_t handler, void *arg, 1538 const char *name) 1539 { 1540 struct resource *res; 1541 void *tag = NULL; 1542 device_t dev = ctx->ifc_dev; 1543 int flags, i, rc; 1544 1545 flags = RF_ACTIVE; 1546 if (ctx->ifc_flags & IFC_LEGACY) 1547 flags |= RF_SHAREABLE; 1548 MPASS(rid < 512); 1549 i = rid; 1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1551 if (res == NULL) { 1552 device_printf(dev, 1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1554 return (ENOMEM); 1555 } 1556 irq->ii_res = res; 1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1559 filter, handler, arg, &tag); 1560 if (rc != 0) { 1561 device_printf(dev, 1562 "failed to setup interrupt for rid %d, name %s: %d\n", 1563 rid, name ? name : "unknown", rc); 1564 return (rc); 1565 } else if (name) 1566 bus_describe_intr(dev, res, tag, "%s", name); 1567 1568 irq->ii_tag = tag; 1569 return (0); 1570 } 1571 1572 /********************************************************************* 1573 * 1574 * Allocate DMA resources for TX buffers as well as memory for the TX 1575 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1576 * iflib_sw_tx_desc_array structure, storing all the information that 1577 * is needed to transmit a packet on the wire. This is called only 1578 * once at attach, setup is done every reset. 1579 * 1580 **********************************************************************/ 1581 static int 1582 iflib_txsd_alloc(iflib_txq_t txq) 1583 { 1584 if_ctx_t ctx = txq->ift_ctx; 1585 if_shared_ctx_t sctx = ctx->ifc_sctx; 1586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1587 device_t dev = ctx->ifc_dev; 1588 bus_size_t tsomaxsize; 1589 int err, nsegments, ntsosegments; 1590 bool tso; 1591 1592 nsegments = scctx->isc_tx_nsegments; 1593 ntsosegments = scctx->isc_tx_tso_segments_max; 1594 tsomaxsize = scctx->isc_tx_tso_size_max; 1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1596 tsomaxsize += sizeof(struct ether_vlan_header); 1597 MPASS(scctx->isc_ntxd[0] > 0); 1598 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1599 MPASS(nsegments > 0); 1600 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1601 MPASS(ntsosegments > 0); 1602 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1603 } 1604 1605 /* 1606 * Set up DMA tags for TX buffers. 1607 */ 1608 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1609 1, 0, /* alignment, bounds */ 1610 BUS_SPACE_MAXADDR, /* lowaddr */ 1611 BUS_SPACE_MAXADDR, /* highaddr */ 1612 NULL, NULL, /* filter, filterarg */ 1613 sctx->isc_tx_maxsize, /* maxsize */ 1614 nsegments, /* nsegments */ 1615 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1616 0, /* flags */ 1617 NULL, /* lockfunc */ 1618 NULL, /* lockfuncarg */ 1619 &txq->ift_buf_tag))) { 1620 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1621 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1622 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1623 goto fail; 1624 } 1625 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1626 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1627 1, 0, /* alignment, bounds */ 1628 BUS_SPACE_MAXADDR, /* lowaddr */ 1629 BUS_SPACE_MAXADDR, /* highaddr */ 1630 NULL, NULL, /* filter, filterarg */ 1631 tsomaxsize, /* maxsize */ 1632 ntsosegments, /* nsegments */ 1633 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1634 0, /* flags */ 1635 NULL, /* lockfunc */ 1636 NULL, /* lockfuncarg */ 1637 &txq->ift_tso_buf_tag))) { 1638 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1639 err); 1640 goto fail; 1641 } 1642 1643 /* Allocate memory for the TX mbuf map. */ 1644 if (!(txq->ift_sds.ifsd_m = 1645 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1646 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1647 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1648 err = ENOMEM; 1649 goto fail; 1650 } 1651 1652 /* 1653 * Create the DMA maps for TX buffers. 1654 */ 1655 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1656 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1657 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1658 device_printf(dev, 1659 "Unable to allocate TX buffer DMA map memory\n"); 1660 err = ENOMEM; 1661 goto fail; 1662 } 1663 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1664 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1665 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1666 device_printf(dev, 1667 "Unable to allocate TSO TX buffer map memory\n"); 1668 err = ENOMEM; 1669 goto fail; 1670 } 1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1672 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1673 &txq->ift_sds.ifsd_map[i]); 1674 if (err != 0) { 1675 device_printf(dev, "Unable to create TX DMA map\n"); 1676 goto fail; 1677 } 1678 if (!tso) 1679 continue; 1680 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1681 &txq->ift_sds.ifsd_tso_map[i]); 1682 if (err != 0) { 1683 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1684 goto fail; 1685 } 1686 } 1687 return (0); 1688 fail: 1689 /* We free all, it handles case where we are in the middle */ 1690 iflib_tx_structures_free(ctx); 1691 return (err); 1692 } 1693 1694 static void 1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1696 { 1697 bus_dmamap_t map; 1698 1699 map = NULL; 1700 if (txq->ift_sds.ifsd_map != NULL) 1701 map = txq->ift_sds.ifsd_map[i]; 1702 if (map != NULL) { 1703 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1704 bus_dmamap_unload(txq->ift_buf_tag, map); 1705 bus_dmamap_destroy(txq->ift_buf_tag, map); 1706 txq->ift_sds.ifsd_map[i] = NULL; 1707 } 1708 1709 map = NULL; 1710 if (txq->ift_sds.ifsd_tso_map != NULL) 1711 map = txq->ift_sds.ifsd_tso_map[i]; 1712 if (map != NULL) { 1713 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1716 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1717 txq->ift_sds.ifsd_tso_map[i] = NULL; 1718 } 1719 } 1720 1721 static void 1722 iflib_txq_destroy(iflib_txq_t txq) 1723 { 1724 if_ctx_t ctx = txq->ift_ctx; 1725 1726 for (int i = 0; i < txq->ift_size; i++) 1727 iflib_txsd_destroy(ctx, txq, i); 1728 if (txq->ift_sds.ifsd_map != NULL) { 1729 free(txq->ift_sds.ifsd_map, M_IFLIB); 1730 txq->ift_sds.ifsd_map = NULL; 1731 } 1732 if (txq->ift_sds.ifsd_tso_map != NULL) { 1733 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1734 txq->ift_sds.ifsd_tso_map = NULL; 1735 } 1736 if (txq->ift_sds.ifsd_m != NULL) { 1737 free(txq->ift_sds.ifsd_m, M_IFLIB); 1738 txq->ift_sds.ifsd_m = NULL; 1739 } 1740 if (txq->ift_buf_tag != NULL) { 1741 bus_dma_tag_destroy(txq->ift_buf_tag); 1742 txq->ift_buf_tag = NULL; 1743 } 1744 if (txq->ift_tso_buf_tag != NULL) { 1745 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1746 txq->ift_tso_buf_tag = NULL; 1747 } 1748 } 1749 1750 static void 1751 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1752 { 1753 struct mbuf **mp; 1754 1755 mp = &txq->ift_sds.ifsd_m[i]; 1756 if (*mp == NULL) 1757 return; 1758 1759 if (txq->ift_sds.ifsd_map != NULL) { 1760 bus_dmamap_sync(txq->ift_buf_tag, 1761 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1762 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1763 } 1764 if (txq->ift_sds.ifsd_tso_map != NULL) { 1765 bus_dmamap_sync(txq->ift_tso_buf_tag, 1766 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1767 bus_dmamap_unload(txq->ift_tso_buf_tag, 1768 txq->ift_sds.ifsd_tso_map[i]); 1769 } 1770 m_free(*mp); 1771 DBG_COUNTER_INC(tx_frees); 1772 *mp = NULL; 1773 } 1774 1775 static int 1776 iflib_txq_setup(iflib_txq_t txq) 1777 { 1778 if_ctx_t ctx = txq->ift_ctx; 1779 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1780 if_shared_ctx_t sctx = ctx->ifc_sctx; 1781 iflib_dma_info_t di; 1782 int i; 1783 1784 /* Set number of descriptors available */ 1785 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1786 /* XXX make configurable */ 1787 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1788 1789 /* Reset indices */ 1790 txq->ift_cidx_processed = 0; 1791 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1792 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1793 1794 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1795 bzero((void *)di->idi_vaddr, di->idi_size); 1796 1797 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1798 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1799 bus_dmamap_sync(di->idi_tag, di->idi_map, 1800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1801 return (0); 1802 } 1803 1804 /********************************************************************* 1805 * 1806 * Allocate DMA resources for RX buffers as well as memory for the RX 1807 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1808 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1809 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1810 * Since we use use one entry in iflib_sw_rx_desc_array per received 1811 * packet, the maximum number of entries we'll need is equal to the 1812 * number of hardware receive descriptors that we've allocated. 1813 * 1814 **********************************************************************/ 1815 static int 1816 iflib_rxsd_alloc(iflib_rxq_t rxq) 1817 { 1818 if_ctx_t ctx = rxq->ifr_ctx; 1819 if_shared_ctx_t sctx = ctx->ifc_sctx; 1820 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1821 device_t dev = ctx->ifc_dev; 1822 iflib_fl_t fl; 1823 int err; 1824 1825 MPASS(scctx->isc_nrxd[0] > 0); 1826 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1827 1828 fl = rxq->ifr_fl; 1829 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1830 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1831 /* Set up DMA tag for RX buffers. */ 1832 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1833 1, 0, /* alignment, bounds */ 1834 BUS_SPACE_MAXADDR, /* lowaddr */ 1835 BUS_SPACE_MAXADDR, /* highaddr */ 1836 NULL, NULL, /* filter, filterarg */ 1837 sctx->isc_rx_maxsize, /* maxsize */ 1838 sctx->isc_rx_nsegments, /* nsegments */ 1839 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1840 0, /* flags */ 1841 NULL, /* lockfunc */ 1842 NULL, /* lockarg */ 1843 &fl->ifl_buf_tag); 1844 if (err) { 1845 device_printf(dev, 1846 "Unable to allocate RX DMA tag: %d\n", err); 1847 goto fail; 1848 } 1849 1850 /* Allocate memory for the RX mbuf map. */ 1851 if (!(fl->ifl_sds.ifsd_m = 1852 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1853 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1854 device_printf(dev, 1855 "Unable to allocate RX mbuf map memory\n"); 1856 err = ENOMEM; 1857 goto fail; 1858 } 1859 1860 /* Allocate memory for the direct RX cluster pointer map. */ 1861 if (!(fl->ifl_sds.ifsd_cl = 1862 (caddr_t *) malloc(sizeof(caddr_t) * 1863 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1864 device_printf(dev, 1865 "Unable to allocate RX cluster map memory\n"); 1866 err = ENOMEM; 1867 goto fail; 1868 } 1869 1870 /* Allocate memory for the RX cluster bus address map. */ 1871 if (!(fl->ifl_sds.ifsd_ba = 1872 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1873 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1874 device_printf(dev, 1875 "Unable to allocate RX bus address map memory\n"); 1876 err = ENOMEM; 1877 goto fail; 1878 } 1879 1880 /* 1881 * Create the DMA maps for RX buffers. 1882 */ 1883 if (!(fl->ifl_sds.ifsd_map = 1884 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1885 device_printf(dev, 1886 "Unable to allocate RX buffer DMA map memory\n"); 1887 err = ENOMEM; 1888 goto fail; 1889 } 1890 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1891 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1892 &fl->ifl_sds.ifsd_map[i]); 1893 if (err != 0) { 1894 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1895 goto fail; 1896 } 1897 } 1898 } 1899 return (0); 1900 1901 fail: 1902 iflib_rx_structures_free(ctx); 1903 return (err); 1904 } 1905 1906 1907 /* 1908 * Internal service routines 1909 */ 1910 1911 struct rxq_refill_cb_arg { 1912 int error; 1913 bus_dma_segment_t seg; 1914 int nseg; 1915 }; 1916 1917 static void 1918 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1919 { 1920 struct rxq_refill_cb_arg *cb_arg = arg; 1921 1922 cb_arg->error = error; 1923 cb_arg->seg = segs[0]; 1924 cb_arg->nseg = nseg; 1925 } 1926 1927 /** 1928 * _iflib_fl_refill - refill an rxq free-buffer list 1929 * @ctx: the iflib context 1930 * @fl: the free list to refill 1931 * @count: the number of new buffers to allocate 1932 * 1933 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1934 * The caller must assure that @count does not exceed the queue's capacity. 1935 */ 1936 static void 1937 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1938 { 1939 struct if_rxd_update iru; 1940 struct rxq_refill_cb_arg cb_arg; 1941 struct mbuf *m; 1942 caddr_t cl, *sd_cl; 1943 struct mbuf **sd_m; 1944 bus_dmamap_t *sd_map; 1945 bus_addr_t bus_addr, *sd_ba; 1946 int err, frag_idx, i, idx, n, pidx; 1947 qidx_t credits; 1948 1949 sd_m = fl->ifl_sds.ifsd_m; 1950 sd_map = fl->ifl_sds.ifsd_map; 1951 sd_cl = fl->ifl_sds.ifsd_cl; 1952 sd_ba = fl->ifl_sds.ifsd_ba; 1953 pidx = fl->ifl_pidx; 1954 idx = pidx; 1955 frag_idx = fl->ifl_fragidx; 1956 credits = fl->ifl_credits; 1957 1958 i = 0; 1959 n = count; 1960 MPASS(n > 0); 1961 MPASS(credits + n <= fl->ifl_size); 1962 1963 if (pidx < fl->ifl_cidx) 1964 MPASS(pidx + n <= fl->ifl_cidx); 1965 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1966 MPASS(fl->ifl_gen == 0); 1967 if (pidx > fl->ifl_cidx) 1968 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1969 1970 DBG_COUNTER_INC(fl_refills); 1971 if (n > 8) 1972 DBG_COUNTER_INC(fl_refills_large); 1973 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1974 while (n--) { 1975 /* 1976 * We allocate an uninitialized mbuf + cluster, mbuf is 1977 * initialized after rx. 1978 * 1979 * If the cluster is still set then we know a minimum sized packet was received 1980 */ 1981 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1982 &frag_idx); 1983 if (frag_idx < 0) 1984 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1985 MPASS(frag_idx >= 0); 1986 if ((cl = sd_cl[frag_idx]) == NULL) { 1987 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1988 break; 1989 1990 cb_arg.error = 0; 1991 MPASS(sd_map != NULL); 1992 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1993 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1994 BUS_DMA_NOWAIT); 1995 if (err != 0 || cb_arg.error) { 1996 /* 1997 * !zone_pack ? 1998 */ 1999 if (fl->ifl_zone == zone_pack) 2000 uma_zfree(fl->ifl_zone, cl); 2001 break; 2002 } 2003 2004 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2005 sd_cl[frag_idx] = cl; 2006 #if MEMORY_LOGGING 2007 fl->ifl_cl_enqueued++; 2008 #endif 2009 } else { 2010 bus_addr = sd_ba[frag_idx]; 2011 } 2012 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2013 BUS_DMASYNC_PREREAD); 2014 2015 if (sd_m[frag_idx] == NULL) { 2016 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2017 break; 2018 } 2019 sd_m[frag_idx] = m; 2020 } 2021 bit_set(fl->ifl_rx_bitmap, frag_idx); 2022 #if MEMORY_LOGGING 2023 fl->ifl_m_enqueued++; 2024 #endif 2025 2026 DBG_COUNTER_INC(rx_allocs); 2027 fl->ifl_rxd_idxs[i] = frag_idx; 2028 fl->ifl_bus_addrs[i] = bus_addr; 2029 fl->ifl_vm_addrs[i] = cl; 2030 credits++; 2031 i++; 2032 MPASS(credits <= fl->ifl_size); 2033 if (++idx == fl->ifl_size) { 2034 fl->ifl_gen = 1; 2035 idx = 0; 2036 } 2037 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2038 iru.iru_pidx = pidx; 2039 iru.iru_count = i; 2040 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2041 i = 0; 2042 pidx = idx; 2043 fl->ifl_pidx = idx; 2044 fl->ifl_credits = credits; 2045 } 2046 } 2047 2048 if (i) { 2049 iru.iru_pidx = pidx; 2050 iru.iru_count = i; 2051 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2052 fl->ifl_pidx = idx; 2053 fl->ifl_credits = credits; 2054 } 2055 DBG_COUNTER_INC(rxd_flush); 2056 if (fl->ifl_pidx == 0) 2057 pidx = fl->ifl_size - 1; 2058 else 2059 pidx = fl->ifl_pidx - 1; 2060 2061 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2062 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2063 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2064 fl->ifl_fragidx = frag_idx; 2065 } 2066 2067 static __inline void 2068 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2069 { 2070 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2071 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2072 #ifdef INVARIANTS 2073 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2074 #endif 2075 2076 MPASS(fl->ifl_credits <= fl->ifl_size); 2077 MPASS(reclaimable == delta); 2078 2079 if (reclaimable > 0) 2080 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2081 } 2082 2083 uint8_t 2084 iflib_in_detach(if_ctx_t ctx) 2085 { 2086 bool in_detach; 2087 2088 STATE_LOCK(ctx); 2089 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2090 STATE_UNLOCK(ctx); 2091 return (in_detach); 2092 } 2093 2094 static void 2095 iflib_fl_bufs_free(iflib_fl_t fl) 2096 { 2097 iflib_dma_info_t idi = fl->ifl_ifdi; 2098 bus_dmamap_t sd_map; 2099 uint32_t i; 2100 2101 for (i = 0; i < fl->ifl_size; i++) { 2102 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2103 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2104 2105 if (*sd_cl != NULL) { 2106 sd_map = fl->ifl_sds.ifsd_map[i]; 2107 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2108 BUS_DMASYNC_POSTREAD); 2109 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2110 if (*sd_cl != NULL) 2111 uma_zfree(fl->ifl_zone, *sd_cl); 2112 // XXX: Should this get moved out? 2113 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2114 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2115 if (*sd_m != NULL) { 2116 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2117 uma_zfree(zone_mbuf, *sd_m); 2118 } 2119 } else { 2120 MPASS(*sd_cl == NULL); 2121 MPASS(*sd_m == NULL); 2122 } 2123 #if MEMORY_LOGGING 2124 fl->ifl_m_dequeued++; 2125 fl->ifl_cl_dequeued++; 2126 #endif 2127 *sd_cl = NULL; 2128 *sd_m = NULL; 2129 } 2130 #ifdef INVARIANTS 2131 for (i = 0; i < fl->ifl_size; i++) { 2132 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2133 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2134 } 2135 #endif 2136 /* 2137 * Reset free list values 2138 */ 2139 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2140 bzero(idi->idi_vaddr, idi->idi_size); 2141 } 2142 2143 /********************************************************************* 2144 * 2145 * Initialize a free list and its buffers. 2146 * 2147 **********************************************************************/ 2148 static int 2149 iflib_fl_setup(iflib_fl_t fl) 2150 { 2151 iflib_rxq_t rxq = fl->ifl_rxq; 2152 if_ctx_t ctx = rxq->ifr_ctx; 2153 2154 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2155 /* 2156 ** Free current RX buffer structs and their mbufs 2157 */ 2158 iflib_fl_bufs_free(fl); 2159 /* Now replenish the mbufs */ 2160 MPASS(fl->ifl_credits == 0); 2161 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2162 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2163 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2164 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2165 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2166 2167 2168 /* avoid pre-allocating zillions of clusters to an idle card 2169 * potentially speeding up attach 2170 */ 2171 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2172 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2173 if (min(128, fl->ifl_size) != fl->ifl_credits) 2174 return (ENOBUFS); 2175 /* 2176 * handle failure 2177 */ 2178 MPASS(rxq != NULL); 2179 MPASS(fl->ifl_ifdi != NULL); 2180 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2181 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2182 return (0); 2183 } 2184 2185 /********************************************************************* 2186 * 2187 * Free receive ring data structures 2188 * 2189 **********************************************************************/ 2190 static void 2191 iflib_rx_sds_free(iflib_rxq_t rxq) 2192 { 2193 iflib_fl_t fl; 2194 int i, j; 2195 2196 if (rxq->ifr_fl != NULL) { 2197 for (i = 0; i < rxq->ifr_nfl; i++) { 2198 fl = &rxq->ifr_fl[i]; 2199 if (fl->ifl_buf_tag != NULL) { 2200 if (fl->ifl_sds.ifsd_map != NULL) { 2201 for (j = 0; j < fl->ifl_size; j++) { 2202 if (fl->ifl_sds.ifsd_map[j] == 2203 NULL) 2204 continue; 2205 bus_dmamap_sync( 2206 fl->ifl_buf_tag, 2207 fl->ifl_sds.ifsd_map[j], 2208 BUS_DMASYNC_POSTREAD); 2209 bus_dmamap_unload( 2210 fl->ifl_buf_tag, 2211 fl->ifl_sds.ifsd_map[j]); 2212 } 2213 } 2214 bus_dma_tag_destroy(fl->ifl_buf_tag); 2215 fl->ifl_buf_tag = NULL; 2216 } 2217 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2219 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2220 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2221 fl->ifl_sds.ifsd_m = NULL; 2222 fl->ifl_sds.ifsd_cl = NULL; 2223 fl->ifl_sds.ifsd_ba = NULL; 2224 fl->ifl_sds.ifsd_map = NULL; 2225 } 2226 free(rxq->ifr_fl, M_IFLIB); 2227 rxq->ifr_fl = NULL; 2228 rxq->ifr_cq_cidx = 0; 2229 } 2230 } 2231 2232 /* 2233 * Timer routine 2234 */ 2235 static void 2236 iflib_timer(void *arg) 2237 { 2238 iflib_txq_t txq = arg; 2239 if_ctx_t ctx = txq->ift_ctx; 2240 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2241 uint64_t this_tick = ticks; 2242 uint32_t reset_on = hz / 2; 2243 2244 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2245 return; 2246 2247 /* 2248 ** Check on the state of the TX queue(s), this 2249 ** can be done without the lock because its RO 2250 ** and the HUNG state will be static if set. 2251 */ 2252 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2253 txq->ift_last_timer_tick = this_tick; 2254 IFDI_TIMER(ctx, txq->ift_id); 2255 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2256 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2257 (sctx->isc_pause_frames == 0))) 2258 goto hung; 2259 2260 if (ifmp_ring_is_stalled(txq->ift_br)) 2261 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2262 txq->ift_cleaned_prev = txq->ift_cleaned; 2263 } 2264 #ifdef DEV_NETMAP 2265 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2266 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2267 #endif 2268 /* handle any laggards */ 2269 if (txq->ift_db_pending) 2270 GROUPTASK_ENQUEUE(&txq->ift_task); 2271 2272 sctx->isc_pause_frames = 0; 2273 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2274 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2275 return; 2276 2277 hung: 2278 device_printf(ctx->ifc_dev, 2279 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2280 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2281 STATE_LOCK(ctx); 2282 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2283 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2284 iflib_admin_intr_deferred(ctx); 2285 STATE_UNLOCK(ctx); 2286 } 2287 2288 static void 2289 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2290 { 2291 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2292 2293 /* 2294 * XXX don't set the max_frame_size to larger 2295 * than the hardware can handle 2296 */ 2297 if (sctx->isc_max_frame_size <= MCLBYTES) 2298 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2299 else 2300 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2301 } 2302 2303 uint32_t 2304 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2305 { 2306 2307 return (ctx->ifc_rx_mbuf_sz); 2308 } 2309 2310 static void 2311 iflib_init_locked(if_ctx_t ctx) 2312 { 2313 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2314 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2315 if_t ifp = ctx->ifc_ifp; 2316 iflib_fl_t fl; 2317 iflib_txq_t txq; 2318 iflib_rxq_t rxq; 2319 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2320 2321 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2322 IFDI_INTR_DISABLE(ctx); 2323 2324 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2325 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2326 /* Set hardware offload abilities */ 2327 if_clearhwassist(ifp); 2328 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2329 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2330 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2331 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2332 if (if_getcapenable(ifp) & IFCAP_TSO4) 2333 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2334 if (if_getcapenable(ifp) & IFCAP_TSO6) 2335 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2336 2337 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2338 CALLOUT_LOCK(txq); 2339 callout_stop(&txq->ift_timer); 2340 CALLOUT_UNLOCK(txq); 2341 iflib_netmap_txq_init(ctx, txq); 2342 } 2343 2344 /* 2345 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2346 * that drivers can use the value when setting up the hardware receive 2347 * buffers. 2348 */ 2349 iflib_calc_rx_mbuf_sz(ctx); 2350 2351 #ifdef INVARIANTS 2352 i = if_getdrvflags(ifp); 2353 #endif 2354 IFDI_INIT(ctx); 2355 MPASS(if_getdrvflags(ifp) == i); 2356 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2357 /* XXX this should really be done on a per-queue basis */ 2358 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2359 MPASS(rxq->ifr_id == i); 2360 iflib_netmap_rxq_init(ctx, rxq); 2361 continue; 2362 } 2363 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2364 if (iflib_fl_setup(fl)) { 2365 device_printf(ctx->ifc_dev, 2366 "setting up free list %d failed - " 2367 "check cluster settings\n", j); 2368 goto done; 2369 } 2370 } 2371 } 2372 done: 2373 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2374 IFDI_INTR_ENABLE(ctx); 2375 txq = ctx->ifc_txqs; 2376 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2377 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2378 txq->ift_timer.c_cpu); 2379 } 2380 2381 static int 2382 iflib_media_change(if_t ifp) 2383 { 2384 if_ctx_t ctx = if_getsoftc(ifp); 2385 int err; 2386 2387 CTX_LOCK(ctx); 2388 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2389 iflib_init_locked(ctx); 2390 CTX_UNLOCK(ctx); 2391 return (err); 2392 } 2393 2394 static void 2395 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2396 { 2397 if_ctx_t ctx = if_getsoftc(ifp); 2398 2399 CTX_LOCK(ctx); 2400 IFDI_UPDATE_ADMIN_STATUS(ctx); 2401 IFDI_MEDIA_STATUS(ctx, ifmr); 2402 CTX_UNLOCK(ctx); 2403 } 2404 2405 void 2406 iflib_stop(if_ctx_t ctx) 2407 { 2408 iflib_txq_t txq = ctx->ifc_txqs; 2409 iflib_rxq_t rxq = ctx->ifc_rxqs; 2410 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2411 if_shared_ctx_t sctx = ctx->ifc_sctx; 2412 iflib_dma_info_t di; 2413 iflib_fl_t fl; 2414 int i, j; 2415 2416 /* Tell the stack that the interface is no longer active */ 2417 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2418 2419 IFDI_INTR_DISABLE(ctx); 2420 DELAY(1000); 2421 IFDI_STOP(ctx); 2422 DELAY(1000); 2423 2424 iflib_debug_reset(); 2425 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2426 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2427 /* make sure all transmitters have completed before proceeding XXX */ 2428 2429 CALLOUT_LOCK(txq); 2430 callout_stop(&txq->ift_timer); 2431 CALLOUT_UNLOCK(txq); 2432 2433 /* clean any enqueued buffers */ 2434 iflib_ifmp_purge(txq); 2435 /* Free any existing tx buffers. */ 2436 for (j = 0; j < txq->ift_size; j++) { 2437 iflib_txsd_free(ctx, txq, j); 2438 } 2439 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2440 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2441 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2442 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2443 txq->ift_pullups = 0; 2444 ifmp_ring_reset_stats(txq->ift_br); 2445 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2446 bzero((void *)di->idi_vaddr, di->idi_size); 2447 } 2448 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2449 /* make sure all transmitters have completed before proceeding XXX */ 2450 2451 rxq->ifr_cq_cidx = 0; 2452 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2453 bzero((void *)di->idi_vaddr, di->idi_size); 2454 /* also resets the free lists pidx/cidx */ 2455 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2456 iflib_fl_bufs_free(fl); 2457 } 2458 } 2459 2460 static inline caddr_t 2461 calc_next_rxd(iflib_fl_t fl, int cidx) 2462 { 2463 qidx_t size; 2464 int nrxd; 2465 caddr_t start, end, cur, next; 2466 2467 nrxd = fl->ifl_size; 2468 size = fl->ifl_rxd_size; 2469 start = fl->ifl_ifdi->idi_vaddr; 2470 2471 if (__predict_false(size == 0)) 2472 return (start); 2473 cur = start + size*cidx; 2474 end = start + size*nrxd; 2475 next = CACHE_PTR_NEXT(cur); 2476 return (next < end ? next : start); 2477 } 2478 2479 static inline void 2480 prefetch_pkts(iflib_fl_t fl, int cidx) 2481 { 2482 int nextptr; 2483 int nrxd = fl->ifl_size; 2484 caddr_t next_rxd; 2485 2486 2487 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2488 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2489 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2490 next_rxd = calc_next_rxd(fl, cidx); 2491 prefetch(next_rxd); 2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2494 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2495 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2498 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2499 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2500 } 2501 2502 static struct mbuf * 2503 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2504 int *pf_rv, if_rxd_info_t ri) 2505 { 2506 bus_dmamap_t map; 2507 iflib_fl_t fl; 2508 caddr_t payload; 2509 struct mbuf *m; 2510 int flid, cidx, len, next; 2511 2512 map = NULL; 2513 flid = irf->irf_flid; 2514 cidx = irf->irf_idx; 2515 fl = &rxq->ifr_fl[flid]; 2516 sd->ifsd_fl = fl; 2517 sd->ifsd_cidx = cidx; 2518 m = fl->ifl_sds.ifsd_m[cidx]; 2519 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2520 fl->ifl_credits--; 2521 #if MEMORY_LOGGING 2522 fl->ifl_m_dequeued++; 2523 #endif 2524 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2525 prefetch_pkts(fl, cidx); 2526 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2527 prefetch(&fl->ifl_sds.ifsd_map[next]); 2528 map = fl->ifl_sds.ifsd_map[cidx]; 2529 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2530 2531 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2532 MPASS(fl->ifl_cidx == cidx); 2533 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2534 2535 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2536 payload = *sd->ifsd_cl; 2537 payload += ri->iri_pad; 2538 len = ri->iri_len - ri->iri_pad; 2539 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2540 len | PFIL_MEMPTR | PFIL_IN, NULL); 2541 switch (*pf_rv) { 2542 case PFIL_DROPPED: 2543 case PFIL_CONSUMED: 2544 /* 2545 * The filter ate it. Everything is recycled. 2546 */ 2547 m = NULL; 2548 unload = 0; 2549 break; 2550 case PFIL_REALLOCED: 2551 /* 2552 * The filter copied it. Everything is recycled. 2553 */ 2554 m = pfil_mem2mbuf(payload); 2555 unload = 0; 2556 break; 2557 case PFIL_PASS: 2558 /* 2559 * Filter said it was OK, so receive like 2560 * normal 2561 */ 2562 fl->ifl_sds.ifsd_m[cidx] = NULL; 2563 break; 2564 default: 2565 MPASS(0); 2566 } 2567 } else { 2568 fl->ifl_sds.ifsd_m[cidx] = NULL; 2569 *pf_rv = PFIL_PASS; 2570 } 2571 2572 if (unload) 2573 bus_dmamap_unload(fl->ifl_buf_tag, map); 2574 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2575 if (__predict_false(fl->ifl_cidx == 0)) 2576 fl->ifl_gen = 0; 2577 bit_clear(fl->ifl_rx_bitmap, cidx); 2578 return (m); 2579 } 2580 2581 static struct mbuf * 2582 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2583 { 2584 struct mbuf *m, *mh, *mt; 2585 caddr_t cl; 2586 int *pf_rv_ptr, flags, i, padlen; 2587 bool consumed; 2588 2589 i = 0; 2590 mh = NULL; 2591 consumed = false; 2592 *pf_rv = PFIL_PASS; 2593 pf_rv_ptr = pf_rv; 2594 do { 2595 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2596 pf_rv_ptr, ri); 2597 2598 MPASS(*sd->ifsd_cl != NULL); 2599 2600 /* 2601 * Exclude zero-length frags & frags from 2602 * packets the filter has consumed or dropped 2603 */ 2604 if (ri->iri_frags[i].irf_len == 0 || consumed || 2605 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2606 if (mh == NULL) { 2607 /* everything saved here */ 2608 consumed = true; 2609 pf_rv_ptr = NULL; 2610 continue; 2611 } 2612 /* XXX we can save the cluster here, but not the mbuf */ 2613 m_init(m, M_NOWAIT, MT_DATA, 0); 2614 m_free(m); 2615 continue; 2616 } 2617 if (mh == NULL) { 2618 flags = M_PKTHDR|M_EXT; 2619 mh = mt = m; 2620 padlen = ri->iri_pad; 2621 } else { 2622 flags = M_EXT; 2623 mt->m_next = m; 2624 mt = m; 2625 /* assuming padding is only on the first fragment */ 2626 padlen = 0; 2627 } 2628 cl = *sd->ifsd_cl; 2629 *sd->ifsd_cl = NULL; 2630 2631 /* Can these two be made one ? */ 2632 m_init(m, M_NOWAIT, MT_DATA, flags); 2633 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2634 /* 2635 * These must follow m_init and m_cljset 2636 */ 2637 m->m_data += padlen; 2638 ri->iri_len -= padlen; 2639 m->m_len = ri->iri_frags[i].irf_len; 2640 } while (++i < ri->iri_nfrags); 2641 2642 return (mh); 2643 } 2644 2645 /* 2646 * Process one software descriptor 2647 */ 2648 static struct mbuf * 2649 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2650 { 2651 struct if_rxsd sd; 2652 struct mbuf *m; 2653 int pf_rv; 2654 2655 /* should I merge this back in now that the two paths are basically duplicated? */ 2656 if (ri->iri_nfrags == 1 && 2657 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2658 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2659 &pf_rv, ri); 2660 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2661 return (m); 2662 if (pf_rv == PFIL_PASS) { 2663 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2664 #ifndef __NO_STRICT_ALIGNMENT 2665 if (!IP_ALIGNED(m)) 2666 m->m_data += 2; 2667 #endif 2668 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2669 m->m_len = ri->iri_frags[0].irf_len; 2670 } 2671 } else { 2672 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2673 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2674 return (m); 2675 } 2676 m->m_pkthdr.len = ri->iri_len; 2677 m->m_pkthdr.rcvif = ri->iri_ifp; 2678 m->m_flags |= ri->iri_flags; 2679 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2680 m->m_pkthdr.flowid = ri->iri_flowid; 2681 M_HASHTYPE_SET(m, ri->iri_rsstype); 2682 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2683 m->m_pkthdr.csum_data = ri->iri_csum_data; 2684 return (m); 2685 } 2686 2687 #if defined(INET6) || defined(INET) 2688 static void 2689 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2690 { 2691 CURVNET_SET(lc->ifp->if_vnet); 2692 #if defined(INET6) 2693 *v6 = V_ip6_forwarding; 2694 #endif 2695 #if defined(INET) 2696 *v4 = V_ipforwarding; 2697 #endif 2698 CURVNET_RESTORE(); 2699 } 2700 2701 /* 2702 * Returns true if it's possible this packet could be LROed. 2703 * if it returns false, it is guaranteed that tcp_lro_rx() 2704 * would not return zero. 2705 */ 2706 static bool 2707 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2708 { 2709 struct ether_header *eh; 2710 2711 eh = mtod(m, struct ether_header *); 2712 switch (eh->ether_type) { 2713 #if defined(INET6) 2714 case htons(ETHERTYPE_IPV6): 2715 return (!v6_forwarding); 2716 #endif 2717 #if defined (INET) 2718 case htons(ETHERTYPE_IP): 2719 return (!v4_forwarding); 2720 #endif 2721 } 2722 2723 return false; 2724 } 2725 #else 2726 static void 2727 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2728 { 2729 } 2730 #endif 2731 2732 static bool 2733 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2734 { 2735 if_t ifp; 2736 if_ctx_t ctx = rxq->ifr_ctx; 2737 if_shared_ctx_t sctx = ctx->ifc_sctx; 2738 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2739 int avail, i; 2740 qidx_t *cidxp; 2741 struct if_rxd_info ri; 2742 int err, budget_left, rx_bytes, rx_pkts; 2743 iflib_fl_t fl; 2744 int lro_enabled; 2745 bool v4_forwarding, v6_forwarding, lro_possible; 2746 2747 /* 2748 * XXX early demux data packets so that if_input processing only handles 2749 * acks in interrupt context 2750 */ 2751 struct mbuf *m, *mh, *mt, *mf; 2752 2753 lro_possible = v4_forwarding = v6_forwarding = false; 2754 ifp = ctx->ifc_ifp; 2755 mh = mt = NULL; 2756 MPASS(budget > 0); 2757 rx_pkts = rx_bytes = 0; 2758 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2759 cidxp = &rxq->ifr_cq_cidx; 2760 else 2761 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2762 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2763 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2764 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2765 DBG_COUNTER_INC(rx_unavail); 2766 return (false); 2767 } 2768 2769 /* pfil needs the vnet to be set */ 2770 CURVNET_SET_QUIET(ifp->if_vnet); 2771 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2772 if (__predict_false(!CTX_ACTIVE(ctx))) { 2773 DBG_COUNTER_INC(rx_ctx_inactive); 2774 break; 2775 } 2776 /* 2777 * Reset client set fields to their default values 2778 */ 2779 rxd_info_zero(&ri); 2780 ri.iri_qsidx = rxq->ifr_id; 2781 ri.iri_cidx = *cidxp; 2782 ri.iri_ifp = ifp; 2783 ri.iri_frags = rxq->ifr_frags; 2784 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2785 2786 if (err) 2787 goto err; 2788 rx_pkts += 1; 2789 rx_bytes += ri.iri_len; 2790 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2791 *cidxp = ri.iri_cidx; 2792 /* Update our consumer index */ 2793 /* XXX NB: shurd - check if this is still safe */ 2794 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2795 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2796 /* was this only a completion queue message? */ 2797 if (__predict_false(ri.iri_nfrags == 0)) 2798 continue; 2799 } 2800 MPASS(ri.iri_nfrags != 0); 2801 MPASS(ri.iri_len != 0); 2802 2803 /* will advance the cidx on the corresponding free lists */ 2804 m = iflib_rxd_pkt_get(rxq, &ri); 2805 avail--; 2806 budget_left--; 2807 if (avail == 0 && budget_left) 2808 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2809 2810 if (__predict_false(m == NULL)) 2811 continue; 2812 2813 /* imm_pkt: -- cxgb */ 2814 if (mh == NULL) 2815 mh = mt = m; 2816 else { 2817 mt->m_nextpkt = m; 2818 mt = m; 2819 } 2820 } 2821 CURVNET_RESTORE(); 2822 /* make sure that we can refill faster than drain */ 2823 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2824 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2825 2826 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2827 if (lro_enabled) 2828 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2829 mt = mf = NULL; 2830 while (mh != NULL) { 2831 m = mh; 2832 mh = mh->m_nextpkt; 2833 m->m_nextpkt = NULL; 2834 #ifndef __NO_STRICT_ALIGNMENT 2835 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2836 continue; 2837 #endif 2838 rx_bytes += m->m_pkthdr.len; 2839 rx_pkts++; 2840 #if defined(INET6) || defined(INET) 2841 if (lro_enabled) { 2842 if (!lro_possible) { 2843 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2844 if (lro_possible && mf != NULL) { 2845 ifp->if_input(ifp, mf); 2846 DBG_COUNTER_INC(rx_if_input); 2847 mt = mf = NULL; 2848 } 2849 } 2850 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2851 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2852 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2853 continue; 2854 } 2855 } 2856 #endif 2857 if (lro_possible) { 2858 ifp->if_input(ifp, m); 2859 DBG_COUNTER_INC(rx_if_input); 2860 continue; 2861 } 2862 2863 if (mf == NULL) 2864 mf = m; 2865 if (mt != NULL) 2866 mt->m_nextpkt = m; 2867 mt = m; 2868 } 2869 if (mf != NULL) { 2870 ifp->if_input(ifp, mf); 2871 DBG_COUNTER_INC(rx_if_input); 2872 } 2873 2874 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2875 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2876 2877 /* 2878 * Flush any outstanding LRO work 2879 */ 2880 #if defined(INET6) || defined(INET) 2881 tcp_lro_flush_all(&rxq->ifr_lc); 2882 #endif 2883 if (avail) 2884 return true; 2885 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2886 err: 2887 STATE_LOCK(ctx); 2888 ctx->ifc_flags |= IFC_DO_RESET; 2889 iflib_admin_intr_deferred(ctx); 2890 STATE_UNLOCK(ctx); 2891 return (false); 2892 } 2893 2894 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2895 static inline qidx_t 2896 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2897 { 2898 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2899 qidx_t minthresh = txq->ift_size / 8; 2900 if (in_use > 4*minthresh) 2901 return (notify_count); 2902 if (in_use > 2*minthresh) 2903 return (notify_count >> 1); 2904 if (in_use > minthresh) 2905 return (notify_count >> 3); 2906 return (0); 2907 } 2908 2909 static inline qidx_t 2910 txq_max_rs_deferred(iflib_txq_t txq) 2911 { 2912 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2913 qidx_t minthresh = txq->ift_size / 8; 2914 if (txq->ift_in_use > 4*minthresh) 2915 return (notify_count); 2916 if (txq->ift_in_use > 2*minthresh) 2917 return (notify_count >> 1); 2918 if (txq->ift_in_use > minthresh) 2919 return (notify_count >> 2); 2920 return (2); 2921 } 2922 2923 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2924 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2925 2926 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2927 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2928 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2929 2930 /* forward compatibility for cxgb */ 2931 #define FIRST_QSET(ctx) 0 2932 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2933 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2934 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2935 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2936 2937 /* XXX we should be setting this to something other than zero */ 2938 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2939 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2940 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2941 2942 static inline bool 2943 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2944 { 2945 qidx_t dbval, max; 2946 bool rang; 2947 2948 rang = false; 2949 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2950 if (ring || txq->ift_db_pending >= max) { 2951 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2952 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2954 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2955 txq->ift_db_pending = txq->ift_npending = 0; 2956 rang = true; 2957 } 2958 return (rang); 2959 } 2960 2961 #ifdef PKT_DEBUG 2962 static void 2963 print_pkt(if_pkt_info_t pi) 2964 { 2965 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2966 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2967 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2968 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2969 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2970 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2971 } 2972 #endif 2973 2974 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2975 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2976 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2977 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2978 2979 static int 2980 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2981 { 2982 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2983 struct ether_vlan_header *eh; 2984 struct mbuf *m; 2985 2986 m = *mp; 2987 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2988 M_WRITABLE(m) == 0) { 2989 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2990 return (ENOMEM); 2991 } else { 2992 m_freem(*mp); 2993 DBG_COUNTER_INC(tx_frees); 2994 *mp = m; 2995 } 2996 } 2997 2998 /* 2999 * Determine where frame payload starts. 3000 * Jump over vlan headers if already present, 3001 * helpful for QinQ too. 3002 */ 3003 if (__predict_false(m->m_len < sizeof(*eh))) { 3004 txq->ift_pullups++; 3005 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3006 return (ENOMEM); 3007 } 3008 eh = mtod(m, struct ether_vlan_header *); 3009 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3010 pi->ipi_etype = ntohs(eh->evl_proto); 3011 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3012 } else { 3013 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3014 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3015 } 3016 3017 switch (pi->ipi_etype) { 3018 #ifdef INET 3019 case ETHERTYPE_IP: 3020 { 3021 struct mbuf *n; 3022 struct ip *ip = NULL; 3023 struct tcphdr *th = NULL; 3024 int minthlen; 3025 3026 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3027 if (__predict_false(m->m_len < minthlen)) { 3028 /* 3029 * if this code bloat is causing too much of a hit 3030 * move it to a separate function and mark it noinline 3031 */ 3032 if (m->m_len == pi->ipi_ehdrlen) { 3033 n = m->m_next; 3034 MPASS(n); 3035 if (n->m_len >= sizeof(*ip)) { 3036 ip = (struct ip *)n->m_data; 3037 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3038 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3039 } else { 3040 txq->ift_pullups++; 3041 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3042 return (ENOMEM); 3043 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3044 } 3045 } else { 3046 txq->ift_pullups++; 3047 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3048 return (ENOMEM); 3049 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3050 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3051 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3052 } 3053 } else { 3054 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3055 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3056 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3057 } 3058 pi->ipi_ip_hlen = ip->ip_hl << 2; 3059 pi->ipi_ipproto = ip->ip_p; 3060 pi->ipi_flags |= IPI_TX_IPV4; 3061 3062 /* TCP checksum offload may require TCP header length */ 3063 if (IS_TX_OFFLOAD4(pi)) { 3064 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3065 if (__predict_false(th == NULL)) { 3066 txq->ift_pullups++; 3067 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3068 return (ENOMEM); 3069 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3070 } 3071 pi->ipi_tcp_hflags = th->th_flags; 3072 pi->ipi_tcp_hlen = th->th_off << 2; 3073 pi->ipi_tcp_seq = th->th_seq; 3074 } 3075 if (IS_TSO4(pi)) { 3076 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3077 return (ENXIO); 3078 /* 3079 * TSO always requires hardware checksum offload. 3080 */ 3081 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3082 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3083 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3084 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3085 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3086 ip->ip_sum = 0; 3087 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3088 } 3089 } 3090 } 3091 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3092 ip->ip_sum = 0; 3093 3094 break; 3095 } 3096 #endif 3097 #ifdef INET6 3098 case ETHERTYPE_IPV6: 3099 { 3100 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3101 struct tcphdr *th; 3102 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3103 3104 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3105 txq->ift_pullups++; 3106 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3107 return (ENOMEM); 3108 } 3109 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3110 3111 /* XXX-BZ this will go badly in case of ext hdrs. */ 3112 pi->ipi_ipproto = ip6->ip6_nxt; 3113 pi->ipi_flags |= IPI_TX_IPV6; 3114 3115 /* TCP checksum offload may require TCP header length */ 3116 if (IS_TX_OFFLOAD6(pi)) { 3117 if (pi->ipi_ipproto == IPPROTO_TCP) { 3118 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3119 txq->ift_pullups++; 3120 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3121 return (ENOMEM); 3122 } 3123 pi->ipi_tcp_hflags = th->th_flags; 3124 pi->ipi_tcp_hlen = th->th_off << 2; 3125 pi->ipi_tcp_seq = th->th_seq; 3126 } 3127 if (IS_TSO6(pi)) { 3128 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3129 return (ENXIO); 3130 /* 3131 * TSO always requires hardware checksum offload. 3132 */ 3133 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3134 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3135 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3136 } 3137 } 3138 break; 3139 } 3140 #endif 3141 default: 3142 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3143 pi->ipi_ip_hlen = 0; 3144 break; 3145 } 3146 *mp = m; 3147 3148 return (0); 3149 } 3150 3151 /* 3152 * If dodgy hardware rejects the scatter gather chain we've handed it 3153 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3154 * m_defrag'd mbufs 3155 */ 3156 static __noinline struct mbuf * 3157 iflib_remove_mbuf(iflib_txq_t txq) 3158 { 3159 int ntxd, pidx; 3160 struct mbuf *m, **ifsd_m; 3161 3162 ifsd_m = txq->ift_sds.ifsd_m; 3163 ntxd = txq->ift_size; 3164 pidx = txq->ift_pidx & (ntxd - 1); 3165 ifsd_m = txq->ift_sds.ifsd_m; 3166 m = ifsd_m[pidx]; 3167 ifsd_m[pidx] = NULL; 3168 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3169 if (txq->ift_sds.ifsd_tso_map != NULL) 3170 bus_dmamap_unload(txq->ift_tso_buf_tag, 3171 txq->ift_sds.ifsd_tso_map[pidx]); 3172 #if MEMORY_LOGGING 3173 txq->ift_dequeued++; 3174 #endif 3175 return (m); 3176 } 3177 3178 static inline caddr_t 3179 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3180 { 3181 qidx_t size; 3182 int ntxd; 3183 caddr_t start, end, cur, next; 3184 3185 ntxd = txq->ift_size; 3186 size = txq->ift_txd_size[qid]; 3187 start = txq->ift_ifdi[qid].idi_vaddr; 3188 3189 if (__predict_false(size == 0)) 3190 return (start); 3191 cur = start + size*cidx; 3192 end = start + size*ntxd; 3193 next = CACHE_PTR_NEXT(cur); 3194 return (next < end ? next : start); 3195 } 3196 3197 /* 3198 * Pad an mbuf to ensure a minimum ethernet frame size. 3199 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3200 */ 3201 static __noinline int 3202 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3203 { 3204 /* 3205 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3206 * and ARP message is the smallest common payload I can think of 3207 */ 3208 static char pad[18]; /* just zeros */ 3209 int n; 3210 struct mbuf *new_head; 3211 3212 if (!M_WRITABLE(*m_head)) { 3213 new_head = m_dup(*m_head, M_NOWAIT); 3214 if (new_head == NULL) { 3215 m_freem(*m_head); 3216 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3217 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3218 DBG_COUNTER_INC(tx_frees); 3219 return ENOMEM; 3220 } 3221 m_freem(*m_head); 3222 *m_head = new_head; 3223 } 3224 3225 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3226 n > 0; n -= sizeof(pad)) 3227 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3228 break; 3229 3230 if (n > 0) { 3231 m_freem(*m_head); 3232 device_printf(dev, "cannot pad short frame\n"); 3233 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3234 DBG_COUNTER_INC(tx_frees); 3235 return (ENOBUFS); 3236 } 3237 3238 return 0; 3239 } 3240 3241 static int 3242 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3243 { 3244 if_ctx_t ctx; 3245 if_shared_ctx_t sctx; 3246 if_softc_ctx_t scctx; 3247 bus_dma_tag_t buf_tag; 3248 bus_dma_segment_t *segs; 3249 struct mbuf *m_head, **ifsd_m; 3250 void *next_txd; 3251 bus_dmamap_t map; 3252 struct if_pkt_info pi; 3253 int remap = 0; 3254 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3255 3256 ctx = txq->ift_ctx; 3257 sctx = ctx->ifc_sctx; 3258 scctx = &ctx->ifc_softc_ctx; 3259 segs = txq->ift_segs; 3260 ntxd = txq->ift_size; 3261 m_head = *m_headp; 3262 map = NULL; 3263 3264 /* 3265 * If we're doing TSO the next descriptor to clean may be quite far ahead 3266 */ 3267 cidx = txq->ift_cidx; 3268 pidx = txq->ift_pidx; 3269 if (ctx->ifc_flags & IFC_PREFETCH) { 3270 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3271 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3272 next_txd = calc_next_txd(txq, cidx, 0); 3273 prefetch(next_txd); 3274 } 3275 3276 /* prefetch the next cache line of mbuf pointers and flags */ 3277 prefetch(&txq->ift_sds.ifsd_m[next]); 3278 prefetch(&txq->ift_sds.ifsd_map[next]); 3279 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3280 } 3281 map = txq->ift_sds.ifsd_map[pidx]; 3282 ifsd_m = txq->ift_sds.ifsd_m; 3283 3284 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3285 buf_tag = txq->ift_tso_buf_tag; 3286 max_segs = scctx->isc_tx_tso_segments_max; 3287 map = txq->ift_sds.ifsd_tso_map[pidx]; 3288 MPASS(buf_tag != NULL); 3289 MPASS(max_segs > 0); 3290 } else { 3291 buf_tag = txq->ift_buf_tag; 3292 max_segs = scctx->isc_tx_nsegments; 3293 map = txq->ift_sds.ifsd_map[pidx]; 3294 } 3295 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3296 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3297 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3298 if (err) { 3299 DBG_COUNTER_INC(encap_txd_encap_fail); 3300 return err; 3301 } 3302 } 3303 m_head = *m_headp; 3304 3305 pkt_info_zero(&pi); 3306 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3307 pi.ipi_pidx = pidx; 3308 pi.ipi_qsidx = txq->ift_id; 3309 pi.ipi_len = m_head->m_pkthdr.len; 3310 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3311 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3312 3313 /* deliberate bitwise OR to make one condition */ 3314 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3315 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3316 DBG_COUNTER_INC(encap_txd_encap_fail); 3317 return (err); 3318 } 3319 m_head = *m_headp; 3320 } 3321 3322 retry: 3323 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3324 BUS_DMA_NOWAIT); 3325 defrag: 3326 if (__predict_false(err)) { 3327 switch (err) { 3328 case EFBIG: 3329 /* try collapse once and defrag once */ 3330 if (remap == 0) { 3331 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3332 /* try defrag if collapsing fails */ 3333 if (m_head == NULL) 3334 remap++; 3335 } 3336 if (remap == 1) { 3337 txq->ift_mbuf_defrag++; 3338 m_head = m_defrag(*m_headp, M_NOWAIT); 3339 } 3340 /* 3341 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3342 * failed to map an mbuf that was run through m_defrag 3343 */ 3344 MPASS(remap <= 1); 3345 if (__predict_false(m_head == NULL || remap > 1)) 3346 goto defrag_failed; 3347 remap++; 3348 *m_headp = m_head; 3349 goto retry; 3350 break; 3351 case ENOMEM: 3352 txq->ift_no_tx_dma_setup++; 3353 break; 3354 default: 3355 txq->ift_no_tx_dma_setup++; 3356 m_freem(*m_headp); 3357 DBG_COUNTER_INC(tx_frees); 3358 *m_headp = NULL; 3359 break; 3360 } 3361 txq->ift_map_failed++; 3362 DBG_COUNTER_INC(encap_load_mbuf_fail); 3363 DBG_COUNTER_INC(encap_txd_encap_fail); 3364 return (err); 3365 } 3366 ifsd_m[pidx] = m_head; 3367 /* 3368 * XXX assumes a 1 to 1 relationship between segments and 3369 * descriptors - this does not hold true on all drivers, e.g. 3370 * cxgb 3371 */ 3372 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3373 txq->ift_no_desc_avail++; 3374 bus_dmamap_unload(buf_tag, map); 3375 DBG_COUNTER_INC(encap_txq_avail_fail); 3376 DBG_COUNTER_INC(encap_txd_encap_fail); 3377 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3378 GROUPTASK_ENQUEUE(&txq->ift_task); 3379 return (ENOBUFS); 3380 } 3381 /* 3382 * On Intel cards we can greatly reduce the number of TX interrupts 3383 * we see by only setting report status on every Nth descriptor. 3384 * However, this also means that the driver will need to keep track 3385 * of the descriptors that RS was set on to check them for the DD bit. 3386 */ 3387 txq->ift_rs_pending += nsegs + 1; 3388 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3389 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3390 pi.ipi_flags |= IPI_TX_INTR; 3391 txq->ift_rs_pending = 0; 3392 } 3393 3394 pi.ipi_segs = segs; 3395 pi.ipi_nsegs = nsegs; 3396 3397 MPASS(pidx >= 0 && pidx < txq->ift_size); 3398 #ifdef PKT_DEBUG 3399 print_pkt(&pi); 3400 #endif 3401 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3402 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3403 DBG_COUNTER_INC(tx_encap); 3404 MPASS(pi.ipi_new_pidx < txq->ift_size); 3405 3406 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3407 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3408 ndesc += txq->ift_size; 3409 txq->ift_gen = 1; 3410 } 3411 /* 3412 * drivers can need as many as 3413 * two sentinels 3414 */ 3415 MPASS(ndesc <= pi.ipi_nsegs + 2); 3416 MPASS(pi.ipi_new_pidx != pidx); 3417 MPASS(ndesc > 0); 3418 txq->ift_in_use += ndesc; 3419 3420 /* 3421 * We update the last software descriptor again here because there may 3422 * be a sentinel and/or there may be more mbufs than segments 3423 */ 3424 txq->ift_pidx = pi.ipi_new_pidx; 3425 txq->ift_npending += pi.ipi_ndescs; 3426 } else { 3427 *m_headp = m_head = iflib_remove_mbuf(txq); 3428 if (err == EFBIG) { 3429 txq->ift_txd_encap_efbig++; 3430 if (remap < 2) { 3431 remap = 1; 3432 goto defrag; 3433 } 3434 } 3435 goto defrag_failed; 3436 } 3437 /* 3438 * err can't possibly be non-zero here, so we don't neet to test it 3439 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3440 */ 3441 return (err); 3442 3443 defrag_failed: 3444 txq->ift_mbuf_defrag_failed++; 3445 txq->ift_map_failed++; 3446 m_freem(*m_headp); 3447 DBG_COUNTER_INC(tx_frees); 3448 *m_headp = NULL; 3449 DBG_COUNTER_INC(encap_txd_encap_fail); 3450 return (ENOMEM); 3451 } 3452 3453 static void 3454 iflib_tx_desc_free(iflib_txq_t txq, int n) 3455 { 3456 uint32_t qsize, cidx, mask, gen; 3457 struct mbuf *m, **ifsd_m; 3458 bool do_prefetch; 3459 3460 cidx = txq->ift_cidx; 3461 gen = txq->ift_gen; 3462 qsize = txq->ift_size; 3463 mask = qsize-1; 3464 ifsd_m = txq->ift_sds.ifsd_m; 3465 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3466 3467 while (n-- > 0) { 3468 if (do_prefetch) { 3469 prefetch(ifsd_m[(cidx + 3) & mask]); 3470 prefetch(ifsd_m[(cidx + 4) & mask]); 3471 } 3472 if ((m = ifsd_m[cidx]) != NULL) { 3473 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3474 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3475 bus_dmamap_sync(txq->ift_tso_buf_tag, 3476 txq->ift_sds.ifsd_tso_map[cidx], 3477 BUS_DMASYNC_POSTWRITE); 3478 bus_dmamap_unload(txq->ift_tso_buf_tag, 3479 txq->ift_sds.ifsd_tso_map[cidx]); 3480 } else { 3481 bus_dmamap_sync(txq->ift_buf_tag, 3482 txq->ift_sds.ifsd_map[cidx], 3483 BUS_DMASYNC_POSTWRITE); 3484 bus_dmamap_unload(txq->ift_buf_tag, 3485 txq->ift_sds.ifsd_map[cidx]); 3486 } 3487 /* XXX we don't support any drivers that batch packets yet */ 3488 MPASS(m->m_nextpkt == NULL); 3489 m_freem(m); 3490 ifsd_m[cidx] = NULL; 3491 #if MEMORY_LOGGING 3492 txq->ift_dequeued++; 3493 #endif 3494 DBG_COUNTER_INC(tx_frees); 3495 } 3496 if (__predict_false(++cidx == qsize)) { 3497 cidx = 0; 3498 gen = 0; 3499 } 3500 } 3501 txq->ift_cidx = cidx; 3502 txq->ift_gen = gen; 3503 } 3504 3505 static __inline int 3506 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3507 { 3508 int reclaim; 3509 if_ctx_t ctx = txq->ift_ctx; 3510 3511 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3512 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3513 3514 /* 3515 * Need a rate-limiting check so that this isn't called every time 3516 */ 3517 iflib_tx_credits_update(ctx, txq); 3518 reclaim = DESC_RECLAIMABLE(txq); 3519 3520 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3521 #ifdef INVARIANTS 3522 if (iflib_verbose_debug) { 3523 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3524 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3525 reclaim, thresh); 3526 3527 } 3528 #endif 3529 return (0); 3530 } 3531 iflib_tx_desc_free(txq, reclaim); 3532 txq->ift_cleaned += reclaim; 3533 txq->ift_in_use -= reclaim; 3534 3535 return (reclaim); 3536 } 3537 3538 static struct mbuf ** 3539 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3540 { 3541 int next, size; 3542 struct mbuf **items; 3543 3544 size = r->size; 3545 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3546 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3547 3548 prefetch(items[(cidx + offset) & (size-1)]); 3549 if (remaining > 1) { 3550 prefetch2cachelines(&items[next]); 3551 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3552 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3553 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3554 } 3555 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3556 } 3557 3558 static void 3559 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3560 { 3561 3562 ifmp_ring_check_drainage(txq->ift_br, budget); 3563 } 3564 3565 static uint32_t 3566 iflib_txq_can_drain(struct ifmp_ring *r) 3567 { 3568 iflib_txq_t txq = r->cookie; 3569 if_ctx_t ctx = txq->ift_ctx; 3570 3571 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3572 return (1); 3573 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3574 BUS_DMASYNC_POSTREAD); 3575 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3576 false)); 3577 } 3578 3579 static uint32_t 3580 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3581 { 3582 iflib_txq_t txq = r->cookie; 3583 if_ctx_t ctx = txq->ift_ctx; 3584 if_t ifp = ctx->ifc_ifp; 3585 struct mbuf *m, **mp; 3586 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3587 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3588 bool do_prefetch, rang, ring; 3589 3590 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3591 !LINK_ACTIVE(ctx))) { 3592 DBG_COUNTER_INC(txq_drain_notready); 3593 return (0); 3594 } 3595 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3596 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3597 avail = IDXDIFF(pidx, cidx, r->size); 3598 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3599 DBG_COUNTER_INC(txq_drain_flushing); 3600 for (i = 0; i < avail; i++) { 3601 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3602 m_free(r->items[(cidx + i) & (r->size-1)]); 3603 r->items[(cidx + i) & (r->size-1)] = NULL; 3604 } 3605 return (avail); 3606 } 3607 3608 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3609 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3610 CALLOUT_LOCK(txq); 3611 callout_stop(&txq->ift_timer); 3612 CALLOUT_UNLOCK(txq); 3613 DBG_COUNTER_INC(txq_drain_oactive); 3614 return (0); 3615 } 3616 if (reclaimed) 3617 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3618 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3619 count = MIN(avail, TX_BATCH_SIZE); 3620 #ifdef INVARIANTS 3621 if (iflib_verbose_debug) 3622 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3623 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3624 #endif 3625 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3626 txq_avail = TXQ_AVAIL(txq); 3627 err = 0; 3628 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3629 int rem = do_prefetch ? count - i : 0; 3630 3631 mp = _ring_peek_one(r, cidx, i, rem); 3632 MPASS(mp != NULL && *mp != NULL); 3633 if (__predict_false(*mp == (struct mbuf *)txq)) { 3634 consumed++; 3635 continue; 3636 } 3637 in_use_prev = txq->ift_in_use; 3638 err = iflib_encap(txq, mp); 3639 if (__predict_false(err)) { 3640 /* no room - bail out */ 3641 if (err == ENOBUFS) 3642 break; 3643 consumed++; 3644 /* we can't send this packet - skip it */ 3645 continue; 3646 } 3647 consumed++; 3648 pkt_sent++; 3649 m = *mp; 3650 DBG_COUNTER_INC(tx_sent); 3651 bytes_sent += m->m_pkthdr.len; 3652 mcast_sent += !!(m->m_flags & M_MCAST); 3653 txq_avail = TXQ_AVAIL(txq); 3654 3655 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3656 ETHER_BPF_MTAP(ifp, m); 3657 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3658 break; 3659 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3660 } 3661 3662 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3663 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3664 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3665 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3666 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3667 if (mcast_sent) 3668 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3669 #ifdef INVARIANTS 3670 if (iflib_verbose_debug) 3671 printf("consumed=%d\n", consumed); 3672 #endif 3673 return (consumed); 3674 } 3675 3676 static uint32_t 3677 iflib_txq_drain_always(struct ifmp_ring *r) 3678 { 3679 return (1); 3680 } 3681 3682 static uint32_t 3683 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3684 { 3685 int i, avail; 3686 struct mbuf **mp; 3687 iflib_txq_t txq; 3688 3689 txq = r->cookie; 3690 3691 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3692 CALLOUT_LOCK(txq); 3693 callout_stop(&txq->ift_timer); 3694 CALLOUT_UNLOCK(txq); 3695 3696 avail = IDXDIFF(pidx, cidx, r->size); 3697 for (i = 0; i < avail; i++) { 3698 mp = _ring_peek_one(r, cidx, i, avail - i); 3699 if (__predict_false(*mp == (struct mbuf *)txq)) 3700 continue; 3701 m_freem(*mp); 3702 DBG_COUNTER_INC(tx_frees); 3703 } 3704 MPASS(ifmp_ring_is_stalled(r) == 0); 3705 return (avail); 3706 } 3707 3708 static void 3709 iflib_ifmp_purge(iflib_txq_t txq) 3710 { 3711 struct ifmp_ring *r; 3712 3713 r = txq->ift_br; 3714 r->drain = iflib_txq_drain_free; 3715 r->can_drain = iflib_txq_drain_always; 3716 3717 ifmp_ring_check_drainage(r, r->size); 3718 3719 r->drain = iflib_txq_drain; 3720 r->can_drain = iflib_txq_can_drain; 3721 } 3722 3723 static void 3724 _task_fn_tx(void *context) 3725 { 3726 iflib_txq_t txq = context; 3727 if_ctx_t ctx = txq->ift_ctx; 3728 #if defined(ALTQ) || defined(DEV_NETMAP) 3729 if_t ifp = ctx->ifc_ifp; 3730 #endif 3731 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3732 3733 #ifdef IFLIB_DIAGNOSTICS 3734 txq->ift_cpu_exec_count[curcpu]++; 3735 #endif 3736 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3737 return; 3738 #ifdef DEV_NETMAP 3739 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3740 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3741 BUS_DMASYNC_POSTREAD); 3742 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3743 netmap_tx_irq(ifp, txq->ift_id); 3744 if (ctx->ifc_flags & IFC_LEGACY) 3745 IFDI_INTR_ENABLE(ctx); 3746 else 3747 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3748 return; 3749 } 3750 #endif 3751 #ifdef ALTQ 3752 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3753 iflib_altq_if_start(ifp); 3754 #endif 3755 if (txq->ift_db_pending) 3756 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3757 else if (!abdicate) 3758 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3759 /* 3760 * When abdicating, we always need to check drainage, not just when we don't enqueue 3761 */ 3762 if (abdicate) 3763 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3764 if (ctx->ifc_flags & IFC_LEGACY) 3765 IFDI_INTR_ENABLE(ctx); 3766 else 3767 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3768 } 3769 3770 static void 3771 _task_fn_rx(void *context) 3772 { 3773 iflib_rxq_t rxq = context; 3774 if_ctx_t ctx = rxq->ifr_ctx; 3775 bool more; 3776 uint16_t budget; 3777 3778 #ifdef IFLIB_DIAGNOSTICS 3779 rxq->ifr_cpu_exec_count[curcpu]++; 3780 #endif 3781 DBG_COUNTER_INC(task_fn_rxs); 3782 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3783 return; 3784 more = true; 3785 #ifdef DEV_NETMAP 3786 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3787 u_int work = 0; 3788 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3789 more = false; 3790 } 3791 } 3792 #endif 3793 budget = ctx->ifc_sysctl_rx_budget; 3794 if (budget == 0) 3795 budget = 16; /* XXX */ 3796 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3797 if (ctx->ifc_flags & IFC_LEGACY) 3798 IFDI_INTR_ENABLE(ctx); 3799 else 3800 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3801 DBG_COUNTER_INC(rx_intr_enables); 3802 } 3803 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3804 return; 3805 if (more) 3806 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3807 } 3808 3809 static void 3810 _task_fn_admin(void *context) 3811 { 3812 if_ctx_t ctx = context; 3813 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3814 iflib_txq_t txq; 3815 int i; 3816 bool oactive, running, do_reset, do_watchdog, in_detach; 3817 uint32_t reset_on = hz / 2; 3818 3819 STATE_LOCK(ctx); 3820 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3821 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3822 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3823 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3824 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3825 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3826 STATE_UNLOCK(ctx); 3827 3828 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3829 return; 3830 if (in_detach) 3831 return; 3832 3833 CTX_LOCK(ctx); 3834 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3835 CALLOUT_LOCK(txq); 3836 callout_stop(&txq->ift_timer); 3837 CALLOUT_UNLOCK(txq); 3838 } 3839 if (do_watchdog) { 3840 ctx->ifc_watchdog_events++; 3841 IFDI_WATCHDOG_RESET(ctx); 3842 } 3843 IFDI_UPDATE_ADMIN_STATUS(ctx); 3844 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3845 #ifdef DEV_NETMAP 3846 reset_on = hz / 2; 3847 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3848 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3849 #endif 3850 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3851 } 3852 IFDI_LINK_INTR_ENABLE(ctx); 3853 if (do_reset) 3854 iflib_if_init_locked(ctx); 3855 CTX_UNLOCK(ctx); 3856 3857 if (LINK_ACTIVE(ctx) == 0) 3858 return; 3859 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3860 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3861 } 3862 3863 3864 static void 3865 _task_fn_iov(void *context) 3866 { 3867 if_ctx_t ctx = context; 3868 3869 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3870 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3871 return; 3872 3873 CTX_LOCK(ctx); 3874 IFDI_VFLR_HANDLE(ctx); 3875 CTX_UNLOCK(ctx); 3876 } 3877 3878 static int 3879 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3880 { 3881 int err; 3882 if_int_delay_info_t info; 3883 if_ctx_t ctx; 3884 3885 info = (if_int_delay_info_t)arg1; 3886 ctx = info->iidi_ctx; 3887 info->iidi_req = req; 3888 info->iidi_oidp = oidp; 3889 CTX_LOCK(ctx); 3890 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3891 CTX_UNLOCK(ctx); 3892 return (err); 3893 } 3894 3895 /********************************************************************* 3896 * 3897 * IFNET FUNCTIONS 3898 * 3899 **********************************************************************/ 3900 3901 static void 3902 iflib_if_init_locked(if_ctx_t ctx) 3903 { 3904 iflib_stop(ctx); 3905 iflib_init_locked(ctx); 3906 } 3907 3908 3909 static void 3910 iflib_if_init(void *arg) 3911 { 3912 if_ctx_t ctx = arg; 3913 3914 CTX_LOCK(ctx); 3915 iflib_if_init_locked(ctx); 3916 CTX_UNLOCK(ctx); 3917 } 3918 3919 static int 3920 iflib_if_transmit(if_t ifp, struct mbuf *m) 3921 { 3922 if_ctx_t ctx = if_getsoftc(ifp); 3923 3924 iflib_txq_t txq; 3925 int err, qidx; 3926 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3927 3928 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3929 DBG_COUNTER_INC(tx_frees); 3930 m_freem(m); 3931 return (ENETDOWN); 3932 } 3933 3934 MPASS(m->m_nextpkt == NULL); 3935 /* ALTQ-enabled interfaces always use queue 0. */ 3936 qidx = 0; 3937 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3938 qidx = QIDX(ctx, m); 3939 /* 3940 * XXX calculate buf_ring based on flowid (divvy up bits?) 3941 */ 3942 txq = &ctx->ifc_txqs[qidx]; 3943 3944 #ifdef DRIVER_BACKPRESSURE 3945 if (txq->ift_closed) { 3946 while (m != NULL) { 3947 next = m->m_nextpkt; 3948 m->m_nextpkt = NULL; 3949 m_freem(m); 3950 DBG_COUNTER_INC(tx_frees); 3951 m = next; 3952 } 3953 return (ENOBUFS); 3954 } 3955 #endif 3956 #ifdef notyet 3957 qidx = count = 0; 3958 mp = marr; 3959 next = m; 3960 do { 3961 count++; 3962 next = next->m_nextpkt; 3963 } while (next != NULL); 3964 3965 if (count > nitems(marr)) 3966 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3967 /* XXX check nextpkt */ 3968 m_freem(m); 3969 /* XXX simplify for now */ 3970 DBG_COUNTER_INC(tx_frees); 3971 return (ENOBUFS); 3972 } 3973 for (next = m, i = 0; next != NULL; i++) { 3974 mp[i] = next; 3975 next = next->m_nextpkt; 3976 mp[i]->m_nextpkt = NULL; 3977 } 3978 #endif 3979 DBG_COUNTER_INC(tx_seen); 3980 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3981 3982 if (abdicate) 3983 GROUPTASK_ENQUEUE(&txq->ift_task); 3984 if (err) { 3985 if (!abdicate) 3986 GROUPTASK_ENQUEUE(&txq->ift_task); 3987 /* support forthcoming later */ 3988 #ifdef DRIVER_BACKPRESSURE 3989 txq->ift_closed = TRUE; 3990 #endif 3991 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3992 m_freem(m); 3993 DBG_COUNTER_INC(tx_frees); 3994 } 3995 3996 return (err); 3997 } 3998 3999 #ifdef ALTQ 4000 /* 4001 * The overall approach to integrating iflib with ALTQ is to continue to use 4002 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4003 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4004 * is redundant/unnecessary, but doing so minimizes the amount of 4005 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4006 * redundantly queueing to an intermediate mp_ring is swamped by the 4007 * performance limitations inherent in using ALTQ. 4008 * 4009 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4010 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4011 * given interface. If ALTQ is enabled for an interface, then all 4012 * transmitted packets for that interface will be submitted to the ALTQ 4013 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4014 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4015 * update stats that the iflib machinery handles, and which is sensitve to 4016 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4017 * will be installed as the start routine for use by ALTQ facilities that 4018 * need to trigger queue drains on a scheduled basis. 4019 * 4020 */ 4021 static void 4022 iflib_altq_if_start(if_t ifp) 4023 { 4024 struct ifaltq *ifq = &ifp->if_snd; 4025 struct mbuf *m; 4026 4027 IFQ_LOCK(ifq); 4028 IFQ_DEQUEUE_NOLOCK(ifq, m); 4029 while (m != NULL) { 4030 iflib_if_transmit(ifp, m); 4031 IFQ_DEQUEUE_NOLOCK(ifq, m); 4032 } 4033 IFQ_UNLOCK(ifq); 4034 } 4035 4036 static int 4037 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4038 { 4039 int err; 4040 4041 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4042 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4043 if (err == 0) 4044 iflib_altq_if_start(ifp); 4045 } else 4046 err = iflib_if_transmit(ifp, m); 4047 4048 return (err); 4049 } 4050 #endif /* ALTQ */ 4051 4052 static void 4053 iflib_if_qflush(if_t ifp) 4054 { 4055 if_ctx_t ctx = if_getsoftc(ifp); 4056 iflib_txq_t txq = ctx->ifc_txqs; 4057 int i; 4058 4059 STATE_LOCK(ctx); 4060 ctx->ifc_flags |= IFC_QFLUSH; 4061 STATE_UNLOCK(ctx); 4062 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4063 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4064 iflib_txq_check_drain(txq, 0); 4065 STATE_LOCK(ctx); 4066 ctx->ifc_flags &= ~IFC_QFLUSH; 4067 STATE_UNLOCK(ctx); 4068 4069 /* 4070 * When ALTQ is enabled, this will also take care of purging the 4071 * ALTQ queue(s). 4072 */ 4073 if_qflush(ifp); 4074 } 4075 4076 4077 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4078 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4079 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4080 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4081 4082 static int 4083 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4084 { 4085 if_ctx_t ctx = if_getsoftc(ifp); 4086 struct ifreq *ifr = (struct ifreq *)data; 4087 #if defined(INET) || defined(INET6) 4088 struct ifaddr *ifa = (struct ifaddr *)data; 4089 #endif 4090 bool avoid_reset = false; 4091 int err = 0, reinit = 0, bits; 4092 4093 switch (command) { 4094 case SIOCSIFADDR: 4095 #ifdef INET 4096 if (ifa->ifa_addr->sa_family == AF_INET) 4097 avoid_reset = true; 4098 #endif 4099 #ifdef INET6 4100 if (ifa->ifa_addr->sa_family == AF_INET6) 4101 avoid_reset = true; 4102 #endif 4103 /* 4104 ** Calling init results in link renegotiation, 4105 ** so we avoid doing it when possible. 4106 */ 4107 if (avoid_reset) { 4108 if_setflagbits(ifp, IFF_UP,0); 4109 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4110 reinit = 1; 4111 #ifdef INET 4112 if (!(if_getflags(ifp) & IFF_NOARP)) 4113 arp_ifinit(ifp, ifa); 4114 #endif 4115 } else 4116 err = ether_ioctl(ifp, command, data); 4117 break; 4118 case SIOCSIFMTU: 4119 CTX_LOCK(ctx); 4120 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4121 CTX_UNLOCK(ctx); 4122 break; 4123 } 4124 bits = if_getdrvflags(ifp); 4125 /* stop the driver and free any clusters before proceeding */ 4126 iflib_stop(ctx); 4127 4128 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4129 STATE_LOCK(ctx); 4130 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4131 ctx->ifc_flags |= IFC_MULTISEG; 4132 else 4133 ctx->ifc_flags &= ~IFC_MULTISEG; 4134 STATE_UNLOCK(ctx); 4135 err = if_setmtu(ifp, ifr->ifr_mtu); 4136 } 4137 iflib_init_locked(ctx); 4138 STATE_LOCK(ctx); 4139 if_setdrvflags(ifp, bits); 4140 STATE_UNLOCK(ctx); 4141 CTX_UNLOCK(ctx); 4142 break; 4143 case SIOCSIFFLAGS: 4144 CTX_LOCK(ctx); 4145 if (if_getflags(ifp) & IFF_UP) { 4146 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4147 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4148 (IFF_PROMISC | IFF_ALLMULTI)) { 4149 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4150 } 4151 } else 4152 reinit = 1; 4153 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4154 iflib_stop(ctx); 4155 } 4156 ctx->ifc_if_flags = if_getflags(ifp); 4157 CTX_UNLOCK(ctx); 4158 break; 4159 case SIOCADDMULTI: 4160 case SIOCDELMULTI: 4161 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4162 CTX_LOCK(ctx); 4163 IFDI_INTR_DISABLE(ctx); 4164 IFDI_MULTI_SET(ctx); 4165 IFDI_INTR_ENABLE(ctx); 4166 CTX_UNLOCK(ctx); 4167 } 4168 break; 4169 case SIOCSIFMEDIA: 4170 CTX_LOCK(ctx); 4171 IFDI_MEDIA_SET(ctx); 4172 CTX_UNLOCK(ctx); 4173 /* FALLTHROUGH */ 4174 case SIOCGIFMEDIA: 4175 case SIOCGIFXMEDIA: 4176 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4177 break; 4178 case SIOCGI2C: 4179 { 4180 struct ifi2creq i2c; 4181 4182 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4183 if (err != 0) 4184 break; 4185 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4186 err = EINVAL; 4187 break; 4188 } 4189 if (i2c.len > sizeof(i2c.data)) { 4190 err = EINVAL; 4191 break; 4192 } 4193 4194 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4195 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4196 sizeof(i2c)); 4197 break; 4198 } 4199 case SIOCSIFCAP: 4200 { 4201 int mask, setmask, oldmask; 4202 4203 oldmask = if_getcapenable(ifp); 4204 mask = ifr->ifr_reqcap ^ oldmask; 4205 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4206 setmask = 0; 4207 #ifdef TCP_OFFLOAD 4208 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4209 #endif 4210 setmask |= (mask & IFCAP_FLAGS); 4211 setmask |= (mask & IFCAP_WOL); 4212 4213 /* 4214 * If any RX csum has changed, change all the ones that 4215 * are supported by the driver. 4216 */ 4217 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4218 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4219 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4220 } 4221 4222 /* 4223 * want to ensure that traffic has stopped before we change any of the flags 4224 */ 4225 if (setmask) { 4226 CTX_LOCK(ctx); 4227 bits = if_getdrvflags(ifp); 4228 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4229 iflib_stop(ctx); 4230 STATE_LOCK(ctx); 4231 if_togglecapenable(ifp, setmask); 4232 STATE_UNLOCK(ctx); 4233 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4234 iflib_init_locked(ctx); 4235 STATE_LOCK(ctx); 4236 if_setdrvflags(ifp, bits); 4237 STATE_UNLOCK(ctx); 4238 CTX_UNLOCK(ctx); 4239 } 4240 if_vlancap(ifp); 4241 break; 4242 } 4243 case SIOCGPRIVATE_0: 4244 case SIOCSDRVSPEC: 4245 case SIOCGDRVSPEC: 4246 CTX_LOCK(ctx); 4247 err = IFDI_PRIV_IOCTL(ctx, command, data); 4248 CTX_UNLOCK(ctx); 4249 break; 4250 default: 4251 err = ether_ioctl(ifp, command, data); 4252 break; 4253 } 4254 if (reinit) 4255 iflib_if_init(ctx); 4256 return (err); 4257 } 4258 4259 static uint64_t 4260 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4261 { 4262 if_ctx_t ctx = if_getsoftc(ifp); 4263 4264 return (IFDI_GET_COUNTER(ctx, cnt)); 4265 } 4266 4267 /********************************************************************* 4268 * 4269 * OTHER FUNCTIONS EXPORTED TO THE STACK 4270 * 4271 **********************************************************************/ 4272 4273 static void 4274 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4275 { 4276 if_ctx_t ctx = if_getsoftc(ifp); 4277 4278 if ((void *)ctx != arg) 4279 return; 4280 4281 if ((vtag == 0) || (vtag > 4095)) 4282 return; 4283 4284 if (iflib_in_detach(ctx)) 4285 return; 4286 4287 CTX_LOCK(ctx); 4288 IFDI_VLAN_REGISTER(ctx, vtag); 4289 /* Re-init to load the changes */ 4290 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4291 iflib_if_init_locked(ctx); 4292 CTX_UNLOCK(ctx); 4293 } 4294 4295 static void 4296 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4297 { 4298 if_ctx_t ctx = if_getsoftc(ifp); 4299 4300 if ((void *)ctx != arg) 4301 return; 4302 4303 if ((vtag == 0) || (vtag > 4095)) 4304 return; 4305 4306 CTX_LOCK(ctx); 4307 IFDI_VLAN_UNREGISTER(ctx, vtag); 4308 /* Re-init to load the changes */ 4309 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4310 iflib_if_init_locked(ctx); 4311 CTX_UNLOCK(ctx); 4312 } 4313 4314 static void 4315 iflib_led_func(void *arg, int onoff) 4316 { 4317 if_ctx_t ctx = arg; 4318 4319 CTX_LOCK(ctx); 4320 IFDI_LED_FUNC(ctx, onoff); 4321 CTX_UNLOCK(ctx); 4322 } 4323 4324 /********************************************************************* 4325 * 4326 * BUS FUNCTION DEFINITIONS 4327 * 4328 **********************************************************************/ 4329 4330 int 4331 iflib_device_probe(device_t dev) 4332 { 4333 const pci_vendor_info_t *ent; 4334 if_shared_ctx_t sctx; 4335 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4336 uint16_t pci_vendor_id; 4337 4338 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4339 return (ENOTSUP); 4340 4341 pci_vendor_id = pci_get_vendor(dev); 4342 pci_device_id = pci_get_device(dev); 4343 pci_subvendor_id = pci_get_subvendor(dev); 4344 pci_subdevice_id = pci_get_subdevice(dev); 4345 pci_rev_id = pci_get_revid(dev); 4346 if (sctx->isc_parse_devinfo != NULL) 4347 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4348 4349 ent = sctx->isc_vendor_info; 4350 while (ent->pvi_vendor_id != 0) { 4351 if (pci_vendor_id != ent->pvi_vendor_id) { 4352 ent++; 4353 continue; 4354 } 4355 if ((pci_device_id == ent->pvi_device_id) && 4356 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4357 (ent->pvi_subvendor_id == 0)) && 4358 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4359 (ent->pvi_subdevice_id == 0)) && 4360 ((pci_rev_id == ent->pvi_rev_id) || 4361 (ent->pvi_rev_id == 0))) { 4362 4363 device_set_desc_copy(dev, ent->pvi_name); 4364 /* this needs to be changed to zero if the bus probing code 4365 * ever stops re-probing on best match because the sctx 4366 * may have its values over written by register calls 4367 * in subsequent probes 4368 */ 4369 return (BUS_PROBE_DEFAULT); 4370 } 4371 ent++; 4372 } 4373 return (ENXIO); 4374 } 4375 4376 int 4377 iflib_device_probe_vendor(device_t dev) 4378 { 4379 int probe; 4380 4381 probe = iflib_device_probe(dev); 4382 if (probe == BUS_PROBE_DEFAULT) 4383 return (BUS_PROBE_VENDOR); 4384 else 4385 return (probe); 4386 } 4387 4388 static void 4389 iflib_reset_qvalues(if_ctx_t ctx) 4390 { 4391 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4392 if_shared_ctx_t sctx = ctx->ifc_sctx; 4393 device_t dev = ctx->ifc_dev; 4394 int i; 4395 4396 if (ctx->ifc_sysctl_ntxqs != 0) 4397 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4398 if (ctx->ifc_sysctl_nrxqs != 0) 4399 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4400 4401 for (i = 0; i < sctx->isc_ntxqs; i++) { 4402 if (ctx->ifc_sysctl_ntxds[i] != 0) 4403 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4404 else 4405 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4406 } 4407 4408 for (i = 0; i < sctx->isc_nrxqs; i++) { 4409 if (ctx->ifc_sysctl_nrxds[i] != 0) 4410 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4411 else 4412 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4413 } 4414 4415 for (i = 0; i < sctx->isc_nrxqs; i++) { 4416 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4417 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4418 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4419 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4420 } 4421 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4422 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4423 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4424 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4425 } 4426 if (!powerof2(scctx->isc_nrxd[i])) { 4427 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4428 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4429 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4430 } 4431 } 4432 4433 for (i = 0; i < sctx->isc_ntxqs; i++) { 4434 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4435 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4436 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4437 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4438 } 4439 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4440 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4441 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4442 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4443 } 4444 if (!powerof2(scctx->isc_ntxd[i])) { 4445 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4446 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4447 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4448 } 4449 } 4450 } 4451 4452 static void 4453 iflib_add_pfil(if_ctx_t ctx) 4454 { 4455 struct pfil_head *pfil; 4456 struct pfil_head_args pa; 4457 iflib_rxq_t rxq; 4458 int i; 4459 4460 pa.pa_version = PFIL_VERSION; 4461 pa.pa_flags = PFIL_IN; 4462 pa.pa_type = PFIL_TYPE_ETHERNET; 4463 pa.pa_headname = ctx->ifc_ifp->if_xname; 4464 pfil = pfil_head_register(&pa); 4465 4466 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4467 rxq->pfil = pfil; 4468 } 4469 } 4470 4471 static void 4472 iflib_rem_pfil(if_ctx_t ctx) 4473 { 4474 struct pfil_head *pfil; 4475 iflib_rxq_t rxq; 4476 int i; 4477 4478 rxq = ctx->ifc_rxqs; 4479 pfil = rxq->pfil; 4480 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4481 rxq->pfil = NULL; 4482 } 4483 pfil_head_unregister(pfil); 4484 } 4485 4486 static uint16_t 4487 get_ctx_core_offset(if_ctx_t ctx) 4488 { 4489 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4490 struct cpu_offset *op; 4491 uint16_t qc; 4492 uint16_t ret = ctx->ifc_sysctl_core_offset; 4493 4494 if (ret != CORE_OFFSET_UNSPECIFIED) 4495 return (ret); 4496 4497 if (ctx->ifc_sysctl_separate_txrx) 4498 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4499 else 4500 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4501 4502 mtx_lock(&cpu_offset_mtx); 4503 SLIST_FOREACH(op, &cpu_offsets, entries) { 4504 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4505 ret = op->offset; 4506 op->offset += qc; 4507 MPASS(op->refcount < UINT_MAX); 4508 op->refcount++; 4509 break; 4510 } 4511 } 4512 if (ret == CORE_OFFSET_UNSPECIFIED) { 4513 ret = 0; 4514 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4515 M_NOWAIT | M_ZERO); 4516 if (op == NULL) { 4517 device_printf(ctx->ifc_dev, 4518 "allocation for cpu offset failed.\n"); 4519 } else { 4520 op->offset = qc; 4521 op->refcount = 1; 4522 CPU_COPY(&ctx->ifc_cpus, &op->set); 4523 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4524 } 4525 } 4526 mtx_unlock(&cpu_offset_mtx); 4527 4528 return (ret); 4529 } 4530 4531 static void 4532 unref_ctx_core_offset(if_ctx_t ctx) 4533 { 4534 struct cpu_offset *op, *top; 4535 4536 mtx_lock(&cpu_offset_mtx); 4537 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4538 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4539 MPASS(op->refcount > 0); 4540 op->refcount--; 4541 if (op->refcount == 0) { 4542 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4543 free(op, M_IFLIB); 4544 } 4545 break; 4546 } 4547 } 4548 mtx_unlock(&cpu_offset_mtx); 4549 } 4550 4551 int 4552 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4553 { 4554 if_ctx_t ctx; 4555 if_t ifp; 4556 if_softc_ctx_t scctx; 4557 kobjop_desc_t kobj_desc; 4558 kobj_method_t *kobj_method; 4559 int err, msix, rid; 4560 uint16_t main_rxq, main_txq; 4561 4562 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4563 4564 if (sc == NULL) { 4565 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4566 device_set_softc(dev, ctx); 4567 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4568 } 4569 4570 ctx->ifc_sctx = sctx; 4571 ctx->ifc_dev = dev; 4572 ctx->ifc_softc = sc; 4573 4574 if ((err = iflib_register(ctx)) != 0) { 4575 device_printf(dev, "iflib_register failed %d\n", err); 4576 goto fail_ctx_free; 4577 } 4578 iflib_add_device_sysctl_pre(ctx); 4579 4580 scctx = &ctx->ifc_softc_ctx; 4581 ifp = ctx->ifc_ifp; 4582 4583 iflib_reset_qvalues(ctx); 4584 CTX_LOCK(ctx); 4585 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4586 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4587 goto fail_unlock; 4588 } 4589 _iflib_pre_assert(scctx); 4590 ctx->ifc_txrx = *scctx->isc_txrx; 4591 4592 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4593 ctx->ifc_mediap = scctx->isc_media; 4594 4595 #ifdef INVARIANTS 4596 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4597 MPASS(scctx->isc_tx_csum_flags); 4598 #endif 4599 4600 if_setcapabilities(ifp, 4601 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4602 if_setcapenable(ifp, 4603 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4604 4605 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4606 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4607 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4608 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4609 4610 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4611 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4612 4613 /* XXX change for per-queue sizes */ 4614 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4615 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4616 4617 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4618 MAX_SINGLE_PACKET_FRACTION) 4619 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4620 MAX_SINGLE_PACKET_FRACTION); 4621 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4622 MAX_SINGLE_PACKET_FRACTION) 4623 scctx->isc_tx_tso_segments_max = max(1, 4624 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4625 4626 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4627 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4628 /* 4629 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4630 * but some MACs do. 4631 */ 4632 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4633 IP_MAXPACKET)); 4634 /* 4635 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4636 * into account. In the worst case, each of these calls will 4637 * add another mbuf and, thus, the requirement for another DMA 4638 * segment. So for best performance, it doesn't make sense to 4639 * advertize a maximum of TSO segments that typically will 4640 * require defragmentation in iflib_encap(). 4641 */ 4642 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4643 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4644 } 4645 if (scctx->isc_rss_table_size == 0) 4646 scctx->isc_rss_table_size = 64; 4647 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4648 4649 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4650 /* XXX format name */ 4651 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4652 NULL, NULL, "admin"); 4653 4654 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4655 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4656 device_printf(dev, "Unable to fetch CPU list\n"); 4657 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4658 } 4659 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4660 4661 /* 4662 ** Now set up MSI or MSI-X, should return us the number of supported 4663 ** vectors (will be 1 for a legacy interrupt and MSI). 4664 */ 4665 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4666 msix = scctx->isc_vectors; 4667 } else if (scctx->isc_msix_bar != 0) 4668 /* 4669 * The simple fact that isc_msix_bar is not 0 does not mean we 4670 * we have a good value there that is known to work. 4671 */ 4672 msix = iflib_msix_init(ctx); 4673 else { 4674 scctx->isc_vectors = 1; 4675 scctx->isc_ntxqsets = 1; 4676 scctx->isc_nrxqsets = 1; 4677 scctx->isc_intr = IFLIB_INTR_LEGACY; 4678 msix = 0; 4679 } 4680 /* Get memory for the station queues */ 4681 if ((err = iflib_queues_alloc(ctx))) { 4682 device_printf(dev, "Unable to allocate queue memory\n"); 4683 goto fail_intr_free; 4684 } 4685 4686 if ((err = iflib_qset_structures_setup(ctx))) 4687 goto fail_queues; 4688 4689 /* 4690 * Now that we know how many queues there are, get the core offset. 4691 */ 4692 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4693 4694 /* 4695 * Group taskqueues aren't properly set up until SMP is started, 4696 * so we disable interrupts until we can handle them post 4697 * SI_SUB_SMP. 4698 * 4699 * XXX: disabling interrupts doesn't actually work, at least for 4700 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4701 * we do null handling and depend on this not causing too large an 4702 * interrupt storm. 4703 */ 4704 IFDI_INTR_DISABLE(ctx); 4705 4706 if (msix > 1) { 4707 /* 4708 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4709 * aren't the default NULL implementation. 4710 */ 4711 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4712 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4713 kobj_desc); 4714 if (kobj_method == &kobj_desc->deflt) { 4715 device_printf(dev, 4716 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4717 err = EOPNOTSUPP; 4718 goto fail_queues; 4719 } 4720 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4721 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4722 kobj_desc); 4723 if (kobj_method == &kobj_desc->deflt) { 4724 device_printf(dev, 4725 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4726 err = EOPNOTSUPP; 4727 goto fail_queues; 4728 } 4729 4730 /* 4731 * Assign the MSI-X vectors. 4732 * Note that the default NULL ifdi_msix_intr_assign method will 4733 * fail here, too. 4734 */ 4735 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4736 if (err != 0) { 4737 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4738 err); 4739 goto fail_queues; 4740 } 4741 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4742 rid = 0; 4743 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4744 MPASS(msix == 1); 4745 rid = 1; 4746 } 4747 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4748 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4749 goto fail_queues; 4750 } 4751 } else { 4752 device_printf(dev, 4753 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4754 err = ENODEV; 4755 goto fail_intr_free; 4756 } 4757 4758 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4759 4760 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4761 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4762 goto fail_detach; 4763 } 4764 4765 /* 4766 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4767 * This must appear after the call to ether_ifattach() because 4768 * ether_ifattach() sets if_hdrlen to the default value. 4769 */ 4770 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4771 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4772 4773 if ((err = iflib_netmap_attach(ctx))) { 4774 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4775 goto fail_detach; 4776 } 4777 *ctxp = ctx; 4778 4779 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4780 4781 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4782 iflib_add_device_sysctl_post(ctx); 4783 iflib_add_pfil(ctx); 4784 ctx->ifc_flags |= IFC_INIT_DONE; 4785 CTX_UNLOCK(ctx); 4786 4787 return (0); 4788 4789 fail_detach: 4790 ether_ifdetach(ctx->ifc_ifp); 4791 fail_intr_free: 4792 iflib_free_intr_mem(ctx); 4793 fail_queues: 4794 iflib_tx_structures_free(ctx); 4795 iflib_rx_structures_free(ctx); 4796 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4797 IFDI_DETACH(ctx); 4798 fail_unlock: 4799 CTX_UNLOCK(ctx); 4800 iflib_deregister(ctx); 4801 fail_ctx_free: 4802 device_set_softc(ctx->ifc_dev, NULL); 4803 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4804 free(ctx->ifc_softc, M_IFLIB); 4805 free(ctx, M_IFLIB); 4806 return (err); 4807 } 4808 4809 int 4810 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4811 struct iflib_cloneattach_ctx *clctx) 4812 { 4813 int err; 4814 if_ctx_t ctx; 4815 if_t ifp; 4816 if_softc_ctx_t scctx; 4817 int i; 4818 void *sc; 4819 uint16_t main_txq; 4820 uint16_t main_rxq; 4821 4822 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4823 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4824 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4825 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4826 ctx->ifc_flags |= IFC_PSEUDO; 4827 4828 ctx->ifc_sctx = sctx; 4829 ctx->ifc_softc = sc; 4830 ctx->ifc_dev = dev; 4831 4832 if ((err = iflib_register(ctx)) != 0) { 4833 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4834 goto fail_ctx_free; 4835 } 4836 iflib_add_device_sysctl_pre(ctx); 4837 4838 scctx = &ctx->ifc_softc_ctx; 4839 ifp = ctx->ifc_ifp; 4840 4841 iflib_reset_qvalues(ctx); 4842 CTX_LOCK(ctx); 4843 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4844 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4845 goto fail_unlock; 4846 } 4847 if (sctx->isc_flags & IFLIB_GEN_MAC) 4848 ether_gen_addr(ifp, &ctx->ifc_mac); 4849 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4850 clctx->cc_params)) != 0) { 4851 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4852 goto fail_ctx_free; 4853 } 4854 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4855 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4856 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4857 4858 #ifdef INVARIANTS 4859 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4860 MPASS(scctx->isc_tx_csum_flags); 4861 #endif 4862 4863 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4864 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4865 4866 ifp->if_flags |= IFF_NOGROUP; 4867 if (sctx->isc_flags & IFLIB_PSEUDO) { 4868 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4869 4870 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4871 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4872 goto fail_detach; 4873 } 4874 *ctxp = ctx; 4875 4876 /* 4877 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4878 * This must appear after the call to ether_ifattach() because 4879 * ether_ifattach() sets if_hdrlen to the default value. 4880 */ 4881 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4882 if_setifheaderlen(ifp, 4883 sizeof(struct ether_vlan_header)); 4884 4885 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4886 iflib_add_device_sysctl_post(ctx); 4887 ctx->ifc_flags |= IFC_INIT_DONE; 4888 return (0); 4889 } 4890 _iflib_pre_assert(scctx); 4891 ctx->ifc_txrx = *scctx->isc_txrx; 4892 4893 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4894 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4895 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4896 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4897 4898 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4899 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4900 4901 /* XXX change for per-queue sizes */ 4902 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4903 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4904 4905 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4906 MAX_SINGLE_PACKET_FRACTION) 4907 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4908 MAX_SINGLE_PACKET_FRACTION); 4909 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4910 MAX_SINGLE_PACKET_FRACTION) 4911 scctx->isc_tx_tso_segments_max = max(1, 4912 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4913 4914 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4915 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4916 /* 4917 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4918 * but some MACs do. 4919 */ 4920 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4921 IP_MAXPACKET)); 4922 /* 4923 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4924 * into account. In the worst case, each of these calls will 4925 * add another mbuf and, thus, the requirement for another DMA 4926 * segment. So for best performance, it doesn't make sense to 4927 * advertize a maximum of TSO segments that typically will 4928 * require defragmentation in iflib_encap(). 4929 */ 4930 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4931 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4932 } 4933 if (scctx->isc_rss_table_size == 0) 4934 scctx->isc_rss_table_size = 64; 4935 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4936 4937 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4938 /* XXX format name */ 4939 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4940 NULL, NULL, "admin"); 4941 4942 /* XXX --- can support > 1 -- but keep it simple for now */ 4943 scctx->isc_intr = IFLIB_INTR_LEGACY; 4944 4945 /* Get memory for the station queues */ 4946 if ((err = iflib_queues_alloc(ctx))) { 4947 device_printf(dev, "Unable to allocate queue memory\n"); 4948 goto fail_iflib_detach; 4949 } 4950 4951 if ((err = iflib_qset_structures_setup(ctx))) { 4952 device_printf(dev, "qset structure setup failed %d\n", err); 4953 goto fail_queues; 4954 } 4955 4956 /* 4957 * XXX What if anything do we want to do about interrupts? 4958 */ 4959 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4960 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4961 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4962 goto fail_detach; 4963 } 4964 4965 /* 4966 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4967 * This must appear after the call to ether_ifattach() because 4968 * ether_ifattach() sets if_hdrlen to the default value. 4969 */ 4970 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4971 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4972 4973 /* XXX handle more than one queue */ 4974 for (i = 0; i < scctx->isc_nrxqsets; i++) 4975 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4976 4977 *ctxp = ctx; 4978 4979 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4980 iflib_add_device_sysctl_post(ctx); 4981 ctx->ifc_flags |= IFC_INIT_DONE; 4982 CTX_UNLOCK(ctx); 4983 4984 return (0); 4985 fail_detach: 4986 ether_ifdetach(ctx->ifc_ifp); 4987 fail_queues: 4988 iflib_tx_structures_free(ctx); 4989 iflib_rx_structures_free(ctx); 4990 fail_iflib_detach: 4991 IFDI_DETACH(ctx); 4992 fail_unlock: 4993 CTX_UNLOCK(ctx); 4994 iflib_deregister(ctx); 4995 fail_ctx_free: 4996 free(ctx->ifc_softc, M_IFLIB); 4997 free(ctx, M_IFLIB); 4998 return (err); 4999 } 5000 5001 int 5002 iflib_pseudo_deregister(if_ctx_t ctx) 5003 { 5004 if_t ifp = ctx->ifc_ifp; 5005 iflib_txq_t txq; 5006 iflib_rxq_t rxq; 5007 int i, j; 5008 struct taskqgroup *tqg; 5009 iflib_fl_t fl; 5010 5011 /* Unregister VLAN event handlers early */ 5012 iflib_unregister_vlan_handlers(ctx); 5013 5014 ether_ifdetach(ifp); 5015 /* XXX drain any dependent tasks */ 5016 tqg = qgroup_if_io_tqg; 5017 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5018 callout_drain(&txq->ift_timer); 5019 if (txq->ift_task.gt_uniq != NULL) 5020 taskqgroup_detach(tqg, &txq->ift_task); 5021 } 5022 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5023 if (rxq->ifr_task.gt_uniq != NULL) 5024 taskqgroup_detach(tqg, &rxq->ifr_task); 5025 5026 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5027 free(fl->ifl_rx_bitmap, M_IFLIB); 5028 } 5029 tqg = qgroup_if_config_tqg; 5030 if (ctx->ifc_admin_task.gt_uniq != NULL) 5031 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5032 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5033 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5034 5035 iflib_tx_structures_free(ctx); 5036 iflib_rx_structures_free(ctx); 5037 5038 iflib_deregister(ctx); 5039 5040 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5041 free(ctx->ifc_softc, M_IFLIB); 5042 free(ctx, M_IFLIB); 5043 return (0); 5044 } 5045 5046 int 5047 iflib_device_attach(device_t dev) 5048 { 5049 if_ctx_t ctx; 5050 if_shared_ctx_t sctx; 5051 5052 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5053 return (ENOTSUP); 5054 5055 pci_enable_busmaster(dev); 5056 5057 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5058 } 5059 5060 int 5061 iflib_device_deregister(if_ctx_t ctx) 5062 { 5063 if_t ifp = ctx->ifc_ifp; 5064 iflib_txq_t txq; 5065 iflib_rxq_t rxq; 5066 device_t dev = ctx->ifc_dev; 5067 int i, j; 5068 struct taskqgroup *tqg; 5069 iflib_fl_t fl; 5070 5071 /* Make sure VLANS are not using driver */ 5072 if (if_vlantrunkinuse(ifp)) { 5073 device_printf(dev, "Vlan in use, detach first\n"); 5074 return (EBUSY); 5075 } 5076 #ifdef PCI_IOV 5077 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5078 device_printf(dev, "SR-IOV in use; detach first.\n"); 5079 return (EBUSY); 5080 } 5081 #endif 5082 5083 STATE_LOCK(ctx); 5084 ctx->ifc_flags |= IFC_IN_DETACH; 5085 STATE_UNLOCK(ctx); 5086 5087 /* Unregister VLAN handlers before calling iflib_stop() */ 5088 iflib_unregister_vlan_handlers(ctx); 5089 5090 iflib_netmap_detach(ifp); 5091 ether_ifdetach(ifp); 5092 5093 CTX_LOCK(ctx); 5094 iflib_stop(ctx); 5095 CTX_UNLOCK(ctx); 5096 5097 iflib_rem_pfil(ctx); 5098 if (ctx->ifc_led_dev != NULL) 5099 led_destroy(ctx->ifc_led_dev); 5100 /* XXX drain any dependent tasks */ 5101 tqg = qgroup_if_io_tqg; 5102 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5103 callout_drain(&txq->ift_timer); 5104 if (txq->ift_task.gt_uniq != NULL) 5105 taskqgroup_detach(tqg, &txq->ift_task); 5106 } 5107 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5108 if (rxq->ifr_task.gt_uniq != NULL) 5109 taskqgroup_detach(tqg, &rxq->ifr_task); 5110 5111 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5112 free(fl->ifl_rx_bitmap, M_IFLIB); 5113 } 5114 tqg = qgroup_if_config_tqg; 5115 if (ctx->ifc_admin_task.gt_uniq != NULL) 5116 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5117 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5118 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5119 CTX_LOCK(ctx); 5120 IFDI_DETACH(ctx); 5121 CTX_UNLOCK(ctx); 5122 5123 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5124 iflib_free_intr_mem(ctx); 5125 5126 bus_generic_detach(dev); 5127 5128 iflib_tx_structures_free(ctx); 5129 iflib_rx_structures_free(ctx); 5130 5131 iflib_deregister(ctx); 5132 5133 device_set_softc(ctx->ifc_dev, NULL); 5134 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5135 free(ctx->ifc_softc, M_IFLIB); 5136 unref_ctx_core_offset(ctx); 5137 free(ctx, M_IFLIB); 5138 return (0); 5139 } 5140 5141 static void 5142 iflib_free_intr_mem(if_ctx_t ctx) 5143 { 5144 5145 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5146 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5147 } 5148 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5149 pci_release_msi(ctx->ifc_dev); 5150 } 5151 if (ctx->ifc_msix_mem != NULL) { 5152 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5153 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5154 ctx->ifc_msix_mem = NULL; 5155 } 5156 } 5157 5158 int 5159 iflib_device_detach(device_t dev) 5160 { 5161 if_ctx_t ctx = device_get_softc(dev); 5162 5163 return (iflib_device_deregister(ctx)); 5164 } 5165 5166 int 5167 iflib_device_suspend(device_t dev) 5168 { 5169 if_ctx_t ctx = device_get_softc(dev); 5170 5171 CTX_LOCK(ctx); 5172 IFDI_SUSPEND(ctx); 5173 CTX_UNLOCK(ctx); 5174 5175 return bus_generic_suspend(dev); 5176 } 5177 int 5178 iflib_device_shutdown(device_t dev) 5179 { 5180 if_ctx_t ctx = device_get_softc(dev); 5181 5182 CTX_LOCK(ctx); 5183 IFDI_SHUTDOWN(ctx); 5184 CTX_UNLOCK(ctx); 5185 5186 return bus_generic_suspend(dev); 5187 } 5188 5189 5190 int 5191 iflib_device_resume(device_t dev) 5192 { 5193 if_ctx_t ctx = device_get_softc(dev); 5194 iflib_txq_t txq = ctx->ifc_txqs; 5195 5196 CTX_LOCK(ctx); 5197 IFDI_RESUME(ctx); 5198 iflib_if_init_locked(ctx); 5199 CTX_UNLOCK(ctx); 5200 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5201 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5202 5203 return (bus_generic_resume(dev)); 5204 } 5205 5206 int 5207 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5208 { 5209 int error; 5210 if_ctx_t ctx = device_get_softc(dev); 5211 5212 CTX_LOCK(ctx); 5213 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5214 CTX_UNLOCK(ctx); 5215 5216 return (error); 5217 } 5218 5219 void 5220 iflib_device_iov_uninit(device_t dev) 5221 { 5222 if_ctx_t ctx = device_get_softc(dev); 5223 5224 CTX_LOCK(ctx); 5225 IFDI_IOV_UNINIT(ctx); 5226 CTX_UNLOCK(ctx); 5227 } 5228 5229 int 5230 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5231 { 5232 int error; 5233 if_ctx_t ctx = device_get_softc(dev); 5234 5235 CTX_LOCK(ctx); 5236 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5237 CTX_UNLOCK(ctx); 5238 5239 return (error); 5240 } 5241 5242 /********************************************************************* 5243 * 5244 * MODULE FUNCTION DEFINITIONS 5245 * 5246 **********************************************************************/ 5247 5248 /* 5249 * - Start a fast taskqueue thread for each core 5250 * - Start a taskqueue for control operations 5251 */ 5252 static int 5253 iflib_module_init(void) 5254 { 5255 return (0); 5256 } 5257 5258 static int 5259 iflib_module_event_handler(module_t mod, int what, void *arg) 5260 { 5261 int err; 5262 5263 switch (what) { 5264 case MOD_LOAD: 5265 if ((err = iflib_module_init()) != 0) 5266 return (err); 5267 break; 5268 case MOD_UNLOAD: 5269 return (EBUSY); 5270 default: 5271 return (EOPNOTSUPP); 5272 } 5273 5274 return (0); 5275 } 5276 5277 /********************************************************************* 5278 * 5279 * PUBLIC FUNCTION DEFINITIONS 5280 * ordered as in iflib.h 5281 * 5282 **********************************************************************/ 5283 5284 5285 static void 5286 _iflib_assert(if_shared_ctx_t sctx) 5287 { 5288 int i; 5289 5290 MPASS(sctx->isc_tx_maxsize); 5291 MPASS(sctx->isc_tx_maxsegsize); 5292 5293 MPASS(sctx->isc_rx_maxsize); 5294 MPASS(sctx->isc_rx_nsegments); 5295 MPASS(sctx->isc_rx_maxsegsize); 5296 5297 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5298 for (i = 0; i < sctx->isc_nrxqs; i++) { 5299 MPASS(sctx->isc_nrxd_min[i]); 5300 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5301 MPASS(sctx->isc_nrxd_max[i]); 5302 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5303 MPASS(sctx->isc_nrxd_default[i]); 5304 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5305 } 5306 5307 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5308 for (i = 0; i < sctx->isc_ntxqs; i++) { 5309 MPASS(sctx->isc_ntxd_min[i]); 5310 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5311 MPASS(sctx->isc_ntxd_max[i]); 5312 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5313 MPASS(sctx->isc_ntxd_default[i]); 5314 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5315 } 5316 } 5317 5318 static void 5319 _iflib_pre_assert(if_softc_ctx_t scctx) 5320 { 5321 5322 MPASS(scctx->isc_txrx->ift_txd_encap); 5323 MPASS(scctx->isc_txrx->ift_txd_flush); 5324 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5325 MPASS(scctx->isc_txrx->ift_rxd_available); 5326 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5327 MPASS(scctx->isc_txrx->ift_rxd_refill); 5328 MPASS(scctx->isc_txrx->ift_rxd_flush); 5329 } 5330 5331 static int 5332 iflib_register(if_ctx_t ctx) 5333 { 5334 if_shared_ctx_t sctx = ctx->ifc_sctx; 5335 driver_t *driver = sctx->isc_driver; 5336 device_t dev = ctx->ifc_dev; 5337 if_t ifp; 5338 5339 _iflib_assert(sctx); 5340 5341 CTX_LOCK_INIT(ctx); 5342 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5343 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5344 if (ifp == NULL) { 5345 device_printf(dev, "can not allocate ifnet structure\n"); 5346 return (ENOMEM); 5347 } 5348 5349 /* 5350 * Initialize our context's device specific methods 5351 */ 5352 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5353 kobj_class_compile((kobj_class_t) driver); 5354 5355 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5356 if_setsoftc(ifp, ctx); 5357 if_setdev(ifp, dev); 5358 if_setinitfn(ifp, iflib_if_init); 5359 if_setioctlfn(ifp, iflib_if_ioctl); 5360 #ifdef ALTQ 5361 if_setstartfn(ifp, iflib_altq_if_start); 5362 if_settransmitfn(ifp, iflib_altq_if_transmit); 5363 if_setsendqready(ifp); 5364 #else 5365 if_settransmitfn(ifp, iflib_if_transmit); 5366 #endif 5367 if_setqflushfn(ifp, iflib_if_qflush); 5368 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5369 5370 ctx->ifc_vlan_attach_event = 5371 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5372 EVENTHANDLER_PRI_FIRST); 5373 ctx->ifc_vlan_detach_event = 5374 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5375 EVENTHANDLER_PRI_FIRST); 5376 5377 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5378 ctx->ifc_mediap = &ctx->ifc_media; 5379 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5380 iflib_media_change, iflib_media_status); 5381 } 5382 return (0); 5383 } 5384 5385 static void 5386 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5387 { 5388 /* Unregister VLAN events */ 5389 if (ctx->ifc_vlan_attach_event != NULL) { 5390 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5391 ctx->ifc_vlan_attach_event = NULL; 5392 } 5393 if (ctx->ifc_vlan_detach_event != NULL) { 5394 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5395 ctx->ifc_vlan_detach_event = NULL; 5396 } 5397 5398 } 5399 5400 static void 5401 iflib_deregister(if_ctx_t ctx) 5402 { 5403 if_t ifp = ctx->ifc_ifp; 5404 5405 /* Remove all media */ 5406 ifmedia_removeall(&ctx->ifc_media); 5407 5408 /* Ensure that VLAN event handlers are unregistered */ 5409 iflib_unregister_vlan_handlers(ctx); 5410 5411 /* Release kobject reference */ 5412 kobj_delete((kobj_t) ctx, NULL); 5413 5414 /* Free the ifnet structure */ 5415 if_free(ifp); 5416 5417 STATE_LOCK_DESTROY(ctx); 5418 5419 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5420 CTX_LOCK_DESTROY(ctx); 5421 } 5422 5423 static int 5424 iflib_queues_alloc(if_ctx_t ctx) 5425 { 5426 if_shared_ctx_t sctx = ctx->ifc_sctx; 5427 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5428 device_t dev = ctx->ifc_dev; 5429 int nrxqsets = scctx->isc_nrxqsets; 5430 int ntxqsets = scctx->isc_ntxqsets; 5431 iflib_txq_t txq; 5432 iflib_rxq_t rxq; 5433 iflib_fl_t fl = NULL; 5434 int i, j, cpu, err, txconf, rxconf; 5435 iflib_dma_info_t ifdip; 5436 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5437 uint32_t *txqsizes = scctx->isc_txqsizes; 5438 uint8_t nrxqs = sctx->isc_nrxqs; 5439 uint8_t ntxqs = sctx->isc_ntxqs; 5440 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5441 caddr_t *vaddrs; 5442 uint64_t *paddrs; 5443 5444 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5445 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5446 5447 /* Allocate the TX ring struct memory */ 5448 if (!(ctx->ifc_txqs = 5449 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5450 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5451 device_printf(dev, "Unable to allocate TX ring memory\n"); 5452 err = ENOMEM; 5453 goto fail; 5454 } 5455 5456 /* Now allocate the RX */ 5457 if (!(ctx->ifc_rxqs = 5458 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5459 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5460 device_printf(dev, "Unable to allocate RX ring memory\n"); 5461 err = ENOMEM; 5462 goto rx_fail; 5463 } 5464 5465 txq = ctx->ifc_txqs; 5466 rxq = ctx->ifc_rxqs; 5467 5468 /* 5469 * XXX handle allocation failure 5470 */ 5471 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5472 /* Set up some basics */ 5473 5474 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5475 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5476 device_printf(dev, 5477 "Unable to allocate TX DMA info memory\n"); 5478 err = ENOMEM; 5479 goto err_tx_desc; 5480 } 5481 txq->ift_ifdi = ifdip; 5482 for (j = 0; j < ntxqs; j++, ifdip++) { 5483 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5484 device_printf(dev, 5485 "Unable to allocate TX descriptors\n"); 5486 err = ENOMEM; 5487 goto err_tx_desc; 5488 } 5489 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5490 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5491 } 5492 txq->ift_ctx = ctx; 5493 txq->ift_id = i; 5494 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5495 txq->ift_br_offset = 1; 5496 } else { 5497 txq->ift_br_offset = 0; 5498 } 5499 /* XXX fix this */ 5500 txq->ift_timer.c_cpu = cpu; 5501 5502 if (iflib_txsd_alloc(txq)) { 5503 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5504 err = ENOMEM; 5505 goto err_tx_desc; 5506 } 5507 5508 /* Initialize the TX lock */ 5509 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5510 device_get_nameunit(dev), txq->ift_id); 5511 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5512 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5513 5514 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5515 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5516 if (err) { 5517 /* XXX free any allocated rings */ 5518 device_printf(dev, "Unable to allocate buf_ring\n"); 5519 goto err_tx_desc; 5520 } 5521 } 5522 5523 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5524 /* Set up some basics */ 5525 5526 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5527 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5528 device_printf(dev, 5529 "Unable to allocate RX DMA info memory\n"); 5530 err = ENOMEM; 5531 goto err_tx_desc; 5532 } 5533 5534 rxq->ifr_ifdi = ifdip; 5535 /* XXX this needs to be changed if #rx queues != #tx queues */ 5536 rxq->ifr_ntxqirq = 1; 5537 rxq->ifr_txqid[0] = i; 5538 for (j = 0; j < nrxqs; j++, ifdip++) { 5539 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5540 device_printf(dev, 5541 "Unable to allocate RX descriptors\n"); 5542 err = ENOMEM; 5543 goto err_tx_desc; 5544 } 5545 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5546 } 5547 rxq->ifr_ctx = ctx; 5548 rxq->ifr_id = i; 5549 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5550 rxq->ifr_fl_offset = 1; 5551 } else { 5552 rxq->ifr_fl_offset = 0; 5553 } 5554 rxq->ifr_nfl = nfree_lists; 5555 if (!(fl = 5556 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5557 device_printf(dev, "Unable to allocate free list memory\n"); 5558 err = ENOMEM; 5559 goto err_tx_desc; 5560 } 5561 rxq->ifr_fl = fl; 5562 for (j = 0; j < nfree_lists; j++) { 5563 fl[j].ifl_rxq = rxq; 5564 fl[j].ifl_id = j; 5565 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5566 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5567 } 5568 /* Allocate receive buffers for the ring */ 5569 if (iflib_rxsd_alloc(rxq)) { 5570 device_printf(dev, 5571 "Critical Failure setting up receive buffers\n"); 5572 err = ENOMEM; 5573 goto err_rx_desc; 5574 } 5575 5576 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5577 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5578 M_WAITOK); 5579 } 5580 5581 /* TXQs */ 5582 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5583 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5584 for (i = 0; i < ntxqsets; i++) { 5585 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5586 5587 for (j = 0; j < ntxqs; j++, di++) { 5588 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5589 paddrs[i*ntxqs + j] = di->idi_paddr; 5590 } 5591 } 5592 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5593 device_printf(ctx->ifc_dev, 5594 "Unable to allocate device TX queue\n"); 5595 iflib_tx_structures_free(ctx); 5596 free(vaddrs, M_IFLIB); 5597 free(paddrs, M_IFLIB); 5598 goto err_rx_desc; 5599 } 5600 free(vaddrs, M_IFLIB); 5601 free(paddrs, M_IFLIB); 5602 5603 /* RXQs */ 5604 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5605 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5606 for (i = 0; i < nrxqsets; i++) { 5607 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5608 5609 for (j = 0; j < nrxqs; j++, di++) { 5610 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5611 paddrs[i*nrxqs + j] = di->idi_paddr; 5612 } 5613 } 5614 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5615 device_printf(ctx->ifc_dev, 5616 "Unable to allocate device RX queue\n"); 5617 iflib_tx_structures_free(ctx); 5618 free(vaddrs, M_IFLIB); 5619 free(paddrs, M_IFLIB); 5620 goto err_rx_desc; 5621 } 5622 free(vaddrs, M_IFLIB); 5623 free(paddrs, M_IFLIB); 5624 5625 return (0); 5626 5627 /* XXX handle allocation failure changes */ 5628 err_rx_desc: 5629 err_tx_desc: 5630 rx_fail: 5631 if (ctx->ifc_rxqs != NULL) 5632 free(ctx->ifc_rxqs, M_IFLIB); 5633 ctx->ifc_rxqs = NULL; 5634 if (ctx->ifc_txqs != NULL) 5635 free(ctx->ifc_txqs, M_IFLIB); 5636 ctx->ifc_txqs = NULL; 5637 fail: 5638 return (err); 5639 } 5640 5641 static int 5642 iflib_tx_structures_setup(if_ctx_t ctx) 5643 { 5644 iflib_txq_t txq = ctx->ifc_txqs; 5645 int i; 5646 5647 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5648 iflib_txq_setup(txq); 5649 5650 return (0); 5651 } 5652 5653 static void 5654 iflib_tx_structures_free(if_ctx_t ctx) 5655 { 5656 iflib_txq_t txq = ctx->ifc_txqs; 5657 if_shared_ctx_t sctx = ctx->ifc_sctx; 5658 int i, j; 5659 5660 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5661 iflib_txq_destroy(txq); 5662 for (j = 0; j < sctx->isc_ntxqs; j++) 5663 iflib_dma_free(&txq->ift_ifdi[j]); 5664 } 5665 free(ctx->ifc_txqs, M_IFLIB); 5666 ctx->ifc_txqs = NULL; 5667 IFDI_QUEUES_FREE(ctx); 5668 } 5669 5670 /********************************************************************* 5671 * 5672 * Initialize all receive rings. 5673 * 5674 **********************************************************************/ 5675 static int 5676 iflib_rx_structures_setup(if_ctx_t ctx) 5677 { 5678 iflib_rxq_t rxq = ctx->ifc_rxqs; 5679 int q; 5680 #if defined(INET6) || defined(INET) 5681 int err, i; 5682 #endif 5683 5684 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5685 #if defined(INET6) || defined(INET) 5686 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5687 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5688 TCP_LRO_ENTRIES, min(1024, 5689 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5690 if (err != 0) { 5691 device_printf(ctx->ifc_dev, 5692 "LRO Initialization failed!\n"); 5693 goto fail; 5694 } 5695 } 5696 #endif 5697 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5698 } 5699 return (0); 5700 #if defined(INET6) || defined(INET) 5701 fail: 5702 /* 5703 * Free LRO resources allocated so far, we will only handle 5704 * the rings that completed, the failing case will have 5705 * cleaned up for itself. 'q' failed, so its the terminus. 5706 */ 5707 rxq = ctx->ifc_rxqs; 5708 for (i = 0; i < q; ++i, rxq++) { 5709 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5710 tcp_lro_free(&rxq->ifr_lc); 5711 } 5712 return (err); 5713 #endif 5714 } 5715 5716 /********************************************************************* 5717 * 5718 * Free all receive rings. 5719 * 5720 **********************************************************************/ 5721 static void 5722 iflib_rx_structures_free(if_ctx_t ctx) 5723 { 5724 iflib_rxq_t rxq = ctx->ifc_rxqs; 5725 int i; 5726 5727 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5728 iflib_rx_sds_free(rxq); 5729 #if defined(INET6) || defined(INET) 5730 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5731 tcp_lro_free(&rxq->ifr_lc); 5732 #endif 5733 } 5734 free(ctx->ifc_rxqs, M_IFLIB); 5735 ctx->ifc_rxqs = NULL; 5736 } 5737 5738 static int 5739 iflib_qset_structures_setup(if_ctx_t ctx) 5740 { 5741 int err; 5742 5743 /* 5744 * It is expected that the caller takes care of freeing queues if this 5745 * fails. 5746 */ 5747 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5748 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5749 return (err); 5750 } 5751 5752 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5753 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5754 5755 return (err); 5756 } 5757 5758 int 5759 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5760 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5761 { 5762 5763 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5764 } 5765 5766 #ifdef SMP 5767 static int 5768 find_nth(if_ctx_t ctx, int qid) 5769 { 5770 cpuset_t cpus; 5771 int i, cpuid, eqid, count; 5772 5773 CPU_COPY(&ctx->ifc_cpus, &cpus); 5774 count = CPU_COUNT(&cpus); 5775 eqid = qid % count; 5776 /* clear up to the qid'th bit */ 5777 for (i = 0; i < eqid; i++) { 5778 cpuid = CPU_FFS(&cpus); 5779 MPASS(cpuid != 0); 5780 CPU_CLR(cpuid-1, &cpus); 5781 } 5782 cpuid = CPU_FFS(&cpus); 5783 MPASS(cpuid != 0); 5784 return (cpuid-1); 5785 } 5786 5787 #ifdef SCHED_ULE 5788 extern struct cpu_group *cpu_top; /* CPU topology */ 5789 5790 static int 5791 find_child_with_core(int cpu, struct cpu_group *grp) 5792 { 5793 int i; 5794 5795 if (grp->cg_children == 0) 5796 return -1; 5797 5798 MPASS(grp->cg_child); 5799 for (i = 0; i < grp->cg_children; i++) { 5800 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5801 return i; 5802 } 5803 5804 return -1; 5805 } 5806 5807 /* 5808 * Find the nth "close" core to the specified core 5809 * "close" is defined as the deepest level that shares 5810 * at least an L2 cache. With threads, this will be 5811 * threads on the same core. If the shared cache is L3 5812 * or higher, simply returns the same core. 5813 */ 5814 static int 5815 find_close_core(int cpu, int core_offset) 5816 { 5817 struct cpu_group *grp; 5818 int i; 5819 int fcpu; 5820 cpuset_t cs; 5821 5822 grp = cpu_top; 5823 if (grp == NULL) 5824 return cpu; 5825 i = 0; 5826 while ((i = find_child_with_core(cpu, grp)) != -1) { 5827 /* If the child only has one cpu, don't descend */ 5828 if (grp->cg_child[i].cg_count <= 1) 5829 break; 5830 grp = &grp->cg_child[i]; 5831 } 5832 5833 /* If they don't share at least an L2 cache, use the same CPU */ 5834 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5835 return cpu; 5836 5837 /* Now pick one */ 5838 CPU_COPY(&grp->cg_mask, &cs); 5839 5840 /* Add the selected CPU offset to core offset. */ 5841 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5842 if (fcpu - 1 == cpu) 5843 break; 5844 CPU_CLR(fcpu - 1, &cs); 5845 } 5846 MPASS(fcpu); 5847 5848 core_offset += i; 5849 5850 CPU_COPY(&grp->cg_mask, &cs); 5851 for (i = core_offset % grp->cg_count; i > 0; i--) { 5852 MPASS(CPU_FFS(&cs)); 5853 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5854 } 5855 MPASS(CPU_FFS(&cs)); 5856 return CPU_FFS(&cs) - 1; 5857 } 5858 #else 5859 static int 5860 find_close_core(int cpu, int core_offset __unused) 5861 { 5862 return cpu; 5863 } 5864 #endif 5865 5866 static int 5867 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5868 { 5869 switch (type) { 5870 case IFLIB_INTR_TX: 5871 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5872 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5873 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5874 case IFLIB_INTR_RX: 5875 case IFLIB_INTR_RXTX: 5876 /* RX queues get the specified core */ 5877 return qid / CPU_COUNT(&ctx->ifc_cpus); 5878 default: 5879 return -1; 5880 } 5881 } 5882 #else 5883 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5884 #define find_close_core(cpuid, tid) CPU_FIRST() 5885 #define find_nth(ctx, gid) CPU_FIRST() 5886 #endif 5887 5888 /* Just to avoid copy/paste */ 5889 static inline int 5890 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5891 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5892 const char *name) 5893 { 5894 device_t dev; 5895 int co, cpuid, err, tid; 5896 5897 dev = ctx->ifc_dev; 5898 co = ctx->ifc_sysctl_core_offset; 5899 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5900 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5901 cpuid = find_nth(ctx, qid + co); 5902 tid = get_core_offset(ctx, type, qid); 5903 if (tid < 0) { 5904 device_printf(dev, "get_core_offset failed\n"); 5905 return (EOPNOTSUPP); 5906 } 5907 cpuid = find_close_core(cpuid, tid); 5908 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5909 name); 5910 if (err) { 5911 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5912 return (err); 5913 } 5914 #ifdef notyet 5915 if (cpuid > ctx->ifc_cpuid_highest) 5916 ctx->ifc_cpuid_highest = cpuid; 5917 #endif 5918 return (0); 5919 } 5920 5921 int 5922 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5923 iflib_intr_type_t type, driver_filter_t *filter, 5924 void *filter_arg, int qid, const char *name) 5925 { 5926 device_t dev; 5927 struct grouptask *gtask; 5928 struct taskqgroup *tqg; 5929 iflib_filter_info_t info; 5930 gtask_fn_t *fn; 5931 int tqrid, err; 5932 driver_filter_t *intr_fast; 5933 void *q; 5934 5935 info = &ctx->ifc_filter_info; 5936 tqrid = rid; 5937 5938 switch (type) { 5939 /* XXX merge tx/rx for netmap? */ 5940 case IFLIB_INTR_TX: 5941 q = &ctx->ifc_txqs[qid]; 5942 info = &ctx->ifc_txqs[qid].ift_filter_info; 5943 gtask = &ctx->ifc_txqs[qid].ift_task; 5944 tqg = qgroup_if_io_tqg; 5945 fn = _task_fn_tx; 5946 intr_fast = iflib_fast_intr; 5947 GROUPTASK_INIT(gtask, 0, fn, q); 5948 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5949 break; 5950 case IFLIB_INTR_RX: 5951 q = &ctx->ifc_rxqs[qid]; 5952 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5953 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5954 tqg = qgroup_if_io_tqg; 5955 fn = _task_fn_rx; 5956 intr_fast = iflib_fast_intr; 5957 GROUPTASK_INIT(gtask, 0, fn, q); 5958 break; 5959 case IFLIB_INTR_RXTX: 5960 q = &ctx->ifc_rxqs[qid]; 5961 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5962 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5963 tqg = qgroup_if_io_tqg; 5964 fn = _task_fn_rx; 5965 intr_fast = iflib_fast_intr_rxtx; 5966 GROUPTASK_INIT(gtask, 0, fn, q); 5967 break; 5968 case IFLIB_INTR_ADMIN: 5969 q = ctx; 5970 tqrid = -1; 5971 info = &ctx->ifc_filter_info; 5972 gtask = &ctx->ifc_admin_task; 5973 tqg = qgroup_if_config_tqg; 5974 fn = _task_fn_admin; 5975 intr_fast = iflib_fast_intr_ctx; 5976 break; 5977 default: 5978 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5979 __func__); 5980 return (EINVAL); 5981 } 5982 5983 info->ifi_filter = filter; 5984 info->ifi_filter_arg = filter_arg; 5985 info->ifi_task = gtask; 5986 info->ifi_ctx = q; 5987 5988 dev = ctx->ifc_dev; 5989 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5990 if (err != 0) { 5991 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5992 return (err); 5993 } 5994 if (type == IFLIB_INTR_ADMIN) 5995 return (0); 5996 5997 if (tqrid != -1) { 5998 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5999 q, name); 6000 if (err) 6001 return (err); 6002 } else { 6003 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6004 } 6005 6006 return (0); 6007 } 6008 6009 void 6010 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6011 { 6012 struct grouptask *gtask; 6013 struct taskqgroup *tqg; 6014 gtask_fn_t *fn; 6015 void *q; 6016 int err; 6017 6018 switch (type) { 6019 case IFLIB_INTR_TX: 6020 q = &ctx->ifc_txqs[qid]; 6021 gtask = &ctx->ifc_txqs[qid].ift_task; 6022 tqg = qgroup_if_io_tqg; 6023 fn = _task_fn_tx; 6024 break; 6025 case IFLIB_INTR_RX: 6026 q = &ctx->ifc_rxqs[qid]; 6027 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6028 tqg = qgroup_if_io_tqg; 6029 fn = _task_fn_rx; 6030 break; 6031 case IFLIB_INTR_IOV: 6032 q = ctx; 6033 gtask = &ctx->ifc_vflr_task; 6034 tqg = qgroup_if_config_tqg; 6035 fn = _task_fn_iov; 6036 break; 6037 default: 6038 panic("unknown net intr type"); 6039 } 6040 GROUPTASK_INIT(gtask, 0, fn, q); 6041 if (irq != NULL) { 6042 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6043 q, name); 6044 if (err) 6045 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6046 irq->ii_res, name); 6047 } else { 6048 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6049 } 6050 } 6051 6052 void 6053 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6054 { 6055 6056 if (irq->ii_tag) 6057 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6058 6059 if (irq->ii_res) 6060 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6061 rman_get_rid(irq->ii_res), irq->ii_res); 6062 } 6063 6064 static int 6065 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6066 { 6067 iflib_txq_t txq = ctx->ifc_txqs; 6068 iflib_rxq_t rxq = ctx->ifc_rxqs; 6069 if_irq_t irq = &ctx->ifc_legacy_irq; 6070 iflib_filter_info_t info; 6071 device_t dev; 6072 struct grouptask *gtask; 6073 struct resource *res; 6074 struct taskqgroup *tqg; 6075 gtask_fn_t *fn; 6076 void *q; 6077 int err, tqrid; 6078 bool rx_only; 6079 6080 q = &ctx->ifc_rxqs[0]; 6081 info = &rxq[0].ifr_filter_info; 6082 gtask = &rxq[0].ifr_task; 6083 tqg = qgroup_if_io_tqg; 6084 tqrid = *rid; 6085 fn = _task_fn_rx; 6086 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6087 6088 ctx->ifc_flags |= IFC_LEGACY; 6089 info->ifi_filter = filter; 6090 info->ifi_filter_arg = filter_arg; 6091 info->ifi_task = gtask; 6092 info->ifi_ctx = rx_only ? ctx : q; 6093 6094 dev = ctx->ifc_dev; 6095 /* We allocate a single interrupt resource */ 6096 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6097 iflib_fast_intr_rxtx, NULL, info, name); 6098 if (err != 0) 6099 return (err); 6100 GROUPTASK_INIT(gtask, 0, fn, q); 6101 res = irq->ii_res; 6102 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6103 6104 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6105 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6106 "tx"); 6107 return (0); 6108 } 6109 6110 void 6111 iflib_led_create(if_ctx_t ctx) 6112 { 6113 6114 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6115 device_get_nameunit(ctx->ifc_dev)); 6116 } 6117 6118 void 6119 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6120 { 6121 6122 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6123 } 6124 6125 void 6126 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6127 { 6128 6129 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6130 } 6131 6132 void 6133 iflib_admin_intr_deferred(if_ctx_t ctx) 6134 { 6135 #ifdef INVARIANTS 6136 struct grouptask *gtask; 6137 6138 gtask = &ctx->ifc_admin_task; 6139 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6140 #endif 6141 6142 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6143 } 6144 6145 void 6146 iflib_iov_intr_deferred(if_ctx_t ctx) 6147 { 6148 6149 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6150 } 6151 6152 void 6153 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6154 { 6155 6156 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6157 name); 6158 } 6159 6160 void 6161 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6162 const char *name) 6163 { 6164 6165 GROUPTASK_INIT(gtask, 0, fn, ctx); 6166 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6167 name); 6168 } 6169 6170 void 6171 iflib_config_gtask_deinit(struct grouptask *gtask) 6172 { 6173 6174 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6175 } 6176 6177 void 6178 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6179 { 6180 if_t ifp = ctx->ifc_ifp; 6181 iflib_txq_t txq = ctx->ifc_txqs; 6182 6183 if_setbaudrate(ifp, baudrate); 6184 if (baudrate >= IF_Gbps(10)) { 6185 STATE_LOCK(ctx); 6186 ctx->ifc_flags |= IFC_PREFETCH; 6187 STATE_UNLOCK(ctx); 6188 } 6189 /* If link down, disable watchdog */ 6190 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6191 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6192 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6193 } 6194 ctx->ifc_link_state = link_state; 6195 if_link_state_change(ifp, link_state); 6196 } 6197 6198 static int 6199 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6200 { 6201 int credits; 6202 #ifdef INVARIANTS 6203 int credits_pre = txq->ift_cidx_processed; 6204 #endif 6205 6206 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6207 BUS_DMASYNC_POSTREAD); 6208 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6209 return (0); 6210 6211 txq->ift_processed += credits; 6212 txq->ift_cidx_processed += credits; 6213 6214 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6215 if (txq->ift_cidx_processed >= txq->ift_size) 6216 txq->ift_cidx_processed -= txq->ift_size; 6217 return (credits); 6218 } 6219 6220 static int 6221 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6222 { 6223 iflib_fl_t fl; 6224 u_int i; 6225 6226 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6227 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6228 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6229 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6230 budget)); 6231 } 6232 6233 void 6234 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6235 const char *description, if_int_delay_info_t info, 6236 int offset, int value) 6237 { 6238 info->iidi_ctx = ctx; 6239 info->iidi_offset = offset; 6240 info->iidi_value = value; 6241 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6242 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6243 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6244 info, 0, iflib_sysctl_int_delay, "I", description); 6245 } 6246 6247 struct sx * 6248 iflib_ctx_lock_get(if_ctx_t ctx) 6249 { 6250 6251 return (&ctx->ifc_ctx_sx); 6252 } 6253 6254 static int 6255 iflib_msix_init(if_ctx_t ctx) 6256 { 6257 device_t dev = ctx->ifc_dev; 6258 if_shared_ctx_t sctx = ctx->ifc_sctx; 6259 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6260 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6261 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6262 6263 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6264 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6265 6266 if (bootverbose) 6267 device_printf(dev, "msix_init qsets capped at %d\n", 6268 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6269 6270 /* Override by tuneable */ 6271 if (scctx->isc_disable_msix) 6272 goto msi; 6273 6274 /* First try MSI-X */ 6275 if ((msgs = pci_msix_count(dev)) == 0) { 6276 if (bootverbose) 6277 device_printf(dev, "MSI-X not supported or disabled\n"); 6278 goto msi; 6279 } 6280 6281 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6282 /* 6283 * bar == -1 => "trust me I know what I'm doing" 6284 * Some drivers are for hardware that is so shoddily 6285 * documented that no one knows which bars are which 6286 * so the developer has to map all bars. This hack 6287 * allows shoddy garbage to use MSI-X in this framework. 6288 */ 6289 if (bar != -1) { 6290 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6291 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6292 if (ctx->ifc_msix_mem == NULL) { 6293 device_printf(dev, "Unable to map MSI-X table\n"); 6294 goto msi; 6295 } 6296 } 6297 6298 admincnt = sctx->isc_admin_intrcnt; 6299 #if IFLIB_DEBUG 6300 /* use only 1 qset in debug mode */ 6301 queuemsgs = min(msgs - admincnt, 1); 6302 #else 6303 queuemsgs = msgs - admincnt; 6304 #endif 6305 #ifdef RSS 6306 queues = imin(queuemsgs, rss_getnumbuckets()); 6307 #else 6308 queues = queuemsgs; 6309 #endif 6310 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6311 if (bootverbose) 6312 device_printf(dev, 6313 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6314 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6315 #ifdef RSS 6316 /* If we're doing RSS, clamp at the number of RSS buckets */ 6317 if (queues > rss_getnumbuckets()) 6318 queues = rss_getnumbuckets(); 6319 #endif 6320 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6321 rx_queues = iflib_num_rx_queues; 6322 else 6323 rx_queues = queues; 6324 6325 if (rx_queues > scctx->isc_nrxqsets) 6326 rx_queues = scctx->isc_nrxqsets; 6327 6328 /* 6329 * We want this to be all logical CPUs by default 6330 */ 6331 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6332 tx_queues = iflib_num_tx_queues; 6333 else 6334 tx_queues = mp_ncpus; 6335 6336 if (tx_queues > scctx->isc_ntxqsets) 6337 tx_queues = scctx->isc_ntxqsets; 6338 6339 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6340 #ifdef INVARIANTS 6341 if (tx_queues != rx_queues) 6342 device_printf(dev, 6343 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6344 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6345 #endif 6346 tx_queues = min(rx_queues, tx_queues); 6347 rx_queues = min(rx_queues, tx_queues); 6348 } 6349 6350 vectors = rx_queues + admincnt; 6351 if (msgs < vectors) { 6352 device_printf(dev, 6353 "insufficient number of MSI-X vectors " 6354 "(supported %d, need %d)\n", msgs, vectors); 6355 goto msi; 6356 } 6357 6358 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6359 tx_queues); 6360 msgs = vectors; 6361 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6362 if (vectors != msgs) { 6363 device_printf(dev, 6364 "Unable to allocate sufficient MSI-X vectors " 6365 "(got %d, need %d)\n", vectors, msgs); 6366 pci_release_msi(dev); 6367 if (bar != -1) { 6368 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6369 ctx->ifc_msix_mem); 6370 ctx->ifc_msix_mem = NULL; 6371 } 6372 goto msi; 6373 } 6374 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6375 vectors); 6376 scctx->isc_vectors = vectors; 6377 scctx->isc_nrxqsets = rx_queues; 6378 scctx->isc_ntxqsets = tx_queues; 6379 scctx->isc_intr = IFLIB_INTR_MSIX; 6380 6381 return (vectors); 6382 } else { 6383 device_printf(dev, 6384 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6385 err); 6386 if (bar != -1) { 6387 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6388 ctx->ifc_msix_mem); 6389 ctx->ifc_msix_mem = NULL; 6390 } 6391 } 6392 6393 msi: 6394 vectors = pci_msi_count(dev); 6395 scctx->isc_nrxqsets = 1; 6396 scctx->isc_ntxqsets = 1; 6397 scctx->isc_vectors = vectors; 6398 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6399 device_printf(dev,"Using an MSI interrupt\n"); 6400 scctx->isc_intr = IFLIB_INTR_MSI; 6401 } else { 6402 scctx->isc_vectors = 1; 6403 device_printf(dev,"Using a Legacy interrupt\n"); 6404 scctx->isc_intr = IFLIB_INTR_LEGACY; 6405 } 6406 6407 return (vectors); 6408 } 6409 6410 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6411 6412 static int 6413 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6414 { 6415 int rc; 6416 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6417 struct sbuf *sb; 6418 const char *ring_state = "UNKNOWN"; 6419 6420 /* XXX needed ? */ 6421 rc = sysctl_wire_old_buffer(req, 0); 6422 MPASS(rc == 0); 6423 if (rc != 0) 6424 return (rc); 6425 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6426 MPASS(sb != NULL); 6427 if (sb == NULL) 6428 return (ENOMEM); 6429 if (state[3] <= 3) 6430 ring_state = ring_states[state[3]]; 6431 6432 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6433 state[0], state[1], state[2], ring_state); 6434 rc = sbuf_finish(sb); 6435 sbuf_delete(sb); 6436 return(rc); 6437 } 6438 6439 enum iflib_ndesc_handler { 6440 IFLIB_NTXD_HANDLER, 6441 IFLIB_NRXD_HANDLER, 6442 }; 6443 6444 static int 6445 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6446 { 6447 if_ctx_t ctx = (void *)arg1; 6448 enum iflib_ndesc_handler type = arg2; 6449 char buf[256] = {0}; 6450 qidx_t *ndesc; 6451 char *p, *next; 6452 int nqs, rc, i; 6453 6454 nqs = 8; 6455 switch(type) { 6456 case IFLIB_NTXD_HANDLER: 6457 ndesc = ctx->ifc_sysctl_ntxds; 6458 if (ctx->ifc_sctx) 6459 nqs = ctx->ifc_sctx->isc_ntxqs; 6460 break; 6461 case IFLIB_NRXD_HANDLER: 6462 ndesc = ctx->ifc_sysctl_nrxds; 6463 if (ctx->ifc_sctx) 6464 nqs = ctx->ifc_sctx->isc_nrxqs; 6465 break; 6466 default: 6467 printf("%s: unhandled type\n", __func__); 6468 return (EINVAL); 6469 } 6470 if (nqs == 0) 6471 nqs = 8; 6472 6473 for (i=0; i<8; i++) { 6474 if (i >= nqs) 6475 break; 6476 if (i) 6477 strcat(buf, ","); 6478 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6479 } 6480 6481 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6482 if (rc || req->newptr == NULL) 6483 return rc; 6484 6485 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6486 i++, p = strsep(&next, " ,")) { 6487 ndesc[i] = strtoul(p, NULL, 10); 6488 } 6489 6490 return(rc); 6491 } 6492 6493 #define NAME_BUFLEN 32 6494 static void 6495 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6496 { 6497 device_t dev = iflib_get_dev(ctx); 6498 struct sysctl_oid_list *child, *oid_list; 6499 struct sysctl_ctx_list *ctx_list; 6500 struct sysctl_oid *node; 6501 6502 ctx_list = device_get_sysctl_ctx(dev); 6503 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6504 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6505 CTLFLAG_RD, NULL, "IFLIB fields"); 6506 oid_list = SYSCTL_CHILDREN(node); 6507 6508 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6509 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6510 "driver version"); 6511 6512 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6513 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6514 "# of txqs to use, 0 => use default #"); 6515 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6516 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6517 "# of rxqs to use, 0 => use default #"); 6518 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6519 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6520 "permit #txq != #rxq"); 6521 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6522 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6523 "disable MSI-X (default 0)"); 6524 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6525 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6526 "set the RX budget"); 6527 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6528 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6529 "cause TX to abdicate instead of running to completion"); 6530 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6531 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6532 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6533 "offset to start using cores at"); 6534 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6535 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6536 "use separate cores for TX and RX"); 6537 6538 /* XXX change for per-queue sizes */ 6539 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6540 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6541 mp_ndesc_handler, "A", 6542 "list of # of TX descriptors to use, 0 = use default #"); 6543 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6544 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6545 mp_ndesc_handler, "A", 6546 "list of # of RX descriptors to use, 0 = use default #"); 6547 } 6548 6549 static void 6550 iflib_add_device_sysctl_post(if_ctx_t ctx) 6551 { 6552 if_shared_ctx_t sctx = ctx->ifc_sctx; 6553 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6554 device_t dev = iflib_get_dev(ctx); 6555 struct sysctl_oid_list *child; 6556 struct sysctl_ctx_list *ctx_list; 6557 iflib_fl_t fl; 6558 iflib_txq_t txq; 6559 iflib_rxq_t rxq; 6560 int i, j; 6561 char namebuf[NAME_BUFLEN]; 6562 char *qfmt; 6563 struct sysctl_oid *queue_node, *fl_node, *node; 6564 struct sysctl_oid_list *queue_list, *fl_list; 6565 ctx_list = device_get_sysctl_ctx(dev); 6566 6567 node = ctx->ifc_sysctl_node; 6568 child = SYSCTL_CHILDREN(node); 6569 6570 if (scctx->isc_ntxqsets > 100) 6571 qfmt = "txq%03d"; 6572 else if (scctx->isc_ntxqsets > 10) 6573 qfmt = "txq%02d"; 6574 else 6575 qfmt = "txq%d"; 6576 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6577 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6578 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6579 CTLFLAG_RD, NULL, "Queue Name"); 6580 queue_list = SYSCTL_CHILDREN(queue_node); 6581 #if MEMORY_LOGGING 6582 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6583 CTLFLAG_RD, 6584 &txq->ift_dequeued, "total mbufs freed"); 6585 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6586 CTLFLAG_RD, 6587 &txq->ift_enqueued, "total mbufs enqueued"); 6588 #endif 6589 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6590 CTLFLAG_RD, 6591 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6592 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6593 CTLFLAG_RD, 6594 &txq->ift_pullups, "# of times m_pullup was called"); 6595 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6596 CTLFLAG_RD, 6597 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6598 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6599 CTLFLAG_RD, 6600 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6601 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6602 CTLFLAG_RD, 6603 &txq->ift_map_failed, "# of times DMA map failed"); 6604 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6605 CTLFLAG_RD, 6606 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6607 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6608 CTLFLAG_RD, 6609 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6610 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6611 CTLFLAG_RD, 6612 &txq->ift_pidx, 1, "Producer Index"); 6613 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6614 CTLFLAG_RD, 6615 &txq->ift_cidx, 1, "Consumer Index"); 6616 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6617 CTLFLAG_RD, 6618 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6619 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6620 CTLFLAG_RD, 6621 &txq->ift_in_use, 1, "descriptors in use"); 6622 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6623 CTLFLAG_RD, 6624 &txq->ift_processed, "descriptors procesed for clean"); 6625 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6626 CTLFLAG_RD, 6627 &txq->ift_cleaned, "total cleaned"); 6628 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6629 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6630 0, mp_ring_state_handler, "A", "soft ring state"); 6631 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6632 CTLFLAG_RD, &txq->ift_br->enqueues, 6633 "# of enqueues to the mp_ring for this queue"); 6634 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6635 CTLFLAG_RD, &txq->ift_br->drops, 6636 "# of drops in the mp_ring for this queue"); 6637 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6638 CTLFLAG_RD, &txq->ift_br->starts, 6639 "# of normal consumer starts in the mp_ring for this queue"); 6640 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6641 CTLFLAG_RD, &txq->ift_br->stalls, 6642 "# of consumer stalls in the mp_ring for this queue"); 6643 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6644 CTLFLAG_RD, &txq->ift_br->restarts, 6645 "# of consumer restarts in the mp_ring for this queue"); 6646 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6647 CTLFLAG_RD, &txq->ift_br->abdications, 6648 "# of consumer abdications in the mp_ring for this queue"); 6649 } 6650 6651 if (scctx->isc_nrxqsets > 100) 6652 qfmt = "rxq%03d"; 6653 else if (scctx->isc_nrxqsets > 10) 6654 qfmt = "rxq%02d"; 6655 else 6656 qfmt = "rxq%d"; 6657 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6658 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6659 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6660 CTLFLAG_RD, NULL, "Queue Name"); 6661 queue_list = SYSCTL_CHILDREN(queue_node); 6662 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6663 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6664 CTLFLAG_RD, 6665 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6666 } 6667 6668 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6669 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6670 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6671 CTLFLAG_RD, NULL, "freelist Name"); 6672 fl_list = SYSCTL_CHILDREN(fl_node); 6673 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6674 CTLFLAG_RD, 6675 &fl->ifl_pidx, 1, "Producer Index"); 6676 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6677 CTLFLAG_RD, 6678 &fl->ifl_cidx, 1, "Consumer Index"); 6679 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6680 CTLFLAG_RD, 6681 &fl->ifl_credits, 1, "credits available"); 6682 #if MEMORY_LOGGING 6683 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6684 CTLFLAG_RD, 6685 &fl->ifl_m_enqueued, "mbufs allocated"); 6686 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6687 CTLFLAG_RD, 6688 &fl->ifl_m_dequeued, "mbufs freed"); 6689 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6690 CTLFLAG_RD, 6691 &fl->ifl_cl_enqueued, "clusters allocated"); 6692 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6693 CTLFLAG_RD, 6694 &fl->ifl_cl_dequeued, "clusters freed"); 6695 #endif 6696 6697 } 6698 } 6699 6700 } 6701 6702 void 6703 iflib_request_reset(if_ctx_t ctx) 6704 { 6705 6706 STATE_LOCK(ctx); 6707 ctx->ifc_flags |= IFC_DO_RESET; 6708 STATE_UNLOCK(ctx); 6709 } 6710 6711 #ifndef __NO_STRICT_ALIGNMENT 6712 static struct mbuf * 6713 iflib_fixup_rx(struct mbuf *m) 6714 { 6715 struct mbuf *n; 6716 6717 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6718 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6719 m->m_data += ETHER_HDR_LEN; 6720 n = m; 6721 } else { 6722 MGETHDR(n, M_NOWAIT, MT_DATA); 6723 if (n == NULL) { 6724 m_freem(m); 6725 return (NULL); 6726 } 6727 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6728 m->m_data += ETHER_HDR_LEN; 6729 m->m_len -= ETHER_HDR_LEN; 6730 n->m_len = ETHER_HDR_LEN; 6731 M_MOVE_PKTHDR(n, m); 6732 n->m_next = m; 6733 } 6734 return (n); 6735 } 6736 #endif 6737 6738 #ifdef DEBUGNET 6739 static void 6740 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6741 { 6742 if_ctx_t ctx; 6743 6744 ctx = if_getsoftc(ifp); 6745 CTX_LOCK(ctx); 6746 *nrxr = NRXQSETS(ctx); 6747 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6748 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6749 CTX_UNLOCK(ctx); 6750 } 6751 6752 static void 6753 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6754 { 6755 if_ctx_t ctx; 6756 if_softc_ctx_t scctx; 6757 iflib_fl_t fl; 6758 iflib_rxq_t rxq; 6759 int i, j; 6760 6761 ctx = if_getsoftc(ifp); 6762 scctx = &ctx->ifc_softc_ctx; 6763 6764 switch (event) { 6765 case DEBUGNET_START: 6766 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6767 rxq = &ctx->ifc_rxqs[i]; 6768 for (j = 0; j < rxq->ifr_nfl; j++) { 6769 fl = rxq->ifr_fl; 6770 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6771 } 6772 } 6773 iflib_no_tx_batch = 1; 6774 break; 6775 default: 6776 break; 6777 } 6778 } 6779 6780 static int 6781 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6782 { 6783 if_ctx_t ctx; 6784 iflib_txq_t txq; 6785 int error; 6786 6787 ctx = if_getsoftc(ifp); 6788 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6789 IFF_DRV_RUNNING) 6790 return (EBUSY); 6791 6792 txq = &ctx->ifc_txqs[0]; 6793 error = iflib_encap(txq, &m); 6794 if (error == 0) 6795 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6796 return (error); 6797 } 6798 6799 static int 6800 iflib_debugnet_poll(if_t ifp, int count) 6801 { 6802 if_ctx_t ctx; 6803 if_softc_ctx_t scctx; 6804 iflib_txq_t txq; 6805 int i; 6806 6807 ctx = if_getsoftc(ifp); 6808 scctx = &ctx->ifc_softc_ctx; 6809 6810 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6811 IFF_DRV_RUNNING) 6812 return (EBUSY); 6813 6814 txq = &ctx->ifc_txqs[0]; 6815 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6816 6817 for (i = 0; i < scctx->isc_nrxqsets; i++) 6818 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6819 return (0); 6820 } 6821 #endif /* DEBUGNET */ 6822